diff --git a/examples/aggregate/Makefile b/examples/aggregate/Makefile new file mode 100644 index 0000000..58e3f11 --- /dev/null +++ b/examples/aggregate/Makefile @@ -0,0 +1,13 @@ +SPIN_APP_NAME = aggregate_global +SPIN_APP_SRCS = aggregate_global.c +SPIN_CFLAGS = -O3 -g +SPIN_LDFLAGS = -lm +NUM_PACKETS ?=512 +HAS_HH=0 +HAS_TH=1 +FULL_PKT=1 +PKT_SIZE ?= 1024 +PKT_DELAY=0 + +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/aggregate/handlers/aggregate_global.c b/examples/aggregate/handlers/aggregate_global.c new file mode 100644 index 0000000..0324ee1 --- /dev/null +++ b/examples/aggregate/handlers/aggregate_global.c @@ -0,0 +1,69 @@ +#ifndef HOST +#include +#else +#include +#endif + +#include + +#define MAX_CLUSTERS 4 +#define MAX_HPUS 32 +#define STRIDE 1 +#define OFFSET 0 +#define NUM_INT_OP 0 + +//#define USE_AMO + +// Handler that implements data race free aggregation for int32 +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0xde, 0xad, 0xbe, 0xef}; + +__handler__ void aggregate_global_hh(handler_args_t *args) +{ +} +__handler__ void aggregate_global_ph(handler_args_t *args) +{ + + task_t* task = args->task; + uint32_t *scratchpad = (uint32_t *)task->scratchpad; + + uint8_t *pkt_pld_ptr; + uint32_t pkt_pld_len; + GET_IP_UDP_PLD(task->pkt_mem, pkt_pld_ptr, pkt_pld_len); + + uint32_t *nic_pld_addr = (uint32_t*) pkt_pld_ptr; + + uint32_t aggregator=0; + for(uint32_t i=0;icluster_id; + amo_add(&(scratchpad[my_cluster_id]), aggregator); +} + +__handler__ void aggregate_global_th(handler_args_t *args) +{ + task_t* task = args->task; + uint32_t *scratchpad=(uint32_t*) task->scratchpad; + uint32_t result=0; + for(uint8_t i=0;ihost_mem_high; + host_address = (host_address << 32) | (task->host_mem_low); + + spin_host_write(host_address, (uint64_t) result, false); +} + + +void init_handlers(handler_fn * hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {aggregate_global_hh, aggregate_global_ph, aggregate_global_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void*) handler_mem; +} diff --git a/examples/copy_from_host/Makefile b/examples/copy_from_host/Makefile new file mode 100644 index 0000000..a2f33c3 --- /dev/null +++ b/examples/copy_from_host/Makefile @@ -0,0 +1,13 @@ +SPIN_APP_NAME = copy_from_host +SPIN_APP_SRCS = copy_from_host.c +SPIN_CFLAGS = -O3 -g -flto +SPIN_LDFLAGS = -lm +NUM_PACKETS ?= 512 +PKT_DELAY ?= 0 +MSG_DELAY ?= 0 +HAS_HH ?= 0 +HAS_TH ?= 0 +FULL_PKT ?= 1 + +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/copy_from_host/handlers/copy_from_host.c b/examples/copy_from_host/handlers/copy_from_host.c new file mode 100644 index 0000000..82d1668 --- /dev/null +++ b/examples/copy_from_host/handlers/copy_from_host.c @@ -0,0 +1,58 @@ +#ifndef HOST +#include +#include +#include +#else +#include +#endif + +#if !defined(TO_L2) && !defined(TO_L1) +#define TO_L1 +#endif + +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0xde, 0xad, 0xbe, 0xef}; + + +__handler__ void copy_from_host_hh(handler_args_t *args) {;} +__handler__ void copy_from_host_ph(handler_args_t *args) +{ + task_t* task = args->task; + ip_hdr_t *ip_hdr = (ip_hdr_t*) (task->pkt_mem); +#ifndef TO_L1 + uint8_t *nic_pld_addr = ((uint8_t*) (task->l2_pkt_mem)); +#else + uint8_t *nic_pld_addr = ((uint8_t*) (task->pkt_mem)); +#endif + uint16_t pkt_pld_len = ip_hdr->length; + udp_hdr_t *udp_hdr = (udp_hdr_t*) (((uint8_t*) (task->pkt_mem)) + ip_hdr->ihl * 4); + + uint32_t src_id = ip_hdr->source_id; + ip_hdr->source_id = ip_hdr->dest_id; + ip_hdr->dest_id = src_id; + + uint16_t src_port = udp_hdr->src_port; + udp_hdr->src_port = udp_hdr->dst_port; + udp_hdr->dst_port = src_port; + + spin_cmd_t dma; + + uint64_t host_address = task->host_mem_high; + host_address = (host_address << 32) | (task->host_mem_low); + spin_dma_from_host(host_address, (uint32_t) nic_pld_addr, pkt_pld_len, 1, &dma); + + spin_cmd_wait(dma); + + spin_cmd_t send; + spin_send_packet(nic_pld_addr, pkt_pld_len, &send); +} +__handler__ void copy_from_host_th(handler_args_t *args){;} + +void init_handlers(handler_fn * hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {copy_from_host_hh, copy_from_host_ph, copy_from_host_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void*) handler_mem; +} diff --git a/examples/copy_to_host/Makefile b/examples/copy_to_host/Makefile new file mode 100644 index 0000000..8a59803 --- /dev/null +++ b/examples/copy_to_host/Makefile @@ -0,0 +1,13 @@ +SPIN_APP_NAME = copy_to_host +SPIN_APP_SRCS = copy_to_host.c +SPIN_CFLAGS = -O3 -g -flto +SPIN_LDFLAGS = -lm +NUM_PACKETS ?= 512 +PKT_DELAY ?= 0 +MSG_DELAY ?= 0 +HAS_HH ?= 0 +HAS_TH ?= 0 +FULL_PKT ?= 1 + +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/copy_to_host/handlers/copy_to_host.c b/examples/copy_to_host/handlers/copy_to_host.c new file mode 100644 index 0000000..b357e16 --- /dev/null +++ b/examples/copy_to_host/handlers/copy_to_host.c @@ -0,0 +1,56 @@ +#ifndef HOST +#include +#include +#include +#else +#include +#endif + +#if !defined(FROM_L2) && !defined(FROM_L1) +#define FROM_L1 +#endif + +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0xde, 0xad, 0xbe, 0xef}; + + +__handler__ void copy_to_host_hh(handler_args_t *args) {;} +__handler__ void copy_to_host_ph(handler_args_t *args) +{ + task_t* task = args->task; + ip_hdr_t *ip_hdr = (ip_hdr_t*) (task->pkt_mem); +#ifdef FROM_L2 + uint8_t *nic_pld_addr = ((uint8_t*) (task->l2_pkt_mem)); +#else + uint8_t *nic_pld_addr = ((uint8_t*) (task->pkt_mem)); +#endif + uint16_t pkt_pld_len = ip_hdr->length; + + spin_cmd_t dma; + + uint64_t host_address = task->host_mem_high; + host_address = (host_address << 32) | (task->host_mem_low); + spin_dma_to_host(host_address, (uint32_t) nic_pld_addr, pkt_pld_len, 1, &dma); + + //It's not strictly necessary to wait. The hw will enforce that the feedback is not + //sent until all commands issued by this handlers are completed. +#ifdef WAIT_POLL + bool completed = false; + do { + spin_cmd_test(dma, &completed); + } while (!completed); +#elif defined(WAIT_SUSPEND) + spin_cmd_wait(dma); +#endif + +} +__handler__ void copy_to_host_th(handler_args_t *args){;} + +void init_handlers(handler_fn * hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {copy_to_host_hh, copy_to_host_ph, copy_to_host_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void*) handler_mem; +} diff --git a/examples/empty/Makefile b/examples/empty/Makefile new file mode 100644 index 0000000..3967fe1 --- /dev/null +++ b/examples/empty/Makefile @@ -0,0 +1,11 @@ +SPIN_APP_NAME = empty +SPIN_APP_SRCS = empty.c +SPIN_CFLAGS = -O3 -g ${DEFINITIONS} +SPIN_LDFLAGS = -lm -flto +NUM_PACKETS ?= 512 +PKT_DELAY ?= 0 +MSG_DELAY ?= 0 + + +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/empty/handlers/empty.c b/examples/empty/handlers/empty.c new file mode 100644 index 0000000..ecc40f6 --- /dev/null +++ b/examples/empty/handlers/empty.c @@ -0,0 +1,40 @@ + +#ifndef HOST +#include +#include +#include +#else +#include +#endif + +#ifndef NUM_INT_OP +#define NUM_INT_OP 0 +#endif + +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0xde, 0xad, 0xbe, 0xef}; + +__handler__ void empty_hh(handler_args_t *args) {;} +__handler__ void empty_ph(handler_args_t *args) +{ + //printf("Payload handler!\n"); +#if (NUM_INT_OP > 0) + volatile int xx = 0; + int x = xx; + for (int i=0; i +#else +#include +#endif + +#include +#include + +#define MAX_HPUS_IN_CLUSTER 4 +#define STRIDE 1 +#define OFFSET 0 +#define NUM_INT_OP 0 +// Handler that implements reduce in scratchpad for int32 +#include "hash_maker/f_d.h" + +#define KEY_SIZE 8 + +//number of 32-bit words fitting in 1 MiB +#define TOT_WORDS 262144 + +#define HASH_JEN_MIX(a,b,c) \ +do { \ + a -= b; a -= c; a ^= ( c >> 13 ); \ + b -= c; b -= a; b ^= ( a << 8 ); \ + c -= a; c -= b; c ^= ( b >> 13 ); \ + a -= b; a -= c; a ^= ( c >> 12 ); \ + b -= c; b -= a; b ^= ( a << 16 ); \ + c -= a; c -= b; c ^= ( b >> 5 ); \ + a -= b; a -= c; a ^= ( c >> 3 ); \ + b -= c; b -= a; b ^= ( a << 10 ); \ + c -= a; c -= b; c ^= ( b >> 15 ); \ +} while (0) + +#define HASH_JEN(key,keylen,hashv) \ +do { \ + unsigned _hj_i,_hj_j,_hj_k; \ + unsigned const char *_hj_key=(unsigned const char*)(key); \ + hashv = 0xfeedbeefu; \ + _hj_i = _hj_j = 0x9e3779b9u; \ + _hj_k = (unsigned)(keylen); \ + while (_hj_k >= 12U) { \ + _hj_i += (_hj_key[0] + ( (unsigned)_hj_key[1] << 8 ) \ + + ( (unsigned)_hj_key[2] << 16 ) \ + + ( (unsigned)_hj_key[3] << 24 ) ); \ + _hj_j += (_hj_key[4] + ( (unsigned)_hj_key[5] << 8 ) \ + + ( (unsigned)_hj_key[6] << 16 ) \ + + ( (unsigned)_hj_key[7] << 24 ) ); \ + hashv += (_hj_key[8] + ( (unsigned)_hj_key[9] << 8 ) \ + + ( (unsigned)_hj_key[10] << 16 ) \ + + ( (unsigned)_hj_key[11] << 24 ) ); \ + \ + HASH_JEN_MIX(_hj_i, _hj_j, hashv); \ + \ + _hj_key += 12; \ + _hj_k -= 12U; \ + } \ + hashv += (unsigned)(keylen); \ + switch ( _hj_k ) { \ + case 11: hashv += ( (unsigned)_hj_key[10] << 24 ); /* FALLTHROUGH */ \ + case 10: hashv += ( (unsigned)_hj_key[9] << 16 ); /* FALLTHROUGH */ \ + case 9: hashv += ( (unsigned)_hj_key[8] << 8 ); /* FALLTHROUGH */ \ + case 8: _hj_j += ( (unsigned)_hj_key[7] << 24 ); /* FALLTHROUGH */ \ + case 7: _hj_j += ( (unsigned)_hj_key[6] << 16 ); /* FALLTHROUGH */ \ + case 6: _hj_j += ( (unsigned)_hj_key[5] << 8 ); /* FALLTHROUGH */ \ + case 5: _hj_j += _hj_key[4]; /* FALLTHROUGH */ \ + case 4: _hj_i += ( (unsigned)_hj_key[3] << 24 ); /* FALLTHROUGH */ \ + case 3: _hj_i += ( (unsigned)_hj_key[2] << 16 ); /* FALLTHROUGH */ \ + case 2: _hj_i += ( (unsigned)_hj_key[1] << 8 ); /* FALLTHROUGH */ \ + case 1: _hj_i += _hj_key[0]; \ + } \ + HASH_JEN_MIX(_hj_i, _hj_j, hashv); \ +} while (0) + +__handler__ void filtering_hh(handler_args_t *args) +{ + +} +__handler__ void filtering_ph(handler_args_t *args) +{ + task_t* task = args->task; + + ip_hdr_t *ip_hdr = (ip_hdr_t*) (task->pkt_mem); + uint32_t *mem = (uint32_t *) task->handler_mem; + uint8_t *key_byte = (uint8_t*) task->pkt_mem; + + uint32_t hash; + HASH_JEN(key_byte, KEY_SIZE, hash); + hash = FAST_MOD(hash, TOT_WORDS); + + *((uint32_t *) task->l2_pkt_mem) = mem[hash]; + + spin_cmd_t cpy; + uint64_t host_address = task->host_mem_high; + host_address = (host_address << 32) | (task->host_mem_low); + spin_dma_to_host(host_address, task->l2_pkt_mem, task->pkt_mem_size, 0, &cpy); + +} +__handler__ void filtering_th(handler_args_t *args) +{ +} + +void init_handlers(handler_fn *hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {filtering_hh, filtering_ph, filtering_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void *)handler_mem; +} diff --git a/examples/hashtable_fun/Makefile b/examples/hashtable_fun/Makefile new file mode 100644 index 0000000..ce237cb --- /dev/null +++ b/examples/hashtable_fun/Makefile @@ -0,0 +1,17 @@ +SPIN_APP_NAME = htable +SPIN_APP_SRCS = htable_handlers.c +SPIN_CFLAGS = -O3 -g ${DEFINITIONS} +SPIN_LDFLAGS = -lm -flto +NUM_PACKETS ?= 4 +PKT_DELAY ?= 0 +MSG_DELAY ?= 0 + + +include $(PSPIN_RT)/spin-handlers.mk + +all:: + make deploy + make driver + +driver: htable_driver.c + gcc -std=c99 -I$(PSPIN_RT)/include/ -I$(PSPIN_HW)/verilator_model/include htable_driver.c -L$(PSPIN_HW)/verilator_model/lib/ -lpspin_debug -o htable_driver diff --git a/examples/hashtable_fun/driver/htable_driver.c b/examples/hashtable_fun/driver/htable_driver.c new file mode 100644 index 0000000..6c563ed --- /dev/null +++ b/examples/hashtable_fun/driver/htable_driver.c @@ -0,0 +1,94 @@ +#include "pspinsim.h" +#include "spin.h" + +#include +#include +#include + +#define NUM_FUNCTIONS 3 + +#define CHECK_ERR(S) {int res; if ((res=S)!=SPIN_SUCCESS) return res;} + +#define NUM_PACKETS 32 +#define PKT_SIZE 64 + +/* This is the handler data memory */ +#define NIC_L2_ADDR 0x1c300000 + +#define HANDLERS_FILE "build/htable" + +/*** Test function that injects some (empty) packets ***/ +int send_packets() +{ + uint8_t pkt_buffer[PKT_SIZE]; + + // find address of the payload handler + spin_nic_addr_t ph_addr; + size_t ph_size; + CHECK_ERR(spin_find_handler_by_name(HANDLERS_FILE, "htable_ph", &ph_addr, &ph_size)); + + /* 1st thing to do: prepare execution context */ + spin_ec_t ec; + ec.handler_mem_addr = (uint32_t) NIC_L2_ADDR; + ec.handler_mem_size = 0x100000; + ec.host_mem_addr = (uint64_t) 0xdeadbeefdeadbeef; + ec.host_mem_size = 0; + ec.hh_addr = 0; //hh_addr; + ec.ph_addr = ph_addr; + ec.th_addr = 0; //th_addr; + ec.hh_size = 0; + ec.ph_size = ph_size; + ec.th_size = 0; + + for (int i=0; i + +typedef void(*fun_ptr_t()); + +void fun1() __attribute__((used)); +void fun2() __attribute__((used)); +void fun3() __attribute__((used)); + +void fun1() +{ + printf("fun1!\n"); +} + +void fun2() +{ + printf("fun2!\n"); +} + +void fun3() +{ + printf("fun3!\n"); +} + + +__handler__ void htable_hh(handler_args_t *args) {;} +__handler__ void htable_th(handler_args_t *args){;} + + +__handler__ void htable_ph(handler_args_t *args) +{ + fun_ptr_t **htable = (fun_ptr_t**) args->task->handler_mem; + + //printf("payload handler (htable[1]: %p; fun2: %p)!\n", htable[1], fun2); + + //TODO: compute hash here and access entry accordingly! + (htable[0])(); + (htable[1])(); + (htable[2])(); + +} + +void init_handlers(handler_fn * hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {htable_hh, htable_ph, htable_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; +} diff --git a/examples/histogram/Makefile b/examples/histogram/Makefile new file mode 100644 index 0000000..95cf591 --- /dev/null +++ b/examples/histogram/Makefile @@ -0,0 +1,15 @@ +SPIN_APP_NAME = histogram_l1 +SPIN_APP_SRCS = histogram_l1.c +SPIN_CFLAGS = -O3 -g -flto +SPIN_LDFLAGS = -lm +NUM_PACKETS ?=512 +HAS_HH ?= 0 +HAS_TH ?= 1 +FULL_PKT = 1 +MSG_COUNT ?=1 +PKT_DELAY ?= 0 +MSG_DELAY ?= 0 +PKT_SIZE ?= 1024 +PKTGEN_CUSTOM_PARAMS="--fill-mod 1024" +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/histogram/handlers/histogram_l1.c b/examples/histogram/handlers/histogram_l1.c new file mode 100644 index 0000000..a3af871 --- /dev/null +++ b/examples/histogram/handlers/histogram_l1.c @@ -0,0 +1,82 @@ +#ifndef HOST +#include +#else +#include +#endif + +#include +#include + +#define NUM_CLUSTERS 4 +#define STRIDE 1 +#define OFFSET 0 +#define NUM_INT_OP 0 + +#define HISTOGRAM_SIZE 1024 + +#ifndef HOST +typedef uint32_t pspin_mem_ptr_t; +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0}; +#else +typedef uint64_t pspin_mem_ptr_t; +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0}; +#endif + +__handler__ void histogram_l1_hh(handler_args_t *args) +{ +} + + +__handler__ void histogram_l1_ph(handler_args_t *args) +{ + task_t* task = args->task; + + uint8_t *pkt_pld_ptr; + uint32_t pkt_pld_len; + GET_IP_UDP_PLD(task->pkt_mem, pkt_pld_ptr, pkt_pld_len); + pkt_pld_ptr += sizeof(app_hdr_t); + pkt_pld_len -= sizeof(app_hdr_t); + + int32_t *nic_pld_addr = (int32_t*) pkt_pld_ptr; + + int32_t *local_mem = (int32_t*) (task->scratchpad[args->cluster_id]); + //volatile uint8_t *local_mem = (volatile uint8_t*) (task->scratchpad[args->cluster_id]); + //printf("pktpld: %p; pkt_pld_len: %lu\n", nic_pld_addr, pkt_pld_len); + + volatile int32_t* word_ptr = &(local_mem[nic_pld_addr[0]]); + //int32_t mul = 4; + //we assume the number of msg size divides the pkt payload size + for (uint32_t i = 1; i < pkt_pld_len / 4; i++) + { + //amo_add(&(local_mem[nic_pld_addr[i]]), 1); + + //uint32_t word_idx = nic_pld_addr[i]; //FAST_MOD(nic_pld_addr[i], HISTOGRAM_SIZE); + //word_ptr = (volatile int32_t*) local_mem; + //asm volatile("p.mac %0, %1, %2" : : "r"(word_ptr), "r"(nic_pld_addr[i]), "r"(mul)); + + //word_ptr = (volatile int32_t*) (local_mem + (nic_pld_addr[i] << 2)); + //amo_add(word_ptr, 1); + + amo_add(word_ptr, 1); + word_ptr = &(local_mem[nic_pld_addr[i]]); + } +} +__handler__ void histogram_l1_th(handler_args_t *args) +{ + task_t* task = args->task; + uint64_t host_address = task->host_mem_high; + host_address = (host_address << 32) | (task->host_mem_low); + + //signal that we completed so to let the host read the result back + spin_host_write(host_address, (uint64_t) 1, false); +} + +void init_handlers(handler_fn *hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {histogram_l1_hh, histogram_l1_ph, histogram_l1_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void *)handler_mem; +} diff --git a/examples/host_direct/Makefile b/examples/host_direct/Makefile new file mode 100644 index 0000000..9d3ed05 --- /dev/null +++ b/examples/host_direct/Makefile @@ -0,0 +1,11 @@ +SPIN_APP_NAME = hostdirect +SPIN_APP_SRCS = hostdirect.c +SPIN_CFLAGS = -O3 -g ${DEFINITIONS} +SPIN_LDFLAGS = -lm -flto +NUM_PACKETS ?= 512 +PKT_DELAY ?= 0 +MSG_DELAY ?= 0 + + +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/host_direct/handlers/hostdirect.c b/examples/host_direct/handlers/hostdirect.c new file mode 100644 index 0000000..e25623c --- /dev/null +++ b/examples/host_direct/handlers/hostdirect.c @@ -0,0 +1,26 @@ + +#include +#include +#include + + +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0xde, 0xad, 0xbe, 0xef}; + +__handler__ void hostdirect_hh(handler_args_t *args) {;} +__handler__ void hostdirect_ph(handler_args_t *args) +{ + spin_cmd_t xfer; + spin_host_write(0xdeadbeef, 0xcafebebe, &xfer); +} +__handler__ void hostdirect_th(handler_args_t *args){;} + +void init_handlers(handler_fn * hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {hostdirect_hh, hostdirect_ph, hostdirect_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void*) handler_mem; +} + diff --git a/examples/ping_pong/Makefile b/examples/ping_pong/Makefile new file mode 100644 index 0000000..13453ec --- /dev/null +++ b/examples/ping_pong/Makefile @@ -0,0 +1,13 @@ +SPIN_APP_NAME = pingpong +SPIN_APP_SRCS = ping_pong.c +SPIN_CFLAGS = -O3 -g -flto +SPIN_LDFLAGS = -lm +NUM_PACKETS ?= 512 +PKT_DELAY ?= 0 +MSG_DELAY ?= 0 +FULL_PKT ?= 1 +HAS_HH = 0 +HAS_TH = 0 + +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/ping_pong/handlers/ping_pong.c b/examples/ping_pong/handlers/ping_pong.c new file mode 100644 index 0000000..c1ba5cd --- /dev/null +++ b/examples/ping_pong/handlers/ping_pong.c @@ -0,0 +1,62 @@ +#ifndef HOST +#include +#include +#include +#else +#include +#endif + +#if !defined(FROM_L2) && !defined(FROM_L1) +#define FROM_L1 +#endif + +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0xde, 0xad, 0xbe, 0xef}; + + +__handler__ void pingpong_hh(handler_args_t *args) {;} +__handler__ void pingpong_ph(handler_args_t *args) +{ + task_t* task = args->task; + ip_hdr_t *ip_hdr = (ip_hdr_t*) (task->pkt_mem); +#ifdef FROM_L2 + uint8_t *nic_pld_addr = ((uint8_t*) (task->l2_pkt_mem)); +#else + uint8_t *nic_pld_addr = ((uint8_t*) (task->pkt_mem)); +#endif + uint16_t pkt_pld_len = ip_hdr->length; + udp_hdr_t *udp_hdr = (udp_hdr_t*) (((uint8_t*) (task->pkt_mem)) + ip_hdr->ihl * 4); + + uint32_t src_id = ip_hdr->source_id; + ip_hdr->source_id = ip_hdr->dest_id; + ip_hdr->dest_id = src_id; + + uint16_t src_port = udp_hdr->src_port; + udp_hdr->src_port = udp_hdr->dst_port; + udp_hdr->dst_port = src_port; + + spin_cmd_t put; + spin_send_packet(nic_pld_addr, pkt_pld_len, &put); + + //It's not strictly necessary to wait. The hw will enforce that the feedback is not + //sent until all commands issued by this handlers are completed. +#ifdef WAIT_POLL + bool completed = false; + do { + spin_cmd_test(put, &completed); + } while (!completed); +#elif defined(WAIT_SUSPEND) + spin_cmd_wait(put); +#endif + +} +__handler__ void pingpong_th(handler_args_t *args){;} + +void init_handlers(handler_fn * hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {pingpong_hh, pingpong_ph, pingpong_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void*) handler_mem; +} diff --git a/examples/reduce/Makefile b/examples/reduce/Makefile new file mode 100644 index 0000000..ec09837 --- /dev/null +++ b/examples/reduce/Makefile @@ -0,0 +1,13 @@ +SPIN_APP_NAME = reduce_l1 +SPIN_APP_SRCS = reduce_l1.c +SPIN_CFLAGS = -O3 -g -flto +SPIN_LDFLAGS = -lm +NUM_PACKETS ?=512 +MSG_COUNT ?=1 +PKT_SIZE ?=1024 +HAS_HH?=0 +HAS_TH?=0 +FULL_PKT=1 +PKT_DELAY=0 +include $(PSPIN_RT)/spin-handlers.mk + diff --git a/examples/reduce/handlers/reduce_l1.c b/examples/reduce/handlers/reduce_l1.c new file mode 100644 index 0000000..48144bf --- /dev/null +++ b/examples/reduce/handlers/reduce_l1.c @@ -0,0 +1,74 @@ +#ifndef HOST +#include +#else +#include +#endif + +#include + +#include +#define NUM_CLUSTERS 4 +#define STRIDE 1 +#define OFFSET 0 +#define NUM_INT_OP 0 + +#define ZEROS 2048 +// Handler that implements reduce in scratchpad for int32 + +// 4 uint32_t -> locks +// 4 uint32_t -> L1 addresses +// 1 uint32_t -> msg_count (now 0x0200) + +#ifndef HOST +typedef uint32_t pspin_mem_ptr_t; +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0}; +#else +typedef uint64_t pspin_mem_ptr_t; +volatile __attribute__((section(".l2_handler_data"))) uint8_t handler_mem[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0}; +#endif + + +__handler__ void reduce_l1_hh(handler_args_t *args) +{ +} +__handler__ void reduce_l1_ph(handler_args_t *args) +{ + + task_t* task = args->task; + + uint8_t *pkt_pld_ptr; + uint32_t pkt_pld_len; + GET_IP_UDP_PLD(task->pkt_mem, pkt_pld_ptr, pkt_pld_len); + + uint32_t *nic_pld_addr = (uint32_t*) pkt_pld_ptr; + + //reduce_mem_t *mem = (reduce_mem_t *)args->her->match_info.handler_mem; + volatile int32_t *local_mem = (int32_t *)(task->scratchpad[args->cluster_id]); + + //we assume the number of msg size divides the pkt payload size + for (uint32_t i = 0; i < pkt_pld_len / 4; i++) + { + amo_add(&(local_mem[i]), nic_pld_addr[i]); + } + // We do need atomics here, as each handler writes to the same adress as other in the same cluster. +} +__handler__ void reduce_l1_th(handler_args_t *args) +{ + task_t* task = args->task; + uint64_t host_address = task->host_mem_high; + host_address = (host_address << 32) | (task->host_mem_low); + + //signal that we completed so to let the host read the result back + spin_host_write(host_address, (uint64_t) 1, false); +} + + +void init_handlers(handler_fn *hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr) +{ + volatile handler_fn handlers[] = {reduce_l1_hh, reduce_l1_ph, reduce_l1_th}; + *hh = handlers[0]; + *ph = handlers[1]; + *th = handlers[2]; + + *handler_mem_ptr = (void *)handler_mem; +} diff --git a/hw/deps/apb/src/apb_intf.sv b/hw/deps/apb/src/apb_intf.sv new file mode 100644 index 0000000..70a659c --- /dev/null +++ b/hw/deps/apb/src/apb_intf.sv @@ -0,0 +1,55 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Fabian Schuiki +// +// This file defines the interfaces we support. + +interface APB_BUS #( + parameter int unsigned APB_ADDR_WIDTH = 32, + parameter int unsigned APB_DATA_WIDTH = 32 +); + + logic [APB_ADDR_WIDTH-1:0] paddr; + logic [APB_DATA_WIDTH-1:0] pwdata; + logic pwrite; + logic psel; + logic penable; + logic [APB_DATA_WIDTH-1:0] prdata; + logic pready; + logic pslverr; + + + // Master Side + modport Master ( + output paddr, pwdata, pwrite, psel, penable, + input prdata, pready, pslverr + ); + + // Slave Side + modport Slave ( + input paddr, pwdata, pwrite, psel, penable, + output prdata, pready, pslverr + ); + + /// The interface as an output (issuing requests, initiator, master). + modport out ( + output paddr, pwdata, pwrite, psel, penable, + input prdata, pready, pslverr + ); + + /// The interface as an input (accepting requests, target, slave) + modport in ( + input paddr, pwdata, pwrite, psel, penable, + output prdata, pready, pslverr + ); + + +endinterface diff --git a/hw/deps/axi/src/axi_atop_filter.sv b/hw/deps/axi/src/axi_atop_filter.sv new file mode 100644 index 0000000..9b82f8b --- /dev/null +++ b/hw/deps/axi/src/axi_atop_filter.sv @@ -0,0 +1,427 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: +// Andreas Kurth + +// AXI ATOP Filter: This module filters atomic operations (ATOPs), i.e., write transactions that +// have a non-zero `aw_atop` value, from its `slv` to its `mst` port. This module guarantees that: +// +// 1) `aw_atop` is always zero on the `mst` port; +// +// 2) write transactions with non-zero `aw_atop` on the `slv` port are handled in conformance with +// the AXI standard by replying to such write transactions with the proper B and R responses. The +// response code on atomic operations that reach this module is always SLVERR +// (implementation-specific, not defined in the AXI standard). +// +// This module is intended to be placed between masters that may issue ATOPs and slaves that do not +// support ATOPs. That way, this module ensures that the AXI protocol remains in a defined state on +// systems with mixed ATOP capabilities. +// +// Interface note: +// The AXI standard specifies that there may be no ordering requirements between different atomic +// bursts (i.e., a burst started by an AW with ATOP other than 0) and none between atomic bursts and +// non-atomic bursts [E2.1.4]. That is, an atomic burst may never have the same ID as any other +// write or read burst that is ongoing at the same time. + +module axi_atop_filter #( + parameter int unsigned AxiIdWidth = 0, // Synopsys DC requires a default value for parameters. + // Maximum number of AXI write bursts outstanding at the same time + parameter int unsigned AxiMaxWriteTxns = 0, + // AXI request & response type + parameter type req_t = logic, + parameter type resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + // slave port + input req_t slv_req_i, + output resp_t slv_resp_o, + // master port + output req_t mst_req_o, + input resp_t mst_resp_i +); + + // Minimum counter width is 2 to detect underflows. + localparam int unsigned COUNTER_WIDTH = (AxiMaxWriteTxns == 1) ? 2 : $clog2(AxiMaxWriteTxns+1); + typedef struct packed { + logic underflow; + logic [COUNTER_WIDTH-1:0] cnt; + } cnt_t; + cnt_t w_cnt_d, w_cnt_q; + + typedef enum logic [2:0] { + W_FEEDTHROUGH, BLOCK_AW, ABSORB_W, HOLD_B, INJECT_B, WAIT_R + } w_state_e; + w_state_e w_state_d, w_state_q; + + typedef enum logic [1:0] { R_FEEDTHROUGH, INJECT_R, R_HOLD } r_state_e; + r_state_e r_state_d, r_state_q; + + typedef logic [AxiIdWidth-1:0] id_t; + id_t id_d, id_q; + + typedef logic [7:0] len_t; + len_t r_beats_d, r_beats_q; + + typedef struct packed { + len_t len; + } r_resp_cmd_t; + r_resp_cmd_t r_resp_cmd_push, r_resp_cmd_pop; + + logic aw_without_complete_w_downstream, + complete_w_without_aw_downstream, + r_resp_cmd_push_valid, r_resp_cmd_push_ready, + r_resp_cmd_pop_valid, r_resp_cmd_pop_ready; + + // An AW without a complete W burst is in-flight downstream if the W counter is > 0 and not + // underflowed. + assign aw_without_complete_w_downstream = !w_cnt_q.underflow && (w_cnt_q.cnt > 0); + // A complete W burst without AW is in-flight downstream if the W counter is -1. + assign complete_w_without_aw_downstream = w_cnt_q.underflow && &(w_cnt_q.cnt); + + // Manage AW, W, and B channels. + always_comb begin + // Defaults: + // Disable AW and W handshakes. + mst_req_o.aw_valid = 1'b0; + slv_resp_o.aw_ready = 1'b0; + mst_req_o.w_valid = 1'b0; + slv_resp_o.w_ready = 1'b0; + // Feed write responses through. + mst_req_o.b_ready = slv_req_i.b_ready; + slv_resp_o.b_valid = mst_resp_i.b_valid; + slv_resp_o.b = mst_resp_i.b; + // Keep ID stored for B and R response. + id_d = id_q; + // Do not push R response commands. + r_resp_cmd_push_valid = 1'b0; + // Keep the current state. + w_state_d = w_state_q; + + unique case (w_state_q) + W_FEEDTHROUGH: begin + // Feed AW channel through if the maximum number of outstanding bursts is not reached. + if (complete_w_without_aw_downstream || (w_cnt_q.cnt < AxiMaxWriteTxns)) begin + mst_req_o.aw_valid = slv_req_i.aw_valid; + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + end + // Feed W channel through if .. + if (aw_without_complete_w_downstream // .. downstream is missing W bursts .. + // .. or a new non-ATOP AW is being applied and there is not already a complete W burst + // downstream (to prevent underflows of w_cnt). + || ((slv_req_i.aw_valid && slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) + && !complete_w_without_aw_downstream) + ) begin + mst_req_o.w_valid = slv_req_i.w_valid; + slv_resp_o.w_ready = mst_resp_i.w_ready; + end + // Filter out AWs that are atomic operations. + if (slv_req_i.aw_valid && slv_req_i.aw.atop[5:4] != axi_pkg::ATOP_NONE) begin + mst_req_o.aw_valid = 1'b0; // Do not let AW pass to master port. + slv_resp_o.aw_ready = 1'b1; // Absorb AW on slave port. + id_d = slv_req_i.aw.id; // Store ID for B response. + // All atomic operations except atomic stores require a response on the R channel. + if (slv_req_i.aw.atop[5:4] != axi_pkg::ATOP_ATOMICSTORE) begin + // Push R response command. We do not have to wait for the ready of the register + // because we know it is ready: we are its only master and will wait for the register to + // be emptied before going back to the `W_FEEDTHROUGH` state. + r_resp_cmd_push_valid = 1'b1; + end + // If downstream is missing W beats, block the AW channel and let the W bursts complete. + if (aw_without_complete_w_downstream) begin + w_state_d = BLOCK_AW; + // If downstream is not missing W beats, absorb the W beats for this atomic AW. + end else begin + mst_req_o.w_valid = 1'b0; // Do not let W beats pass to master port. + slv_resp_o.w_ready = 1'b1; // Absorb W beats on slave port. + if (slv_req_i.w_valid && slv_req_i.w.last) begin + // If the W beat is valid and the last, proceed by injecting the B response. + // However, if there is a non-handshaked B on our response port, we must let that + // complete first. + if (slv_resp_o.b_valid && !slv_req_i.b_ready) begin + w_state_d = HOLD_B; + end else begin + w_state_d = INJECT_B; + end + end else begin + // Otherwise continue with absorbing W beats. + w_state_d = ABSORB_W; + end + end + end + end + + BLOCK_AW: begin + // Feed W channel through to let outstanding bursts complete. + if (aw_without_complete_w_downstream) begin + mst_req_o.w_valid = slv_req_i.w_valid; + slv_resp_o.w_ready = mst_resp_i.w_ready; + end else begin + // If there are no more outstanding W bursts, start absorbing the next W burst. + slv_resp_o.w_ready = 1'b1; + if (slv_req_i.w_valid && slv_req_i.w.last) begin + // If the W beat is valid and the last, proceed by injecting the B response. + if (slv_resp_o.b_valid && !slv_req_i.b_ready) begin + w_state_d = HOLD_B; + end else begin + w_state_d = INJECT_B; + end + end else begin + // Otherwise continue with absorbing W beats. + w_state_d = ABSORB_W; + end + end + end + + ABSORB_W: begin + // Absorb all W beats of the current burst. + slv_resp_o.w_ready = 1'b1; + if (slv_req_i.w_valid && slv_req_i.w.last) begin + if (slv_resp_o.b_valid && !slv_req_i.b_ready) begin + w_state_d = HOLD_B; + end else begin + w_state_d = INJECT_B; + end + end + end + + HOLD_B: begin + // Proceed with injection of B response upon handshake. + if (slv_resp_o.b_valid && slv_req_i.b_ready) begin + w_state_d = INJECT_B; + end + end + + INJECT_B: begin + // Pause forwarding of B response. + mst_req_o.b_ready = 1'b0; + // Inject error response instead. Since the B channel has an ID and the atomic burst we are + // replying to is guaranteed to be the only burst with this ID in flight, we do not have to + // observe any ordering and can immediately inject on the B channel. + slv_resp_o.b = '0; + slv_resp_o.b.id = id_q; + slv_resp_o.b.resp = axi_pkg::RESP_SLVERR; + slv_resp_o.b_valid = 1'b1; + if (slv_req_i.b_ready) begin + // If not all beats of the R response have been injected, wait for them. Otherwise, return + // to `W_FEEDTHROUGH`. + if (r_resp_cmd_pop_valid && !r_resp_cmd_pop_ready) begin + w_state_d = WAIT_R; + end else begin + w_state_d = W_FEEDTHROUGH; + end + end + end + + WAIT_R: begin + // Wait with returning to `W_FEEDTHROUGH` until all beats of the R response have been + // injected. + if (!r_resp_cmd_pop_valid) begin + w_state_d = W_FEEDTHROUGH; + end + end + + default: w_state_d = W_FEEDTHROUGH; + endcase + end + // Connect signals on AW and W channel that are not managed by the control FSM from slave port to + // master port. + // Feed-through of the AW and W vectors, make sure that downstream aw.atop is always zero + always_comb begin + // overwrite the atop signal + mst_req_o.aw = slv_req_i.aw; + mst_req_o.aw.atop = '0; + end + assign mst_req_o.w = slv_req_i.w; + + // Manage R channel. + always_comb begin + // Defaults: + // Feed read responses through. + slv_resp_o.r = mst_resp_i.r; + slv_resp_o.r_valid = mst_resp_i.r_valid; + mst_req_o.r_ready = slv_req_i.r_ready; + // Do not pop R response command. + r_resp_cmd_pop_ready = 1'b0; + // Keep the current value of the beats counter. + r_beats_d = r_beats_q; + // Keep the current state. + r_state_d = r_state_q; + + unique case (r_state_q) + R_FEEDTHROUGH: begin + if (mst_resp_i.r_valid && !slv_req_i.r_ready) begin + r_state_d = R_HOLD; + end else if (r_resp_cmd_pop_valid) begin + // Upon a command to inject an R response, immediately proceed with doing so because there + // are no ordering requirements with other bursts that may be ongoing on the R channel at + // this moment. + r_beats_d = r_resp_cmd_pop.len; + r_state_d = INJECT_R; + end + end + + INJECT_R: begin + mst_req_o.r_ready = 1'b0; + slv_resp_o.r = '0; + slv_resp_o.r.id = id_q; + slv_resp_o.r.resp = axi_pkg::RESP_SLVERR; + slv_resp_o.r.last = (r_beats_q == '0); + slv_resp_o.r_valid = 1'b1; + if (slv_req_i.r_ready) begin + if (slv_resp_o.r.last) begin + r_resp_cmd_pop_ready = 1'b1; + r_state_d = R_FEEDTHROUGH; + end else begin + r_beats_d -= 1; + end + end + end + + R_HOLD: begin + if (mst_resp_i.r_valid && slv_req_i.r_ready) begin + r_state_d = R_FEEDTHROUGH; + end + end + + default: r_state_d = R_FEEDTHROUGH; + endcase + end + // Feed all signals on AR through. + assign mst_req_o.ar = slv_req_i.ar; + assign mst_req_o.ar_valid = slv_req_i.ar_valid; + assign slv_resp_o.ar_ready = mst_resp_i.ar_ready; + + // Keep track of outstanding downstream write bursts and responses. + always_comb begin + w_cnt_d = w_cnt_q; + if (mst_req_o.aw_valid && mst_resp_i.aw_ready) begin + w_cnt_d.cnt += 1; + end + if (mst_req_o.w_valid && mst_resp_i.w_ready && mst_req_o.w.last) begin + w_cnt_d.cnt -= 1; + end + if (w_cnt_q.underflow && (w_cnt_d.cnt == '0)) begin + w_cnt_d.underflow = 1'b0; + end else if (w_cnt_q.cnt == '0 && &(w_cnt_d.cnt)) begin + w_cnt_d.underflow = 1'b1; + end + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + id_q <= '0; + r_beats_q <= '0; + r_state_q <= R_FEEDTHROUGH; + w_cnt_q <= '{default: '0}; + w_state_q <= W_FEEDTHROUGH; + end else begin + id_q <= id_d; + r_beats_q <= r_beats_d; + r_state_q <= r_state_d; + w_cnt_q <= w_cnt_d; + w_state_q <= w_state_d; + end + end + + stream_register #( + .T(r_resp_cmd_t) + ) r_resp_cmd ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_i (1'b0), + .testmode_i (1'b0), + .valid_i (r_resp_cmd_push_valid), + .ready_o (r_resp_cmd_push_ready), + .data_i (r_resp_cmd_push), + .valid_o (r_resp_cmd_pop_valid), + .ready_i (r_resp_cmd_pop_ready), + .data_o (r_resp_cmd_pop) + ); + assign r_resp_cmd_push.len = slv_req_i.aw.len; + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (AxiIdWidth >= 1) else $fatal(1, "AXI ID width must be at least 1!"); + assert (AxiMaxWriteTxns >= 1) + else $fatal(1, "Maximum number of outstanding write transactions must be at least 1!"); + end +`endif +// pragma translate_on +endmodule + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +// interface wrapper +module axi_atop_filter_intf #( + parameter int unsigned AXI_ID_WIDTH = 0, // Synopsys DC requires a default value for parameters. + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + // Maximum number of AXI write bursts outstanding at the same time + parameter int unsigned AXI_MAX_WRITE_TXNS = 0 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv, + AXI_BUS.Master mst +); + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req, mst_req; + resp_t slv_resp, mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_atop_filter #( + .AxiIdWidth ( AXI_ID_WIDTH ), + // Maximum number of AXI write bursts outstanding at the same time + .AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ), + // AXI request & response type + .req_t ( req_t ), + .resp_t ( resp_t ) + ) i_axi_atop_filter ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI ADDR width must be at least 1!"); + assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI DATA width must be at least 1!"); + assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI USER width must be at least 1!"); + end +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/axi/src/axi_buf.sv b/hw/deps/axi/src/axi_buf.sv new file mode 100644 index 0000000..9a56d78 --- /dev/null +++ b/hw/deps/axi/src/axi_buf.sv @@ -0,0 +1,247 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "axi/typedef.svh" + +module axi_buf #( + parameter int unsigned AwDepth = 32'd0, + parameter bit AwFallthrough = 1'b1, + parameter int unsigned WDepth = 32'd0, + parameter bit WFallthrough = 1'b1, + parameter int unsigned BDepth = 32'd0, + parameter bit BFallthrough = 1'b1, + parameter int unsigned ArDepth = 32'd0, + parameter bit ArFallthrough = 1'b1, + parameter int unsigned RDepth = 32'd0, + parameter bit RFallthrough = 1'b1, + parameter type req_t = logic, + parameter type resp_t = logic, + parameter int unsigned AddrWidth = 32'd0, + parameter int unsigned DataWidth = 32'd0, + parameter int unsigned IdWidth = 32'd0, + parameter int unsigned UserWidth = 32'd0 +) ( + input logic clk_i, + input logic rst_ni, + + input req_t slv_req_i, + output resp_t slv_resp_o, + + output req_t mst_req_o, + input resp_t mst_resp_i +); + + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [DataWidth/8-1:0] strb_t; + typedef logic [IdWidth-1:0] id_t; + typedef logic [UserWidth-1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + + if (AwDepth == 0) begin : gen_no_aw_fifo + assign mst_req_o.aw = slv_req_i.aw; + assign mst_req_o.aw_valid = slv_req_i.aw_valid; + assign slv_resp_o.aw_ready = mst_resp_i.aw_ready; + end else begin + stream_fifo #( + .FALL_THROUGH (AwFallthrough), + .DATA_WIDTH ($bits(aw_chan_t)), + .DEPTH (AwDepth) + ) i_aw_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .usage_o (/* unused */), + .data_i (slv_req_i.aw), + .valid_i (slv_req_i.aw_valid), + .ready_o (slv_resp_o.aw_ready), + .data_o (mst_req_o.aw), + .valid_o (mst_req_o.aw_valid), + .ready_i (mst_resp_i.aw_ready) + ); + end + + if (WDepth == 0) begin : gen_no_w_fifo + assign mst_req_o.w = slv_req_i.w; + assign mst_req_o.w_valid = slv_req_i.w_valid; + assign slv_resp_o.w_ready = mst_resp_i.w_ready; + end else begin + stream_fifo #( + .FALL_THROUGH (WFallthrough), + .DATA_WIDTH ($bits(w_chan_t)), + .DEPTH (WDepth) + ) i_w_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .usage_o (/* unused */), + .data_i (slv_req_i.w), + .valid_i (slv_req_i.w_valid), + .ready_o (slv_resp_o.w_ready), + .data_o (mst_req_o.w), + .valid_o (mst_req_o.w_valid), + .ready_i (mst_resp_i.w_ready) + ); + end + + if (BDepth == 0) begin : gen_no_b_fifo + assign slv_resp_o.b = mst_resp_i.b; + assign slv_resp_o.b_valid = mst_resp_i.b_valid; + assign mst_req_o.b_ready = slv_req_i.b_ready; + end else begin + stream_fifo #( + .FALL_THROUGH (BFallthrough), + .DATA_WIDTH ($bits(b_chan_t)), + .DEPTH (BDepth) + ) i_b_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .usage_o (/* unused */), + .data_i (mst_resp_i.b), + .valid_i (mst_resp_i.b_valid), + .ready_o (mst_req_o.b_ready), + .data_o (slv_resp_o.b), + .valid_o (slv_resp_o.b_valid), + .ready_i (slv_req_i.b_ready) + ); + end + + if (ArDepth == 0) begin : gen_no_ar_fifo + assign mst_req_o.ar = slv_req_i.ar; + assign mst_req_o.ar_valid = slv_req_i.ar_valid; + assign slv_resp_o.ar_ready = mst_resp_i.ar_ready; + end else begin + stream_fifo #( + .FALL_THROUGH (ArFallthrough), + .DATA_WIDTH ($bits(ar_chan_t)), + .DEPTH (ArDepth) + ) i_ar_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .usage_o (/* unused */), + .data_i (slv_req_i.ar), + .valid_i (slv_req_i.ar_valid), + .ready_o (slv_resp_o.ar_ready), + .data_o (mst_req_o.ar), + .valid_o (mst_req_o.ar_valid), + .ready_i (mst_resp_i.ar_ready) + ); + end + + if (RDepth == 0) begin : gen_no_r_fifo + assign slv_resp_o.r = mst_resp_i.r; + assign slv_resp_o.r_valid = mst_resp_i.r_valid; + assign mst_req_o.r_ready = slv_req_i.r_ready; + end else begin + stream_fifo #( + .FALL_THROUGH (RFallthrough), + .DATA_WIDTH ($bits(r_chan_t)), + .DEPTH (RDepth) + ) i_r_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .usage_o (/* unused */), + .data_i (mst_resp_i.r), + .valid_i (mst_resp_i.r_valid), + .ready_o (mst_req_o.r_ready), + .data_o (slv_resp_o.r), + .valid_o (slv_resp_o.r_valid), + .ready_i (slv_req_i.r_ready) + ); + end + +endmodule + +`include "axi/assign.svh" + +module axi_buf_intf #( + parameter int unsigned AW_DEPTH = 32'd0, + parameter bit AW_FALLTHROUGH = 1'b1, + parameter int unsigned W_DEPTH = 32'd0, + parameter bit W_FALLTHROUGH = 1'b1, + parameter int unsigned B_DEPTH = 32'd0, + parameter bit B_FALLTHROUGH = 1'b1, + parameter int unsigned AR_DEPTH = 32'd0, + parameter bit AR_FALLTHROUGH = 1'b1, + parameter int unsigned R_DEPTH = 32'd0, + parameter bit R_FALLTHROUGH = 1'b1, + parameter int unsigned ADDR_WIDTH = 32'd0, + parameter int unsigned DATA_WIDTH = 32'd0, + parameter int unsigned ID_WIDTH = 32'd0, + parameter int unsigned USER_WIDTH = 32'd0 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv, + AXI_BUS.Master mst +); + + typedef logic [ID_WIDTH-1:0] id_t; + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + typedef logic [USER_WIDTH-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req, mst_req; + resp_t slv_resp, mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_buf #( + .AwDepth (AW_DEPTH), + .AwFallthrough (AW_FALLTHROUGH), + .WDepth (W_DEPTH), + .WFallthrough (W_FALLTHROUGH), + .BDepth (B_DEPTH), + .BFallthrough (B_FALLTHROUGH), + .ArDepth (AR_DEPTH), + .ArFallthrough (AR_FALLTHROUGH), + .RDepth (R_DEPTH), + .RFallthrough (R_FALLTHROUGH), + .req_t (req_t), + .resp_t (resp_t), + .AddrWidth (ADDR_WIDTH), + .DataWidth (DATA_WIDTH), + .IdWidth (ID_WIDTH), + .UserWidth (USER_WIDTH) + ) i_axi_buf ( + .clk_i, + .rst_ni, + .slv_req_i (slv_req), + .slv_resp_o (slv_resp), + .mst_req_o (mst_req), + .mst_resp_i (mst_resp) + ); + +endmodule diff --git a/hw/deps/axi/src/axi_cut.sv b/hw/deps/axi/src/axi_cut.sv new file mode 100644 index 0000000..45bfa96 --- /dev/null +++ b/hw/deps/axi/src/axi_cut.sv @@ -0,0 +1,263 @@ +// Copyright (c) 2014-2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Fabian Schuiki +// Andreas Kurth + +/// An AXI4 cut. +/// +/// Breaks all combinatorial paths between its input and output. +module axi_cut #( + // bypass enable + parameter bit Bypass = 1'b0, + // AXI channel structs + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + // AXI request & response structs + parameter type req_t = logic, + parameter type resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + // salve port + input req_t slv_req_i, + output resp_t slv_resp_o, + // master port + output req_t mst_req_o, + input resp_t mst_resp_i +); + + // a spill register for each channel + spill_register #( + .T ( aw_chan_t ), + .Bypass ( Bypass ) + ) i_reg_aw ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.aw_valid ), + .ready_o ( slv_resp_o.aw_ready ), + .data_i ( slv_req_i.aw ), + .valid_o ( mst_req_o.aw_valid ), + .ready_i ( mst_resp_i.aw_ready ), + .data_o ( mst_req_o.aw ) + ); + + spill_register #( + .T ( w_chan_t ), + .Bypass ( Bypass ) + ) i_reg_w ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.w_valid ), + .ready_o ( slv_resp_o.w_ready ), + .data_i ( slv_req_i.w ), + .valid_o ( mst_req_o.w_valid ), + .ready_i ( mst_resp_i.w_ready ), + .data_o ( mst_req_o.w ) + ); + + spill_register #( + .T ( b_chan_t ), + .Bypass ( Bypass ) + ) i_reg_b ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.b_valid ), + .ready_o ( mst_req_o.b_ready ), + .data_i ( mst_resp_i.b ), + .valid_o ( slv_resp_o.b_valid ), + .ready_i ( slv_req_i.b_ready ), + .data_o ( slv_resp_o.b ) + ); + + spill_register #( + .T ( ar_chan_t ), + .Bypass ( Bypass ) + ) i_reg_ar ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.ar_valid ), + .ready_o ( slv_resp_o.ar_ready ), + .data_i ( slv_req_i.ar ), + .valid_o ( mst_req_o.ar_valid ), + .ready_i ( mst_resp_i.ar_ready ), + .data_o ( mst_req_o.ar ) + ); + + spill_register #( + .T ( r_chan_t ), + .Bypass ( Bypass ) + ) i_reg_r ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.r_valid ), + .ready_o ( mst_req_o.r_ready ), + .data_i ( mst_resp_i.r ), + .valid_o ( slv_resp_o.r_valid ), + .ready_i ( slv_req_i.r_ready ), + .data_o ( slv_resp_o.r ) + ); +endmodule + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +// interface wrapper +module axi_cut_intf #( + // Bypass eneable + parameter bit BYPASS = 1'b0, + // The address width. + parameter int unsigned ADDR_WIDTH = 0, + // The data width. + parameter int unsigned DATA_WIDTH = 0, + // The ID width. + parameter int unsigned ID_WIDTH = 0, + // The user data width. + parameter int unsigned USER_WIDTH = 0 +) ( + input logic clk_i , + input logic rst_ni , + AXI_BUS.Slave in , + AXI_BUS.Master out +); + + typedef logic [ID_WIDTH-1:0] id_t; + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + typedef logic [USER_WIDTH-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req, mst_req; + resp_t slv_resp, mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, in) + `AXI_ASSIGN_FROM_RESP(in, slv_resp) + + `AXI_ASSIGN_FROM_REQ(out, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, out) + + axi_cut #( + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .req_t ( req_t ), + .resp_t ( resp_t ) + ) i_axi_cut ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + + // Check the invariants. + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (ADDR_WIDTH > 0) else $fatal(1, "Wrong addr width parameter"); + assert (DATA_WIDTH > 0) else $fatal(1, "Wrong data width parameter"); + assert (ID_WIDTH > 0) else $fatal(1, "Wrong id width parameter"); + assert (USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); + assert (in.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_ID_WIDTH == ID_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_USER_WIDTH == USER_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_ID_WIDTH == ID_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_USER_WIDTH == USER_WIDTH) else $fatal(1, "Wrong interface definition"); + end + `endif + // pragma translate_on +endmodule + +module axi_lite_cut_intf #( + // bypass enable + parameter bit BYPASS = 1'b0, + /// The address width. + parameter int unsigned ADDR_WIDTH = 0, + /// The data width. + parameter int unsigned DATA_WIDTH = 0 +) ( + input logic clk_i , + input logic rst_ni , + AXI_LITE.Slave in , + AXI_LITE.Master out +); + + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + + `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t) + `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t) + `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) + `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) + `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) + `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req, mst_req; + resp_t slv_resp, mst_resp; + + `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) + `AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp) + + `AXI_LITE_ASSIGN_FROM_REQ(out, mst_req) + `AXI_LITE_ASSIGN_TO_RESP(mst_resp, out) + + axi_cut #( + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .req_t ( req_t ), + .resp_t ( resp_t ) + ) i_axi_cut ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + + // Check the invariants. + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (ADDR_WIDTH > 0) else $fatal(1, "Wrong addr width parameter"); + assert (DATA_WIDTH > 0) else $fatal(1, "Wrong data width parameter"); + assert (in.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + end + `endif + // pragma translate_on +endmodule diff --git a/hw/deps/axi/src/axi_demux.sv b/hw/deps/axi/src/axi_demux.sv new file mode 100644 index 0000000..3cc3120 --- /dev/null +++ b/hw/deps/axi/src/axi_demux.sv @@ -0,0 +1,741 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +`include "common_cells/registers.svh" + + + +// axi_demux: Demultiplex an AXI bus from one slave port to multiple master ports. +// See `doc/axi_demux.md` for the documentation, including the definition of parameters and ports. +module axi_demux #( + parameter int unsigned AxiIdWidth = 32'd0, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type req_t = logic, + parameter type resp_t = logic, + parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned MaxTrans = 32'd8, + parameter int unsigned AxiLookBits = 32'd3, + parameter bit FallThrough = 1'b0, + parameter bit SpillAw = 1'b1, + parameter bit SpillW = 1'b0, + parameter bit SpillB = 1'b0, + parameter bit SpillAr = 1'b1, + parameter bit SpillR = 1'b0, + // Dependent parameters, DO NOT OVERRIDE! + parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1, + parameter type select_t = logic [SelectWidth-1:0] +) ( + input logic clk_i, + input logic rst_ni, + input logic test_i, + // Slave Port + input req_t slv_req_i, + input select_t slv_aw_select_i, + input select_t slv_ar_select_i, + output resp_t slv_resp_o, + // Master Ports + /* verilator lint_off UNOPTFLAT */ + output req_t [NoMstPorts-1:0] mst_reqs_o, + /* verilator lint_on UNOPTFLAT */ + input resp_t [NoMstPorts-1:0] mst_resps_i +); + + localparam int unsigned IdCounterWidth = MaxTrans > 1 ? $clog2(MaxTrans) : 1; + + //-------------------------------------- + // Typedefs for the FIFOs / Queues + //-------------------------------------- + typedef logic [AxiIdWidth-1:0] axi_id_t; + typedef struct packed { + aw_chan_t aw_chan; + select_t aw_select; + } aw_chan_select_t; + typedef struct packed { + ar_chan_t ar_chan; + select_t ar_select; + } ar_chan_select_t; + + // pass through if only one master port + if (NoMstPorts == 32'h1) begin : gen_no_demux + assign mst_reqs_o[0] = slv_req_i; + assign slv_resp_o = mst_resps_i; + // other non degenerate cases + end else begin : gen_demux + + //-------------------------------------- + //-------------------------------------- + // Signal Declarations + //-------------------------------------- + //-------------------------------------- + + //-------------------------------------- + // Write Transaction + //-------------------------------------- + // comes from spill register at input + aw_chan_select_t slv_aw_chan_select; + logic slv_aw_valid, slv_aw_ready; + + // AW ID counter + select_t lookup_aw_select; + logic aw_select_occupied, aw_id_cnt_full; + logic aw_push; + // Upon an ATOP load, inject IDs from the AW into the AR channel + logic atop_inject; + + // W FIFO: stores the decision to which master W beats should go + logic w_fifo_pop; + logic w_fifo_full, w_fifo_empty; + select_t w_select; + + // Register which locks the AW valid signal + logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; + logic aw_valid, aw_ready; + + // W channel from spill reg + w_chan_t slv_w_chan; + logic slv_w_valid, slv_w_ready; + + // B channles input into the arbitration + b_chan_t [NoMstPorts-1:0] mst_b_chans; + logic [NoMstPorts-1:0] mst_b_valids, mst_b_readies; + + // B channel to spill register + b_chan_t slv_b_chan; + logic slv_b_valid, slv_b_ready; + + //-------------------------------------- + // Read Transaction + //-------------------------------------- + // comes from spill register at input + ar_chan_select_t slv_ar_chan_select; + logic slv_ar_valid, slv_ar_ready; + + // AR ID counter + select_t lookup_ar_select; + logic ar_select_occupied, ar_id_cnt_full; + logic ar_push; + + // Register which locks the AR valid signel + logic lock_ar_valid_d, lock_ar_valid_q, load_ar_lock; + logic ar_valid, ar_ready; + + // R channles input into the arbitration + r_chan_t [NoMstPorts-1:0] mst_r_chans; + logic [NoMstPorts-1:0] mst_r_valids, mst_r_readies; + + // R channel to spill register + r_chan_t slv_r_chan; + logic slv_r_valid, slv_r_ready; + + //-------------------------------------- + //-------------------------------------- + // Channel Control + //-------------------------------------- + //-------------------------------------- + + //-------------------------------------- + // AW Channel + //-------------------------------------- + // spill register at the channel input + aw_chan_select_t slv_aw_chan_select_in; + assign slv_aw_chan_select_in.aw_chan = slv_req_i.aw; + assign slv_aw_chan_select_in.aw_select = slv_aw_select_i; + + spill_register #( + .T ( aw_chan_select_t ), + .Bypass ( ~SpillAw ) // because module param indicates if we want a spill reg + ) i_aw_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.aw_valid ), + .ready_o ( slv_resp_o.aw_ready ), + .data_i ( slv_aw_chan_select_in ), + .valid_o ( slv_aw_valid ), + .ready_i ( slv_aw_ready ), + .data_o ( slv_aw_chan_select ) + ); + + // Control of the AW handshake + always_comb begin + // AXI Handshakes + slv_aw_ready = 1'b0; + aw_valid = 1'b0; + // `lock_aw_valid`, used to be protocol conform as it is not allowed to deassert + // a valid if there was no corresponding ready. As this process has to be able to inject + // an AXI ID into the counter of the AR channel on an ATOP, there could be a case where + // this process waits on `aw_ready` but in the mean time on the AR channel the counter gets + // full. + lock_aw_valid_d = lock_aw_valid_q; + load_aw_lock = 1'b0; + // AW ID counter and W FIFO + aw_push = 1'b0; + // ATOP injection into ar counter + atop_inject = 1'b0; + // we had an arbitration decision, the valid is locked, wait for the transaction + if (lock_aw_valid_q) begin + aw_valid = 1'b1; + // transaction + if (aw_ready) begin + slv_aw_ready = 1'b1; + lock_aw_valid_d = 1'b0; + load_aw_lock = 1'b1; + atop_inject = slv_aw_chan_select.aw_chan.atop[5]; // inject the ATOP if necessary + end + end else begin + // Process can start handling a transaction if its `i_aw_id_counter` and `w_fifo` have + // space in them. Further check if we could inject something on the AR channel. + if (!aw_id_cnt_full && !w_fifo_full && !ar_id_cnt_full) begin + // there is a valid AW vector make the id lookup and go further, if it passes + if (slv_aw_valid && (!aw_select_occupied || + (slv_aw_chan_select.aw_select == lookup_aw_select))) begin + // connect the handshake + aw_valid = 1'b1; + // push arbitration to the W FIFO regardless, do not wait for the AW transaction + aw_push = 1'b1; + // on AW transaction + if (aw_ready) begin + slv_aw_ready = 1'b1; + atop_inject = slv_aw_chan_select.aw_chan.atop[5]; + // no AW transaction this cycle, lock the decision + end else begin + lock_aw_valid_d = 1'b1; + load_aw_lock = 1'b1; + end + end + end + end + end + + // lock the valid signal, as the selection gets pushed into the W FIFO on first assertion, + // prevent further pushing + `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + + axi_demux_id_counters #( + .AxiIdBits ( AxiLookBits ), + .CounterWidth ( IdCounterWidth ), + .mst_port_select_t ( select_t ) + ) i_aw_id_counter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .lookup_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ), + .lookup_mst_select_o ( lookup_aw_select ), + .lookup_mst_select_occupied_o ( aw_select_occupied ), + .full_o ( aw_id_cnt_full ), + .inject_axi_id_i ( '0 ), + .inject_i ( 1'b0 ), + .push_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ), + .push_mst_select_i ( slv_aw_chan_select.aw_select ), + .push_i ( aw_push ), + .pop_axi_id_i ( slv_b_chan.id[0+:AxiLookBits] ), + .pop_i ( slv_b_valid & slv_b_ready ) + ); + // pop from ID counter on outward transaction + + // FIFO to save W selection + fifo_v3 #( + .FALL_THROUGH ( FallThrough ), + .DEPTH ( MaxTrans ), + .dtype ( select_t ) + ) i_w_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( test_i ), + .full_o ( w_fifo_full ), + .empty_o ( w_fifo_empty ), + .usage_o ( ), + .data_i ( slv_aw_chan_select.aw_select ), + .push_i ( aw_push ), // controlled from proc_aw_chan + .data_o ( w_select ), // where the w beat should go + .pop_i ( w_fifo_pop ) // controlled from proc_w_chan + ); + + //-------------------------------------- + // W Channel + //-------------------------------------- + spill_register #( + .T ( w_chan_t ), + .Bypass ( ~SpillW ) + ) i_w_spill_reg( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.w_valid ), + .ready_o ( slv_resp_o.w_ready ), + .data_i ( slv_req_i.w ), + .valid_o ( slv_w_valid ), + .ready_i ( slv_w_ready ), + .data_o ( slv_w_chan ) + ); + + //-------------------------------------- + // B Channel + //-------------------------------------- + // optional spill register + spill_register #( + .T ( b_chan_t ), + .Bypass ( ~SpillB ) + ) i_b_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_b_valid ), + .ready_o ( slv_b_ready ), + .data_i ( slv_b_chan ), + .valid_o ( slv_resp_o.b_valid ), + .ready_i ( slv_req_i.b_ready ), + .data_o ( slv_resp_o.b ) + ); + + // Arbitration of the different B responses + rr_arb_tree #( + .NumIn ( NoMstPorts ), + .DataType ( b_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_b_mux ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i( 1'b0 ), + .rr_i ( '0 ), + .req_i ( mst_b_valids ), + .gnt_o ( mst_b_readies ), + .data_i ( mst_b_chans ), + .gnt_i ( slv_b_ready ), + .req_o ( slv_b_valid ), + .data_o ( slv_b_chan ), + .idx_o ( ) + ); + + //-------------------------------------- + // AR Channel + //-------------------------------------- + ar_chan_select_t slv_ar_chan_select_in; + assign slv_ar_chan_select_in.ar_chan = slv_req_i.ar; + // assign slv_ar_chan_select_in.ar_chan = slv_ar_chan_i; + assign slv_ar_chan_select_in.ar_select = slv_ar_select_i; + spill_register #( + .T ( ar_chan_select_t ), + .Bypass ( ~SpillAr ) + ) i_ar_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.ar_valid ), + .ready_o ( slv_resp_o.ar_ready ), + .data_i ( slv_ar_chan_select_in ), + .valid_o ( slv_ar_valid ), + .ready_i ( slv_ar_ready ), + .data_o ( slv_ar_chan_select ) + ); + + // control of the AR handshake + always_comb begin + // AXI Handshakes + slv_ar_ready = 1'b0; + ar_valid = 1'b0; + // `lock_ar_valid`: Used to be protocol conform as it is not allowed to deassert `ar_valid` + // if there was no corresponding `ar_ready`. There is the possibility that an injection + // of a R response from an `atop` from the AW channel can change the occupied flag of the + // `i_ar_id_counter`, even if it was previously empty. This FF prevents the deassertion. + lock_ar_valid_d = lock_ar_valid_q; + load_ar_lock = 1'b0; + // AR id counter + ar_push = 1'b0; + // The process had an arbitration decision in a previous cycle, the valid is locked, + // wait for the AR transaction. + if (lock_ar_valid_q) begin + ar_valid = 1'b1; + // transaction + if (ar_ready) begin + slv_ar_ready = 1'b1; + ar_push = 1'b1; + lock_ar_valid_d = 1'b0; + load_ar_lock = 1'b1; + end + end else begin + // The process can start handling AR transaction if `i_ar_id_counter` has space. + if (!ar_id_cnt_full) begin + // There is a valid AR, so look the ID up. + if (slv_ar_valid && (!ar_select_occupied || + (slv_ar_chan_select.ar_select == lookup_ar_select))) begin + // connect the AR handshake + ar_valid = 1'b1; + // on transaction + if (ar_ready) begin + slv_ar_ready = 1'b1; + ar_push = 1'b1; + // no transaction this cycle, lock the valid decision! + end else begin + lock_ar_valid_d = 1'b1; + load_ar_lock = 1'b1; + end + end + end + end + end + + // this ff is needed so that ar does not get de-asserted if an atop gets injected + `FFLARN(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni) + + axi_demux_id_counters #( + .AxiIdBits ( AxiLookBits ), + .CounterWidth ( IdCounterWidth ), + .mst_port_select_t ( select_t ) + ) i_ar_id_counter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .lookup_axi_id_i ( slv_ar_chan_select.ar_chan.id[0+:AxiLookBits] ), + .lookup_mst_select_o ( lookup_ar_select ), + .lookup_mst_select_occupied_o ( ar_select_occupied ), + .full_o ( ar_id_cnt_full ), + .inject_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ), + .inject_i ( atop_inject ), + .push_axi_id_i ( slv_ar_chan_select.ar_chan.id[0+:AxiLookBits] ), + .push_mst_select_i ( slv_ar_chan_select.ar_select ), + .push_i ( ar_push ), + .pop_axi_id_i ( slv_r_chan.id[0+:AxiLookBits] ), + .pop_i ( slv_r_valid & slv_r_ready & slv_r_chan.last ) + ); + + //-------------------------------------- + // R Channel + //-------------------------------------- + // optional spill register + spill_register #( + .T ( r_chan_t ), + .Bypass ( ~SpillR ) + ) i_r_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_r_valid ), + .ready_o ( slv_r_ready ), + .data_i ( slv_r_chan ), + .valid_o ( slv_resp_o.r_valid ), + .ready_i ( slv_req_i.r_ready ), + .data_o ( slv_resp_o.r ) + ); + + // Arbitration of the different r responses + rr_arb_tree #( + .NumIn ( NoMstPorts ), + .DataType ( r_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_r_mux ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i( 1'b0 ), + .rr_i ( '0 ), + .req_i ( mst_r_valids ), + .gnt_o ( mst_r_readies ), + .data_i ( mst_r_chans ), + .gnt_i ( slv_r_ready ), + .req_o ( slv_r_valid ), + .data_o ( slv_r_chan ), + .idx_o ( ) + ); + + // process that defines the individual demuxes and assignments for the arbitration + // as mst_reqs_o has to be drivem from the same always comb block! + always_comb begin + // default assignments + mst_reqs_o = '0; + aw_ready = 1'b0; + slv_w_ready = 1'b0; + w_fifo_pop = 1'b0; + ar_ready = 1'b0; + + for (int unsigned i = 0; i < NoMstPorts; i++) begin + // AW channel + mst_reqs_o[i].aw = slv_aw_chan_select.aw_chan; + mst_reqs_o[i].aw_valid = 1'b0; + if (aw_valid && (slv_aw_chan_select.aw_select == i)) begin + mst_reqs_o[i].aw_valid = 1'b1; + aw_ready = mst_resps_i[i].aw_ready; + end + + // W channel + mst_reqs_o[i].w = slv_w_chan; + mst_reqs_o[i].w_valid = 1'b0; + if (!w_fifo_empty && (w_select == i)) begin + mst_reqs_o[i].w_valid = slv_w_valid; + slv_w_ready = mst_resps_i[i].w_ready; + w_fifo_pop = slv_w_valid & mst_resps_i[i].w_ready & slv_w_chan.last; + end + + // B channel + mst_reqs_o[i].b_ready = mst_b_readies[i]; + + // AR channel + mst_reqs_o[i].ar = slv_ar_chan_select.ar_chan; + mst_reqs_o[i].ar_valid = 1'b0; + if (ar_valid && (slv_ar_chan_select.ar_select == i)) begin + mst_reqs_o[i].ar_valid = 1'b1; + ar_ready = mst_resps_i[i].ar_ready; + end + + // R channel + mst_reqs_o[i].r_ready = mst_r_readies[i]; + end + end + // unpack the response B and R channels for the arbitration + for (genvar i = 0; i < NoMstPorts; i++) begin : gen_b_channels + assign mst_b_chans[i] = mst_resps_i[i].b; + assign mst_b_valids[i] = mst_resps_i[i].b_valid; + assign mst_r_chans[i] = mst_resps_i[i].r; + assign mst_r_valids[i] = mst_resps_i[i].r_valid; + end + + +// Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + no_mst_ports: assume (NoMstPorts > 0) else + $fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1"); + AXI_ID_BITS: assume (AxiIdWidth >= AxiLookBits) else + $fatal(1, "AxiIdBits has to be equal or smaller than AxiIdWidth."); + end + default disable iff (!rst_ni); + aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> + (slv_aw_select_i < NoMstPorts))) else + $fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\ + NoMstPorts: %d", slv_aw_select_i, NoMstPorts); + ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |-> + (slv_ar_select_i < NoMstPorts))) else + $fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\ + NoMstPorts: %d", slv_ar_select_i, NoMstPorts); + aw_valid_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) |=> aw_valid) else + $fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle."); + ar_valid_stable: assert property( @(posedge clk_i) + (ar_valid && !ar_ready) |=> ar_valid) else + $fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle."); + aw_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) + |=> $stable(slv_aw_chan_select)) else + $fatal(1, "slv_aw_chan_select unstable with valid set."); + ar_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) + |=> $stable(slv_ar_chan_select)) else + $fatal(1, "slv_aw_chan_select unstable with valid set."); +`endif +// pragma translate_on + end +endmodule + +module axi_demux_id_counters #( + // the lower bits of the AXI ID that should be considered, results in 2**AXI_ID_BITS counters + parameter int unsigned AxiIdBits = 2, + parameter int unsigned CounterWidth = 4, + parameter type mst_port_select_t = logic +) ( + input clk_i, // Clock + input rst_ni, // Asynchronous reset active low + // lookup + input logic [AxiIdBits-1:0] lookup_axi_id_i, + output mst_port_select_t lookup_mst_select_o, + output logic lookup_mst_select_occupied_o, + // push + output logic full_o, + input logic [AxiIdBits-1:0] push_axi_id_i, + input mst_port_select_t push_mst_select_i, + input logic push_i, + // inject ATOPs in AR channel + input logic [AxiIdBits-1:0] inject_axi_id_i, + input logic inject_i, + // pop + input logic [AxiIdBits-1:0] pop_axi_id_i, + input logic pop_i +); + localparam int unsigned NoCounters = 2**AxiIdBits; + typedef logic [CounterWidth-1:0] cnt_t; + + // registers, each gets loaded when push_en[i] + mst_port_select_t [NoCounters-1:0] mst_select_q; + + // counter signals + logic [NoCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full; + + //----------------------------------- + // Lookup + //----------------------------------- + assign lookup_mst_select_o = mst_select_q[lookup_axi_id_i]; + assign lookup_mst_select_occupied_o = occupied[lookup_axi_id_i]; + //----------------------------------- + // Push and Pop + //----------------------------------- + assign push_en = (push_i) ? (1 << push_axi_id_i) : '0; + assign inject_en = (inject_i) ? (1 << inject_axi_id_i) : '0; + assign pop_en = (pop_i) ? (1 << pop_axi_id_i) : '0; + assign full_o = |cnt_full; + // counters + for (genvar i = 0; i < NoCounters; i++) begin : gen_counters + logic cnt_en, cnt_down, overflow; + cnt_t cnt_delta, in_flight; + always_comb begin + unique case ({push_en[i], inject_en[i], pop_en[i]}) + 3'b001 : begin // pop_i = -1 + cnt_en = 1'b1; + cnt_down = 1'b1; + cnt_delta = cnt_t'(1); + end + 3'b010 : begin // inject_i = +1 + cnt_en = 1'b1; + cnt_down = 1'b0; + cnt_delta = cnt_t'(1); + end + // 3'b011, inject_i & pop_i = 0 --> use default + 3'b100 : begin // push_i = +1 + cnt_en = 1'b1; + cnt_down = 1'b0; + cnt_delta = cnt_t'(1); + end + // 3'b101, push_i & pop_i = 0 --> use default + 3'b110 : begin // push_i & inject_i = +2 + cnt_en = 1'b1; + cnt_down = 1'b0; + cnt_delta = cnt_t'(2); + end + 3'b111 : begin // push_i & inject_i & pop_i = +1 + cnt_en = 1'b1; + cnt_down = 1'b0; + cnt_delta = cnt_t'(1); + end + default : begin // do nothing to the counters + cnt_en = 1'b0; + cnt_down = 1'b0; + cnt_delta = cnt_t'(0); + end + endcase + end + + delta_counter #( + .WIDTH ( CounterWidth ), + .STICKY_OVERFLOW ( 1'b0 ) + ) i_in_flight_cnt ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( 1'b0 ), + .en_i ( cnt_en ), + .load_i ( 1'b0 ), + .down_i ( cnt_down ), + .delta_i ( cnt_delta ), + .d_i ( '0 ), + .q_o ( in_flight ), + .overflow_o ( overflow ) + ); + assign occupied[i] = |in_flight; + assign cnt_full[i] = overflow | (&in_flight); + + // holds the selection signal for this id + `FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni) + +// pragma translate_off +`ifndef VERILATOR + // Validate parameters. + cnt_underflow: assert property( + @(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else + $fatal(1, "axi_demux_id_counters > Counter: %0d underflowed.\ + The reason is probably a faulty AXI response.", i); +`endif +// pragma translate_on + end +endmodule + +// interface wrapper +`include "axi/assign.svh" +`include "axi/typedef.svh" +module axi_demux_intf #( + parameter int unsigned AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned NO_MST_PORTS = 32'd3, + parameter int unsigned MAX_TRANS = 32'd8, + parameter int unsigned AXI_LOOK_BITS = 32'd3, + parameter bit FALL_THROUGH = 1'b0, + parameter bit SPILL_AW = 1'b1, + parameter bit SPILL_W = 1'b0, + parameter bit SPILL_B = 1'b0, + parameter bit SPILL_AR = 1'b1, + parameter bit SPILL_R = 1'b0, + // Dependent parameters, DO NOT OVERRIDE! + parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1, + parameter type select_t = logic [SELECT_WIDTH-1:0] // MST port select type +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable + input select_t slv_aw_select_i, // has to be stable, when aw_valid + input select_t slv_ar_select_i, // has to be stable, when ar_valid + AXI_BUS.Slave slv, // slave port + AXI_BUS.Master mst [NO_MST_PORTS-1:0] // master ports +); + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req; + resp_t slv_resp; + req_t [NO_MST_PORTS-1:0] mst_req; + resp_t [NO_MST_PORTS-1:0] mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + + for (genvar i = 0; i < NO_MST_PORTS; i++) begin : gen_assign_mst_ports + `AXI_ASSIGN_FROM_REQ(mst[i], mst_req[i]) + `AXI_ASSIGN_TO_RESP(mst_resp[i], mst[i]) + end + + axi_demux #( + .AxiIdWidth ( AXI_ID_WIDTH ), // ID Width + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .req_t ( req_t ), + .resp_t ( resp_t ), + .NoMstPorts ( NO_MST_PORTS ), + .MaxTrans ( MAX_TRANS ), + .AxiLookBits ( AXI_LOOK_BITS ), + .FallThrough ( FALL_THROUGH ), + .SpillAw ( SPILL_AW ), + .SpillW ( SPILL_W ), + .SpillB ( SPILL_B ), + .SpillAr ( SPILL_AR ), + .SpillR ( SPILL_R ) + ) i_axi_demux ( + .clk_i, // Clock + .rst_ni, // Asynchronous reset active low + .test_i, // Testmode enable + // slave port + .slv_req_i ( slv_req ), + .slv_aw_select_i ( slv_aw_select_i ), + .slv_ar_select_i ( slv_ar_select_i ), + .slv_resp_o ( slv_resp ), + // master port + .mst_reqs_o ( mst_req ), + .mst_resps_i ( mst_resp ) + ); +endmodule diff --git a/hw/deps/axi/src/axi_dw_converter.sv b/hw/deps/axi/src/axi_dw_converter.sv new file mode 100644 index 0000000..d708c62 --- /dev/null +++ b/hw/deps/axi/src/axi_dw_converter.sv @@ -0,0 +1,188 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Matheus Cavalcante + +// NOTE: The upsizer/downsizer do not support WRAP and FIXED bursts, and +// will answer with SLVERR upon receiving a burst of such types. + +module axi_dw_converter #( + parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads + parameter int unsigned AxiSlvPortDataWidth = 8 , // Data width of the slv port + parameter int unsigned AxiMstPortDataWidth = 8 , // Data width of the mst port + parameter int unsigned AxiAddrWidth = 1 , // Address width + parameter int unsigned AxiIdWidth = 1 , // ID width + parameter type aw_chan_t = logic, // AW Channel Type + parameter type mst_w_chan_t = logic, // W Channel Type for the mst port + parameter type slv_w_chan_t = logic, // W Channel Type for the slv port + parameter type b_chan_t = logic, // B Channel Type + parameter type ar_chan_t = logic, // AR Channel Type + parameter type mst_r_chan_t = logic, // R Channel Type for the mst port + parameter type slv_r_chan_t = logic, // R Channel Type for the slv port + parameter type axi_mst_req_t = logic, // AXI Request Type for mst ports + parameter type axi_mst_resp_t = logic, // AXI Response Type for mst ports + parameter type axi_slv_req_t = logic, // AXI Request Type for slv ports + parameter type axi_slv_resp_t = logic // AXI Response Type for slv ports + ) ( + input logic clk_i, + input logic rst_ni, + // Slave interface + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + // Master interface + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i + ); + + if (AxiMstPortDataWidth == AxiSlvPortDataWidth) begin: gen_no_dw_conversion + assign mst_req_o = slv_req_i ; + assign slv_resp_o = mst_resp_i; + end : gen_no_dw_conversion + + if (AxiMstPortDataWidth > AxiSlvPortDataWidth) begin: gen_dw_upsize + axi_dw_upsizer #( + .AxiMaxReads (AxiMaxReads ), + .AxiSlvPortDataWidth(AxiSlvPortDataWidth), + .AxiMstPortDataWidth(AxiMstPortDataWidth), + .AxiAddrWidth (AxiAddrWidth ), + .AxiIdWidth (AxiIdWidth ), + .aw_chan_t (aw_chan_t ), + .mst_w_chan_t (mst_w_chan_t ), + .slv_w_chan_t (slv_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .mst_r_chan_t (mst_r_chan_t ), + .slv_r_chan_t (slv_r_chan_t ), + .axi_mst_req_t (axi_mst_req_t ), + .axi_mst_resp_t (axi_mst_resp_t ), + .axi_slv_req_t (axi_slv_req_t ), + .axi_slv_resp_t (axi_slv_resp_t ) + ) i_axi_dw_upsizer ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + // Slave interface + .slv_req_i (slv_req_i ), + .slv_resp_o(slv_resp_o), + // Master interface + .mst_req_o (mst_req_o ), + .mst_resp_i(mst_resp_i) + ); + end : gen_dw_upsize + + if (AxiMstPortDataWidth < AxiSlvPortDataWidth) begin: gen_dw_downsize + axi_dw_downsizer #( + .AxiMaxReads (AxiMaxReads ), + .AxiSlvPortDataWidth(AxiSlvPortDataWidth), + .AxiMstPortDataWidth(AxiMstPortDataWidth), + .AxiAddrWidth (AxiAddrWidth ), + .AxiIdWidth (AxiIdWidth ), + .aw_chan_t (aw_chan_t ), + .mst_w_chan_t (mst_w_chan_t ), + .slv_w_chan_t (slv_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .mst_r_chan_t (mst_r_chan_t ), + .slv_r_chan_t (slv_r_chan_t ), + .axi_mst_req_t (axi_mst_req_t ), + .axi_mst_resp_t (axi_mst_resp_t ), + .axi_slv_req_t (axi_slv_req_t ), + .axi_slv_resp_t (axi_slv_resp_t ) + ) i_axi_dw_downsizer ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + // Slave interface + .slv_req_i (slv_req_i ), + .slv_resp_o(slv_resp_o), + // Master interface + .mst_req_o (mst_req_o ), + .mst_resp_i(mst_resp_i) + ); + end : gen_dw_downsize + +endmodule : axi_dw_converter + +// Interface wrapper + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module axi_dw_converter_intf #( + parameter int unsigned AXI_ID_WIDTH = 1, + parameter int unsigned AXI_ADDR_WIDTH = 1, + parameter int unsigned AXI_SLV_PORT_DATA_WIDTH = 8, + parameter int unsigned AXI_MST_PORT_DATA_WIDTH = 8, + parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned AXI_MAX_READS = 8 + ) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv, + AXI_BUS.Master mst + ); + + typedef logic [AXI_ID_WIDTH-1:0] id_t ; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t ; + typedef logic [AXI_MST_PORT_DATA_WIDTH-1:0] mst_data_t ; + typedef logic [AXI_MST_PORT_DATA_WIDTH/8-1:0] mst_strb_t; + typedef logic [AXI_SLV_PORT_DATA_WIDTH-1:0] slv_data_t ; + typedef logic [AXI_SLV_PORT_DATA_WIDTH/8-1:0] slv_strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t ; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, mst_data_t, mst_strb_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, slv_data_t, slv_strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, mst_data_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, slv_data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_t, mst_w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_t, slv_w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_t, slv_r_chan_t) + + slv_req_t slv_req; + slv_resp_t slv_resp; + mst_req_t mst_req; + mst_resp_t mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_dw_converter #( + .AxiMaxReads ( AXI_MAX_READS ), + .AxiSlvPortDataWidth( AXI_SLV_PORT_DATA_WIDTH ), + .AxiMstPortDataWidth( AXI_MST_PORT_DATA_WIDTH ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiIdWidth ( AXI_ID_WIDTH ), + .aw_chan_t ( aw_chan_t ), + .mst_w_chan_t ( mst_w_chan_t ), + .slv_w_chan_t ( slv_w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .axi_mst_req_t ( mst_req_t ), + .axi_mst_resp_t ( mst_resp_t ), + .axi_slv_req_t ( slv_req_t ), + .axi_slv_resp_t ( slv_resp_t ) + ) i_axi_dw_converter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + // slave port + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + // master port + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + +endmodule : axi_dw_converter_intf diff --git a/hw/deps/axi/src/axi_dw_downsizer.sv b/hw/deps/axi/src/axi_dw_downsizer.sv new file mode 100644 index 0000000..dee4ba3 --- /dev/null +++ b/hw/deps/axi/src/axi_dw_downsizer.sv @@ -0,0 +1,767 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Matheus Cavalcante + +// Description: +// Data width downsize conversion. +// Connects a wide master to a narrower slave. + +// NOTE: The downsizer does not support WRAP and FIXED bursts, and +// will answer with SLVERR upon receiving a burst of such types. + +module axi_dw_downsizer #( + parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads + parameter int unsigned AxiSlvPortDataWidth = 8 , // Data width of the slv port + parameter int unsigned AxiMstPortDataWidth = 8 , // Data width of the mst port + parameter int unsigned AxiAddrWidth = 1 , // Address width + parameter int unsigned AxiIdWidth = 1 , // ID width + parameter type aw_chan_t = logic, // AW Channel Type + parameter type mst_w_chan_t = logic, // W Channel Type for mst port + parameter type slv_w_chan_t = logic, // W Channel Type for slv port + parameter type b_chan_t = logic, // B Channel Type + parameter type ar_chan_t = logic, // AR Channel Type + parameter type mst_r_chan_t = logic, // R Channel Type for mst port + parameter type slv_r_chan_t = logic, // R Channel Type for slv port + parameter type axi_mst_req_t = logic, // AXI Request Type for mst ports + parameter type axi_mst_resp_t = logic, // AXI Response Type for mst ports + parameter type axi_slv_req_t = logic, // AXI Request Type for slv ports + parameter type axi_slv_resp_t = logic // AXI Response Type for slv ports + ) ( + input logic clk_i, + input logic rst_ni, + // Slave interface + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + // Master interface + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i + ); + + /***************** + * DEFINITIONS * + *****************/ + import axi_pkg::aligned_addr; + + // Type used to index which adapter is handling each outstanding transaction. + localparam TranIdWidth = AxiMaxReads > 1 ? $clog2(AxiMaxReads) : 1; + typedef logic [TranIdWidth-1:0] tran_id_t; + + // Data width + localparam AxiSlvPortStrbWidth = AxiSlvPortDataWidth / 8; + localparam AxiMstPortStrbWidth = AxiMstPortDataWidth / 8; + + localparam AxiSlvPortMaxSize = $clog2(AxiSlvPortStrbWidth); + localparam AxiMstPortMaxSize = $clog2(AxiMstPortStrbWidth); + + localparam SlvPortByteMask = AxiSlvPortStrbWidth - 1; + localparam MstPortByteMask = AxiMstPortStrbWidth - 1; + + // Address width + typedef logic [AxiAddrWidth-1:0] addr_t; + + // ID width + typedef logic [AxiIdWidth-1:0] id_t; + + // Length of burst after upsizing + typedef logic [$clog2(AxiSlvPortStrbWidth/AxiMstPortStrbWidth) + 7:0] burst_len_t; + + // Internal AXI bus + axi_mst_req_t mst_req; + axi_mst_resp_t mst_resp; + + /************** + * ARBITERS * + **************/ + + // R + + slv_r_chan_t [AxiMaxReads-1:0] slv_r_tran; + logic [AxiMaxReads-1:0] slv_r_valid_tran; + logic [AxiMaxReads-1:0] slv_r_ready_tran; + + rr_arb_tree #( + .NumIn (AxiMaxReads ), + .DataType (slv_r_chan_t), + .AxiVldRdy(1'b1 ), + .ExtPrio (1'b0 ), + .LockIn (1'b1 ) + ) i_slv_r_arb ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + .rr_i ('0 ), + .req_i (slv_r_valid_tran ), + .gnt_o (slv_r_ready_tran ), + .data_i (slv_r_tran ), + .gnt_i (slv_req_i.r_ready ), + .req_o (slv_resp_o.r_valid), + .data_o (slv_resp_o.r ), + .idx_o (/* Unused */ ) + ); + + logic [AxiMaxReads-1:0] mst_r_ready_tran; + assign mst_req.r_ready = |mst_r_ready_tran; + + // AR + + id_t arb_slv_ar_id; + logic arb_slv_ar_req; + logic arb_slv_ar_gnt; + logic [AxiMaxReads-1:0] arb_slv_ar_gnt_tran; + // Multiplex AR slave between AR and AW for the injection of atomic operations with an R response. + logic inject_aw_into_ar; + logic inject_aw_into_ar_req; + logic inject_aw_into_ar_gnt; + + assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; + + rr_arb_tree #( + .NumIn (2 ), + .DataWidth (AxiIdWidth), + .ExtPrio (1'b0 ), + .AxiVldRdy (1'b1 ), + .LockIn (1'b0 ) + ) i_slv_ar_arb ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i (1'b0 ), + .rr_i ('0 ), + .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid} ), + .gnt_o ({inject_aw_into_ar_gnt, slv_resp_o.ar_ready}), + .data_i ({slv_req_i.aw.id, slv_req_i.ar.id} ), + .req_o (arb_slv_ar_req ), + .gnt_i (arb_slv_ar_gnt ), + .data_o (arb_slv_ar_id ), + .idx_o (inject_aw_into_ar ) + ); + + ar_chan_t [AxiMaxReads-1:0] mst_ar_tran; + id_t [AxiMaxReads-1:0] mst_ar_id; + logic [AxiMaxReads-1:0] mst_ar_valid_tran; + logic [AxiMaxReads-1:0] mst_ar_ready_tran; + tran_id_t mst_req_idx; + + rr_arb_tree #( + .NumIn (AxiMaxReads), + .DataType (ar_chan_t ), + .AxiVldRdy(1'b1 ), + .ExtPrio (1'b0 ), + .LockIn (1'b1 ) + ) i_mst_ar_arb ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + .rr_i ('0 ), + .req_i (mst_ar_valid_tran), + .gnt_o (mst_ar_ready_tran), + .data_i (mst_ar_tran ), + .gnt_i (mst_resp.ar_ready), + .req_o (mst_req.ar_valid ), + .data_o (mst_req.ar ), + .idx_o (mst_req_idx ) + ); + + /***************** + * ERROR SLAVE * + *****************/ + + axi_mst_req_t axi_err_req; + axi_mst_resp_t axi_err_resp; + + axi_err_slv #( + .AxiIdWidth(AxiIdWidth ), + .Resp (axi_pkg::RESP_SLVERR), + .req_t (axi_mst_req_t ), + .resp_t (axi_mst_resp_t ) + ) i_axi_err_slv ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .slv_req_i (axi_err_req ), + .slv_resp_o(axi_err_resp) + ); + + /*********** + * DEMUX * + ***********/ + + // Requests can be sent either to the error slave, + // or to the DWC's master port. + + logic [AxiMaxReads-1:0] mst_req_ar_err; + logic mst_req_aw_err; + + axi_demux #( + .AxiIdWidth (AxiIdWidth ), + .AxiLookBits(AxiIdWidth ), + .aw_chan_t (aw_chan_t ), + .w_chan_t (mst_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .r_chan_t (mst_r_chan_t ), + .req_t (axi_mst_req_t ), + .resp_t (axi_mst_resp_t), + .NoMstPorts (2 ), + .MaxTrans (AxiMaxReads ), + .SpillAw (1'b1 ) // Required to break dependency between AW and W channels + ) i_axi_demux ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .mst_reqs_o ({axi_err_req, mst_req_o} ), + .mst_resps_i ({axi_err_resp, mst_resp_i} ), + .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), + .slv_aw_select_i(mst_req_aw_err ), + .slv_req_i (mst_req ), + .slv_resp_o (mst_resp ) + ); + + /********** + * READ * + **********/ + + typedef enum logic [1:0] { + R_IDLE , + R_PASSTHROUGH , + R_INCR_DOWNSIZE, + R_SPLIT_INCR_DOWNSIZE + } r_state_e; + + typedef struct packed { + ar_chan_t ar ; + logic ar_valid ; + logic ar_throw_error ; + slv_r_chan_t r ; + logic r_valid ; + burst_len_t burst_len ; + axi_pkg::size_t orig_ar_size; + } r_req_t; + + // Decide which downsizer will handle the incoming AXI transaction + logic [AxiMaxReads-1:0] idle_read_downsizer; + tran_id_t idx_ar_downsizer; + + // Find an idle downsizer to handle this transaction + tran_id_t idx_idle_downsizer; + lzc #( + .WIDTH(AxiMaxReads) + ) i_idle_lzc ( + .in_i (idle_read_downsizer), + .cnt_o (idx_idle_downsizer ), + .empty_o(/* Unused */ ) + ); + + // Is there already another downsizer handling a transaction with the same id + logic [AxiMaxReads-1:0] id_clash_downsizer; + tran_id_t idx_id_clash_downsizer; + for (genvar t = 0; t < AxiMaxReads; t++) begin: gen_id_clash + assign id_clash_downsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_downsizer[t]; + end + + onehot_to_bin #( + .ONEHOT_WIDTH(AxiMaxReads) + ) i_id_clash_onehot_to_bin ( + .onehot(id_clash_downsizer ), + .bin (idx_id_clash_downsizer) + ); + + // Choose an idle downsizer, unless there is an id clash + assign idx_ar_downsizer = (|id_clash_downsizer) ? idx_id_clash_downsizer : idx_idle_downsizer; + + // This ID queue is used to resolve which downsizer is handling + // each outstanding read transaction. + + logic [AxiMaxReads-1:0] idqueue_push; + logic [AxiMaxReads-1:0] idqueue_pop; + tran_id_t idqueue_id; + logic idqueue_valid; + + id_queue #( + .ID_WIDTH(AxiIdWidth ), + .CAPACITY(AxiMaxReads), + .data_t (tran_id_t ) + ) i_read_id_queue ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .inp_id_i (arb_slv_ar_id ), + .inp_data_i (idx_ar_downsizer), + .inp_req_i (|idqueue_push ), + .inp_gnt_o (/* Unused */ ), + .oup_id_i (mst_resp.r.id ), + .oup_pop_i (|idqueue_pop ), + .oup_req_i (1'b1 ), + .oup_data_o (idqueue_id ), + .oup_data_valid_o(idqueue_valid ), + .oup_gnt_o (/* Unused */ ), + .exists_data_i ('0 ), + .exists_mask_i ('0 ), + .exists_req_i ('0 ), + .exists_o (/* Unused */ ), + .exists_gnt_o (/* Unused */ ) + ); + + for (genvar t = 0; unsigned'(t) < AxiMaxReads; t++) begin: gen_read_downsizer + r_state_e r_state_d, r_state_q; + r_req_t r_req_d , r_req_q ; + + // Are we idle? + assign idle_read_downsizer[t] = (r_state_q == R_IDLE); + + always_comb begin + // Maintain state + r_state_d = r_state_q; + r_req_d = r_req_q ; + + // AR Channel + mst_ar_tran[t] = r_req_q.ar ; + mst_ar_id[t] = r_req_q.ar.id ; + mst_ar_valid_tran[t] = r_req_q.ar_valid; + + // Throw an error + mst_req_ar_err[t] = r_req_q.ar_throw_error; + + // R Channel + slv_r_tran[t] = r_req_q.r ; + slv_r_valid_tran[t] = r_req_q.r_valid; + + idqueue_push[t] = '0; + idqueue_pop[t] = '0; + + arb_slv_ar_gnt_tran[t] = 1'b0; + + mst_r_ready_tran[t] = 1'b0; + + // Got a grant on the AR channel + if (mst_ar_valid_tran[t] && mst_ar_ready_tran[t]) begin + r_req_d.ar_valid = 1'b0; + r_req_d.ar_throw_error = 1'b0; + end + + case (r_state_q) + R_IDLE : begin + // Reset channels + r_req_d.ar = '0; + r_req_d.r = '0; + + // New read request + if (arb_slv_ar_req && (idx_ar_downsizer == t)) begin + arb_slv_ar_gnt_tran[t] = 1'b1; + // Push to ID queue + idqueue_push[t] = 1'b1; + + // Default state + r_state_d = R_PASSTHROUGH; + + // Save beat + r_req_d.ar = slv_req_i.ar ; + r_req_d.ar_valid = 1'b1 ; + r_req_d.burst_len = slv_req_i.ar.len ; + r_req_d.orig_ar_size = slv_req_i.ar.size; + if (inject_aw_into_ar) begin + r_req_d.ar.id = slv_req_i.aw.id ; + r_req_d.ar.addr = slv_req_i.aw.addr ; + r_req_d.ar.size = slv_req_i.aw.size ; + r_req_d.ar.burst = slv_req_i.aw.burst ; + r_req_d.ar.len = slv_req_i.aw.len ; + r_req_d.ar.lock = slv_req_i.aw.lock ; + r_req_d.ar.cache = slv_req_i.aw.cache ; + r_req_d.ar.prot = slv_req_i.aw.prot ; + r_req_d.ar.qos = slv_req_i.aw.qos ; + r_req_d.ar.region = slv_req_i.aw.region; + r_req_d.ar.user = slv_req_i.aw.user ; + r_req_d.ar_valid = 1'b0 ; // Injected "AR"s from AW are not valid. + r_req_d.burst_len = slv_req_i.aw.len ; + r_req_d.orig_ar_size = slv_req_i.aw.size ; + end + + case (r_req_d.ar.burst) + axi_pkg::BURST_INCR : begin + // Modifiable transaction + if (|(r_req_d.ar.cache & axi_pkg::CACHE_MODIFIABLE)) begin + // Evaluate downsize ratio + automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ; + automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth; + + // Evaluate output burst length + automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth; + r_req_d.burst_len = (r_req_d.ar.len + 1) * conv_ratio - align_adj - 1 ; + + if (conv_ratio != 1) begin + r_req_d.ar.size = AxiMstPortMaxSize; + + if (r_req_d.burst_len <= 255) begin + r_state_d = R_INCR_DOWNSIZE ; + r_req_d.ar.len = r_req_d.burst_len; + end else begin + r_state_d = R_SPLIT_INCR_DOWNSIZE; + r_req_d.ar.len = 255 - align_adj ; + end + end + // Non-modifiable transaction + end else begin + // Incoming transaction is wider than the master bus + if (r_req_d.ar.size > AxiMstPortMaxSize) begin + r_req_d.ar_throw_error = 1'b1 ; + r_state_d = R_PASSTHROUGH; + end + end + end + + axi_pkg::BURST_WRAP: begin + // The DW converter does not support this kind of burst ... + r_state_d = R_PASSTHROUGH; + r_req_d.ar_throw_error = 1'b1 ; + + // ... but might if this is a narrow single-beat transaction + if (r_req_d.ar.len == '0 && r_req_d.ar.size <= AxiMstPortMaxSize) + r_req_d.ar_throw_error = 1'b0; + end + + axi_pkg::BURST_FIXED: begin + // The DW converter does not support this kind of burst ... + r_state_d = R_PASSTHROUGH; + r_req_d.ar_throw_error = 1'b1 ; + + // ... but might if this is a narrow single-beat transaction + if (r_req_d.ar.len == '0 && r_req_d.ar.size <= AxiMstPortMaxSize) + r_req_d.ar_throw_error = 1'b0; + end + endcase + end + end + + R_PASSTHROUGH, R_INCR_DOWNSIZE, R_SPLIT_INCR_DOWNSIZE: begin + // Got a grant on the R channel + if (slv_r_valid_tran[t] && slv_r_ready_tran[t]) begin + r_req_d.r = '0 ; + r_req_d.r_valid = 1'b0; + end + + // Request was accepted + if (!r_req_q.ar_valid) + // Our turn + if ((idqueue_id == t) && idqueue_valid) + // Ready to accept more data + if (!slv_r_valid_tran[t] || (slv_r_valid_tran[t] && slv_r_ready_tran[t])) begin + mst_r_ready_tran[t] = 1'b1; + + if (mst_resp.r_valid) begin + automatic addr_t mst_port_offset = r_req_q.ar.addr[(AxiMstPortStrbWidth == 1 ? 1 : $clog2(AxiMstPortStrbWidth)) - 1:0]; + automatic addr_t slv_port_offset = r_req_q.ar.addr[(AxiSlvPortStrbWidth == 1 ? 1 : $clog2(AxiSlvPortStrbWidth)) - 1:0]; + + // Serialization + for (int b = 0; b < AxiSlvPortStrbWidth; b++) + if ((b >= slv_port_offset) && + (b - slv_port_offset < (1 << r_req_q.orig_ar_size)) && + (b + mst_port_offset - slv_port_offset < AxiMstPortStrbWidth)) begin + r_req_d.r.data[8*b +: 8] = mst_resp.r.data[8*(b + mst_port_offset - slv_port_offset) +: 8]; + end + + r_req_d.burst_len = r_req_q.burst_len - 1 ; + r_req_d.ar.len = r_req_q.ar.len - 1 ; + r_req_d.ar.addr = aligned_addr(r_req_q.ar.addr, r_req_q.ar.size) + (1 << r_req_q.ar.size); + r_req_d.r.last = (r_req_q.burst_len == 0) ; + r_req_d.r.id = mst_resp.r.id ; + r_req_d.r.resp = mst_resp.r.resp ; + r_req_d.r.user = mst_resp.r.user ; + + if (r_req_q.burst_len == 0) + idqueue_pop[t] = 1'b1; + + case (r_state_q) + R_PASSTHROUGH : + // Forward data as soon as we can + r_req_d.r_valid = 1'b1; + + R_INCR_DOWNSIZE, R_SPLIT_INCR_DOWNSIZE: + // Forward when the burst is finished, or after filling up a word + if (r_req_q.burst_len == 0 || (aligned_addr(r_req_d.ar.addr, r_req_q.orig_ar_size) != aligned_addr(r_req_q.ar.addr, r_req_q.orig_ar_size))) + r_req_d.r_valid = 1'b1; + endcase + + // Trigger another burst request, if needed + if (r_state_q == R_SPLIT_INCR_DOWNSIZE) + // Finished current burst, but whole transaction hasn't finished + if (r_req_q.ar.len == '0 && r_req_q.burst_len != '0) begin + r_req_d.ar_valid = 1'b1; + r_req_d.ar.len = (r_req_d.burst_len <= 255) ? r_req_d.burst_len : 255; + end + end + end + + if (slv_r_valid_tran[t] && slv_r_ready_tran[t]) + if (r_req_q.burst_len == '1) + r_state_d = R_IDLE; + end + endcase + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + r_state_q <= R_IDLE; + r_req_q <= '0 ; + end else begin + r_state_q <= r_state_d; + r_req_q <= r_req_d ; + end + end + end : gen_read_downsizer + + /*********** + * WRITE * + ***********/ + typedef enum logic [1:0] { + W_IDLE , + W_PASSTHROUGH , + W_INCR_DOWNSIZE, + W_SPLIT_INCR_DOWNSIZE + } w_state_e; + + typedef struct packed { + aw_chan_t aw ; + logic aw_valid ; + logic aw_throw_error ; + burst_len_t burst_len ; + axi_pkg::size_t orig_aw_size; + } w_req_t; + + w_state_e w_state_d, w_state_q; + w_req_t w_req_d, w_req_q; + + // This FIFO holds the number of bursts generated by each write transactions handled by this downsizer. + // This is used to forward only the correct B beats to the slave. + logic forward_b_beat_i; + logic forward_b_beat_o; + logic forward_b_beat_push; + logic forward_b_beat_pop; + logic forward_b_beat_full; + + fifo_v3 #( + .DATA_WIDTH (1 ), + .DEPTH (AxiMaxReads), + .FALL_THROUGH(1'b1 ) + ) i_forward_b_beats_queue ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i (1'b0 ), + .testmode_i(1'b0 ), + .data_i (forward_b_beat_i ), + .push_i (forward_b_beat_push ), + .full_o (forward_b_beat_full ), + .data_o (forward_b_beat_o ), + .pop_i (forward_b_beat_pop ), + .empty_o (/* Unused */ ), + .usage_o (/* Unused */ ) + ); + + always_comb begin + inject_aw_into_ar_req = 1'b0; + + // i_num_b_beats default state + forward_b_beat_i = '0 ; + forward_b_beat_push = 1'b0; + forward_b_beat_pop = 1'b0; + + // Maintain state + w_state_d = w_state_q; + w_req_d = w_req_q ; + + // AW Channel + mst_req.aw = w_req_q.aw ; + mst_req.aw_valid = w_req_q.aw_valid; + slv_resp_o.aw_ready = '0 ; + + // Throw an error. + mst_req_aw_err = w_req_q.aw_throw_error; + + // W Channel + mst_req.w = '0; + mst_req.w_valid = '0; + slv_resp_o.w_ready = '0; + + // B Channel (No latency) + slv_resp_o.b = mst_resp.b; + + // Each write transaction might trigger several B beats on the master (narrow) side. + // Only forward the last B beat of each transaction. + if (forward_b_beat_o) begin + slv_resp_o.b_valid = mst_resp.b_valid ; + mst_req.b_ready = slv_req_i.b_ready; + + // Got an ack on the B channel. Pop transaction. + if (mst_req.b_ready && mst_resp.b_valid) + forward_b_beat_pop = 1'b1; + end else begin + // Otherwise, just acknowlegde the B beats + slv_resp_o.b_valid = 1'b0 ; + mst_req.b_ready = 1'b1 ; + forward_b_beat_pop = mst_resp.b_valid; + end + + // Got a grant on the AW channel + if (mst_req.aw_valid & mst_resp.aw_ready) begin + w_req_d.aw_valid = 1'b0; + w_req_d.aw_throw_error = 1'b0; + end + + case (w_state_q) + W_PASSTHROUGH, W_INCR_DOWNSIZE, W_SPLIT_INCR_DOWNSIZE: begin + // Request was accepted + if (!w_req_q.aw_valid) + if (slv_req_i.w_valid) begin + automatic addr_t mst_port_offset = w_req_q.aw.addr[(AxiMstPortStrbWidth == 1 ? 1 : $clog2(AxiMstPortStrbWidth)) - 1:0]; + automatic addr_t slv_port_offset = w_req_q.aw.addr[(AxiSlvPortStrbWidth == 1 ? 1 : $clog2(AxiSlvPortStrbWidth)) - 1:0]; + + // Valid output + mst_req.w_valid = 1'b1 ; + mst_req.w.last = w_req_q.aw.len == 0; + mst_req.w.user = slv_req_i.w.user ; + + // Lane steering + for (int b = 0; b < AxiSlvPortStrbWidth; b++) + if ((b >= slv_port_offset) && + (b - slv_port_offset < (1 << w_req_q.orig_aw_size)) && + (b + mst_port_offset - slv_port_offset < AxiMstPortStrbWidth)) begin + mst_req.w.data[8*(b + mst_port_offset - slv_port_offset) +: 8] = slv_req_i.w.data[8*b +: 8]; + mst_req.w.strb[b + mst_port_offset - slv_port_offset] = slv_req_i.w.strb[b] ; + end + end + + // Acknowledgment + if (mst_resp.w_ready && mst_req.w_valid) begin + w_req_d.burst_len = w_req_q.burst_len - 1 ; + w_req_d.aw.len = w_req_q.aw.len - 1 ; + w_req_d.aw.addr = aligned_addr(w_req_q.aw.addr, w_req_q.aw.size) + (1 << w_req_q.aw.size); + + case (w_state_q) + W_PASSTHROUGH: + slv_resp_o.w_ready = 1'b1; + + W_INCR_DOWNSIZE, W_SPLIT_INCR_DOWNSIZE: + if (w_req_q.burst_len == 0 || (aligned_addr(w_req_d.aw.addr, w_req_q.orig_aw_size) != aligned_addr(w_req_q.aw.addr, w_req_q.orig_aw_size))) + slv_resp_o.w_ready = 1'b1; + endcase + + // Trigger another burst request, if needed + if (w_state_q == W_SPLIT_INCR_DOWNSIZE) + // Finished current burst, but whole transaction hasn't finished + if (w_req_q.aw.len == '0 && w_req_q.burst_len != '0 && !forward_b_beat_full) begin + w_req_d.aw_valid = 1'b1; + w_req_d.aw.len = (w_req_d.burst_len <= 255) ? w_req_d.burst_len : 255; + + // We will receive an extraneous B beat. Ignore it. + forward_b_beat_i = 1'b0; + forward_b_beat_push = 1'b1; + end + + if (w_req_q.burst_len == 0 && !forward_b_beat_full) begin + w_state_d = W_IDLE; + + forward_b_beat_push = 1'b1; + forward_b_beat_i = 1'b1; + end + end + end + endcase + + // Can start a new request as soon as w_state_d is W_IDLE + if (w_state_d == W_IDLE) begin + // Reset channels + w_req_d.aw = '0 ; + w_req_d.aw_valid = 1'b0; + w_req_d.aw_throw_error = 1'b0; + + if (slv_req_i.aw_valid && slv_req_i.aw.atop[5]) begin // ATOP with an R response + inject_aw_into_ar_req = 1'b1 ; + slv_resp_o.aw_ready = inject_aw_into_ar_gnt; + end else begin // Regular AW + slv_resp_o.aw_ready = 1'b1; + end + + // New write request + if (slv_req_i.aw_valid && slv_resp_o.aw_ready && !forward_b_beat_full) begin + // Default state + w_state_d = W_PASSTHROUGH; + + // Save beat + w_req_d.aw = slv_req_i.aw ; + w_req_d.aw_valid = 1'b1 ; + w_req_d.burst_len = slv_req_i.aw.len ; + w_req_d.orig_aw_size = slv_req_i.aw.size; + + case (slv_req_i.aw.burst) + axi_pkg::BURST_INCR: begin + // Modifiable transaction + if (|(slv_req_i.aw.cache & axi_pkg::CACHE_MODIFIABLE)) begin + // Evaluate downsize ratio + automatic addr_t size_mask = (1 << slv_req_i.aw.size) - 1 ; + automatic addr_t conv_ratio = ((1 << slv_req_i.aw.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth; + + // Evaluate output burst length + automatic addr_t align_adj = (slv_req_i.aw.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth; + w_req_d.burst_len = (slv_req_i.aw.len + 1) * conv_ratio - align_adj - 1 ; + + if (conv_ratio != 1) begin + w_req_d.aw.size = AxiMstPortMaxSize; + + if (w_req_d.burst_len <= 255) begin + w_state_d = W_INCR_DOWNSIZE ; + w_req_d.aw.len = w_req_d.burst_len; + end else begin + w_state_d = W_SPLIT_INCR_DOWNSIZE; + w_req_d.aw.len = 255 - align_adj ; + end + end + // Non-modifiable transaction. + end else begin + // Incoming transaction is wider than the master bus. + if (slv_req_i.aw.size > AxiMstPortMaxSize) begin + w_state_d = W_PASSTHROUGH; + w_req_d.aw_throw_error = 1'b1 ; + end + end + end + + axi_pkg::BURST_WRAP: begin + // The DW converter does not support this kind of burst ... + w_state_d = W_PASSTHROUGH; + w_req_d.aw_throw_error = 1'b1 ; + + // ... but might if this is a narrow single-beat transaction + if (slv_req_i.aw.size <= AxiSlvPortMaxSize && slv_req_i.aw.len == '0) + w_req_d.aw_throw_error = 1'b0; + end + + axi_pkg::BURST_FIXED: begin + // The DW converter does not support this kind of burst ... + w_state_d = W_PASSTHROUGH; + w_req_d.aw_throw_error = 1'b1 ; + + // ... but might if this is a narrow single-beat transaction + if (slv_req_i.aw.size <= AxiSlvPortMaxSize && slv_req_i.aw.len == '0) + w_req_d.aw_throw_error = 1'b0; + end + endcase + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + w_state_q <= W_IDLE; + w_req_q <= '0 ; + end else begin + w_state_q <= w_state_d; + w_req_q <= w_req_d ; + end + end + +endmodule : axi_dw_downsizer diff --git a/hw/deps/axi/src/axi_dw_upsizer.sv b/hw/deps/axi/src/axi_dw_upsizer.sv new file mode 100644 index 0000000..08766cc --- /dev/null +++ b/hw/deps/axi/src/axi_dw_upsizer.sv @@ -0,0 +1,645 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Matheus Cavalcante + +// Description: +// Data width upsize conversion. +// Connects a narrow master to a wider slave. + +// NOTE: The upsizer does not support WRAP and FIXED bursts, and +// will answer with SLVERR upon receiving a burst of such types. + +module axi_dw_upsizer #( + parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads + parameter int unsigned AxiSlvPortDataWidth = 8 , // Data width of the slv port + parameter int unsigned AxiMstPortDataWidth = 8 , // Data width of the mst port + parameter int unsigned AxiAddrWidth = 1 , // Address width + parameter int unsigned AxiIdWidth = 1 , // ID width + parameter type aw_chan_t = logic, // AW Channel Type + parameter type mst_w_chan_t = logic, // W Channel Type for mst port + parameter type slv_w_chan_t = logic, // W Channel Type for slv port + parameter type b_chan_t = logic, // B Channel Type + parameter type ar_chan_t = logic, // AR Channel Type + parameter type mst_r_chan_t = logic, // R Channel Type for mst port + parameter type slv_r_chan_t = logic, // R Channel Type for slv port + parameter type axi_mst_req_t = logic, // AXI Request Type for mst ports + parameter type axi_mst_resp_t = logic, // AXI Response Type for mst ports + parameter type axi_slv_req_t = logic, // AXI Request Type for slv ports + parameter type axi_slv_resp_t = logic // AXI Response Type for slv ports + ) ( + input logic clk_i, + input logic rst_ni, + // Slave interface + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + // Master interface + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i + ); + + /***************** + * DEFINITIONS * + *****************/ + import axi_pkg::aligned_addr; + import axi_pkg::beat_addr ; + + // Type used to index which adapter is handling each outstanding transaction. + localparam TranIdWidth = AxiMaxReads > 1 ? $clog2(AxiMaxReads) : 1; + typedef logic [TranIdWidth-1:0] tran_id_t; + + // Data width + localparam AxiSlvPortStrbWidth = AxiSlvPortDataWidth / 8; + localparam AxiMstPortStrbWidth = AxiMstPortDataWidth / 8; + + localparam AxiSlvPortMaxSize = $clog2(AxiSlvPortStrbWidth); + localparam AxiMstPortMaxSize = $clog2(AxiMstPortStrbWidth); + + // Address width + typedef logic [AxiAddrWidth-1:0] addr_t; + + // ID width + typedef logic [AxiIdWidth-1:0] id_t; + + // Length of burst after upsizing + typedef logic [$clog2(AxiMstPortStrbWidth/AxiSlvPortStrbWidth) + 7:0] burst_len_t; + + // Internal AXI bus + axi_mst_req_t mst_req; + axi_mst_resp_t mst_resp; + + /************** + * ARBITERS * + **************/ + + // R + + slv_r_chan_t [AxiMaxReads-1:0] slv_r_tran; + logic [AxiMaxReads-1:0] slv_r_valid_tran; + logic [AxiMaxReads-1:0] slv_r_ready_tran; + + rr_arb_tree #( + .NumIn (AxiMaxReads ), + .DataType (slv_r_chan_t), + .AxiVldRdy(1'b1 ), + .ExtPrio (1'b0 ), + .LockIn (1'b1 ) + ) i_slv_r_arb ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + .rr_i ('0 ), + .req_i (slv_r_valid_tran ), + .gnt_o (slv_r_ready_tran ), + .data_i (slv_r_tran ), + .gnt_i (slv_req_i.r_ready ), + .req_o (slv_resp_o.r_valid), + .data_o (slv_resp_o.r ), + .idx_o (/* Unused */ ) + ); + + logic [AxiMaxReads-1:0] mst_r_ready_tran; + assign mst_req.r_ready = |mst_r_ready_tran; + + // AR + + id_t arb_slv_ar_id; + logic arb_slv_ar_req; + logic arb_slv_ar_gnt; + logic [AxiMaxReads-1:0] arb_slv_ar_gnt_tran; + // Multiplex AR slave between AR and AW for the injection of atomic operations with an R response. + logic inject_aw_into_ar; + logic inject_aw_into_ar_req; + logic inject_aw_into_ar_gnt; + + assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; + + rr_arb_tree #( + .NumIn (2 ), + .DataWidth (AxiIdWidth), + .ExtPrio (1'b0 ), + .AxiVldRdy (1'b1 ), + .LockIn (1'b0 ) + ) i_slv_ar_arb ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + .rr_i ('0 ), + .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid} ), + .gnt_o ({inject_aw_into_ar_gnt, slv_resp_o.ar_ready}), + .data_i ({slv_req_i.aw.id, slv_req_i.ar.id} ), + .req_o (arb_slv_ar_req ), + .gnt_i (arb_slv_ar_gnt ), + .data_o (arb_slv_ar_id ), + .idx_o (inject_aw_into_ar ) + ); + + ar_chan_t [AxiMaxReads-1:0] mst_ar_tran; + id_t [AxiMaxReads-1:0] mst_ar_id; + logic [AxiMaxReads-1:0] mst_ar_valid_tran; + logic [AxiMaxReads-1:0] mst_ar_ready_tran; + tran_id_t mst_req_idx; + + rr_arb_tree #( + .NumIn (AxiMaxReads), + .DataType (ar_chan_t ), + .AxiVldRdy(1'b1 ), + .ExtPrio (1'b0 ), + .LockIn (1'b1 ) + ) i_mst_ar_arb ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + .rr_i ('0 ), + .req_i (mst_ar_valid_tran), + .gnt_o (mst_ar_ready_tran), + .data_i (mst_ar_tran ), + .gnt_i (mst_resp.ar_ready), + .req_o (mst_req.ar_valid ), + .data_o (mst_req.ar ), + .idx_o (mst_req_idx ) + ); + + /***************** + * ERROR SLAVE * + *****************/ + + axi_mst_req_t axi_err_req; + axi_mst_resp_t axi_err_resp; + + axi_err_slv #( + .AxiIdWidth(AxiIdWidth ), + .Resp (axi_pkg::RESP_SLVERR), + .req_t (axi_mst_req_t ), + .resp_t (axi_mst_resp_t ) + ) i_axi_err_slv ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .slv_req_i (axi_err_req ), + .slv_resp_o(axi_err_resp) + ); + + /*********** + * DEMUX * + ***********/ + + // Requests can be sent either to the error slave, + // or to the DWC's master port. + + logic [AxiMaxReads-1:0] mst_req_ar_err; + logic mst_req_aw_err; + + axi_demux #( + .AxiIdWidth (AxiIdWidth ), + .AxiLookBits(AxiIdWidth ), + .aw_chan_t (aw_chan_t ), + .w_chan_t (mst_w_chan_t ), + .b_chan_t (b_chan_t ), + .ar_chan_t (ar_chan_t ), + .r_chan_t (mst_r_chan_t ), + .req_t (axi_mst_req_t ), + .resp_t (axi_mst_resp_t), + .NoMstPorts (2 ), + .MaxTrans (AxiMaxReads ), + .SpillAw (1'b1 ) // Required to break dependency between AW and W channels + ) i_axi_demux ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .mst_reqs_o ({axi_err_req, mst_req_o} ), + .mst_resps_i ({axi_err_resp, mst_resp_i} ), + .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), + .slv_aw_select_i(mst_req_aw_err ), + .slv_req_i (mst_req ), + .slv_resp_o (mst_resp ) + ); + + /********** + * READ * + **********/ + + typedef enum logic [1:0] { + R_IDLE , + R_PASSTHROUGH, + R_INCR_UPSIZE + } r_state_e; + + // Decide which upsizer will handle the incoming AXI transaction + logic [AxiMaxReads-1:0] idle_read_upsizer; + tran_id_t idx_ar_upsizer ; + + // Find an idle upsizer to handle this transaction + tran_id_t idx_idle_upsizer; + lzc #( + .WIDTH(AxiMaxReads) + ) i_idle_lzc ( + .in_i (idle_read_upsizer), + .cnt_o (idx_idle_upsizer ), + .empty_o(/* Unused */ ) + ); + + // Is there already another upsizer handling a transaction with the same id + logic [AxiMaxReads-1:0] id_clash_upsizer; + tran_id_t idx_id_clash_upsizer ; + for (genvar t = 0; t < AxiMaxReads; t++) begin: gen_id_clash + assign id_clash_upsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_upsizer[t]; + end + + onehot_to_bin #( + .ONEHOT_WIDTH(AxiMaxReads) + ) i_id_clash_onehot_to_bin ( + .onehot(id_clash_upsizer ), + .bin (idx_id_clash_upsizer) + ); + + // Choose an idle upsizer, unless there is an id clash + assign idx_ar_upsizer = (|id_clash_upsizer) ? idx_id_clash_upsizer : idx_idle_upsizer; + + // This logic is used to resolve which upsizer is handling + // each outstanding read transaction + + logic r_upsizer_valid; + tran_id_t idx_r_upsizer; + + logic [AxiMaxReads-1:0] rid_upsizer_match; + + // Is there a upsizer handling this transaction? + assign r_upsizer_valid = |rid_upsizer_match; + + for (genvar t = 0; t < AxiMaxReads; t++) begin: gen_rid_match + assign rid_upsizer_match[t] = (mst_resp.r.id == mst_ar_id[t]) && !idle_read_upsizer[t]; + end + + onehot_to_bin #( + .ONEHOT_WIDTH(AxiMaxReads) + ) i_rid_upsizer_lzc ( + .onehot(rid_upsizer_match), + .bin (idx_r_upsizer ) + ); + + typedef struct packed { + ar_chan_t ar ; + logic ar_valid ; + logic ar_throw_error ; + axi_pkg::len_t burst_len ; + axi_pkg::size_t orig_ar_size; + } r_req_t; + + for (genvar t = 0; unsigned'(t) < AxiMaxReads; t++) begin: gen_read_upsizer + r_state_e r_state_d, r_state_q; + r_req_t r_req_d , r_req_q ; + + // Are we idle? + assign idle_read_upsizer[t] = (r_state_q == R_IDLE); + + always_comb begin + // Maintain state + r_state_d = r_state_q; + r_req_d = r_req_q ; + + // AR Channel + mst_ar_tran[t] = r_req_q.ar ; + mst_ar_id[t] = r_req_q.ar.id ; + mst_ar_valid_tran[t] = r_req_q.ar_valid; + + // Throw an error + mst_req_ar_err[t] = r_req_q.ar_throw_error; + + // R Channel + // No latency + slv_r_tran[t] = '0 ; + slv_r_tran[t].id = mst_resp.r.id ; + slv_r_tran[t].resp = mst_resp.r.resp; + slv_r_tran[t].user = mst_resp.r.user; + + arb_slv_ar_gnt_tran[t] = 1'b0; + + mst_r_ready_tran[t] = 1'b0; + slv_r_valid_tran[t] = 1'b0; + + // Got a grant on the AR channel + if (mst_ar_valid_tran[t] && mst_ar_ready_tran[t]) begin + r_req_d.ar_valid = 1'b0; + r_req_d.ar_throw_error = 1'b0; + end + + case (r_state_q) + R_IDLE : begin + // Reset channels + r_req_d.ar = '0; + + // New read request + if (arb_slv_ar_req && (idx_ar_upsizer == t)) begin + arb_slv_ar_gnt_tran[t] = 1'b1; + + // Default state + r_state_d = R_PASSTHROUGH; + + // Save beat + r_req_d.ar = slv_req_i.ar ; + r_req_d.ar_valid = 1'b1 ; + r_req_d.burst_len = slv_req_i.ar.len ; + r_req_d.orig_ar_size = slv_req_i.ar.size; + if (inject_aw_into_ar) begin + r_req_d.ar.id = slv_req_i.aw.id ; + r_req_d.ar.addr = slv_req_i.aw.addr ; + r_req_d.ar.size = slv_req_i.aw.size ; + r_req_d.ar.burst = slv_req_i.aw.burst ; + r_req_d.ar.len = slv_req_i.aw.len ; + r_req_d.ar.lock = slv_req_i.aw.lock ; + r_req_d.ar.cache = slv_req_i.aw.cache ; + r_req_d.ar.prot = slv_req_i.aw.prot ; + r_req_d.ar.qos = slv_req_i.aw.qos ; + r_req_d.ar.region = slv_req_i.aw.region; + r_req_d.ar.user = slv_req_i.aw.user ; + r_req_d.ar_valid = 1'b0 ; // Injected "AR"s from AW are not valid. + r_req_d.burst_len = slv_req_i.aw.len ; + r_req_d.orig_ar_size = slv_req_i.aw.size ; + end + + case (r_req_d.ar.burst) + axi_pkg::BURST_INCR : begin + // Modifiable transaction + if (|(r_req_d.ar.cache & axi_pkg::CACHE_MODIFIABLE)) begin + // No need to upsize single-beat transactions. + if (r_req_d.ar.len != '0) begin + // Evaluate output burst length + automatic addr_t start_addr = aligned_addr(r_req_d.ar.addr, AxiMstPortMaxSize) ; + automatic addr_t end_addr = aligned_addr(beat_addr(r_req_d.ar.addr, r_req_d.orig_ar_size, r_req_d.burst_len), AxiMstPortMaxSize); + + r_req_d.ar.len = (end_addr - start_addr) >> AxiMstPortMaxSize; + r_req_d.ar.size = AxiMstPortMaxSize ; + r_state_d = R_INCR_UPSIZE ; + end + end + end + + axi_pkg::BURST_WRAP: begin + // The DW converter does not support this kind of burst ... + r_state_d = R_PASSTHROUGH; + r_req_d.ar_throw_error = 1'b1 ; + + // ... but might if this is a single-beat transaction + if (r_req_d.ar.len == '0) + r_req_d.ar_throw_error = 1'b0; + end + + axi_pkg::BURST_FIXED: begin + // The DW converter does not support this kind of burst ... + r_state_d = R_PASSTHROUGH; + r_req_d.ar_throw_error = 1'b1 ; + + // ... but might if this is a single-beat transaction + if (r_req_d.ar.len == '0) + r_req_d.ar_throw_error = 1'b0; + end + endcase + end + end + + R_PASSTHROUGH, R_INCR_UPSIZE: begin + // Request was accepted + if (!r_req_q.ar_valid) + if (mst_resp.r_valid && (idx_r_upsizer == t) && r_upsizer_valid) begin + automatic addr_t mst_port_offset = r_req_q.ar.addr[(AxiMstPortStrbWidth == 1 ? 1 : $clog2(AxiMstPortStrbWidth)) - 1:0]; + automatic addr_t slv_port_offset = r_req_q.ar.addr[(AxiSlvPortStrbWidth == 1 ? 1 : $clog2(AxiSlvPortStrbWidth)) - 1:0]; + + // Valid output + slv_r_valid_tran[t] = 1'b1 ; + slv_r_tran[t].last = mst_resp.r.last && (r_req_q.burst_len == 0); + + // Lane steering + for (int b = 0; b < AxiMstPortStrbWidth; b++) begin + if ((b >= mst_port_offset) && + (b - mst_port_offset < (1 << r_req_q.orig_ar_size)) && + (b + slv_port_offset - mst_port_offset < AxiSlvPortStrbWidth)) begin + slv_r_tran[t].data[8*(b + slv_port_offset - mst_port_offset) +: 8] = mst_resp.r.data[8*b +: 8]; + end + end + + // Acknowledgment + if (slv_r_ready_tran[t]) begin + r_req_d.burst_len = r_req_q.burst_len - 1 ; + r_req_d.ar.addr = aligned_addr(r_req_q.ar.addr, r_req_q.orig_ar_size) + (1 << r_req_q.orig_ar_size); + + case (r_state_q) + R_PASSTHROUGH : + mst_r_ready_tran[t] = 1'b1; + + R_INCR_UPSIZE : + if (r_req_q.burst_len == 0 || (aligned_addr(r_req_d.ar.addr, AxiMstPortMaxSize) != aligned_addr(r_req_q.ar.addr, AxiMstPortMaxSize))) + mst_r_ready_tran[t] = 1'b1; + endcase + + if (r_req_q.burst_len == '0) + r_state_d = R_IDLE; + end + end + end + endcase + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + r_state_q <= R_IDLE; + r_req_q <= '0 ; + end else begin + r_state_q <= r_state_d; + r_req_q <= r_req_d ; + end + end + end : gen_read_upsizer + + /*********** + * WRITE * + ***********/ + + typedef enum logic [1:0] { + W_IDLE , + W_PASSTHROUGH, + W_INCR_UPSIZE + } w_state_e; + + typedef struct packed { + aw_chan_t aw ; + logic aw_valid ; + logic aw_throw_error ; + mst_w_chan_t w ; + logic w_valid ; + axi_pkg::len_t burst_len ; + axi_pkg::size_t orig_aw_size; + } w_req_t; + + w_state_e w_state_d, w_state_q; + w_req_t w_req_d , w_req_q ; + + always_comb begin + inject_aw_into_ar_req = 1'b0; + + // Maintain state + w_state_d = w_state_q; + w_req_d = w_req_q ; + + // AW Channel + mst_req.aw = w_req_q.aw ; + mst_req.aw_valid = w_req_q.aw_valid; + slv_resp_o.aw_ready = '0 ; + + // Throw an error. + mst_req_aw_err = w_req_q.aw_throw_error; + + // W Channel + mst_req.w = w_req_q.w ; + mst_req.w_valid = w_req_q.w_valid; + slv_resp_o.w_ready = '0 ; + + // B Channel (No latency) + slv_resp_o.b = mst_resp.b ; + slv_resp_o.b_valid = mst_resp.b_valid ; + mst_req.b_ready = slv_req_i.b_ready; + + // Got a grant on the AW channel + if (mst_req.aw_valid && mst_resp.aw_ready) begin + w_req_d.aw_valid = 1'b0; + w_req_d.aw_throw_error = 1'b0; + end + + case (w_state_q) + W_PASSTHROUGH, W_INCR_UPSIZE: begin + // Got a grant on the W channel + if (mst_req.w_valid && mst_resp.w_ready) begin + w_req_d.w = '0 ; + w_req_d.w_valid = 1'b0; + end + + // Request was accepted + if (!w_req_q.aw_valid) begin + // Ready if downstream interface is idle, or if it is ready + slv_resp_o.w_ready = ~mst_req.w_valid || mst_resp.w_ready; + + if (slv_req_i.w_valid && slv_resp_o.w_ready) begin + automatic addr_t mst_port_offset = w_req_q.aw.addr[(AxiMstPortStrbWidth == 1 ? 1 : $clog2(AxiMstPortStrbWidth)) - 1:0]; + automatic addr_t slv_port_offset = w_req_q.aw.addr[(AxiSlvPortStrbWidth == 1 ? 1 : $clog2(AxiSlvPortStrbWidth)) - 1:0]; + + // Serialization + for (int b = 0; b < AxiMstPortStrbWidth; b++) + if ((b >= mst_port_offset) && + (b - mst_port_offset < (1 << w_req_q.orig_aw_size)) && + (b + slv_port_offset - mst_port_offset < AxiSlvPortStrbWidth)) begin + w_req_d.w.data[8*b +: 8] = slv_req_i.w.data[8*(b + slv_port_offset - mst_port_offset) +: 8]; + w_req_d.w.strb[b] = slv_req_i.w.strb[b + slv_port_offset - mst_port_offset] ; + end + + w_req_d.burst_len = w_req_q.burst_len - 1 ; + w_req_d.aw.addr = aligned_addr(w_req_q.aw.addr, w_req_q.orig_aw_size) + (1 << w_req_q.orig_aw_size); + w_req_d.w.last = (w_req_q.burst_len == 0) ; + w_req_d.w.user = slv_req_i.w.user ; + + case (w_state_q) + W_PASSTHROUGH: + // Forward data as soon as we can + w_req_d.w_valid = 1'b1; + + W_INCR_UPSIZE: + // Forward when the burst is finished, or after filling up a word + if (w_req_q.burst_len == 0 || (aligned_addr(w_req_d.aw.addr, AxiMstPortMaxSize) != aligned_addr(w_req_q.aw.addr, AxiMstPortMaxSize))) + w_req_d.w_valid = 1'b1; + endcase + end + end + + if (mst_req.w_valid && mst_resp.w_ready) + if (w_req_q.burst_len == '1) begin + slv_resp_o.w_ready = 1'b0 ; + w_state_d = W_IDLE; + end + end + endcase + + // Can start a new request as soon as w_state_d is W_IDLE + if (w_state_d == W_IDLE) begin + // Reset channels + w_req_d.aw = '0 ; + w_req_d.aw_valid = 1'b0; + w_req_d.aw_throw_error = 1'b0; + w_req_d.w = '0 ; + w_req_d.w_valid = 1'b0; + + if (slv_req_i.aw_valid && slv_req_i.aw.atop[5]) begin // ATOP with an R response + inject_aw_into_ar_req = 1'b1 ; + slv_resp_o.aw_ready = inject_aw_into_ar_gnt; + end else begin // Regular AW + slv_resp_o.aw_ready = 1'b1; + end + + // New write request + if (slv_req_i.aw_valid & slv_resp_o.aw_ready) begin + // Default state + w_state_d = W_PASSTHROUGH; + + // Save beat + w_req_d.aw = slv_req_i.aw; + w_req_d.aw_valid = 1'b1 ; + + w_req_d.burst_len = slv_req_i.aw.len ; + w_req_d.orig_aw_size = slv_req_i.aw.size; + + case (slv_req_i.aw.burst) + axi_pkg::BURST_INCR: begin + // Modifiable transaction + if (|(slv_req_i.aw.cache & axi_pkg::CACHE_MODIFIABLE)) + // No need to upsize single-beat transactions. + if (slv_req_i.aw.len != '0) begin + // Evaluate output burst length + automatic addr_t start_addr = aligned_addr(slv_req_i.aw.addr, AxiMstPortMaxSize) ; + automatic addr_t end_addr = aligned_addr(beat_addr(slv_req_i.aw.addr, slv_req_i.aw.size, slv_req_i.aw.len), AxiMstPortMaxSize); + + w_req_d.aw.len = (end_addr - start_addr) >> AxiMstPortMaxSize; + w_req_d.aw.size = AxiMstPortMaxSize ; + w_state_d = W_INCR_UPSIZE ; + end + end + + axi_pkg::BURST_WRAP: begin + // The DW converter does not support this kind of burst ... + w_state_d = W_PASSTHROUGH; + w_req_d.aw_throw_error = 1'b1 ; + + // ... but might if this is a single-beat transaction + if (slv_req_i.aw.len == '0) + w_req_d.aw_throw_error = 1'b0; + end + + axi_pkg::BURST_FIXED: begin + // The DW converter does not support this kind of burst ... + w_state_d = W_PASSTHROUGH; + w_req_d.aw_throw_error = 1'b1 ; + + // ... but might if this is a single-beat transaction + if (slv_req_i.aw.len == '0) + w_req_d.aw_throw_error = 1'b0; + end + endcase + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + w_state_q <= W_IDLE; + w_req_q <= '0 ; + end else begin + w_state_q <= w_state_d; + w_req_q <= w_req_d ; + end + end + +endmodule : axi_dw_upsizer diff --git a/hw/deps/axi/src/axi_err_slv.sv b/hw/deps/axi/src/axi_err_slv.sv new file mode 100644 index 0000000..b3a8b9c --- /dev/null +++ b/hw/deps/axi/src/axi_err_slv.sv @@ -0,0 +1,256 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +// AXI Error Slave: This module always responds with an AXI error for transactions that are sent to +// it. This module optionally supports ATOPs if the `ATOPs` parameter is set. + +module axi_err_slv #( + parameter int unsigned AxiIdWidth = 0, // AXI ID Width + parameter type req_t = logic, // AXI 4 request struct, with atop field + parameter type resp_t = logic, // AXI 4 response struct + parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this slave. + parameter int unsigned RespWidth = 32'd64, // Data response width, gets zero extended or truncated to r.data. + parameter logic [RespWidth-1:0] RespData = 64'hCA11AB1EBADCAB1E, // Hexvalue for data return value + parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this slave could ever get an atomic AXI transaction. + parameter int unsigned MaxTrans = 1 // Maximum # of accepted transactions before stalling +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable + // slave port + input req_t slv_req_i, + output resp_t slv_resp_o +); + typedef logic [AxiIdWidth-1:0] id_t; + typedef struct packed { + id_t id; + axi_pkg::len_t len; + } r_data_t; + + req_t err_req; + resp_t err_resp; + + if (ATOPs) begin + axi_atop_filter #( + .AxiIdWidth ( AxiIdWidth ), + .AxiMaxWriteTxns ( MaxTrans ), + .req_t ( req_t ), + .resp_t ( resp_t ) + ) i_atop_filter ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req_i ), + .slv_resp_o ( slv_resp_o ), + .mst_req_o ( err_req ), + .mst_resp_i ( err_resp ) + ); + end else begin + assign err_req = slv_req_i; + assign slv_resp_o = err_resp; + end + + // w fifo + logic w_fifo_full, w_fifo_empty; + logic w_fifo_push, w_fifo_pop; + id_t w_fifo_data; + // b fifo + logic b_fifo_full, b_fifo_empty; + logic b_fifo_push, b_fifo_pop; + id_t b_fifo_data; + // r fifo + r_data_t r_fifo_inp; + logic r_fifo_full, r_fifo_empty; + logic r_fifo_push, r_fifo_pop; + r_data_t r_fifo_data; + // r counter + logic r_cnt_clear, r_cnt_en, r_cnt_load; + axi_pkg::len_t r_current_beat; + // r status + logic r_busy_d, r_busy_q, r_busy_load; + + //-------------------------------------- + // Write Transactions + //-------------------------------------- + // push, when there is room in the fifo + assign w_fifo_push = err_req.aw_valid & ~w_fifo_full; + assign err_resp.aw_ready = ~w_fifo_full; + + fifo_v3 #( + .FALL_THROUGH ( 1'b1 ), + .DEPTH ( MaxTrans ), + .dtype ( id_t ) + ) i_w_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( test_i ), + .full_o ( w_fifo_full ), + .empty_o ( w_fifo_empty ), + .usage_o ( ), + .data_i ( err_req.aw.id ), + .push_i ( w_fifo_push ), + .data_o ( w_fifo_data ), + .pop_i ( w_fifo_pop ) + ); + + always_comb begin : proc_w_channel + err_resp.w_ready = 1'b0; + w_fifo_pop = 1'b0; + b_fifo_push = 1'b0; + if (!w_fifo_empty && !b_fifo_full) begin + // eat the beats + err_resp.w_ready = 1'b1; + // on the last w transaction + if (err_req.w_valid && err_req.w.last) begin + w_fifo_pop = 1'b1; + b_fifo_push = 1'b1; + end + end + end + + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .DEPTH ( unsigned'(2) ), // two placed so that w can eat beats if b is not sent + .dtype ( id_t ) + ) i_b_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( test_i ), + .full_o ( b_fifo_full ), + .empty_o ( b_fifo_empty ), + .usage_o ( ), + .data_i ( w_fifo_data ), + .push_i ( b_fifo_push ), + .data_o ( b_fifo_data ), + .pop_i ( b_fifo_pop ) + ); + + always_comb begin : proc_b_channel + b_fifo_pop = 1'b0; + err_resp.b = '0; + err_resp.b.id = b_fifo_data; + err_resp.b.resp = Resp; + err_resp.b_valid = 1'b0; + if (!b_fifo_empty) begin + err_resp.b_valid = 1'b1; + // b transaction + b_fifo_pop = err_req.b_ready; + end + end + + //-------------------------------------- + // Read Transactions + //-------------------------------------- + // push if there is room in the fifo + assign r_fifo_push = err_req.ar_valid & ~r_fifo_full; + assign err_resp.ar_ready = ~r_fifo_full; + + // fifo data assignment + assign r_fifo_inp.id = err_req.ar.id; + assign r_fifo_inp.len = err_req.ar.len; + + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .DEPTH ( MaxTrans ), + .dtype ( r_data_t ) + ) i_r_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( test_i ), + .full_o ( r_fifo_full ), + .empty_o ( r_fifo_empty ), + .usage_o ( ), + .data_i ( r_fifo_inp ), + .push_i ( r_fifo_push ), + .data_o ( r_fifo_data ), + .pop_i ( r_fifo_pop ) + ); + + always_comb begin : proc_r_channel + // default assignments + r_busy_d = r_busy_q; + r_busy_load = 1'b0; + // r fifo signals + r_fifo_pop = 1'b0; + // r counter signals + r_cnt_clear = 1'b0; + r_cnt_en = 1'b0; + r_cnt_load = 1'b0; + // r_channel + err_resp.r = '0; + err_resp.r.id = r_fifo_data.id; + err_resp.r.data = RespData; + err_resp.r.resp = Resp; + err_resp.r_valid = 1'b0; + // control + if (r_busy_q) begin + err_resp.r_valid = 1'b1; + err_resp.r.last = (r_current_beat == '0); + // r transaction + if (err_req.r_ready) begin + r_cnt_en = 1'b1; + if (r_current_beat == '0) begin + r_busy_d = 1'b0; + r_busy_load = 1'b1; + r_cnt_clear = 1'b1; + r_fifo_pop = 1'b1; + end + end + end else begin + // when not busy and fifo not empty, start counter err gen + if (!r_fifo_empty) begin + r_busy_d = 1'b1; + r_busy_load = 1'b1; + r_cnt_load = 1'b1; + end + end + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + r_busy_q <= '0; + end else if (r_busy_load) begin + r_busy_q <= r_busy_d; + end + end + + counter #( + .WIDTH ($bits(axi_pkg::len_t)) + ) i_r_counter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( r_cnt_clear ), + .en_i ( r_cnt_en ), + .load_i ( r_cnt_load ), + .down_i ( 1'b1 ), + .d_i ( r_fifo_data.len ), + .q_o ( r_current_beat ), + .overflow_o( ) + ); + + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (Resp == axi_pkg::RESP_DECERR || Resp == axi_pkg::RESP_SLVERR) else + $fatal(1, "This module may only generate RESP_DECERR or RESP_SLVERR responses!"); + end + default disable iff (!rst_ni); + if (!ATOPs) begin : gen_assert_atops_unsupported + assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0)) else + $fatal(1, "Got ATOP but not configured to support ATOPs!"); + end + `endif + // pragma translate_on + +endmodule diff --git a/hw/deps/axi/src/axi_id_prepend.sv b/hw/deps/axi/src/axi_id_prepend.sv new file mode 100644 index 0000000..317ae32 --- /dev/null +++ b/hw/deps/axi/src/axi_id_prepend.sv @@ -0,0 +1,159 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +// AXI ID Prepend: This module prepends/strips the MSB from the AXI IDs. +// Constraints enforced through assertions: ID width of slave and master port + +module axi_id_prepend #( + parameter int unsigned NoBus = 1, // Can take multiple axi busses + parameter int unsigned AxiIdWidthSlvPort = 4, // AXI ID Width of the Slave Ports + parameter int unsigned AxiIdWidthMstPort = 6, // AXI ID Width of the Master Ports + parameter type slv_aw_chan_t = logic, // AW Channel Type for slv port + parameter type slv_w_chan_t = logic, // W Channel Type for slv port + parameter type slv_b_chan_t = logic, // B Channel Type for slv port + parameter type slv_ar_chan_t = logic, // AR Channel Type for slv port + parameter type slv_r_chan_t = logic, // R Channel Type for slv port + parameter type mst_aw_chan_t = logic, // AW Channel Type for mst port + parameter type mst_w_chan_t = logic, // W Channel Type for mst port + parameter type mst_b_chan_t = logic, // B Channel Type for mst port + parameter type mst_ar_chan_t = logic, // AR Channel Type for mst port + parameter type mst_r_chan_t = logic, // R Channel Type for mst port + // DEPENDENT PARAMETER DO NOT OVERWRITE! + parameter int unsigned PreIdWidth = AxiIdWidthMstPort - AxiIdWidthSlvPort +) ( + input logic [PreIdWidth-1:0] pre_id_i, // ID to be prepended + // slave port (input), connect master modules here + // AW channel + input slv_aw_chan_t [NoBus-1:0] slv_aw_chans_i, + input logic [NoBus-1:0] slv_aw_valids_i, + output logic [NoBus-1:0] slv_aw_readies_o, + // W channel + input slv_w_chan_t [NoBus-1:0] slv_w_chans_i, + input logic [NoBus-1:0] slv_w_valids_i, + output logic [NoBus-1:0] slv_w_readies_o, + // B channel + output slv_b_chan_t [NoBus-1:0] slv_b_chans_o, + output logic [NoBus-1:0] slv_b_valids_o, + input logic [NoBus-1:0] slv_b_readies_i, + // AR channel + input slv_ar_chan_t [NoBus-1:0] slv_ar_chans_i, + input logic [NoBus-1:0] slv_ar_valids_i, + output logic [NoBus-1:0] slv_ar_readies_o, + // R channel + output slv_r_chan_t [NoBus-1:0] slv_r_chans_o, + output logic [NoBus-1:0] slv_r_valids_o, + input logic [NoBus-1:0] slv_r_readies_i, + // master ports (output), connect slave modules here + // AW channel + output mst_aw_chan_t [NoBus-1:0] mst_aw_chans_o, + output logic [NoBus-1:0] mst_aw_valids_o, + input logic [NoBus-1:0] mst_aw_readies_i, + // W channel + output mst_w_chan_t [NoBus-1:0] mst_w_chans_o, + output logic [NoBus-1:0] mst_w_valids_o, + input logic [NoBus-1:0] mst_w_readies_i, + // B channel + input mst_b_chan_t [NoBus-1:0] mst_b_chans_i, + input logic [NoBus-1:0] mst_b_valids_i, + output logic [NoBus-1:0] mst_b_readies_o, + // AR channel + output mst_ar_chan_t [NoBus-1:0] mst_ar_chans_o, + output logic [NoBus-1:0] mst_ar_valids_o, + input logic [NoBus-1:0] mst_ar_readies_i, + // R channel + input mst_r_chan_t [NoBus-1:0] mst_r_chans_i, + input logic [NoBus-1:0] mst_r_valids_i, + output logic [NoBus-1:0] mst_r_readies_o +); + + // prepend the ID + for (genvar i = 0; i < NoBus; i++) begin : gen_id_prepend + if (PreIdWidth == 0) begin : gen_no_prepend + assign mst_aw_chans_o[i] = slv_aw_chans_i[i]; + assign mst_ar_chans_o[i] = slv_ar_chans_i[i]; + end else begin : gen_prepend + always_comb begin + mst_aw_chans_o[i] = slv_aw_chans_i[i]; + mst_ar_chans_o[i] = slv_ar_chans_i[i]; + mst_aw_chans_o[i].id = {pre_id_i, slv_aw_chans_i[i].id[AxiIdWidthSlvPort-1:0]}; + mst_ar_chans_o[i].id = {pre_id_i, slv_ar_chans_i[i].id[AxiIdWidthSlvPort-1:0]}; + end + end + // The ID is in the highest bits of the struct, so an assignment from a channel with a wide ID + // to a channel with a shorter ID correctly cuts the prepended ID. + assign slv_b_chans_o[i] = mst_b_chans_i[i]; + assign slv_r_chans_o[i] = mst_r_chans_i[i]; + end + + // assign the handshaking's and w channel + assign mst_w_chans_o = slv_w_chans_i; + assign mst_aw_valids_o = slv_aw_valids_i; + assign slv_aw_readies_o = mst_aw_readies_i; + assign mst_w_valids_o = slv_w_valids_i; + assign slv_w_readies_o = mst_w_readies_i; + assign slv_b_valids_o = mst_b_valids_i; + assign mst_b_readies_o = slv_b_readies_i; + assign mst_ar_valids_o = slv_ar_valids_i; + assign slv_ar_readies_o = mst_ar_readies_i; + assign slv_r_valids_o = mst_r_valids_i; + assign mst_r_readies_o = slv_r_readies_i; + +// pragma translate_off +`ifndef VERILATOR + initial begin : p_assert + assert(NoBus > 0) + else $fatal(1, "Input must be at least one element wide."); + assert(PreIdWidth == ($bits(mst_aw_chans_o[0].id) - $bits(slv_aw_chans_i[0].id))) + else $fatal(1, "Prepend ID Width must be: $bits(mst_aw_chans_o.id)-$bits(slv_aw_chans_i.id)"); + assert ($bits(mst_aw_chans_o[0].id) > $bits(slv_aw_chans_i[0].id)) + else $fatal(1, "The master AXI port has to have a wider ID than the slave port."); + end + + aw_id : assert final( + mst_aw_chans_o[0].id[$bits(slv_aw_chans_i[0].id)-1:0] === slv_aw_chans_i[0].id) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_addr : assert final(mst_aw_chans_o[0].addr === slv_aw_chans_i[0].addr) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_len : assert final(mst_aw_chans_o[0].len === slv_aw_chans_i[0].len) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_size : assert final(mst_aw_chans_o[0].size === slv_aw_chans_i[0].size) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_qos : assert final(mst_aw_chans_o[0].qos === slv_aw_chans_i[0].qos) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + + b_id : assert final( + mst_b_chans_i[0].id[$bits(slv_b_chans_o[0].id)-1:0] === slv_b_chans_o[0].id) + else $fatal (1, "Something with the B channel ID stripping went wrong."); + b_resp : assert final(mst_b_chans_i[0].resp === slv_b_chans_o[0].resp) + else $fatal (1, "Something with the B channel ID stripping went wrong."); + + ar_id : assert final( + mst_ar_chans_o[0].id[$bits(slv_ar_chans_i[0].id)-1:0] === slv_ar_chans_i[0].id) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_addr : assert final(mst_ar_chans_o[0].addr === slv_ar_chans_i[0].addr) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_len : assert final(mst_ar_chans_o[0].len === slv_ar_chans_i[0].len) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_size : assert final(mst_ar_chans_o[0].size === slv_ar_chans_i[0].size) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_qos : assert final(mst_ar_chans_o[0].qos === slv_ar_chans_i[0].qos) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + + r_id : assert final(mst_r_chans_i[0].id[$bits(slv_r_chans_o[0].id)-1:0] === slv_r_chans_o[0].id) + else $fatal (1, "Something with the R channel ID stripping went wrong."); + r_data : assert final(mst_r_chans_i[0].data === slv_r_chans_o[0].data) + else $fatal (1, "Something with the R channel ID stripping went wrong."); + r_resp : assert final(mst_r_chans_i[0].resp === slv_r_chans_o[0].resp) + else $fatal (1, "Something with the R channel ID stripping went wrong."); +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/axi/src/axi_id_remap.sv b/hw/deps/axi/src/axi_id_remap.sv new file mode 100644 index 0000000..78033f2 --- /dev/null +++ b/hw/deps/axi/src/axi_id_remap.sv @@ -0,0 +1,640 @@ +// Copyright (c) 2014-2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Andreas Kurth +// Florian Zaruba +// Wolfgang Roenninger + +`include "common_cells/registers.svh" + +/// Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port. +/// +/// This module is designed to remap an overly wide, sparsely used ID space to a narrower, densely +/// used ID space. This scenario occurs, for example, when an AXI master has wide ID ports but +/// effectively only uses a (not necessarily contiguous) subset of IDs. +/// +/// This module retains the independence of IDs. That is, if two transactions have different IDs at +/// the slave port of this module, they are guaranteed to have different IDs at the master port of +/// this module. This implies a lower bound on the [width of IDs on the master +/// port](#parameter.AxiMstPortIdWidth). If you require narrower master port IDs and can forgo ID +/// independence, use [`axi_id_serialize`](module.axi_id_serialize) instead. +/// +/// Internally, a [table is used for remapping IDs](module.axi_id_remap_table). +module axi_id_remap #( + /// ID width of the AXI4+ATOP slave port. + parameter int unsigned AxiSlvPortIdWidth = 32'd0, + /// Maximum number of different IDs that can be in flight at the slave port. Reads and writes are + /// counted separately (except for ATOPs, which count as both read and write). + /// + /// It is legal for upstream to have transactions with more unique IDs than the maximum given by + /// this parameter in flight, but a transaction exceeding the maximum will be stalled until all + /// transactions of another ID complete. + /// + /// The maximum value of this parameter is `2**AxiSlvPortIdWidth`. + parameter int unsigned AxiSlvPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID. + /// + /// It is legal for upstream to have more transactions than the maximum given by this parameter in + /// flight for any ID, but a transaction exceeding the maximum will be stalled until another + /// transaction with the same ID completes. + parameter int unsigned AxiMaxTxnsPerId = 32'd0, + /// ID width of the AXI4+ATOP master port. + /// + /// The minimum value of this parameter is the ceiled binary logarithm of `AxiSlvPortMaxUniqIds`, + /// because IDs at the master port must be wide enough to represent IDs up to + /// `AxiSlvPortMaxUniqIds-1`. + /// + /// If master IDs are wider than the minimum, they are extended by prepending zeros. + parameter int unsigned AxiMstPortIdWidth = 32'd0, + /// Request struct type of the AXI4+ATOP slave port. + /// + /// The width of all IDs in this struct must match `AxiSlvPortIdWidth`. + parameter type slv_req_t = logic, + /// Response struct type of the AXI4+ATOP slave port. + /// + /// The width of all IDs in this struct must match `AxiSlvPortIdWidth`. + parameter type slv_resp_t = logic, + /// Request struct type of the AXI4+ATOP master port + /// + /// The width of all IDs in this struct must match `AxiMstPortIdWidth`. + parameter type mst_req_t = logic, + /// Response struct type of the AXI4+ATOP master port + /// + /// The width of all IDs in this struct must match `AxiMstPortIdWidth`. + parameter type mst_resp_t = logic +) ( + /// Rising-edge clock of all ports + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Slave port request + input slv_req_t slv_req_i, + /// Slave port response + output slv_resp_t slv_resp_o, + /// Master port request + output mst_req_t mst_req_o, + /// Master port response + input mst_resp_t mst_resp_i +); + + // Feed all signals that are not ID or flow control of AW and AR through. + assign mst_req_o.aw.addr = slv_req_i.aw.addr; + assign mst_req_o.aw.len = slv_req_i.aw.len; + assign mst_req_o.aw.size = slv_req_i.aw.size; + assign mst_req_o.aw.burst = slv_req_i.aw.burst; + assign mst_req_o.aw.lock = slv_req_i.aw.lock; + assign mst_req_o.aw.cache = slv_req_i.aw.cache; + assign mst_req_o.aw.prot = slv_req_i.aw.prot; + assign mst_req_o.aw.qos = slv_req_i.aw.qos; + assign mst_req_o.aw.region = slv_req_i.aw.region; + assign mst_req_o.aw.atop = slv_req_i.aw.atop; + assign mst_req_o.aw.user = slv_req_i.aw.user; + + assign mst_req_o.w = slv_req_i.w; + assign mst_req_o.w_valid = slv_req_i.w_valid; + assign slv_resp_o.w_ready = mst_resp_i.w_ready; + + assign slv_resp_o.b.resp = mst_resp_i.b.resp; + assign slv_resp_o.b.user = mst_resp_i.b.user; + assign slv_resp_o.b_valid = mst_resp_i.b_valid; + assign mst_req_o.b_ready = slv_req_i.b_ready; + + assign mst_req_o.ar.addr = slv_req_i.ar.addr; + assign mst_req_o.ar.len = slv_req_i.ar.len; + assign mst_req_o.ar.size = slv_req_i.ar.size; + assign mst_req_o.ar.burst = slv_req_i.ar.burst; + assign mst_req_o.ar.lock = slv_req_i.ar.lock; + assign mst_req_o.ar.cache = slv_req_i.ar.cache; + assign mst_req_o.ar.prot = slv_req_i.ar.prot; + assign mst_req_o.ar.qos = slv_req_i.ar.qos; + assign mst_req_o.ar.region = slv_req_i.ar.region; + assign mst_req_o.ar.user = slv_req_i.ar.user; + + assign slv_resp_o.r.data = mst_resp_i.r.data; + assign slv_resp_o.r.resp = mst_resp_i.r.resp; + assign slv_resp_o.r.last = mst_resp_i.r.last; + assign slv_resp_o.r.user = mst_resp_i.r.user; + assign slv_resp_o.r_valid = mst_resp_i.r_valid; + assign mst_req_o.r_ready = slv_req_i.r_ready; + + + // Remap tables keep track of in-flight bursts and their input and output IDs. + localparam int unsigned IdxWidth = cf_math_pkg::idx_width(AxiSlvPortMaxUniqIds); + typedef logic [AxiSlvPortMaxUniqIds-1:0] field_t; + typedef logic [AxiSlvPortIdWidth-1:0] id_inp_t; + typedef logic [IdxWidth-1:0] idx_t; + field_t wr_free, rd_free, both_free; + id_inp_t rd_push_inp_id; + idx_t wr_free_oup_id, rd_free_oup_id, both_free_oup_id, + wr_push_oup_id, rd_push_oup_id, + wr_exists_id, rd_exists_id; + logic wr_exists, rd_exists, + wr_exists_full, rd_exists_full, + wr_full, rd_full, + wr_push, rd_push; + + logic ar_must_pass_q, ar_must_pass_d; + + axi_id_remap_table #( + .InpIdWidth ( AxiSlvPortIdWidth ), + .MaxUniqInpIds ( AxiSlvPortMaxUniqIds ), + .MaxTxnsPerId ( AxiMaxTxnsPerId ) + ) i_wr_table ( + .clk_i, + .rst_ni, + .free_o ( wr_free ), + .free_oup_id_o ( wr_free_oup_id ), + .full_o ( wr_full ), + .push_i ( wr_push ), + .push_inp_id_i ( slv_req_i.aw.id ), + .push_oup_id_i ( wr_push_oup_id ), + .exists_inp_id_i ( slv_req_i.aw.id ), + .exists_o ( wr_exists ), + .exists_oup_id_o ( wr_exists_id ), + .exists_full_o ( wr_exists_full ), + .pop_i ( slv_resp_o.b_valid && slv_req_i.b_ready ), + .pop_oup_id_i ( mst_resp_i.b.id[IdxWidth-1:0] ), + .pop_inp_id_o ( slv_resp_o.b.id ) + ); + axi_id_remap_table #( + .InpIdWidth ( AxiSlvPortIdWidth ), + .MaxUniqInpIds ( AxiSlvPortMaxUniqIds ), + .MaxTxnsPerId ( AxiMaxTxnsPerId ) + ) i_rd_table ( + .clk_i, + .rst_ni, + .free_o ( rd_free ), + .free_oup_id_o ( rd_free_oup_id ), + .full_o ( rd_full ), + .push_i ( rd_push ), + .push_inp_id_i ( rd_push_inp_id ), + .push_oup_id_i ( rd_push_oup_id ), + .exists_inp_id_i ( slv_req_i.ar.id ), + .exists_o ( rd_exists ), + .exists_oup_id_o ( rd_exists_id ), + .exists_full_o ( rd_exists_full ), + .pop_i ( slv_resp_o.r_valid && slv_req_i.r_ready && slv_resp_o.r.last ), + .pop_oup_id_i ( mst_resp_i.r.id[IdxWidth-1:0] ), + .pop_inp_id_o ( slv_resp_o.r.id ) + ); + assign both_free = wr_free & rd_free; + lzc #( + .WIDTH ( AxiSlvPortMaxUniqIds ), + .MODE ( 1'b0 ) + ) i_lzc ( + .in_i ( both_free ), + .cnt_o ( both_free_oup_id ), + .empty_o ( /* unused */ ) + ); + + // Zero-extend output IDs if the output IDs is are wider than the IDs from the tables. + localparam ZeroWidth = AxiMstPortIdWidth - IdxWidth; + assign mst_req_o.ar.id = {{ZeroWidth{1'b0}}, rd_push_oup_id}; + assign mst_req_o.aw.id = {{ZeroWidth{1'b0}}, wr_push_oup_id}; + + // Handle requests. + enum logic [1:0] {Ready, HoldAR, HoldAW, HoldAx} state_d, state_q; + idx_t ar_id_d, ar_id_q, + aw_id_d, aw_id_q; + always_comb begin + mst_req_o.aw_valid = 1'b0; + slv_resp_o.aw_ready = 1'b0; + wr_push = 1'b0; + wr_push_oup_id = '0; + mst_req_o.ar_valid = 1'b0; + slv_resp_o.ar_ready = 1'b0; + rd_push = 1'b0; + rd_push_inp_id = '0; + rd_push_oup_id = '0; + ar_id_d = ar_id_q; + aw_id_d = aw_id_q; + state_d = state_q; + ar_must_pass_d = ar_must_pass_q; + + unique case (state_q) + Ready: begin + // Reads + if (slv_req_i.ar_valid) begin + // If a burst with the same input ID is already in flight or there are free output IDs: + if ((rd_exists && !rd_exists_full) || (!rd_exists && !rd_full)) begin + // Determine the output ID: if another in-flight burst had the same input ID, we must + // reuse its output ID to maintain ordering; else, we assign the next free ID. + rd_push_inp_id = slv_req_i.ar.id; + rd_push_oup_id = rd_exists ? rd_exists_id : rd_free_oup_id; + // Forward the AR and push a new entry to the read table. + mst_req_o.ar_valid = 1'b1; + rd_push = 1'b1; + end + end + + // Writes + if (slv_req_i.aw_valid) begin + // If this is not an ATOP that gives rise to an R response, we can handle it in isolation + // on the write direction. + if (!slv_req_i.aw.atop[5]) begin + // If a burst with the same input ID is already in flight or there are free output IDs: + if ((wr_exists && !wr_exists_full) || (!wr_exists && !wr_full)) begin + // Determine the output ID: if another in-flight burst had the same input ID, we must + // reuse its output ID to maintain ordering; else, we assign the next free ID. + wr_push_oup_id = wr_exists ? wr_exists_id : wr_free_oup_id; + // Forward the AW and push a new entry to the write table. + mst_req_o.aw_valid = 1'b1; + wr_push = 1'b1; + end + // If this is an ATOP that gives rise to an R response, we must remap to an ID that is + // free on both read and write direction and push also to the read table. + end else if (ar_must_pass_q == 1'b0) begin + // Nullify a potential AR at our output. This is legal in this state. + ar_must_pass_d = mst_req_o.ar_valid; + mst_req_o.ar_valid = 1'b0; + slv_resp_o.ar_ready = 1'b0; + rd_push = 1'b0; + if ((|both_free)) begin + // Use an output ID that is free in both directions. + wr_push_oup_id = both_free_oup_id; + rd_push_inp_id = slv_req_i.aw.id; + rd_push_oup_id = both_free_oup_id; + // Forward the AW and push a new entry to both tables. + mst_req_o.aw_valid = 1'b1; + rd_push = 1'b1; + wr_push = 1'b1; + end + end + end + + // Hold AR, AW, or both if they are valid but not yet ready. + if (mst_req_o.ar_valid) begin + ar_must_pass_d = 1'b0; + slv_resp_o.ar_ready = mst_resp_i.ar_ready; + if (!mst_resp_i.ar_ready) begin + ar_id_d = rd_push_oup_id; + end + end + if (mst_req_o.aw_valid) begin + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + if (!mst_resp_i.aw_ready) begin + aw_id_d = wr_push_oup_id; + end + end + priority casez ({mst_req_o.ar_valid, mst_resp_i.ar_ready, + mst_req_o.aw_valid, mst_resp_i.aw_ready}) + 4'b1010: state_d = HoldAx; + 4'b10??: state_d = HoldAR; + 4'b??10: state_d = HoldAW; + default: state_d = Ready; + endcase + end + + HoldAR: begin + // Drive `mst_req_o.ar.id` through `rd_push_oup_id`. + rd_push_oup_id = ar_id_q; + mst_req_o.ar_valid = 1'b1; + slv_resp_o.ar_ready = mst_resp_i.ar_ready; + if (mst_resp_i.ar_ready) begin + state_d = Ready; + end + end + + HoldAW: begin + // Drive mst_req_o.aw.id through `wr_push_oup_id`. + wr_push_oup_id = aw_id_q; + mst_req_o.aw_valid = 1'b1; + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + if (mst_resp_i.aw_ready) begin + state_d = Ready; + end + end + + HoldAx: begin + rd_push_oup_id = ar_id_q; + mst_req_o.ar_valid = 1'b1; + slv_resp_o.ar_ready = mst_resp_i.ar_ready; + wr_push_oup_id = aw_id_q; + mst_req_o.aw_valid = 1'b1; + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + unique case ({mst_resp_i.ar_ready, mst_resp_i.aw_ready}) + 2'b01: state_d = HoldAR; + 2'b10: state_d = HoldAW; + 2'b11: state_d = Ready; + default: /*do nothing / stay in this state*/; + endcase + end + + default: state_d = Ready; + endcase + end + + // Registers + `FFARN(ar_id_q, ar_id_d, '0, clk_i, rst_ni) + `FFARN(aw_id_q, aw_id_d, '0, clk_i, rst_ni) + `FFARN(ar_must_pass_q, ar_must_pass_d, '0, clk_i, rst_ni) + `FFARN(state_q, state_d, Ready, clk_i, rst_ni) + + `ifndef VERILATOR + // pragma translate_off + initial begin : p_assert + assert(AxiSlvPortIdWidth > 32'd0) + else $fatal(1, "Parameter AxiSlvPortIdWidth has to be larger than 0!"); + assert(AxiMstPortIdWidth >= IdxWidth) + else $fatal(1, "Parameter AxiMstPortIdWidth has to be at least IdxWidth!"); + assert (AxiSlvPortMaxUniqIds > 0) + else $fatal(1, "Parameter AxiSlvPortMaxUniqIds has to be larger than 0!"); + assert (AxiSlvPortMaxUniqIds <= 2**AxiSlvPortIdWidth) + else $fatal(1, "Parameter AxiSlvPortMaxUniqIds may be at most 2**AxiSlvPortIdWidth!"); + assert (AxiMaxTxnsPerId > 0) + else $fatal(1, "Parameter AxiMaxTxnsPerId has to be larger than 0!"); + assert($bits(slv_req_i.aw.addr) == $bits(mst_req_o.aw.addr)) + else $fatal(1, "AXI AW address widths are not equal!"); + assert($bits(slv_req_i.w.data) == $bits(mst_req_o.w.data)) + else $fatal(1, "AXI W data widths are not equal!"); + assert($bits(slv_req_i.ar.addr) == $bits(mst_req_o.ar.addr)) + else $fatal(1, "AXI AR address widths are not equal!"); + assert($bits(slv_resp_o.r.data) == $bits(mst_resp_i.r.data)) + else $fatal(1, "AXI R data widths are not equal!"); + assert ($bits(slv_req_i.aw.id) == AxiSlvPortIdWidth); + assert ($bits(slv_resp_o.b.id) == AxiSlvPortIdWidth); + assert ($bits(slv_req_i.ar.id) == AxiSlvPortIdWidth); + assert ($bits(slv_resp_o.r.id) == AxiSlvPortIdWidth); + assert ($bits(mst_req_o.aw.id) == AxiMstPortIdWidth); + assert ($bits(mst_resp_i.b.id) == AxiMstPortIdWidth); + assert ($bits(mst_req_o.ar.id) == AxiMstPortIdWidth); + assert ($bits(mst_resp_i.r.id) == AxiMstPortIdWidth); + end + + default disable iff (!rst_ni); + assert property (@(posedge clk_i) slv_req_i.aw_valid && slv_resp_o.aw_ready + |-> mst_req_o.aw_valid && mst_resp_i.aw_ready); + assert property (@(posedge clk_i) mst_resp_i.b_valid && mst_req_o.b_ready + |-> slv_resp_o.b_valid && slv_req_i.b_ready); + assert property (@(posedge clk_i) slv_req_i.ar_valid && slv_resp_o.ar_ready + |-> mst_req_o.ar_valid && mst_resp_i.ar_ready); + assert property (@(posedge clk_i) mst_resp_i.r_valid && mst_req_o.r_ready + |-> slv_resp_o.r_valid && slv_req_i.r_ready); + assert property (@(posedge clk_i) slv_resp_o.r_valid + |-> slv_resp_o.r.last == mst_resp_i.r.last); + assert property (@(posedge clk_i) mst_req_o.ar_valid && !mst_resp_i.ar_ready + |=> mst_req_o.ar_valid && $stable(mst_req_o.ar.id)); + assert property (@(posedge clk_i) mst_req_o.aw_valid && !mst_resp_i.aw_ready + |=> mst_req_o.aw_valid && $stable(mst_req_o.aw.id)); + // pragma translate_on + `endif +endmodule + +/// Internal module of [`axi_id_remap`](module.axi_id_remap): Table to remap input to output IDs. +/// +/// This module contains a table indexed by the output ID (type `idx_t`). Each table entry has two +/// fields: the input ID and a counter that records how many transactions with the input and output +/// ID of the entry are in-flight. +/// +/// The mapping from input and output IDs is injective. Therefore, when the table contains an entry +/// for an input ID with non-zero counter value, subsequent input IDs must use the same entry and +/// thus the same output ID. +/// +/// ## Relation of types and table layout +/// ![diagram of table](axi_id_remap_table.svg) +/// +/// ## Complexity +/// This module has: +/// - `MaxUniqInpIds * InpIdWidth * clog2(MaxTxnsPerId)` flip flops; +/// - `MaxUniqInpIds` comparators of width `InpIdWidth`; +/// - 2 leading-zero counters of width `MaxUniqInpIds`. +module axi_id_remap_table #( + /// Width of input IDs, therefore width of `id_inp_t`. + parameter int unsigned InpIdWidth = 32'd0, + /// Maximum number of different input IDs that can be in-flight. This defines the number of remap + /// table entries. + /// + /// The maximum value of this parameter is `2**InpIdWidth`. + parameter int unsigned MaxUniqInpIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID. + parameter int unsigned MaxTxnsPerId = 32'd0, + /// Derived (**=do not override**) type of input IDs. + localparam type id_inp_t = logic [InpIdWidth-1:0], + /// Derived (**=do not override**) width of table index (ceiled binary logarithm of + /// `MaxUniqInpIds`). + localparam int unsigned IdxWidth = cf_math_pkg::idx_width(MaxUniqInpIds), + /// Derived (**=do not override**) type of table index (width = `IdxWidth`). + localparam type idx_t = logic [IdxWidth-1:0], + /// Derived (**=do not override**) type with one bit per table entry (thus also output ID). + localparam type field_t = logic [MaxUniqInpIds-1:0] +) ( + /// Rising-edge clock of all ports + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + + /// One bit per table entry / output ID that indicates whether the entry is free. + output field_t free_o, + /// Lowest free output ID. Only valid if the table is not full (i.e., `!full_o`). + output idx_t free_oup_id_o, + /// Indicates whether the table is full. + output logic full_o, + + /// Push an input/output ID pair to the table. + input logic push_i, + /// Input ID to be pushed. If the table already contains this ID, its counter must be smaller than + /// `MaxTxnsPerId`. + input id_inp_t push_inp_id_i, + /// Output ID to be pushed. If the table already contains the input ID to be pushed, the output + /// ID **must** match the output ID of the existing entry with the same input ID. + input idx_t push_oup_id_i, + + /// Input ID to look up in the table. + input id_inp_t exists_inp_id_i, + /// Indicates whether the given input ID exists in the table. + output logic exists_o, + /// The output ID of the given input ID. Only valid if the input ID exists (i.e., `exists_o`). + output idx_t exists_oup_id_o, + /// Indicates whether the maximum number of transactions for the given input ID is reached. Only + /// valid if the input ID exists (i.e., `exists_o`). + output logic exists_full_o, + + /// Pop an output ID from the table. This reduces the counter for the table index given in + /// `pop_oup_id_i` by one. + input logic pop_i, + /// Output ID to be popped. The counter for this ID must be larger than `0`. + input idx_t pop_oup_id_i, + /// Input ID corresponding to the popped output ID. + output id_inp_t pop_inp_id_o +); + + /// Counter width, derived to hold numbers up to `MaxTxnsPerId`. + localparam int unsigned CntWidth = $clog2(MaxTxnsPerId+1); + /// Counter that tracks the number of in-flight transactions with an ID. + typedef logic [CntWidth-1:0] cnt_t; + + /// Type of a table entry. + typedef struct packed { + id_inp_t inp_id; + cnt_t cnt; + } entry_t; + + // Table indexed by output IDs that contains the corresponding input IDs + entry_t [MaxUniqInpIds-1:0] table_d, table_q; + + // Determine lowest free output ID. + for (genvar i = 0; i < MaxUniqInpIds; i++) begin : gen_free_o + assign free_o[i] = table_q[i].cnt == '0; + end + lzc #( + .WIDTH ( MaxUniqInpIds ), + .MODE ( 1'b0 ) + ) i_lzc_free ( + .in_i ( free_o ), + .cnt_o ( free_oup_id_o ), + .empty_o ( full_o ) + ); + + // Determine the input ID for a given output ID. + assign pop_inp_id_o = table_q[pop_oup_id_i].inp_id; + + // Determine if given output ID is already used and, if it is, by which input ID. + field_t match; + for (genvar i = 0; i < MaxUniqInpIds; i++) begin : gen_match + assign match[i] = table_q[i].cnt > 0 && table_q[i].inp_id == exists_inp_id_i; + end + logic no_match; + lzc #( + .WIDTH ( MaxUniqInpIds ), + .MODE ( 1'b0 ) + ) i_lzc_match ( + .in_i ( match ), + .cnt_o ( exists_oup_id_o ), + .empty_o ( no_match ) + ); + assign exists_o = ~no_match; + assign exists_full_o = table_q[exists_oup_id_o].cnt == MaxTxnsPerId; + + // Push and pop table entries. + always_comb begin + table_d = table_q; + if (push_i) begin + table_d[push_oup_id_i].inp_id = push_inp_id_i; + table_d[push_oup_id_i].cnt += 1; + end + if (pop_i) begin + table_d[pop_oup_id_i].cnt -= 1; + end + end + + // Registers + `FFARN(table_q, table_d, '0, clk_i, rst_ni) + + // Assertions + // pragma translate_off + `ifndef VERILATOR + default disable iff (!rst_ni); + assume property (@(posedge clk_i) push_i |-> + table_q[push_oup_id_i].cnt == '0 || table_q[push_oup_id_i].inp_id == push_inp_id_i) + else $error("Push must be to empty output ID or match existing input ID!"); + assume property (@(posedge clk_i) push_i |-> table_q[push_oup_id_i].cnt < MaxTxnsPerId) + else $error("Maximum number of in-flight bursts must not be exceeded!"); + assume property (@(posedge clk_i) pop_i |-> table_q[pop_oup_id_i].cnt > 0) + else $error("Pop must target output ID with non-zero counter!"); + assume property (@(posedge clk_i) $onehot0(match)) + else $error("Input ID in table must be unique!"); + initial begin + assert (InpIdWidth > 0); + assert (MaxUniqInpIds > 0); + assert (MaxUniqInpIds <= (1 << InpIdWidth)); + assert (MaxTxnsPerId > 0); + assert (IdxWidth >= 1); + end + `endif + // pragma translate_on + +endmodule + + +`include "axi/typedef.svh" +`include "axi/assign.svh" +/// Interface variant of [`axi_id_remap`](module.axi_id_remap). +/// +/// See the documentation of the main module for the definition of ports and parameters. +module axi_id_remap_intf #( + parameter int unsigned AXI_SLV_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_SLV_PORT_MAX_UNIQ_IDS = 32'd0, + parameter int unsigned AXI_MAX_TXNS_PER_ID = 32'd0, + parameter int unsigned AXI_MST_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv, + AXI_BUS.Master mst +); + typedef logic [AXI_SLV_PORT_ID_WIDTH-1:0] slv_id_t; + typedef logic [AXI_MST_PORT_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] axi_data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] axi_strb_t; + typedef logic [AXI_USER_WIDTH-1:0] axi_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + + slv_req_t slv_req; + slv_resp_t slv_resp; + mst_req_t mst_req; + mst_resp_t mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_id_remap #( + .AxiSlvPortIdWidth ( AXI_SLV_PORT_ID_WIDTH ), + .AxiSlvPortMaxUniqIds ( AXI_SLV_PORT_MAX_UNIQ_IDS ), + .AxiMaxTxnsPerId ( AXI_MAX_TXNS_PER_ID ), + .AxiMstPortIdWidth ( AXI_MST_PORT_ID_WIDTH ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ) + ) i_axi_id_remap ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (slv.AXI_ID_WIDTH == AXI_SLV_PORT_ID_WIDTH); + assert (slv.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (slv.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (slv.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (mst.AXI_ID_WIDTH == AXI_MST_PORT_ID_WIDTH); + assert (mst.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (mst.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (mst.AXI_USER_WIDTH == AXI_USER_WIDTH); + end + `endif + // pragma translate_on +endmodule diff --git a/hw/deps/axi/src/axi_intf.sv b/hw/deps/axi/src/axi_intf.sv new file mode 100644 index 0000000..38047fc --- /dev/null +++ b/hw/deps/axi/src/axi_intf.sv @@ -0,0 +1,434 @@ +// Copyright (c) 2014-2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Fabian Schuiki +// +// This file defines the interfaces we support. + + + +/// An AXI4 interface. +interface AXI_BUS #( + parameter AXI_ADDR_WIDTH = -1, + parameter AXI_DATA_WIDTH = -1, + parameter AXI_ID_WIDTH = -1, + parameter AXI_USER_WIDTH = -1 +); + + localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + + id_t aw_id; + addr_t aw_addr; + axi_pkg::len_t aw_len; + axi_pkg::size_t aw_size; + axi_pkg::burst_t aw_burst; + logic aw_lock; + axi_pkg::cache_t aw_cache; + axi_pkg::prot_t aw_prot; + axi_pkg::qos_t aw_qos; + axi_pkg::region_t aw_region; + axi_pkg::atop_t aw_atop; + user_t aw_user; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_last; + user_t w_user; + logic w_valid; + logic w_ready; + + id_t b_id; + axi_pkg::resp_t b_resp; + user_t b_user; + logic b_valid; + logic b_ready; + + id_t ar_id; + addr_t ar_addr; + axi_pkg::len_t ar_len; + axi_pkg::size_t ar_size; + axi_pkg::burst_t ar_burst; + logic ar_lock; + axi_pkg::cache_t ar_cache; + axi_pkg::prot_t ar_prot; + axi_pkg::qos_t ar_qos; + axi_pkg::region_t ar_region; + user_t ar_user; + logic ar_valid; + logic ar_ready; + + id_t r_id; + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + user_t r_user; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready, + output w_data, w_strb, w_last, w_user, w_valid, input w_ready, + input b_id, b_resp, b_user, b_valid, output b_ready, + output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready, + input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready + ); + + modport Slave ( + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready, + input w_data, w_strb, w_last, w_user, w_valid, output w_ready, + output b_id, b_resp, b_user, b_valid, input b_ready, + input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready, + output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready + ); + +endinterface + + +/// A clocked AXI4 interface for use in design verification. +interface AXI_BUS_DV #( + parameter AXI_ADDR_WIDTH = -1, + parameter AXI_DATA_WIDTH = -1, + parameter AXI_ID_WIDTH = -1, + parameter AXI_USER_WIDTH = -1 +)( + input logic clk_i +); + + localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + + id_t aw_id; + addr_t aw_addr; + axi_pkg::len_t aw_len; + axi_pkg::size_t aw_size; + axi_pkg::burst_t aw_burst; + logic aw_lock; + axi_pkg::cache_t aw_cache; + axi_pkg::prot_t aw_prot; + axi_pkg::qos_t aw_qos; + axi_pkg::region_t aw_region; + axi_pkg::atop_t aw_atop; + user_t aw_user; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_last; + user_t w_user; + logic w_valid; + logic w_ready; + + id_t b_id; + axi_pkg::resp_t b_resp; + user_t b_user; + logic b_valid; + logic b_ready; + + id_t ar_id; + addr_t ar_addr; + axi_pkg::len_t ar_len; + axi_pkg::size_t ar_size; + axi_pkg::burst_t ar_burst; + logic ar_lock; + axi_pkg::cache_t ar_cache; + axi_pkg::prot_t ar_prot; + axi_pkg::qos_t ar_qos; + axi_pkg::region_t ar_region; + user_t ar_user; + logic ar_valid; + logic ar_ready; + + id_t r_id; + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + user_t r_user; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready, + output w_data, w_strb, w_last, w_user, w_valid, input w_ready, + input b_id, b_resp, b_user, b_valid, output b_ready, + output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready, + input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready + ); + + modport Slave ( + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready, + input w_data, w_strb, w_last, w_user, w_valid, output w_ready, + output b_id, b_resp, b_user, b_valid, input b_ready, + input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready, + output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready + ); + + // pragma translate_off + `ifndef VERILATOR + // Single-Channel Assertions: Signals including valid must not change between valid and handshake. + // AW + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_id))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_addr))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_len))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_size))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_burst))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_lock))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_cache))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_prot))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_qos))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_region))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_atop))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_user))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> aw_valid)); + // W + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_data))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_strb))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_last))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_user))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> w_valid)); + // B + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_id))); + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_resp))); + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_user))); + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> b_valid)); + // AR + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_id))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_addr))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_len))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_size))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_burst))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_lock))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_cache))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_prot))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_qos))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_region))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_user))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> ar_valid)); + // R + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_id))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_data))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_resp))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_last))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_user))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> r_valid)); + `endif + // pragma translate_on + +endinterface + +/// An asynchronous AXI4 interface. +interface AXI_BUS_ASYNC +#( + parameter AXI_ADDR_WIDTH = -1, + parameter AXI_DATA_WIDTH = -1, + parameter AXI_ID_WIDTH = -1, + parameter AXI_USER_WIDTH = -1, + parameter BUFFER_WIDTH = -1 +); + + localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [BUFFER_WIDTH-1:0] buffer_t; + + id_t aw_id; + addr_t aw_addr; + axi_pkg::len_t aw_len; + axi_pkg::size_t aw_size; + axi_pkg::burst_t aw_burst; + logic aw_lock; + axi_pkg::cache_t aw_cache; + axi_pkg::prot_t aw_prot; + axi_pkg::qos_t aw_qos; + axi_pkg::region_t aw_region; + axi_pkg::atop_t aw_atop; + user_t aw_user; + buffer_t aw_writetoken; + buffer_t aw_readpointer; + + data_t w_data; + strb_t w_strb; + logic w_last; + user_t w_user; + buffer_t w_writetoken; + buffer_t w_readpointer; + + id_t b_id; + axi_pkg::resp_t b_resp; + user_t b_user; + buffer_t b_writetoken; + buffer_t b_readpointer; + + id_t ar_id; + addr_t ar_addr; + axi_pkg::len_t ar_len; + axi_pkg::size_t ar_size; + axi_pkg::burst_t ar_burst; + logic ar_lock; + axi_pkg::cache_t ar_cache; + axi_pkg::prot_t ar_prot; + axi_pkg::qos_t ar_qos; + axi_pkg::region_t ar_region; + user_t ar_user; + buffer_t ar_writetoken; + buffer_t ar_readpointer; + + id_t r_id; + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + user_t r_user; + buffer_t r_writetoken; + buffer_t r_readpointer; + + modport Master ( + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, input aw_readpointer, + output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer, + input b_id, b_resp, b_user, b_writetoken, output b_readpointer, + output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, input ar_readpointer, + input r_id, r_data, r_resp, r_last, r_user, r_writetoken, output r_readpointer + ); + + modport Slave ( + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, output aw_readpointer, + input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer, + output b_id, b_resp, b_user, b_writetoken, input b_readpointer, + input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, output ar_readpointer, + output r_id, r_data, r_resp, r_last, r_user, r_writetoken, input r_readpointer + ); + +endinterface + + +/// An AXI4-Lite interface. +interface AXI_LITE #( + parameter AXI_ADDR_WIDTH = -1, + parameter AXI_DATA_WIDTH = -1 +); + + localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + + // AW channel + addr_t aw_addr; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_valid; + logic w_ready; + + axi_pkg::resp_t b_resp; + logic b_valid; + logic b_ready; + + addr_t ar_addr; + logic ar_valid; + logic ar_ready; + + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_addr, aw_valid, input aw_ready, + output w_data, w_strb, w_valid, input w_ready, + input b_resp, b_valid, output b_ready, + output ar_addr, ar_valid, input ar_ready, + input r_data, r_resp, r_valid, output r_ready + ); + + modport Slave ( + input aw_addr, aw_valid, output aw_ready, + input w_data, w_strb, w_valid, output w_ready, + output b_resp, b_valid, input b_ready, + input ar_addr, ar_valid, output ar_ready, + output r_data, r_resp, r_valid, input r_ready + ); + +endinterface + +/// A clocked AXI4-Lite interface for use in design verification. +interface AXI_LITE_DV #( + parameter AXI_ADDR_WIDTH = -1, + parameter AXI_DATA_WIDTH = -1 +)( + input logic clk_i +); + + localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + + // AW channel + addr_t aw_addr; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_valid; + logic w_ready; + + axi_pkg::resp_t b_resp; + logic b_valid; + logic b_ready; + + addr_t ar_addr; + logic ar_valid; + logic ar_ready; + + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_addr, aw_valid, input aw_ready, + output w_data, w_strb, w_valid, input w_ready, + input b_resp, b_valid, output b_ready, + output ar_addr, ar_valid, input ar_ready, + input r_data, r_resp, r_valid, output r_ready + ); + + modport Slave ( + input aw_addr, aw_valid, output aw_ready, + input w_data, w_strb, w_valid, output w_ready, + output b_resp, b_valid, input b_ready, + input ar_addr, ar_valid, output ar_ready, + output r_data, r_resp, r_valid, input r_ready + ); + +endinterface diff --git a/hw/deps/axi/src/axi_mux.sv b/hw/deps/axi/src/axi_mux.sv new file mode 100644 index 0000000..f6644ff --- /dev/null +++ b/hw/deps/axi/src/axi_mux.sv @@ -0,0 +1,520 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +// AXI Multiplexer: This module multiplexes the AXI4 slave ports down to one master port. +// The AXI IDs from the slave ports get extended with the respective slave port index. +// The extension width can be calculated with `$clog2(NoSlvPorts)`. This means the AXI +// ID for the master port has to be this `$clog2(NoSlvPorts)` wider than the ID for the +// slave ports. +// Responses are switched based on these bits. For example, with 4 slave ports +// a response with ID `6'b100110` will be forwarded to slave port 2 (`2'b10`). + +// register macros +`include "common_cells/registers.svh" + +module axi_mux #( + // AXI parameter and channel types + parameter int unsigned SlvAxiIDWidth = 32'd0, // AXI ID width, slave ports + parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports + parameter type mst_aw_chan_t = logic, // AW Channel Type, master port + parameter type w_chan_t = logic, // W Channel Type, all ports + parameter type slv_b_chan_t = logic, // B Channel Type, slave ports + parameter type mst_b_chan_t = logic, // B Channel Type, master port + parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports + parameter type mst_ar_chan_t = logic, // AR Channel Type, master port + parameter type slv_r_chan_t = logic, // R Channel Type, slave ports + parameter type mst_r_chan_t = logic, // R Channel Type, master port + parameter type slv_req_t = logic, // Slave port request type + parameter type slv_resp_t = logic, // Slave port response type + parameter type mst_req_t = logic, // Master ports request type + parameter type mst_resp_t = logic, // Master ports response type + parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports + // Maximum number of outstanding transactions per write + parameter int unsigned MaxWTrans = 32'd8, + // If enabled, this multiplexer is purely combinatorial + parameter bit FallThrough = 1'b0, + // add spill register on write master ports, adds a cycle latency on write channels + parameter bit SpillAw = 1'b1, + parameter bit SpillW = 1'b0, + parameter bit SpillB = 1'b0, + // add spill register on read master ports, adds a cycle latency on read channels + parameter bit SpillAr = 1'b1, + parameter bit SpillR = 1'b0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Test Mode enable + // slave ports (AXI inputs), connect master modules here + input slv_req_t [NoSlvPorts-1:0] slv_reqs_i, + output slv_resp_t [NoSlvPorts-1:0] slv_resps_o, + // master port (AXI outputs), connect slave modules here + output mst_req_t mst_req_o, + input mst_resp_t mst_resp_i +); + + localparam int unsigned MstIdxBits = $clog2(NoSlvPorts); + localparam int unsigned MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits; + + // pass through if only one slave port + if (NoSlvPorts == 32'h1) begin : gen_no_mux + assign mst_req_o = slv_reqs_i[0]; + assign slv_resps_o[0] = mst_resp_i; + // other non degenerate cases + end else begin : gen_mux + + typedef logic [MstIdxBits-1:0] switch_id_t; + + // AXI channels between the ID prepend unit and the rest of the multiplexer + mst_aw_chan_t [NoSlvPorts-1:0] slv_aw_chans; + logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies; + w_chan_t [NoSlvPorts-1:0] slv_w_chans; + logic [NoSlvPorts-1:0] slv_w_valids, slv_w_readies; + mst_b_chan_t [NoSlvPorts-1:0] slv_b_chans; + logic [NoSlvPorts-1:0] slv_b_valids, slv_b_readies; + mst_ar_chan_t [NoSlvPorts-1:0] slv_ar_chans; + logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies; + mst_r_chan_t [NoSlvPorts-1:0] slv_r_chans; + logic [NoSlvPorts-1:0] slv_r_valids, slv_r_readies; + + // These signals are all ID prepended + // AW channel + mst_aw_chan_t mst_aw_chan; + logic mst_aw_valid, mst_aw_ready; + + // AW master handshake internal, so that we are able to stall, if w_fifo is full + logic aw_valid, aw_ready; + + // FF to lock the AW valid signal, when a new arbitration decision is made the decision + // gets pushed into the W FIFO, when it now stalls prevent subsequent pushing + // This FF removes AW to W dependency + logic lock_aw_valid_d, lock_aw_valid_q; + logic load_aw_lock; + + // signals for the FIFO that holds the last switching decision of the AW channel + logic w_fifo_full, w_fifo_empty; + logic w_fifo_push, w_fifo_pop; + switch_id_t w_fifo_data; + + // W channel spill reg + w_chan_t mst_w_chan; + logic mst_w_valid, mst_w_ready; + + // master ID in the b_id + switch_id_t switch_b_id; + + // B channel spill reg + mst_b_chan_t mst_b_chan; + logic mst_b_valid; + + // AR channel for when spill is enabled + mst_ar_chan_t mst_ar_chan; + logic ar_valid, ar_ready; + + // master ID in the r_id + switch_id_t switch_r_id; + + // R channel spill reg + mst_r_chan_t mst_r_chan; + logic mst_r_valid; + + //-------------------------------------- + // ID prepend for all slave ports + //-------------------------------------- + for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_id_prepend + axi_id_prepend #( + .NoBus ( 32'd1 ), // one AXI bus per slave port + .AxiIdWidthSlvPort( SlvAxiIDWidth ), + .AxiIdWidthMstPort( MstAxiIDWidth ), + .slv_aw_chan_t ( slv_aw_chan_t ), + .slv_w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .mst_w_chan_t ( w_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ) + ) i_id_prepend ( + .pre_id_i ( switch_id_t'(i) ), + .slv_aw_chans_i ( slv_reqs_i[i].aw ), + .slv_aw_valids_i ( slv_reqs_i[i].aw_valid ), + .slv_aw_readies_o ( slv_resps_o[i].aw_ready ), + .slv_w_chans_i ( slv_reqs_i[i].w ), + .slv_w_valids_i ( slv_reqs_i[i].w_valid ), + .slv_w_readies_o ( slv_resps_o[i].w_ready ), + .slv_b_chans_o ( slv_resps_o[i].b ), + .slv_b_valids_o ( slv_resps_o[i].b_valid ), + .slv_b_readies_i ( slv_reqs_i[i].b_ready ), + .slv_ar_chans_i ( slv_reqs_i[i].ar ), + .slv_ar_valids_i ( slv_reqs_i[i].ar_valid ), + .slv_ar_readies_o ( slv_resps_o[i].ar_ready ), + .slv_r_chans_o ( slv_resps_o[i].r ), + .slv_r_valids_o ( slv_resps_o[i].r_valid ), + .slv_r_readies_i ( slv_reqs_i[i].r_ready ), + .mst_aw_chans_o ( slv_aw_chans[i] ), + .mst_aw_valids_o ( slv_aw_valids[i] ), + .mst_aw_readies_i ( slv_aw_readies[i] ), + .mst_w_chans_o ( slv_w_chans[i] ), + .mst_w_valids_o ( slv_w_valids[i] ), + .mst_w_readies_i ( slv_w_readies[i] ), + .mst_b_chans_i ( slv_b_chans[i] ), + .mst_b_valids_i ( slv_b_valids[i] ), + .mst_b_readies_o ( slv_b_readies[i] ), + .mst_ar_chans_o ( slv_ar_chans[i] ), + .mst_ar_valids_o ( slv_ar_valids[i] ), + .mst_ar_readies_i ( slv_ar_readies[i] ), + .mst_r_chans_i ( slv_r_chans[i] ), + .mst_r_valids_i ( slv_r_valids[i] ), + .mst_r_readies_o ( slv_r_readies[i] ) + ); + end + + //-------------------------------------- + // AW Channel + //-------------------------------------- + rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .DataType ( mst_aw_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_aw_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i( 1'b0 ), + .rr_i ( '0 ), + .req_i ( slv_aw_valids ), + .gnt_o ( slv_aw_readies ), + .data_i ( slv_aw_chans ), + .gnt_i ( aw_ready ), + .req_o ( aw_valid ), + .data_o ( mst_aw_chan ), + .idx_o ( ) + ); + + // control of the AW channel + always_comb begin + // default assignments + lock_aw_valid_d = lock_aw_valid_q; + load_aw_lock = 1'b0; + w_fifo_push = 1'b0; + mst_aw_valid = 1'b0; + aw_ready = 1'b0; + // had a downstream stall, be valid and send the AW along + if (lock_aw_valid_q) begin + mst_aw_valid = 1'b1; + // transaction + if (mst_aw_ready) begin + aw_ready = 1'b1; + lock_aw_valid_d = 1'b0; + load_aw_lock = 1'b1; + end + end else begin + if (!w_fifo_full && aw_valid) begin + mst_aw_valid = 1'b1; + w_fifo_push = 1'b1; + if (mst_aw_ready) begin + aw_ready = 1'b1; + end else begin + // go to lock if transaction not in this cycle + lock_aw_valid_d = 1'b1; + load_aw_lock = 1'b1; + end + end + end + end + + `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + + fifo_v3 #( + .FALL_THROUGH ( FallThrough ), + .DEPTH ( MaxWTrans ), + .dtype ( switch_id_t ) + ) i_w_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( test_i ), + .full_o ( w_fifo_full ), + .empty_o ( w_fifo_empty ), + .usage_o ( ), + .data_i ( mst_aw_chan.id[SlvAxiIDWidth+:MstIdxBits] ), + .push_i ( w_fifo_push ), + .data_o ( w_fifo_data ), + .pop_i ( w_fifo_pop ) + ); + + spill_register #( + .T ( mst_aw_chan_t ), + .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg + ) i_aw_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_aw_valid ), + .ready_o ( mst_aw_ready ), + .data_i ( mst_aw_chan ), + .valid_o ( mst_req_o.aw_valid ), + .ready_i ( mst_resp_i.aw_ready ), + .data_o ( mst_req_o.aw ) + ); + + //-------------------------------------- + // W Channel + //-------------------------------------- + // multiplexer + assign mst_w_chan = slv_w_chans[w_fifo_data]; + always_comb begin + // default assignments + mst_w_valid = 1'b0; + slv_w_readies = '0; + w_fifo_pop = 1'b0; + // control + if (!w_fifo_empty) begin + // connect the handshake + mst_w_valid = slv_w_valids[w_fifo_data]; + slv_w_readies[w_fifo_data] = mst_w_ready; + // pop FIFO on a last transaction + w_fifo_pop = slv_w_valids[w_fifo_data] & mst_w_ready & mst_w_chan.last; + end + end + + spill_register #( + .T ( w_chan_t ), + .Bypass ( ~SpillW ) + ) i_w_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_w_valid ), + .ready_o ( mst_w_ready ), + .data_i ( mst_w_chan ), + .valid_o ( mst_req_o.w_valid ), + .ready_i ( mst_resp_i.w_ready ), + .data_o ( mst_req_o.w ) + ); + + //-------------------------------------- + // B Channel + //-------------------------------------- + // replicate B channels + assign slv_b_chans = {NoSlvPorts{mst_b_chan}}; + // control B channel handshake + assign switch_b_id = mst_b_chan.id[SlvAxiIDWidth+:MstIdxBits]; + assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0; + + spill_register #( + .T ( mst_b_chan_t ), + .Bypass ( ~SpillB ) + ) i_b_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.b_valid ), + .ready_o ( mst_req_o.b_ready ), + .data_i ( mst_resp_i.b ), + .valid_o ( mst_b_valid ), + .ready_i ( slv_b_readies[switch_b_id] ), + .data_o ( mst_b_chan ) + ); + + //-------------------------------------- + // AR Channel + //-------------------------------------- + rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .DataType ( mst_ar_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_ar_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i( 1'b0 ), + .rr_i ( '0 ), + .req_i ( slv_ar_valids ), + .gnt_o ( slv_ar_readies ), + .data_i ( slv_ar_chans ), + .gnt_i ( ar_ready ), + .req_o ( ar_valid ), + .data_o ( mst_ar_chan ), + .idx_o ( ) + ); + + spill_register #( + .T ( mst_ar_chan_t ), + .Bypass ( ~SpillAr ) + ) i_ar_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( ar_valid ), + .ready_o ( ar_ready ), + .data_i ( mst_ar_chan ), + .valid_o ( mst_req_o.ar_valid ), + .ready_i ( mst_resp_i.ar_ready ), + .data_o ( mst_req_o.ar ) + ); + + //-------------------------------------- + // R Channel + //-------------------------------------- + // replicate R channels + assign slv_r_chans = {NoSlvPorts{mst_r_chan}}; + // R channel handshake control + assign switch_r_id = mst_r_chan.id[SlvAxiIDWidth+:MstIdxBits]; + assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0; + + spill_register #( + .T ( mst_r_chan_t ), + .Bypass ( ~SpillR ) + ) i_r_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.r_valid ), + .ready_o ( mst_req_o.r_ready ), + .data_i ( mst_resp_i.r ), + .valid_o ( mst_r_valid ), + .ready_i ( slv_r_readies[switch_r_id] ), + .data_o ( mst_r_chan ) + ); + end + +// pragma translate_off +`ifndef VERILATOR + initial begin + assert (SlvAxiIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!"); + assert (NoSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!"); + assert (MaxWTrans > 0) + else $fatal(1, "Maximum number of outstanding writes must be non-zero!"); + assert (MstAxiIDWidth >= SlvAxiIDWidth + $clog2(NoSlvPorts)) + else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!"); + // Assert ID widths (one slave is sufficient since they all have the same type). + assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of AW channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_reqs_i[0].ar.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of AR channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_resps_o[0].b.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of B channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_resps_o[0].r.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of R channel of slave ports does not match parameter!"); + assert ($unsigned($bits(mst_req_o.aw.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of AW channel of master port is wrong!"); + assert ($unsigned($bits(mst_req_o.ar.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of AR channel of master port is wrong!"); + assert ($unsigned($bits(mst_resp_i.b.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of B channel of master port is wrong!"); + assert ($unsigned($bits(mst_resp_i.r.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of R channel of master port is wrong!"); + end +`endif +// pragma translate_on +endmodule + +// interface wrap +`include "axi/assign.svh" +`include "axi/typedef.svh" +module axi_mux_intf #( + parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter int unsigned MST_AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports + // Maximum number of outstanding transactions per write + parameter int unsigned MAX_W_TRANS = 32'd8, + // if enabled, this multiplexer is purely combinatorial + parameter bit FALL_THROUGH = 1'b0, + // add spill register on write master ports, adds a cycle latency on write channels + parameter bit SPILL_AW = 1'b1, + parameter bit SPILL_W = 1'b0, + parameter bit SPILL_B = 1'b0, + // add spill register on read master ports, adds a cycle latency on read channels + parameter bit SPILL_AR = 1'b1, + parameter bit SPILL_R = 1'b0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable + AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports + AXI_BUS.Master mst // master port +); + + typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t; + typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + // channels typedef + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t) + + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t) + + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + + slv_req_t [NO_SLV_PORTS-1:0] slv_reqs; + slv_resp_t [NO_SLV_PORTS-1:0] slv_resps; + mst_req_t mst_req; + mst_resp_t mst_resp; + + for (genvar i = 0; i < NO_SLV_PORTS; i++) begin : gen_assign_slv_ports + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) + `AXI_ASSIGN_FROM_RESP(slv[i], slv_resps[i]) + end + + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_mux #( + .SlvAxiIDWidth ( SLV_AXI_ID_WIDTH ), + .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .w_chan_t ( w_chan_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports + .MaxWTrans ( MAX_W_TRANS ), + .FallThrough ( FALL_THROUGH ), + .SpillAw ( SPILL_AW ), + .SpillW ( SPILL_W ), + .SpillB ( SPILL_B ), + .SpillAr ( SPILL_AR ), + .SpillR ( SPILL_R ) + ) i_axi_mux ( + .clk_i ( clk_i ), // Clock + .rst_ni ( rst_ni ), // Asynchronous reset active low + .test_i ( test_i ), // Test Mode enable + .slv_reqs_i ( slv_reqs ), + .slv_resps_o ( slv_resps ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); +endmodule diff --git a/hw/deps/axi/src/axi_pkg.sv b/hw/deps/axi/src/axi_pkg.sv new file mode 100644 index 0000000..74e879d --- /dev/null +++ b/hw/deps/axi/src/axi_pkg.sv @@ -0,0 +1,311 @@ +// Copyright (c) 2014-2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Fabian Schuiki +// Andreas Kurth + +//! AXI Package +/// Contains all necessary type definitions, constants, and generally useful functions. +package axi_pkg; + /// AXI Transaction Burst Type. + typedef logic [1:0] burst_t; + /// AXI Transaction Response Type. + typedef logic [1:0] resp_t; + /// AXI Transaction Cacheability Type. + typedef logic [3:0] cache_t; + /// AXI Transaction Protection Type. + typedef logic [2:0] prot_t; + /// AXI Transaction Quality of Service Type. + typedef logic [3:0] qos_t; + /// AXI Transaction Region Type. + typedef logic [3:0] region_t; + /// AXI Transaction Length Type. + typedef logic [7:0] len_t; + /// AXI Transaction Size Type. + typedef logic [2:0] size_t; + /// AXI5 Atomic Operation Type. + typedef logic [5:0] atop_t; // atomic operations + /// AXI5 Non-Secure Address Identifier. + typedef logic [3:0] nsaid_t; + + /// In a fixed burst: + /// - The address is the same for every transfer in the burst. + /// - The byte lanes that are valid are constant for all beats in the burst. However, within + /// those byte lanes, the actual bytes that have `wstrb` asserted can differ for each beat in + /// the burst. + /// This burst type is used for repeated accesses to the same location such as when loading or + /// emptying a FIFO. + localparam BURST_FIXED = 2'b00; + /// In an incrementing burst, the address for each transfer in the burst is an increment of the + /// address for the previous transfer. The increment value depends on the size of the transfer. + /// For example, the address for each transfer in a burst with a size of 4 bytes is the previous + /// address plus four. + /// This burst type is used for accesses to normal sequential memory. + localparam BURST_INCR = 2'b01; + /// A wrapping burst is similar to an incrementing burst, except that the address wraps around to + /// a lower address if an upper address limit is reached. + /// The following restrictions apply to wrapping bursts: + /// - The start address must be aligned to the size of each transfer. + /// - The length of the burst must be 2, 4, 8, or 16 transfers. + localparam BURST_WRAP = 2'b10; + + /// Normal access success. Indicates that a normal access has been successful. Can also indicate + /// that an exclusive access has failed. + localparam RESP_OKAY = 2'b00; + /// Exclusive access okay. Indicates that either the read or write portion of an exclusive access + /// has been successful. + localparam RESP_EXOKAY = 2'b01; + /// Slave error. Used when the access has reached the slave successfully, but the slave wishes to + /// return an error condition to the originating master. + localparam RESP_SLVERR = 2'b10; + /// Decode error. Generated, typically by an interconnect component, to indicate that there is no + /// slave at the transaction address. + localparam RESP_DECERR = 2'b11; + + /// When this bit is asserted, the interconnect, or any component, can delay the transaction + /// reaching its final destination for any number of cycles. + localparam CACHE_BUFFERABLE = 4'b0001; + /// When HIGH, Modifiable indicates that the characteristics of the transaction can be modified. + /// When Modifiable is LOW, the transaction is Non-modifiable. + localparam CACHE_MODIFIABLE = 4'b0010; + /// When this bit is asserted, read allocation of the transaction is recommended but is not + /// mandatory. + localparam CACHE_RD_ALLOC = 4'b0100; + /// When this bit is asserted, write allocation of the transaction is recommended but is not + /// mandatory. + localparam CACHE_WR_ALLOC = 4'b1000; + + /// Maximum number of bytes per burst, as specified by `size` (see Table A3-2). + function automatic shortint unsigned num_bytes(size_t size); + return 1 << size; + endfunction + + /// An overly long address type. + /// It lets us define functions that work generically for shorter addresses. We rely on the + /// synthesizer to optimize the unused bits away. + typedef logic [127:0] largest_addr_t; + + /// Aligned address of burst (see A3-51). + function automatic largest_addr_t aligned_addr(largest_addr_t addr, size_t size); + return (addr >> size) << size; + endfunction + + /// Address of beat (see A3-51). + function automatic largest_addr_t + beat_addr(largest_addr_t addr, size_t size, shortint unsigned i_beat); + if (i_beat == 0) begin + return addr; + end else begin + return aligned_addr(addr, size) + i_beat * num_bytes(size); + end + endfunction + + /// Index of lowest beat in byte (see A3-51). + function automatic shortint unsigned + beat_lower_byte(largest_addr_t addr, size_t size, shortint unsigned strobe_width, + shortint unsigned i_beat); + largest_addr_t _addr = beat_addr(addr, size, i_beat); + return _addr - (_addr / strobe_width) * strobe_width; + endfunction + + /// Index of highest beat in byte (see A3-51). + function automatic shortint unsigned + beat_upper_byte(largest_addr_t addr, size_t size, shortint unsigned strobe_width, + shortint unsigned i_beat); + if (i_beat == 0) begin + return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width; + end else begin + return beat_lower_byte(addr, size, strobe_width, i_beat) + num_bytes(size) - 1; + end + endfunction + + /// Memory Type. + typedef enum logic [3:0] { + DEVICE_NONBUFFERABLE, + DEVICE_BUFFERABLE, + NORMAL_NONCACHEABLE_NONBUFFERABLE, + NORMAL_NONCACHEABLE_BUFFERABLE, + WTHRU_NOALLOCATE, + WTHRU_RALLOCATE, + WTHRU_WALLOCATE, + WTHRU_RWALLOCATE, + WBACK_NOALLOCATE, + WBACK_RALLOCATE, + WBACK_WALLOCATE, + WBACK_RWALLOCATE + } mem_type_t; + + /// Create an `AR_CACHE` field from a `mem_type_t` type. + function automatic logic [3:0] get_arcache(mem_type_t mtype); + unique case (mtype) + DEVICE_NONBUFFERABLE : return 4'b0000; + DEVICE_BUFFERABLE : return 4'b0001; + NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010; + NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011; + WTHRU_NOALLOCATE : return 4'b1010; + WTHRU_RALLOCATE : return 4'b1110; + WTHRU_WALLOCATE : return 4'b1010; + WTHRU_RWALLOCATE : return 4'b1110; + WBACK_NOALLOCATE : return 4'b1011; + WBACK_RALLOCATE : return 4'b1111; + WBACK_WALLOCATE : return 4'b1011; + WBACK_RWALLOCATE : return 4'b1111; + endcase // mtype + endfunction + + /// Create an `AW_CACHE` field from a `mem_type_t` type. + function automatic logic [3:0] get_awcache(mem_type_t mtype); + unique case (mtype) + DEVICE_NONBUFFERABLE : return 4'b0000; + DEVICE_BUFFERABLE : return 4'b0001; + NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010; + NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011; + WTHRU_NOALLOCATE : return 4'b0110; + WTHRU_RALLOCATE : return 4'b0110; + WTHRU_WALLOCATE : return 4'b1110; + WTHRU_RWALLOCATE : return 4'b1110; + WBACK_NOALLOCATE : return 4'b0111; + WBACK_RALLOCATE : return 4'b0111; + WBACK_WALLOCATE : return 4'b1111; + WBACK_RWALLOCATE : return 4'b1111; + endcase // mtype + endfunction + + // ATOP[5:0] + /// - Sends a single data value with an address. + /// - The target swaps the value at the addressed location with the data value that is supplied in + /// the transaction. + /// - The original data value at the addressed location is returned. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + /// - Inbound data size is the same as the outbound data size. + localparam ATOP_ATOMICSWAP = 6'b110000; + /// - Sends two data values, the compare value and the swap value, to the addressed location. + /// The compare and swap values are of equal size. + /// - The data value at the addressed location is checked against the compare value: + /// - If the values match, the swap value is written to the addressed location. + /// - If the values do not match, the swap value is not written to the addressed location. + /// - The original data value at the addressed location is returned. + /// - Outbound data size is 2, 4, 8, 16, or 32 bytes. + /// - Inbound data size is half of the outbound data size because the outbound data contains both + /// compare and swap values, whereas the inbound data has only the original data value. + localparam ATOP_ATOMICCMP = 6'b110001; + // ATOP[5:4] + /// Perform no atomic operation. + localparam ATOP_NONE = 2'b00; + /// - Sends a single data value with an address and the atomic operation to be performed. + /// - The target performs the operation using the sent data and value at the addressed location as + /// operands. + /// - The result is stored in the address location. + /// - A single response is given without data. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + localparam ATOP_ATOMICSTORE = 2'b01; + /// Sends a single data value with an address and the atomic operation to be performed. + /// - The original data value at the addressed location is returned. + /// - The target performs the operation using the sent data and value at the addressed location as + /// operands. + /// - The result is stored in the address location. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + /// - Inbound data size is the same as the outbound data size. + localparam ATOP_ATOMICLOAD = 2'b10; + // ATOP[3] + /// For AtomicStore and AtomicLoad transactions `AWATOP[3]` indicates the endianness that is + /// required for the atomic operation. The value of `AWATOP[3]` applies to arithmetic operations + /// only and is ignored for bitwise logical operations. + /// When deasserted, this bit indicates that the operation is little-endian. + localparam ATOP_LITTLE_END = 1'b0; + /// When asserted, this bit indicates that the operation is big-endian. + localparam ATOP_BIG_END = 1'b1; + // ATOP[2:0] + /// The value in memory is added to the sent data and the result stored in memory. + localparam ATOP_ADD = 3'b000; + /// Every set bit in the sent data clears the corresponding bit of the data in memory. + localparam ATOP_CLR = 3'b001; + /// Bitwise exclusive OR of the sent data and value in memory. + localparam ATOP_EOR = 3'b010; + /// Every set bit in the sent data sets the corresponding bit of the data in memory. + localparam ATOP_SET = 3'b011; + /// The value stored in memory is the maximum of the existing value and sent data. This operation + /// assumes signed data. + localparam ATOP_SMAX = 3'b100; + /// The value stored in memory is the minimum of the existing value and sent data. This operation + /// assumes signed data. + localparam ATOP_SMIN = 3'b101; + /// The value stored in memory is the maximum of the existing value and sent data. This operation + /// assumes unsigned data. + localparam ATOP_UMAX = 3'b110; + /// The value stored in memory is the minimum of the existing value and sent data. This operation + /// assumes unsigned data. + localparam ATOP_UMIN = 3'b111; + // ATOP[5] == 1'b1 indicated that an atomic transaction has a read response + // Ussage eg: if (req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin + localparam ATOP_R_RESP = 32'd5; + + // `xbar_latency_e` and `xbar_cfg_t` are documented in `doc/axi_xbar.md`. + /// Slice on Demux AW channel. + localparam logic [9:0] DemuxAw = (1 << 9); + /// Slice on Demux W channel. + localparam logic [9:0] DemuxW = (1 << 8); + /// Slice on Demux B channel. + localparam logic [9:0] DemuxB = (1 << 7); + /// Slice on Demux AR channel. + localparam logic [9:0] DemuxAr = (1 << 6); + /// Slice on Demux R channel. + localparam logic [9:0] DemuxR = (1 << 5); + /// Slice on Mux AW channel. + localparam logic [9:0] MuxAw = (1 << 4); + /// Slice on Mux W channel. + localparam logic [9:0] MuxW = (1 << 3); + /// Slice on Mux B channel. + localparam logic [9:0] MuxB = (1 << 2); + /// Slice on Mux AR channel. + localparam logic [9:0] MuxAr = (1 << 1); + /// Slice on Mux R channel. + localparam logic [9:0] MuxR = (1 << 0); + /// Latency configuration for `axi_xbar`. + typedef enum logic [9:0] { + NO_LATENCY = 10'b000_00_000_00, + CUT_SLV_AX = DemuxAw | DemuxAr, + CUT_MST_AX = MuxAw | MuxAr, + CUT_ALL_AX = DemuxAw | DemuxAr | MuxAw | MuxAr, + CUT_SLV_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR, + CUT_MST_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR, + CUT_ALL_PORTS = 10'b111_11_111_11 + } xbar_latency_e; + + /// Configuration for `axi_xbar`. + typedef struct packed { + int unsigned NoSlvPorts; + int unsigned NoMstPorts; + int unsigned MaxMstTrans; + int unsigned MaxSlvTrans; + bit FallThrough; + xbar_latency_e LatencyMode; + int unsigned AxiIdWidthSlvPorts; + int unsigned AxiIdUsedSlvPorts; + int unsigned AxiAddrWidth; + int unsigned AxiDataWidth; + int unsigned NoAddrRules; + } xbar_cfg_t; + + /// Commonly used rule types for `axi_xbar` (64-bit addresses). + typedef struct packed { + int unsigned idx; + logic [63:0] start_addr; + logic [63:0] end_addr; + } xbar_rule_64_t; + + /// Commonly used rule types for `axi_xbar` (32-bit addresses). + typedef struct packed { + int unsigned idx; + logic [31:0] start_addr; + logic [31:0] end_addr; + } xbar_rule_32_t; +endpackage diff --git a/hw/deps/axi/src/axi_serializer.sv b/hw/deps/axi/src/axi_serializer.sv new file mode 100644 index 0000000..5ff0d91 --- /dev/null +++ b/hw/deps/axi/src/axi_serializer.sv @@ -0,0 +1,294 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Andreas Kurth +// Wolfgang Roenninger + +`include "common_cells/registers.svh" + +/// Serialize all AXI transactions to a single ID (zero). +/// +/// This module contains one queue with slave port IDs for the read direction and one for the write +/// direction. These queues are used to reconstruct the ID of responses at the slave port. The +/// depth of each queue is defined by `MaxReadTxns` and `MaxWriteTxns`, respectively. +module axi_serializer #( + /// Maximum number of in flight read transactions. + parameter int unsigned MaxReadTxns = 32'd0, + /// Maximum number of in flight write transactions. + parameter int unsigned MaxWriteTxns = 32'd0, + /// AXI4+ATOP ID width. + parameter int unsigned AxiIdWidth = 32'd0, + /// AXI4+ATOP request struct definition. + parameter type req_t = logic, + /// AXI4+ATOP response struct definition. + parameter type resp_t = logic +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Slave port request + input req_t slv_req_i, + /// Slave port response + output resp_t slv_resp_o, + /// Master port request + output req_t mst_req_o, + /// Master port response + input resp_t mst_resp_i +); + + typedef logic [AxiIdWidth-1:0] id_t; + typedef enum logic [1:0] { + AtopIdle = 2'b00, + AtopDrain = 2'b01, + AtopExecute = 2'b10 + } state_e; + + logic rd_fifo_full, rd_fifo_empty, rd_fifo_push, rd_fifo_pop, + wr_fifo_full, wr_fifo_empty, wr_fifo_push, wr_fifo_pop; + id_t b_id, + r_id, ar_id; + state_e state_q, state_d; + + always_comb begin + // Default assignments + state_d = state_q; + rd_fifo_push = 1'b0; + wr_fifo_push = 1'b0; + + // Default, connect the channels + mst_req_o = slv_req_i; + slv_resp_o = mst_resp_i; + + // Serialize transactions -> tie downstream IDs to zero. + mst_req_o.aw.id = '0; + mst_req_o.ar.id = '0; + + // Reflect upstream ID in response. + ar_id = slv_req_i.ar.id; + slv_resp_o.b.id = b_id; + slv_resp_o.r.id = r_id; + + // Default, cut the AW/AR handshaking + mst_req_o.ar_valid = 1'b0; + slv_resp_o.ar_ready = 1'b0; + mst_req_o.aw_valid = 1'b0; + slv_resp_o.aw_ready = 1'b0; + + unique case (state_q) + AtopIdle, AtopExecute: begin + + // Wait until the ATOP response(s) have been sent back upstream. + if (state_q == AtopExecute) begin + if ((wr_fifo_empty && rd_fifo_empty) || (wr_fifo_pop && rd_fifo_pop) || + (wr_fifo_empty && rd_fifo_pop) || (wr_fifo_pop && rd_fifo_empty)) begin + state_d = AtopIdle; + end + end + + // This part lets new Transactions through, if no ATOP is underway or the last ATOP + // response has been transmitted. + if ((state_q == AtopIdle) || (state_d == AtopIdle)) begin + // Gate AR handshake with ready output of Read FIFO. + mst_req_o.ar_valid = slv_req_i.ar_valid & ~rd_fifo_full; + slv_resp_o.ar_ready = mst_resp_i.ar_ready & ~rd_fifo_full; + rd_fifo_push = mst_req_o.ar_valid & mst_resp_i.ar_ready; + if (slv_req_i.aw_valid) begin + if (slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin + // Normal operation + // Gate AW handshake with ready output of Write FIFO. + mst_req_o.aw_valid = ~wr_fifo_full; + slv_resp_o.aw_ready = mst_resp_i.aw_ready & ~wr_fifo_full; + wr_fifo_push = mst_req_o.aw_valid & mst_resp_i.aw_ready; + end else begin + // Atomic Operation received, go to drain state, when both channels are ready + // Wait for finished or no AR beat + if (!mst_req_o.ar_valid || (mst_req_o.ar_valid && mst_resp_i.ar_ready)) begin + state_d = AtopDrain; + end + end + end + end + end + AtopDrain: begin + // Send the ATOP AW when the last open transaction terminates + if (wr_fifo_empty && rd_fifo_empty) begin + mst_req_o.aw_valid = 1'b1; + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + wr_fifo_push = mst_resp_i.aw_ready; + if (slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin + // Overwrite the read ID with the one from AW + ar_id = slv_req_i.aw.id; + rd_fifo_push = mst_resp_i.aw_ready; + end + if (mst_resp_i.aw_ready) begin + state_d = AtopExecute; + end + end + end + default : /* do nothing */; + endcase + + // Gate B handshake with empty flag output of Write FIFO. + slv_resp_o.b_valid = mst_resp_i.b_valid & ~wr_fifo_empty; + mst_req_o.b_ready = slv_req_i.b_ready & ~wr_fifo_empty; + + // Gate R handshake with empty flag output of Read FIFO. + slv_resp_o.r_valid = mst_resp_i.r_valid & ~rd_fifo_empty; + mst_req_o.r_ready = slv_req_i.r_ready & ~rd_fifo_empty; + end + + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), // No fall-through as response has to come a cycle later anyway + .DEPTH ( MaxReadTxns ), + .dtype ( id_t ) + ) i_rd_id_fifo ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .data_i ( ar_id ), + .push_i ( rd_fifo_push ), + .full_o ( rd_fifo_full ), + .data_o ( r_id ), + .empty_o ( rd_fifo_empty ), + .pop_i ( rd_fifo_pop ), + .usage_o ( /*not used*/ ) + ); + // Assign as this condition is needed in FSM + assign rd_fifo_pop = slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last; + + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .DEPTH ( MaxWriteTxns ), + .dtype ( id_t ) + ) i_wr_id_fifo ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .data_i ( slv_req_i.aw.id ), + .push_i ( wr_fifo_push ), + .full_o ( wr_fifo_full ), + .data_o ( b_id ), + .empty_o ( wr_fifo_empty ), + .pop_i ( wr_fifo_pop ), + .usage_o ( /*not used*/ ) + ); + // Assign as this condition is needed in FSM + assign wr_fifo_pop = slv_resp_o.b_valid & slv_req_i.b_ready; + + `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni) + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (AxiIdWidth >= 1) else $fatal(1, "AXI ID width must be at least 1!"); + assert (MaxReadTxns >= 1) + else $fatal(1, "Maximum number of read transactions must be >= 1!"); + assert (MaxWriteTxns >= 1) + else $fatal(1, "Maximum number of write transactions must be >= 1!"); + end + default disable iff (~rst_ni); + aw_lost : assert property( @(posedge clk_i) + (slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready)) + else $error("AW beat lost."); + w_lost : assert property( @(posedge clk_i) + (slv_req_i.w_valid & slv_resp_o.w_ready |-> mst_req_o.w_valid & mst_resp_i.w_ready)) + else $error("W beat lost."); + b_lost : assert property( @(posedge clk_i) + (mst_resp_i.b_valid & mst_req_o.b_ready |-> slv_resp_o.b_valid & slv_req_i.b_ready)) + else $error("B beat lost."); + ar_lost : assert property( @(posedge clk_i) + (slv_req_i.ar_valid & slv_resp_o.ar_ready |-> mst_req_o.ar_valid & mst_resp_i.ar_ready)) + else $error("AR beat lost."); + r_lost : assert property( @(posedge clk_i) + (mst_resp_i.r_valid & mst_req_o.r_ready |-> slv_resp_o.r_valid & slv_req_i.r_ready)) + else $error("R beat lost."); +`endif +// pragma translate_on +endmodule + +`include "axi/typedef.svh" +`include "axi/assign.svh" +/// Serialize all AXI transactions to a single ID (zero), interface version. +module axi_serializer_intf #( + /// AXI4+ATOP ID width. + parameter int unsigned AXI_ID_WIDTH = 32'd0, + /// AXI4+ATOP address width. + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + /// AXI4+ATOP data width. + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + /// AXI4+ATOP user width. + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// Maximum number of in flight read transactions. + parameter int unsigned MAX_READ_TXNS = 32'd0, + /// Maximum number of in flight write transactions. + parameter int unsigned MAX_WRITE_TXNS = 32'd0 +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// AXI4+ATOP Slave modport + AXI_BUS.Slave slv, + /// AXI4+ATOP Master modport + AXI_BUS.Master mst +); + + typedef logic [AXI_ID_WIDTH -1:0] id_t; + typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; + typedef logic [AXI_DATA_WIDTH -1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH -1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + req_t slv_req, mst_req; + resp_t slv_resp, mst_resp; + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_serializer #( + .MaxReadTxns ( MAX_READ_TXNS ), + .MaxWriteTxns ( MAX_WRITE_TXNS ), + .AxiIdWidth ( AXI_ID_WIDTH ), + .req_t ( req_t ), + .resp_t ( resp_t ) + ) i_axi_serializer ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI address width must be at least 1!"); + assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI data width must be at least 1!"); + assert (AXI_ID_WIDTH >= 1) else $fatal(1, "AXI ID width must be at least 1!"); + assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); + assert (MAX_READ_TXNS >= 1) + else $fatal(1, "Maximum number of read transactions must be >= 1!"); + assert (MAX_WRITE_TXNS >= 1) + else $fatal(1, "Maximum number of write transactions must be >= 1!"); + end +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/axi/src/axi_xbar.sv b/hw/deps/axi/src/axi_xbar.sv new file mode 100644 index 0000000..5d0b79c --- /dev/null +++ b/hw/deps/axi/src/axi_xbar.sv @@ -0,0 +1,312 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. +// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. +module axi_xbar #( + parameter axi_pkg::xbar_cfg_t Cfg = '0, + parameter type slv_aw_chan_t = logic, + parameter type mst_aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type slv_b_chan_t = logic, + parameter type mst_b_chan_t = logic, + parameter type slv_ar_chan_t = logic, + parameter type mst_ar_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type mst_r_chan_t = logic, + parameter type slv_req_t = logic, + parameter type slv_resp_t = logic, + parameter type mst_req_t = logic, + parameter type mst_resp_t = logic, + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + input logic clk_i, + input logic rst_ni, + input logic test_i, + input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, + output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, + output mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, + input mst_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_mst_port_i +); + + typedef logic [Cfg.AxiAddrWidth-1:0] addr_t; + // to account for the decoding error slave + typedef logic [$clog2(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t; + + // signals from the axi_demuxes, one index more for decode error + slv_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; + slv_resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; + + // signals into the axi_muxes, are of type slave as the multiplexer extends the ID + slv_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; + slv_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux + logic [$clog2(Cfg.NoMstPorts)-1:0] dec_aw, dec_ar; + mst_port_idx_t slv_aw_select, slv_ar_select; + logic dec_aw_valid, dec_aw_error; + logic dec_ar_valid, dec_ar_error; + + addr_decode #( + .NoIndices ( Cfg.NoMstPorts ), + .NoRules ( Cfg.NoAddrRules ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) + ) i_axi_aw_decode ( + .addr_i ( slv_ports_req_i[i].aw.addr ), + .addr_map_i ( addr_map_i ), + .idx_o ( dec_aw ), + .dec_valid_o ( dec_aw_valid ), + .dec_error_o ( dec_aw_error ), + .en_default_idx_i ( en_default_mst_port_i[i] ), + .default_idx_i ( default_mst_port_i[i] ) + ); + + addr_decode #( + .NoIndices ( Cfg.NoMstPorts ), + .addr_t ( addr_t ), + .NoRules ( Cfg.NoAddrRules ), + .rule_t ( rule_t ) + ) i_axi_ar_decode ( + .addr_i ( slv_ports_req_i[i].ar.addr ), + .addr_map_i ( addr_map_i ), + .idx_o ( dec_ar ), + .dec_valid_o ( dec_ar_valid ), + .dec_error_o ( dec_ar_error ), + .en_default_idx_i ( en_default_mst_port_i[i] ), + .default_idx_i ( default_mst_port_i[i] ) + ); + + assign slv_aw_select = (dec_aw_error) ? + mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_aw); + assign slv_ar_select = (dec_ar_error) ? + mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_ar); + + // make sure that the default slave does not get changed, if there is an unserved Ax + // pragma translate_off + `ifndef VERILATOR + default disable iff (~rst_ni); + default_aw_mst_port_en: assert property( + @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) + |=> $stable(en_default_mst_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mst port\ + enable, when there is an unserved Aw beat. Slave Port: %0d", i)); + default_aw_mst_port: assert property( + @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) + |=> $stable(default_mst_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mst port\ + when there is an unserved Aw beat. Slave Port: %0d", i)); + default_ar_mst_port_en: assert property( + @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready) + |=> $stable(en_default_mst_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the enable, when\ + there is an unserved Ar beat. Slave Port: %0d", i)); + default_ar_mst_port: assert property( + @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready) + |=> $stable(default_mst_port_i[i])) + else $fatal (1, $sformatf("It is not allowed to change the default mst port\ + when there is an unserved Ar beat. Slave Port: %0d", i)); + `endif + // pragma translate_on + axi_demux #( + .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), // ID Width + .aw_chan_t ( slv_aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( slv_b_chan_t ), // B Channel Type + .ar_chan_t ( slv_ar_chan_t ), // AR Channel Type + .r_chan_t ( slv_r_chan_t ), // R Channel Type + .req_t ( slv_req_t ), + .resp_t ( slv_resp_t ), + .NoMstPorts ( Cfg.NoMstPorts + 1 ), + .MaxTrans ( Cfg.MaxMstTrans ), + .AxiLookBits ( Cfg.AxiIdUsedSlvPorts ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[9] ), + .SpillW ( Cfg.LatencyMode[8] ), + .SpillB ( Cfg.LatencyMode[7] ), + .SpillAr ( Cfg.LatencyMode[6] ), + .SpillR ( Cfg.LatencyMode[5] ) + ) i_axi_demux ( + .clk_i, // Clock + .rst_ni, // Asynchronous reset active low + .test_i, // Testmode enable + .slv_req_i ( slv_ports_req_i[i] ), + .slv_aw_select_i ( slv_aw_select ), + .slv_ar_select_i ( slv_ar_select ), + .slv_resp_o ( slv_ports_resp_o[i] ), + .mst_reqs_o ( slv_reqs[i] ), + .mst_resps_i ( slv_resps[i] ) + ); + + axi_err_slv #( + .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), + .req_t ( slv_req_t ), + .resp_t ( slv_resp_t ), + .Resp ( axi_pkg::RESP_DECERR ), + .ATOPs ( 1'b1 ), + .MaxTrans ( 4 ) // Transactions terminate at this slave, so minimize + // resource consumption by accepting only a few + // transactions at a time. + ) i_axi_err_slv ( + .clk_i, // Clock + .rst_ni, // Asynchronous reset active low + .test_i, // Testmode enable + // slave port + .slv_req_i ( slv_reqs[i][Cfg.NoMstPorts] ), + .slv_resp_o ( slv_resps[i][Cfg.NoMstPorts] ) + ); + end + + // cross all channels + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_xbar_slv_cross + for (genvar j = 0; j < Cfg.NoMstPorts; j++) begin : gen_xbar_mst_cross + assign mst_reqs[j][i] = slv_reqs[i][j]; + assign slv_resps[i][j] = mst_resps[j][i]; + end + end + + for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux + axi_mux #( + .SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts ), // ID width of the slave ports + .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .w_chan_t ( w_chan_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module + .MaxWTrans ( Cfg.MaxSlvTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[4] ), + .SpillW ( Cfg.LatencyMode[3] ), + .SpillB ( Cfg.LatencyMode[2] ), + .SpillAr ( Cfg.LatencyMode[1] ), + .SpillR ( Cfg.LatencyMode[0] ) + ) i_axi_mux ( + .clk_i, // Clock + .rst_ni, // Asynchronous reset active low + .test_i, // Test Mode enable + .slv_reqs_i ( mst_reqs[i] ), + .slv_resps_o ( mst_resps[i] ), + .mst_req_o ( mst_ports_req_o[i] ), + .mst_resp_i ( mst_ports_resp_i[i] ) + ); + end + + // pragma translate_off + `ifndef VERILATOR + initial begin : check_params + id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else + $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); + id_slv_resp_ports: assert ($bits(slv_ports_resp_o[0].r.id) == Cfg.AxiIdWidthSlvPorts) else + $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); + end + `endif + // pragma translate_on +endmodule + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module axi_xbar_intf #( + parameter int unsigned AXI_USER_WIDTH = 0, + parameter axi_pkg::xbar_cfg_t Cfg = '0, + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + input logic clk_i, + input logic rst_ni, + input logic test_i, + AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], + AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_mst_port_i +); + + localparam int unsigned AxiIdWidthMstPorts = Cfg.AxiIdWidthSlvPorts + $clog2(Cfg.NoSlvPorts); + + typedef logic [AxiIdWidthMstPorts -1:0] id_mst_t; + typedef logic [Cfg.AxiIdWidthSlvPorts -1:0] id_slv_t; + typedef logic [Cfg.AxiAddrWidth -1:0] addr_t; + typedef logic [Cfg.AxiDataWidth -1:0] data_t; + typedef logic [Cfg.AxiDataWidth/8 -1:0] strb_t; + typedef logic [AXI_USER_WIDTH -1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + mst_req_t [Cfg.NoMstPorts-1:0] mst_reqs; + mst_resp_t [Cfg.NoMstPorts-1:0] mst_resps; + slv_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; + slv_resp_t [Cfg.NoSlvPorts-1:0] slv_resps; + + for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst + `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) + `AXI_ASSIGN_TO_RESP(mst_resps[i], mst_ports[i]) + end + + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) + `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) + end + + axi_xbar #( + .Cfg (Cfg), + .slv_aw_chan_t ( slv_aw_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .rule_t ( rule_t ) + ) i_xbar ( + .clk_i, + .rst_ni, + .test_i, + .slv_ports_req_i (slv_reqs ), + .slv_ports_resp_o (slv_resps), + .mst_ports_req_o (mst_reqs ), + .mst_ports_resp_i (mst_resps), + .addr_map_i, + .en_default_mst_port_i, + .default_mst_port_i + ); + +endmodule diff --git a/hw/deps/axi/src/dma/axi_dma_backend.sv b/hw/deps/axi/src/dma/axi_dma_backend.sv new file mode 100644 index 0000000..1c072d9 --- /dev/null +++ b/hw/deps/axi/src/dma/axi_dma_backend.sv @@ -0,0 +1,588 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +/// The backend implements the generic 1D data transfer on an AXI BUS +module axi_dma_backend #( + /// Data width of the AXI bus + parameter int unsigned DataWidth = -1, + /// Address width of the AXI bus + parameter int unsigned AddrWidth = -1, + /// ID width of the AXI bus + parameter int unsigned IdWidth = -1, + /// Number of AX beats that can be in-flight + parameter int unsigned AxReqFifoDepth = -1, + /// Number of generic 1D requests that can be buffered + parameter int unsigned TransFifoDepth = -1, + /// Number of elements the realignment buffer can hold. To achieve + /// full performance a depth of 3 is minimally required. + parameter int unsigned BufferDepth = -1, + /// AXI4+ATOP request struct definition. + parameter type axi_req_t = logic, + /// AXI4+ATOP response struct definition. + parameter type axi_res_t = logic, + /// Arbitrary 1D burst request definition: + /// - `id`: the AXI id used - this id should be constant, as the DMA does not support reordering + /// - `src`, `dst`: source and destination address, same width as the AXI 4 channels + /// - `num_bytes`: the length of the contiguous 1D transfer requested, can be up to 32/64 bit long + /// num_bytes will be interpreted as an unsigned number + /// A value of 0 will cause the backend to discard the transfer prematurely + /// - `src_cache`, `dst_cache`: the configuration of the cache fields in the AX beats + /// - `src_burst`, `dst_burst`: currently only incremental bursts are supported (`2'b01`) + /// - `decouple_rw`: if set to true, there is no longer exactly one AXI write_request issued for + /// every read request. This mode can improve performance of unaligned transfers when crossing + /// the AXI page boundaries. + /// - `deburst`: if set, the DMA will split all bursts in single transfers + /// - `serialize`: if set, the DMA will only send AX belonging to a given Arbitrary 1D burst request + /// at a time. This is default behavior to prevent deadlocks. + parameter type burst_req_t = logic, + /// Give each DMA backend a unique id + parameter int unsigned DmaIdWidth = -1, + /// Enable or disable tracing + parameter bit DmaTracing = 0 + +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// AXI4+ATOP master request + output axi_req_t axi_dma_req_o, + /// AXI4+ATOP master response + input axi_res_t axi_dma_res_i, + /// Arbitrary 1D burst request + input burst_req_t burst_req_i, + /// Handshake: 1D burst request is valid + input logic valid_i, + /// Handshake: 1D burst can be accepted + output logic ready_o, + /// High if the backend is idle + output logic backend_idle_o, + /// Event: a 1D burst request has completed + output logic trans_complete_o, + /// unique DMA id + input logic [DmaIdWidth-1:0] dma_id_i +); + + /// Number of bytes per word + localparam int unsigned StrobeWidth = DataWidth / 8; + /// Offset width + localparam int unsigned OffsetWidth = $clog2(StrobeWidth); + /// Offset type + typedef logic [OffsetWidth-1:0] offset_t; + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + + /// id: AXI id + /// last: last transaction in burst + /// address: address of burst + /// length: burst length + /// size: bytes in each burst + /// burst: burst type; only INC supported + /// cache: cache type + typedef struct packed { + axi_id_t id; + logic last; + addr_t addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + axi_pkg::cache_t cache; + } desc_ax_t; + + /// offset: initial misalignment + /// tailer: final misalignment + /// shift: amount the data needs to be shifted to realign it + typedef struct packed { + offset_t offset; + offset_t tailer; + offset_t shift; + } desc_r_t; + + /// offset: initial misalignment + /// tailer: final misalignment + /// num_beats: number of beats in the burst + /// is_single: burst length is 0 + typedef struct packed { + offset_t offset; + offset_t tailer; + axi_pkg::len_t num_beats; + logic is_single; + } desc_w_t; + + /// Write request definition + typedef struct packed { + desc_ax_t aw; + desc_w_t w; + } write_req_t; + + /// Read request definition + typedef struct packed { + desc_ax_t ar; + desc_r_t r; + } read_req_t; + + //-------------------------------------- + // Assertions + //-------------------------------------- + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (DataWidth inside {16, 32, 64, 128, 256, 512, 1024}) + else $fatal(1, "16 <= DataWidth <= 1024"); + assert (AddrWidth >= 32 & AddrWidth <= 128) /* this is outside AXI4 specs -> be careful! */ + else $fatal(1, " 32 <= AddrWidth <= 128"); + end + `endif + // pragma translate_on + + //-------------------------------------- + // Request Fifo + //-------------------------------------- + burst_req_t burst_req; + logic burst_req_empty; + logic burst_req_pop; + logic burst_req_full; + + // buffer the input requests in a fifo + fifo_v3 #( + .dtype ( burst_req_t ), + .DEPTH ( TransFifoDepth ) + ) i_burst_request_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( 1'b0 ), + .full_o ( burst_req_full ), + .empty_o ( burst_req_empty ), + .usage_o ( ), + .data_i ( burst_req_i ), + .push_i ( valid_i && ready_o ), + .data_o ( burst_req ), + .pop_i ( burst_req_pop ) + ); + + assign ready_o = !burst_req_full; + + //-------------------------------------- + // Burst reshaper + //-------------------------------------- + write_req_t write_req; + read_req_t read_req; + + logic read_req_valid; + logic read_req_ready; + logic write_req_valid; + logic write_req_ready; + + // send the next burst either immediately or once the last burst + // has been completed. The former mode is not AXI4+ATOP spec + // conform and may result in deadlocks! + logic in_flight_d, in_flight_q; + logic burst_valid; + always_comb begin : proc_select_burst_valid + if (burst_req.serialize) begin + // AXI4-conform behavior. As both the buffer and the memory system + // assume in-order operation. + burst_valid = ~burst_req_empty & (~in_flight_q | trans_complete_o); + end else begin + // legacy, non-AXI4-conform behavior. Send as many AX as possible + // This can lead to deadlocks due to in-memory reordering + burst_valid = ~burst_req_empty; + end + end + + // transforms arbitrary burst into AXI conform bursts + axi_dma_burst_reshaper #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .IdWidth ( IdWidth ), + .burst_req_t ( burst_req_t ), + .read_req_t ( read_req_t ), + .write_req_t ( write_req_t ) + ) i_axi_dma_burst_reshaper ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .burst_req_i ( burst_req ), + .valid_i ( burst_valid ), + .ready_o ( burst_req_pop ), + .write_req_o ( write_req ), + .read_req_o ( read_req ), + .r_valid_o ( read_req_valid ), + .r_ready_i ( read_req_ready ), + .w_valid_o ( write_req_valid ), + .w_ready_i ( write_req_ready ) + ); + + //-------------------------------------- + // Data mover + //-------------------------------------- + axi_dma_data_mover #( + .DataWidth ( DataWidth ), + .ReqFifoDepth ( AxReqFifoDepth ), + .BufferDepth ( BufferDepth ), + .read_req_t ( read_req_t ), + .write_req_t ( write_req_t ), + .axi_req_t ( axi_req_t ), + .axi_res_t ( axi_res_t ), + .desc_ax_t ( desc_ax_t ), + .desc_r_t ( desc_r_t ), + .desc_w_t ( desc_w_t ) + ) i_axi_dma_data_mover ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .axi_dma_req_o ( axi_dma_req_o ), + .axi_dma_res_i ( axi_dma_res_i ), + .read_req_i ( read_req ), + .write_req_i ( write_req ), + .r_valid_i ( read_req_valid ), + .r_ready_o ( read_req_ready ), + .w_valid_i ( write_req_valid ), + .w_ready_o ( write_req_ready ), + .data_mover_idle_o ( backend_idle_o ), + .trans_complete_o ( trans_complete_o ) + ); + + //-------------------------------------- + // In-flight check + //-------------------------------------- + // to conform to the AXI4+ATOP spec: only send a burst + // once the last one has been completed . This check can be overridden + always_comb begin : proc_in_flight_check + + // default: last state + in_flight_d = in_flight_q; + + // new transfer: set in-flight to one + if (burst_req_pop & ~burst_req_empty) begin + in_flight_d = 1; + end else begin + // no new transfer and the old retires -> idle + if (trans_complete_o) begin + in_flight_d = 0; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_in_flight_check_state + if(~rst_ni) begin + in_flight_q <= 0; + end else begin + in_flight_q <= in_flight_d; + end + end + + //-------------------------------------- + // Tracer + //-------------------------------------- + //pragma translate_off + `ifndef SYNTHESYS + `ifndef VERILATOR + generate if (DmaTracing) begin : gen_dma_tracer + string fn; + integer f; + + logic [DataWidth/8-1:0][BufferDepth-1:0][7:0] buffer_mem; + + // open file + initial begin + #1; + $sformat(fn, "dma_trace_%05x.log", dma_id_i); + f = $fopen(fn, "w"); + $display("[Tracer] Logging DMA %d to %s", dma_id_i, fn); + end + + // access buffer memory storage + for(genvar d = 0; d < BufferDepth; d++) begin + for(genvar i = 0; i < DataWidth/8-1; i++) begin + assign buffer_mem[i][d] = + i_axi_dma_data_mover.i_axi_dma_data_path.fifo_buffer[i].i_fifo_buffer.mem_q[d]; + end + end + + // do the tracing + always_ff @(posedge clk_i) begin : proc_tracer + // dict + automatic longint dma_meta [string]; + automatic longint dma_backend [string]; + automatic longint dma_burst_res [string]; + automatic longint dma_data_mover [string]; + automatic logic [DataWidth-1:0] dma_data_path [string]; + automatic string dma_string; + + // start of python dict + dma_string = "{"; + + // we do not dump while reset + if (rst_ni) begin + + // commented signals are currently not used by the python golden model :) + + //-------------------------------------- + // Metadata + //-------------------------------------- + dma_meta = '{ + // time + "time" : $time(), + "DataWidth" : DataWidth, + "AddrWidth" : AddrWidth, + "IdWidth" : IdWidth, + "AxReqFifoDepth" : AxReqFifoDepth, + "TransFifoDepth" : TransFifoDepth, + "BufferDepth" : BufferDepth + }; + + //-------------------------------------- + // Backend + //-------------------------------------- + dma_backend = '{ + // dma backend interface + "backend_burst_req_id" : burst_req_i.id, + "backend_burst_req_src" : burst_req_i.src, + "backend_burst_req_dst" : burst_req_i.dst, + "backend_burst_req_num_bytes" : burst_req_i.num_bytes, + // "backend_burst_req_cache_src" : burst_req_i.cache_src, + // "backend_burst_req_cache_dst" : burst_req_i.cache_dst, + // "backend_burst_req_burst_src" : burst_req_i.burst_src, + // "backend_burst_req_burst_dst" : burst_req_i.burst_dst, + "backend_burst_req_burst_decouple_rw" : burst_req_i.decouple_rw, + "backend_burst_req_burst_deburst" : burst_req_i.deburst, + "backend_burst_req_valid" : valid_i, + "backend_burst_req_ready" : ready_o, + "backend_idle" : backend_idle_o, + "transfer_completed" : trans_complete_o + }; + + //-------------------------------------- + // Burst Reshaper + //-------------------------------------- + dma_burst_res = '{ + // burst request + "burst_reshaper_burst_req_id" : i_axi_dma_burst_reshaper.burst_req_i.id, + "burst_reshaper_burst_req_src" : i_axi_dma_burst_reshaper.burst_req_i.src, + "burst_reshaper_burst_req_dst" : i_axi_dma_burst_reshaper.burst_req_i.dst, + "burst_reshaper_burst_req_num_bytes" : i_axi_dma_burst_reshaper.burst_req_i.num_bytes, + // "burst_reshaper_burst_req_cache_src" : i_axi_dma_burst_reshaper.burst_req_i.cache_src, + // "burst_reshaper_burst_req_cache_dst" : i_axi_dma_burst_reshaper.burst_req_i.cache_dst, + // "burst_reshaper_burst_req_burst_src" : i_axi_dma_burst_reshaper.burst_req_i.burst_src, + // "burst_reshaper_burst_req_burst_dst" : i_axi_dma_burst_reshaper.burst_req_i.burst_dst, + "burst_reshaper_burst_req_decouple_rw" : i_axi_dma_burst_reshaper.burst_req_i.decouple_rw, + "burst_reshaper_burst_req_deburst" : i_axi_dma_burst_reshaper.burst_req_i.deburst, + "burst_reshaper_burst_req_valid" : i_axi_dma_burst_reshaper.valid_i, + "burst_reshaper_burst_req_ready" : i_axi_dma_burst_reshaper.ready_o, + // write request + "burst_reshaper_write_req_aw_id" : i_axi_dma_burst_reshaper.write_req_o.aw.id, + "burst_reshaper_write_req_aw_last" : i_axi_dma_burst_reshaper.write_req_o.aw.last, + "burst_reshaper_write_req_aw_addr" : i_axi_dma_burst_reshaper.write_req_o.aw.addr, + "burst_reshaper_write_req_aw_len" : i_axi_dma_burst_reshaper.write_req_o.aw.len, + "burst_reshaper_write_req_aw_size" : i_axi_dma_burst_reshaper.write_req_o.aw.size, + "burst_reshaper_write_req_aw_burst" : i_axi_dma_burst_reshaper.write_req_o.aw.burst, + "burst_reshaper_write_req_aw_cache" : i_axi_dma_burst_reshaper.write_req_o.aw.cache, + "burst_reshaper_write_req_w_offset" : i_axi_dma_burst_reshaper.write_req_o.w.offset, + "burst_reshaper_write_req_w_tailer" : i_axi_dma_burst_reshaper.write_req_o.w.tailer, + "burst_reshaper_write_req_w_num_beats" : i_axi_dma_burst_reshaper.write_req_o.w.num_beats, + // "burst_reshaper_write_req_w_is_single" : i_axi_dma_burst_reshaper.write_req_o.w.is_single, + "burst_reshaper_write_req_valid" : i_axi_dma_burst_reshaper.w_valid_o, + "burst_reshaper_write_req_ready" : i_axi_dma_burst_reshaper.w_ready_i, + // read request + "burst_reshaper_read_req_ar_id" : i_axi_dma_burst_reshaper.read_req_o.ar.id, + "burst_reshaper_read_req_ar_last" : i_axi_dma_burst_reshaper.read_req_o.ar.last, + "burst_reshaper_read_req_ar_addr" : i_axi_dma_burst_reshaper.read_req_o.ar.addr, + "burst_reshaper_read_req_ar_len" : i_axi_dma_burst_reshaper.read_req_o.ar.len, + "burst_reshaper_read_req_ar_size" : i_axi_dma_burst_reshaper.read_req_o.ar.size, + "burst_reshaper_read_req_ar_burst" : i_axi_dma_burst_reshaper.read_req_o.ar.burst, + "burst_reshaper_read_req_ar_cache" : i_axi_dma_burst_reshaper.read_req_o.ar.cache, + "burst_reshaper_read_req_r_offset" : i_axi_dma_burst_reshaper.read_req_o.r.offset, + "burst_reshaper_read_req_r_tailer" : i_axi_dma_burst_reshaper.read_req_o.r.tailer, + "burst_reshaper_read_req_r_shift" : i_axi_dma_burst_reshaper.read_req_o.r.shift, + "burst_reshaper_read_req_valid" : i_axi_dma_burst_reshaper.r_valid_o, + "burst_reshaper_read_req_ready" : i_axi_dma_burst_reshaper.r_ready_i// , + // current burst + // "burst_reshaper_burst_src_id" : i_axi_dma_burst_reshaper.burst_q.src.id, + // "burst_reshaper_burst_src_addr" : i_axi_dma_burst_reshaper.burst_q.src.addr, + // "burst_reshaper_burst_src_num_bytes" : i_axi_dma_burst_reshaper.burst_q.src.num_bytes, + // "burst_reshaper_burst_src_cache" : i_axi_dma_burst_reshaper.burst_q.src.cache, + // "burst_reshaper_burst_src_burst" : i_axi_dma_burst_reshaper.burst_q.src.burst, + // "burst_reshaper_burst_src_valid" : i_axi_dma_burst_reshaper.burst_q.src.valid, + // "burst_reshaper_burst_dst_id" : i_axi_dma_burst_reshaper.burst_q.dst.id, + // "burst_reshaper_burst_dst_addr" : i_axi_dma_burst_reshaper.burst_q.dst.addr, + // "burst_reshaper_burst_dst_num_bytes" : i_axi_dma_burst_reshaper.burst_q.dst.num_bytes, + // "burst_reshaper_burst_dst_cache" : i_axi_dma_burst_reshaper.burst_q.dst.cache, + // "burst_reshaper_burst_dst_burst" : i_axi_dma_burst_reshaper.burst_q.dst.burst, + // "burst_reshaper_burst_dst_valid" : i_axi_dma_burst_reshaper.burst_q.dst.valid, + // "burst_reshaper_burst_shift" : i_axi_dma_burst_reshaper.burst_q.shift, + // "burst_reshaper_burst_decouple_rw" : i_axi_dma_burst_reshaper.burst_q.decouple_rw, + // "burst_reshaper_burst_deburst" : i_axi_dma_burst_reshaper.burst_q.deburst, + // page + // "burst_reshaper_r_page_offset" : i_axi_dma_burst_reshaper.r_page_offset, + // "burst_reshaper_r_num_bytes_to_pb" : i_axi_dma_burst_reshaper.r_num_bytes_to_pb, + // "burst_reshaper_w_page_offset" : i_axi_dma_burst_reshaper.w_page_offset, + // "burst_reshaper_w_num_bytes_to_pb" : i_axi_dma_burst_reshaper.w_num_bytes_to_pb, + // "burst_reshaper_c_num_bytes_to_pb" : i_axi_dma_burst_reshaper.c_num_bytes_to_pb, + // issue process + // "burst_reshaper_r_num_bytes_possible" : i_axi_dma_burst_reshaper.r_num_bytes_possible, + // "burst_reshaper_r_num_bytes" : i_axi_dma_burst_reshaper.r_num_bytes, + // "burst_reshaper_r_finish" : i_axi_dma_burst_reshaper.r_finish, + // "burst_reshaper_r_addr_offset" : i_axi_dma_burst_reshaper.r_addr_offset, + // "burst_reshaper_w_num_bytes_possible" : i_axi_dma_burst_reshaper.w_num_bytes_possible, + // "burst_reshaper_w_num_bytes" : i_axi_dma_burst_reshaper.w_num_bytes, + // "burst_reshaper_w_finish" : i_axi_dma_burst_reshaper.w_finish, + // "burst_reshaper_w_addr_offset" : i_axi_dma_burst_reshaper.w_addr_offset + }; + + //-------------------------------------- + // Data Mover + //-------------------------------------- + dma_data_mover = '{ + // AR emitter + // "data_mover_ar_emitter_full" : i_axi_dma_data_mover.ar_emitter_full, + // "data_mover_ar_emitter_empty" : i_axi_dma_data_mover.ar_emitter_empty, + // "data_mover_ar_emitter_push" : i_axi_dma_data_mover.ar_emitter_push, + // "data_mover_ar_emitter_pop" : i_axi_dma_data_mover.ar_emitter_pop, + // AW emitter + // "data_mover_aw_emitter_full" : i_axi_dma_data_mover.aw_emitter_full, + // "data_mover_aw_emitter_empty" : i_axi_dma_data_mover.aw_emitter_empty, + // "data_mover_aw_emitter_push" : i_axi_dma_data_mover.aw_emitter_push, + // "data_mover_aw_emitter_pop" : i_axi_dma_data_mover.aw_emitter_pop, + // "data_mover_is_last_aw" : i_axi_dma_data_mover.is_last_aw, + // R emitter + // "data_mover_r_emitter_full" : i_axi_dma_data_mover.r_emitter_full, + // "data_mover_r_emitter_empty" : i_axi_dma_data_mover.r_emitter_empty, + // "data_mover_r_emitter_push" : i_axi_dma_data_mover.r_emitter_push, + // "data_mover_r_emitter_pop" : i_axi_dma_data_mover.r_emitter_pop, + // W emitter + // "data_mover_w_emitter_full" : i_axi_dma_data_mover.w_emitter_full, + // "data_mover_w_emitter_empty" : i_axi_dma_data_mover.w_emitter_empty, + // "data_mover_w_emitter_push" : i_axi_dma_data_mover.w_emitter_push, + // "data_mover_w_emitter_pop" : i_axi_dma_data_mover.w_emitter_pop, + // AW AXI signals + // "axi_dma_bus_aw_id" : i_axi_dma_data_mover.axi_dma_req_o.aw.id, + // "axi_dma_bus_aw_addr" : i_axi_dma_data_mover.axi_dma_req_o.aw.addr, + "axi_dma_bus_aw_len" : i_axi_dma_data_mover.axi_dma_req_o.aw.len, + "axi_dma_bus_aw_size" : i_axi_dma_data_mover.axi_dma_req_o.aw.size, + // "axi_dma_bus_aw_burst" : i_axi_dma_data_mover.axi_dma_req_o.aw.burst, + // "axi_dma_bus_aw_cache" : i_axi_dma_data_mover.axi_dma_req_o.aw.cache, + "axi_dma_bus_aw_valid" : i_axi_dma_data_mover.axi_dma_req_o.aw_valid, + "axi_dma_bus_aw_ready" : i_axi_dma_data_mover.axi_dma_res_i.aw_ready, + // B AXI signals + "axi_dma_bus_b_ready" : i_axi_dma_data_mover.axi_dma_req_o.b_ready, + "axi_dma_bus_b_valid" : i_axi_dma_data_mover.axi_dma_res_i.b_valid, + // AR AXI signals + // "axi_dma_bus_ar_id" : i_axi_dma_data_mover.axi_dma_req_o.ar.id, + // "axi_dma_bus_ar_addr" : i_axi_dma_data_mover.axi_dma_req_o.ar.addr, + "axi_dma_bus_ar_len" : i_axi_dma_data_mover.axi_dma_req_o.ar.len, + "axi_dma_bus_ar_size" : i_axi_dma_data_mover.axi_dma_req_o.ar.size, + // "axi_dma_bus_ar_burst" : i_axi_dma_data_mover.axi_dma_req_o.ar.burst, + // "axi_dma_bus_ar_cache" : i_axi_dma_data_mover.axi_dma_req_o.ar.cache, + "axi_dma_bus_ar_valid" : i_axi_dma_data_mover.axi_dma_req_o.ar_valid, + "axi_dma_bus_ar_ready" : i_axi_dma_data_mover.axi_dma_res_i.ar_ready + }; + + //-------------------------------------- + // Data Path + //-------------------------------------- + dma_data_path = '{ + // r channel + "data_path_r_dp_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.r_dp_valid_i, + "data_path_r_dp_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.r_dp_ready_o, + "data_path_r_tailer_i" : i_axi_dma_data_mover.i_axi_dma_data_path.r_tailer_i, + "data_path_r_offset_i" : i_axi_dma_data_mover.i_axi_dma_data_path.r_offset_i, + "data_path_r_shift_i" : i_axi_dma_data_mover.i_axi_dma_data_path.r_shift_i, + "axi_dma_bus_r_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.r_valid_i, + // "axi_dma_bus_r_data" : i_axi_dma_data_mover.i_axi_dma_data_path.r_data_i, + // "axi_dma_bus_r_last" : i_axi_dma_data_mover.i_axi_dma_data_path.r_last_i, + // "axi_dma_bus_r_resp" : i_axi_dma_data_mover.i_axi_dma_data_path.r_resp_i, + "axi_dma_bus_r_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.r_ready_o, + // w channel + "data_path_w_dp_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.w_dp_valid_i, + "data_path_w_dp_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.w_dp_ready_o, + "data_path_w_tailer_i" : i_axi_dma_data_mover.i_axi_dma_data_path.w_tailer_i, + "data_path_w_offset_i" : i_axi_dma_data_mover.i_axi_dma_data_path.w_offset_i, + "data_path_w_num_beats" : i_axi_dma_data_mover.i_axi_dma_data_path.w_num_beats_i, + "data_path_w_is_single" : i_axi_dma_data_mover.i_axi_dma_data_path.w_is_single_i, + "axi_dma_bus_w_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.w_valid_o, + // "axi_dma_bus_w_data" : i_axi_dma_data_mover.i_axi_dma_data_path.w_data_o, + "axi_dma_bus_w_strb" : i_axi_dma_data_mover.i_axi_dma_data_path.w_strb_o, + // "axi_dma_bus_w_last" : i_axi_dma_data_mover.i_axi_dma_data_path.w_last_o, + "axi_dma_bus_w_ready" : i_axi_dma_data_mover.i_axi_dma_data_path.w_ready_i, + // mask pre-calculation + "data_path_r_first_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.r_first_mask, + "data_path_r_last_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.r_last_mask, + "data_path_w_first_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.w_first_mask, + "data_path_w_last_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.w_last_mask, + // barrel shifter + // "data_path_buffer_in" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_in, + "data_path_read_aligned_in_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.read_aligned_in_mask, + "data_path_write_aligned_in_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.in_mask, + // in mask generation + // "data_path_is_first_r" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_r, + // "data_path_is_first_r_d" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_r_d, + // "data_path_is_first_r_d" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_r_d, + // read control + // "data_path_buffer_full" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_full, + // "data_path_buffer_push" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_push, + // "data_path_full" : i_axi_dma_data_mover.i_axi_dma_data_path.full, + "data_path_push" : i_axi_dma_data_mover.i_axi_dma_data_path.push, + // out mask generation + "data_path_out_mask" : i_axi_dma_data_mover.i_axi_dma_data_path.out_mask, + // "data_path_is_first_w" : i_axi_dma_data_mover.i_axi_dma_data_path.is_first_w, + // "data_path_is_last_w" : i_axi_dma_data_mover.i_axi_dma_data_path.is_last_w, + // write control + // "data_path_buffer_out" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_out, + // "data_path_buffer_empty" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_empty, + // "data_path_buffer_pop" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_pop, + // "data_path_w_num_beats" : i_axi_dma_data_mover.i_axi_dma_data_path.w_num_beats_q, + // "data_path_w_cnt_valid" : i_axi_dma_data_mover.i_axi_dma_data_path.w_cnt_valid_q, + "data_path_pop" : i_axi_dma_data_mover.i_axi_dma_data_path.pop// , + // "data_path_write_happening" : i_axi_dma_data_mover.i_axi_dma_data_path.write_happening, + // "data_path_ready_to_write" : i_axi_dma_data_mover.i_axi_dma_data_path.ready_to_write, + // "data_path_first_possible" : i_axi_dma_data_mover.i_axi_dma_data_path.first_possible, + // "data_path_buffer_clean" : i_axi_dma_data_mover.i_axi_dma_data_path.buffer_clean + }; + + // write dicts to string + foreach(dma_meta[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_meta[key]); + // only write bulk of data if dma is actually active :) + if (!backend_idle_o | valid_i & ready_o | i_axi_dma_burst_reshaper.valid_i & i_axi_dma_burst_reshaper.ready_o | + i_axi_dma_burst_reshaper.burst_q.src.valid | i_axi_dma_burst_reshaper.burst_q.dst.valid | trans_complete_o) begin + foreach(dma_backend[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_backend[key]); + foreach(dma_burst_res[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_burst_res[key]); + foreach(dma_data_mover[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_data_mover[key]); + foreach(dma_data_path[key]) dma_string = $sformatf("%s'%s': 0x%0x, ", dma_string, key, dma_data_path[key]); + + //-------------------------------------- + // Realign Buffer Data Store + //-------------------------------------- + // for(int d = 0; d < BUFFER_DEPTH; d++) begin + // for(int i = 0; i < DATA_WIDTH/8; i++) begin + // dma_string = $sformatf("%s'buffer_mem_%0d_level_%0d': 0x%0x, ", + // dma_string, i, d, buffer_mem[i][d] + // ); + // end + // end + end + dma_string = $sformatf("%s}", dma_string); + $fwrite(f, dma_string); + $fwrite(f, "\n"); + end + end + // close the file + final begin + $fclose(f); + end + end + endgenerate + `endif + `endif + //pragma translate_on +endmodule : axi_dma_backend diff --git a/hw/deps/axi/src/dma/axi_dma_burst_reshaper.sv b/hw/deps/axi/src/dma/axi_dma_burst_reshaper.sv new file mode 100644 index 0000000..c456984 --- /dev/null +++ b/hw/deps/axi/src/dma/axi_dma_burst_reshaper.sv @@ -0,0 +1,357 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +/// Splits a generic 1D transfer in AXI-conform transfers +module axi_dma_burst_reshaper #( + /// Data width of the AXI bus + parameter int unsigned DataWidth = -1, + /// Address width of the AXI bus + parameter int unsigned AddrWidth = -1, + /// ID width of the AXI bus + parameter int unsigned IdWidth = -1, + /// Arbitrary 1D burst request definition: + /// - id: the AXI id used - this id should be constant, as the DMA does not support reordering + /// - src, dst: source and destination address, same width as the AXI 4 interface + /// - num_bytes: the length of the contiguous 1D transfer requested, can be up to 32/64 bit long + /// num_bytes will be interpreted as an unsigned number + /// A value of 0 will cause the backend to discard the transfer prematurely + /// - src_cache, dst_cache: the configuration of the cache fields in the AX beats + /// - src_burst, dst_burst: currently only incremental bursts are supported (2'b01) + /// - decouple_rw: if set to true, there is no longer exactly one AXI write_request issued for + /// every read request. This mode can improve performance of unaligned transfers when crossing + /// the AXI page boundaries. + /// - deburst: if set, the DMA will split all bursts in single transfers + parameter type burst_req_t = logic, + /// Read request definition. Includes: + /// - ax descriptor + /// - id: AXI id + /// - last: last transaction in burst + /// - address: address of burst + /// - length: burst length + /// - size: bytes in each burst + /// - burst: burst type; only INC supported + /// - cache: cache type + /// - r descriptor + /// - offset: initial misalignment + /// - tailer: final misalignment + /// - shift: amount the data needs to be shifted to realign it + parameter type read_req_t = logic, + /// Write request definition. Includes: + /// - ax descriptor + /// - id: AXI id + /// - last: last transaction in burst + /// - address: address of burst + /// - length: burst length + /// - size: bytes in each burst + /// - burst: burst type; only INC supported + /// - cache: cache type + /// - w descriptor + /// - offset: initial misalignment + /// - tailer: final misalignment + /// - num_beats: number of beats in the burst + /// - is_single: burst length is 0 + parameter type write_req_t = logic + +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Arbitrary 1D burst request + input burst_req_t burst_req_i, + + /// Handshake: burst request is valid + input logic valid_i, + /// Handshake: burst request can be accepted + output logic ready_o, + + /// Write transfer request + output write_req_t write_req_o, + /// Read transfer request + output read_req_t read_req_o, + + /// Handshake: read transfer request valid + output logic r_valid_o, + /// Handshake: read transfer request ready + input logic r_ready_i, + /// Handshake: write transfer request valid + output logic w_valid_o, + /// Handshake: write transfer request ready + input logic w_ready_i +); + + localparam int unsigned StrbWidth = DataWidth / 8; + localparam int unsigned OffsetWidth = $clog2(StrbWidth); + localparam int unsigned PageSize = (256 * StrbWidth > 4096) ? 4096 : 256 * StrbWidth; + localparam int unsigned PageAddrWidth = $clog2(PageSize); + /// Offset type + typedef logic [ OffsetWidth-1:0] offset_t; + /// Address Type + typedef logic [ AddrWidth-1:0] addr_t; + /// AXI ID Type + typedef logic [ IdWidth-1:0] axi_id_t; + + /// Type containing burst description for each channel independently + typedef struct packed { + axi_id_t id; + addr_t addr; + addr_t num_bytes; + axi_pkg::cache_t cache; + axi_pkg::burst_t burst; + logic valid; + } burst_chan_t; + + /// Type containing burst description + typedef struct packed { + burst_chan_t src; + burst_chan_t dst; + offset_t shift; + logic decouple_rw; + logic deburst; + } burst_decoupled_t; + + //-------------------------------------- + // state; internally hold one transfer + //-------------------------------------- + burst_decoupled_t burst_d, burst_q; + + //-------------------------------------- + // page boundary check + //-------------------------------------- + logic [PageAddrWidth-1:0] r_page_offset; + logic [PageAddrWidth :0] r_num_bytes_to_pb; + logic [PageAddrWidth-1:0] w_page_offset; + logic [PageAddrWidth :0] w_num_bytes_to_pb; + logic [PageAddrWidth :0] c_num_bytes_to_pb; + + always_comb begin : proc_write_page_boundry_check + // implement deburst operation + if (burst_q.deburst) begin + // deburst + // read pages + r_page_offset = burst_q.src.addr[OffsetWidth-1:0]; + // how many transfers are remaining until the end of the bus? + r_num_bytes_to_pb = (StrbWidth - r_page_offset) % (2 * StrbWidth); + + // write pages + w_page_offset = burst_q.dst.addr[OffsetWidth-1:0]; + // how many transfers are remaining until the end of the bus? + w_num_bytes_to_pb = (StrbWidth - w_page_offset) % (2 * StrbWidth); + end else begin + // bursts allowed + // read pages + r_page_offset = burst_q.src.addr[PageAddrWidth-1:0]; + // how many transfers are remaining in current page? + r_num_bytes_to_pb = PageSize - r_page_offset; + + // write pages + w_page_offset = burst_q.dst.addr[PageAddrWidth-1:0]; + // how many transfers are remaining in current page? + w_num_bytes_to_pb = PageSize - w_page_offset; + end + // how many transfers are remaining when concerning both r/w pages? + // take the boundary that is closer + c_num_bytes_to_pb = (r_num_bytes_to_pb > w_num_bytes_to_pb) ? + w_num_bytes_to_pb : r_num_bytes_to_pb; + + end + + //-------------------------------------- + // Synchronized R/W process + //-------------------------------------- + logic [PageAddrWidth:0] r_num_bytes_possible; + logic [PageAddrWidth:0] r_num_bytes; + logic r_finish; + logic [OffsetWidth-1:0] r_addr_offset; + + logic [PageAddrWidth:0] w_num_bytes_possible; + logic [PageAddrWidth:0] w_num_bytes; + logic w_finish; + logic [OffsetWidth-1:0] w_addr_offset; + + always_comb begin : proc_read_write_transaction + + // default: keep last state + burst_d = burst_q; + + //-------------------------------------- + // Specify read transaction + //-------------------------------------- + // max num bytes according to page(s) + r_num_bytes_possible = (burst_q.decouple_rw == 1'b1) ? + r_num_bytes_to_pb : c_num_bytes_to_pb; + + // more bytes remaining than we can send + if (burst_q.src.num_bytes > r_num_bytes_possible) begin + r_num_bytes = r_num_bytes_possible; + // calculate remainder + burst_d.src.num_bytes = burst_q.src.num_bytes - r_num_bytes_possible; + // not finished + r_finish = 1'b0; + // next address, depends on burst type. only type 01 is supported yet + burst_d.src.addr = (burst_q.src.burst == axi_pkg::BURST_INCR) ? + burst_q.src.addr + r_num_bytes : burst_q.src.addr; + + // remaining bytes fit in one burst + // reset storage for the read channel to stop this channel + end else begin + r_num_bytes = burst_q.src.num_bytes[PageAddrWidth:0]; + // default: when a transfer is finished, set it to 0 + burst_d.src = '0; + // finished + r_finish = 1'b1; + end + + // calculate the address offset aligned to transfer sizes. + r_addr_offset = burst_q.src.addr[OffsetWidth-1:0]; + + // create the AR request + read_req_o.ar.addr = { burst_q.src.addr[AddrWidth-1:OffsetWidth], + {{OffsetWidth}{1'b0}} }; + read_req_o.ar.len = ((r_num_bytes + r_addr_offset - 1) >> OffsetWidth); + read_req_o.ar.size = axi_pkg::size_t'(OffsetWidth); + read_req_o.ar.id = burst_q.src.id; + read_req_o.ar.last = r_finish; + read_req_o.ar.burst = burst_q.src.burst; + read_req_o.ar.cache = burst_q.src.cache; + r_valid_o = burst_q.decouple_rw ? + burst_q.src.valid : burst_q.src.valid & w_ready_i; + + // create the R request + read_req_o.r.offset = r_addr_offset; + read_req_o.r.tailer = OffsetWidth'(r_num_bytes + r_addr_offset); + // shift is determined on a per 1D request base + read_req_o.r.shift = burst_q.shift; + + //-------------------------------------- + // Specify write transaction + //-------------------------------------- + // max num bytes according to page(s) + w_num_bytes_possible = (burst_q.decouple_rw == 1'b1) ? + w_num_bytes_to_pb : c_num_bytes_to_pb; + + // more bytes remaining than we can send + if (burst_q.dst.num_bytes > w_num_bytes_possible) begin + w_num_bytes = w_num_bytes_possible; + // calculate remainder + burst_d.dst.num_bytes = burst_q.dst.num_bytes - w_num_bytes_possible; + // not finished + w_finish = 1'b0; + // next address, depends on burst type. only type 01 is supported yet + burst_d.dst.addr = (burst_q.dst.burst == axi_pkg::BURST_INCR) ? + burst_q.dst.addr + w_num_bytes : burst_q.dst.addr; + + // remaining bytes fit in one burst + // reset storage for the write channel to stop this channel + end else begin + w_num_bytes = burst_q.dst.num_bytes[PageAddrWidth:0]; + // default: when a transfer is finished, set it to 0 + burst_d.dst = '0; + // finished + w_finish = 1'b1; + end + + // calculate the address offset aligned to transfer sizes. + w_addr_offset = burst_q.dst.addr[OffsetWidth-1:0]; + + // create the AW request + write_req_o.aw.addr = { burst_q.dst.addr[AddrWidth-1:OffsetWidth], + {{OffsetWidth}{1'b0}} }; + write_req_o.aw.len = ((w_num_bytes + w_addr_offset - 1) >> OffsetWidth); + write_req_o.aw.size = axi_pkg::size_t'(OffsetWidth); + write_req_o.aw.id = burst_q.dst.id; + // hand over internal transaction id + write_req_o.aw.last = w_finish; + write_req_o.aw.burst = burst_q.dst.burst; + write_req_o.aw.cache = burst_q.dst.cache; + w_valid_o = burst_q.decouple_rw ? + burst_q.dst.valid : burst_q.dst.valid & r_ready_i; + + // create the W request + write_req_o.w.offset = w_addr_offset; + write_req_o.w.tailer = OffsetWidth'(w_num_bytes + w_addr_offset); + write_req_o.w.num_beats = write_req_o.aw.len; + // is the transfer be only one beat in length? Counters don't have to be initialized then. + write_req_o.w.is_single = (write_req_o.aw.len == '0); + + //-------------------------------------- + // Module control + //-------------------------------------- + ready_o = r_finish & w_finish & valid_i & r_ready_i & w_ready_i; + + //-------------------------------------- + // Refill + //-------------------------------------- + // new request is taken in if both r and w machines are ready. + if (ready_o) begin + // unfortunately this is unpacked + burst_d.src.id = burst_req_i.id; + burst_d.src.addr = burst_req_i.src; + burst_d.src.num_bytes = burst_req_i.num_bytes; + burst_d.src.cache = burst_req_i.cache_src; + burst_d.src.burst = burst_req_i.burst_src; + // check if transfer is possible -> num_bytes has to be larger than 0 + burst_d.src.valid = (burst_req_i.num_bytes == '0) ? 1'b0 : valid_i; + + burst_d.dst.id = burst_req_i.id; + burst_d.dst.addr = burst_req_i.dst; + burst_d.dst.num_bytes = burst_req_i.num_bytes; + burst_d.dst.cache = burst_req_i.cache_dst; + burst_d.dst.burst = burst_req_i.burst_dst; + // check if transfer is possible -> num_bytes has to be larger than 0 + burst_d.dst.valid = (burst_req_i.num_bytes == '0) ? 1'b0 : valid_i; + + burst_d.decouple_rw = burst_req_i.decouple_rw; + burst_d.deburst = burst_req_i.deburst; + // shift is calculated for each 1D transfer + burst_d.shift = burst_req_i.src[OffsetWidth-1:0] - + burst_req_i.dst[OffsetWidth-1:0]; + + // assertions + // pragma translate_off + `ifndef VERILATOR + assert property (@(posedge clk_i) disable iff (~rst_ni) + (valid_i |-> burst_req_i.burst_src inside {axi_pkg::BURST_INCR})) else + $fatal(1, "Unsupported DMA src_burst request.."); + assert property (@(posedge clk_i) disable iff (~rst_ni) + (valid_i |-> burst_req_i.burst_dst inside {axi_pkg::BURST_INCR})) else + $fatal(1, "Unsupported DMA dst_burst request."); + `endif + // pragma translate_on + end + end + + //-------------------------------------- + // State + //-------------------------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + burst_q.decouple_rw <= '0; + burst_q.deburst <= '0; + burst_q.shift <= '0; + burst_q.src <= '0; + burst_q.dst <= '0; + end else begin + burst_q.decouple_rw <= burst_d.decouple_rw; + burst_q.deburst <= burst_d.deburst; + burst_q.shift <= burst_d.shift; + // couple read and write machines in the coupled test + if (burst_d.decouple_rw) begin + if (r_ready_i) burst_q.src <= burst_d.src; + if (w_ready_i) burst_q.dst <= burst_d.dst; + end else begin + if (r_ready_i & w_ready_i) burst_q.src <= burst_d.src; + if (w_ready_i & r_ready_i) burst_q.dst <= burst_d.dst; + end + end + end +endmodule : axi_dma_burst_reshaper diff --git a/hw/deps/axi/src/dma/axi_dma_data_mover.sv b/hw/deps/axi/src/dma/axi_dma_data_mover.sv new file mode 100644 index 0000000..433fed0 --- /dev/null +++ b/hw/deps/axi/src/dma/axi_dma_data_mover.sv @@ -0,0 +1,370 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +/// Module, that controls the AXI bus. Takes two configuration structs (R/W) as an +/// input. Implements the DMA functionality on the AXI bus. +/// R and W config structs need to appear at the input simultaneously; sending a +/// R config w/o the corresponding W could lead to wrong AXI transfers. +module axi_dma_data_mover #( + /// Data width of the AXI bus + parameter int unsigned DataWidth = -1, + /// Number of AX beats that can be in-flight + parameter int unsigned ReqFifoDepth = -1, + /// Number of elements the realignment buffer can hold. To achieve + /// full performance a depth of 3 is minimally required. + parameter int unsigned BufferDepth = -1, + /// AXI4+ATOP request struct definition. + parameter type axi_req_t = logic, + /// AXI4+ATOP response struct definition. + parameter type axi_res_t = logic, + /// ax descriptor + /// - `id`: AXI id + /// - `last`: last transaction in burst + /// - `address`: address of burst + /// - `length`: burst length + /// - `size`: bytes in each burst + /// - `burst`: burst type; only INC supported + /// - `cache`: cache type + parameter type desc_ax_t = logic, + /// r descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `shift`: amount the data needs to be shifted to realign it + parameter type desc_r_t = logic, + /// w descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `num_beats`: number of beats in the burst + /// - `is_single`: burst length is 0 + parameter type desc_w_t = logic, + /// Read request definition. Includes: + /// - ax descriptor + /// - `id`: AXI id + /// - `last`: last transaction in burst + /// - `address`: address of burst + /// - `length`: burst length + /// - `size`: bytes in each burst + /// - `burst`: burst type; only INC supported + /// - `cache`: cache type + /// - r descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `shift`: amount the data needs to be shifted to realign it + parameter type read_req_t = logic, + /// Write request definition. Includes: + /// - ax descriptor + /// - `id`: AXI id + /// - `last`: last transaction in burst + /// - `address`: address of burst + /// - `length`: burst length + /// - `size`: bytes in each burst + /// - `burst`: burst type; only INC supported + /// - `cache`: cache type + /// - w descriptor + /// - `offset`: initial misalignment + /// - `tailer`: final misalignment + /// - `num_beats`: number of beats in the burst + /// - `is_single`: burst length is 0 + parameter type write_req_t = logic +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// AXI4+ATOP master request + output axi_req_t axi_dma_req_o, + /// AXI4+ATOP master response + input axi_res_t axi_dma_res_i, + /// Read transfer request + input read_req_t read_req_i, + /// Write transfer request + input write_req_t write_req_i, + /// Handshake: read transfer request valid + input logic r_valid_i, + /// Handshake: read transfer request ready + output logic r_ready_o, + /// Handshake: write transfer request valid + input logic w_valid_i, + /// Handshake: write transfer request ready + output logic w_ready_o, + /// High if the data mover is idle + output logic data_mover_idle_o, + /// Event: a transaction has completed + output logic trans_complete_o +); + + localparam int unsigned StrbWidth = DataWidth / 8; + // local types + typedef logic [DataWidth-1:0] data_t; + typedef logic [StrbWidth-1:0] strb_t; + + //-------------------------------------- + // AR emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_ax_t current_ar_req; + // control signals + logic ar_emitter_full; + logic ar_emitter_empty; + logic ar_emitter_push; + logic ar_emitter_pop; + + // instanciate a fifo to buffer the address read requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .DEPTH ( ReqFifoDepth ), + .dtype ( desc_ax_t ) + ) i_fifo_ar_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( ar_emitter_full ), + .empty_o ( ar_emitter_empty ), + .usage_o ( ), + .data_i ( read_req_i.ar ), + .push_i ( ar_emitter_push ), + .data_o ( current_ar_req ), + .pop_i ( ar_emitter_pop ) + ); + + //-------------------------------------- + // AW emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_ax_t current_aw_req; + // control signals + logic aw_emitter_full; + logic aw_emitter_empty; + logic aw_emitter_push; + logic aw_emitter_pop; + + // instantiate a fifo to buffer the address write requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .dtype ( desc_ax_t ), + .DEPTH ( ReqFifoDepth ) + ) i_fifo_aw_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( aw_emitter_full ), + .empty_o ( aw_emitter_empty ), + .usage_o ( ), + .data_i ( write_req_i.aw ), + .push_i ( aw_emitter_push ), + .data_o ( current_aw_req ), + .pop_i ( aw_emitter_pop ) + ); + + //-------------------------------------- + // R emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_r_t current_r_req; + // control signals + logic r_emitter_full; + logic r_emitter_empty; + logic r_emitter_push; + logic r_emitter_pop; + + // instantiate a fifo to buffer the read requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .dtype ( desc_r_t ), + .DEPTH ( ReqFifoDepth ) + ) i_fifo_r_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( r_emitter_full ), + .empty_o ( r_emitter_empty ), + .usage_o ( ), + .data_i ( read_req_i.r ), + .push_i ( r_emitter_push ), + .data_o ( current_r_req ), + .pop_i ( r_emitter_pop ) + ); + + //-------------------------------------- + // W emitter + //-------------------------------------- + // object currently at the tail of the fifo + desc_w_t current_w_req; + // control signals + logic w_emitter_full; + logic w_emitter_empty; + logic w_emitter_push; + logic w_emitter_pop; + + // instanciate a fifo to buffer the read requests + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .dtype ( desc_w_t ), + .DEPTH ( ReqFifoDepth ) + ) i_fifo_w_emitter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( w_emitter_full ), + .empty_o ( w_emitter_empty ), + .usage_o ( ), + .data_i ( write_req_i.w ), + .push_i ( w_emitter_push ), + .data_o ( current_w_req ), + .pop_i ( w_emitter_pop ) + ); + + //-------------------------------------- + // instantiate of the data path + //-------------------------------------- + // AXI bus signals from and to the datapath + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + logic r_valid; + logic r_ready; + data_t w_data; + strb_t w_strb; + logic w_valid; + logic w_last; + logic w_ready; + + logic w_next; + + axi_dma_data_path #( + .DataWidth ( DataWidth ), + .BufferDepth ( BufferDepth ) + ) i_axi_dma_data_path ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .r_dp_valid_i ( ~r_emitter_empty ), + .r_dp_ready_o ( r_emitter_pop ), + .w_dp_valid_i ( ~w_emitter_empty ), + .w_dp_ready_o ( w_emitter_pop ), + .data_path_idle_o ( data_mover_idle_o ), + // AXI R signals + .r_data_i ( r_data ), + .r_valid_i ( r_valid ), + .r_last_i ( r_last ), + .r_resp_i ( r_resp ), + .r_ready_o ( r_ready ), + // R control + .r_tailer_i ( current_r_req.tailer ), + .r_offset_i ( current_r_req.offset ), + .r_shift_i ( current_r_req.shift ), + // AXI W signals + .w_data_o ( w_data ), + .w_strb_o ( w_strb ), + .w_valid_o ( w_valid ), + .w_last_o ( w_last ), + .w_ready_i ( w_ready ), + // W control + .w_offset_i ( current_w_req.offset ), + .w_tailer_i ( current_w_req.tailer ), + .w_num_beats_i ( current_w_req.num_beats ), + .w_is_single_i ( current_w_req.is_single ) + ); + + //-------------------------------------- + // Refill control + //-------------------------------------- + // the ax and x fifos of both channels are filled + // together, as request come bundled. + always_comb begin : proc_refill + // Read related channels + r_ready_o = ~ar_emitter_full & ~r_emitter_full; + r_emitter_push = r_valid_i & r_ready_o; + ar_emitter_push = r_valid_i & r_ready_o; + + // Write related channels + w_ready_o = ~aw_emitter_full & ~w_emitter_full; + w_emitter_push = w_valid_i & w_ready_o; + aw_emitter_push = w_valid_i & w_ready_o; + end + + //-------------------------------------- + // Bus control + //-------------------------------------- + // here the AXI bus is unpacked/packed. + always_comb begin : proc_bus_packer + // defaults: not used signals -> 0 + axi_dma_req_o = '0; + + // assign R signals + r_data = axi_dma_res_i.r.data; + r_resp = axi_dma_res_i.r.resp; + r_last = axi_dma_res_i.r.last; + r_valid = axi_dma_res_i.r_valid; + axi_dma_req_o.r_ready = r_ready; + + // assign W signals + axi_dma_req_o.w.data = w_data; + axi_dma_req_o.w.strb = w_strb; + axi_dma_req_o.w.last = w_last; + axi_dma_req_o.w_valid = w_valid; + w_ready = axi_dma_res_i.w_ready; + + // AW signals + axi_dma_req_o.aw.id = current_aw_req.id; + axi_dma_req_o.aw.addr = current_aw_req.addr; + axi_dma_req_o.aw.len = current_aw_req.len; + axi_dma_req_o.aw.size = current_aw_req.size; + axi_dma_req_o.aw.burst = current_aw_req.burst; + axi_dma_req_o.aw.cache = current_aw_req.cache; + // flow control + axi_dma_req_o.aw_valid = ~aw_emitter_empty; + aw_emitter_pop = axi_dma_res_i.aw_ready & axi_dma_req_o.aw_valid; + + // B signals + // we are always ready to accept b signals, as we do not need them + // inside the DMA (we don't care if write failed) + axi_dma_req_o.b_ready = 1'b1; + + // AR signals + axi_dma_req_o.ar.id = current_ar_req.id; + axi_dma_req_o.ar.addr = current_ar_req.addr; + axi_dma_req_o.ar.len = current_ar_req.len; + axi_dma_req_o.ar.size = current_ar_req.size; + axi_dma_req_o.ar.burst = current_ar_req.burst; + axi_dma_req_o.ar.cache = current_ar_req.cache; + // flow control + axi_dma_req_o.ar_valid = ~ar_emitter_empty; + ar_emitter_pop = axi_dma_res_i.ar_ready & axi_dma_req_o.ar_valid; + end + + //-------------------------------------- + // ID control + //-------------------------------------- + logic is_last_aw; + fifo_v3 #( + .DEPTH ( ReqFifoDepth + BufferDepth + 1 ), + .dtype ( logic ) + ) i_last_transaction_queue ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( ), + .empty_o ( ), + .usage_o ( ), + .data_i ( current_aw_req.last ), + .push_i ( aw_emitter_pop ), + .data_o ( is_last_aw ), + .pop_i ( axi_dma_res_i.b_valid ) + ); + assign trans_complete_o = is_last_aw & axi_dma_res_i.b_valid; + +endmodule : axi_dma_data_mover diff --git a/hw/deps/axi/src/dma/axi_dma_data_path.sv b/hw/deps/axi/src/dma/axi_dma_data_path.sv new file mode 100644 index 0000000..73a197e --- /dev/null +++ b/hw/deps/axi/src/dma/axi_dma_data_path.sv @@ -0,0 +1,393 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +/// Data path for the AXI DMA. This modules handles the R/W channel of the +/// AXI protocol. +/// Module gets read stream, realigns data and emits a write stream. +/// AXI-like valid/ready handshaking is used to communicate with the rest +/// of the backend. +module axi_dma_data_path #( + /// Data width of the AXI bus + parameter int DataWidth = -1, + /// Number of elements the realignment buffer can hold. To achieve + /// full performance a depth of 3 is minimally required. + parameter int BufferDepth = -1, + // DO NOT OVERWRITE THIS PARAMETER + parameter int StrbWidth = DataWidth / 8, + parameter int OffsetWidth = $clog2(StrbWidth) +) ( + // status signals + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + + // handshaking signals + /// Handshake: read side of data path is presented with a valid request + input logic r_dp_valid_i, + /// Handshake: read side of data path is ready to accept new requests + output logic r_dp_ready_o, + /// Handshake: write side of data path is presented with a valid request + input logic w_dp_valid_i, + /// Handshake: write side of data path is ready to accept new requests + output logic w_dp_ready_o, + + // status signal + /// High if the data path is idle + output logic data_path_idle_o, + + // r-channel + /// Read data from the AXI bus + input logic [DataWidth-1:0] r_data_i, + /// Valid signal of the AXI r channel + input logic r_valid_i, + /// Last signal of the AXI r channel + input logic r_last_i, + /// Response signal of the AXI r channel + input logic [ 1:0] r_resp_i, + /// Ready signal of the AXI r channel + output logic r_ready_o, + + /// number of bytes the end of the read transfer is short to reach a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] r_tailer_i, + /// number of bytes the read transfers starts after a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] r_offset_i, + /// The amount the read data has to be shifted to write-align it + input logic [OffsetWidth-1:0] r_shift_i, + + // w-channel + /// Write data of the AXI bus + output logic [DataWidth-1:0] w_data_o, + /// Write strobe of the AXI bus + output logic [StrbWidth-1:0] w_strb_o, + /// Valid signal of the AXI w channel + output logic w_valid_o, + /// Last signal of the AXI w channel + output logic w_last_o, + /// Ready signal of the AXI w channel + input logic w_ready_i, + + /// number of bytes the write transfers starts after a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] w_offset_i, + /// number of bytes the end of the write transfer is short to reach a + /// Bus-aligned boundary + input logic [OffsetWidth-1:0] w_tailer_i, + /// Number of beats requested by this transfer + input logic [ 7:0] w_num_beats_i, + /// True if the transfer only consists of a single beat + input logic w_is_single_i +); + + // buffer contains 8 data bits per FIFO + // buffer is at least 3 deep to prevent stalls + + // 64 bit DATA Width example: + // DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD <- head + // DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD + // DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD <- tail + // -byte7--|-byte6--|-byte5--|-byte4--|-byte3--|-byte2--|-byte1--|-byte0--| + + + //-------------------------------------- + // Mask pre-calculation + //-------------------------------------- + // in contiguous transfers that are unaligned, there will be some + // invalid bytes at the beginning and the end of the stream + // example: 25B in 64 bit system + // iiiivvvv|vvvvvvvv|vvvvvvvv|vvvvviii + // last msk|----full mask----|first msk + + // offsets needed for masks to fill/empty buffer + logic [StrbWidth-1:0] r_first_mask; + logic [StrbWidth-1:0] r_last_mask; + logic [StrbWidth-1:0] w_first_mask; + logic [StrbWidth-1:0] w_last_mask; + + // read align masks + assign r_first_mask = '1 << r_offset_i; + assign r_last_mask = '1 >> (StrbWidth - r_tailer_i); + + // write align masks + assign w_first_mask = '1 << w_offset_i; + assign w_last_mask = '1 >> (StrbWidth - w_tailer_i); + + + //-------------------------------------- + // Barrel shifter + //-------------------------------------- + // data arrives in chuncks of length DATA_WDITH, the buffer will be filled with + // the realigned data. StrbWidth bytes will be inserted starting from the + // provided address, overflows will naturally wrap + + // signals connected to the buffer + logic [StrbWidth-1:0][7:0] buffer_in; + + // read aligned in mask. needs to be rotated together with the data before + // it can be used to fill in valid data into the buffer + logic [StrbWidth-1:0] read_aligned_in_mask; + + // in mask is write aligned, so it is the result of the read aligned in mask + // that is rotated together with the data in the barrel shifter + logic [StrbWidth-1:0] in_mask; + + // a barrel shifter is a concatenation of the same array with itself and a normal + // shift. + assign buffer_in = {r_data_i, r_data_i} >> (r_shift_i * 8); + assign in_mask = {read_aligned_in_mask, read_aligned_in_mask} >> r_shift_i; + + //-------------------------------------- + // In mask generation + //-------------------------------------- + // in the case of unaligned reads -> not all data is valid + logic is_first_r, is_first_r_d; + + always_comb begin : proc_in_mask_generator + // default case: all ones + read_aligned_in_mask = '1; + // is first word: some bytes at the beginning may be invalid + read_aligned_in_mask = is_first_r ? + read_aligned_in_mask & r_first_mask : read_aligned_in_mask; + // is last word in write burst: some bytes at the end may be invalid + if (r_tailer_i != '0) begin + read_aligned_in_mask = r_last_i ? + read_aligned_in_mask & r_last_mask : read_aligned_in_mask; + end + end + + //-------------------------------------- + // Read control + //-------------------------------------- + logic [StrbWidth-1:0] buffer_full; + logic [StrbWidth-1:0] buffer_push; + logic full; + // this signal is used for pushing data to the control fifo + logic push; + + always_comb begin : proc_read_control + // sticky is first bit for read + if (r_valid_i & !r_last_i) begin + // new transfer has started + is_first_r_d = 1'b0; + end else if (r_last_i & r_valid_i) begin + // finish read burst + is_first_r_d = 1'b1; + end else begin + // no change + is_first_r_d = is_first_r; + end + + // the buffer can be pushed to if all the masked fifo buffers (in_mask) are not full. + full = |(buffer_full & in_mask); + // the read can accept data if the buffer is not full + r_ready_o = ~full; + + // once valid data is applied, it can be pushed in all the selected (in_mask) buffers + push = r_valid_i && ~full; + buffer_push = push ? in_mask : '0; + + // r_dp_ready_o is triggered by the last element arriving from the read + r_dp_ready_o = r_dp_valid_i && r_last_i && r_valid_i && ~full;; + end + + //-------------------------------------- + // Out mask generation -> wstrb mask + //-------------------------------------- + // only pop the data actually needed for write from the buffer, + // determine valid data to pop by calculation the wstrb + logic [StrbWidth-1:0] out_mask; + logic is_first_w; + logic is_last_w; + + always_comb begin : proc_out_mask_generator + // default case: all ones + out_mask = '1; + // is first word: some bytes at the beginning may be invalid + out_mask = is_first_w ? (out_mask & w_first_mask) : out_mask; + // is last word in write burst: some bytes at the end may be invalid + if (w_tailer_i != '0) begin + out_mask = is_last_w ? out_mask & w_last_mask : out_mask; + end + end + + //-------------------------------------- + // Write control + //-------------------------------------- + // once buffer contains a full line -> all fifos are non-empty + // push it out. + // signals connected to the buffer + logic [StrbWidth-1:0][7:0] buffer_out; + logic [StrbWidth-1:0] buffer_empty; + logic [StrbWidth-1:0] buffer_pop; + + // write is decoupled from read, due to misalignments in the read/write + // addresses, page crossing can be encountered at any time. + // To handle this efficiently, a 2-to-1 or 1-to-2 mapping of r/w beats + // is required. The write unit needs to keep track of progress through + // a counter and cannot use `r_last` for that. + logic [7:0] w_num_beats_d, w_num_beats_q; + logic w_cnt_valid_d, w_cnt_valid_q; + + // data from buffer is popped + logic pop; + // write happens + logic write_happening; + // buffer is ready to write the requested data + logic ready_to_write; + // first transfer is possible - this signal is used to detect + // the first write transfer in a burst + logic first_possible; + // buffer is completely empty + logic buffer_clean; + + always_comb begin : proc_write_control + // counter + w_num_beats_d = w_num_beats_q; + w_cnt_valid_d = w_cnt_valid_q; + // buffer ctrl + pop = 1'b0; + buffer_pop = 'b0; + write_happening = 1'b0; + ready_to_write = 1'b0; + first_possible = 1'b0; + // bus signals + w_valid_o = 1'b0; + w_data_o = '0; + w_strb_o = '0; + w_last_o = 1'b0; + // mask control + is_first_w = 1'b0; + is_last_w = 1'b0; + // data flow + w_dp_ready_o = 1'b0; + + + // all elements needed (defined by the mask) are in the buffer and the buffer is non-empty + ready_to_write = ((~buffer_empty & out_mask) == out_mask) && (buffer_empty != '1); + + // data needed by the first mask is available in the buffer -> r_first happened for sure + // this signal can be high during a transfer as well, it needs to be masked + first_possible = ((~buffer_empty & w_first_mask) == w_first_mask) && (buffer_empty != '1); + + // the buffer is completely empty (debug only signal) + buffer_clean = &(buffer_empty); + + // write happening: both the bus (w_ready) and the buffer (ready_to_write) is high + write_happening = ready_to_write & w_ready_i; + + // signal the control fifo it could be popped + pop = write_happening; + + // the main buffer is conditionally to the write mask popped + buffer_pop = write_happening ? out_mask : '0; + + // signal the bus that we are ready + w_valid_o = ready_to_write; + + // control the write to the bus apply data to the bus only if data should be written + if (ready_to_write == 1'b1) begin + // assign data from buffers, mask out non valid entries + for (int i = 0; i < StrbWidth; i++) begin + w_data_o[i*8 +: 8] = out_mask[i] ? buffer_out[i] : 8'b0; + end + // assign the out mask to the strobe + w_strb_o = out_mask; + end + + // differentiate between the burst and non-burst case. If a transfer + // consists just of one beat the counters are disabled + if (w_is_single_i) begin + // in the single case the transfer is both first and last. + is_first_w = 1'b1; + is_last_w = 1'b1; + + // in the bursted case the counters are needed to keep track of the progress of sending + // beats. The w_last_o depends on the state of the counter + end else begin + // first transfer happens as soon as a) the buffer is ready for a first transfer and b) + // the counter is currently invalid + is_first_w = first_possible & ~w_cnt_valid_q; + + // last happens as soon as a) the counter is valid and b) the counter is now down to 1 + is_last_w = w_cnt_valid_q & (w_num_beats_q == 8'h01); + + // load the counter with data in a first cycle, only modifying state if bus is ready + if (is_first_w && write_happening) begin + w_num_beats_d = w_num_beats_i; + w_cnt_valid_d = 1'b1; + end + + // if we hit the last element, invalidate the counter, only modifying state + // if bus is ready + if (is_last_w && write_happening) begin + w_cnt_valid_d = 1'b0; + end + + // count down the beats if the counter is valid and valid data is written to the bus + if (w_cnt_valid_q && write_happening) w_num_beats_d = w_num_beats_q - 8'h01; + end + + // the w_last_o signal should only be applied to the bus if an actual transfer happens + w_last_o = is_last_w & ready_to_write; + + // we are ready for the next transfer internally, once the w_last_o signal is applied + w_dp_ready_o = is_last_w & write_happening; + end + + + //-------------------------------------- + // Buffer - implemented as fifo + //-------------------------------------- + logic control_empty; + + for (genvar i = 0; i < StrbWidth; i++) begin : fifo_buffer + fifo_v3 #( + .FALL_THROUGH ( 1'b0 ), + .DATA_WIDTH ( 8 ), + .DEPTH ( BufferDepth ) + ) i_fifo_buffer ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( buffer_full [i] ), + .empty_o ( buffer_empty[i] ), + .usage_o ( ), + .data_i ( buffer_in [i] ), + .push_i ( buffer_push [i] ), + .data_o ( buffer_out [i] ), + .pop_i ( buffer_pop [i] ) + ); + end + + //-------------------------------------- + // Module Control + //------------------------------------- + assign data_path_idle_o = !(r_dp_valid_i | r_dp_ready_o | + w_dp_valid_i | w_dp_ready_o | !buffer_clean); + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ff + if (!rst_ni) begin + is_first_r <= 1'b1; + w_cnt_valid_q <= 1'b0; + w_num_beats_q <= 8'h0; + end else begin + // running_q <= running_d; + if (r_valid_i & r_ready_o) is_first_r <= is_first_r_d; + w_cnt_valid_q <= w_cnt_valid_d; + w_num_beats_q <= w_num_beats_d; + end + end + +endmodule : axi_dma_data_path diff --git a/hw/deps/axi/src/dma/frontends/pspin_soc_frontend/src/pspin_soc_dma.sv b/hw/deps/axi/src/dma/frontends/pspin_soc_frontend/src/pspin_soc_dma.sv new file mode 100644 index 0000000..b7be8c6 --- /dev/null +++ b/hw/deps/axi/src/dma/frontends/pspin_soc_frontend/src/pspin_soc_dma.sv @@ -0,0 +1,259 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +/// soc-level dma + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module pspin_soc_dma #( + /// id width of the DMA AXI Master port + parameter int unsigned DmaAxiIdWidth = -1, + /// data width of the DMA AXI Master port + parameter int unsigned DmaDataWidth = -1, + /// address width of the DMA AXI Master port + parameter int unsigned DmaAddrWidth = -1, + /// user width + parameter int unsigned DmaUserWidth = -1, + /// number of AX requests in-flight + parameter int unsigned AxiAxReqDepth = -1, + /// number of 1D transfers buffered in backend + parameter int unsigned TfReqFifoDepth = -1, + /// data request type + parameter type axi_req_t = logic, + /// data response type + parameter type axi_res_t = logic, + /// transfer descriptor for hw access to DMA + parameter type transf_descr_t = logic, + parameter logic[DmaAddrWidth-1:0] PCIeStartAddr = '0, + parameter logic[DmaAddrWidth-1:0] PCIeEndAddr = '0, + parameter logic[DmaAddrWidth-1:0] NHIStartAddr = '0, + parameter logic[DmaAddrWidth-1:0] NHIEndAddr = '0 +) ( + input logic clk_i, + input logic rst_ni, + /// direct hw port + input logic rx_req_valid_i, + output logic rx_req_ready_o, + input transf_descr_t rx_req_i, + output logic rx_rsp_valid_o, + /// direct hw port + input logic tx_req_valid_i, + output logic tx_req_ready_o, + input transf_descr_t tx_req_i, + output logic tx_rsp_valid_o, + /// wide AXI pcie ports + output axi_req_t pcie_dma_req_o, + input axi_res_t pcie_dma_res_i, + /// wide AXI nhi ports + output axi_req_t nhi_dma_req_o, + input axi_res_t nhi_dma_res_i, + /// status signal + output logic [1:0] idle_o +); + + localparam int unsigned BaseDMAId = 'h10; + + // 1D burst request + typedef logic [DmaAddrWidth-1 :0] addr_t; + typedef logic [DmaAxiIdWidth-1:0] axi_id_t; + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // axi definition + localparam int unsigned DmaAxiIdWidthMst = DmaAxiIdWidth - 1; + + typedef logic [DmaDataWidth-1 :0] data_t; + typedef logic [DmaAxiIdWidthMst-1:0] id_mst_t; + typedef logic [DmaAxiIdWidth-1 :0] id_slv_t; + typedef logic [DmaDataWidth/8-1 :0] strb_t; + typedef logic [DmaUserWidth-1 :0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t); + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t); + `AXI_TYPEDEF_W_CHAN_T (w_chan_t, data_t, strb_t, user_t); + `AXI_TYPEDEF_B_CHAN_T (b_chan_mst_t, id_mst_t, user_t); + `AXI_TYPEDEF_B_CHAN_T (b_chan_slv_t, id_slv_t, user_t); + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t); + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t); + `AXI_TYPEDEF_R_CHAN_T (r_chan_mst_t, data_t, id_mst_t, user_t); + `AXI_TYPEDEF_R_CHAN_T (r_chan_slv_t, data_t, id_slv_t, user_t); + `AXI_TYPEDEF_REQ_T (axi_dma_req_mst_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t); + `AXI_TYPEDEF_REQ_T (axi_dma_req_slv_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t); + `AXI_TYPEDEF_RESP_T (axi_dma_resp_mst_t, b_chan_mst_t, r_chan_mst_t); + `AXI_TYPEDEF_RESP_T (axi_dma_resp_slv_t, b_chan_slv_t, r_chan_slv_t); + + axi_dma_req_mst_t axi_dma_tx_req, axi_dma_rx_req; + axi_dma_resp_mst_t axi_dma_tx_resp, axi_dma_rx_resp; + + burst_req_t rx_burst_req, tx_burst_req; + + always_comb begin : proc_map_rx_to_1D_burst + rx_burst_req.id = BaseDMAId; + rx_burst_req.src = rx_req_i.src_addr; + rx_burst_req.dst = rx_req_i.dst_addr; + rx_burst_req.num_bytes = rx_req_i.num_bytes; + rx_burst_req.burst_src = axi_pkg::BURST_INCR; + rx_burst_req.burst_dst = axi_pkg::BURST_INCR; + rx_burst_req.cache_src = 4'h0; + rx_burst_req.cache_dst = 4'h0; + rx_burst_req.deburst = rx_req_i.deburst; + rx_burst_req.decouple_rw = rx_req_i.decouple; + rx_burst_req.serialize = rx_req_i.serialize; + end + + always_comb begin : proc_map_tx_to_1D_burst + tx_burst_req.id = BaseDMAId; + tx_burst_req.src = tx_req_i.src_addr; + tx_burst_req.dst = tx_req_i.dst_addr; + tx_burst_req.num_bytes = tx_req_i.num_bytes; + tx_burst_req.burst_src = axi_pkg::BURST_INCR; + tx_burst_req.burst_dst = axi_pkg::BURST_INCR; + tx_burst_req.cache_src = 4'h0; + tx_burst_req.cache_dst = 4'h0; + tx_burst_req.deburst = tx_req_i.deburst; + tx_burst_req.decouple_rw = tx_req_i.decouple; + tx_burst_req.serialize = tx_req_i.serialize; + end + axi_dma_backend #( + .DataWidth ( DmaDataWidth ), + .AddrWidth ( DmaAddrWidth ), + .IdWidth ( DmaAxiIdWidthMst ), + .AxReqFifoDepth ( AxiAxReqDepth ), + .TransFifoDepth ( TfReqFifoDepth ), + .BufferDepth ( 3 ), // minimal number giving full performance + .axi_req_t ( axi_dma_req_mst_t ), + .axi_res_t ( axi_dma_resp_mst_t ), + .burst_req_t ( burst_req_t ), + .DmaIdWidth ( 32 ), // the width of the internal id of the dma engine (debug only) + .DmaTracing ( 0 ) + ) i_rx_dma_backend ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .dma_id_i ( BaseDMAId + 0 ), + .axi_dma_req_o ( axi_dma_rx_req ), + .axi_dma_res_i ( axi_dma_rx_resp ), + .burst_req_i ( rx_burst_req ), + .valid_i ( rx_req_valid_i ), + .ready_o ( rx_req_ready_o ), + .backend_idle_o ( idle_o [0] ), + .trans_complete_o ( rx_rsp_valid_o ) + ); + + axi_dma_backend #( + .DataWidth ( DmaDataWidth ), + .AddrWidth ( DmaAddrWidth ), + .IdWidth ( DmaAxiIdWidthMst ), + .AxReqFifoDepth ( AxiAxReqDepth ), + .TransFifoDepth ( TfReqFifoDepth ), + .BufferDepth ( 3 ), // minimal number giving full performance + .axi_req_t ( axi_dma_req_mst_t ), + .axi_res_t ( axi_dma_resp_mst_t ), + .burst_req_t ( burst_req_t ), + .DmaIdWidth ( 32 ), // the width of the internal id of the dma engine (debug only) + .DmaTracing ( 0 ) + ) i_tx_dma_backend ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .dma_id_i ( BaseDMAId + 1 ), + .axi_dma_req_o ( axi_dma_tx_req ), + .axi_dma_res_i ( axi_dma_tx_resp ), + .burst_req_i ( tx_burst_req ), + .valid_i ( tx_req_valid_i ), + .ready_o ( tx_req_ready_o ), + .backend_idle_o ( idle_o [1] ), + .trans_complete_o ( tx_rsp_valid_o ) + ); + + // include a x-bar to allow full-duplex copy + localparam int unsigned NumRules = 2; + localparam int unsigned IdxPcie = 0; + localparam int unsigned IdxNhi = 1; + + typedef struct packed { + int unsigned idx; + logic [64:0] start_addr; + logic [64:0] end_addr; + } xbar_rule_65_t; + + xbar_rule_65_t [NumRules-1:0] addr_map; + + assign addr_map[IdxPcie] = '{ + start_addr: PCIeStartAddr, + end_addr: PCIeEndAddr, + idx: IdxPcie + }; + + //I'm not being more detailed here because a detailed + //address map is already in the NHI interconnect + assign addr_map[IdxNhi] = '{ + start_addr: NHIStartAddr, + end_addr: NHIEndAddr, + idx: IdxNhi + }; + + localparam NumMstPorts = 2; + localparam NumSlvPorts = 2; + + /* verilator lint_off WIDTHCONCAT */ + localparam axi_pkg::xbar_cfg_t XbarCfg = '{ + NoSlvPorts: NumSlvPorts, + NoMstPorts: NumMstPorts, + MaxMstTrans: 16, + MaxSlvTrans: 32, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: DmaAxiIdWidthMst, + AxiIdUsedSlvPorts: DmaAxiIdWidthMst, + AxiAddrWidth: DmaAddrWidth, + AxiDataWidth: DmaDataWidth, + NoAddrRules: NumRules + }; + /* verilator lint_on WIDTHCONCAT */ + + axi_xbar #( + .Cfg ( XbarCfg ), + .slv_aw_chan_t ( aw_chan_mst_t ), + .mst_aw_chan_t ( aw_chan_slv_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( b_chan_mst_t ), + .mst_b_chan_t ( b_chan_slv_t ), + .slv_ar_chan_t ( ar_chan_mst_t ), + .mst_ar_chan_t ( ar_chan_slv_t ), + .slv_r_chan_t ( r_chan_mst_t ), + .mst_r_chan_t ( r_chan_slv_t ), + .slv_req_t ( axi_dma_req_mst_t ), + .slv_resp_t ( axi_dma_resp_mst_t ), + .mst_req_t ( axi_dma_req_slv_t ), + .mst_resp_t ( axi_dma_resp_slv_t ), + .rule_t ( xbar_rule_65_t ) + ) i_soc_dma_xbar ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ( 1'b0 ), + .slv_ports_req_i ( '{ axi_dma_rx_req, axi_dma_tx_req } ), + .slv_ports_resp_o ( '{ axi_dma_rx_resp, axi_dma_tx_resp } ), + .mst_ports_req_o ( '{ nhi_dma_req_o, pcie_dma_req_o } ), + .mst_ports_resp_i ( '{ nhi_dma_res_i, pcie_dma_res_i } ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) + ); + +endmodule : pspin_soc_dma diff --git a/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend.sv b/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend.sv new file mode 100644 index 0000000..e40a9d2 --- /dev/null +++ b/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend.sv @@ -0,0 +1,425 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +/// replaces the mchan in the pulp cluster if the new AXI DMA should be used +/// strictly 32 bit on the TCDM side. +module pulp_cluster_frontend #( + /// number of cores in the cluster + parameter int unsigned NumCores = -1, + /// id width of peripherals + parameter int unsigned PerifIdWidth = -1, + /// id width of the DMA AXI Master port + parameter int unsigned DmaAxiIdWidth = -1, + /// data width of the DMA AXI Master port + parameter int unsigned DmaDataWidth = -1, + /// address width of the DMA AXI Master port + parameter int unsigned DmaAddrWidth = -1, + /// number of AX requests in-flight + parameter int unsigned AxiAxReqDepth = -1, + /// number of 1D transfers buffered in backend + parameter int unsigned TfReqFifoDepth = -1, + /// data request type + parameter type axi_req_t = logic, + /// data response type + parameter type axi_res_t = logic, + /// transfer descriptor for hw access to DMA + parameter type transf_descr_t = logic +)( + input logic clk_i, + input logic rst_ni, + input logic [5:0] cluster_id_i, + /// x-bar + input logic ctrl_pe_targ_req_i, + input logic ctrl_pe_targ_type_i, + input logic [3:0] ctrl_pe_targ_be_i, + input logic [31:0] ctrl_pe_targ_add_i, + input logic [31:0] ctrl_pe_targ_data_i, + input logic [PerifIdWidth-1:0] ctrl_pe_targ_id_i, + output logic ctrl_pe_targ_gnt_o, + output logic ctrl_pe_targ_r_valid_o, + output logic [31:0] ctrl_pe_targ_r_data_o, + output logic ctrl_pe_targ_r_opc_o, + output logic [PerifIdWidth-1:0] ctrl_pe_targ_r_id_o, + /// from cores + input logic [NumCores-1:0] ctrl_targ_req_i, + input logic [NumCores-1:0] ctrl_targ_type_i, + input logic [NumCores-1:0][3:0] ctrl_targ_be_i, + input logic [NumCores-1:0][31:0] ctrl_targ_add_i, + input logic [NumCores-1:0][31:0] ctrl_targ_data_i, + output logic [NumCores-1:0] ctrl_targ_gnt_o, + output logic [NumCores-1:0] ctrl_targ_r_valid_o, + output logic [NumCores-1:0][31:0] ctrl_targ_r_data_o, + /// direct hw port + input logic dma_req_valid_i, + output logic dma_req_ready_o, + input transf_descr_t dma_req_i, + output logic dma_rsp_valid_o, + /// wide AXI port + output axi_req_t axi_dma_req_o, + input axi_res_t axi_dma_res_i, + /// status signal + output logic busy_o, + /// events and interrupts (cores) + output logic [NumCores-1:0] term_event_o, + output logic [NumCores-1:0] term_irq_o, + /// events and interrupts (peripherals) + output logic term_event_pe_o, + output logic term_irq_pe_o, + /// events and interrupts (cores) + output logic [NumCores-1:0] no_req_pending_o +); + + // number of register sets in fe + localparam int unsigned NumRegs = NumCores + 1; + + // arbitration index width + localparam int unsigned IdxWidth = (NumRegs + 1 > 32'd1) ? unsigned'($clog2(NumRegs + 1)) : 32'd1; + + // buffer depth + localparam int unsigned BufferDepth = 3; // + 64; + + localparam int unsigned TfFifoDepth = TfReqFifoDepth + AxiAxReqDepth + BufferDepth + 1; + + // 1D burst request + typedef logic [DmaAddrWidth-1 :0] addr_t; + typedef logic [DmaAxiIdWidth-1:0] axi_id_t; + typedef struct packed { + axi_id_t id; + addr_t src, dst, num_bytes; + axi_pkg::cache_t cache_src, cache_dst; + axi_pkg::burst_t burst_src, burst_dst; + logic decouple_rw; + logic deburst; + logic serialize; + } burst_req_t; + + // debug only: logfile + integer log_file; + string log_file_name; + + // rr input + transf_descr_t [NumRegs-1:0] transf_descr; + logic [NumRegs-1:0] be_ready; + logic [NumRegs-1:0] be_valid; + // rr output + transf_descr_t transf_descr_arb; + logic be_ready_arb; + logic be_valid_arb; + // the index ob the chosen pe + logic [IdxWidth-1:0] pe_idx_arb; + + // burst request definition + burst_req_t burst_req; + + // transaction id + logic [31:0] next_id, done_id; + + // keep track of peripherals + logic [PerifIdWidth-1:0] peripherals_id_q; + + // backend idle signal + logic be_idle; + logic trans_complete; + + // information about most recent transfer + logic [IdxWidth-1:0] tf_head; + logic tf_empty; + + // define a counter to keep track of the cores individual requests + localparam int unsigned MaxNumRequests = TfReqFifoDepth + BufferDepth + 1; + localparam int unsigned MaxReqWidth = $clog2(MaxNumRequests); + logic [NumCores-1:0][MaxReqWidth-1:0] core_tf_num_d, core_tf_num_q; + + // generate registers for cores + for (genvar i = 0; i < NumCores; i++) begin : gen_core_regs + + pulp_cluster_frontend_regs #( + .transf_descr_t ( transf_descr_t ) + ) i_dma_conf_regs_cores ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .ctrl_req_i ( ctrl_targ_req_i [i] ), + .ctrl_type_i ( ctrl_targ_type_i [i] ), + .ctrl_be_i ( ctrl_targ_be_i [i] ), + .ctrl_add_i ( ctrl_targ_add_i [i] ), + .ctrl_data_i ( ctrl_targ_data_i [i] ), + .ctrl_gnt_o ( ctrl_targ_gnt_o [i] ), + .ctrl_valid_o ( ctrl_targ_r_valid_o [i] ), + .ctrl_data_o ( ctrl_targ_r_data_o [i] ), + .next_id_i ( next_id ), + .done_id_i ( done_id ), + .be_ready_i ( be_ready [i] ), + .be_valid_o ( be_valid [i] ), + .be_busy_i ( busy_o ), + .transf_descr_o ( transf_descr [i] ) + ); + end // gen_core_regs + + // generate registers for cores + for (genvar i = 0; i < NumCores; i++) begin : gen_req_counters + //increase counter if tf is started + always_comb begin : proc_counter + // default + core_tf_num_d[i] = core_tf_num_q[i]; + // increase + if (be_ready[i] & be_valid[i] & transf_descr[i].num_bytes != 0) begin + core_tf_num_d[i] = core_tf_num_d[i] + 1; + end + // decrement + if ((tf_head == i) & !tf_empty & trans_complete) begin + core_tf_num_d[i] = core_tf_num_d[i] - 1; + end + end + // assign output + assign no_req_pending_o[i] = core_tf_num_d[i] == 0; + end // gen_req_counters + + // generate registers for peripherals + pulp_cluster_frontend_regs #( + .transf_descr_t ( transf_descr_t ) + ) i_dma_conf_regs_periphs ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .ctrl_req_i ( ctrl_pe_targ_req_i ), + .ctrl_type_i ( ctrl_pe_targ_type_i ), + .ctrl_be_i ( ctrl_pe_targ_be_i ), + .ctrl_add_i ( ctrl_pe_targ_add_i ), + .ctrl_data_i ( ctrl_pe_targ_data_i ), + .ctrl_gnt_o ( ctrl_pe_targ_gnt_o ), + .ctrl_valid_o ( ctrl_pe_targ_r_valid_o ), + .ctrl_data_o ( ctrl_pe_targ_r_data_o ), + .next_id_i ( next_id ), + .done_id_i ( done_id ), + .be_ready_i ( be_ready [NumCores] ), + .be_valid_o ( be_valid [NumCores] ), + .be_busy_i ( busy_o ), + .transf_descr_o ( transf_descr [NumCores] ) + ); + + // set this to zero as it is done mchan + assign ctrl_pe_targ_r_opc_o = 1'b0; + + // round robin to arbitrate + rr_arb_tree #( + .NumIn ( NumRegs + 1 ), // +1 is the external unit + .DataWidth ( -1 ), + .DataType ( transf_descr_t ), + .ExtPrio ( 0 ), + .AxiVldRdy ( 1 ), + .LockIn ( 1 ) + ) i_rr_arb_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .rr_i ( '0 ), + .req_i ( { dma_req_valid_i, be_valid } ), + .gnt_o ( { dma_req_ready_o, be_ready } ), + .data_i ( { dma_req_i, transf_descr } ), + .gnt_i ( be_ready_arb ), + .req_o ( be_valid_arb ), + .data_o ( transf_descr_arb ), + .idx_o ( pe_idx_arb ) + ); + + // global transfer id + transfer_id_gen #( + // keep this fixed at 32 bit as two 32 bit counters are + // relatively cheap + .ID_WIDTH ( 32 ) + ) i_transfer_id_gen ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .issue_i ( be_ready_arb & be_valid_arb & transf_descr_arb.num_bytes != 0 ), + .retire_i ( trans_complete ), + .next_o ( next_id ), + .completed_o ( done_id ) + ); + + // hold a bit for each launched transfer where it came from + fifo_v3 #( + .dtype ( logic [IdxWidth-1:0] ), + .DEPTH ( TfFifoDepth ) + ) i_tf_id_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( 1'b0 ), + .full_o ( ), + .empty_o ( tf_empty ), + .usage_o ( ), + .data_i ( pe_idx_arb ), // we are external tf + .push_i ( be_ready_arb & be_valid_arb & transf_descr_arb.num_bytes != 0 ), + .data_o ( tf_head ), + .pop_i ( trans_complete ) + ); + + assign dma_rsp_valid_o = (tf_head == NumRegs) & !tf_empty & trans_complete; + // ack external tf tf came from ext valid we are done :) + + //---------NON SYNTHESIZABLE --------------- + `ifndef VERILATOR + //pragma translate_off + // log dma transfers to disk + initial begin + @(posedge rst_ni); + $sformat(log_file_name, "DMA_TRANSFERS_%2h.log", cluster_id_i); + log_file = $fopen(log_file_name, "w"); + $fwrite(log_file, "queue_time pe_id tf_id src dst num_bytes launch_time completion_time\n"); + $fclose(log_file); + end + // datatype to store arbitrated tf + typedef struct packed { + longint queue_time; + longint pe_id; + longint next_id; + longint src; + longint dst; + longint len; + } queued_tf_t; + // launch tf + typedef struct packed { + queued_tf_t queued_tf; + longint launch_time; + } launched_tf_t; + // create queued tf + queued_tf_t queued_tf, queued_tf_head; + // pack queued tf + always_comb begin + queued_tf.queue_time = $time(); + queued_tf.pe_id = pe_idx_arb; + queued_tf.next_id = next_id; + queued_tf.src = transf_descr_arb.src_addr; + queued_tf.dst = transf_descr_arb.dst_addr; + queued_tf.len = transf_descr_arb.num_bytes; + end + // use a fifo to model queuing + fifo_v3 #( + .dtype ( queued_tf_t ), + .DEPTH ( TfReqFifoDepth ) + ) i_queue_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( 1'b0 ), + .full_o ( ), + .empty_o ( ), + .usage_o ( ), + .data_i ( queued_tf ), + .push_i ( be_valid_arb && be_ready_arb ), + .data_o ( queued_tf_head ), + .pop_i ( i_axi_dma_backend.burst_req_pop ) + ); + // launched tf + launched_tf_t launched_tf, launched_tf_head; + // pack launched tf + always_comb begin + launched_tf.queued_tf = queued_tf_head; + launched_tf.launch_time = $time(); + end + // use a fifo to hold tf info while it goes through the backend + fifo_v3 #( + .dtype ( launched_tf_t ), + .DEPTH ( AxiAxReqDepth + BufferDepth + 1 ) + ) i_launch_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( 1'b0 ), + .full_o ( ), + .empty_o ( ), + .usage_o ( ), + .data_i ( launched_tf ), + .push_i ( i_axi_dma_backend.burst_req_pop ), + .data_o ( launched_tf_head ), + .pop_i ( trans_complete ) + ); + // write info to file + always @(posedge clk_i) begin + #0; + if(trans_complete) begin + log_file = $fopen(log_file_name, "a"); + $fwrite(log_file, "%0d %0d %0d 0x%0x 0x%0x %0d %0d %0d\n", + launched_tf_head.queued_tf.queue_time, launched_tf_head.queued_tf.pe_id, + launched_tf_head.queued_tf.next_id, launched_tf_head.queued_tf.src, + launched_tf_head.queued_tf.dst, launched_tf_head.queued_tf.len, + launched_tf_head.launch_time, $time() + ); + $fclose(log_file); + end + end + //pragma translate_on + `endif + //---------NON SYNTHESIZABLE --------------- + + // map arbitrated transfer descriptor onto generic burst request + always_comb begin : proc_map_to_1D_burst + burst_req = '0; + burst_req.src = transf_descr_arb.src_addr; + burst_req.dst = transf_descr_arb.dst_addr; + burst_req.num_bytes = transf_descr_arb.num_bytes; + burst_req.burst_src = axi_pkg::BURST_INCR; + burst_req.burst_dst = axi_pkg::BURST_INCR; + burst_req.decouple_rw = transf_descr_arb.decouple; + burst_req.deburst = transf_descr_arb.deburst; + burst_req.serialize = transf_descr_arb.serialize; + end + + // instantiate backend :) + axi_dma_backend #( + .DataWidth ( DmaDataWidth ), + .AddrWidth ( DmaAddrWidth ), + .IdWidth ( DmaAxiIdWidth ), + .AxReqFifoDepth ( AxiAxReqDepth ), + .TransFifoDepth ( TfReqFifoDepth ), + .BufferDepth ( BufferDepth ), // minimal 3 for giving full performance + .axi_req_t ( axi_req_t ), + .axi_res_t ( axi_res_t ), + .burst_req_t ( burst_req_t ), + .DmaIdWidth ( 6 ), + .DmaTracing ( 0 ) + ) i_axi_dma_backend ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .dma_id_i ( cluster_id_i ), + .axi_dma_req_o ( axi_dma_req_o ), + .axi_dma_res_i ( axi_dma_res_i ), + .burst_req_i ( burst_req ), + .valid_i ( be_valid_arb ), + .ready_o ( be_ready_arb ), + .backend_idle_o ( be_idle ), + .trans_complete_o ( trans_complete ) + ); + + // busy if not idle + assign busy_o = ~be_idle; + + // interrupts and events (unconditionally) + assign term_event_o = trans_complete ? '1 : '0; + assign term_irq_o = trans_complete ? '1 : '0; + assign term_event_pe_o = trans_complete ? '1 : '0; + assign term_irq_pe_o = trans_complete ? '1 : '0; + + // keep id for peripherals + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_id_peripherals + if(~rst_ni) begin + peripherals_id_q <= 0; + core_tf_num_q <= 0; + end else begin + peripherals_id_q <= ctrl_pe_targ_id_i; + core_tf_num_q <= core_tf_num_d; + end + end + + // id is returned + assign ctrl_pe_targ_r_id_o = peripherals_id_q; + +endmodule : pulp_cluster_frontend diff --git a/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend_regs.sv b/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend_regs.sv new file mode 100644 index 0000000..bd3de44 --- /dev/null +++ b/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend_regs.sv @@ -0,0 +1,205 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +// register file for one pe in the pulp_cluster_frontend +// strictly 32 bit on TCDM side. + +module pulp_cluster_frontend_regs #( + parameter type transf_descr_t = logic +)( + input logic clk_i, + input logic rst_ni, + // tcdm forwards channel + input logic ctrl_req_i, + input logic ctrl_type_i, + input logic [3:0] ctrl_be_i, + input logic [31:0] ctrl_add_i, + input logic [31:0] ctrl_data_i, + output logic ctrl_gnt_o, + // return channel + output logic ctrl_valid_o, + output logic [31:0] ctrl_data_o, + // transfer ids + input logic [31:0] next_id_i, + input logic [31:0] done_id_i, + // backend handshake + input logic be_ready_i, + output logic be_valid_o, + input logic be_busy_i, + output transf_descr_t transf_descr_o +); + + // DMA transfer descriptor + typedef struct packed { + logic [31:0] num_bytes; + logic [31:0] dst_addr; + logic [31:0] src_addr; + } transf_descr_regular_t; + + // data stored + typedef union packed { + logic [2:0][31:0] words; + logic [2:0][ 3:0][7:0] bytes; + transf_descr_regular_t transfer; + } dma_data_store_t; + + // have 8 registers per PE + logic [5:0] reg_addr; + // 6 registers are r/w so we need to keep a state + dma_data_store_t data_store_d, data_store_q; + logic [2:0] conf_store_d, conf_store_q; + // data is delayed one cycle + logic [31:0] rdata_d, rdata_q; + logic valid_d, valid_q; + + // assign address to register address + assign reg_addr = ctrl_add_i[5:0]; + + // address decode + always_comb begin : proc_address_decode + + // defaults + ctrl_gnt_o = 1'b0; + rdata_d = '0; + valid_d = 1'b0; + be_valid_o = 1'b0; + data_store_d = data_store_q; + conf_store_d = conf_store_q; + + // if we have access + if (ctrl_req_i) begin + + // only grant if a request is here + ctrl_gnt_o = 1'b1; + + // address decoding + case(reg_addr) + // source address (low) + 6'h00 : begin + valid_d = 1'b1; + if (ctrl_type_i) begin // read + rdata_d = data_store_q.words[0]; + end else begin // write + for (int i = 0; i < 4; i++) begin + if (ctrl_be_i[i]) + data_store_d.bytes[0][i] = ctrl_data_i[8 * i +: 8]; + end + end + end + //// source address (high) + //6'h04 : begin + // valid_d = 1'b1; + // if (ctrl_type_i) begin // read + // rdata_d = data_store_q.words[1]; + // end else begin // write + // for (int i = 0; i < 4; i++) begin + // if (ctrl_be_i[i]) + // data_store_d.bytes[1][i] = ctrl_data_i[8 * i +: 8]; + // end + // end + //end + // destination address (low) + 6'h08 : begin + valid_d = 1'b1; + if (ctrl_type_i) begin // read + rdata_d = data_store_q.words[1]; + end else begin // write + for (int i = 0; i < 4; i++) begin + if (ctrl_be_i[i]) + data_store_d.bytes[1][i] = ctrl_data_i[8 * i +: 8]; + end + end + end + //// destination address (high) + //6'h0c : begin + // valid_d = 1'b1; + // if (ctrl_type_i) begin // read + // rdata_d = data_store_q.words[3]; + // end else begin // write + // for (int i = 0; i < 4; i++) begin + // if (ctrl_be_i[i]) + // data_store_d.bytes[3][i] = ctrl_data_i[8 * i +: 8]; + // end + // end + //end + // num bytes + 6'h10 : begin + valid_d = 1'b1; + if (ctrl_type_i) begin // read + rdata_d = data_store_q.words[2]; + end else begin // write + for (int i = 0; i < 4; i++) begin + if (ctrl_be_i[i]) + data_store_d.bytes[2][i] = ctrl_data_i[8 * i +: 8]; + end + end + end + // next_id + 6'h18 : begin + valid_d = be_ready_i; + if (ctrl_type_i) begin // read + ctrl_gnt_o = be_ready_i; + rdata_d = next_id_i; + be_valid_o = 1'b1; + end + end + // completed id + 6'h20 : begin + valid_d = 1'b1; + if (ctrl_type_i) begin // read + rdata_d = done_id_i; + end + end + // status / conf + 6'h28 : begin + valid_d = 1'b1; + if (ctrl_type_i) begin // read + rdata_d = {15'h0000, be_busy_i, 13'h0000, conf_store_q}; + end else begin // write + conf_store_d = ctrl_data_i[2:0]; + end + end + // default case + default : begin + rdata_d = '0; + valid_d = 1'b1; + end + endcase + end + end + + // data store + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_data_store + if(~rst_ni) begin + data_store_q <= '0; + conf_store_q <= 3'b001; + rdata_q <= '0; + valid_q <= '0; + end else begin + data_store_q <= data_store_d; + conf_store_q <= conf_store_d; + rdata_q <= rdata_d; + valid_q <= valid_d; + end + end + + assign ctrl_valid_o = valid_q; + assign ctrl_data_o = rdata_q; + + assign transf_descr_o.num_bytes = data_store_q.transfer.num_bytes; + assign transf_descr_o.dst_addr = data_store_q.transfer.dst_addr; + assign transf_descr_o.src_addr = data_store_q.transfer.src_addr; + assign transf_descr_o.decouple = conf_store_q[0]; + assign transf_descr_o.deburst = conf_store_q[1]; + assign transf_descr_o.serialize = conf_store_q[2]; + +endmodule : pulp_cluster_frontend_regs diff --git a/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/transfer_id_gen.sv b/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/transfer_id_gen.sv new file mode 100644 index 0000000..2fa6008 --- /dev/null +++ b/hw/deps/axi/src/dma/frontends/pulp_cluster_frontend/src/transfer_id_gen.sv @@ -0,0 +1,58 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Thomas Benz + +// transaction id generator. just increase the transaction id on every request + +module transfer_id_gen #( + parameter int unsigned ID_WIDTH = -1 +) ( + input logic clk_i, + input logic rst_ni, + // new request is pushed + input logic issue_i, + // request is popped + input logic retire_i, + // next id is + output logic [ID_WIDTH-1:0] next_o, + // last id completed is + output logic [ID_WIDTH-1:0] completed_o +); + + //-------------------------------------- + // counters + //-------------------------------------- + logic [ID_WIDTH-1:0] next_d, next_q; + logic [ID_WIDTH-1:0] completed_d, completed_q; + + // count up on events + assign next_d = (issue_i == 1'b1) ? next_q + 'h1 : next_q; + assign completed_d = (retire_i == 1'b1) ? completed_q + 'h1 : completed_q; + + // assign outputs + assign next_o = next_q; + assign completed_o = completed_q; + + //-------------------------------------- + // state + //-------------------------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_id_gen + if(~rst_ni) begin + next_q <= 1; + completed_q <= 0; + end else begin + next_q <= next_d; + completed_q <= completed_d; + end + end + +endmodule : transfer_id_gen + diff --git a/hw/deps/axi2apb/src/axi2apb_64_32.sv b/hw/deps/axi2apb/src/axi2apb_64_32.sv new file mode 100644 index 0000000..7c7343b --- /dev/null +++ b/hw/deps/axi2apb/src/axi2apb_64_32.sv @@ -0,0 +1,756 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Igor Loi +// Davide Rossi +// Florian Zaruba + +`define OKAY 2'b00 +`define EXOKAY 2'b01 +`define SLVERR 2'b10 +`define DECERR 2'b11 + +module axi2apb_64_32 #( + parameter int unsigned AXI4_ADDRESS_WIDTH = 32, + parameter int unsigned AXI4_RDATA_WIDTH = 64, + parameter int unsigned AXI4_WDATA_WIDTH = 64, + parameter int unsigned AXI4_ID_WIDTH = 16, + parameter int unsigned AXI4_USER_WIDTH = 10, + parameter int unsigned AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, + + parameter int unsigned BUFF_DEPTH_SLAVE = 4, + parameter int unsigned APB_NUM_SLAVES = 8, + parameter int unsigned APB_ADDR_WIDTH = 12 +) +( + input logic ACLK, + input logic ARESETn, + input logic test_en_i, + // --------------------------------------------------------- + // AXI TARG Port Declarations ------------------------------ + // --------------------------------------------------------- + //AXI write address bus -------------- // USED// ----------- + input logic [AXI4_ID_WIDTH-1:0] AWID_i , + input logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR_i , + input logic [ 7:0] AWLEN_i , + input logic [ 2:0] AWSIZE_i , + input logic [ 1:0] AWBURST_i , + input logic AWLOCK_i , + input logic [ 3:0] AWCACHE_i , + input logic [ 2:0] AWPROT_i , + input logic [ 3:0] AWREGION_i , + input logic [ 5:0] AWATOP_i , + input logic [ AXI4_USER_WIDTH-1:0] AWUSER_i , + input logic [ 3:0] AWQOS_i , + input logic AWVALID_i , + output logic AWREADY_o , + // --------------------------------------------------------- + + //AXI write data bus -------------- // USED// -------------- + input logic [AXI_NUMBYTES-1:0][7:0] WDATA_i , + input logic [AXI_NUMBYTES-1:0] WSTRB_i , + input logic WLAST_i , + input logic [AXI4_USER_WIDTH-1:0] WUSER_i , + input logic WVALID_i , + output logic WREADY_o , + // --------------------------------------------------------- + + //AXI write response bus -------------- // USED// ---------- + output logic [AXI4_ID_WIDTH-1:0] BID_o , + output logic [ 1:0] BRESP_o , + output logic BVALID_o , + output logic [AXI4_USER_WIDTH-1:0] BUSER_o , + input logic BREADY_i , + // --------------------------------------------------------- + + //AXI read address bus ------------------------------------- + input logic [AXI4_ID_WIDTH-1:0] ARID_i , + input logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR_i , + input logic [ 7:0] ARLEN_i , + input logic [ 2:0] ARSIZE_i , + input logic [ 1:0] ARBURST_i , + input logic ARLOCK_i , + input logic [ 3:0] ARCACHE_i , + input logic [ 2:0] ARPROT_i , + input logic [ 3:0] ARREGION_i , + input logic [ AXI4_USER_WIDTH-1:0] ARUSER_i , + input logic [ 3:0] ARQOS_i , + input logic ARVALID_i , + output logic ARREADY_o , + // --------------------------------------------------------- + + //AXI read data bus ---------------------------------------- + output logic [AXI4_ID_WIDTH-1:0] RID_o , + output logic [AXI4_RDATA_WIDTH-1:0] RDATA_o , + output logic [ 1:0] RRESP_o , + output logic RLAST_o , + output logic [AXI4_USER_WIDTH-1:0] RUSER_o , + output logic RVALID_o , + input logic RREADY_i , + // --------------------------------------------------------- + + output logic PENABLE , + output logic PWRITE , + output logic [APB_ADDR_WIDTH-1:0] PADDR , + output logic PSEL , + output logic [31:0] PWDATA , + input logic [31:0] PRDATA , + input logic PREADY , + input logic PSLVERR +); + + // -------------------- + // AXI write address bus + // -------------------- + logic [AXI4_ID_WIDTH-1:0] AWID; + logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR; + logic [ 7:0] AWLEN; + logic [ 2:0] AWSIZE; + logic [ 1:0] AWBURST; + logic AWLOCK; + logic [ 3:0] AWCACHE; + logic [ 2:0] AWPROT; + logic [ 3:0] AWREGION; + logic [ AXI4_USER_WIDTH-1:0] AWUSER; + logic [ 3:0] AWQOS; + logic AWVALID; + logic AWREADY; + // -------------------- + // AXI write data bus + // -------------------- + logic [1:0][31:0] WDATA; // from FIFO + logic [AXI_NUMBYTES-1:0] WSTRB; // from FIFO + logic WLAST; // from FIFO + logic [AXI4_USER_WIDTH-1:0] WUSER; // from FIFO + logic WVALID; // from FIFO + logic WREADY; // TO FIFO + // -------------------- + // AXI write response bus + // -------------------- + logic [AXI4_ID_WIDTH-1:0] BID; + logic [ 1:0] BRESP; + logic BVALID; + logic [AXI4_USER_WIDTH-1:0] BUSER; + logic BREADY; + // -------------------- + // AXI read address bus + // -------------------- + logic [AXI4_ID_WIDTH-1:0] ARID; + logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR; + logic [ 7:0] ARLEN; + logic [ 2:0] ARSIZE; + logic [ 1:0] ARBURST; + logic ARLOCK; + logic [ 3:0] ARCACHE; + logic [ 2:0] ARPROT; + logic [ 3:0] ARREGION; + logic [ AXI4_USER_WIDTH-1:0] ARUSER; + logic [ 3:0] ARQOS; + logic ARVALID; + logic ARREADY; + // -------------------- + // AXI read data bus + // -------------------- + logic [AXI4_ID_WIDTH-1:0] RID; + logic [1:0][31:0] RDATA; + logic [ 1:0] RRESP; + logic RLAST; + logic [AXI4_USER_WIDTH-1:0] RUSER; + logic RVALID; + logic RREADY; + + enum logic [3:0] { IDLE, + SINGLE_RD, SINGLE_RD_64, + BURST_RD_1, BURST_RD, BURST_RD_64, + BURST_WR, BURST_WR_64, + SINGLE_WR,SINGLE_WR_64, + WAIT_R_PREADY, WAIT_W_PREADY + } CS, NS; + + logic W_word_sel; + + logic [APB_ADDR_WIDTH-1:0] address; + + logic read_req; + logic write_req; + + logic sample_AR; + logic [8:0] ARLEN_Q; + logic decr_ARLEN; + + logic sample_AW; + logic [8:0] AWLEN_Q; + logic decr_AWLEN; + + logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR_Q; + logic incr_ARADDR; + + logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR_Q; + logic incr_AWADDR; + + logic sample_RDATA_0; // sample the first 32 bit chunk to be aggregated in 64 bit rdata + logic sample_RDATA_1; // sample the second 32 bit chunk to be aggregated in 64 bit rdata + logic [31:0] RDATA_Q_0; + logic [31:0] RDATA_Q_1; + + assign PENABLE = write_req | read_req; + assign PWRITE = write_req; + assign PADDR = address[APB_ADDR_WIDTH-1:0]; + + assign PWDATA = WDATA[W_word_sel]; + assign PSEL = 1'b1; + + // AXI WRITE ADDRESS CHANNEL BUFFER + axi_aw_buffer #( + .ID_WIDTH ( AXI4_ID_WIDTH ), + .ADDR_WIDTH ( AXI4_ADDRESS_WIDTH ), + .USER_WIDTH ( AXI4_USER_WIDTH ), + .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) + ) slave_aw_buffer_i ( + .clk_i ( ACLK ), + .rst_ni ( ARESETn ), + .test_en_i ( test_en_i ), + .slave_valid_i ( AWVALID_i ), + .slave_addr_i ( AWADDR_i ), + .slave_prot_i ( AWPROT_i ), + .slave_region_i ( AWREGION_i ), + .slave_atop_i ( '0 ), + .slave_len_i ( AWLEN_i ), + .slave_size_i ( AWSIZE_i ), + .slave_burst_i ( AWBURST_i ), + .slave_lock_i ( AWLOCK_i ), + .slave_cache_i ( AWCACHE_i ), + .slave_qos_i ( AWQOS_i ), + .slave_id_i ( AWID_i ), + .slave_user_i ( AWUSER_i ), + .slave_ready_o ( AWREADY_o ), + .master_valid_o ( AWVALID ), + .master_addr_o ( AWADDR ), + .master_prot_o ( AWPROT ), + .master_region_o ( AWREGION ), + .master_atop_o ( ), + .master_len_o ( AWLEN ), + .master_size_o ( AWSIZE ), + .master_burst_o ( AWBURST ), + .master_lock_o ( AWLOCK ), + .master_cache_o ( AWCACHE ), + .master_qos_o ( AWQOS ), + .master_id_o ( AWID ), + .master_user_o ( AWUSER ), + .master_ready_i ( AWREADY ) + ); + // AXI WRITE ADDRESS CHANNEL BUFFER + axi_ar_buffer #( + .ID_WIDTH ( AXI4_ID_WIDTH ), + .ADDR_WIDTH ( AXI4_ADDRESS_WIDTH ), + .USER_WIDTH ( AXI4_USER_WIDTH ), + .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) + ) slave_ar_buffer_i ( + .clk_i ( ACLK ), + .rst_ni ( ARESETn ), + .test_en_i ( test_en_i ), + .slave_valid_i ( ARVALID_i ), + .slave_addr_i ( ARADDR_i ), + .slave_prot_i ( ARPROT_i ), + .slave_region_i ( ARREGION_i ), + .slave_len_i ( ARLEN_i ), + .slave_size_i ( ARSIZE_i ), + .slave_burst_i ( ARBURST_i ), + .slave_lock_i ( ARLOCK_i ), + .slave_cache_i ( ARCACHE_i ), + .slave_qos_i ( ARQOS_i ), + .slave_id_i ( ARID_i ), + .slave_user_i ( ARUSER_i ), + .slave_ready_o ( ARREADY_o ), + .master_valid_o ( ARVALID ), + .master_addr_o ( ARADDR ), + .master_prot_o ( ARPROT ), + .master_region_o ( ARREGION ), + .master_len_o ( ARLEN ), + .master_size_o ( ARSIZE ), + .master_burst_o ( ARBURST ), + .master_lock_o ( ARLOCK ), + .master_cache_o ( ARCACHE ), + .master_qos_o ( ARQOS ), + .master_id_o ( ARID ), + .master_user_o ( ARUSER ), + .master_ready_i ( ARREADY ) + ); + axi_w_buffer #( + .DATA_WIDTH ( AXI4_WDATA_WIDTH ), + .USER_WIDTH ( AXI4_USER_WIDTH ), + .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) + ) slave_w_buffer_i ( + .clk_i ( ACLK ), + .rst_ni ( ARESETn ), + .test_en_i ( test_en_i ), + .slave_valid_i ( WVALID_i ), + .slave_data_i ( WDATA_i ), + .slave_strb_i ( WSTRB_i ), + .slave_user_i ( WUSER_i ), + .slave_last_i ( WLAST_i ), + .slave_ready_o ( WREADY_o ), + .master_valid_o ( WVALID ), + .master_data_o ( WDATA ), + .master_strb_o ( WSTRB ), + .master_user_o ( WUSER ), + .master_last_o ( WLAST ), + .master_ready_i ( WREADY ) + ); + axi_r_buffer #( + .ID_WIDTH ( AXI4_ID_WIDTH ), + .DATA_WIDTH ( AXI4_RDATA_WIDTH ), + .USER_WIDTH ( AXI4_USER_WIDTH ), + .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) + ) slave_r_buffer_i ( + .clk_i ( ACLK ), + .rst_ni ( ARESETn ), + .test_en_i ( test_en_i ), + .slave_valid_i ( RVALID ), + .slave_data_i ( RDATA ), + .slave_resp_i ( RRESP ), + .slave_user_i ( RUSER ), + .slave_id_i ( RID ), + .slave_last_i ( RLAST ), + .slave_ready_o ( RREADY ), + .master_valid_o ( RVALID_o ), + .master_data_o ( RDATA_o ), + .master_resp_o ( RRESP_o ), + .master_user_o ( RUSER_o ), + .master_id_o ( RID_o ), + .master_last_o ( RLAST_o ), + .master_ready_i ( RREADY_i ) + ); + + axi_b_buffer #( + .ID_WIDTH ( AXI4_ID_WIDTH ), + .USER_WIDTH ( AXI4_USER_WIDTH ), + .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) + ) slave_b_buffer_i ( + .clk_i ( ACLK ), + .rst_ni ( ARESETn ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( BVALID ), + .slave_resp_i ( BRESP ), + .slave_id_i ( BID ), + .slave_user_i ( BUSER ), + .slave_ready_o ( BREADY ), + + .master_valid_o ( BVALID_o ), + .master_resp_o ( BRESP_o ), + .master_id_o ( BID_o ), + .master_user_o ( BUSER_o ), + .master_ready_i ( BREADY_i ) + ); + + always_comb begin + read_req = 1'b0; + write_req = 1'b0; + W_word_sel = 1'b0; // Write Word Selector + + sample_AW = 1'b0; + decr_AWLEN = 1'b0; + sample_AR = 1'b0; + decr_ARLEN = 1'b0; + + incr_AWADDR = 1'b0; + incr_ARADDR = 1'b0; + + sample_RDATA_0 = 1'b0; + sample_RDATA_1 = 1'b0; + + ARREADY = 1'b0; + AWREADY = 1'b0; + WREADY = 1'b0; + RDATA = '0; + + BVALID = 1'b0; + BRESP = `OKAY; + BID = AWID; + BUSER = AWUSER; + + RVALID = 1'b0; + RLAST = 1'b0; + RID = ARID; + RUSER = ARUSER; + RRESP = `OKAY; + + case(CS) + + WAIT_R_PREADY: begin + sample_AR = 1'b0; + read_req = 1'b1; + address = ARADDR; + + if (PREADY == 1'b1) begin// APB is READY --> RDATA is AVAILABLE + if (ARLEN == 0) begin + case (ARSIZE) + 3'h3: begin + NS = SINGLE_RD_64; + if (ARADDR[2:0] == 3'h4) + sample_RDATA_1 = 1'b1; + else sample_RDATA_0 = 1'b1; + end + + default: begin + NS = SINGLE_RD; + if (ARADDR[2:0] == 3'h4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + endcase + end else begin // ARLEN > 0 --> BURST + NS = BURST_RD_64; + sample_RDATA_0 = 1'b1; + decr_ARLEN = 1'b1; + incr_ARADDR = 1'b1; + end + end else begin // APB not ready + NS = WAIT_R_PREADY; + end + end + + WAIT_W_PREADY: begin + address = AWADDR; + write_req = 1'b1; + + if (AWADDR[2:0] == 3'h4) + W_word_sel = 1'b1; + else + W_word_sel = 1'b0; + + // There is a Pending WRITE!! + if (PREADY == 1'b1) begin // APB is READY --> WDATA is LAtched + if (AWLEN == 0) begin // single write + case (AWSIZE) + 3'h3: NS = SINGLE_WR_64; + default: NS = SINGLE_WR; + endcase + end else begin // BURST WRITE + sample_AW = 1'b1; + NS = BURST_WR_64; + end + end else begin // APB not READY + NS = WAIT_W_PREADY; + end + end + + IDLE: begin + if (ARVALID == 1'b1) begin + sample_AR = 1'b1; + read_req = 1'b1; + address = ARADDR; + + if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE + if (ARLEN == 0) begin + case (ARSIZE) + 3'h3: begin + NS = SINGLE_RD_64; + if (ARADDR[2:0] == 4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + default: begin + NS = SINGLE_RD; + if (ARADDR[2:0] == 4) + sample_RDATA_1 = 1'b1; + else + sample_RDATA_0 = 1'b1; + end + endcase end else begin //ARLEN > 0 --> BURST + NS = BURST_RD_64; + sample_RDATA_0 = 1'b1; + end + end else begin // APB not ready + NS = WAIT_R_PREADY; + end + end else begin + + if (AWVALID) begin //: _VALID_AW_REQ_ + if (WVALID) begin // : _VALID_W_REQ_ + write_req = 1'b1; + address = AWADDR; + + if (AWADDR[2:0] == 3'h4) + W_word_sel = 1'b1; + else + W_word_sel = 1'b0; + + // There is a Pending WRITE!! + if (PREADY == 1'b1) begin// APB is READY --> WDATA is LAtched _APB_SLAVE_READY_ + if(AWLEN == 0) begin //: _SINGLE_WRITE_ + case(AWSIZE) + 3'h3: NS = SINGLE_WR_64; + default: NS = SINGLE_WR; + endcase + end else begin // BURST WRITE + sample_AW = 1'b1; + if ((AWADDR[2:0] == 3'h4) && (WSTRB[7:4] == 0)) + incr_AWADDR = 1'b0; + else + incr_AWADDR = 1'b1; + NS = BURST_WR_64; + end + end else begin// APB not READY + NS = WAIT_W_PREADY; + end + end else begin // GOT ADDRESS WRITE, not DATA + write_req = 1'b0; + address = '0; + NS = IDLE; + end + end else begin// No requests + NS = IDLE; + address = '0; + end + end + end + + SINGLE_WR_64: begin + address = AWADDR + 4; + W_word_sel = 1'b1; // write the Second data chunk + write_req = WVALID; + if (WVALID) begin + if (PREADY == 1'b1) + NS = SINGLE_WR; + else + NS = SINGLE_WR_64; + end else begin + NS = SINGLE_WR_64; + end + end + + SINGLE_WR: begin + BVALID = 1'b1; + address = '0; + if (BREADY) begin + NS = IDLE; + AWREADY = 1'b1; + WREADY = 1'b1; + end else begin + NS = SINGLE_WR; + end + end + + BURST_WR_64: begin + W_word_sel = 1'b1; // write the Second data chunk first + write_req = WVALID & (|WSTRB[7:4]); + address = AWADDR_Q; // second Chunk, Fixzed Burst + + if (WVALID) begin + if (&WSTRB[7:4]) begin + if(PREADY == 1'b1) begin + NS = BURST_WR; + WREADY = 1'b1; // pop onother data from the WDATA fifo + decr_AWLEN = 1'b1; // decrement the remaining BURST beat + incr_AWADDR = 1'b1; // increment address + end else begin + NS = BURST_WR_64; + end + end else begin + NS = BURST_WR; + WREADY = 1'b1; // pop onother data from the WDATA fifo + decr_AWLEN = 1'b1; // decrement the remaining BURST beat + incr_AWADDR = 1'b1; // increment address + end + end else begin + NS = BURST_WR_64; + end + end + + BURST_WR: begin + address = AWADDR_Q; // second Chunk, Fixzed Burst + if (AWLEN_Q == 0) begin // last : _BURST_COMPLETED_ + BVALID = 1'b1; + if (BREADY) begin + NS = IDLE; + AWREADY = 1'b1; + end else + NS = BURST_WR; + end else begin //: _BUSRST_NOT_COMPLETED_ + W_word_sel = 1'b0; // write the Second data chunk first + write_req = WVALID & (&WSTRB[3:0]); + if (WVALID) begin + if (PREADY == 1'b1) begin + NS = BURST_WR_64; + incr_AWADDR = 1'b1; + decr_AWLEN = 1'b1; //decrement the remaining BURST beat + end else + NS = BURST_WR; + end else begin + NS = BURST_WR_64; + end + end + end + + BURST_RD_64: begin + read_req = 1'b1; + address = ARADDR_Q; + + if (ARLEN_Q == 0) begin // burst completed + NS = IDLE; + ARREADY = 1'b1; + end else begin + if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE + decr_ARLEN = 1'b1; + sample_RDATA_1 = 1'b1; + NS = BURST_RD; + + if (ARADDR_Q[2:0] == 3'h4) + incr_ARADDR = 1'b1; + else + incr_ARADDR = 1'b0; + end + else begin + NS = BURST_RD_64; + end + end + end + + BURST_RD: begin + RVALID = 1'b1; + RDATA[0] = RDATA_Q_0; + RDATA[1] = RDATA_Q_1; + RLAST = (ARLEN_Q == 0) ? 1'b1 : 1'b0; + address = ARADDR_Q; + + if (RREADY) begin // ready to send back the rdata + if (ARLEN_Q == 0) begin // burst completed + NS = IDLE; + ARREADY = 1'b1; + end else begin //: _READ_BUSRST_NOT_COMPLETED_ + read_req = 1'b1; + if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE + sample_RDATA_0 = 1'b1; + NS = BURST_RD_64; + incr_ARADDR = 1'b1; + decr_ARLEN = 1'b1; + end else begin + NS = BURST_RD_1; + end + end + end else begin // NOT ready to send back the rdata + NS = BURST_RD; + end + end + + BURST_RD_1: begin + read_req = 1'b1; + address = ARADDR_Q; + + if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE + sample_RDATA_0 = 1'b1; + NS = BURST_RD_64; + incr_ARADDR = 1'b1; + decr_ARLEN = 1'b1; + end else begin + NS = BURST_RD_1; + end + end + + SINGLE_RD: begin + RVALID = 1'b1; + RDATA[0] = RDATA_Q_0; + RDATA[1] = RDATA_Q_1; + RLAST = 1; + address = '0; + + if (RREADY) begin // ready to send back the rdata + NS = IDLE; + ARREADY = 1'b1; + end else begin // NOT ready to send back the rdata + NS = SINGLE_RD; + end + end + + SINGLE_RD_64: begin + read_req = 1'b1; + address = ARADDR + 4; + if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE + NS = SINGLE_RD; + if(ARADDR[2:0] == 3'h4) + sample_RDATA_0 = 1'b1; + else + sample_RDATA_1 = 1'b1; + end else begin + NS = SINGLE_RD_64; + end + end + + default: begin + NS = IDLE; + address = '0; + end + endcase + end + + // ----------- + // Registers + // ----------- + always_ff @(posedge ACLK, negedge ARESETn) begin + if (ARESETn == 1'b0) begin + CS <= IDLE; + //Read Channel + ARLEN_Q <= '0; + AWADDR_Q <= '0; + //Write Channel + AWLEN_Q <= '0; + RDATA_Q_0 <= '0; + RDATA_Q_1 <= '0; + ARADDR_Q <= '0; + end else begin + CS <= NS; + + if (sample_AR) begin + ARLEN_Q <= {ARLEN,1'b0} + 2; + end else if (decr_ARLEN) begin + ARLEN_Q <= ARLEN_Q - 1; + end + + if (sample_RDATA_0) + RDATA_Q_0 <= PRDATA; + + if (sample_RDATA_1) + RDATA_Q_1 <= PRDATA; + + case ({sample_AW, decr_AWLEN}) + 2'b00: AWLEN_Q <= AWLEN_Q; + 2'b01: AWLEN_Q <= AWLEN_Q - 1; + 2'b10: AWLEN_Q <= {AWLEN, 1'b0} + 1; + 2'b11: AWLEN_Q <= {AWLEN, 1'b0}; + endcase + + case ({sample_AW, incr_AWADDR}) + 2'b00: AWADDR_Q <= AWADDR_Q; + 2'b01: AWADDR_Q <= AWADDR_Q + 4; + 2'b10: AWADDR_Q <= {AWADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000}; + 2'b11: AWADDR_Q <= {AWADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000} + 4; + endcase + + case({sample_AR, incr_ARADDR}) + 2'b00: ARADDR_Q <= ARADDR_Q; + 2'b01: ARADDR_Q <= ARADDR_Q + 4; + 2'b10: ARADDR_Q <= {ARADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000}; + 2'b11: ARADDR_Q <= {ARADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000} + 4; + endcase + end + end + + `ifndef VERILATOR + //pragma translate_off + assert property (@(posedge ACLK) (ARESETn && AWVALID_i |-> AWATOP_i == '0)) + else $error("This module does not support atomic operations!"); + //pragma translate_on + `endif + +endmodule diff --git a/hw/deps/axi2apb/src/axi2apb_wrap.sv b/hw/deps/axi2apb/src/axi2apb_wrap.sv new file mode 100644 index 0000000..8ccde3a --- /dev/null +++ b/hw/deps/axi2apb/src/axi2apb_wrap.sv @@ -0,0 +1,180 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module axi2apb_wrap #( + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 32, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_WIDTH = 6, + parameter int unsigned APB_ADDR_WIDTH = 32, + parameter int unsigned APB_DATA_WIDTH = 32 +)( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + AXI_BUS.Slave axi_slave, + APB_BUS.Master apb_master +); + + // ---------------- + // AXI2APB WRAPER + // ---------------- + generate if (AXI_DATA_WIDTH == APB_DATA_WIDTH) begin + axi2apb #( + .AXI4_ADDRESS_WIDTH ( AXI_ADDR_WIDTH ), + .AXI4_RDATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI4_WDATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI4_ID_WIDTH ( AXI_ID_WIDTH ), + .AXI4_USER_WIDTH ( AXI_USER_WIDTH ), + + .BUFF_DEPTH_SLAVE ( 2 ), + .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ) + ) axi2apb_i ( + .ACLK ( clk_i ), + .ARESETn ( rst_ni ), + .test_en_i ( test_en_i ), + + .AWID_i ( axi_slave.aw_id ), + .AWADDR_i ( axi_slave.aw_addr ), + .AWLEN_i ( axi_slave.aw_len ), + .AWSIZE_i ( axi_slave.aw_size ), + .AWBURST_i ( axi_slave.aw_burst ), + .AWLOCK_i ( axi_slave.aw_lock ), + .AWCACHE_i ( axi_slave.aw_cache ), + .AWPROT_i ( axi_slave.aw_prot ), + .AWREGION_i ( axi_slave.aw_region ), + .AWATOP_i ( axi_slave.aw_atop ), + .AWUSER_i ( axi_slave.aw_user ), + .AWQOS_i ( axi_slave.aw_qos ), + .AWVALID_i ( axi_slave.aw_valid ), + .AWREADY_o ( axi_slave.aw_ready ), + + .WDATA_i ( axi_slave.w_data ), + .WSTRB_i ( axi_slave.w_strb ), + .WLAST_i ( axi_slave.w_last ), + .WUSER_i ( axi_slave.w_user ), + .WVALID_i ( axi_slave.w_valid ), + .WREADY_o ( axi_slave.w_ready ), + + .BID_o ( axi_slave.b_id ), + .BRESP_o ( axi_slave.b_resp ), + .BVALID_o ( axi_slave.b_valid ), + .BUSER_o ( axi_slave.b_user ), + .BREADY_i ( axi_slave.b_ready ), + + .ARID_i ( axi_slave.ar_id ), + .ARADDR_i ( axi_slave.ar_addr ), + .ARLEN_i ( axi_slave.ar_len ), + .ARSIZE_i ( axi_slave.ar_size ), + .ARBURST_i ( axi_slave.ar_burst ), + .ARLOCK_i ( axi_slave.ar_lock ), + .ARCACHE_i ( axi_slave.ar_cache ), + .ARPROT_i ( axi_slave.ar_prot ), + .ARREGION_i ( axi_slave.ar_region ), + .ARUSER_i ( axi_slave.ar_user ), + .ARQOS_i ( axi_slave.ar_qos ), + .ARVALID_i ( axi_slave.ar_valid ), + .ARREADY_o ( axi_slave.ar_ready ), + + .RID_o ( axi_slave.r_id ), + .RDATA_o ( axi_slave.r_data ), + .RRESP_o ( axi_slave.r_resp ), + .RLAST_o ( axi_slave.r_last ), + .RUSER_o ( axi_slave.r_user ), + .RVALID_o ( axi_slave.r_valid ), + .RREADY_i ( axi_slave.r_ready ), + + .PENABLE ( apb_master.penable ), + .PWRITE ( apb_master.pwrite ), + .PADDR ( apb_master.paddr ), + .PSEL ( apb_master.psel ), + .PWDATA ( apb_master.pwdata ), + .PRDATA ( apb_master.prdata ), + .PREADY ( apb_master.pready ), + .PSLVERR ( apb_master.pslverr ) + ); + end else if (AXI_DATA_WIDTH == 64 && APB_DATA_WIDTH == 32) begin + axi2apb_64_32 #( + .AXI4_ADDRESS_WIDTH ( AXI_ADDR_WIDTH ), + .AXI4_RDATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI4_WDATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI4_ID_WIDTH ( AXI_ID_WIDTH ), + .AXI4_USER_WIDTH ( AXI_USER_WIDTH ), + + .BUFF_DEPTH_SLAVE ( 2 ), + .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ) + ) axi2apb_i ( + .ACLK ( clk_i ), + .ARESETn ( rst_ni ), + .test_en_i ( test_en_i ), + + .AWID_i ( axi_slave.aw_id ), + .AWADDR_i ( axi_slave.aw_addr ), + .AWLEN_i ( axi_slave.aw_len ), + .AWSIZE_i ( axi_slave.aw_size ), + .AWBURST_i ( axi_slave.aw_burst ), + .AWLOCK_i ( axi_slave.aw_lock ), + .AWCACHE_i ( axi_slave.aw_cache ), + .AWPROT_i ( axi_slave.aw_prot ), + .AWREGION_i ( axi_slave.aw_region ), + .AWATOP_i ( axi_slave.aw_atop ), + .AWUSER_i ( axi_slave.aw_user ), + .AWQOS_i ( axi_slave.aw_qos ), + .AWVALID_i ( axi_slave.aw_valid ), + .AWREADY_o ( axi_slave.aw_ready ), + + .WDATA_i ( axi_slave.w_data ), + .WSTRB_i ( axi_slave.w_strb ), + .WLAST_i ( axi_slave.w_last ), + .WUSER_i ( axi_slave.w_user ), + .WVALID_i ( axi_slave.w_valid ), + .WREADY_o ( axi_slave.w_ready ), + + .BID_o ( axi_slave.b_id ), + .BRESP_o ( axi_slave.b_resp ), + .BVALID_o ( axi_slave.b_valid ), + .BUSER_o ( axi_slave.b_user ), + .BREADY_i ( axi_slave.b_ready ), + + .ARID_i ( axi_slave.ar_id ), + .ARADDR_i ( axi_slave.ar_addr ), + .ARLEN_i ( axi_slave.ar_len ), + .ARSIZE_i ( axi_slave.ar_size ), + .ARBURST_i ( axi_slave.ar_burst ), + .ARLOCK_i ( axi_slave.ar_lock ), + .ARCACHE_i ( axi_slave.ar_cache ), + .ARPROT_i ( axi_slave.ar_prot ), + .ARREGION_i ( axi_slave.ar_region ), + .ARUSER_i ( axi_slave.ar_user ), + .ARQOS_i ( axi_slave.ar_qos ), + .ARVALID_i ( axi_slave.ar_valid ), + .ARREADY_o ( axi_slave.ar_ready ), + + .RID_o ( axi_slave.r_id ), + .RDATA_o ( axi_slave.r_data ), + .RRESP_o ( axi_slave.r_resp ), + .RLAST_o ( axi_slave.r_last ), + .RUSER_o ( axi_slave.r_user ), + .RVALID_o ( axi_slave.r_valid ), + .RREADY_i ( axi_slave.r_ready ), + + .PENABLE ( apb_master.penable ), + .PWRITE ( apb_master.pwrite ), + .PADDR ( apb_master.paddr ), + .PSEL ( apb_master.psel ), + .PWDATA ( apb_master.pwdata ), + .PRDATA ( apb_master.prdata ), + .PREADY ( apb_master.pready ), + .PSLVERR ( apb_master.pslverr ) + ); + end + endgenerate +endmodule diff --git a/hw/deps/axi2mem/src/axi_to_mem.sv b/hw/deps/axi2mem/src/axi_to_mem.sv new file mode 100644 index 0000000..bc93220 --- /dev/null +++ b/hw/deps/axi2mem/src/axi_to_mem.sv @@ -0,0 +1,782 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Andreas Kurth + +module axi_to_mem #( + parameter type axi_req_t = logic, // AXI request type + parameter type axi_resp_t = logic, // AXI response type + parameter int unsigned AddrWidth = 0, // address width + parameter int unsigned DataWidth = 0, // AXI data width + parameter int unsigned IdWidth = 0, // AXI ID width + parameter int unsigned NumBanks = 0, // number of banks at output + parameter int unsigned BufDepth = 1, // depth of memory response buffer + // Dependent parameters, do not override. + localparam type addr_t = logic [AddrWidth-1:0], + localparam type mem_atop_t = logic [5:0], + localparam type mem_data_t = logic [DataWidth/NumBanks-1:0], + localparam type mem_strb_t = logic [DataWidth/NumBanks/8-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + output logic busy_o, + + input axi_req_t axi_req_i, + output axi_resp_t axi_resp_o, + + output logic [NumBanks-1:0] mem_req_o, + input logic [NumBanks-1:0] mem_gnt_i, + output addr_t [NumBanks-1:0] mem_addr_o, // byte address + output mem_data_t [NumBanks-1:0] mem_wdata_o, // write data + output mem_strb_t [NumBanks-1:0] mem_strb_o, // byte-wise strobe + output mem_atop_t [NumBanks-1:0] mem_atop_o, // atomic operation + output logic [NumBanks-1:0] mem_we_o, // write enable + input logic [NumBanks-1:0] mem_rvalid_i, // response valid + input mem_data_t [NumBanks-1:0] mem_rdata_i // read data +); + + typedef logic [DataWidth-1:0] axi_data_t; + typedef logic [DataWidth/8-1:0] axi_strb_t; + typedef logic [IdWidth-1:0] axi_id_t; + + typedef struct packed { + addr_t addr; + mem_atop_t atop; + axi_strb_t strb; + axi_data_t wdata; + logic we; + } mem_req_t; + + typedef struct packed { + addr_t addr; + axi_pkg::len_t len; + axi_pkg::atop_t atop; + axi_id_t id; + logic last; + axi_pkg::qos_t qos; + axi_pkg::size_t size; + logic write; + } meta_t; + + axi_data_t mem_rdata, + m2s_resp; + axi_pkg::len_t r_cnt_d, r_cnt_q, + w_cnt_d, w_cnt_q; + logic arb_valid, arb_ready, + rd_valid, rd_ready, + rd_buf_valid, rd_buf_ready, + wr_valid, wr_ready, + rd_mux_valid, rd_mux_ready, + rd_prio_demux, + rd_prio_inp_valid, rd_prio_inp_ready, + rd_regu_inp_valid, rd_regu_inp_ready, + rd_prio_mux, + rd_prio_valid, rd_prio_ready, + rd_regu_valid, rd_regu_ready, + sel_b, sel_buf_b, + sel_r, sel_buf_r, + sel_valid, sel_ready, + sel_buf_valid, sel_buf_ready, + sel_lock_d, sel_lock_q, + meta_valid, meta_ready, + meta_buf_valid, meta_buf_ready, + meta_sel_d, meta_sel_q, + m2s_req_valid, m2s_req_ready, + m2s_resp_valid, m2s_resp_ready, + mem_req_valid, mem_req_ready, + mem_rvalid; + mem_req_t m2s_req, + mem_req; + meta_t rd_meta, + rd_meta_d, rd_meta_q, + rd_buf_meta, + rd_mux_meta, + rd_prio_meta, + rd_regu_meta, + wr_meta, + wr_meta_d, wr_meta_q, + meta, meta_buf; + + assign busy_o = axi_req_i.aw_valid | axi_req_i.ar_valid | axi_req_i.w_valid | + axi_resp_o.b_valid | axi_resp_o.r_valid | + (r_cnt_q > 0) | (w_cnt_q > 0); + + // This is not ready for upstreaming; for that, we would have to compare the incoming ID against + // all IDs in both queues to ensure ordering. + stream_demux #( + .N_OUP (2) + ) i_rd_prio_demux ( + .inp_valid_i (axi_req_i.ar_valid), + .inp_ready_o (axi_resp_o.ar_ready), + .oup_sel_i (rd_prio_demux), + .oup_valid_o ({rd_prio_inp_valid, rd_regu_inp_valid}), + .oup_ready_i ({rd_prio_inp_ready, rd_regu_inp_ready}) + ); + assign rd_prio_demux = axi_req_i.ar_valid & axi_req_i.ar.len == '0 & axi_req_i.ar.qos != '0; + stream_fifo #( + .FALL_THROUGH (1'b1), + .DEPTH (16), + .T (meta_t) + ) i_rd_regu_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .data_i ('{ + addr: axi_req_i.ar.addr, + len: axi_req_i.ar.len, + atop: '0, + id: axi_req_i.ar.id, + last: (axi_req_i.ar.len == '0), + qos: axi_req_i.ar.qos, + size: axi_req_i.ar.size, + write: 1'b0 + }), + .valid_i (rd_regu_inp_valid), + .ready_o (rd_regu_inp_ready), + .data_o (rd_regu_meta), + .valid_o (rd_regu_valid), + .ready_i (rd_regu_ready), + .usage_o (/* unused */) + ); + stream_fifo #( + .FALL_THROUGH (1'b1), + .DEPTH (4), + .T (meta_t) + ) i_rd_prio_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .data_i ('{ + addr: axi_req_i.ar.addr, + len: axi_req_i.ar.len, + atop: '0, + id: axi_req_i.ar.id, + last: (axi_req_i.ar.len == '0), + qos: axi_req_i.ar.qos, + size: axi_req_i.ar.size, + write: 1'b0 + }), + .valid_i (rd_prio_inp_valid), + .ready_o (rd_prio_inp_ready), + .data_o (rd_prio_meta), + .valid_o (rd_prio_valid), + .ready_i (rd_prio_ready), + .usage_o (/* unused */) + ); + stream_mux #( + .DATA_T (meta_t), + .N_INP (2) + ) i_rd_prio_mux ( + .inp_data_i ({rd_prio_meta, rd_regu_meta}), + .inp_valid_i ({rd_prio_valid, rd_regu_valid}), + .inp_ready_o ({rd_prio_ready, rd_regu_ready}), + .inp_sel_i (rd_prio_mux), + .oup_data_o (rd_mux_meta), + .oup_valid_o (rd_mux_valid), + .oup_ready_i (rd_mux_ready) + ); + assign rd_prio_mux = rd_prio_valid; + + // Handle reads. + always_comb begin + // Default assignments + rd_mux_ready = 1'b0; + rd_meta_d = rd_meta_q; + r_cnt_d = r_cnt_q; + rd_meta = '{ default: 'x }; + rd_valid = 1'b0; + // Prioritize single-beat read with QoS > 0 over in-progress bursts. + if (rd_mux_valid && rd_mux_meta.len == '0 && rd_mux_meta.qos != '0 && + // Additionally, we may only handle this request if we are not currently handling a burst + // with the same ID. + (r_cnt_q == '0 || rd_meta_q.id != rd_mux_meta.id)) begin + rd_meta = rd_mux_meta; + rd_valid = 1'b1; + rd_mux_ready = rd_ready; + // Handle R burst in progress. + end else if (r_cnt_q > '0) begin + rd_meta_d.last = (r_cnt_q == 8'd1); + rd_meta = rd_meta_d; + rd_meta.addr = rd_meta_q.addr + axi_pkg::num_bytes(rd_meta_q.size); + rd_valid = 1'b1; + if (rd_ready) begin + r_cnt_d--; + rd_meta_d.addr = rd_meta.addr; + end + // Handle new AR if there is one. + end else if (rd_mux_valid) begin + rd_meta_d = rd_mux_meta; + rd_meta_d.addr = axi_pkg::aligned_addr(rd_mux_meta.addr, rd_mux_meta.size); + rd_meta = rd_meta_d; + rd_meta.addr = rd_mux_meta.addr; + rd_valid = 1'b1; + if (rd_ready) begin + r_cnt_d = rd_mux_meta.len; + rd_mux_ready = 1'b1; + end + end + end + + // FT register required to absorb changes to `rd_meta` while `rd_valid` but not yet `rd_ready`. + fall_through_register #( + .T (meta_t) + ) i_rd_ft_reg ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .testmode_i (1'b0), + .valid_i (rd_valid), + .ready_o (rd_ready), + .data_i (rd_meta), + .valid_o (rd_buf_valid), + .ready_i (rd_buf_ready), + .data_o (rd_buf_meta) + ); + + // Handle writes. + always_comb begin + // Default assignments + axi_resp_o.aw_ready = 1'b0; + axi_resp_o.w_ready = 1'b0; + wr_meta_d = wr_meta_q; + wr_meta = 'x; + wr_valid = 1'b0; + w_cnt_d = w_cnt_q; + // Handle W bursts in progress. + if (w_cnt_q > '0) begin + wr_meta_d.last = (w_cnt_q == 8'd1); + wr_meta = wr_meta_d; + wr_meta.addr = wr_meta_q.addr + axi_pkg::num_bytes(wr_meta_q.size); + if (axi_req_i.w_valid) begin + wr_valid = 1'b1; + if (wr_ready) begin + axi_resp_o.w_ready = 1'b1; + w_cnt_d--; + wr_meta_d.addr = wr_meta.addr; + end + end + // Handle new AW if there is one. + end else if (axi_req_i.aw_valid && axi_req_i.w_valid) begin + wr_meta_d = '{ + addr: axi_pkg::aligned_addr(axi_req_i.aw.addr, axi_req_i.aw.size), + len: axi_req_i.aw.len, + atop: axi_req_i.aw.atop, + id: axi_req_i.aw.id, + last: (axi_req_i.aw.len == '0), + qos: axi_req_i.aw.qos, + size: axi_req_i.aw.size, + write: 1'b1 + }; + wr_meta = wr_meta_d; + wr_meta.addr = axi_req_i.aw.addr; + wr_valid = 1'b1; + if (wr_ready) begin + w_cnt_d = axi_req_i.aw.len; + axi_resp_o.aw_ready = 1'b1; + axi_resp_o.w_ready = 1'b1; + end + end + end + + // Arbitrate between reads and writes. + + /* verilator lint_off UNOPTFLAT */ + logic [1:0] ax_mux_inp_ready; + /* verilator lint_on UNOPTFLAT */ + + assign rd_buf_ready = ax_mux_inp_ready[0]; + assign wr_ready = ax_mux_inp_ready[1]; + + stream_mux #( + .DATA_T (meta_t), + .N_INP (2) + ) i_ax_mux ( + .inp_data_i ({wr_meta, rd_buf_meta}), + .inp_valid_i ({wr_valid, rd_buf_valid}), + .inp_ready_o (ax_mux_inp_ready), + .inp_sel_i (meta_sel_d), + .oup_data_o (meta), + .oup_valid_o (arb_valid), + .oup_ready_i (arb_ready) + ); + always_comb begin + meta_sel_d = meta_sel_q; + sel_lock_d = sel_lock_q; + if (sel_lock_q) begin + meta_sel_d = meta_sel_q; + if (arb_valid && arb_ready) begin + sel_lock_d = 1'b0; + end + end else begin + if (wr_valid ^ rd_buf_valid) begin + // If either write or read is valid but not both, select the valid one. + meta_sel_d = wr_valid; + end else if (wr_valid && rd_buf_valid) begin + // If both write and read are valid, decide according to QoS then burst properties. + // Priorize higher QoS. + if (wr_meta.qos > rd_buf_meta.qos) begin + meta_sel_d = 1'b1; + end else if (rd_buf_meta.qos > wr_meta.qos) begin + meta_sel_d = 1'b0; + // Decide requests with identical QoS. + end else if (wr_meta.qos == rd_buf_meta.qos) begin + // 1. Priorize individual writes over read bursts. + // Rationale: Read bursts can be interleaved on AXI but write bursts cannot. However, + // progress of read bursts must still be guaranteed, so this condition only applies if the + // last beat granted was a read. + if (wr_meta.last && !rd_buf_meta.last && !meta_sel_q) begin + meta_sel_d = 1'b1; + // 2. Prioritize ongoing burst. + // Rationale: Stalled bursts create backpressure or require costly buffers. + end else if (w_cnt_q > '0) begin + meta_sel_d = 1'b1; + end else if (r_cnt_q > '0) begin + meta_sel_d = 1'b0; + // 3. Otherwise arbitrate round robin to prevent starvation. + end else begin + meta_sel_d = ~meta_sel_q; + end + end + end + // Lock arbitration if valid but not yet ready. + if (arb_valid && !arb_ready) begin + sel_lock_d = 1'b1; + end + end + end + + // Fork arbitrated stream to meta data, memory requests, and R/B channel selection. + stream_fork #( + .N_OUP (3) + ) i_fork ( + .clk_i, + .rst_ni, + .valid_i (arb_valid), + .ready_o (arb_ready), + .valid_o ({sel_valid, meta_valid, m2s_req_valid}), + .ready_i ({sel_ready, meta_ready, m2s_req_ready}) + ); + + assign sel_b = meta.write & meta.last; + assign sel_r = ~meta.write | meta.atop[5]; + + stream_fifo #( + .FALL_THROUGH (1'b0), + .DEPTH (1 + BufDepth), + .T (logic[1:0]) + ) i_sel_buf ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .data_i ({sel_b, sel_r}), + .valid_i (sel_valid), + .ready_o (sel_ready), + .data_o ({sel_buf_b, sel_buf_r}), + .valid_o (sel_buf_valid), + .ready_i (sel_buf_ready), + .usage_o (/* unused */) + ); + + stream_fifo #( + .FALL_THROUGH (1'b0), + .DEPTH (1 + BufDepth), + .T (meta_t) + ) i_meta_buf ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .data_i (meta), + .valid_i (meta_valid), + .ready_o (meta_ready), + .data_o (meta_buf), + .valid_o (meta_buf_valid), + .ready_i (meta_buf_ready), + .usage_o (/* unused */) + ); + + // Map AXI ATOPs to RI5CY AMOs. + always_comb begin + m2s_req.atop = '0; + m2s_req.wdata = axi_req_i.w.data; + if (arb_valid && meta.atop[5:4] != axi_pkg::ATOP_NONE) begin + m2s_req.atop[5] = 1'b1; + if (meta.atop == axi_pkg::ATOP_ATOMICSWAP) begin + m2s_req.atop[4:0] = riscv_defines::AMO_SWAP; + end else begin + case (meta.atop[2:0]) + axi_pkg::ATOP_ADD: m2s_req.atop[4:0] = riscv_defines::AMO_ADD; + axi_pkg::ATOP_CLR: begin + m2s_req.atop[4:0] = riscv_defines::AMO_AND; + m2s_req.wdata = ~axi_req_i.w.data; + end + axi_pkg::ATOP_EOR: m2s_req.atop[4:0] = riscv_defines::AMO_XOR; + axi_pkg::ATOP_SET: m2s_req.atop[4:0] = riscv_defines::AMO_OR; + axi_pkg::ATOP_SMAX: m2s_req.atop[4:0] = riscv_defines::AMO_MAX; + axi_pkg::ATOP_SMIN: m2s_req.atop[4:0] = riscv_defines::AMO_MIN; + axi_pkg::ATOP_UMAX: m2s_req.atop[4:0] = riscv_defines::AMO_MAXU; + axi_pkg::ATOP_UMIN: m2s_req.atop[4:0] = riscv_defines::AMO_MINU; + endcase + end + end + end + assign m2s_req.addr = meta.addr; + assign m2s_req.strb = axi_req_i.w.strb; + assign m2s_req.we = meta.write; + + // Interface memory as stream. + stream_to_mem #( + .mem_req_t (mem_req_t), + .mem_resp_t (axi_data_t), + .BufDepth (BufDepth) + ) i_stream_to_mem ( + .clk_i, + .rst_ni, + .req_i (m2s_req), + .req_valid_i (m2s_req_valid), + .req_ready_o (m2s_req_ready), + .resp_o (m2s_resp), + .resp_valid_o (m2s_resp_valid), + .resp_ready_i (m2s_resp_ready), + .mem_req_o (mem_req), + .mem_req_valid_o (mem_req_valid), + .mem_req_ready_i (mem_req_ready), + .mem_resp_i (mem_rdata), + .mem_resp_valid_i (mem_rvalid) + ); + + // Split single memory request to desired number of banks. + mem_to_banks #( + .AddrWidth (AddrWidth), + .DataWidth (DataWidth), + .NumBanks (NumBanks) + ) i_mem_to_banks ( + .clk_i, + .rst_ni, + .req_i (mem_req_valid), + .gnt_o (mem_req_ready), + .addr_i (mem_req.addr), + .wdata_i (mem_req.wdata), + .strb_i (mem_req.strb), + .atop_i (mem_req.atop), + .we_i (mem_req.we), + .rvalid_o (mem_rvalid), + .rdata_o (mem_rdata), + .bank_req_o (mem_req_o), + .bank_gnt_i (mem_gnt_i), + .bank_addr_o (mem_addr_o), + .bank_wdata_o (mem_wdata_o), + .bank_strb_o (mem_strb_o), + .bank_atop_o (mem_atop_o), + .bank_we_o (mem_we_o), + .bank_rvalid_i (mem_rvalid_i), + .bank_rdata_i (mem_rdata_i) + ); + + // Join memory read data and meta data stream. + logic mem_join_valid, mem_join_ready; + stream_join #( + .N_INP (2) + ) i_join ( + .inp_valid_i ({m2s_resp_valid, meta_buf_valid}), + .inp_ready_o ({m2s_resp_ready, meta_buf_ready}), + .oup_valid_o (mem_join_valid), + .oup_ready_i (mem_join_ready) + ); + + // Dynamically fork the joined stream to B and R channels. + stream_fork_dynamic #( + .N_OUP (2) + ) i_fork_dynamic ( + .clk_i, + .rst_ni, + .valid_i (mem_join_valid), + .ready_o (mem_join_ready), + .sel_i ({sel_buf_b, sel_buf_r}), + .sel_valid_i (sel_buf_valid), + .sel_ready_o (sel_buf_ready), + .valid_o ({axi_resp_o.b_valid, axi_resp_o.r_valid}), + .ready_i ({axi_req_i.b_ready, axi_req_i.r_ready}) + ); + + // Compose B responses. + assign axi_resp_o.b = '{ + id: meta_buf.id, + resp: axi_pkg::RESP_OKAY, + user: '0 + }; + + // Compose R responses. + assign axi_resp_o.r = '{ + data: m2s_resp, + id: meta_buf.id, + last: meta_buf.last, + resp: axi_pkg::RESP_OKAY, + user: '0 + }; + + // Registers + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + meta_sel_q <= 1'b0; + sel_lock_q <= 1'b0; + rd_meta_q <= '{default: '0}; + wr_meta_q <= '{default: '0}; + r_cnt_q <= '0; + w_cnt_q <= '0; + end else begin + meta_sel_q <= meta_sel_d; + sel_lock_q <= sel_lock_d; + rd_meta_q <= rd_meta_d; + wr_meta_q <= wr_meta_d; + r_cnt_q <= r_cnt_d; + w_cnt_q <= w_cnt_d; + end + end + + // Assertions + `ifndef VERILATOR + `ifndef TARGET_SYNTHESIS + default disable iff (!rst_ni); + assume property (@(posedge clk_i) + axi_req_i.ar_valid && !axi_resp_o.ar_ready |=> $stable(axi_req_i.ar)) + else $error("AR must remain stable until handshake has happened!"); + assert property (@(posedge clk_i) + axi_resp_o.r_valid && !axi_req_i.r_ready |=> $stable(axi_resp_o.r)) + else $error("R must remain stable until handshake has happened!"); + assume property (@(posedge clk_i) + axi_req_i.aw_valid && !axi_resp_o.aw_ready |=> $stable(axi_req_i.aw)) + else $error("AW must remain stable until handshake has happened!"); + assume property (@(posedge clk_i) + axi_req_i.w_valid && !axi_resp_o.w_ready |=> $stable(axi_req_i.w)) + else $error("W must remain stable until handshake has happened!"); + assert property (@(posedge clk_i) + axi_resp_o.b_valid && !axi_req_i.b_ready |=> $stable(axi_resp_o.b)) + else $error("B must remain stable until handshake has happened!"); + assert property (@(posedge clk_i) axi_req_i.ar_valid && axi_req_i.ar.len > 0 |-> + axi_req_i.ar.burst == axi_pkg::BURST_INCR) + else $error("Non-incrementing bursts are not supported!"); + assert property (@(posedge clk_i) axi_req_i.aw_valid && axi_req_i.aw.len > 0 |-> + axi_req_i.aw.burst == axi_pkg::BURST_INCR) + else $error("Non-incrementing bursts are not supported!"); + assert property (@(posedge clk_i) meta_valid && meta.atop != '0 |-> meta.write) + else $warning("Unexpected atomic operation on read."); + `endif + `endif + +endmodule + + +`include "axi/assign.svh" +`include "axi/typedef.svh" +// Interface wrapper for axi_to_mem +module axi_to_mem_intf #( + parameter int unsigned AddrWidth = 0, + parameter int unsigned DataWidth = 0, + parameter int unsigned IdWidth = 0, + parameter int unsigned UserWidth = 0, + parameter int unsigned NumBanks = 0, + parameter int unsigned BufDepth = 1, // depth of memory response buffer + // Dependent parameters, do not override. + localparam type addr_t = logic [AddrWidth-1:0], + localparam type mem_atop_t = logic [5:0], + localparam type mem_data_t = logic [DataWidth/NumBanks-1:0], + localparam type mem_strb_t = logic [DataWidth/NumBanks/8-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + output logic busy_o, + + AXI_BUS.Slave slv, + + output logic [NumBanks-1:0] mem_req_o, + input logic [NumBanks-1:0] mem_gnt_i, + output addr_t [NumBanks-1:0] mem_addr_o, // byte address + output mem_data_t [NumBanks-1:0] mem_wdata_o, // write data + output mem_strb_t [NumBanks-1:0] mem_strb_o, // byte-wise strobe + output mem_atop_t [NumBanks-1:0] mem_atop_o, // atomic operation + output logic [NumBanks-1:0] mem_we_o, // write enable + input logic [NumBanks-1:0] mem_rvalid_i, // response valid + input mem_data_t [NumBanks-1:0] mem_rdata_i // read data +); + typedef logic [IdWidth-1:0] id_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [DataWidth/8-1:0] strb_t; + typedef logic [UserWidth-1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + req_t req; + resp_t resp; + `AXI_ASSIGN_TO_REQ(req, slv) + `AXI_ASSIGN_FROM_RESP(slv, resp) + axi_to_mem #( + .axi_req_t (req_t), + .axi_resp_t (resp_t), + .AddrWidth (AddrWidth), + .DataWidth (DataWidth), + .IdWidth (IdWidth), + .NumBanks (NumBanks), + .BufDepth (BufDepth) + ) i_axi_to_mem ( + .clk_i, + .rst_ni, + .busy_o, + .axi_req_i (req), + .axi_resp_o (resp), + .mem_req_o, + .mem_gnt_i, + .mem_addr_o, + .mem_wdata_o, + .mem_strb_o, + .mem_atop_o, + .mem_we_o, + .mem_rvalid_i, + .mem_rdata_i + ); +endmodule + + +// Split memory access over multiple parallel banks, where each bank has its own req/gnt request and +// valid response direction. +module mem_to_banks #( + parameter int unsigned AddrWidth = 0, // input address width + parameter int unsigned DataWidth = 0, // input data width, must be a power of two + parameter int unsigned NumBanks = 0, // number of banks at output, must evenly divide the data + // width + // Dependent parameters, do not override. + localparam type addr_t = logic [AddrWidth-1:0], + localparam type atop_t = logic [5:0], + localparam type inp_data_t = logic [DataWidth-1:0], + localparam type inp_strb_t = logic [DataWidth/8-1:0], + localparam type oup_data_t = logic [DataWidth/NumBanks-1:0], + localparam type oup_strb_t = logic [DataWidth/NumBanks/8-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + input logic req_i, + output logic gnt_o, + input addr_t addr_i, + input inp_data_t wdata_i, + input inp_strb_t strb_i, + input atop_t atop_i, + input logic we_i, + output logic rvalid_o, + output inp_data_t rdata_o, + + output logic [NumBanks-1:0] bank_req_o, + input logic [NumBanks-1:0] bank_gnt_i, + output addr_t [NumBanks-1:0] bank_addr_o, + output oup_data_t [NumBanks-1:0] bank_wdata_o, + output oup_strb_t [NumBanks-1:0] bank_strb_o, + output atop_t [NumBanks-1:0] bank_atop_o, + output logic [NumBanks-1:0] bank_we_o, + input logic [NumBanks-1:0] bank_rvalid_i, + input oup_data_t [NumBanks-1:0] bank_rdata_i +); + + localparam DataBytes = $bits(inp_strb_t); + localparam BitsPerBank = $bits(oup_data_t); + localparam BytesPerBank = $bits(oup_strb_t); + + typedef struct packed { + addr_t addr; + oup_data_t wdata; + oup_strb_t strb; + atop_t atop; + logic we; + } req_t; + + logic req_valid; + logic [NumBanks-1:0] req_ready, + resp_valid, resp_ready; + req_t [NumBanks-1:0] bank_req, + bank_oup; + + function automatic addr_t align_addr(input addr_t addr); + return (addr >> $clog2(DataBytes)) << $clog2(DataBytes); + endfunction + + // Handle requests. + assign req_valid = req_i & gnt_o; + for (genvar i = 0; i < NumBanks; i++) begin : gen_reqs + assign bank_req[i].addr = align_addr(addr_i) + i * BytesPerBank; + assign bank_req[i].wdata = wdata_i[i*BitsPerBank+:BitsPerBank]; + assign bank_req[i].strb = strb_i[i*BytesPerBank+:BytesPerBank]; + assign bank_req[i].atop = atop_i; + assign bank_req[i].we = we_i; + fall_through_register #( + .T (req_t) + ) i_ft_reg ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .testmode_i (1'b0), + .valid_i (req_valid), + .ready_o (req_ready[i]), + .data_i (bank_req[i]), + .valid_o (bank_req_o[i]), + .ready_i (bank_gnt_i[i]), + .data_o (bank_oup[i]) + ); + assign bank_addr_o[i] = bank_oup[i].addr; + assign bank_wdata_o[i] = bank_oup[i].wdata; + assign bank_strb_o[i] = bank_oup[i].strb; + assign bank_atop_o[i] = bank_oup[i].atop; + assign bank_we_o[i] = bank_oup[i].we; + end + + // Grant output if all our requests have been granted. + assign gnt_o = (&req_ready) & (&resp_ready); + + // Handle responses. + for (genvar i = 0; i < NumBanks; i++) begin : gen_resp_regs + fall_through_register #( + .T (oup_data_t) + ) i_ft_reg ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .testmode_i (1'b0), + .valid_i (bank_rvalid_i[i]), + .ready_o (resp_ready[i]), + .data_i (bank_rdata_i[i]), + .data_o (rdata_o[i*BitsPerBank+:BitsPerBank]), + .ready_i (rvalid_o), + .valid_o (resp_valid[i]) + ); + end + assign rvalid_o = &resp_valid; + + // Assertions + `ifndef VERILATOR + `ifndef TARGET_SYNTHESIS + initial begin + assume (DataWidth != 0 && (DataWidth & (DataWidth - 1)) == 0) + else $fatal(1, "Data width must be a power of two!"); + assume (DataWidth % NumBanks == 0) + else $fatal(1, "Data width must be evenly divisible over banks!"); + assume ((DataWidth / NumBanks) % 8 == 0) + else $fatal(1, "Data width of each bank must be divisible into 8-bit bytes!"); + end + `endif + `endif + +endmodule diff --git a/hw/deps/axi2mem/src/axi_to_mem_banked_mp.sv b/hw/deps/axi2mem/src/axi_to_mem_banked_mp.sv new file mode 100644 index 0000000..573d9da --- /dev/null +++ b/hw/deps/axi2mem/src/axi_to_mem_banked_mp.sv @@ -0,0 +1,373 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Wolfgang Rönninger + +/// AXI4+ATOP to banked SRAM memory slave. Allows for parallel read and write transactions. Multi-port extension. +module axi_to_mem_banked_mp #( + /// AXI4+ATOP ID width + parameter int unsigned AxiIdWidth = 32'd0, + /// AXI4+ATOP address width + parameter int unsigned AxiAddrWidth = 32'd0, + /// AXI4+ATOP data width + parameter int unsigned AxiDataWidth = 32'd0, + /// AXI4+ATOP AW channel struct + parameter type axi_aw_chan_t = logic, + /// AXI4+ATOP W channel struct + parameter type axi_w_chan_t = logic, + /// AXI4+ATOP B channel struct + parameter type axi_b_chan_t = logic, + /// AXI4+ATOP AR channel struct + parameter type axi_ar_chan_t = logic, + /// AXI4+ATOP R channel struct + parameter type axi_r_chan_t = logic, + /// AXI4+ATOP request struct + parameter type axi_req_t = logic, + /// AXI4+ATOP response struct + parameter type axi_resp_t = logic, + // Number of slave ports + parameter int unsigned NumSlvPorts = 1, + /// Number of memory banks / macros + /// Has to satisfy: + /// - MemNumBanks >= 2 * AxiDataWidth / MemDataWidth + /// - MemNumBanks is a power of 2. + parameter int unsigned MemNumBanks = 32'd4, + /// Address width of an individual memory bank. + parameter int unsigned MemAddrWidth = 32'd11, + /// Data width of the memory macros. + /// Has to satisfy: + /// - AxiDataWidth % MemDataWidth = 0 + parameter int unsigned MemDataWidth = 32'd32, + /// Read latency of the connected memory in cycles + parameter int unsigned MemLatency = 32'd1, + /// TCDM topology can be: LIC, BFLY2, BFLY4, CLOS + parameter tcdm_interconnect_pkg::topo_e Topology = tcdm_interconnect_pkg::LIC, + /// DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter type mem_addr_t = logic [MemAddrWidth-1:0], + parameter type mem_atop_t = logic [5:0], + parameter type mem_data_t = logic [MemDataWidth-1:0], + parameter type mem_strb_t = logic [MemDataWidth/8-1:0] +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Testmode enable + input logic test_i, + /// AXI4+ATOP slave port, request struct + input axi_req_t [NumSlvPorts-1:0] axi_req_i, + /// AXI4+ATOP slave port, response struct + output axi_resp_t [NumSlvPorts-1:0] axi_resp_o, + /// Memory bank request + output logic [MemNumBanks-1:0] mem_req_o, + /// Memory request grant + input logic [MemNumBanks-1:0] mem_gnt_i, + /// Request address + output mem_addr_t [MemNumBanks-1:0] mem_add_o, + /// Write request enable, active high + output logic [MemNumBanks-1:0] mem_wen_o, + /// Write data + output mem_data_t [MemNumBanks-1:0] mem_wdata_o, + /// Write data byte enable, active high + output mem_strb_t [MemNumBanks-1:0] mem_be_o, + /// Atomic operation + output mem_atop_t [MemNumBanks-1:0] mem_atop_o, + /// Read data response + input mem_data_t [MemNumBanks-1:0] mem_rdata_i, + /// Status output, busy flag of `axi_to_mem` + output logic [NumSlvPorts-1:0][1:0] axi_to_mem_busy_o +); + localparam int unsigned BanksPerAxiChannel = AxiDataWidth / MemDataWidth; + // atop signal is piggybacked on tcdm_data + localparam int unsigned TcdmDataWidth = MemDataWidth + 6; + + // Typedef for defining the channels + typedef enum logic { + ReadAccess = 1'b0, + WriteAccess = 1'b1 + } access_type_e; + typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [TcdmDataWidth-1:0] tcdm_data_t; + + axi_req_t [NumSlvPorts-1:0][1:0] mem_axi_reqs; + axi_resp_t [NumSlvPorts-1:0][1:0] mem_axi_resps; + + for (genvar i=0; i= 1) else $fatal(1, "AxiIdWidth must be at least 1!"); + assert (AxiAddrWidth >= 1) else $fatal(1, "AxiAddrWidth must be at least 1!"); + assert (AxiDataWidth >= 1) else $fatal(1, "AxiDataWidth must be at least 1!"); + assert (MemNumBanks >= 2 * AxiDataWidth / MemDataWidth) else + $fatal(1, "MemNumBanks has to be >= 2 * AxiDataWidth / MemDataWidth"); + assert ($onehot(MemNumBanks)) else $fatal(1, "MemNumBanks has to be a power of 2."); + assert (MemAddrWidth >= 1) else $fatal(1, "MemAddrWidth must be at least 1!"); + assert (MemDataWidth >= 1) else $fatal(1, "MemDataWidth must be at least 1!"); + assert (AxiDataWidth % MemDataWidth == 0) else + $fatal(1, "MemDataWidth has to be a divisor of AxiDataWidth."); + end +`endif +// pragma translate_on +endmodule + +`include "axi/typedef.svh" +`include "axi/assign.svh" +/// AXI4+ATOP interface wrapper for `axi_to_mem` +module axi_to_mem_banked_2p_intf #( + /// AXI4+ATOP ID width + parameter int unsigned AXI_ID_WIDTH = 32'd0, + /// AXI4+ATOP address width + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + /// AXI4+ATOP data width + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + /// AXI4+ATOP user width + parameter int unsigned AXI_USER_WIDTH = 32'd0, + /// Number of memory banks / macros + /// Has to satisfy: + /// - MemNumBanks >= 2 * AxiDataWidth / MemDataWidth + /// - MemNumBanks is a power of 2. + parameter int unsigned MEM_NUM_BANKS = 32'd4, + /// Address width of an individual memory bank. + parameter int unsigned MEM_ADDR_WIDTH = 32'd11, + /// Data width of the memory macros. + /// Has to satisfy: + /// - AxiDataWidth % MemDataWidth = 0 + parameter int unsigned MEM_DATA_WIDTH = 32'd32, + /// Read latency of the connected memory in cycles + parameter int unsigned MEM_LATENCY = 32'd1, + /// TCDM topology can be: LIC, BFLY2, BFLY4, CLOS + parameter tcdm_interconnect_pkg::topo_e TOPOLOGY = tcdm_interconnect_pkg::LIC, + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter type mem_addr_t = logic [MEM_ADDR_WIDTH-1:0], + parameter type mem_atop_t = logic [5:0], + parameter type mem_data_t = logic [MEM_DATA_WIDTH-1:0], + parameter type mem_strb_t = logic [MEM_DATA_WIDTH/8-1:0] +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Testmode enable + input logic test_i, + /// AXI4+ATOP slave ports + // seems that array of interfaces are not supported? + AXI_BUS.Slave slv_a, + AXI_BUS.Slave slv_b, + /// Memory bank request + output logic [MEM_NUM_BANKS-1:0] mem_req_o, + /// Memory request grant + input logic [MEM_NUM_BANKS-1:0] mem_gnt_i, + /// Request address + output mem_addr_t [MEM_NUM_BANKS-1:0] mem_add_o, + /// Write request enable, active high + output logic [MEM_NUM_BANKS-1:0] mem_wen_o, + /// Write data + output mem_data_t [MEM_NUM_BANKS-1:0] mem_wdata_o, + /// Write data byte enable, active high + output mem_strb_t [MEM_NUM_BANKS-1:0] mem_be_o, + /// Atomic operation + output mem_atop_t [MEM_NUM_BANKS-1:0] mem_atop_o, + /// Read data response + input mem_data_t [MEM_NUM_BANKS-1:0] mem_rdata_i, + /// Status output, busy flag of `axi_to_mem` + output logic [1:0] axi_to_mem_busy_a_o, + output logic [1:0] axi_to_mem_busy_b_o +); + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + + axi_req_t [1:0] mem_axi_req; + axi_resp_t [1:0] mem_axi_resp; + + `AXI_ASSIGN_TO_REQ(mem_axi_req[0], slv_a) + `AXI_ASSIGN_FROM_RESP(slv_a, mem_axi_resp[0]) + + `AXI_ASSIGN_TO_REQ(mem_axi_req[1], slv_b) + `AXI_ASSIGN_FROM_RESP(slv_b, mem_axi_resp[1]) + + axi_to_mem_banked_mp #( + .AxiIdWidth ( AXI_ID_WIDTH ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .axi_aw_chan_t ( aw_chan_t ), + .axi_w_chan_t ( w_chan_t ), + .axi_b_chan_t ( b_chan_t ), + .axi_ar_chan_t ( ar_chan_t ), + .axi_r_chan_t ( r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .NumSlvPorts ( 2 ), + .MemNumBanks ( MEM_NUM_BANKS ), + .MemAddrWidth ( MEM_ADDR_WIDTH ), + .MemDataWidth ( MEM_DATA_WIDTH ), + .MemLatency ( MEM_LATENCY ), + .Topology ( tcdm_interconnect_pkg::LIC ) + ) i_axi_to_mem_banked ( + .clk_i, + .rst_ni, + .test_i, + .axi_to_mem_busy_o ( {axi_to_mem_busy_a_o, axi_to_mem_busy_b_o}), + .axi_req_i ( mem_axi_req ), + .axi_resp_o ( mem_axi_resp ), + .mem_req_o, + .mem_gnt_i, + .mem_add_o, + .mem_wdata_o, + .mem_be_o, + .mem_atop_o, + .mem_wen_o, + .mem_rdata_i + ); + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI address width must be at least 1!"); + assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI data width must be at least 1!"); + assert (AXI_ID_WIDTH >= 1) else $fatal(1, "AXI ID width must be at least 1!"); + assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!"); + end +`endif +// pragma translate_on +endmodule + diff --git a/hw/deps/axi2mem/src/axi_to_mem_interleaved.sv b/hw/deps/axi2mem/src/axi_to_mem_interleaved.sv new file mode 100644 index 0000000..9e87787 --- /dev/null +++ b/hw/deps/axi2mem/src/axi_to_mem_interleaved.sv @@ -0,0 +1,209 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module axi_to_mem_interleaved #( + parameter type axi_req_t = logic, // AXI request type + parameter type axi_resp_t = logic, // AXI response type + parameter int unsigned AddrWidth = 0, // address width + parameter int unsigned DataWidth = 0, // AXI data width + parameter int unsigned IdWidth = 0, // AXI ID width + parameter int unsigned NumBanks = 0, // number of banks at output + parameter int unsigned BufDepth = 1, // depth of memory response buffer + // Dependent parameters, do not override. + localparam type addr_t = logic [AddrWidth-1:0], + localparam type mem_atop_t = logic [5:0], + localparam type mem_data_t = logic [DataWidth/NumBanks-1:0], + localparam type mem_strb_t = logic [DataWidth/NumBanks/8-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + output logic busy_o, + + input axi_req_t axi_req_i, + output axi_resp_t axi_resp_o, + + output logic [NumBanks-1:0] mem_req_o, + input logic [NumBanks-1:0] mem_gnt_i, + output addr_t [NumBanks-1:0] mem_addr_o, // byte address + output mem_data_t [NumBanks-1:0] mem_wdata_o, // write data + output mem_strb_t [NumBanks-1:0] mem_strb_o, // byte-wise strobe + output mem_atop_t [NumBanks-1:0] mem_atop_o, // atomic operation + output logic [NumBanks-1:0] mem_we_o, // write enable + input logic [NumBanks-1:0] mem_rvalid_i, // response valid + input mem_data_t [NumBanks-1:0] mem_rdata_i // read data +); + + // internal signals + logic w_busy, r_busy; + logic arb_outcome, arb_outcome_head; + + // internal AXI buses + axi_req_t r_axi_req, w_axi_req; + axi_resp_t r_axi_resp, w_axi_resp; + + // internal TCDM buses + logic [NumBanks-1:0] r_mem_req, w_mem_req; + logic [NumBanks-1:0] r_mem_gnt, w_mem_gnt; + addr_t [NumBanks-1:0] r_mem_addr, w_mem_addr; + mem_data_t [NumBanks-1:0] r_mem_wdata, w_mem_wdata; + mem_strb_t [NumBanks-1:0] r_mem_strb, w_mem_strb; + mem_atop_t [NumBanks-1:0] r_mem_atop, w_mem_atop; + logic [NumBanks-1:0] r_mem_we, w_mem_we; + logic [NumBanks-1:0] r_mem_rvalid, w_mem_rvalid; + mem_data_t [NumBanks-1:0] r_mem_rdata, w_mem_rdata; + + // split AXI bus in read and write + always_comb begin : proc_axi_rw_split + axi_resp_o.r = r_axi_resp.r; + axi_resp_o.r_valid = r_axi_resp.r_valid; + axi_resp_o.ar_ready = r_axi_resp.ar_ready; + axi_resp_o.b = w_axi_resp.b; + axi_resp_o.b_valid = w_axi_resp.b_valid; + axi_resp_o.w_ready = w_axi_resp.w_ready; + axi_resp_o.aw_ready = w_axi_resp.aw_ready; + + w_axi_req = '0; + w_axi_req.aw = axi_req_i.aw; + w_axi_req.aw_valid = axi_req_i.aw_valid; + w_axi_req.w = axi_req_i.w; + w_axi_req.w_valid = axi_req_i.w_valid; + w_axi_req.b_ready = axi_req_i.b_ready; + + r_axi_req = '0; + r_axi_req.ar = axi_req_i.ar; + r_axi_req.ar_valid = axi_req_i.ar_valid; + r_axi_req.r_ready = axi_req_i.r_ready; + end + + axi_to_mem #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .AddrWidth ( AddrWidth ), + .DataWidth ( DataWidth ), + .IdWidth ( IdWidth ), + .NumBanks ( NumBanks ), + .BufDepth ( BufDepth ) + ) i_axi_to_mem_write ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .busy_o ( w_busy ), + .axi_req_i ( w_axi_req ), + .axi_resp_o ( w_axi_resp ), + .mem_req_o ( w_mem_req ), + .mem_gnt_i ( w_mem_gnt ), + .mem_addr_o ( w_mem_addr ), + .mem_wdata_o ( w_mem_wdata ), + .mem_strb_o ( w_mem_strb ), + .mem_atop_o ( w_mem_atop ), + .mem_we_o ( w_mem_we ), + .mem_rvalid_i ( w_mem_rvalid ), + .mem_rdata_i ( w_mem_rdata ) + ); + + axi_to_mem #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .AddrWidth ( AddrWidth ), + .DataWidth ( DataWidth ), + .IdWidth ( IdWidth ), + .NumBanks ( NumBanks ), + .BufDepth ( BufDepth ) + ) i_axi_to_mem_read ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .busy_o ( r_busy ), + .axi_req_i ( r_axi_req ), + .axi_resp_o ( r_axi_resp ), + .mem_req_o ( r_mem_req ), + .mem_gnt_i ( r_mem_gnt ), + .mem_addr_o ( r_mem_addr ), + .mem_wdata_o ( r_mem_wdata ), + .mem_strb_o ( r_mem_strb ), + .mem_atop_o ( r_mem_atop ), + .mem_we_o ( r_mem_we ), + .mem_rvalid_i ( r_mem_rvalid ), + .mem_rdata_i ( r_mem_rdata ) + ); + + // create a struct for the rr-arb-tree + typedef struct packed { + addr_t addr; + mem_data_t wdata; + mem_strb_t strb; + logic we; + mem_atop_t atop; + } mem_req_payload_t; + + mem_req_payload_t r_payload, w_payload, payload; + + // pack the mem + assign r_payload.addr = r_mem_addr; + assign r_payload.wdata = r_mem_wdata; + assign r_payload.strb = r_mem_strb; + assign r_payload.we = r_mem_we; + assign r_payload.atop = r_mem_atop; + + assign w_payload.addr = w_mem_addr; + assign w_payload.wdata = w_mem_wdata; + assign w_payload.strb = w_mem_strb; + assign w_payload.we = w_mem_we; + assign w_payload.atop = w_mem_atop; + + assign mem_addr_o = payload.addr; + assign mem_wdata_o = payload.wdata; + assign mem_strb_o = payload.strb; + assign mem_we_o = payload.we; + assign mem_atop_o = payload.atop; + + // route data back to both channels + assign w_mem_rdata = mem_rdata_i; + assign r_mem_rdata = mem_rdata_i; + + assign w_mem_rvalid = mem_rvalid_i & !arb_outcome_head; + assign r_mem_rvalid = mem_rvalid_i & arb_outcome_head; + + // fine-grain arbitration + rr_arb_tree #( + .NumIn ( 2 ), + .DataType ( mem_req_payload_t ) + ) i_rr_arb_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .rr_i ( '0 ), + .req_i ( { r_mem_req, w_mem_req } ), + .gnt_o ( { r_mem_gnt, w_mem_gnt } ), + .data_i ( { r_payload, w_payload } ), + .req_o ( mem_req_o ), + .gnt_i ( mem_gnt_i ), + .data_o ( payload ), + .idx_o ( arb_outcome ) + ); + + // back-routing store + fifo_v3 #( + .DATA_WIDTH ( 1 ), + .DEPTH ( BufDepth + 1 ) + ) i_fifo_v3_response_trgt_store ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( ), + .empty_o ( ), + .usage_o ( ), + .data_i ( arb_outcome ), + .push_i ( mem_req_o & mem_gnt_i ), + .data_o ( arb_outcome_head ), + .pop_i ( mem_rvalid_i ) + ); + +endmodule : axi_to_mem_interleaved diff --git a/hw/deps/axi2per/axi2per.sv b/hw/deps/axi2per/axi2per.sv new file mode 100644 index 0000000..a8d0656 --- /dev/null +++ b/hw/deps/axi2per/axi2per.sv @@ -0,0 +1,467 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi2per +#( + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3, + parameter BUFFER_DEPTH = 2, + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 +) +( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + input logic [5:0] cluster_id_i, + + // AXI4 SLAVE + //*************************************** + // WRITE ADDRESS CHANNEL + input logic axi_slave_aw_valid_i, + input logic [AXI_ADDR_WIDTH-1:0] axi_slave_aw_addr_i, + input logic [2:0] axi_slave_aw_prot_i, + input logic [3:0] axi_slave_aw_region_i, + input logic [7:0] axi_slave_aw_len_i, + input logic [2:0] axi_slave_aw_size_i, + input logic [1:0] axi_slave_aw_burst_i, + input logic axi_slave_aw_lock_i, + input logic [5:0] axi_slave_aw_atop_i, + input logic [3:0] axi_slave_aw_cache_i, + input logic [3:0] axi_slave_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] axi_slave_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_slave_aw_user_i, + output logic axi_slave_aw_ready_o, + + // READ ADDRESS CHANNEL + input logic axi_slave_ar_valid_i, + input logic [AXI_ADDR_WIDTH-1:0] axi_slave_ar_addr_i, + input logic [2:0] axi_slave_ar_prot_i, + input logic [3:0] axi_slave_ar_region_i, + input logic [7:0] axi_slave_ar_len_i, + input logic [2:0] axi_slave_ar_size_i, + input logic [1:0] axi_slave_ar_burst_i, + input logic axi_slave_ar_lock_i, + input logic [3:0] axi_slave_ar_cache_i, + input logic [3:0] axi_slave_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] axi_slave_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_slave_ar_user_i, + output logic axi_slave_ar_ready_o, + + // WRITE DATA CHANNEL + input logic axi_slave_w_valid_i, + input logic [AXI_DATA_WIDTH-1:0] axi_slave_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] axi_slave_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] axi_slave_w_user_i, + input logic axi_slave_w_last_i, + output logic axi_slave_w_ready_o, + + // READ DATA CHANNEL + output logic axi_slave_r_valid_o, + output logic [AXI_DATA_WIDTH-1:0] axi_slave_r_data_o, + output logic [1:0] axi_slave_r_resp_o, + output logic axi_slave_r_last_o, + output logic [AXI_ID_WIDTH-1:0] axi_slave_r_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_slave_r_user_o, + input logic axi_slave_r_ready_i, + + // WRITE RESPONSE CHANNEL + output logic axi_slave_b_valid_o, + output logic [1:0] axi_slave_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] axi_slave_b_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_slave_b_user_o, + input logic axi_slave_b_ready_i, + + // PERIPHERAL INTERCONNECT MASTER + //*************************************** + //REQUEST CHANNEL + output logic per_master_req_o, + output logic [PER_ADDR_WIDTH-1:0] per_master_add_o, + output logic per_master_we_no, + output logic [5:0] per_master_atop_o, + output logic [31:0] per_master_wdata_o, + output logic [3:0] per_master_be_o, + input logic per_master_gnt_i, + + //RESPONSE CHANNEL + input logic per_master_r_valid_i, + input logic per_master_r_opc_i, + input logic [31:0] per_master_r_rdata_i, + + // BUSY SIGNAL + output logic busy_o +); + + // SIGNAL DECLARATION + logic s_aw_valid; + logic [AXI_ADDR_WIDTH-1:0] s_aw_addr; + logic [2:0] s_aw_prot; + logic [3:0] s_aw_region; + logic [7:0] s_aw_len; + logic [2:0] s_aw_size; + logic [1:0] s_aw_burst; + logic s_aw_lock; + logic [5:0] s_aw_atop; + logic [3:0] s_aw_cache; + logic [3:0] s_aw_qos; + logic [AXI_ID_WIDTH-1:0] s_aw_id; + logic [AXI_USER_WIDTH-1:0] s_aw_user; + logic s_aw_ready; + + logic s_ar_valid; + logic [AXI_ADDR_WIDTH-1:0] s_ar_addr; + logic [2:0] s_ar_prot; + logic [3:0] s_ar_region; + logic [7:0] s_ar_len; + logic [2:0] s_ar_size; + logic [1:0] s_ar_burst; + logic s_ar_lock; + logic [3:0] s_ar_cache; + logic [3:0] s_ar_qos; + logic [AXI_ID_WIDTH-1:0] s_ar_id; + logic [AXI_USER_WIDTH-1:0] s_ar_user; + logic s_ar_ready; + + logic s_w_valid; + logic [AXI_DATA_WIDTH-1:0] s_w_data; + logic [AXI_STRB_WIDTH-1:0] s_w_strb; + logic [AXI_USER_WIDTH-1:0] s_w_user; + logic s_w_last; + logic s_w_ready; + + logic s_r_valid; + logic [AXI_DATA_WIDTH-1:0] s_r_data; + logic [1:0] s_r_resp; + logic s_r_last; + logic [AXI_ID_WIDTH-1:0] s_r_id; + logic [AXI_USER_WIDTH-1:0] s_r_user; + logic s_r_ready; + + logic s_b_valid; + logic [1:0] s_b_resp; + logic [AXI_ID_WIDTH-1:0] s_b_id; + logic [AXI_USER_WIDTH-1:0] s_b_user; + logic s_b_ready; + + logic s_trans_req; + logic s_trans_we, + s_trans_atop_r; + logic [AXI_ID_WIDTH-1:0] s_trans_id; + logic [AXI_ADDR_WIDTH-1:0] s_trans_add; + logic s_trans_r_valid; + + // AXI2PER REQUEST CHANNEL + axi2per_req_channel + #( + .PER_ADDR_WIDTH ( PER_ADDR_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + ) + req_channel_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .cluster_id_i ( cluster_id_i ), + + .axi_slave_aw_valid_i ( s_aw_valid ), + .axi_slave_aw_addr_i ( s_aw_addr ), + .axi_slave_aw_prot_i ( s_aw_prot ), + .axi_slave_aw_region_i ( s_aw_region ), + .axi_slave_aw_len_i ( s_aw_len ), + .axi_slave_aw_size_i ( s_aw_size ), + .axi_slave_aw_burst_i ( s_aw_burst ), + .axi_slave_aw_lock_i ( s_aw_lock ), + .axi_slave_aw_atop_i ( s_aw_atop ), + .axi_slave_aw_cache_i ( s_aw_cache ), + .axi_slave_aw_qos_i ( s_aw_qos ), + .axi_slave_aw_id_i ( s_aw_id ), + .axi_slave_aw_user_i ( s_aw_user ), + .axi_slave_aw_ready_o ( s_aw_ready ), + + .axi_slave_ar_valid_i ( s_ar_valid ), + .axi_slave_ar_addr_i ( s_ar_addr ), + .axi_slave_ar_prot_i ( s_ar_prot ), + .axi_slave_ar_region_i ( s_ar_region ), + .axi_slave_ar_len_i ( s_ar_len ), + .axi_slave_ar_size_i ( s_ar_size ), + .axi_slave_ar_burst_i ( s_ar_burst ), + .axi_slave_ar_lock_i ( s_ar_lock ), + .axi_slave_ar_cache_i ( s_ar_cache ), + .axi_slave_ar_qos_i ( s_ar_qos ), + .axi_slave_ar_id_i ( s_ar_id ), + .axi_slave_ar_user_i ( s_ar_user ), + .axi_slave_ar_ready_o ( s_ar_ready ), + + .axi_slave_w_valid_i ( s_w_valid ), + .axi_slave_w_data_i ( s_w_data ), + .axi_slave_w_strb_i ( s_w_strb ), + .axi_slave_w_user_i ( s_w_user ), + .axi_slave_w_last_i ( s_w_last ), + .axi_slave_w_ready_o ( s_w_ready ), + + .per_master_req_o ( per_master_req_o ), + .per_master_add_o ( per_master_add_o ), + .per_master_we_o ( per_master_we_no ), + .per_master_atop_o ( per_master_atop_o ), + .per_master_wdata_o ( per_master_wdata_o ), + .per_master_be_o ( per_master_be_o ), + .per_master_gnt_i ( per_master_gnt_i ), + + .trans_req_o ( s_trans_req ), + .trans_we_o ( s_trans_we ), + .trans_atop_r_o ( s_trans_atop_r ), + .trans_id_o ( s_trans_id ), + .trans_add_o ( s_trans_add ), + .trans_r_valid_i ( s_trans_r_valid ), + + .busy_o ( busy_o ) + ); + + // AXI2PER RESPONSE CHANNEL + axi2per_res_channel + #( + .PER_ADDR_WIDTH ( PER_ADDR_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + ) + res_channel_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .axi_slave_r_valid_o ( s_r_valid ), + .axi_slave_r_data_o ( s_r_data ), + .axi_slave_r_resp_o ( s_r_resp ), + .axi_slave_r_last_o ( s_r_last ), + .axi_slave_r_id_o ( s_r_id ), + .axi_slave_r_user_o ( s_r_user ), + .axi_slave_r_ready_i ( s_r_ready ), + + .axi_slave_b_valid_o ( s_b_valid ), + .axi_slave_b_resp_o ( s_b_resp ), + .axi_slave_b_id_o ( s_b_id ), + .axi_slave_b_user_o ( s_b_user ), + .axi_slave_b_ready_i ( s_b_ready ), + + .per_master_r_valid_i ( per_master_r_valid_i ), + .per_master_r_opc_i ( per_master_r_opc_i ), + .per_master_r_rdata_i ( per_master_r_rdata_i ), + + .trans_req_i ( s_trans_req ), + .trans_we_i ( s_trans_we ), + .trans_atop_r_i ( s_trans_atop_r ), + .trans_id_i ( s_trans_id ), + .trans_add_i ( s_trans_add ), + .trans_r_valid_o ( s_trans_r_valid ) + ); + + + + + // AXI WRITE ADDRESS CHANNEL BUFFER + axi_aw_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) + aw_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( axi_slave_aw_valid_i ), + .slave_addr_i ( axi_slave_aw_addr_i ), + .slave_prot_i ( axi_slave_aw_prot_i ), + .slave_region_i ( axi_slave_aw_region_i ), + .slave_len_i ( axi_slave_aw_len_i ), + .slave_size_i ( axi_slave_aw_size_i ), + .slave_burst_i ( axi_slave_aw_burst_i ), + .slave_lock_i ( axi_slave_aw_lock_i ), + .slave_atop_i ( axi_slave_aw_atop_i ), + .slave_cache_i ( axi_slave_aw_cache_i ), + .slave_qos_i ( axi_slave_aw_qos_i ), + .slave_id_i ( axi_slave_aw_id_i ), + .slave_user_i ( axi_slave_aw_user_i ), + .slave_ready_o ( axi_slave_aw_ready_o ), + + .master_valid_o ( s_aw_valid ), + .master_addr_o ( s_aw_addr ), + .master_prot_o ( s_aw_prot ), + .master_region_o ( s_aw_region ), + .master_len_o ( s_aw_len ), + .master_size_o ( s_aw_size ), + .master_burst_o ( s_aw_burst ), + .master_lock_o ( s_aw_lock ), + .master_atop_o ( s_aw_atop ), + .master_cache_o ( s_aw_cache ), + .master_qos_o ( s_aw_qos ), + .master_id_o ( s_aw_id ), + .master_user_o ( s_aw_user ), + .master_ready_i ( s_aw_ready ) + ); + + // AXI READ ADDRESS CHANNEL BUFFER + axi_ar_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) + ar_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( axi_slave_ar_valid_i ), + .slave_addr_i ( axi_slave_ar_addr_i ), + .slave_prot_i ( axi_slave_ar_prot_i ), + .slave_region_i ( axi_slave_ar_region_i ), + .slave_len_i ( axi_slave_ar_len_i ), + .slave_size_i ( axi_slave_ar_size_i ), + .slave_burst_i ( axi_slave_ar_burst_i ), + .slave_lock_i ( axi_slave_ar_lock_i ), + .slave_cache_i ( axi_slave_ar_cache_i ), + .slave_qos_i ( axi_slave_ar_qos_i ), + .slave_id_i ( axi_slave_ar_id_i ), + .slave_user_i ( axi_slave_ar_user_i ), + .slave_ready_o ( axi_slave_ar_ready_o ), + + .master_valid_o ( s_ar_valid ), + .master_addr_o ( s_ar_addr ), + .master_prot_o ( s_ar_prot ), + .master_region_o ( s_ar_region ), + .master_len_o ( s_ar_len ), + .master_size_o ( s_ar_size ), + .master_burst_o ( s_ar_burst ), + .master_lock_o ( s_ar_lock ), + .master_cache_o ( s_ar_cache ), + .master_qos_o ( s_ar_qos ), + .master_id_o ( s_ar_id ), + .master_user_o ( s_ar_user ), + .master_ready_i ( s_ar_ready ) + ); + + // WRITE DATA CHANNEL BUFFER + axi_w_buffer + #( + .DATA_WIDTH ( AXI_DATA_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) + w_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( axi_slave_w_valid_i ), + .slave_data_i ( axi_slave_w_data_i ), + .slave_strb_i ( axi_slave_w_strb_i ), + .slave_user_i ( axi_slave_w_user_i ), + .slave_last_i ( axi_slave_w_last_i ), + .slave_ready_o ( axi_slave_w_ready_o ), + + .master_valid_o ( s_w_valid ), + .master_data_o ( s_w_data ), + .master_strb_o ( s_w_strb ), + .master_user_o ( s_w_user ), + .master_last_o ( s_w_last ), + .master_ready_i ( s_w_ready ) + ); + + // READ DATA CHANNEL BUFFER + axi_r_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .DATA_WIDTH ( AXI_DATA_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) + r_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( s_r_valid ), + .slave_data_i ( s_r_data ), + .slave_resp_i ( s_r_resp ), + .slave_user_i ( s_r_user ), + .slave_id_i ( s_r_id ), + .slave_last_i ( s_r_last ), + .slave_ready_o ( s_r_ready ), + + .master_valid_o ( axi_slave_r_valid_o ), + .master_data_o ( axi_slave_r_data_o ), + .master_resp_o ( axi_slave_r_resp_o ), + .master_user_o ( axi_slave_r_user_o ), + .master_id_o ( axi_slave_r_id_o ), + .master_last_o ( axi_slave_r_last_o ), + .master_ready_i ( axi_slave_r_ready_i ) + ); + + // WRITE RESPONSE CHANNEL BUFFER + axi_b_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) + b_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( s_b_valid ), + .slave_resp_i ( s_b_resp ), + .slave_id_i ( s_b_id ), + .slave_user_i ( s_b_user ), + .slave_ready_o ( s_b_ready ), + + .master_valid_o ( axi_slave_b_valid_o ), + .master_resp_o ( axi_slave_b_resp_o ), + .master_id_o ( axi_slave_b_id_o ), + .master_user_o ( axi_slave_b_user_o ), + .master_ready_i ( axi_slave_b_ready_i ) + ); + + `ifndef TARGET_SYNTHESIS + assert property (@(posedge clk_i) disable iff (!rst_ni) + axi_slave_aw_valid_i |-> axi_slave_aw_len_i == '0) + else $error("This module does not support bursts!"); + assert property (@(posedge clk_i) disable iff (!rst_ni) + axi_slave_ar_valid_i |-> axi_slave_ar_len_i == '0) + else $error("This module does not support bursts!"); + assert property (@(posedge clk_i) disable iff (!rst_ni) + axi_slave_aw_valid_i |-> axi_slave_aw_size_i <= 3'd2) + else $error("This module does not support beats wider than 32 bit!"); + assert property (@(posedge clk_i) disable iff (!rst_ni) + axi_slave_ar_valid_i |-> axi_slave_ar_size_i <= 3'd2) + else $error("This module does not support beats wider than 32 bit!"); + `endif + +endmodule diff --git a/hw/deps/axi2per/axi2per_req_channel.sv b/hw/deps/axi2per/axi2per_req_channel.sv new file mode 100644 index 0000000..0437673 --- /dev/null +++ b/hw/deps/axi2per/axi2per_req_channel.sv @@ -0,0 +1,215 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi2per_req_channel #( + // PARAMETERS + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3, + // LOCAL PARAMETERS --> DO NOT OVERRIDE + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 // DO NOT OVERRIDE +) ( + input logic clk_i, + input logic rst_ni, + + input logic [5:0] cluster_id_i, + + input logic axi_slave_aw_valid_i, + input logic [AXI_ADDR_WIDTH-1:0] axi_slave_aw_addr_i, + input logic [2:0] axi_slave_aw_prot_i, + input logic [3:0] axi_slave_aw_region_i, + input logic [7:0] axi_slave_aw_len_i, + input logic [2:0] axi_slave_aw_size_i, + input logic [1:0] axi_slave_aw_burst_i, + input logic axi_slave_aw_lock_i, + input logic [5:0] axi_slave_aw_atop_i, + input logic [3:0] axi_slave_aw_cache_i, + input logic [3:0] axi_slave_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] axi_slave_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_slave_aw_user_i, + output logic axi_slave_aw_ready_o, + + // READ ADDRESS CHANNEL + input logic axi_slave_ar_valid_i, + input logic [AXI_ADDR_WIDTH-1:0] axi_slave_ar_addr_i, + input logic [2:0] axi_slave_ar_prot_i, + input logic [3:0] axi_slave_ar_region_i, + input logic [7:0] axi_slave_ar_len_i, + input logic [2:0] axi_slave_ar_size_i, + input logic [1:0] axi_slave_ar_burst_i, + input logic axi_slave_ar_lock_i, + input logic [3:0] axi_slave_ar_cache_i, + input logic [3:0] axi_slave_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] axi_slave_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_slave_ar_user_i, + output logic axi_slave_ar_ready_o, + + // WRITE DATA CHANNEL + input logic axi_slave_w_valid_i, + input logic [AXI_DATA_WIDTH-1:0] axi_slave_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] axi_slave_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] axi_slave_w_user_i, + input logic axi_slave_w_last_i, + output logic axi_slave_w_ready_o, + + // PERIPHERAL REQUEST CHANNEL + output logic per_master_req_o, + output logic [PER_ADDR_WIDTH-1:0] per_master_add_o, + output logic per_master_we_o, + output logic [5:0] per_master_atop_o, + output logic [31:0] per_master_wdata_o, + output logic [3:0] per_master_be_o, + input logic per_master_gnt_i, + + // CONTROL SIGNALS + output logic trans_req_o, + output logic trans_we_o, + output logic trans_atop_r_o, + output logic [AXI_ID_WIDTH-1:0] trans_id_o, + output logic [AXI_ADDR_WIDTH-1:0] trans_add_o, + input logic trans_r_valid_i, + + // BUSY SIGNAL + output logic busy_o +); + + enum logic {TransIdle, TransPending} state_d, state_q; + + logic inv_wdata; + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + state_q <= TransIdle; + end else begin + state_q <= state_d; + end + end + + // COMPUTE NEXT STATE + always_comb begin + axi_slave_aw_ready_o = 1'b0; + axi_slave_ar_ready_o = 1'b0; + axi_slave_w_ready_o = 1'b0; + + per_master_req_o = 1'b0; + per_master_add_o = '0; + per_master_we_o = 1'b0; + per_master_wdata_o = '0; + per_master_be_o = '0; + + trans_req_o = 1'b0; + trans_id_o = '0; + trans_add_o = '0; + + busy_o = 1'b0; + + state_d = state_q; + + case (state_q) + TransIdle: begin + // Handle request on AR + if (axi_slave_ar_valid_i) begin + per_master_req_o = 1'b1; + per_master_we_o = 1'b1; // write enable is active low + per_master_add_o = axi_slave_ar_addr_i; + + if (per_master_gnt_i) begin + axi_slave_ar_ready_o = 1'b1; + + trans_req_o = 1'b1; + trans_id_o = axi_slave_ar_id_i; + trans_add_o = axi_slave_ar_addr_i; + + state_d = TransPending; + end + // Handle request on AW and W + end else if (axi_slave_aw_valid_i && axi_slave_w_valid_i) begin + per_master_req_o = 1'b1; + per_master_we_o = 1'b0; // write enable is active low + per_master_add_o = axi_slave_aw_addr_i; + + // Multiplex 64-bit W channel to 32-bit peripheral data channel based on the address. + if (axi_slave_aw_addr_i[2]) begin + per_master_be_o = axi_slave_w_strb_i[7:4]; + per_master_wdata_o = axi_slave_w_data_i[63:32]; + end else begin + per_master_be_o = axi_slave_w_strb_i[3:0]; + per_master_wdata_o = axi_slave_w_data_i[31:0]; + end + + if (inv_wdata) begin + per_master_wdata_o = ~per_master_wdata_o; + end + + if (per_master_gnt_i) begin + axi_slave_aw_ready_o = 1'b1; + axi_slave_w_ready_o = 1'b1; + + trans_req_o = 1'b1; + trans_id_o = axi_slave_aw_id_i; + trans_add_o = axi_slave_aw_addr_i; + + state_d = TransPending; + end + end + per_master_add_o = per_master_add_o - (32'h0040_0000 * cluster_id_i); + end + + TransPending: begin + busy_o = 1'b1; + if (trans_r_valid_i) begin + // Received notification from response channel -> transaction completed. + state_d = TransIdle; + end + end + endcase + end + assign trans_we_o = per_master_we_o; + + always_comb begin + inv_wdata = 1'b0; + per_master_atop_o = '0; + trans_atop_r_o = 1'b0; + if (!per_master_we_o && axi_slave_aw_atop_i[5:4] != axi_pkg::ATOP_NONE) begin + if (axi_slave_aw_atop_i == axi_pkg::ATOP_ATOMICSWAP) begin + per_master_atop_o = riscv_defines::AMO_SWAP; + end else begin + case (axi_slave_aw_atop_i[2:0]) + axi_pkg::ATOP_ADD: per_master_atop_o = riscv_defines::AMO_ADD; + axi_pkg::ATOP_CLR: begin + inv_wdata = 1'b1; + per_master_atop_o = riscv_defines::AMO_AND; + end + axi_pkg::ATOP_EOR: per_master_atop_o = riscv_defines::AMO_XOR; + axi_pkg::ATOP_SET: per_master_atop_o = riscv_defines::AMO_OR; + axi_pkg::ATOP_SMAX: per_master_atop_o = riscv_defines::AMO_MAX; + axi_pkg::ATOP_SMIN: per_master_atop_o = riscv_defines::AMO_MIN; + axi_pkg::ATOP_UMAX: per_master_atop_o = riscv_defines::AMO_MAXU; + axi_pkg::ATOP_UMIN: per_master_atop_o = riscv_defines::AMO_MINU; + endcase + if (axi_slave_aw_atop_i[5:4] == axi_pkg::ATOP_ATOMICLOAD) begin + trans_atop_r_o = 1'b1; + end + end + end + end + + `ifndef TARGET_SYNTHESIS + assert property (@(posedge clk_i) disable iff (!rst_ni) + axi_slave_aw_atop_i != axi_pkg::ATOP_ATOMICCMP) + else $error("Atomic compare-and-swap not supported!"); + `endif + +endmodule diff --git a/hw/deps/axi2per/axi2per_res_channel.sv b/hw/deps/axi2per/axi2per_res_channel.sv new file mode 100644 index 0000000..4c7700e --- /dev/null +++ b/hw/deps/axi2per/axi2per_res_channel.sv @@ -0,0 +1,183 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi2per_res_channel #( + // PARAMETERS + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3 +) ( + input logic clk_i, + input logic rst_ni, + + // PERIPHERAL INTERCONNECT MASTER + //*************************************** + //RESPONSE CHANNEL + input logic per_master_r_valid_i, + input logic per_master_r_opc_i, + input logic [31:0] per_master_r_rdata_i, + + // AXI4 MASTER + //*************************************** + // READ DATA CHANNEL + output logic axi_slave_r_valid_o, + output logic [AXI_DATA_WIDTH-1:0] axi_slave_r_data_o, + output logic [1:0] axi_slave_r_resp_o, + output logic axi_slave_r_last_o, + output logic [AXI_ID_WIDTH-1:0] axi_slave_r_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_slave_r_user_o, + input logic axi_slave_r_ready_i, + + // WRITE RESPONSE CHANNEL + output logic axi_slave_b_valid_o, + output logic [1:0] axi_slave_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] axi_slave_b_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_slave_b_user_o, + input logic axi_slave_b_ready_i, + + // CONTROL SIGNALS + input logic trans_req_i, + input logic trans_we_i, + input logic trans_atop_r_i, + input logic [AXI_ID_WIDTH-1:0] trans_id_i, + input logic [AXI_ADDR_WIDTH-1:0] trans_add_i, + output logic trans_r_valid_o +); + + logic [AXI_DATA_WIDTH-1:0] s_axi_slave_r_data; + + logic [31:0] s_per_master_r_data; + + logic s_trans_add_alignment, //0 --> aligned to 64bit, 1--> not aligned to 64bit + s_trans_atop_r_buf, + s_trans_we_buf; + logic [AXI_ID_WIDTH-1:0] s_trans_id_buf; + + enum logic [1:0] {Idle, Pending, HoldB, HoldR} state_d, state_q; + + always_comb begin + axi_slave_r_valid_o = 1'b0; + axi_slave_r_data_o = '0; + axi_slave_r_last_o = 1'b0; + + axi_slave_b_valid_o = 1'b0; + + state_d = state_q; + + unique case (state_q) + Idle: begin + if (per_master_r_valid_i) begin + state_d = Pending; + end + end + + Pending: begin + if (s_trans_we_buf) begin // read + axi_slave_r_data_o = s_axi_slave_r_data; + axi_slave_r_last_o = 1'b1; + axi_slave_r_valid_o = 1'b1; + if (axi_slave_r_ready_i) begin + state_d = Idle; + end + end else begin // write + axi_slave_b_valid_o = 1'b1; + if (axi_slave_b_ready_i) begin + state_d = Idle; + end + if (s_trans_atop_r_buf) begin // ATOP with R response + axi_slave_r_data_o = s_axi_slave_r_data; + axi_slave_r_last_o = 1'b1; + axi_slave_r_valid_o = 1'b1; + case ({axi_slave_b_ready_i, axi_slave_r_ready_i}) + 2'b01: state_d = HoldB; + 2'b10: state_d = HoldR; + 2'b11: state_d = Idle; + endcase + end + end + end + + HoldB: begin + axi_slave_b_valid_o = 1'b1; + if (axi_slave_b_ready_i) begin + state_d = Idle; + end + end + + HoldR: begin + axi_slave_r_data_o = s_axi_slave_r_data; + axi_slave_r_last_o = 1'b1; + axi_slave_r_valid_o = 1'b1; + if (axi_slave_r_ready_i) begin + state_d = Idle; + end + end + + default: state_d = Idle; + endcase + end + + assign trans_r_valid_o = axi_slave_b_valid_o | axi_slave_r_valid_o; + assign axi_slave_b_id_o = s_trans_id_buf; + assign axi_slave_r_id_o = s_trans_id_buf; + + // Demultiplex the 32-bit data of the peripheral bus to the 64-bit AXI R channel. + always_comb begin + if (!s_trans_add_alignment) begin + s_axi_slave_r_data = {32'b0, s_per_master_r_data}; + end else begin + s_axi_slave_r_data = {s_per_master_r_data, 32'b0}; + end + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + s_per_master_r_data <= '0; + s_trans_add_alignment <= 1'b0; + s_trans_atop_r_buf <= 1'b0; + s_trans_id_buf <= '0; + s_trans_we_buf <= 1'b0; + state_q <= Idle; + end else begin + if (per_master_r_valid_i) begin + s_per_master_r_data <= per_master_r_rdata_i; + end + if (trans_req_i) begin + s_trans_add_alignment <= trans_add_i[2]; + s_trans_atop_r_buf <= trans_atop_r_i; + s_trans_id_buf <= trans_id_i; + s_trans_we_buf <= trans_we_i; + end + state_q <= state_d; + end + end + + // UNUSED SIGNALS + assign axi_slave_r_resp_o = '0; + assign axi_slave_r_user_o = '0; + assign axi_slave_b_resp_o = '0; + assign axi_slave_b_user_o = '0; + + `ifndef VERILATOR + `ifndef TARGET_SYNTHESIS + default disable iff (!rst_ni); + assert property (@(posedge clk_i) per_master_r_valid_i |-> state_q == Idle) + else $error("Lost response on peripheral bus!"); + assert property (@(posedge clk_i) trans_req_i |-> state_q == Idle) + else $error("Lost transfer request!"); + `endif + `endif + +endmodule diff --git a/hw/deps/axi_riscv_atomics/src/axi_res_tbl.sv b/hw/deps/axi_riscv_atomics/src/axi_res_tbl.sv new file mode 100644 index 0000000..657e6f5 --- /dev/null +++ b/hw/deps/axi_riscv_atomics/src/axi_res_tbl.sv @@ -0,0 +1,89 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI Reservation Table +module axi_res_tbl #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic [AXI_ADDR_WIDTH-1:0] check_clr_addr_i, + input logic [AXI_ID_WIDTH-1:0] check_id_i, + input logic check_clr_excl_i, + output logic check_res_o, + input logic check_clr_req_i, + output logic check_clr_gnt_o, + input logic [AXI_ADDR_WIDTH-1:0] set_addr_i, + input logic [AXI_ID_WIDTH-1:0] set_id_i, + input logic set_req_i, + output logic set_gnt_o +); + + localparam integer N_IDS = 2**AXI_ID_WIDTH; + + // Declarations of Signals and Types + logic [N_IDS-1:0][AXI_ADDR_WIDTH-1:0] tbl_d, tbl_q; + logic clr, + set; + + generate for (genvar i = 0; i < N_IDS; ++i) begin: gen_tbl + always_comb begin + tbl_d[i] = tbl_q[i]; + if (set && i == set_id_i) begin + tbl_d[i] = set_addr_i; + end else if (clr && tbl_q[i] == check_clr_addr_i) begin + tbl_d[i] = '0; + end + end + end endgenerate + + // Table-Managing Logic + always_comb begin + clr = 1'b0; + set = 1'b0; + set_gnt_o = 1'b0; + check_res_o = 1'b0; + check_clr_gnt_o = 1'b0; + + if (check_clr_req_i) begin + automatic logic match = (tbl_q[check_id_i] == check_clr_addr_i); + check_clr_gnt_o = 1'b1; + check_res_o = match; + clr = !(check_clr_excl_i && !match); + end else if (set_req_i) begin + set = 1'b1; + set_gnt_o = 1'b1; + end + end + + // Registers + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + tbl_q <= '0; + end else begin + tbl_q <= tbl_d; + end + end + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (AXI_ADDR_WIDTH > 0) + else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!"); + assert (AXI_ID_WIDTH > 0) + else $fatal(1, "AXI_ID_WIDTH must be greater than 0!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/axi_riscv_atomics/src/axi_riscv_amos.sv b/hw/deps/axi_riscv_atomics/src/axi_riscv_amos.sv new file mode 100644 index 0000000..98b3a73 --- /dev/null +++ b/hw/deps/axi_riscv_atomics/src/axi_riscv_amos.sv @@ -0,0 +1,1075 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V Atomic Operations (AMOs) Adapter +// +// This adapter implements atomic memory operations in accordance with the RVWMO memory consistency +// model. +// +// Interface notes: +// - This module has combinational paths between AXI inputs and outputs for minimum latency. Add +// slices upstream or downstream or in both directions if combinatorial paths become too long. +// The module adheres to the AXI ready/valid dependency specification to prevent combinatorial +// loops. + +module axi_riscv_amos #( + // AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + // Maximum number of AXI write transactions outstanding at the same time + parameter int unsigned AXI_MAX_WRITE_TXNS = 0, + // Word width of the widest RISC-V processor that can issue requests to this module. + // 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are + // supported if `aw_strb` is set correctly. + parameter int unsigned RISCV_WORD_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + + /// Slave Interface + input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i, + input logic [2:0] slv_aw_prot_i, + input logic [3:0] slv_aw_region_i, + input logic [5:0] slv_aw_atop_i, + input logic [7:0] slv_aw_len_i, + input logic [2:0] slv_aw_size_i, + input logic [1:0] slv_aw_burst_i, + input logic slv_aw_lock_i, + input logic [3:0] slv_aw_cache_i, + input logic [3:0] slv_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i, + output logic slv_aw_ready_o, + input logic slv_aw_valid_i, + + input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i, + input logic [2:0] slv_ar_prot_i, + input logic [3:0] slv_ar_region_i, + input logic [7:0] slv_ar_len_i, + input logic [2:0] slv_ar_size_i, + input logic [1:0] slv_ar_burst_i, + input logic slv_ar_lock_i, + input logic [3:0] slv_ar_cache_i, + input logic [3:0] slv_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i, + output logic slv_ar_ready_o, + input logic slv_ar_valid_i, + + input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] slv_w_user_i, + input logic slv_w_last_i, + output logic slv_w_ready_o, + input logic slv_w_valid_i, + + output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o, + output logic [1:0] slv_r_resp_o, + output logic slv_r_last_o, + output logic [AXI_ID_WIDTH-1:0] slv_r_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_r_user_o, + input logic slv_r_ready_i, + output logic slv_r_valid_o, + + output logic [1:0] slv_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] slv_b_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_b_user_o, + input logic slv_b_ready_i, + output logic slv_b_valid_o, + + /// Master Interface + output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o, + output logic [2:0] mst_aw_prot_o, + output logic [3:0] mst_aw_region_o, + output logic [5:0] mst_aw_atop_o, + output logic [7:0] mst_aw_len_o, + output logic [2:0] mst_aw_size_o, + output logic [1:0] mst_aw_burst_o, + output logic mst_aw_lock_o, + output logic [3:0] mst_aw_cache_o, + output logic [3:0] mst_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o, + input logic mst_aw_ready_i, + output logic mst_aw_valid_o, + + output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o, + output logic [2:0] mst_ar_prot_o, + output logic [3:0] mst_ar_region_o, + output logic [7:0] mst_ar_len_o, + output logic [2:0] mst_ar_size_o, + output logic [1:0] mst_ar_burst_o, + output logic mst_ar_lock_o, + output logic [3:0] mst_ar_cache_o, + output logic [3:0] mst_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o, + input logic mst_ar_ready_i, + output logic mst_ar_valid_o, + + output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] mst_w_user_o, + output logic mst_w_last_o, + input logic mst_w_ready_i, + output logic mst_w_valid_o, + + input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i, + input logic [1:0] mst_r_resp_i, + input logic mst_r_last_i, + input logic [AXI_ID_WIDTH-1:0] mst_r_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_r_user_i, + output logic mst_r_ready_o, + input logic mst_r_valid_i, + + input logic [1:0] mst_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] mst_b_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_b_user_i, + output logic mst_b_ready_o, + input logic mst_b_valid_i +); + + localparam int unsigned OUTSTND_BURSTS_WIDTH = $clog2(AXI_MAX_WRITE_TXNS+1); + localparam int unsigned AXI_ALU_RATIO = AXI_DATA_WIDTH/RISCV_WORD_WIDTH; + + // State types + typedef enum logic [1:0] { FEEDTHROUGH_AW, WAIT_RESULT_AW, SEND_AW } aw_state_t; + aw_state_t aw_state_d, aw_state_q; + + typedef enum logic [2:0] { FEEDTHROUGH_W, WAIT_DATA_W, WAIT_RESULT_W, WAIT_CHANNEL_W, SEND_W } w_state_t; + w_state_t w_state_d, w_state_q; + + typedef enum logic [1:0] { FEEDTHROUGH_B, WAIT_COMPLETE_B, WAIT_CHANNEL_B, SEND_B } b_state_t; + b_state_t b_state_d, b_state_q; + + typedef enum logic [1:0] { FEEDTHROUGH_AR, WAIT_CHANNEL_AR, SEND_AR } ar_state_t; + ar_state_t ar_state_d, ar_state_q; + + typedef enum logic [1:0] { FEEDTHROUGH_R, WAIT_DATA_R, WAIT_CHANNEL_R, SEND_R } r_state_t; + r_state_t r_state_d, r_state_q; + + typedef enum logic [1:0] { NONE, INVALID, LOAD, STORE } atop_req_t; + atop_req_t atop_valid_d, atop_valid_q; + + // Signal declarations + // Transaction FF + logic [AXI_ADDR_WIDTH-1:0] addr_d, addr_q; + logic [AXI_ID_WIDTH-1:0] id_d, id_q; + logic [AXI_STRB_WIDTH-1:0] strb_d, strb_q; + logic [2:0] size_d, size_q; + logic [5:0] atop_d, atop_q; + logic [3:0] cache_d, cache_q; + logic [2:0] prot_d, prot_q; + logic [3:0] qos_d, qos_q; + logic [3:0] region_d, region_q; + logic [1:0] r_resp_d, r_resp_q; + logic [AXI_USER_WIDTH-1:0] aw_user_d, aw_user_q, + w_user_d, w_user_q, + r_user_d, r_user_q; + // Data FF + logic [AXI_DATA_WIDTH-1:0] w_data_d, w_data_q; // AMO operand + logic [AXI_DATA_WIDTH-1:0] r_data_d, r_data_q; // Data from memory + logic [AXI_DATA_WIDTH-1:0] result_d, result_q; // Result of AMO operation + logic w_d_valid_d, w_d_valid_q, // AMO operand valid + r_d_valid_d, r_d_valid_q; // Data from memory valid + // Counters + logic [OUTSTND_BURSTS_WIDTH-1:0] aw_trans_d, aw_trans_q; // AW transaction in flight downstream + logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_d, w_cnt_q; // Outstanding W beats + logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_req_d, w_cnt_req_q; // W beats until AMO can read W + logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_inj_d, w_cnt_inj_q; // W beats until AMO can insert its W + // States + logic adapter_ready; + logic transaction_collision; + logic force_wf_d, force_wf_q; + logic start_wf_d, start_wf_q; + logic b_resp_valid; + logic aw_valid, aw_ready, aw_free, + w_valid, w_ready, w_free, + b_valid, b_ready, b_free, + ar_valid, ar_ready, ar_free, + r_valid, r_ready, r_free; + // ALU Signals + logic [RISCV_WORD_WIDTH-1:0] alu_operand_a; + logic [RISCV_WORD_WIDTH-1:0] alu_operand_b; + logic [RISCV_WORD_WIDTH-1:0] alu_result; + logic [AXI_DATA_WIDTH-1:0] alu_result_ext; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a_sign_ext; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b_sign_ext; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] res; + logic [AXI_STRB_WIDTH-1:0][7:0] strb_ext; + logic sign_a; + logic sign_b; + + /** + * Calculate ready signals and channel states + */ + + // Check if all state machines are ready for the next atomic request + assign adapter_ready = (aw_state_q == FEEDTHROUGH_AW) && + ( w_state_q == FEEDTHROUGH_W ) && + ( b_state_q == FEEDTHROUGH_B ) && + (ar_state_q == FEEDTHROUGH_AR) && + ( r_state_q == FEEDTHROUGH_R ); + + // Calculate if the channels are free + assign aw_free = ~aw_valid | aw_ready; + assign w_free = ~ w_valid | w_ready; + assign b_free = ~ b_valid | b_ready; + assign ar_free = ~ar_valid | ar_ready; + assign r_free = ~ r_valid | r_ready; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + aw_valid <= 0; + aw_ready <= 0; + w_valid <= 0; + w_ready <= 0; + b_valid <= 0; + b_ready <= 0; + ar_valid <= 0; + ar_ready <= 0; + r_valid <= 0; + r_ready <= 0; + end else begin + aw_valid <= mst_aw_valid_o; + aw_ready <= mst_aw_ready_i; + w_valid <= mst_w_valid_o; + w_ready <= mst_w_ready_i; + b_valid <= slv_b_valid_o; + b_ready <= slv_b_ready_i; + ar_valid <= mst_ar_valid_o; + ar_ready <= mst_ar_ready_i; + r_valid <= slv_r_valid_o; + r_ready <= slv_r_ready_i; + end + end + + // Calculate if the request interferes with the ongoing atomic transaction + // The protected bytes go from addr_q up to addr_q + (1 << size_q) - 1 + // TODO Bursts need special treatment + assign transaction_collision = (slv_aw_addr_i < ( addr_q + (8'h01 << size_q))) & + ( addr_q < (slv_aw_addr_i + (8'h01 << slv_aw_size_i))); + + always_comb begin : calc_atop_valid + atop_valid_d = atop_valid_q; + if (adapter_ready) begin + atop_valid_d = NONE; + if (slv_aw_valid_i && slv_aw_atop_i) begin + // Default is invalid request + atop_valid_d = INVALID; + // Valid load operation + if ((slv_aw_atop_i == axi_pkg::ATOP_ATOMICSWAP) || + (slv_aw_atop_i[5:3] == {axi_pkg::ATOP_ATOMICLOAD , axi_pkg::ATOP_LITTLE_END})) begin + atop_valid_d = LOAD; + end + // Valid store operation + if (slv_aw_atop_i[5:3] == {axi_pkg::ATOP_ATOMICSTORE, axi_pkg::ATOP_LITTLE_END}) begin + atop_valid_d = STORE; + end + // Invalidate valid request if control signals do not match + // Burst or exclusive access + if (slv_aw_len_i | slv_aw_lock_i) begin + atop_valid_d = INVALID; + end + // Unsupported size + if (slv_aw_size_i > $clog2(RISCV_WORD_WIDTH/8)) begin + atop_valid_d = INVALID; + end + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_atop_valid + if(~rst_ni) begin + atop_valid_q <= NONE; + end else begin + atop_valid_q <= atop_valid_d; + end + end + + /** + * Write Channel: AW, W, B + */ + + /*==================================================================== + = AW = + ====================================================================*/ + always_comb begin : axi_aw_channel + // Defaults AXI Bus + mst_aw_id_o = slv_aw_id_i; + mst_aw_addr_o = slv_aw_addr_i; + mst_aw_len_o = slv_aw_len_i; + mst_aw_size_o = slv_aw_size_i; + mst_aw_burst_o = slv_aw_burst_i; + mst_aw_lock_o = slv_aw_lock_i; + mst_aw_cache_o = slv_aw_cache_i; + mst_aw_prot_o = slv_aw_prot_i; + mst_aw_qos_o = slv_aw_qos_i; + mst_aw_region_o = slv_aw_region_i; + mst_aw_atop_o = 6'b0; + mst_aw_user_o = slv_aw_user_i; + // Defaults FF + addr_d = addr_q; + id_d = id_q; + size_d = size_q; + atop_d = atop_q; + cache_d = cache_q; + prot_d = prot_q; + qos_d = qos_q; + region_d = region_q; + aw_user_d = aw_user_q; + w_cnt_inj_d = w_cnt_inj_q; + // State Machine + aw_state_d = aw_state_q; + + // Default control: Block AW channel if... + if (slv_aw_valid_i && slv_aw_atop_i) begin + // Block if atomic request + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + end else if (w_cnt_q == AXI_MAX_WRITE_TXNS || aw_trans_q == AXI_MAX_WRITE_TXNS) begin + // Block if counter is overflowing + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + end else if (force_wf_q && aw_free) begin // TODO: no not instantly block the channel but only if its free + // Block if the adapter is in force wait-free mode + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + end else if (slv_aw_valid_i && transaction_collision && !adapter_ready) begin + // Block requests to the same address as current atomic transaction + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + end else begin + // Forward + mst_aw_valid_o = slv_aw_valid_i; + slv_aw_ready_o = mst_aw_ready_i; + end + + // Count W burst to know when to inject the W data + if (w_cnt_inj_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_inj_d = w_cnt_inj_q - 1; + end + + unique case (aw_state_q) + + FEEDTHROUGH_AW: begin + // Feedthrough slave to master until atomic operation is detected + if (slv_aw_valid_i && slv_aw_atop_i && adapter_ready) begin + // Acknowledge atomic transaction + slv_aw_ready_o = 1'b1; + // Remember request + atop_d = slv_aw_atop_i; + addr_d = slv_aw_addr_i; + id_d = slv_aw_id_i; + size_d = slv_aw_size_i; + cache_d = slv_aw_cache_i; + prot_d = slv_aw_prot_i; + qos_d = slv_aw_qos_i; + region_d = slv_aw_region_i; + aw_user_d = slv_aw_user_i; + // If valid AMO --> wait for result + if (atop_valid_d != INVALID) begin + aw_state_d = WAIT_RESULT_AW; + end + end + + if (start_wf_q) begin + // Forced wait-free state --> wait for ALU once more + aw_state_d = WAIT_RESULT_AW; + end + + + end // FEEDTHROUGH_AW + + WAIT_RESULT_AW, SEND_AW: begin + // If the result is ready and the channel is free --> inject AW request + if ((r_d_valid_q && w_d_valid_q && aw_free) || (aw_state_q == SEND_AW)) begin + // Block + slv_aw_ready_o = 1'b0; + // Make write request + mst_aw_valid_o = 1'b1; + mst_aw_addr_o = addr_q; + mst_aw_len_o = 8'h00; + mst_aw_id_o = id_q; + mst_aw_size_o = size_q; + mst_aw_burst_o = 2'b00; + mst_aw_lock_o = ~force_wf_q; + mst_aw_cache_o = cache_q; + mst_aw_prot_o = prot_q; + mst_aw_qos_o = qos_q; + mst_aw_region_o = region_q; + mst_aw_user_o = aw_user_q; + // Check if request is acknowledged + if (mst_aw_ready_i) begin + aw_state_d = FEEDTHROUGH_AW; + end else begin + aw_state_d = SEND_AW; + end + // Remember outstanding W beats before injected request + if (aw_state_q == WAIT_RESULT_AW) begin + if (w_cnt_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_inj_d = w_cnt_q - 1; + end else begin + w_cnt_inj_d = w_cnt_q; + end + end + end + end // WAIT_RESULT_AW, SEND_AW + + default: aw_state_d = FEEDTHROUGH_AW; + + endcase + end // axi_aw_channel + + /*==================================================================== + = W = + ====================================================================*/ + always_comb begin : axi_w_channel + // Defaults AXI Bus + mst_w_data_o = slv_w_data_i; + mst_w_strb_o = slv_w_strb_i; + mst_w_last_o = slv_w_last_i; + mst_w_user_o = slv_w_user_i; + // Defaults FF + strb_d = strb_q; + w_user_d = w_user_q; + w_data_d = w_data_q; + result_d = result_q; + w_d_valid_d = w_d_valid_q; + w_cnt_req_d = w_cnt_req_q; + // State Machine + w_state_d = w_state_q; + + // Default control + // Make sure no data is sent without knowing if it's atomic + if (w_cnt_q == 0) begin + // Stall W as it precedes the AW request + slv_w_ready_o = 1'b0; + mst_w_valid_o = 1'b0; + end else begin + mst_w_valid_o = slv_w_valid_i; + slv_w_ready_o = mst_w_ready_i; + end + + unique case (w_state_q) + + FEEDTHROUGH_W: begin + if (adapter_ready) begin + // Reset read flag + w_d_valid_d = 1'b0; + result_d = '0; + + if (atop_valid_d != NONE) begin + // Check if data is also available and does not belong to previous request + if (w_cnt_q == 0) begin + // Block downstream + mst_w_valid_o = 1'b0; + // Fetch data and wait for all data + slv_w_ready_o = 1'b1; + if (slv_w_valid_i) begin + if (atop_valid_d != INVALID) begin + w_data_d = slv_w_data_i; + strb_d = slv_w_strb_i; + w_user_d = slv_w_user_i; + w_d_valid_d = 1'b1; + w_state_d = WAIT_RESULT_W; + end + end else begin + w_cnt_req_d = '0; + w_state_d = WAIT_DATA_W; + end + end else begin + // Remember the amount of outstanding bursts and count down + if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_req_d = w_cnt_q - 1; + end else begin + w_cnt_req_d = w_cnt_q; + end + w_state_d = WAIT_DATA_W; + end + end + end + + if (start_wf_q) begin + // Forced wait-free state --> wait for ALU once more + w_state_d = WAIT_RESULT_W; + end + + end // FEEDTHROUGH_W + + WAIT_DATA_W: begin + // Count W beats until data arrives that belongs to the AMO request + if (w_cnt_req_q == 0) begin + // Block downstream + mst_w_valid_o = 1'b0; + // Ready upstream + slv_w_ready_o = 1'b1; + + if (slv_w_valid_i) begin + if (atop_valid_q == INVALID) begin + w_state_d = FEEDTHROUGH_W; + end else begin + w_data_d = slv_w_data_i; + strb_d = slv_w_strb_i; + w_user_d = slv_w_user_i; + w_d_valid_d = 1'b1; + w_state_d = WAIT_RESULT_W; + end + end + end else if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_req_d = w_cnt_req_q - 1; + end + end // WAIT_DATA_W + + WAIT_RESULT_W: begin + // If the result is ready, try to write it + if (r_d_valid_q && w_d_valid_q && aw_free) begin + // Check if W channel is free and make sure data is not interleaved + result_d = alu_result_ext; + if (w_free && w_cnt_q == 0) begin + // Block + slv_w_ready_o = 1'b0; + // Send write data + mst_w_valid_o = 1'b1; + mst_w_data_o = alu_result_ext; + mst_w_last_o = 1'b1; + mst_w_strb_o = strb_q; + mst_w_user_o = w_user_q; + if (mst_w_ready_i) begin + w_state_d = FEEDTHROUGH_W; + end else begin + w_state_d = SEND_W; + end + end else begin + w_state_d = WAIT_CHANNEL_W; + end + end + end // WAIT_RESULT_W + + WAIT_CHANNEL_W, SEND_W: begin + // Wait to not interleave the data + if ((w_free && w_cnt_inj_q == 0) || (w_state_q == SEND_W)) begin + // Block + slv_w_ready_o = 1'b0; + // Send write data + mst_w_valid_o = 1'b1; + mst_w_data_o = result_q; + mst_w_last_o = 1'b1; + mst_w_strb_o = strb_q; + mst_w_user_o = w_user_q; + if (mst_w_ready_i) begin + w_state_d = FEEDTHROUGH_W; + end else begin + w_state_d = SEND_W; + end + end + end // WAIT_CHANNEL_W, SEND_W + + default: w_state_d = FEEDTHROUGH_W; + + endcase + end // axi_w_channel + + /*==================================================================== + = B = + ====================================================================*/ + always_comb begin : axi_b_channel + // Defaults AXI Bus + mst_b_ready_o = slv_b_ready_i; + slv_b_id_o = mst_b_id_i; + slv_b_resp_o = mst_b_resp_i; + slv_b_user_o = mst_b_user_i; + slv_b_valid_o = mst_b_valid_i; + // Defaults FF + force_wf_d = force_wf_q; + start_wf_d = 1'b0; + b_resp_valid = 1'b0; + // State Machine + b_state_d = b_state_q; + + unique case (b_state_q) + + FEEDTHROUGH_B: begin + if (adapter_ready) begin + if (atop_valid_d == LOAD || atop_valid_d == STORE) begin + // Wait until write is complete + b_state_d = WAIT_COMPLETE_B; + end else if (atop_valid_d == INVALID) begin + // Inject B error resp once the channel is free + if (b_free) begin + // Block downstream + mst_b_ready_o = 1'b0; + // Write B response + slv_b_valid_o = 1'b1; + slv_b_id_o = slv_aw_id_i; + slv_b_resp_o = axi_pkg::RESP_SLVERR; + slv_b_user_o = '0; + if (!slv_b_ready_i) begin + b_state_d = SEND_B; + end + end else begin + b_state_d = WAIT_CHANNEL_B; + end + end + end + end // FEEDTHROUGH_B + + WAIT_CHANNEL_B, SEND_B: begin + if (b_free || (b_state_q == SEND_B)) begin + // Block downstream + mst_b_ready_o = 1'b0; + // Write B response + slv_b_valid_o = 1'b1; + slv_b_id_o = id_q; + slv_b_resp_o = axi_pkg::RESP_SLVERR; + slv_b_user_o = '0; + if (slv_b_ready_i) begin + b_state_d = FEEDTHROUGH_B; + end else begin + b_state_d = SEND_B; + end + end + end // WAIT_CHANNEL_B, SEND_B + + WAIT_COMPLETE_B: begin + if (mst_b_valid_i && (mst_b_id_i == id_q)) begin + // Check if store-conditional was successful + if (mst_b_resp_i == axi_pkg::RESP_OKAY) begin + if (force_wf_q) begin + // We were in wf mode so now we are done + force_wf_d = 1'b0; + b_resp_valid = 1'b1; + b_state_d = FEEDTHROUGH_B; + end else begin + // We were not in wf mode --> catch response + mst_b_ready_o = 1'b1; + slv_b_valid_o = 1'b0; + // Go into wf mode + start_wf_d = 1'b1; + force_wf_d = 1'b1; + end + end else if (mst_b_resp_i == axi_pkg::RESP_EXOKAY) begin + // Modify the B response to regular OK. + b_resp_valid = 1'b1; + slv_b_resp_o = axi_pkg::RESP_OKAY; + if (slv_b_ready_i) begin + b_state_d = FEEDTHROUGH_B; + end + end else begin + b_resp_valid = 1'b1; + b_state_d = FEEDTHROUGH_B; + end + end + end // WAIT_COMPLETE_B + + default: b_state_d = FEEDTHROUGH_B; + + endcase + end // axi_b_channel + + // Keep track of AW requests missing a W and of downstream transactions + always_comb begin + w_cnt_d = w_cnt_q; + aw_trans_d = aw_trans_q; + if (mst_aw_valid_o && mst_aw_ready_i) begin + w_cnt_d += 1; + aw_trans_d += 1; + end + if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_d -= 1; + end + if (mst_b_valid_i && mst_b_ready_o) begin + aw_trans_d -= 1; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : axi_write_channel_ff + if(~rst_ni) begin + aw_state_q <= FEEDTHROUGH_AW; + w_state_q <= FEEDTHROUGH_W; + b_state_q <= FEEDTHROUGH_B; + aw_trans_q <= '0; + w_cnt_q <= '0; + w_cnt_req_q <= '0; + w_cnt_inj_q <= '0; + force_wf_q <= 1'b0; + start_wf_q <= 1'b0; + addr_q <= '0; + id_q <= '0; + size_q <= '0; + strb_q <= '0; + cache_q <= '0; + prot_q <= '0; + qos_q <= '0; + region_q <= '0; + aw_user_q <= '0; + w_user_q <= '0; + w_data_q <= '0; + result_q <= '0; + w_d_valid_q <= '0; + atop_q <= 6'b0; + end else begin + aw_state_q <= aw_state_d; + w_state_q <= w_state_d; + b_state_q <= b_state_d; + aw_trans_q <= aw_trans_d; + w_cnt_q <= w_cnt_d; + w_cnt_req_q <= w_cnt_req_d; + w_cnt_inj_q <= w_cnt_inj_d; + force_wf_q <= force_wf_d; + start_wf_q <= start_wf_d; + addr_q <= addr_d; + id_q <= id_d; + size_q <= size_d; + strb_q <= strb_d; + cache_q <= cache_d; + prot_q <= prot_d; + qos_q <= qos_d; + region_q <= region_d; + aw_user_q <= aw_user_d; + w_user_q <= w_user_d; + w_data_q <= w_data_d; + result_q <= result_d; + w_d_valid_q <= w_d_valid_d; + atop_q <= atop_d; + end + end + + /** + * Read Channel: AR, R + */ + + /*==================================================================== + = AR = + ====================================================================*/ + always_comb begin : axi_ar_channel + // Defaults AXI Bus + mst_ar_id_o = slv_ar_id_i; + mst_ar_addr_o = slv_ar_addr_i; + mst_ar_len_o = slv_ar_len_i; + mst_ar_size_o = slv_ar_size_i; + mst_ar_burst_o = slv_ar_burst_i; + mst_ar_lock_o = slv_ar_lock_i; + mst_ar_cache_o = slv_ar_cache_i; + mst_ar_prot_o = slv_ar_prot_i; + mst_ar_qos_o = slv_ar_qos_i; + mst_ar_region_o = slv_ar_region_i; + mst_ar_user_o = slv_ar_user_i; + mst_ar_valid_o = 1'b0; + slv_ar_ready_o = 1'b0; + // State Machine + ar_state_d = ar_state_q; + + unique case (ar_state_q) + + FEEDTHROUGH_AR: begin + // Feed through + mst_ar_valid_o = slv_ar_valid_i; + slv_ar_ready_o = mst_ar_ready_i; + + if (adapter_ready && (atop_valid_d == LOAD || atop_valid_d == STORE)) begin + if (ar_free) begin + // Acquire channel + slv_ar_ready_o = 1'b0; + // Immediately start read request + mst_ar_valid_o = 1'b1; + mst_ar_addr_o = slv_aw_addr_i; + mst_ar_id_o = slv_aw_id_i; + mst_ar_len_o = 8'h00; + mst_ar_size_o = slv_aw_size_i; + mst_ar_burst_o = 2'b00; + mst_ar_lock_o = ~force_wf_q; + mst_ar_cache_o = slv_aw_cache_i; + mst_ar_prot_o = slv_aw_prot_i; + mst_ar_qos_o = slv_aw_qos_i; + mst_ar_region_o = slv_aw_region_i; + mst_ar_user_o = slv_aw_user_i; + if (!mst_ar_ready_i) begin + // Hold read request but do not depend on AW + ar_state_d = SEND_AR; + end + end else begin + // Wait until AR is free + ar_state_d = WAIT_CHANNEL_AR; + end + end + + if (start_wf_q) begin + ar_state_d = WAIT_CHANNEL_AR; + end + end // FEEDTHROUGH_AR + + WAIT_CHANNEL_AR, SEND_AR: begin + // Issue read request + if ((ar_free && (aw_trans_q == 0 || force_wf_q == 0)) || (ar_state_q == SEND_AR)) begin + // Inject read request + mst_ar_valid_o = 1'b1; + mst_ar_addr_o = addr_q; + mst_ar_id_o = id_q; + mst_ar_len_o = 8'h00; + mst_ar_size_o = size_q; + mst_ar_burst_o = 2'b00; + mst_ar_lock_o = ~force_wf_q; + mst_ar_cache_o = cache_q; + mst_ar_prot_o = prot_q; + mst_ar_qos_o = qos_q; + mst_ar_region_o = region_q; + mst_ar_user_o = aw_user_q; + if (mst_ar_ready_i) begin + // Request acknowledged + ar_state_d = FEEDTHROUGH_AR; + end else begin + // Hold read request + ar_state_d = SEND_AR; + end + end else begin + // Wait until AR is free + mst_ar_valid_o = slv_ar_valid_i; + slv_ar_ready_o = mst_ar_ready_i; + end + end // WAIT_CHANNEL_AR, SEND_AR + + default: ar_state_d = FEEDTHROUGH_AR; + + endcase + end // axi_ar_channel + + /*==================================================================== + = R = + ====================================================================*/ + always_comb begin : axi_r_channel + // Defaults AXI Bus + mst_r_ready_o = slv_r_ready_i; + slv_r_id_o = mst_r_id_i; + slv_r_data_o = mst_r_data_i; + slv_r_resp_o = mst_r_resp_i; + slv_r_last_o = mst_r_last_i; + slv_r_user_o = mst_r_user_i; + slv_r_valid_o = mst_r_valid_i; + // Defaults FF + r_data_d = r_data_q; + r_resp_d = r_resp_q; + r_user_d = r_user_q; + r_d_valid_d = r_d_valid_q; + // State Machine + r_state_d = r_state_q; + + unique case (r_state_q) + + FEEDTHROUGH_R: begin + if (adapter_ready) begin + // Reset read flag + r_d_valid_d = 1'b0; + + if (atop_valid_d == LOAD || atop_valid_d == STORE) begin + // Wait for R response to read data + r_state_d = WAIT_DATA_R; + end else if (atop_valid_d == INVALID) begin + // Send R response once channel is free + if (r_free) begin + // Acquire the R channel + // Block downstream + mst_r_ready_o = 1'b0; + // Send R error response + slv_r_valid_o = 1'b1; + slv_r_data_o = '0; + slv_r_id_o = slv_aw_id_i; + slv_r_last_o = 1'b1; + slv_r_resp_o = axi_pkg::RESP_SLVERR; + slv_r_user_o = '0; + if (!slv_r_ready_i) begin + // Hold R response + r_state_d = SEND_R; + end + end else begin + r_state_d = WAIT_CHANNEL_R; + end + end + end + + if (start_wf_q) begin + r_d_valid_d = 1'b0; + r_state_d = WAIT_DATA_R; + end + end // FEEDTHROUGH_R + + WAIT_DATA_R: begin + // Read data + if (mst_r_valid_i && (mst_r_id_i == id_q)) begin + // Acknowledge downstream and block upstream + mst_r_ready_o = 1'b1; + slv_r_valid_o = 1'b0; + // Store data + r_data_d = mst_r_data_i; + r_resp_d = mst_r_resp_i; + r_user_d = mst_r_user_i; + r_d_valid_d = 1'b1; + if (atop_valid_q == STORE) begin + r_state_d = FEEDTHROUGH_R; + end else begin + // Wait for B resp before injecting R + r_state_d = WAIT_CHANNEL_R; + end + end + end // WAIT_DATA_R + + WAIT_CHANNEL_R, SEND_R: begin + // Wait for the R channel to become free and B response to be valid + if ((r_free && (b_resp_valid || b_state_q != WAIT_COMPLETE_B)) || (r_state_q == SEND_R)) begin + // Block downstream + mst_r_ready_o = 1'b0; + // Send R response + slv_r_valid_o = 1'b1; + slv_r_data_o = r_data_q; + slv_r_id_o = id_q; + slv_r_last_o = 1'b1; + slv_r_resp_o = r_resp_q; + slv_r_user_o = r_user_q; + if (atop_valid_q == INVALID) begin + slv_r_data_o = '0; + slv_r_resp_o = axi_pkg::RESP_SLVERR; + slv_r_user_o = '0; + end + if (slv_r_ready_i) begin + r_state_d = FEEDTHROUGH_R; + end else begin + r_state_d = SEND_R; + end + end + + if (start_wf_q) begin + r_d_valid_d = 1'b0; + r_state_d = WAIT_DATA_R; + end + end // WAIT_CHANNEL_R, SEND_R + + default: r_state_d = FEEDTHROUGH_R; + + endcase + end // axi_r_channel + + always_ff @(posedge clk_i or negedge rst_ni) begin : axi_read_channel_ff + if(~rst_ni) begin + ar_state_q <= FEEDTHROUGH_AR; + r_state_q <= FEEDTHROUGH_R; + r_data_q <= '0; + r_resp_q <= '0; + r_user_q <= '0; + r_d_valid_q <= 1'b0; + end else begin + ar_state_q <= ar_state_d; + r_state_q <= r_state_d; + r_data_q <= r_data_d; + r_resp_q <= r_resp_d; + r_user_q <= r_user_d; + r_d_valid_q <= r_d_valid_d; + end + end + + /** + * ALU + */ + + assign op_a = r_data_q & strb_ext; + assign op_b = w_data_q & strb_ext; + assign sign_a = |(op_a & ~(strb_ext >> 1)); + assign sign_b = |(op_b & ~(strb_ext >> 1)); + assign alu_result_ext = res; + + generate + if (AXI_ALU_RATIO == 1 && RISCV_WORD_WIDTH == 32) begin + assign alu_operand_a = op_a; + assign alu_operand_b = op_b; + assign res = alu_result; + end else if (AXI_ALU_RATIO == 1 && RISCV_WORD_WIDTH == 64) begin + assign res = alu_result; + always_comb begin + op_a_sign_ext = op_a | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_a}} & ~strb_ext); + op_b_sign_ext = op_b | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_b}} & ~strb_ext); + + if (atop_q[2:0] == axi_pkg::ATOP_SMAX || atop_q[2:0] == axi_pkg::ATOP_SMIN) begin + // Sign extend + alu_operand_a = op_a_sign_ext; + alu_operand_b = op_b_sign_ext; + end else begin + // No sign extension necessary + alu_operand_a = op_a; + alu_operand_b = op_b; + end + end + end else begin + always_comb begin + op_a_sign_ext = op_a | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_a}} & ~strb_ext); + op_b_sign_ext = op_b | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_b}} & ~strb_ext); + + if (atop_q[2:0] == axi_pkg::ATOP_SMAX || atop_q[2:0] == axi_pkg::ATOP_SMIN) begin + // Sign extend + alu_operand_a = op_a_sign_ext[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + alu_operand_b = op_b_sign_ext[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + end else begin + // No sign extension necessary + alu_operand_a = op_a[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + alu_operand_b = op_b[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + end + res = '0; + res[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]] = alu_result; + end + end + endgenerate + + generate + for (genvar i = 0; i < AXI_STRB_WIDTH; i++) begin + always_comb begin + if (strb_q[i]) begin + strb_ext[i] = 8'hFF; + end else begin + strb_ext[i] = 8'h00; + end + end + end + endgenerate + + axi_riscv_amos_alu #( + .DATA_WIDTH ( RISCV_WORD_WIDTH ) + ) i_amo_alu ( + .amo_op_i ( atop_q ), + .amo_operand_a_i ( alu_operand_a ), + .amo_operand_b_i ( alu_operand_b ), + .amo_result_o ( alu_result ) + ); + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (AXI_ADDR_WIDTH > 0) + else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!"); + assert (AXI_DATA_WIDTH > 0) + else $fatal(1, "AXI_DATA_WIDTH must be greater than 0!"); + assert (AXI_ID_WIDTH > 0) + else $fatal(1, "AXI_ID_WIDTH must be greater than 0!"); + assert (AXI_MAX_WRITE_TXNS > 0) + else $fatal(1, "AXI_MAX_WRITE_TXNS must be greater than 0!"); + assert (RISCV_WORD_WIDTH == 32 || RISCV_WORD_WIDTH == 64) + else $fatal(1, "RISCV_WORD_WIDTH must be 32 or 64!"); + assert (RISCV_WORD_WIDTH <= AXI_DATA_WIDTH) + else $fatal(1, "RISCV_WORD_WIDTH must not be greater than AXI_DATA_WIDTH!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/axi_riscv_atomics/src/axi_riscv_amos_alu.sv b/hw/deps/axi_riscv_atomics/src/axi_riscv_amos_alu.sv new file mode 100644 index 0000000..40a52b0 --- /dev/null +++ b/hw/deps/axi_riscv_atomics/src/axi_riscv_amos_alu.sv @@ -0,0 +1,78 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V Atomic Operations (AMOs) ALU +module axi_riscv_amos_alu # ( + parameter int unsigned DATA_WIDTH = 0 +) ( + input logic [5:0] amo_op_i, + input logic [DATA_WIDTH-1:0] amo_operand_a_i, + input logic [DATA_WIDTH-1:0] amo_operand_b_i, + output logic [DATA_WIDTH-1:0] amo_result_o +); + + logic [DATA_WIDTH:0] adder_sum; + logic [DATA_WIDTH:0] adder_operand_a, adder_operand_b; + + assign adder_sum = adder_operand_a + adder_operand_b; + + always_comb begin + + adder_operand_a = $signed(amo_operand_a_i); + adder_operand_b = $signed(amo_operand_b_i); + + amo_result_o = amo_operand_a_i; + + if (amo_op_i == axi_pkg::ATOP_ATOMICSWAP) begin + // Swap operation + amo_result_o = amo_operand_b_i; + end else if ((amo_op_i[5:4] == axi_pkg::ATOP_ATOMICLOAD) | (amo_op_i[5:4] == axi_pkg::ATOP_ATOMICSTORE)) begin + // Load operation + unique case (amo_op_i[2:0]) + // the default is to output operand_a + axi_pkg::ATOP_ADD: amo_result_o = adder_sum[DATA_WIDTH-1:0]; + axi_pkg::ATOP_CLR: amo_result_o = amo_operand_a_i & (~amo_operand_b_i); + axi_pkg::ATOP_SET: amo_result_o = amo_operand_a_i | amo_operand_b_i; + axi_pkg::ATOP_EOR: amo_result_o = amo_operand_a_i ^ amo_operand_b_i; + axi_pkg::ATOP_SMAX: begin + adder_operand_b = -$signed(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_b_i : amo_operand_a_i; + end + axi_pkg::ATOP_SMIN: begin + adder_operand_b = -$signed(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_a_i : amo_operand_b_i; + end + axi_pkg::ATOP_UMAX: begin + adder_operand_a = $unsigned(amo_operand_a_i); + adder_operand_b = -$unsigned(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_b_i : amo_operand_a_i; + end + axi_pkg::ATOP_UMIN: begin + adder_operand_a = $unsigned(amo_operand_a_i); + adder_operand_b = -$unsigned(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_a_i : amo_operand_b_i; + end + default: amo_result_o = '0; + endcase + end + end + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (DATA_WIDTH > 0) + else $fatal(1, "DATA_WIDTH must be greater than 0!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/axi_riscv_atomics/src/axi_riscv_atomics.sv b/hw/deps/axi_riscv_atomics/src/axi_riscv_atomics.sv new file mode 100644 index 0000000..464f3a0 --- /dev/null +++ b/hw/deps/axi_riscv_atomics/src/axi_riscv_atomics.sv @@ -0,0 +1,404 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V Atomics ("A" Extension) Adapter +// +// This AXI adapter implements the RISC-V "A" extension and adheres to the RVWMO memory consistency +// model. +// +// Maintainer: Andreas Kurth + +module axi_riscv_atomics #( + /// AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + // Maximum number of AXI read bursts outstanding at the same time + parameter int unsigned AXI_MAX_READ_TXNS = 0, + // Maximum number of AXI write bursts outstanding at the same time + parameter int unsigned AXI_MAX_WRITE_TXNS = 0, + // Word width of the widest RISC-V processor that can issue requests to this module. + // 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are + // supported if `aw_strb` is set correctly. + parameter int unsigned RISCV_WORD_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + + /// Slave Interface + input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i, + input logic [2:0] slv_aw_prot_i, + input logic [3:0] slv_aw_region_i, + input logic [5:0] slv_aw_atop_i, + input logic [7:0] slv_aw_len_i, + input logic [2:0] slv_aw_size_i, + input logic [1:0] slv_aw_burst_i, + input logic slv_aw_lock_i, + input logic [3:0] slv_aw_cache_i, + input logic [3:0] slv_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i, + output logic slv_aw_ready_o, + input logic slv_aw_valid_i, + + input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i, + input logic [2:0] slv_ar_prot_i, + input logic [3:0] slv_ar_region_i, + input logic [7:0] slv_ar_len_i, + input logic [2:0] slv_ar_size_i, + input logic [1:0] slv_ar_burst_i, + input logic slv_ar_lock_i, + input logic [3:0] slv_ar_cache_i, + input logic [3:0] slv_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i, + output logic slv_ar_ready_o, + input logic slv_ar_valid_i, + + input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] slv_w_user_i, + input logic slv_w_last_i, + output logic slv_w_ready_o, + input logic slv_w_valid_i, + + output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o, + output logic [1:0] slv_r_resp_o, + output logic slv_r_last_o, + output logic [AXI_ID_WIDTH-1:0] slv_r_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_r_user_o, + input logic slv_r_ready_i, + output logic slv_r_valid_o, + + output logic [1:0] slv_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] slv_b_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_b_user_o, + input logic slv_b_ready_i, + output logic slv_b_valid_o, + + /// Master Interface + output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o, + output logic [2:0] mst_aw_prot_o, + output logic [3:0] mst_aw_region_o, + output logic [5:0] mst_aw_atop_o, + output logic [7:0] mst_aw_len_o, + output logic [2:0] mst_aw_size_o, + output logic [1:0] mst_aw_burst_o, + output logic mst_aw_lock_o, + output logic [3:0] mst_aw_cache_o, + output logic [3:0] mst_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o, + input logic mst_aw_ready_i, + output logic mst_aw_valid_o, + + output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o, + output logic [2:0] mst_ar_prot_o, + output logic [3:0] mst_ar_region_o, + output logic [7:0] mst_ar_len_o, + output logic [2:0] mst_ar_size_o, + output logic [1:0] mst_ar_burst_o, + output logic mst_ar_lock_o, + output logic [3:0] mst_ar_cache_o, + output logic [3:0] mst_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o, + input logic mst_ar_ready_i, + output logic mst_ar_valid_o, + + output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] mst_w_user_o, + output logic mst_w_last_o, + input logic mst_w_ready_i, + output logic mst_w_valid_o, + + input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i, + input logic [1:0] mst_r_resp_i, + input logic mst_r_last_i, + input logic [AXI_ID_WIDTH-1:0] mst_r_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_r_user_i, + output logic mst_r_ready_o, + input logic mst_r_valid_i, + + input logic [1:0] mst_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] mst_b_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_b_user_i, + output logic mst_b_ready_o, + input logic mst_b_valid_i +); + + // Make the entire address range exclusively accessible. Since the AMO adapter does not support + // address ranges, it would not make sense to expose the address range as a parameter of this + // module. + localparam longint unsigned ADDR_BEGIN = '0; + localparam longint unsigned ADDR_END = {AXI_ADDR_WIDTH{1'b1}}; + + logic [AXI_ADDR_WIDTH-1:0] int_axi_aw_addr; + logic [2:0] int_axi_aw_prot; + logic [3:0] int_axi_aw_region; + logic [5:0] int_axi_aw_atop; + logic [7:0] int_axi_aw_len; + logic [2:0] int_axi_aw_size; + logic [1:0] int_axi_aw_burst; + logic int_axi_aw_lock; + logic [3:0] int_axi_aw_cache; + logic [3:0] int_axi_aw_qos; + logic [AXI_ID_WIDTH-1:0] int_axi_aw_id; + logic [AXI_USER_WIDTH-1:0] int_axi_aw_user; + logic int_axi_aw_ready; + logic int_axi_aw_valid; + + logic [AXI_ADDR_WIDTH-1:0] int_axi_ar_addr; + logic [2:0] int_axi_ar_prot; + logic [3:0] int_axi_ar_region; + logic [7:0] int_axi_ar_len; + logic [2:0] int_axi_ar_size; + logic [1:0] int_axi_ar_burst; + logic int_axi_ar_lock; + logic [3:0] int_axi_ar_cache; + logic [3:0] int_axi_ar_qos; + logic [AXI_ID_WIDTH-1:0] int_axi_ar_id; + logic [AXI_USER_WIDTH-1:0] int_axi_ar_user; + logic int_axi_ar_ready; + logic int_axi_ar_valid; + + logic [AXI_DATA_WIDTH-1:0] int_axi_w_data; + logic [AXI_STRB_WIDTH-1:0] int_axi_w_strb; + logic [AXI_USER_WIDTH-1:0] int_axi_w_user; + logic int_axi_w_last; + logic int_axi_w_ready; + logic int_axi_w_valid; + + logic [AXI_DATA_WIDTH-1:0] int_axi_r_data; + logic [1:0] int_axi_r_resp; + logic int_axi_r_last; + logic [AXI_ID_WIDTH-1:0] int_axi_r_id; + logic [AXI_USER_WIDTH-1:0] int_axi_r_user; + logic int_axi_r_ready; + logic int_axi_r_valid; + + logic [1:0] int_axi_b_resp; + logic [AXI_ID_WIDTH-1:0] int_axi_b_id; + logic [AXI_USER_WIDTH-1:0] int_axi_b_user; + logic int_axi_b_ready; + logic int_axi_b_valid; + + axi_riscv_amos #( + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH), + .AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS), + .RISCV_WORD_WIDTH (RISCV_WORD_WIDTH) + ) i_amos ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_aw_addr_i ( slv_aw_addr_i ), + .slv_aw_prot_i ( slv_aw_prot_i ), + .slv_aw_region_i ( slv_aw_region_i ), + .slv_aw_atop_i ( slv_aw_atop_i ), + .slv_aw_len_i ( slv_aw_len_i ), + .slv_aw_size_i ( slv_aw_size_i ), + .slv_aw_burst_i ( slv_aw_burst_i ), + .slv_aw_lock_i ( slv_aw_lock_i ), + .slv_aw_cache_i ( slv_aw_cache_i ), + .slv_aw_qos_i ( slv_aw_qos_i ), + .slv_aw_id_i ( slv_aw_id_i ), + .slv_aw_user_i ( slv_aw_user_i ), + .slv_aw_ready_o ( slv_aw_ready_o ), + .slv_aw_valid_i ( slv_aw_valid_i ), + .slv_ar_addr_i ( slv_ar_addr_i ), + .slv_ar_prot_i ( slv_ar_prot_i ), + .slv_ar_region_i ( slv_ar_region_i ), + .slv_ar_len_i ( slv_ar_len_i ), + .slv_ar_size_i ( slv_ar_size_i ), + .slv_ar_burst_i ( slv_ar_burst_i ), + .slv_ar_lock_i ( slv_ar_lock_i ), + .slv_ar_cache_i ( slv_ar_cache_i ), + .slv_ar_qos_i ( slv_ar_qos_i ), + .slv_ar_id_i ( slv_ar_id_i ), + .slv_ar_user_i ( slv_ar_user_i ), + .slv_ar_ready_o ( slv_ar_ready_o ), + .slv_ar_valid_i ( slv_ar_valid_i ), + .slv_w_data_i ( slv_w_data_i ), + .slv_w_strb_i ( slv_w_strb_i ), + .slv_w_user_i ( slv_w_user_i ), + .slv_w_last_i ( slv_w_last_i ), + .slv_w_ready_o ( slv_w_ready_o ), + .slv_w_valid_i ( slv_w_valid_i ), + .slv_r_data_o ( slv_r_data_o ), + .slv_r_resp_o ( slv_r_resp_o ), + .slv_r_last_o ( slv_r_last_o ), + .slv_r_id_o ( slv_r_id_o ), + .slv_r_user_o ( slv_r_user_o ), + .slv_r_ready_i ( slv_r_ready_i ), + .slv_r_valid_o ( slv_r_valid_o ), + .slv_b_resp_o ( slv_b_resp_o ), + .slv_b_id_o ( slv_b_id_o ), + .slv_b_user_o ( slv_b_user_o ), + .slv_b_ready_i ( slv_b_ready_i ), + .slv_b_valid_o ( slv_b_valid_o ), + .mst_aw_addr_o ( int_axi_aw_addr ), + .mst_aw_prot_o ( int_axi_aw_prot ), + .mst_aw_region_o ( int_axi_aw_region ), + .mst_aw_atop_o ( int_axi_aw_atop ), + .mst_aw_len_o ( int_axi_aw_len ), + .mst_aw_size_o ( int_axi_aw_size ), + .mst_aw_burst_o ( int_axi_aw_burst ), + .mst_aw_lock_o ( int_axi_aw_lock ), + .mst_aw_cache_o ( int_axi_aw_cache ), + .mst_aw_qos_o ( int_axi_aw_qos ), + .mst_aw_id_o ( int_axi_aw_id ), + .mst_aw_user_o ( int_axi_aw_user ), + .mst_aw_ready_i ( int_axi_aw_ready ), + .mst_aw_valid_o ( int_axi_aw_valid ), + .mst_ar_addr_o ( int_axi_ar_addr ), + .mst_ar_prot_o ( int_axi_ar_prot ), + .mst_ar_region_o ( int_axi_ar_region ), + .mst_ar_len_o ( int_axi_ar_len ), + .mst_ar_size_o ( int_axi_ar_size ), + .mst_ar_burst_o ( int_axi_ar_burst ), + .mst_ar_lock_o ( int_axi_ar_lock ), + .mst_ar_cache_o ( int_axi_ar_cache ), + .mst_ar_qos_o ( int_axi_ar_qos ), + .mst_ar_id_o ( int_axi_ar_id ), + .mst_ar_user_o ( int_axi_ar_user ), + .mst_ar_ready_i ( int_axi_ar_ready ), + .mst_ar_valid_o ( int_axi_ar_valid ), + .mst_w_data_o ( int_axi_w_data ), + .mst_w_strb_o ( int_axi_w_strb ), + .mst_w_user_o ( int_axi_w_user ), + .mst_w_last_o ( int_axi_w_last ), + .mst_w_ready_i ( int_axi_w_ready ), + .mst_w_valid_o ( int_axi_w_valid ), + .mst_r_data_i ( int_axi_r_data ), + .mst_r_resp_i ( int_axi_r_resp ), + .mst_r_last_i ( int_axi_r_last ), + .mst_r_id_i ( int_axi_r_id ), + .mst_r_user_i ( int_axi_r_user ), + .mst_r_ready_o ( int_axi_r_ready ), + .mst_r_valid_i ( int_axi_r_valid ), + .mst_b_resp_i ( int_axi_b_resp ), + .mst_b_id_i ( int_axi_b_id ), + .mst_b_user_i ( int_axi_b_user ), + .mst_b_ready_o ( int_axi_b_ready ), + .mst_b_valid_i ( int_axi_b_valid ) + ); + + axi_riscv_lrsc #( + .ADDR_BEGIN (ADDR_BEGIN), + .ADDR_END (ADDR_END), + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH), + .AXI_MAX_READ_TXNS (AXI_MAX_READ_TXNS), + .AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS) + ) i_lrsc ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_aw_addr_i ( int_axi_aw_addr ), + .slv_aw_prot_i ( int_axi_aw_prot ), + .slv_aw_region_i ( int_axi_aw_region ), + .slv_aw_atop_i ( int_axi_aw_atop ), + .slv_aw_len_i ( int_axi_aw_len ), + .slv_aw_size_i ( int_axi_aw_size ), + .slv_aw_burst_i ( int_axi_aw_burst ), + .slv_aw_lock_i ( int_axi_aw_lock ), + .slv_aw_cache_i ( int_axi_aw_cache ), + .slv_aw_qos_i ( int_axi_aw_qos ), + .slv_aw_id_i ( int_axi_aw_id ), + .slv_aw_user_i ( int_axi_aw_user ), + .slv_aw_ready_o ( int_axi_aw_ready ), + .slv_aw_valid_i ( int_axi_aw_valid ), + .slv_ar_addr_i ( int_axi_ar_addr ), + .slv_ar_prot_i ( int_axi_ar_prot ), + .slv_ar_region_i ( int_axi_ar_region ), + .slv_ar_len_i ( int_axi_ar_len ), + .slv_ar_size_i ( int_axi_ar_size ), + .slv_ar_burst_i ( int_axi_ar_burst ), + .slv_ar_lock_i ( int_axi_ar_lock ), + .slv_ar_cache_i ( int_axi_ar_cache ), + .slv_ar_qos_i ( int_axi_ar_qos ), + .slv_ar_id_i ( int_axi_ar_id ), + .slv_ar_user_i ( int_axi_ar_user ), + .slv_ar_ready_o ( int_axi_ar_ready ), + .slv_ar_valid_i ( int_axi_ar_valid ), + .slv_w_data_i ( int_axi_w_data ), + .slv_w_strb_i ( int_axi_w_strb ), + .slv_w_user_i ( int_axi_w_user ), + .slv_w_last_i ( int_axi_w_last ), + .slv_w_ready_o ( int_axi_w_ready ), + .slv_w_valid_i ( int_axi_w_valid ), + .slv_r_data_o ( int_axi_r_data ), + .slv_r_resp_o ( int_axi_r_resp ), + .slv_r_last_o ( int_axi_r_last ), + .slv_r_id_o ( int_axi_r_id ), + .slv_r_user_o ( int_axi_r_user ), + .slv_r_ready_i ( int_axi_r_ready ), + .slv_r_valid_o ( int_axi_r_valid ), + .slv_b_resp_o ( int_axi_b_resp ), + .slv_b_id_o ( int_axi_b_id ), + .slv_b_user_o ( int_axi_b_user ), + .slv_b_ready_i ( int_axi_b_ready ), + .slv_b_valid_o ( int_axi_b_valid ), + .mst_aw_addr_o ( mst_aw_addr_o ), + .mst_aw_prot_o ( mst_aw_prot_o ), + .mst_aw_region_o ( mst_aw_region_o ), + .mst_aw_atop_o ( mst_aw_atop_o ), + .mst_aw_len_o ( mst_aw_len_o ), + .mst_aw_size_o ( mst_aw_size_o ), + .mst_aw_burst_o ( mst_aw_burst_o ), + .mst_aw_lock_o ( mst_aw_lock_o ), + .mst_aw_cache_o ( mst_aw_cache_o ), + .mst_aw_qos_o ( mst_aw_qos_o ), + .mst_aw_id_o ( mst_aw_id_o ), + .mst_aw_user_o ( mst_aw_user_o ), + .mst_aw_ready_i ( mst_aw_ready_i ), + .mst_aw_valid_o ( mst_aw_valid_o ), + .mst_ar_addr_o ( mst_ar_addr_o ), + .mst_ar_prot_o ( mst_ar_prot_o ), + .mst_ar_region_o ( mst_ar_region_o ), + .mst_ar_len_o ( mst_ar_len_o ), + .mst_ar_size_o ( mst_ar_size_o ), + .mst_ar_burst_o ( mst_ar_burst_o ), + .mst_ar_lock_o ( mst_ar_lock_o ), + .mst_ar_cache_o ( mst_ar_cache_o ), + .mst_ar_qos_o ( mst_ar_qos_o ), + .mst_ar_id_o ( mst_ar_id_o ), + .mst_ar_user_o ( mst_ar_user_o ), + .mst_ar_ready_i ( mst_ar_ready_i ), + .mst_ar_valid_o ( mst_ar_valid_o ), + .mst_w_data_o ( mst_w_data_o ), + .mst_w_strb_o ( mst_w_strb_o ), + .mst_w_user_o ( mst_w_user_o ), + .mst_w_last_o ( mst_w_last_o ), + .mst_w_ready_i ( mst_w_ready_i ), + .mst_w_valid_o ( mst_w_valid_o ), + .mst_r_data_i ( mst_r_data_i ), + .mst_r_resp_i ( mst_r_resp_i ), + .mst_r_last_i ( mst_r_last_i ), + .mst_r_id_i ( mst_r_id_i ), + .mst_r_user_i ( mst_r_user_i ), + .mst_r_ready_o ( mst_r_ready_o ), + .mst_r_valid_i ( mst_r_valid_i ), + .mst_b_resp_i ( mst_b_resp_i ), + .mst_b_id_i ( mst_b_id_i ), + .mst_b_user_i ( mst_b_user_i ), + .mst_b_ready_o ( mst_b_ready_o ), + .mst_b_valid_i ( mst_b_valid_i ) + ); + +endmodule diff --git a/hw/deps/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv b/hw/deps/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv new file mode 100644 index 0000000..024f5d5 --- /dev/null +++ b/hw/deps/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv @@ -0,0 +1,154 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Wrapper for the AXI RISC-V Atomics Adapter that exposes AXI SystemVerilog interfaces. +// +// See the header of `axi_riscv_atomics` for a description. +// +// Maintainer: Andreas Kurth + +module axi_riscv_atomics_wrap #( + /// AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + // Maximum number of AXI read bursts outstanding at the same time + parameter int unsigned AXI_MAX_READ_TXNS = 0, + // Maximum number of AXI write bursts outstanding at the same time + parameter int unsigned AXI_MAX_WRITE_TXNS = 0, + // Word width of the widest RISC-V processor that can issue requests to this module. + // 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are + // supported if `aw_strb` is set correctly. + parameter int unsigned RISCV_WORD_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Master mst, + AXI_BUS.Slave slv +); + + axi_riscv_atomics #( + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH), + .AXI_MAX_READ_TXNS (AXI_MAX_READ_TXNS), + .AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS), + .RISCV_WORD_WIDTH (RISCV_WORD_WIDTH) + ) i_atomics ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_aw_addr_i ( slv.aw_addr ), + .slv_aw_prot_i ( slv.aw_prot ), + .slv_aw_region_i ( slv.aw_region ), + .slv_aw_atop_i ( slv.aw_atop ), + .slv_aw_len_i ( slv.aw_len ), + .slv_aw_size_i ( slv.aw_size ), + .slv_aw_burst_i ( slv.aw_burst ), + .slv_aw_lock_i ( slv.aw_lock ), + .slv_aw_cache_i ( slv.aw_cache ), + .slv_aw_qos_i ( slv.aw_qos ), + .slv_aw_id_i ( slv.aw_id ), + .slv_aw_user_i ( slv.aw_user ), + .slv_aw_ready_o ( slv.aw_ready ), + .slv_aw_valid_i ( slv.aw_valid ), + .slv_ar_addr_i ( slv.ar_addr ), + .slv_ar_prot_i ( slv.ar_prot ), + .slv_ar_region_i ( slv.ar_region ), + .slv_ar_len_i ( slv.ar_len ), + .slv_ar_size_i ( slv.ar_size ), + .slv_ar_burst_i ( slv.ar_burst ), + .slv_ar_lock_i ( slv.ar_lock ), + .slv_ar_cache_i ( slv.ar_cache ), + .slv_ar_qos_i ( slv.ar_qos ), + .slv_ar_id_i ( slv.ar_id ), + .slv_ar_user_i ( slv.ar_user ), + .slv_ar_ready_o ( slv.ar_ready ), + .slv_ar_valid_i ( slv.ar_valid ), + .slv_w_data_i ( slv.w_data ), + .slv_w_strb_i ( slv.w_strb ), + .slv_w_user_i ( slv.w_user ), + .slv_w_last_i ( slv.w_last ), + .slv_w_ready_o ( slv.w_ready ), + .slv_w_valid_i ( slv.w_valid ), + .slv_r_data_o ( slv.r_data ), + .slv_r_resp_o ( slv.r_resp ), + .slv_r_last_o ( slv.r_last ), + .slv_r_id_o ( slv.r_id ), + .slv_r_user_o ( slv.r_user ), + .slv_r_ready_i ( slv.r_ready ), + .slv_r_valid_o ( slv.r_valid ), + .slv_b_resp_o ( slv.b_resp ), + .slv_b_id_o ( slv.b_id ), + .slv_b_user_o ( slv.b_user ), + .slv_b_ready_i ( slv.b_ready ), + .slv_b_valid_o ( slv.b_valid ), + .mst_aw_addr_o ( mst.aw_addr ), + .mst_aw_prot_o ( mst.aw_prot ), + .mst_aw_region_o ( mst.aw_region ), + .mst_aw_atop_o ( mst.aw_atop ), + .mst_aw_len_o ( mst.aw_len ), + .mst_aw_size_o ( mst.aw_size ), + .mst_aw_burst_o ( mst.aw_burst ), + .mst_aw_lock_o ( mst.aw_lock ), + .mst_aw_cache_o ( mst.aw_cache ), + .mst_aw_qos_o ( mst.aw_qos ), + .mst_aw_id_o ( mst.aw_id ), + .mst_aw_user_o ( mst.aw_user ), + .mst_aw_ready_i ( mst.aw_ready ), + .mst_aw_valid_o ( mst.aw_valid ), + .mst_ar_addr_o ( mst.ar_addr ), + .mst_ar_prot_o ( mst.ar_prot ), + .mst_ar_region_o ( mst.ar_region ), + .mst_ar_len_o ( mst.ar_len ), + .mst_ar_size_o ( mst.ar_size ), + .mst_ar_burst_o ( mst.ar_burst ), + .mst_ar_lock_o ( mst.ar_lock ), + .mst_ar_cache_o ( mst.ar_cache ), + .mst_ar_qos_o ( mst.ar_qos ), + .mst_ar_id_o ( mst.ar_id ), + .mst_ar_user_o ( mst.ar_user ), + .mst_ar_ready_i ( mst.ar_ready ), + .mst_ar_valid_o ( mst.ar_valid ), + .mst_w_data_o ( mst.w_data ), + .mst_w_strb_o ( mst.w_strb ), + .mst_w_user_o ( mst.w_user ), + .mst_w_last_o ( mst.w_last ), + .mst_w_ready_i ( mst.w_ready ), + .mst_w_valid_o ( mst.w_valid ), + .mst_r_data_i ( mst.r_data ), + .mst_r_resp_i ( mst.r_resp ), + .mst_r_last_i ( mst.r_last ), + .mst_r_id_i ( mst.r_id ), + .mst_r_user_i ( mst.r_user ), + .mst_r_ready_o ( mst.r_ready ), + .mst_r_valid_i ( mst.r_valid ), + .mst_b_resp_i ( mst.b_resp ), + .mst_b_id_i ( mst.b_id ), + .mst_b_user_i ( mst.b_user ), + .mst_b_ready_o ( mst.b_ready ), + .mst_b_valid_i ( mst.b_valid ) + ); + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (AXI_STRB_WIDTH == AXI_DATA_WIDTH/8) + else $fatal(1, "AXI_STRB_WIDTH must equal AXI_DATA_WIDTH/8!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/axi_riscv_atomics/src/axi_riscv_lrsc.sv b/hw/deps/axi_riscv_atomics/src/axi_riscv_lrsc.sv new file mode 100644 index 0000000..2c5df0e --- /dev/null +++ b/hw/deps/axi_riscv_atomics/src/axi_riscv_lrsc.sv @@ -0,0 +1,987 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V LR/SC Adapter +// +// This adapter adds support for AXI4 exclusive accesses to a slave that natively does not support +// exclusive accesses. It is to be placed between that slave and the upstream master port, so that +// the `mst` port of this module drives the slave and the `slv` port of this module is driven by +// the upstream master. +// +// Exclusive accesses are only enabled for a range of addresses specified through parameters. All +// addresses within that range are guaranteed to fulfill the constraints described in A7.2 of the +// AXI4 standard, both for normal and exclusive memory accesses. Addresses outside that range +// behave like a slave that does not support exclusive memory accesses (see AXI4, A7.2.5). +// +// Limitations: +// - The adapter does not support bursts in exclusive accessing. Only single words can be +// reserved. +// +// Maintainer: Andreas Kurth + +module axi_riscv_lrsc #( + /// Exclusively-accessible address range (closed interval from ADDR_BEGIN to ADDR_END) + parameter longint unsigned ADDR_BEGIN = 0, + parameter longint unsigned ADDR_END = 0, + /// AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned AXI_MAX_READ_TXNS = 0, // Maximum number of in-flight read transactions + parameter int unsigned AXI_MAX_WRITE_TXNS = 0, // Maximum number of in-flight write transactions + /// Enable debug prints (not synthesizable). + parameter bit DEBUG = 1'b0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + + /// Slave Interface + input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i, + input logic [2:0] slv_aw_prot_i, + input logic [3:0] slv_aw_region_i, + input logic [5:0] slv_aw_atop_i, + input logic [7:0] slv_aw_len_i, + input logic [2:0] slv_aw_size_i, + input logic [1:0] slv_aw_burst_i, + input logic slv_aw_lock_i, + input logic [3:0] slv_aw_cache_i, + input logic [3:0] slv_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i, + output logic slv_aw_ready_o, + input logic slv_aw_valid_i, + + input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i, + input logic [2:0] slv_ar_prot_i, + input logic [3:0] slv_ar_region_i, + input logic [7:0] slv_ar_len_i, + input logic [2:0] slv_ar_size_i, + input logic [1:0] slv_ar_burst_i, + input logic slv_ar_lock_i, + input logic [3:0] slv_ar_cache_i, + input logic [3:0] slv_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i, + output logic slv_ar_ready_o, + input logic slv_ar_valid_i, + + input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] slv_w_user_i, + input logic slv_w_last_i, + output logic slv_w_ready_o, + input logic slv_w_valid_i, + + output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o, + output logic [1:0] slv_r_resp_o, + output logic slv_r_last_o, + output logic [AXI_ID_WIDTH-1:0] slv_r_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_r_user_o, + input logic slv_r_ready_i, + output logic slv_r_valid_o, + + output logic [1:0] slv_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] slv_b_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_b_user_o, + input logic slv_b_ready_i, + output logic slv_b_valid_o, + + /// Master Interface + output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o, + output logic [2:0] mst_aw_prot_o, + output logic [3:0] mst_aw_region_o, + output logic [5:0] mst_aw_atop_o, + output logic [7:0] mst_aw_len_o, + output logic [2:0] mst_aw_size_o, + output logic [1:0] mst_aw_burst_o, + output logic mst_aw_lock_o, + output logic [3:0] mst_aw_cache_o, + output logic [3:0] mst_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o, + input logic mst_aw_ready_i, + output logic mst_aw_valid_o, + + output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o, + output logic [2:0] mst_ar_prot_o, + output logic [3:0] mst_ar_region_o, + output logic [7:0] mst_ar_len_o, + output logic [2:0] mst_ar_size_o, + output logic [1:0] mst_ar_burst_o, + output logic mst_ar_lock_o, + output logic [3:0] mst_ar_cache_o, + output logic [3:0] mst_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o, + input logic mst_ar_ready_i, + output logic mst_ar_valid_o, + + output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] mst_w_user_o, + output logic mst_w_last_o, + input logic mst_w_ready_i, + output logic mst_w_valid_o, + + input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i, + input logic [1:0] mst_r_resp_i, + input logic mst_r_last_i, + input logic [AXI_ID_WIDTH-1:0] mst_r_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_r_user_i, + output logic mst_r_ready_o, + input logic mst_r_valid_i, + + input logic [1:0] mst_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] mst_b_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_b_user_i, + output logic mst_b_ready_o, + input logic mst_b_valid_i +); + + // Declarations of Signals and Types + + typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] axi_data_t; + typedef logic [AXI_ID_WIDTH-1:0] axi_id_t; + typedef logic [1:0] axi_resp_t; + typedef logic [AXI_USER_WIDTH-1:0] axi_user_t; + typedef logic [AXI_ADDR_WIDTH-3:0] res_addr_t; // Track reservations word wise. + + typedef enum logic [1:0] { + B_U='x, B_REGULAR='0, B_EXCLUSIVE, B_INJECT + } b_cmd_t; + + typedef struct packed { + axi_id_t id; + axi_user_t user; + } b_inj_t; + + typedef struct packed { + axi_id_t id; + axi_user_t user; + axi_resp_t resp; + } b_chan_t; + + typedef struct packed { + axi_id_t id; + axi_data_t data; + axi_resp_t resp; + axi_user_t user; + logic last; + } r_chan_t; + + typedef struct packed { + logic excl; + } r_flight_t; + + typedef struct packed { + logic forward; + axi_id_t id; + axi_user_t user; + } w_cmd_t; + + typedef struct packed { + res_addr_t addr; + logic excl; + } w_flight_t; + + typedef struct packed { + w_flight_t data; + logic [$bits(w_flight_t)-1:0] mask; + } wifq_exists_t; + + typedef enum logic { + AR_IDLE, AR_WAIT + } ar_state_t; + + typedef enum logic { + AW_IDLE, AW_WAIT + } aw_state_t; + + typedef struct packed { + axi_addr_t addr; + logic [2:0] prot; + logic [3:0] region; + logic [5:0] atop; + logic [7:0] len; + logic [2:0] size; + logic [1:0] burst; + logic [3:0] cache; + logic [3:0] qos; + axi_id_t id; + axi_user_t user; + } aw_chan_t; + + typedef enum logic { + B_NORMAL, B_FORWARD + } b_state_t; + + axi_id_t ar_push_id, + art_check_id, + b_status_inp_id, + b_status_oup_id, + rifq_oup_id; + + res_addr_t ar_push_addr, + art_check_clr_addr; + + logic ar_push_excl, + ar_push_res; + + logic art_check_clr_excl; + + logic ar_push_valid, ar_push_ready, + art_check_clr_req, art_check_clr_gnt, + art_filter_valid, art_filter_ready, + art_set_req, art_set_gnt; + + logic rifq_inp_req, rifq_inp_gnt, + rifq_oup_req, rifq_oup_gnt, + rifq_oup_pop, + rifq_oup_data_valid; + + r_flight_t rifq_inp_data, + rifq_oup_data; + + logic wifq_exists, + ar_wifq_exists_req, ar_wifq_exists_gnt, + aw_wifq_exists_req, aw_wifq_exists_gnt, + wifq_exists_req, wifq_exists_gnt, + wifq_inp_gnt, + wifq_oup_req, wifq_oup_gnt, + wifq_oup_data_valid; + + wifq_exists_t ar_wifq_exists_inp, + aw_wifq_exists_inp, + wifq_exists_inp; + + b_chan_t slv_b; + + logic slv_b_valid, slv_b_ready; + + r_chan_t slv_r; + + logic slv_r_valid, slv_r_ready; + + logic mst_b_valid, mst_b_ready; + + w_cmd_t w_cmd_inp, w_cmd_oup; + + logic w_cmd_push, w_cmd_pop, + w_cmd_full, w_cmd_empty; + + b_inj_t b_inj_inp, b_inj_oup; + + logic b_inj_push, b_inj_pop, + b_inj_full, b_inj_empty; + + b_cmd_t b_status_inp_cmd, b_status_oup_cmd; + + logic b_status_inp_req, b_status_oup_req, + b_status_inp_gnt, b_status_oup_gnt, + b_status_oup_pop, + b_status_oup_valid; + + logic art_check_res; + + ar_state_t ar_state_d, ar_state_q; + + aw_state_t aw_state_d, aw_state_q; + + b_state_t b_state_d, b_state_q; + + aw_chan_t slv_aw, mst_aw; + + logic mst_aw_valid, mst_aw_ready; + + // AR and R Channel + + // IQ Queue to track in-flight reads + id_queue #( + .ID_WIDTH (AXI_ID_WIDTH), + .CAPACITY (AXI_MAX_READ_TXNS), + .data_t (r_flight_t) + ) i_read_in_flight_queue ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .inp_id_i (ar_push_id), + .inp_data_i (rifq_inp_data), + .inp_req_i (rifq_inp_req), + .inp_gnt_o (rifq_inp_gnt), + .exists_data_i (), + .exists_mask_i (), + .exists_req_i (1'b0), + .exists_o (), + .exists_gnt_o (), + .oup_id_i (rifq_oup_id), + .oup_pop_i (rifq_oup_pop), + .oup_req_i (rifq_oup_req), + .oup_data_o (rifq_oup_data), + .oup_data_valid_o (rifq_oup_data_valid), + .oup_gnt_o (rifq_oup_gnt) + ); + assign rifq_inp_data.excl = ar_push_excl; + + // Fork requests from AR into reservation table and queue of in-flight reads. + stream_fork #( + .N_OUP (2) + ) i_ar_push_fork ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .valid_i (ar_push_valid), + .ready_o (ar_push_ready), + .valid_o ({art_filter_valid, rifq_inp_req}), + .ready_i ({art_filter_ready, rifq_inp_gnt}) + ); + + stream_filter i_art_filter ( + .valid_i (art_filter_valid), + .ready_o (art_filter_ready), + .drop_i (!ar_push_res), + .valid_o (art_set_req), + .ready_i (art_set_gnt) + ); + + // Time-Invariant Signal Assignments + assign mst_ar_addr_o = slv_ar_addr_i; + assign mst_ar_prot_o = slv_ar_prot_i; + assign mst_ar_region_o = slv_ar_region_i; + assign mst_ar_len_o = slv_ar_len_i; + assign mst_ar_size_o = slv_ar_size_i; + assign mst_ar_burst_o = slv_ar_burst_i; + assign mst_ar_lock_o = 1'b0; + assign mst_ar_cache_o = slv_ar_cache_i; + assign mst_ar_qos_o = slv_ar_qos_i; + assign mst_ar_id_o = slv_ar_id_i; + assign mst_ar_user_o = slv_ar_user_i; + assign slv_r.data = mst_r_data_i; + assign slv_r.last = mst_r_last_i; + assign slv_r.id = mst_r_id_i; + assign slv_r.user = mst_r_user_i; + + // Control R Channel + always_comb begin + mst_r_ready_o = 1'b0; + slv_r.resp = 'x; + slv_r_valid = 1'b0; + rifq_oup_id = 'x; + rifq_oup_pop = 1'b0; + rifq_oup_req = 1'b0; + if (mst_r_valid_i && slv_r_ready) begin + rifq_oup_id = mst_r_id_i; + rifq_oup_pop = mst_r_last_i; + rifq_oup_req = 1'b1; + if (rifq_oup_gnt) begin + mst_r_ready_o = 1'b1; + if (mst_r_resp_i[1] == 1'b0) begin + slv_r.resp = {1'b0, rifq_oup_data.excl}; + end else begin + slv_r.resp = mst_r_resp_i; + end + slv_r_valid = 1'b1; + end + end + end + +// pragma translate_off + always @(posedge clk_i) begin + if (~rst_ni) begin + if (rifq_oup_req && rifq_oup_gnt) begin + assert (rifq_oup_data_valid) else $error("Unexpected R with ID %0x!", mst_r_id_i); + end + end + end +// pragma translate_on + + // Control AR Channel + always_comb begin + mst_ar_valid_o = 1'b0; + slv_ar_ready_o = 1'b0; + ar_push_addr = 'x; + ar_push_excl = 'x; + ar_push_id = 'x; + ar_push_res = 'x; + ar_push_valid = 1'b0; + ar_wifq_exists_inp.data.addr = 'x; + ar_wifq_exists_inp.data.excl = 1'b0; + ar_wifq_exists_inp.mask = '1; + ar_wifq_exists_inp.mask[0] = 1'b0; // Don't care on `excl` bit. + ar_wifq_exists_req = 1'b0; + ar_state_d = ar_state_q; + + case (ar_state_q) + + AR_IDLE: begin + if (slv_ar_valid_i) begin + ar_push_addr = slv_ar_addr_i[AXI_ADDR_WIDTH-1:2]; + ar_push_id = slv_ar_id_i; + ar_push_excl = (slv_ar_addr_i >= ADDR_BEGIN && slv_ar_addr_i <= ADDR_END && + slv_ar_lock_i && slv_ar_len_i == 8'h00); + if (ar_push_excl) begin + ar_wifq_exists_inp.data.addr = slv_ar_addr_i[AXI_ADDR_WIDTH-1:2]; + ar_wifq_exists_req = 1'b1; + if (ar_wifq_exists_gnt) begin + ar_push_res = !wifq_exists; + ar_push_valid = 1'b1; + end + end else begin + ar_push_res = 1'b0; + ar_push_valid = 1'b1; + end + if (ar_push_ready) begin + mst_ar_valid_o = 1'b1; + if (mst_ar_ready_i) begin + slv_ar_ready_o = 1'b1; + end else begin + ar_state_d = AR_WAIT; + end + end + end + end + + AR_WAIT: begin + mst_ar_valid_o = slv_ar_valid_i; + slv_ar_ready_o = mst_ar_ready_i; + if (mst_ar_ready_i && mst_ar_valid_o) begin + ar_state_d = AR_IDLE; + end + end + + default: begin + ar_state_d = AR_IDLE; + end + endcase + end + + // AW, W and B Channel + + // FIFO to track commands for W bursts. + fifo_v3 #( + .FALL_THROUGH (1'b0), // TODO: Why is there a combinatorial loop if this is fall-through? + .dtype (w_cmd_t), + .DEPTH (AXI_MAX_WRITE_TXNS) + ) i_w_cmd_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i (1'b0), + .full_o (w_cmd_full), + .empty_o (w_cmd_empty), + .usage_o (), + .data_i (w_cmd_inp), + .push_i (w_cmd_push), + .data_o (w_cmd_oup), + .pop_i (w_cmd_pop) + ); + + // ID Queue to track downstream W bursts and their pending B responses. + id_queue #( + .ID_WIDTH (AXI_ID_WIDTH), + .CAPACITY (AXI_MAX_WRITE_TXNS), + .data_t (b_cmd_t) + ) i_b_status_queue ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .inp_id_i (b_status_inp_id), + .inp_data_i (b_status_inp_cmd), + .inp_req_i (b_status_inp_req), + .inp_gnt_o (b_status_inp_gnt), + .exists_data_i (), + .exists_mask_i (), + .exists_req_i (1'b0), + .exists_o (), + .exists_gnt_o (), + .oup_id_i (b_status_oup_id), + .oup_pop_i (b_status_oup_pop), + .oup_req_i (b_status_oup_req), + .oup_data_o (b_status_oup_cmd), + .oup_data_valid_o (b_status_oup_valid), + .oup_gnt_o (b_status_oup_gnt) + ); + + // ID Queue to track in-flight writes. + id_queue #( + .ID_WIDTH (AXI_ID_WIDTH), + .CAPACITY (AXI_MAX_WRITE_TXNS), + .data_t (w_flight_t) + ) i_write_in_flight_queue ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .inp_id_i (mst_aw_id_o), + .inp_data_i ({mst_aw_addr_o[AXI_ADDR_WIDTH-1:2], slv_aw_lock_i}), + .inp_req_i (mst_aw_valid && mst_aw_ready), + .inp_gnt_o (wifq_inp_gnt), + .exists_data_i (wifq_exists_inp.data), + .exists_mask_i (wifq_exists_inp.mask), + .exists_req_i (wifq_exists_req), + .exists_o (wifq_exists), + .exists_gnt_o (wifq_exists_gnt), + .oup_id_i (mst_b_id_i), + .oup_pop_i (1'b1), + .oup_req_i (wifq_oup_req), + .oup_data_o (), + .oup_data_valid_o (wifq_oup_data_valid), + .oup_gnt_o (wifq_oup_gnt) + ); + +// pragma translate_off + always @(posedge clk_i) begin + if (~rst_ni) begin + if (mst_aw_valid && mst_aw_ready) begin + assert (wifq_inp_gnt) else $error("Missed enqueuing of in-flight write!"); + end + if (wifq_oup_req && wifq_oup_gnt) begin + assert (wifq_oup_data_valid) else $error("Unexpected B!"); + end + end + end +// pragma translate_on + + stream_arbiter #( + .DATA_T (wifq_exists_t), + .N_INP (2) + ) i_wifq_exists_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .inp_data_i ({ar_wifq_exists_inp, aw_wifq_exists_inp}), + .inp_valid_i ({ar_wifq_exists_req, aw_wifq_exists_req}), + .inp_ready_o ({ar_wifq_exists_gnt, aw_wifq_exists_gnt}), + .oup_data_o (wifq_exists_inp), + .oup_valid_o (wifq_exists_req), + .oup_ready_i (wifq_exists_gnt) + ); + + stream_fork #( + .N_OUP (2) + ) i_mst_b_fork ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .valid_i (mst_b_valid_i), + .ready_o (mst_b_ready_o), + .valid_o ({mst_b_valid, wifq_oup_req}), + .ready_i ({mst_b_ready, wifq_oup_gnt}) + ); + + // FIFO to track B responses that are to be injected. + fifo_v3 #( + .FALL_THROUGH (1'b0), + .dtype (b_inj_t), + .DEPTH (AXI_MAX_WRITE_TXNS) + ) i_b_inj_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i (1'b0), + .full_o (b_inj_full), + .empty_o (b_inj_empty), + .usage_o (), + .data_i (b_inj_inp), + .push_i (b_inj_push), + .data_o (b_inj_oup), + .pop_i (b_inj_pop) + ); + + // Fall-through register to hold AW transactin that passed + assign slv_aw = {slv_aw_addr_i, + slv_aw_prot_i, + slv_aw_region_i, + slv_aw_atop_i, + slv_aw_len_i, + slv_aw_size_i, + slv_aw_burst_i, + slv_aw_cache_i, + slv_aw_qos_i, + slv_aw_id_i, + slv_aw_user_i}; + assign {mst_aw_addr_o, + mst_aw_prot_o, + mst_aw_region_o, + mst_aw_atop_o, + mst_aw_len_o, + mst_aw_size_o, + mst_aw_burst_o, + mst_aw_cache_o, + mst_aw_qos_o, + mst_aw_id_o, + mst_aw_user_o} = mst_aw; + + + fall_through_register #( + .T (aw_chan_t) + ) i_aw_trans_reg ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_i (1'b0), + .testmode_i (1'b0), + // Input + .valid_i (mst_aw_valid), + .ready_o (mst_aw_ready), + .data_i (slv_aw), + // Output + .valid_o (mst_aw_valid_o), + .ready_i (mst_aw_ready_i), + .data_o (mst_aw) + ); + + // Time-Invariant Signal Assignments + assign mst_aw_lock_o = 1'b0; + assign mst_w_data_o = slv_w_data_i; + assign mst_w_strb_o = slv_w_strb_i; + assign mst_w_user_o = slv_w_user_i; + assign mst_w_last_o = slv_w_last_i; + + // Control AW Channel + always_comb begin + mst_aw_valid = 1'b0; + slv_aw_ready_o = 1'b0; + art_check_clr_addr = 'x; + art_check_id = 'x; + art_check_clr_excl = 'x; + art_check_clr_req = 1'b0; + aw_wifq_exists_inp.data = 'x; + aw_wifq_exists_inp.mask = '1; + aw_wifq_exists_req = 1'b0; + b_status_inp_id = '0; + b_status_inp_cmd = B_U; + b_status_inp_req = 1'b0; + w_cmd_inp = 'x; + w_cmd_push = 1'b0; + aw_state_d = aw_state_q; + + case (aw_state_q) + AW_IDLE: begin + if (slv_aw_valid_i && !w_cmd_full && b_status_inp_gnt && wifq_inp_gnt) begin + // New AW and we are ready to handle it. + if (slv_aw_addr_i >= ADDR_BEGIN && slv_aw_addr_i <= ADDR_END) begin + // Inside exclusively-accessible range. + // Make sure no exclusive AR to the same address is currently waiting. + if (!(slv_ar_valid_i && slv_ar_lock_i && + slv_ar_addr_i[AXI_ADDR_WIDTH-1:2] == slv_aw_addr_i[AXI_ADDR_WIDTH-1:2])) begin + // Make sure no exclusive write to the same address is currently in + // flight. + aw_wifq_exists_inp.data.addr = slv_aw_addr_i[AXI_ADDR_WIDTH-1:2]; + aw_wifq_exists_inp.data.excl = 1'b1; + aw_wifq_exists_req = 1'b1; + if (aw_wifq_exists_gnt && !wifq_exists) begin + // Check reservation and clear identical addresses. + art_check_clr_addr = slv_aw_addr_i[AXI_ADDR_WIDTH-1:2]; + art_check_id = slv_aw_id_i; + art_check_clr_excl = slv_aw_lock_i; + if (mst_aw_ready) begin + art_check_clr_req = 1'b1; + end + if (art_check_clr_gnt) begin + if (slv_aw_lock_i && slv_aw_len_i == 8'h00) begin + // Exclusive access and no burst, so check reservation. + if (art_check_res) begin + // Reservation exists, so forward downstream. + mst_aw_valid = 1'b1; + slv_aw_ready_o = mst_aw_ready; + if (!mst_aw_ready) begin + aw_state_d = AW_WAIT; + end + end else begin + // No reservation exists, so drop AW. + slv_aw_ready_o = 1'b1; + end + // Store command to forward or drop W burst. + w_cmd_inp = '{forward: art_check_res, id: slv_aw_id_i, + user: slv_aw_user_i}; + w_cmd_push = 1'b1; + // Add B status for this ID (exclusive if there is a + // reservation, inject otherwise). + b_status_inp_cmd = art_check_res ? B_EXCLUSIVE : B_INJECT; + end else begin + // Non-exclusive access or burst, so forward downstream. + mst_aw_valid = 1'b1; + slv_aw_ready_o = mst_aw_ready; + // Store command to forward W burst. + w_cmd_inp = '{forward: 1'b1, id: 'x, user: 'x}; + w_cmd_push = 1'b1; + // Track B response as regular-okay. + b_status_inp_cmd = B_REGULAR; + if (!mst_aw_ready) begin + aw_state_d = AW_WAIT; + end + end + b_status_inp_id = slv_aw_id_i; + b_status_inp_req = 1'b1; + end + end + end + end else begin + // Outside exclusively-accessible address range, so bypass any + // modifications. + mst_aw_valid = 1'b1; + slv_aw_ready_o = mst_aw_ready; + if (mst_aw_ready) begin + // Store command to forward W burst. + w_cmd_inp = '{forward: 1'b1, id: 'x, user: 'x}; + w_cmd_push = 1'b1; + // Track B response as regular-okay. + b_status_inp_id = slv_aw_id_i; + b_status_inp_cmd = B_REGULAR; + b_status_inp_req = 1'b1; + end + end + end + end + + AW_WAIT: begin + mst_aw_valid = 1'b1; + slv_aw_ready_o = mst_aw_ready; + if (mst_aw_ready) begin + aw_state_d = AW_IDLE; + end + end + + default: + aw_state_d = AW_IDLE; + endcase + end + +// pragma translate_off + if (DEBUG) begin + always @(posedge clk_i) begin + if (b_status_inp_req && b_status_inp_gnt) begin + $display("%0t: AW added %0x as %0d", $time, b_status_inp_id, b_status_inp_cmd); + end + end + end +// pragma translate_on + + // Control W Channel + always_comb begin + mst_w_valid_o = 1'b0; + slv_w_ready_o = 1'b0; + b_inj_inp = 'x; + b_inj_push = 1'b0; + w_cmd_pop = 1'b0; + if (slv_w_valid_i && !w_cmd_empty && !b_inj_full) begin + if (w_cmd_oup.forward) begin + // Forward + mst_w_valid_o = 1'b1; + slv_w_ready_o = mst_w_ready_i; + end else begin + // Drop + slv_w_ready_o = 1'b1; + end + if (slv_w_ready_o && slv_w_last_i) begin + w_cmd_pop = 1'b1; + if (!w_cmd_oup.forward) begin + // Add command to inject B response. + b_inj_inp = '{id: w_cmd_oup.id, user: w_cmd_oup.user}; + b_inj_push = 1'b1; + end + end + end + end + +// pragma translate_off + if (DEBUG) begin + always @(posedge clk_i) begin + if (b_inj_push) begin + $display("%0t: W added inject for %0x", $time, b_inj_inp.id); + end + end + end +// pragma translate_on + + // Control B Channel + always_comb begin + slv_b.id = mst_b_id_i; + slv_b.resp = mst_b_resp_i; + slv_b.user = mst_b_user_i; + slv_b_valid = 1'b0; + mst_b_ready = 1'b0; + b_inj_pop = 1'b0; + b_status_oup_id = 'x; + b_status_oup_req = 1'b0; + b_state_d = b_state_q; + + case (b_state_q) + B_NORMAL: begin + if (!b_inj_empty) begin + // There is a response to be injected .. + b_status_oup_id = b_inj_oup.id; + b_status_oup_req = 1'b1; + if (b_status_oup_gnt && b_status_oup_valid) begin + if (b_status_oup_cmd == B_INJECT) begin + // .. and the next B for that ID is indeed an injection, so go ahead and + // inject it. + slv_b.id = b_inj_oup.id; + slv_b.resp = axi_pkg::RESP_OKAY; + slv_b.user = b_inj_oup.user; + slv_b_valid = 1'b1; + b_inj_pop = slv_b_ready; + end else begin + // .. but the next B for that ID is *not* an injection, so try to + // forward a B. + b_state_d = B_FORWARD; + end + end + end else if (mst_b_valid) begin + // There is currently no response to be injected, so try to forward a B. + b_status_oup_id = mst_b_id_i; + b_status_oup_req = 1'b1; + if (b_status_oup_gnt && b_status_oup_valid) begin + if (mst_b_resp_i[1] == 1'b0) begin + slv_b.resp = {1'b0, (b_status_oup_cmd == B_EXCLUSIVE)}; + end else begin + slv_b.resp = mst_b_resp_i; + end + slv_b_valid = 1'b1; + mst_b_ready = slv_b_ready; + end + end + end + + B_FORWARD: begin + if (mst_b_valid) begin + b_status_oup_id = mst_b_id_i; + b_status_oup_req = 1'b1; + if (b_status_oup_gnt && b_status_oup_valid) begin + if (mst_b_resp_i[1] == 1'b0) begin + slv_b.resp = {1'b0, (b_status_oup_cmd == B_EXCLUSIVE)}; + end else begin + slv_b.resp = mst_b_resp_i; + end + slv_b_valid = 1'b1; + mst_b_ready = slv_b_ready; + if (slv_b_ready) begin + b_state_d = B_NORMAL; + end + end + end + end + + default: + b_state_d = B_NORMAL; + endcase + end + +// pragma translate_off + always @(posedge clk_i) begin + if (b_status_oup_req && b_status_oup_gnt) begin + assert (b_status_oup_valid); + if ((b_state_q == B_NORMAL && b_inj_empty) || b_state_q == B_FORWARD) begin + assert (b_status_oup_cmd != B_INJECT); + end + end + end +// pragma translate_on + +// pragma translate_off + if (DEBUG) begin + always @(posedge clk_i) begin + if (slv_b_valid && slv_b_ready) begin + if (mst_b_ready) begin + $display("%0t: B forwarded %0x", $time, slv_b.id); + end else begin + $display("%0t: B injected %0x", $time, slv_b.id); + end + end + end + end +// pragma translate_on + + assign b_status_oup_pop = slv_b_valid && slv_b_ready; + + // Register in front of slv_b to prevent changes by FSM while valid and not yet ready. + fall_through_register #( + .T (b_chan_t) + ) slv_b_reg ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_i (1'b0), + .testmode_i (1'b0), + + .valid_i (slv_b_valid), + .ready_o (slv_b_ready), + .data_i (slv_b), + + .valid_o (slv_b_valid_o), + .ready_i (slv_b_ready_i), + .data_o ({slv_b_id_o, slv_b_user_o, slv_b_resp_o}) + ); + + // Fall-through register in front of slv_r to remove mutual dependency. + spill_register #( // TODO: Why is there a combinatorial loop if this is a `fall_through_register`? + .T (r_chan_t) + ) slv_r_reg ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .valid_i (slv_r_valid), + .ready_o (slv_r_ready), + .data_i (slv_r), + + .valid_o (slv_r_valid_o), + .ready_i (slv_r_ready_i), + .data_o ({slv_r_id_o, slv_r_data_o, slv_r_resp_o, slv_r_user_o, slv_r_last_o}) + ); + + // AXI Reservation Table + axi_res_tbl #( + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH-2), // Track reservations word-wise. + .AXI_ID_WIDTH (AXI_ID_WIDTH) + ) i_art ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .check_clr_addr_i (art_check_clr_addr), + .check_id_i (art_check_id), + .check_clr_excl_i (art_check_clr_excl), + .check_res_o (art_check_res), + .check_clr_req_i (art_check_clr_req), + .check_clr_gnt_o (art_check_clr_gnt), + .set_addr_i (ar_push_addr), + .set_id_i (ar_push_id), + .set_req_i (art_set_req), + .set_gnt_o (art_set_gnt) + ); + + // Registers + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + ar_state_q = AR_IDLE; + aw_state_q = AW_IDLE; + b_state_q = B_NORMAL; + end else begin + ar_state_q = ar_state_d; + aw_state_q = aw_state_d; + b_state_q = b_state_d; + end + end + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (ADDR_END > ADDR_BEGIN) + else $fatal(1, "ADDR_END must be greater than ADDR_BEGIN!"); + assert (AXI_ADDR_WIDTH > 0) + else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!"); + assert (AXI_DATA_WIDTH > 0) + else $fatal(1, "AXI_DATA_WIDTH must be greater than 0!"); + assert (AXI_ID_WIDTH > 0) + else $fatal(1, "AXI_ID_WIDTH must be greater than 0!"); + assert (AXI_MAX_READ_TXNS > 0) + else $fatal(1, "AXI_MAX_READ_TXNS must be greater than 0!"); + assert (AXI_MAX_WRITE_TXNS > 0) + else $fatal(1, "AXI_MAX_WRITE_TXNS must be greater than 0!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/axi_slice/src/axi_ar_buffer.sv b/hw/deps/axi_slice/src/axi_ar_buffer.sv new file mode 100644 index 0000000..e133693 --- /dev/null +++ b/hw/deps/axi_slice/src/axi_ar_buffer.sv @@ -0,0 +1,74 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi_ar_buffer #( + parameter int ID_WIDTH = -1, + parameter int ADDR_WIDTH = -1, + parameter int USER_WIDTH = -1, + parameter int BUFFER_DEPTH = -1 +)( + + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + input logic slave_valid_i, + input logic [ADDR_WIDTH-1:0] slave_addr_i, + input logic [2:0] slave_prot_i, + input logic [3:0] slave_region_i, + input logic [7:0] slave_len_i, + input logic [2:0] slave_size_i, + input logic [1:0] slave_burst_i, + input logic slave_lock_i, + input logic [3:0] slave_cache_i, + input logic [3:0] slave_qos_i, + input logic [ID_WIDTH-1:0] slave_id_i, + input logic [USER_WIDTH-1:0] slave_user_i, + output logic slave_ready_o, + + output logic master_valid_o, + output logic [ADDR_WIDTH-1:0] master_addr_o, + output logic [2:0] master_prot_o, + output logic [3:0] master_region_o, + output logic [7:0] master_len_o, + output logic [2:0] master_size_o, + output logic [1:0] master_burst_o, + output logic master_lock_o, + output logic [3:0] master_cache_o, + output logic [3:0] master_qos_o, + output logic [ID_WIDTH-1:0] master_id_o, + output logic [USER_WIDTH-1:0] master_user_o, + input logic master_ready_i +); + + logic [29+ADDR_WIDTH+USER_WIDTH+ID_WIDTH-1:0] s_data_in; + logic [29+ADDR_WIDTH+USER_WIDTH+ID_WIDTH-1:0] s_data_out; + + assign s_data_in = {slave_cache_i, slave_prot_i, slave_lock_i, slave_burst_i, slave_size_i, slave_len_i, slave_qos_i, slave_region_i, slave_addr_i, slave_user_i, slave_id_i} ; + assign {master_cache_o, master_prot_o, master_lock_o, master_burst_o, master_size_o, master_len_o, master_qos_o, master_region_o, master_addr_o, master_user_o, master_id_o} = s_data_out; + + + + axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(29+ADDR_WIDTH+USER_WIDTH+ID_WIDTH)) i_axi_single_slice ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( test_en_i ), + .valid_i ( slave_valid_i ), + .ready_o ( slave_ready_o ), + .data_i ( s_data_in ), + .ready_i ( master_ready_i ), + .valid_o ( master_valid_o ), + .data_o ( s_data_out ) + ); + + +endmodule diff --git a/hw/deps/axi_slice/src/axi_aw_buffer.sv b/hw/deps/axi_slice/src/axi_aw_buffer.sv new file mode 100644 index 0000000..da8ab41 --- /dev/null +++ b/hw/deps/axi_slice/src/axi_aw_buffer.sv @@ -0,0 +1,78 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi_aw_buffer #( + parameter int ID_WIDTH = -1, + parameter int ADDR_WIDTH = -1, + parameter int USER_WIDTH = -1, + parameter int BUFFER_DEPTH = -1 +)( + + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + input logic slave_valid_i, + input logic [ADDR_WIDTH-1:0] slave_addr_i, + input logic [2:0] slave_prot_i, + input logic [3:0] slave_region_i, + input logic [7:0] slave_len_i, + input logic [2:0] slave_size_i, + input logic [1:0] slave_burst_i, + input logic slave_lock_i, + input logic [5:0] slave_atop_i, + input logic [3:0] slave_cache_i, + input logic [3:0] slave_qos_i, + input logic [ID_WIDTH-1:0] slave_id_i, + input logic [USER_WIDTH-1:0] slave_user_i, + output logic slave_ready_o, + + output logic master_valid_o, + output logic [ADDR_WIDTH-1:0] master_addr_o, + output logic [2:0] master_prot_o, + output logic [3:0] master_region_o, + output logic [7:0] master_len_o, + output logic [2:0] master_size_o, + output logic [1:0] master_burst_o, + output logic master_lock_o, + output logic [5:0] master_atop_o, + output logic [3:0] master_cache_o, + output logic [3:0] master_qos_o, + output logic [ID_WIDTH-1:0] master_id_o, + output logic [USER_WIDTH-1:0] master_user_o, + input logic master_ready_i +); + + localparam int unsigned DATA_WIDTH = 29+6+ADDR_WIDTH+USER_WIDTH+ID_WIDTH; + + logic [DATA_WIDTH-1:0] s_data_in; + logic [DATA_WIDTH-1:0] s_data_out; + + + + assign s_data_in = {slave_cache_i, slave_prot_i, slave_lock_i, slave_atop_i, slave_burst_i, slave_size_i, slave_len_i, slave_qos_i, slave_region_i, slave_addr_i, slave_user_i, slave_id_i}; + assign {master_cache_o, master_prot_o, master_lock_o, master_atop_o, master_burst_o, master_size_o, master_len_o, master_qos_o, master_region_o, master_addr_o, master_user_o, master_id_o} = s_data_out; + + + axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(DATA_WIDTH)) i_axi_single_slice ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( test_en_i ), + .valid_i ( slave_valid_i ), + .ready_o ( slave_ready_o ), + .data_i ( s_data_in ), + .ready_i ( master_ready_i ), + .valid_o ( master_valid_o ), + .data_o ( s_data_out ) + ); + +endmodule diff --git a/hw/deps/axi_slice/src/axi_b_buffer.sv b/hw/deps/axi_slice/src/axi_b_buffer.sv new file mode 100644 index 0000000..d2576bb --- /dev/null +++ b/hw/deps/axi_slice/src/axi_b_buffer.sv @@ -0,0 +1,54 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi_b_buffer #( + parameter int ID_WIDTH = -1, + parameter int USER_WIDTH = -1, + parameter int BUFFER_DEPTH = -1 +)( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + input logic slave_valid_i, + input logic [1:0] slave_resp_i, + input logic [ID_WIDTH-1:0] slave_id_i, + input logic [USER_WIDTH-1:0] slave_user_i, + output logic slave_ready_o, + + output logic master_valid_o, + output logic [1:0] master_resp_o, + output logic [ID_WIDTH-1:0] master_id_o, + output logic [USER_WIDTH-1:0] master_user_o, + input logic master_ready_i +); + + logic [2+USER_WIDTH+ID_WIDTH-1:0] s_data_in; + logic [2+USER_WIDTH+ID_WIDTH-1:0] s_data_out; + + assign s_data_in = {slave_id_i, slave_user_i, slave_resp_i}; + assign {master_id_o, master_user_o, master_resp_o} = s_data_out; + + + axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(2+USER_WIDTH+ID_WIDTH)) i_axi_single_slice ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( test_en_i ), + .valid_i ( slave_valid_i ), + .ready_o ( slave_ready_o ), + .data_i ( s_data_in ), + .ready_i ( master_ready_i ), + .valid_o ( master_valid_o ), + .data_o ( s_data_out ) + ); + +endmodule diff --git a/hw/deps/axi_slice/src/axi_r_buffer.sv b/hw/deps/axi_slice/src/axi_r_buffer.sv new file mode 100644 index 0000000..3c92b25 --- /dev/null +++ b/hw/deps/axi_slice/src/axi_r_buffer.sv @@ -0,0 +1,60 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi_r_buffer #( + parameter ID_WIDTH = 4, + parameter DATA_WIDTH = 64, + parameter USER_WIDTH = 6, + parameter BUFFER_DEPTH = 8, + parameter STRB_WIDTH = DATA_WIDTH/8 // DO NOT OVERRIDE +)( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + input logic slave_valid_i, + input logic [DATA_WIDTH-1:0] slave_data_i, + input logic [1:0] slave_resp_i, + input logic [USER_WIDTH-1:0] slave_user_i, + input logic [ID_WIDTH-1:0] slave_id_i, + input logic slave_last_i, + output logic slave_ready_o, + + output logic master_valid_o, + output logic [DATA_WIDTH-1:0] master_data_o, + output logic [1:0] master_resp_o, + output logic [USER_WIDTH-1:0] master_user_o, + output logic [ID_WIDTH-1:0] master_id_o, + output logic master_last_o, + input logic master_ready_i +); + + logic [2+DATA_WIDTH+USER_WIDTH+ID_WIDTH:0] s_data_in; + logic [2+DATA_WIDTH+USER_WIDTH+ID_WIDTH:0] s_data_out; + + + assign s_data_in = {slave_id_i, slave_user_i, slave_data_i, slave_resp_i, slave_last_i}; + assign {master_id_o, master_user_o, master_data_o, master_resp_o, master_last_o} = s_data_out; + + axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(3+DATA_WIDTH+USER_WIDTH+ID_WIDTH)) i_axi_single_slice ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( test_en_i ), + .valid_i ( slave_valid_i ), + .ready_o ( slave_ready_o ), + .data_i ( s_data_in ), + .ready_i ( master_ready_i ), + .valid_o ( master_valid_o ), + .data_o ( s_data_out ) + ); + +endmodule diff --git a/hw/deps/axi_slice/src/axi_single_slice.sv b/hw/deps/axi_slice/src/axi_single_slice.sv new file mode 100644 index 0000000..fe7fbbc --- /dev/null +++ b/hw/deps/axi_slice/src/axi_single_slice.sv @@ -0,0 +1,51 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Wrapper for a generic fifo +module axi_single_slice #( + parameter int BUFFER_DEPTH = -1, + parameter int DATA_WIDTH = -1 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic testmode_i, + input logic valid_i, + output logic ready_o, + input logic [DATA_WIDTH-1:0] data_i, + + input logic ready_i, + output logic valid_o, + output logic [DATA_WIDTH-1:0] data_o +); + + logic full, empty; + + assign ready_o = ~full; + assign valid_o = ~empty; + + fifo #( + .FALL_THROUGH ( 1'b0 ), + .DATA_WIDTH ( DATA_WIDTH ), + .DEPTH ( BUFFER_DEPTH ) + ) i_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .threshold_o (), // NC + .testmode_i ( testmode_i ), + .full_o ( full ), + .empty_o ( empty ), + .data_i ( data_i ), + .push_i ( valid_i & ready_o ), + .data_o ( data_o ), + .pop_i ( ready_i & valid_o ) + ); + +endmodule diff --git a/hw/deps/axi_slice/src/axi_w_buffer.sv b/hw/deps/axi_slice/src/axi_w_buffer.sv new file mode 100644 index 0000000..0e89a47 --- /dev/null +++ b/hw/deps/axi_slice/src/axi_w_buffer.sv @@ -0,0 +1,55 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module axi_w_buffer #( + parameter int DATA_WIDTH = -1, + parameter int USER_WIDTH = -1, + parameter int BUFFER_DEPTH = -1, + parameter int STRB_WIDTH = DATA_WIDTH/8 // DO NOT OVERRIDE +)( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + input logic slave_valid_i, + input logic [DATA_WIDTH-1:0] slave_data_i, + input logic [STRB_WIDTH-1:0] slave_strb_i, + input logic [USER_WIDTH-1:0] slave_user_i, + input logic slave_last_i, + output logic slave_ready_o, + + output logic master_valid_o, + output logic [DATA_WIDTH-1:0] master_data_o, + output logic [STRB_WIDTH-1:0] master_strb_o, + output logic [USER_WIDTH-1:0] master_user_o, + output logic master_last_o, + input logic master_ready_i +); + + logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_in; + logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_out; + + assign s_data_in = { slave_user_i, slave_strb_i, slave_data_i, slave_last_i }; + assign { master_user_o, master_strb_o, master_data_o, master_last_o } = s_data_out; + + axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(1+DATA_WIDTH+STRB_WIDTH+USER_WIDTH)) i_axi_single_slice ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( test_en_i ), + .valid_i ( slave_valid_i ), + .ready_o ( slave_ready_o ), + .data_i ( s_data_in ), + .ready_i ( master_ready_i ), + .valid_o ( master_valid_o ), + .data_o ( s_data_out ) + ); +endmodule diff --git a/hw/deps/axi_slice_dc/src/dc_synchronizer.v b/hw/deps/axi_slice_dc/src/dc_synchronizer.v new file mode 100644 index 0000000..8be6034 --- /dev/null +++ b/hw/deps/axi_slice_dc/src/dc_synchronizer.v @@ -0,0 +1,38 @@ +// Copyright 2015-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_synchronizer (clk, rstn, d_in, d_out); + + parameter WIDTH = 1; + parameter RESET_VALUE = 'h0; + + input clk; + input rstn; + input [WIDTH - 1 : 0] d_in; + output [WIDTH - 1 : 0] d_out; + + reg [WIDTH - 1 : 0] d_middle; + reg [WIDTH - 1 : 0] d_out; + + always @(posedge clk or negedge rstn) + begin: update_state + if (rstn == 1'b0) + begin + d_middle <= RESET_VALUE; + d_out <= RESET_VALUE; + end + else + begin + d_middle <= d_in; + d_out <= d_middle; + end + end + +endmodule diff --git a/hw/deps/axi_slice_dc/src/dc_token_ring.v b/hw/deps/axi_slice_dc/src/dc_token_ring.v new file mode 100644 index 0000000..4c35237 --- /dev/null +++ b/hw/deps/axi_slice_dc/src/dc_token_ring.v @@ -0,0 +1,40 @@ +// Copyright 2015-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_token_ring(clk, rstn, enable, state); + + parameter BUFFER_DEPTH = 8; + parameter RESET_VALUE = 'h3; + + input clk; + input rstn; + input enable; + output [BUFFER_DEPTH - 1 : 0] state; + + reg [BUFFER_DEPTH - 1 : 0] state; + reg [BUFFER_DEPTH - 1 : 0] next_state; + + always @(posedge clk or negedge rstn) + begin: update_state + if (rstn == 1'b0) + state <= RESET_VALUE; + else + state <= next_state; + end + + always @(enable, state) + begin + if (enable) + next_state = {state[BUFFER_DEPTH - 2 : 0], state[BUFFER_DEPTH - 1]}; + else + next_state = state; + end + +endmodule diff --git a/hw/deps/axi_slice_dc/src/dc_token_ring_fifo_dout.v b/hw/deps/axi_slice_dc/src/dc_token_ring_fifo_dout.v new file mode 100644 index 0000000..66deeb2 --- /dev/null +++ b/hw/deps/axi_slice_dc/src/dc_token_ring_fifo_dout.v @@ -0,0 +1,77 @@ +// Copyright 2015-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module dc_token_ring_fifo_dout(clk, rstn, data_async, write_token, read_pointer, data, valid, ready); + + parameter DATA_WIDTH = 10; + parameter BUFFER_DEPTH = 8; + + input [DATA_WIDTH - 1 : 0] data_async; + + input clk; + input rstn; + output [DATA_WIDTH - 1 : 0] data; + output valid; + input ready; + + input [BUFFER_DEPTH - 1 : 0] write_token; + output [BUFFER_DEPTH - 1 : 0] read_pointer; + + wire read_enable; + wire stall; + // Pointers to the write, read addresses (two-hot encoding) + wire [BUFFER_DEPTH - 1 : 0] read_token; + + wire [BUFFER_DEPTH - 1 : 0] write_token_dn; + wire [BUFFER_DEPTH - 1 : 0] empty; + + assign data = data_async; + + assign stall = ~ready; + + // FIFO read/write enable + assign read_enable = (valid & ~stall); + + // Logic to compute the read, write pointers + dc_token_ring + #( + .BUFFER_DEPTH ( BUFFER_DEPTH ), + .RESET_VALUE ( 'h3 ) + ) + read_tr + ( + .clk ( clk ), + .rstn ( rstn ), + .enable ( read_enable ), + .state ( read_token ) + ); + + // Pointers to the write, read addresses (semi-accurate, leveraging the two-hot encoding for extra robustness) + assign read_pointer = {read_token[BUFFER_DEPTH - 3 : 0], read_token[BUFFER_DEPTH - 1 : BUFFER_DEPTH - 2]} & + {read_token[BUFFER_DEPTH - 4 : 0], read_token[BUFFER_DEPTH - 1 : BUFFER_DEPTH - 3]}; + + // Empty detector; if any of the bits is 1, the synchronizer is empty + dc_synchronizer + #( + .WIDTH ( BUFFER_DEPTH ), + .RESET_VALUE ( 'hc ) + ) + empty_synch + ( + .clk ( clk ), + .rstn ( rstn ), + .d_in ( write_token ), + .d_out ( write_token_dn ) + ); + + assign empty = ~write_token_dn & {write_token_dn[0], write_token_dn[BUFFER_DEPTH - 1 : 1]} & {read_pointer[1 : 0], read_pointer[BUFFER_DEPTH - 1 : 2]}; + assign valid = ~(|empty); + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/interfaces/tcdm_bank_mem_bus.sv b/hw/deps/cluster_interconnect/rtl/interfaces/tcdm_bank_mem_bus.sv new file mode 100644 index 0000000..ed9dfe5 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/interfaces/tcdm_bank_mem_bus.sv @@ -0,0 +1,30 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +interface TCDM_BANK_MEM_BUS; + + logic [31:0] wdata; + logic [31:0] add; + logic req; + logic wen; + logic [3:0] be; + logic [31:0] rdata; + + modport Master ( + output wdata, add, req, wen, be, + input rdata + ); + + modport Slave ( + input wdata, add, req, wen, be, + output rdata + ); + +endinterface diff --git a/hw/deps/cluster_interconnect/rtl/interfaces/wide_dma_tcdm.sv b/hw/deps/cluster_interconnect/rtl/interfaces/wide_dma_tcdm.sv new file mode 100644 index 0000000..fd122c1 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/interfaces/wide_dma_tcdm.sv @@ -0,0 +1,39 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +interface WIDE_DMA_TCDM_BUS #( + parameter int unsigned ADDR_WIDTH = -1, + parameter int unsigned DATA_WIDTH = -1 +); + + // Request Channel + logic req; + logic [ADDR_WIDTH-1:0] add; + logic wen; + logic [DATA_WIDTH-1:0] wdata; + logic [DATA_WIDTH/8-1:0] be; + logic gnt; + + // Response Channel + logic r_opc; + logic [DATA_WIDTH-1:0] r_rdata; + logic r_valid; + + modport Master ( + output req,add, wen, wdata, be, + input gnt, r_rdata, r_opc, r_valid + ); + + modport Slave ( + input req,add, wen, wdata, be, + output gnt, r_rdata, r_opc, r_valid + ); + +endinterface diff --git a/hw/deps/cluster_interconnect/rtl/interfaces/xbar_demux_bus.sv b/hw/deps/cluster_interconnect/rtl/interfaces/xbar_demux_bus.sv new file mode 100644 index 0000000..ad6e529 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/interfaces/xbar_demux_bus.sv @@ -0,0 +1,41 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +interface XBAR_DEMUX_BUS; + + // Request Channel + logic barrier; + logic busy; + logic exec_cancel; + logic exec_stall; + logic req; + logic [31:0] add; + logic we; + logic [5:0] atop; + logic [31:0] wdata; + logic [3:0] be; + logic gnt; + + // Response Channel + logic r_gnt; + logic r_valid; + logic [31:0] r_rdata; + + modport Master ( + output barrier, exec_cancel, exec_stall, req, add, we, atop, wdata, be, r_gnt, + input busy, gnt, r_rdata, r_valid + ); + + modport Slave ( + input barrier, exec_cancel, exec_stall, req, add, we, atop, wdata, be, r_gnt, + output busy, gnt, r_rdata, r_valid + ); + +endinterface diff --git a/hw/deps/cluster_interconnect/rtl/interfaces/xbar_periph_bus.sv b/hw/deps/cluster_interconnect/rtl/interfaces/xbar_periph_bus.sv new file mode 100644 index 0000000..446b141 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/interfaces/xbar_periph_bus.sv @@ -0,0 +1,40 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +interface XBAR_PERIPH_BUS #( + parameter int ID_WIDTH = 9 // typically number of cores plus one +); + + // Request Channel + logic req; + logic [31:0] add; + logic wen; + logic [31:0] wdata; + logic [3:0] be; + logic gnt; + logic [ID_WIDTH-1:0] id; + + // Response Channel + logic r_valid; + logic r_opc; + logic [ID_WIDTH-1:0] r_id; + logic [31:0] r_rdata; + + modport Master ( + output req, add, wen, wdata, be, id, + input gnt, r_rdata, r_opc, r_id, r_valid + ); + + modport Slave ( + input req, add, wen, wdata, be, id, + output gnt, r_rdata, r_opc, r_id, r_valid + ); + +endinterface diff --git a/hw/deps/cluster_interconnect/rtl/interfaces/xbar_tcdm_bus.sv b/hw/deps/cluster_interconnect/rtl/interfaces/xbar_tcdm_bus.sv new file mode 100644 index 0000000..06f0b5b --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/interfaces/xbar_tcdm_bus.sv @@ -0,0 +1,36 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +interface XBAR_TCDM_BUS; + + // Request Channel + logic req; + logic [31:0] add; + logic wen; + logic [31:0] wdata; + logic [3:0] be; + logic gnt; + + // Response Channel + logic r_opc; + logic [31:0] r_rdata; + logic r_valid; + + modport Master ( + output req,add, wen, wdata, be, + input gnt, r_rdata, r_opc, r_valid + ); + + modport Slave ( + input req,add, wen, wdata, be, + output gnt, r_rdata, r_opc, r_valid + ); + +endinterface diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_PE_Req.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_PE_Req.sv new file mode 100644 index 0000000..c424ed0 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_PE_Req.sv @@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 29/06/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: AddressDecoder_PE_Req // +// Language: SystemVerilog // +// // +// Description: Address Decoder used to generate the individual requests // +// for all the available memory cuts. It backroutes the // +// grants from the Arbitration tree to the processor // +// // +// // +// Revision: // +// Revision v0.1 - File Created // +// Revision v0.2 - Code Restyling (19/02/2015) // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + +module AddressDecoder_PE_Req +#( + parameter int ID_WIDTH = 17, // ID WIDTH (number of bits) --> see ID comment + parameter int ID = 1, // ID routed with REQUEST used to backroute response + parameter int N_SLAVE = 16, // Number of Memory cuts + parameter int LOG_CLUSTER = 5, + parameter int ADDR_WIDTH = 32, + parameter int PE_ROUTING_LSB = 16, + parameter int PE_ROUTING_MSB = 19, + parameter bit CLUSTER_ALIAS = 1'b0, + parameter int CLUSTER_ALIAS_BASE = 12'h000 +) +( + input logic [LOG_CLUSTER-1:0] CLUSTER_ID, + // MASTER SIDE + input logic data_req_i, // Request from Master + input logic [ADDR_WIDTH-1:0] data_add_i, // Address from Master +`ifdef GNT_BASED_FC + output logic data_gnt_o, // Grant delivered to Master + input logic [N_SLAVE-1:0] data_gnt_i, // Grant Array: one for each memory on ARB TREE SIDE +`else + output logic data_stall_o, // Stall delivered to Master + input logic [N_SLAVE-1:0] data_stall_i, // Stall Array: one for each memory on ARB TREE SIDE +`endif + // ARB TREE SIDE + output logic [N_SLAVE-1:0] data_req_o, // Request Array: one for each memory + output logic [ID_WIDTH-1:0] data_ID_o // data_ID_o is sent whit the request (like a PID) +); + + localparam LOG_SLAVE = `log2(N_SLAVE-1); + + logic [LOG_SLAVE-1:0] ROUTING_ADDR; // M = Number of memory cuts + + logic [11:0] PE_END; + logic [11:0] PE_START; + + assign data_ID_o = ID; // ID is simply attached to the ID_OUT + + assign PE_START = 12'h100 + (CLUSTER_ID << 2) + 2; + assign PE_END = 12'h100 + (CLUSTER_ID << 2) + 3; + + always_comb begin + if (data_add_i[31:20] >= PE_START && data_add_i[31:20] < PE_END + || (CLUSTER_ALIAS + && data_add_i[31:20] >= CLUSTER_ALIAS_BASE+2 + && data_add_i[31:20] < (CLUSTER_ALIAS_BASE+3) + ) + ) begin + ROUTING_ADDR = data_add_i[PE_ROUTING_MSB:PE_ROUTING_LSB]; + end else begin + ROUTING_ADDR = '1; + end + end + + always_comb + begin : Combinational_ADDR_DEC_REQ + //DEFAULT VALUES + data_req_o = '0; + // Apply the rigth value + data_req_o[ROUTING_ADDR] = data_req_i; + `ifdef GNT_BASED_FC + data_gnt_o = data_gnt_i[ROUTING_ADDR]; + `else + data_stall_o = data_stall_i[ROUTING_ADDR]; + `endif + end + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv new file mode 100644 index 0000000..5e94d3d --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv @@ -0,0 +1,63 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 06/07/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: AddressDecoder_Resp // +// Project Name: MegaLEON // +// Language: SystemVerilog // +// // +// Description: Address Decoder used to generate the individual requests // +// for all the available masters . It routes the read data // +// from the memory to the processor // +// // +// // +// Revision: // +// Revision v0.1 - File Created // +// Revision v0.2 - Code Restyling (19/02/2015) // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + +module AddressDecoder_Resp_PE +#( + parameter ID_WIDTH = 20, // ID WIDTH (number of bits) --> see ID comment + parameter N_MASTER = 20 // Number of Master +) +( + // FROM Test And Set Interface + input logic data_r_valid_i, + input logic [ID_WIDTH-1:0] data_ID_i, + + // To Response Network + output logic [N_MASTER-1:0] data_r_valid_o +); + + assign data_r_valid_o = {ID_WIDTH{data_r_valid_i}} & data_ID_i; + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/ArbitrationTree_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/ArbitrationTree_PE.sv new file mode 100644 index 0000000..b9d7cfe --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/ArbitrationTree_PE.sv @@ -0,0 +1,347 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 06/07/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: ArbitrationTree // +// Project Name: MegaLEON // +// Language: SystemVerilog // +// // +// Description: Arbitration tree: This block performs the arbitration // +// between the N_MASTER requests. The arbitration is // +// distributed in the several arbitration primitives that // +// compose this routing block. The arbistrtion is round robin // +// and the round robin flag generator is embedded inside this // +// block. Flag updating happens only when requests are grant // +// // +// Revision: // +// Revision v0.1 - File Created // +// Revision v0.2 - Code Restyling (19/02/2015) // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + + +module ArbitrationTree_PE +#( + parameter ADDR_WIDTH = 32, + parameter ID_WIDTH = 20, + parameter N_MASTER = 16, + parameter DATA_WIDTH = 32, + parameter BE_WIDTH = DATA_WIDTH/8, + parameter MAX_COUNT = N_MASTER +) +( + input logic clk, + input logic rst_n, + + // ---------------- REQ_SIDE -------------------------- + input logic [N_MASTER-1:0] data_req_i, + input logic [N_MASTER-1:0][ADDR_WIDTH-1:0] data_add_i, + input logic [N_MASTER-1:0] data_wen_i, + input logic [N_MASTER-1:0][5:0] data_atop_i, + input logic [N_MASTER-1:0][DATA_WIDTH-1:0] data_wdata_i, + input logic [N_MASTER-1:0][BE_WIDTH-1:0] data_be_i, + input logic [N_MASTER-1:0][ID_WIDTH-1:0] data_ID_i, +`ifdef GNT_BASED_FC + output logic [N_MASTER-1:0] data_gnt_o, +`else + output logic [N_MASTER-1:0] data_stall_o, +`endif + // Outputs + output logic data_req_o, + output logic [ADDR_WIDTH-1:0] data_add_o, + output logic data_wen_o, + output logic [5:0] data_atop_o, + output logic [DATA_WIDTH-1:0] data_wdata_o, + output logic [BE_WIDTH-1:0] data_be_o, + output logic [ID_WIDTH-1:0] data_ID_o, +`ifdef GNT_BASED_FC + input logic data_gnt_i +`else + input logic data_stall_i +`endif +); + + localparam LOG_MASTER = `log2(N_MASTER-1); + localparam N_WIRE = N_MASTER - 2; + + logic [LOG_MASTER-1:0] RR_FLAG; + + genvar j,k; + + generate + if(N_MASTER == 2) + begin : INCR // START of MASTER == 2 + // ---------------- FAN IN PRIMITIVE ------------------------- + FanInPrimitive_Req_PE + #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ) + ) + i_FanInPrimitive_Req_PE + ( + .RR_FLAG(RR_FLAG), + // LEFT SIDE" + .data_wdata0_i(data_wdata_i[0]), + .data_wdata1_i(data_wdata_i[1]), + .data_add0_i(data_add_i[0]), + .data_add1_i(data_add_i[1]), + .data_req0_i(data_req_i[0]), + .data_req1_i(data_req_i[1]), + .data_wen0_i(data_wen_i[0]), + .data_wen1_i(data_wen_i[1]), + .data_atop0_i(data_atop_i[0]), + .data_atop1_i(data_atop_i[1]), + .data_ID0_i(data_ID_i[0]), + .data_ID1_i(data_ID_i[1]), + .data_be0_i(data_be_i[0]), + .data_be1_i(data_be_i[1]), + `ifdef GNT_BASED_FC + .data_gnt0_o(data_gnt_o[0]), + .data_gnt1_o(data_gnt_o[1]), + `else + .data_stall0_o(data_stall_o[0]), + .data_stall1_o(data_stall_o[1]), + `endif + // RIGTH SIDE" + .data_wdata_o(data_wdata_o), + .data_add_o(data_add_o), + .data_req_o(data_req_o), + .data_wen_o(data_wen_o), + .data_atop_o(data_atop_o), + .data_ID_o(data_ID_o), + .data_be_o(data_be_o), + `ifdef GNT_BASED_FC + .data_gnt_i(data_gnt_i) + `else + .data_stall_i(data_stall_i) + `endif + ); + end // END OF MASTER == 2 + else // More than two master + begin : BINARY_TREE + //// ---------------------------------------------------------------------- //// + //// ------- REQ ARBITRATION TREE WIRES ----------- //// + //// ---------------------------------------------------------------------- //// + logic [DATA_WIDTH-1:0] data_wdata_LEVEL[N_WIRE-1:0]; + logic [ADDR_WIDTH-1:0] data_add_LEVEL[N_WIRE-1:0]; + logic data_req_LEVEL[N_WIRE-1:0]; + logic data_wen_LEVEL[N_WIRE-1:0]; + logic [5:0] data_atop_LEVEL[N_WIRE-1:0]; + logic [ID_WIDTH-1:0] data_ID_LEVEL[N_WIRE-1:0]; + logic [BE_WIDTH-1:0] data_be_LEVEL[N_WIRE-1:0]; + `ifdef GNT_BASED_FC + logic data_gnt_LEVEL[N_WIRE-1:0]; + `else + logic data_stall_LEVEL[N_WIRE-1:0]; + `endif + + for(j=0; j < LOG_MASTER; j++) // Iteration for the number of the stages minus one + begin : STAGE + for(k=0; k<2**j; k=k+1) // Iteration needed to create the binary tree + begin : INCR_VERT + if (j == 0 ) // LAST NODE, drives the module outputs + begin : LAST_NODE + FanInPrimitive_Req_PE + #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ) + ) + i_FanInPrimitive_Req_PE + ( + .RR_FLAG(RR_FLAG[LOG_MASTER-j-1]), + // LEFT SIDE + .data_wdata0_i(data_wdata_LEVEL[2*k]), + .data_wdata1_i(data_wdata_LEVEL[2*k+1]), + .data_add0_i(data_add_LEVEL[2*k]), + .data_add1_i(data_add_LEVEL[2*k+1]), + .data_req0_i(data_req_LEVEL[2*k]), + .data_req1_i(data_req_LEVEL[2*k+1]), + .data_wen0_i(data_wen_LEVEL[2*k]), + .data_wen1_i(data_wen_LEVEL[2*k+1]), + .data_atop0_i(data_atop_LEVEL[2*k]), + .data_atop1_i(data_atop_LEVEL[2*k+1]), + .data_ID0_i(data_ID_LEVEL[2*k]), + .data_ID1_i(data_ID_LEVEL[2*k+1]), + .data_be0_i(data_be_LEVEL[2*k]), + .data_be1_i(data_be_LEVEL[2*k+1]), + `ifdef GNT_BASED_FC + .data_gnt0_o(data_gnt_LEVEL[2*k]), + .data_gnt1_o(data_gnt_LEVEL[2*k+1]), + `else + .data_stall0_o(data_stall_LEVEL[2*k]), + .data_stall1_o(data_stall_LEVEL[2*k+1]), + `endif + // RIGTH SIDE + .data_wdata_o(data_wdata_o), + .data_add_o(data_add_o), + .data_req_o(data_req_o), + .data_wen_o(data_wen_o), + .data_atop_o(data_atop_o), + .data_ID_o(data_ID_o), + .data_be_o(data_be_o), + `ifdef GNT_BASED_FC + .data_gnt_i(data_gnt_i) + `else + .data_stall_i(data_stall_i) + `endif + ); + end + else if ( j < LOG_MASTER - 1) // Middle Nodes + begin : MIDDLE_NODES // START of MIDDLE LEVELS Nodes + FanInPrimitive_Req_PE + #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ) + ) + i_FanInPrimitive_Req_PE + ( + .RR_FLAG(RR_FLAG[LOG_MASTER-j-1]), + // LEFT SIDE + .data_wdata0_i (data_wdata_LEVEL[((2**j)*2-2) + 2*k]), + .data_wdata1_i (data_wdata_LEVEL[((2**j)*2-2) + 2*k +1]), + .data_add0_i (data_add_LEVEL[((2**j)*2-2) + 2*k]), + .data_add1_i (data_add_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_req0_i (data_req_LEVEL[((2**j)*2-2) + 2*k]), + .data_req1_i (data_req_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_wen0_i (data_wen_LEVEL[((2**j)*2-2) + 2*k]), + .data_wen1_i (data_wen_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_atop0_i (data_atop_LEVEL[((2**j)*2-2) + 2*k]), + .data_atop1_i (data_atop_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_ID0_i (data_ID_LEVEL[((2**j)*2-2) + 2*k]), + .data_ID1_i (data_ID_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_be0_i (data_be_LEVEL[((2**j)*2-2) + 2*k]), + .data_be1_i (data_be_LEVEL[((2**j)*2-2) + 2*k+1]), + `ifdef GNT_BASED_FC + .data_gnt0_o (data_gnt_LEVEL[((2**j)*2-2) + 2*k]), + .data_gnt1_o (data_gnt_LEVEL[((2**j)*2-2) + 2*k+1]), + `else + .data_stall0_o (data_stall_LEVEL[((2**j)*2-2) + 2*k]), + .data_stall1_o (data_stall_LEVEL[((2**j)*2-2) + 2*k+1]), + `endif + + // RIGTH SIDE + .data_wdata_o(data_wdata_LEVEL[((2**(j-1))*2-2) + k]), + .data_add_o(data_add_LEVEL[((2**(j-1))*2-2) + k]), + .data_req_o(data_req_LEVEL[((2**(j-1))*2-2) + k]), + .data_wen_o(data_wen_LEVEL[((2**(j-1))*2-2) + k]), + .data_atop_o(data_atop_LEVEL[((2**(j-1))*2-2) + k]), + .data_ID_o(data_ID_LEVEL[((2**(j-1))*2-2) + k]), + .data_be_o(data_be_LEVEL[((2**(j-1))*2-2) + k]), + `ifdef GNT_BASED_FC + .data_gnt_i(data_gnt_LEVEL[((2**(j-1))*2-2) + k]) + `else + .data_stall_i(data_stall_LEVEL[((2**(j-1))*2-2) + k]) + `endif + ); + end // END of MIDDLE LEVELS Nodes + else // First stage (connected with the Main inputs ) --> ( j == N_MASTER - 1 ) + begin : LEAF_NODES // START of FIRST LEVEL Nodes (LEAF) + FanInPrimitive_Req_PE + #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ) + ) + i_FanInPrimitive_Req_PE + ( + .RR_FLAG(RR_FLAG[LOG_MASTER-j-1]), + // LEFT SIDE + .data_wdata0_i(data_wdata_i[2*k]), + .data_wdata1_i(data_wdata_i[2*k+1]), + .data_add0_i(data_add_i[2*k]), + .data_add1_i(data_add_i[2*k+1]), + .data_req0_i(data_req_i[2*k]), + .data_req1_i(data_req_i[2*k+1]), + .data_wen0_i(data_wen_i[2*k]), + .data_wen1_i(data_wen_i[2*k+1]), + .data_atop0_i(data_atop_i[2*k]), + .data_atop1_i(data_atop_i[2*k+1]), + .data_ID0_i(data_ID_i[2*k]), + .data_ID1_i(data_ID_i[2*k+1]), + .data_be0_i(data_be_i[2*k]), + .data_be1_i(data_be_i[2*k+1]), + `ifdef GNT_BASED_FC + .data_gnt0_o(data_gnt_o[2*k]), + .data_gnt1_o(data_gnt_o[2*k+1]), + `else + .data_stall0_o(data_stall_o[2*k]), + .data_stall1_o(data_stall_o[2*k+1]), + `endif + + // RIGTH SIDE + .data_wdata_o(data_wdata_LEVEL[((2**(j-1))*2-2) + k]), + .data_add_o(data_add_LEVEL[((2**(j-1))*2-2) + k]), + .data_req_o(data_req_LEVEL[((2**(j-1))*2-2) + k]), + .data_wen_o(data_wen_LEVEL[((2**(j-1))*2-2) + k]), + .data_atop_o(data_atop_LEVEL[((2**(j-1))*2-2) + k]), + .data_ID_o(data_ID_LEVEL[((2**(j-1))*2-2) + k]), + .data_be_o(data_be_LEVEL[((2**(j-1))*2-2) + k]), + `ifdef GNT_BASED_FC + .data_gnt_i(data_gnt_LEVEL[((2**(j-1))*2-2) + k]) + `else + .data_stall_i(data_stall_LEVEL[((2**(j-1))*2-2) + k]) + `endif + ); + end // End of FIRST LEVEL Nodes (LEAF) + end + + end + + end + endgenerate + + //COUNTER USED TO SWITCH PERIODICALLY THE PRIORITY FLAG" + RR_Flag_Req_PE + #( + .WIDTH(LOG_MASTER), + .MAX_COUNT(MAX_COUNT) + ) + RR_REQ + ( + .clk(clk), + .rst_n(rst_n), + .RR_FLAG_o(RR_FLAG), + .data_req_i(data_req_o), + `ifdef GNT_BASED_FC + .data_gnt_i(data_gnt_i) + `else + .data_stall_i(data_stall_i) + `endif + ); + + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv new file mode 100644 index 0000000..9959c99 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv @@ -0,0 +1,87 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 29/06/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: FanInPrimitive_Resp // +// Language: SystemVerilog // +// // +// Description: Routing primitives used to build the Routing trees. // +// They are part of the response network // +// // +// // +// Revision: // +// Revision v0.1 02/07/2011 - File Created // +// v0.2 15/08/2012 - Improved the Interface Structure, // +// Changed the routing mechanism // +// Revision v0.3 19/02/2015 - Code Restyling // +// // +// // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + + +`include "parameters.v" + +module FanInPrimitive_PE_Resp +#( + parameter DATA_WIDTH = 32 +) +( + // UPSTREAM SIDE + input logic [DATA_WIDTH-1:0] data_r_rdata0_i, + input logic [DATA_WIDTH-1:0] data_r_rdata1_i, + input logic data_r_valid0_i, + input logic data_r_valid1_i, + input logic data_r_opc0_i, + input logic data_r_opc1_i, + + // DOWNSTREAM SIDE + output logic [DATA_WIDTH-1:0] data_r_rdata_o, + output logic data_r_valid_o, + output logic data_r_opc_o +); + + // Selector for the FanOut multiplexer + logic SEL; + + // VAlid is simply the or of the two requests + assign data_r_valid_o = data_r_valid1_i | data_r_valid0_i; + + // FIXME: (req0 & req1) must be always 0 + assign SEL = data_r_valid1_i; + + + // SEL CONTROLLER + always_comb + begin : FanOut_MUX2 + case(SEL) + 1'b0: begin data_r_rdata_o = data_r_rdata0_i; data_r_opc_o = data_r_opc0_i; end + 1'b1: begin data_r_rdata_o = data_r_rdata1_i; data_r_opc_o = data_r_opc1_i; end + endcase + end +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv new file mode 100644 index 0000000..5f51062 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv @@ -0,0 +1,137 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 29/06/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: FanInPrimitive_Req // +// Project Name: MegaLEON // +// Language: SystemVerilog // +// // +// Description: Arbitration primitives used to build the arbitration trees.// +// They are part of the request network with a distributed // +// arbiter. The arbitration Algorithm is ROUND ROBIN // +// // +// // +// Revision: // +// Revision v0.1 - File Created // +// Revision v0.2 - Code Restyling (19/02/2015) // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + + +module FanInPrimitive_Req_PE +#( + parameter ADDR_WIDTH = 32, + parameter ID_WIDTH = 16, + parameter DATA_WIDTH = 32, + parameter BE_WIDTH = DATA_WIDTH/8 +) +( + input logic RR_FLAG, + + // LEFT SIDE + input logic [DATA_WIDTH-1:0] data_wdata0_i, + input logic [DATA_WIDTH-1:0] data_wdata1_i, + input logic [ADDR_WIDTH-1:0] data_add0_i, + input logic [ADDR_WIDTH-1:0] data_add1_i, + input logic data_req0_i, + input logic data_req1_i, + input logic data_wen0_i, + input logic data_wen1_i, + input logic [5:0] data_atop0_i, + input logic [5:0] data_atop1_i, + input logic [BE_WIDTH-1:0] data_be0_i, + input logic [BE_WIDTH-1:0] data_be1_i, + input logic [ID_WIDTH-1:0] data_ID0_i, + input logic [ID_WIDTH-1:0] data_ID1_i, +`ifdef GNT_BASED_FC + output logic data_gnt0_o, + output logic data_gnt1_o, +`else + output logic data_stall0_o, + output logic data_stall1_o, +`endif + // RIGTH SIDE + output logic [DATA_WIDTH-1:0] data_wdata_o, + output logic [ADDR_WIDTH-1:0] data_add_o, + output logic data_req_o, + output logic [ID_WIDTH-1:0] data_ID_o, + output logic data_wen_o, + output logic [5:0] data_atop_o, + output logic [BE_WIDTH-1:0] data_be_o, +`ifdef GNT_BASED_FC + input logic data_gnt_i +`else + input logic data_stall_i +`endif +); + + logic SEL; + + assign data_req_o = data_req0_i | data_req1_i; + assign SEL = ~data_req0_i | ( RR_FLAG & data_req1_i); // SEL FOR ROUND ROBIN MUX + + `ifdef GNT_BASED_FC + // Grant gnt0 and gnt1 + assign data_gnt0_o = (( data_req0_i & ~data_req1_i) | ( data_req0_i & ~RR_FLAG)) & data_gnt_i; + assign data_gnt1_o = ((~data_req0_i & data_req1_i) | ( data_req1_i & RR_FLAG)) & data_gnt_i; + `else + // Data stall0 and stall1 + assign data_stall0_o = (data_req0_i & data_req1_i & RR_FLAG) | ((( data_req0_i & ~data_req1_i) | ( data_req0_i & ~RR_FLAG)) & data_stall_i); + assign data_stall1_o = (data_req0_i & data_req1_i & ~RR_FLAG) | (((~data_req0_i & data_req1_i) | ( data_req1_i & RR_FLAG)) & data_stall_i); + `endif + + //MUXES AND DEMUXES + always_comb + begin : FanIn_MUX2 + case(SEL) //synopsys full_case + 1'b0: + begin //PRIORITY ON CH_0 + data_wdata_o = data_wdata0_i; + data_add_o = data_add0_i; + data_wen_o = data_wen0_i; + data_atop_o = data_atop0_i; + data_ID_o = data_ID0_i; + data_be_o = data_be0_i; + end + + 1'b1: + begin //PRIORITY ON CH_1 + data_wdata_o = data_wdata1_i; + data_add_o = data_add1_i; + data_wen_o = data_wen1_i; + data_atop_o = data_atop1_i; + data_ID_o = data_ID1_i; + data_be_o = data_be1_i; + end + + endcase + end + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/MUX2_REQ_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/MUX2_REQ_PE.sv new file mode 100644 index 0000000..0cfd973 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/MUX2_REQ_PE.sv @@ -0,0 +1,147 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 29/06/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: MUX2_REQ // +// Language: SystemVerilog // +// // +// Description: two input multiplxer whith custom ports used to multiplex // +// the datapath request data. It includes an embeddedd // +// Fixed Priory arbiter with max priority to Channel 0 (CH0) // +// // +// // +// Revision: // +// Revision v0.1 - File Created // +// Revision v0.2 - Code Restyling (19/02/2015) // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + + +`include "parameters.v" + +module MUX2_REQ_PE +#( + parameter ID_WIDTH = 20, + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32, + parameter BE_WIDTH = DATA_WIDTH/8 +) +( + input logic data_req_CH0_i, + input logic [ADDR_WIDTH-1:0] data_add_CH0_i, + input logic data_wen_CH0_i, + input logic [5:0] data_atop_CH0_i, + input logic [DATA_WIDTH-1:0] data_wdata_CH0_i, + input logic [BE_WIDTH-1:0] data_be_CH0_i, + input logic [ID_WIDTH-1:0] data_ID_CH0_i, +`ifdef GNT_BASED_FC + output logic data_gnt_CH0_o, +`else + output logic data_stall_CH0_o, +`endif + + + input logic data_req_CH1_i, + input logic [ADDR_WIDTH-1:0] data_add_CH1_i, + input logic data_wen_CH1_i, + input logic [5:0] data_atop_CH1_i, + input logic [DATA_WIDTH-1:0] data_wdata_CH1_i, + input logic [BE_WIDTH-1:0] data_be_CH1_i, + input logic [ID_WIDTH-1:0] data_ID_CH1_i, +`ifdef GNT_BASED_FC + output logic data_gnt_CH1_o, +`else + output logic data_stall_CH1_o, +`endif + + output logic data_req_o, + output logic [ADDR_WIDTH-1:0] data_add_o, + output logic data_wen_o, + output logic [5:0] data_atop_o, + output logic [DATA_WIDTH-1:0] data_wdata_o, + output logic [BE_WIDTH-1:0] data_be_o, + output logic [ID_WIDTH-1:0] data_ID_o, +`ifdef GNT_BASED_FC + input logic data_gnt_i, +`else + input logic data_stall_i, +`endif + + input logic clk, + input logic rst_n +); + + logic SEL; // Mux Selector + logic RR_FLAG; + + // Request is simply an or between indoming request + assign data_req_o = data_req_CH0_i | data_req_CH1_i; + + // FIXED PRIORITY ENCODER + assign SEL = ~data_req_CH0_i | ( RR_FLAG & data_req_CH1_i); // SEL FOR ROUND ROBIN MUX +`ifdef GNT_BASED_FC + assign data_gnt_CH0_o = (( data_req_CH0_i & ~data_req_CH1_i) | ( data_req_CH0_i & ~RR_FLAG)) & data_gnt_i; + assign data_gnt_CH1_o = ((~data_req_CH0_i & data_req_CH1_i) | ( data_req_CH1_i & RR_FLAG)) & data_gnt_i; +`else + assign data_stall_CH0_o = (data_req_CH0_i & data_req_CH1_i & RR_FLAG) | ((( data_req_CH0_i & ~data_req_CH1_i) | ( data_req_CH0_i & ~RR_FLAG)) & data_stall_i); + assign data_stall_CH1_o = (data_req_CH0_i & data_req_CH1_i & ~RR_FLAG) | (((~data_req_CH0_i & data_req_CH1_i) | ( data_req_CH1_i & RR_FLAG)) & data_stall_i); +`endif + + always_ff @(posedge clk, negedge rst_n) + begin + if(rst_n == 1'b0) + RR_FLAG <= 1'b0; + else if((data_req_o == 1'b1) && `ifdef GNT_BASED_FC (data_gnt_i == 1'b1) `else (data_stall_i == 1'b0) `endif) + RR_FLAG <= ~RR_FLAG; + end + + always_comb + begin : MUX2_REQ_COMB + case(SEL) // synopsys full_case + 1'b0: + begin + data_add_o = data_add_CH0_i; + data_wen_o = data_wen_CH0_i; + data_atop_o = data_atop_CH0_i; + data_wdata_o = data_wdata_CH0_i; + data_be_o = data_be_CH0_i; + data_ID_o = data_ID_CH0_i; + end + + 1'b1: + begin + data_add_o = data_add_CH1_i; + data_wen_o = data_wen_CH1_i; + data_atop_o = data_atop_CH1_i; + data_wdata_o = data_wdata_CH1_i; + data_be_o = data_be_CH1_i; + data_ID_o = data_ID_CH1_i; + end + endcase + end +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/RR_Flag_Req_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/RR_Flag_Req_PE.sv new file mode 100644 index 0000000..b2c03be --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/RR_Flag_Req_PE.sv @@ -0,0 +1,87 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 29/06/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: RR_Flag_Req // +// Project Name: MegaLEON // +// Language: SystemVerilog // +// // +// Description: Round Robing FLAG generator for the arbitration trees. // +// The values ( RR_FLAG_REQ ) is update only when request and // +// grant are high. This allow to avoid high sw activity when // +// there is no valid traffic. Allows for clock gating // +// insertion // +// // +// Revision: // +// Revision v0.1 - File Created // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + + +module RR_Flag_Req_PE +#( + parameter WIDTH = 3, + parameter MAX_COUNT = 2**WIDTH-1 +) +( + input logic clk, + input logic rst_n, + output logic [WIDTH-1:0] RR_FLAG_o, + input logic data_req_i, +`ifdef GNT_BASED_FC + input logic data_gnt_i +`else + input logic data_stall_i +`endif +); + + + + + always_ff @(posedge clk, negedge rst_n) + begin : RR_Flag_Req_SEQ + if(rst_n == 1'b0) + RR_FLAG_o <= '0; + else + `ifdef GNT_BASED_FC + if( data_req_i & data_gnt_i ) + `else + if( data_req_i & ~data_stall_i ) + `endif + begin + if(RR_FLAG_o < MAX_COUNT) + RR_FLAG_o <= RR_FLAG_o + 1'b1; + else + RR_FLAG_o <= '0; + end + end + + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/RequestBlock2CH_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/RequestBlock2CH_PE.sv new file mode 100644 index 0000000..f4783fc --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/RequestBlock2CH_PE.sv @@ -0,0 +1,637 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 02/07/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: RequestBlock2CH_PE // +// Language: SystemVerilog // +// // +// Description: Request Block: it embed inside the routing trees and the // +// Multiplexer to mix the request from two channels (one // +// distributed in the several arbitration primitives that // +// compose this routing block. The arbistrtion is round robin // +// and the round robin flag generator is embedded inside this // +// block. Flag updating happens only when requests are grant // +// // +// Revision: // +// Revision v0.1 02/07/2011 - File Created // +// v0.2 14/08/2012 - Improved the Interface Structure, // +// Changed the routing mechanism // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + +// FOR TWO INPUTS +module RequestBlock2CH_PE +#( + parameter ADDR_WIDTH = 32, + parameter N_CH0 = 16, // Example Number of cores + parameter N_CH1 = 1, // Example Number of DMAs + parameter ID_WIDTH = N_CH0+N_CH1, + parameter DATA_WIDTH = 32, + parameter BE_WIDTH = DATA_WIDTH/8 +) +( + // CHANNEL CH0 --> (example: Used for cores) + input logic [N_CH0-1:0] data_req_CH0_i, + input logic [N_CH0-1:0][ADDR_WIDTH-1:0] data_add_CH0_i, + input logic [N_CH0-1:0] data_wen_CH0_i, + input logic [N_CH0-1:0][5:0] data_atop_CH0_i, + input logic [N_CH0-1:0][DATA_WIDTH-1:0] data_wdata_CH0_i, + input logic [N_CH0-1:0][BE_WIDTH-1:0] data_be_CH0_i, + input logic [N_CH0-1:0][ID_WIDTH-1:0] data_ID_CH0_i, +`ifdef GNT_BASED_FC + output logic [N_CH0-1:0] data_gnt_CH0_o, +`else + output logic [N_CH0-1:0] data_stall_CH0_o, +`endif + + // CHANNEL CH1 --> (example: Used for DMAs) + input logic [N_CH1-1:0] data_req_CH1_i, + input logic [N_CH1-1:0][ADDR_WIDTH-1:0] data_add_CH1_i, + input logic [N_CH1-1:0] data_wen_CH1_i, + input logic [N_CH1-1:0][5:0] data_atop_CH1_i, + input logic [N_CH1-1:0][DATA_WIDTH-1:0] data_wdata_CH1_i, + input logic [N_CH1-1:0][BE_WIDTH-1:0] data_be_CH1_i, + input logic [N_CH1-1:0][ID_WIDTH-1:0] data_ID_CH1_i, +`ifdef GNT_BASED_FC + output logic [N_CH1-1:0] data_gnt_CH1_o, +`else + output logic [N_CH1-1:0] data_stall_CH1_o, +`endif + + // ----------------- MEMORY ------------------- + // ---------------- RequestBlock OUTPUT (Connected to MEMORY) ---------------- + output logic data_req_o, + output logic [ADDR_WIDTH-1:0] data_add_o, + output logic data_wen_o, + output logic [5:0] data_atop_o, + output logic [DATA_WIDTH-1:0] data_wdata_o, + output logic [BE_WIDTH-1:0] data_be_o, + output logic [ID_WIDTH-1:0] data_ID_o, +`ifdef GNT_BASED_FC + input logic data_gnt_i, +`else + input logic data_stall_i, +`endif + input logic data_r_valid_i, + input logic [ID_WIDTH-1:0] data_r_ID_i, + + + + // GEN VALID_SIGNALS in the response path + output logic [N_CH0-1:0] data_r_valid_CH0_o, + output logic [N_CH1-1:0] data_r_valid_CH1_o, + + input logic clk, + input logic rst_n + + ); + + // OUT CHANNEL CH0 --> (example: Used for cores) + logic data_req_CH0; + logic [ADDR_WIDTH-1:0] data_add_CH0; + logic data_wen_CH0; + logic [5:0] data_atop_CH0; + logic [DATA_WIDTH-1:0] data_wdata_CH0; + logic [BE_WIDTH-1:0] data_be_CH0; + logic [ID_WIDTH-1:0] data_ID_CH0; + `ifdef GNT_BASED_FC + logic data_gnt_CH0; + `else + logic data_stall_CH0; + `endif + + // OUT CHANNEL CH1 --> (example: Used for DMAs) + logic data_req_CH1; + logic [ADDR_WIDTH-1:0] data_add_CH1; + logic data_wen_CH1; + logic [5:0] data_atop_CH1; + logic [DATA_WIDTH-1:0] data_wdata_CH1; + logic [BE_WIDTH-1:0] data_be_CH1; + logic [ID_WIDTH-1:0] data_ID_CH1; + `ifdef GNT_BASED_FC + logic data_gnt_CH1; + `else + logic data_stall_CH1; + `endif + + + // CHANNEL CH0 --> (example: Used for Processing Elements / CORES) + logic [2**$clog2(N_CH0)-1:0] data_req_CH0_int; + logic [2**$clog2(N_CH0)-1:0][ADDR_WIDTH-1:0] data_add_CH0_int; + logic [2**$clog2(N_CH0)-1:0] data_wen_CH0_int; + logic [2**$clog2(N_CH0)-1:0][5:0] data_atop_CH0_int; + logic [2**$clog2(N_CH0)-1:0][DATA_WIDTH-1:0] data_wdata_CH0_int; + logic [2**$clog2(N_CH0)-1:0][BE_WIDTH-1:0] data_be_CH0_int; + logic [2**$clog2(N_CH0)-1:0][ID_WIDTH-1:0] data_ID_CH0_int; +`ifdef GNT_BASED_FC + logic [2**$clog2(N_CH0)-1:0] data_gnt_CH0_int; +`else + logic [2**$clog2(N_CH0)-1:0] data_stall_CH0_int; +`endif + + + + // CHANNEL CH0 --> (example: Used for Processing Elements / CORES) + logic [2**$clog2(N_CH1)-1:0] data_req_CH1_int; + logic [2**$clog2(N_CH1)-1:0][ADDR_WIDTH-1:0] data_add_CH1_int; + logic [2**$clog2(N_CH1)-1:0] data_wen_CH1_int; + logic [2**$clog2(N_CH1)-1:0][5:0] data_atop_CH1_int; + logic [2**$clog2(N_CH1)-1:0][DATA_WIDTH-1:0] data_wdata_CH1_int; + logic [2**$clog2(N_CH1)-1:0][BE_WIDTH-1:0] data_be_CH1_int; + logic [2**$clog2(N_CH1)-1:0][ID_WIDTH-1:0] data_ID_CH1_int; +`ifdef GNT_BASED_FC + logic [2**$clog2(N_CH1)-1:0] data_gnt_CH1_int; +`else + logic [2**$clog2(N_CH1)-1:0] data_stall_CH1_int; +`endif + + + + + generate + + + if(2**$clog2(N_CH0) != N_CH0) // if N_CH0 is not power of 2 --> then use power 2 ports + begin : _DUMMY_CH0_PORTS_ + + logic [2**$clog2(N_CH0)-N_CH0 -1 :0] data_req_CH0_dummy; + logic [2**$clog2(N_CH0)-N_CH0 -1 :0][ADDR_WIDTH-1:0] data_add_CH0_dummy; // Memory address + T&S bit + logic [2**$clog2(N_CH0)-N_CH0 -1 :0] data_wen_CH0_dummy; + logic [2**$clog2(N_CH0)-N_CH0 -1 :0][5:0] data_atop_CH0_dummy; + logic [2**$clog2(N_CH0)-N_CH0 -1 :0][DATA_WIDTH-1:0] data_wdata_CH0_dummy; + logic [2**$clog2(N_CH0)-N_CH0 -1 :0][BE_WIDTH-1:0] data_be_CH0_dummy; + logic [2**$clog2(N_CH0)-N_CH0 -1 :0][ID_WIDTH-1:0] data_ID_CH0_dummy; + `ifdef GNT_BASED_FC + logic [2**$clog2(N_CH0)-N_CH0 -1 :0] data_gnt_CH0_dummy; + `else + logic [2**$clog2(N_CH0)-N_CH0 -1 :0] data_stall_CH0_dummy; + `endif + + assign data_req_CH0_dummy = '0 ; + assign data_add_CH0_dummy = '0 ; + assign data_wen_CH0_dummy = '0 ; + assign data_atop_CH0_dummy = '0 ; + assign data_wdata_CH0_dummy = '0 ; + assign data_be_CH0_dummy = '0 ; + assign data_ID_CH0_dummy = '0 ; + + assign data_req_CH0_int = { data_req_CH0_dummy , data_req_CH0_i }; + assign data_add_CH0_int = { data_add_CH0_dummy , data_add_CH0_i }; + assign data_wen_CH0_int = { data_wen_CH0_dummy , data_wen_CH0_i }; + assign data_atop_CH0_int = { data_atop_CH0_dummy , data_atop_CH0_i }; + assign data_wdata_CH0_int = { data_wdata_CH0_dummy , data_wdata_CH0_i }; + assign data_be_CH0_int = { data_be_CH0_dummy , data_be_CH0_i }; + assign data_ID_CH0_int = { data_ID_CH0_dummy , data_ID_CH0_i }; + + + for(genvar j=0; j then use power 2 ports + begin : _DUMMY_CH1_PORTS_ + + logic [2**$clog2(N_CH1)-N_CH1 -1 :0] data_req_CH1_dummy; + logic [2**$clog2(N_CH1)-N_CH1 -1 :0][ADDR_WIDTH-1:0] data_add_CH1_dummy; // Memory address + T&S bit + logic [2**$clog2(N_CH1)-N_CH1 -1 :0] data_wen_CH1_dummy; + logic [2**$clog2(N_CH1)-N_CH1 -1 :0][5:0] data_atop_CH1_dummy; + logic [2**$clog2(N_CH1)-N_CH1 -1 :0][DATA_WIDTH-1:0] data_wdata_CH1_dummy; + logic [2**$clog2(N_CH1)-N_CH1 -1 :0][BE_WIDTH-1:0] data_be_CH1_dummy; + logic [2**$clog2(N_CH1)-N_CH1 -1 :0][ID_WIDTH-1:0] data_ID_CH1_dummy; + `ifdef GNT_BASED_FC + logic [2**$clog2(N_CH1)-N_CH1 -1 :0] data_gnt_CH1_dummy; + `else + logic [2**$clog2(N_CH1)-N_CH1 -1 :0] data_stall_CH1_dummy; + `endif + + assign data_req_CH1_dummy = '0 ; + assign data_add_CH1_dummy = '0 ; + assign data_wen_CH1_dummy = '0 ; + assign data_atop_CH1_dummy = '0 ; + assign data_wdata_CH1_dummy = '0 ; + assign data_be_CH1_dummy = '0 ; + assign data_ID_CH1_dummy = '0 ; + + assign data_req_CH1_int = { data_req_CH1_dummy , data_req_CH1_i }; + assign data_add_CH1_int = { data_add_CH1_dummy , data_add_CH1_i }; + assign data_wen_CH1_int = { data_wen_CH1_dummy , data_wen_CH1_i }; + assign data_atop_CH1_int = { data_atop_CH1_dummy , data_atop_CH1_i }; + assign data_wdata_CH1_int = { data_wdata_CH1_dummy , data_wdata_CH1_i }; + assign data_be_CH1_int = { data_be_CH1_dummy , data_be_CH1_i }; + assign data_ID_CH1_int = { data_ID_CH1_dummy , data_ID_CH1_i }; + + + for(genvar j=0; j 1) + begin : CH0_ARB_TREE + ArbitrationTree_PE + #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .N_MASTER ( N_CH0 ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .MAX_COUNT ( N_CH0 - 1 ) + ) + i_ArbitrationTree_PE + ( + .clk ( clk ), + .rst_n ( rst_n ), + // INPUTS + .data_req_i ( data_req_CH0_int ), + .data_add_i ( data_add_CH0_int ), + .data_wen_i ( data_wen_CH0_int ), + .data_atop_i ( data_atop_CH0_int ), + .data_wdata_i ( data_wdata_CH0_int ), + .data_be_i ( data_be_CH0_int ), + .data_ID_i ( data_ID_CH0_int ), + `ifdef GNT_BASED_FC + .data_gnt_o ( data_gnt_CH0_int ), + `else + .data_stall_o ( data_stall_CH0_int ), + `endif + // OUTPUTS + .data_req_o ( data_req_CH0 ), + .data_add_o ( data_add_CH0 ), + .data_wen_o ( data_wen_CH0 ), + .data_atop_o ( data_atop_CH0 ), + .data_wdata_o ( data_wdata_CH0 ), + .data_be_o ( data_be_CH0 ), + .data_ID_o ( data_ID_CH0 ), + `ifdef GNT_BASED_FC + .data_gnt_i ( data_gnt_CH0 ) + `else + .data_stall_i ( data_stall_CH0 ) + `endif + ); + end + + if(N_CH1 > 1) + begin : CH1_ARB_TREE + ArbitrationTree_PE + #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .N_MASTER ( N_CH1 ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .MAX_COUNT ( N_CH1 - 1 ) + ) + i_ArbitrationTree_PE + ( + .clk ( clk ), + .rst_n ( rst_n ), + // INPUTS + .data_req_i ( data_req_CH1_int ), + .data_add_i ( data_add_CH1_int ), + .data_wen_i ( data_wen_CH1_int ), + .data_atop_i ( data_atop_CH1_int ), + .data_wdata_i ( data_wdata_CH1_int ), + .data_be_i ( data_be_CH1_int ), + .data_ID_i ( data_ID_CH1_int ), + `ifdef GNT_BASED_FC + .data_gnt_o ( data_gnt_CH1_int ), + `else + .data_stall_o ( data_stall_CH1_int ), + `endif + // OUTPUTS + .data_req_o ( data_req_CH1 ), + .data_add_o ( data_add_CH1 ), + .data_wen_o ( data_wen_CH1 ), + .data_atop_o ( data_atop_CH1 ), + .data_wdata_o ( data_wdata_CH1 ), + .data_be_o ( data_be_CH1 ), + .data_ID_o ( data_ID_CH1 ), + `ifdef GNT_BASED_FC + .data_gnt_i ( data_gnt_CH1 ) + `else + .data_stall_i ( data_stall_CH1 ) + `endif + ); + end + + if(N_CH1 == 1) + begin : MONO_CH1 + if(N_CH0 == 1) + begin : MONO_CH0 + MUX2_REQ_PE + #( + .ID_WIDTH ( ID_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( DATA_WIDTH/8 ) + ) + i_MUX2_REQ_PE + ( + // CH0 input + .data_req_CH0_i ( data_req_CH0_int ), + .data_add_CH0_i ( data_add_CH0_int ), + .data_wen_CH0_i ( data_wen_CH0_int ), + .data_atop_CH0_i ( data_atop_CH0_int ), + .data_wdata_CH0_i ( data_wdata_CH0_int ), + .data_be_CH0_i ( data_be_CH0_int ), + .data_ID_CH0_i ( data_ID_CH0_int ), + `ifdef GNT_BASED_FC + .data_gnt_CH0_o ( data_gnt_CH0_int ), + `else + .data_stall_CH0_o ( data_stall_CH0_int ), + `endif + // CH1 input + .data_req_CH1_i ( data_req_CH1_int ), + .data_add_CH1_i ( data_add_CH1_int ), + .data_wen_CH1_i ( data_wen_CH1_int ), + .data_atop_CH1_i ( data_atop_CH1_int ), + .data_wdata_CH1_i ( data_wdata_CH1_int ), + .data_be_CH1_i ( data_be_CH1_int ), + .data_ID_CH1_i ( data_ID_CH1_int ), + `ifdef GNT_BASED_FC + .data_gnt_CH1_o ( data_gnt_CH1_int ), + `else + .data_stall_CH1_o ( data_stall_CH1_int ), + `endif + // MUX output + .data_req_o ( data_req_o ), + .data_add_o ( data_add_o ), + .data_wen_o ( data_wen_o ), + .data_atop_o ( data_atop_o ), + .data_wdata_o ( data_wdata_o ), + .data_be_o ( data_be_o ), + .data_ID_o ( data_ID_o ), + `ifdef GNT_BASED_FC + .data_gnt_i ( data_gnt_i ), + `else + .data_stall_i ( data_stall_i ), + `endif + .clk ( clk ), + .rst_n ( rst_n ) + ); + end // END MONO_CH0 + else + begin : POLY_CH0 + MUX2_REQ_PE + #( + .ID_WIDTH ( ID_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( DATA_WIDTH/8 ) + ) + i_MUX2_REQ_PE + ( + // CH0 input + .data_req_CH0_i ( data_req_CH0 ), + .data_add_CH0_i ( data_add_CH0 ), + .data_wen_CH0_i ( data_wen_CH0 ), + .data_atop_CH0_i ( data_atop_CH0 ), + .data_wdata_CH0_i ( data_wdata_CH0 ), + .data_be_CH0_i ( data_be_CH0 ), + .data_ID_CH0_i ( data_ID_CH0 ), + `ifdef GNT_BASED_FC + .data_gnt_CH0_o ( data_gnt_CH0 ), + `else + .data_stall_CH0_o ( data_stall_CH0 ), + `endif + // CH1 input + .data_req_CH1_i ( data_req_CH1_int ), + .data_add_CH1_i ( data_add_CH1_int ), + .data_wen_CH1_i ( data_wen_CH1_int ), + .data_atop_CH1_i ( data_atop_CH1_int ), + .data_wdata_CH1_i ( data_wdata_CH1_int ), + .data_be_CH1_i ( data_be_CH1_int ), + .data_ID_CH1_i ( data_ID_CH1_int ), + `ifdef GNT_BASED_FC + .data_gnt_CH1_o ( data_gnt_CH1_int ), + `else + .data_stall_CH1_o ( data_stall_CH1_int ), + `endif + // MUX output + .data_req_o ( data_req_o ), + .data_add_o ( data_add_o ), + .data_wen_o ( data_wen_o ), + .data_atop_o ( data_atop_o ), + .data_wdata_o ( data_wdata_o ), + .data_be_o ( data_be_o ), + .data_ID_o ( data_ID_o ), + `ifdef GNT_BASED_FC + .data_gnt_i ( data_gnt_i ), + `else + .data_stall_i ( data_stall_i ), + `endif + .clk ( clk ), + .rst_n ( rst_n ) + ); + end // END POLY_CH0 + end + else + begin : POLY_CH1 + if(N_CH0 == 1) + begin : MONO_CH0 + MUX2_REQ_PE + #( + .ID_WIDTH ( ID_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( DATA_WIDTH/8 ) + ) + i_MUX2_REQ_PE + ( + // CH0 input + .data_req_CH0_i ( data_req_CH0_int ), + .data_add_CH0_i ( data_add_CH0_int ), + .data_wen_CH0_i ( data_wen_CH0_int ), + .data_atop_CH0_i ( data_atop_CH0_int ), + .data_wdata_CH0_i ( data_wdata_CH0_int ), + .data_be_CH0_i ( data_be_CH0_int ), + .data_ID_CH0_i ( data_ID_CH0_int ), + `ifdef GNT_BASED_FC + .data_gnt_CH0_o ( data_gnt_CH0_int ), + `else + .data_stall_CH0_o ( data_stall_CH0_int ), + `endif + // CH1 input + .data_req_CH1_i ( data_req_CH1 ), + .data_add_CH1_i ( data_add_CH1 ), + .data_wen_CH1_i ( data_wen_CH1 ), + .data_atop_CH1_i ( data_atop_CH1 ), + .data_wdata_CH1_i ( data_wdata_CH1 ), + .data_be_CH1_i ( data_be_CH1 ), + .data_ID_CH1_i ( data_ID_CH1 ), + `ifdef GNT_BASED_FC + .data_gnt_CH1_o ( data_gnt_CH1 ), + `else + .data_stall_CH1_o ( data_stall_CH1 ), + `endif + // MUX output + .data_req_o ( data_req_o ), + .data_add_o ( data_add_o ), + .data_wen_o ( data_wen_o ), + .data_atop_o ( data_atop_o ), + .data_wdata_o ( data_wdata_o ), + .data_be_o ( data_be_o ), + .data_ID_o ( data_ID_o ), + `ifdef GNT_BASED_FC + .data_gnt_i ( data_gnt_i ), + `else + .data_stall_i ( data_stall_i ), + `endif + .clk ( clk ), + .rst_n ( rst_n ) + ); + end + else + begin : POLY_CH0 + MUX2_REQ_PE + #( + .ID_WIDTH ( ID_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( DATA_WIDTH/8 ) + ) + i_MUX2_REQ_PE + ( + // CH0 input + .data_req_CH0_i ( data_req_CH0 ), + .data_add_CH0_i ( data_add_CH0 ), + .data_wen_CH0_i ( data_wen_CH0 ), + .data_atop_CH0_i ( data_atop_CH0 ), + .data_wdata_CH0_i ( data_wdata_CH0 ), + .data_be_CH0_i ( data_be_CH0 ), + .data_ID_CH0_i ( data_ID_CH0 ), + `ifdef GNT_BASED_FC + .data_gnt_CH0_o ( data_gnt_CH0 ), + `else + .data_stall_CH0_o ( data_stall_CH0 ), + `endif + // CH1 input + .data_req_CH1_i ( data_req_CH1 ), + .data_add_CH1_i ( data_add_CH1 ), + .data_wen_CH1_i ( data_wen_CH1 ), + .data_atop_CH1_i ( data_atop_CH1 ), + .data_wdata_CH1_i ( data_wdata_CH1 ), + .data_be_CH1_i ( data_be_CH1 ), + .data_ID_CH1_i ( data_ID_CH1 ), + `ifdef GNT_BASED_FC + .data_gnt_CH1_o ( data_gnt_CH1 ), + `else + .data_stall_CH1_o ( data_stall_CH1 ), + `endif + // MUX output + .data_req_o ( data_req_o ), + .data_add_o ( data_add_o ), + .data_wen_o ( data_wen_o ), + .data_atop_o ( data_atop_o ), + .data_wdata_o ( data_wdata_o ), + .data_be_o ( data_be_o ), + .data_ID_o ( data_ID_o ), + `ifdef GNT_BASED_FC + .data_gnt_i ( data_gnt_i ), + `else + .data_stall_i ( data_stall_i ), + `endif + .clk ( clk ), + .rst_n ( rst_n ) + ); + end + end + endgenerate + + + + + AddressDecoder_Resp_PE + #( + .ID_WIDTH(ID_WIDTH), + .N_MASTER(N_CH0+N_CH1) + ) + i_AddressDecoder_Resp_PE + ( + // FROM Test And Set Interface + .data_r_valid_i(data_r_valid_i), + .data_ID_i(data_r_ID_i), + // To Response Network + .data_r_valid_o({data_r_valid_CH1_o,data_r_valid_CH0_o}) + ); + + + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/ResponseBlock_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/ResponseBlock_PE.sv new file mode 100644 index 0000000..b45141e --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/ResponseBlock_PE.sv @@ -0,0 +1,150 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 02/07/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: ResponseBlock_PE // +// Language: SystemVerilog // +// // +// Description: Response block that embeds address request address decoder // +// and Response tree. // +// // +// Revision: // +// Revision v0.1 02/07/2011 - File Created // +// v0.2 15/08/2012 - Improved the Interface Structure, // +// Changed the routing mechanism // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + + + +`include "parameters.v" + +module ResponseBlock_PE +#( + parameter int ID = 1, + parameter int ID_WIDTH = 17, + parameter int N_SLAVE = 16, + + parameter int DATA_WIDTH = 32, + + parameter int LOG_CLUSTER = 5, + parameter int ADDR_WIDTH = 32, + parameter int PE_ROUTING_LSB = 16, + parameter int PE_ROUTING_MSB = 19, + parameter bit CLUSTER_ALIAS = 1'b0, + parameter int CLUSTER_ALIAS_BASE = 12'h000 +) +( + input logic [LOG_CLUSTER-1:0] CLUSTER_ID, + // -----------------------------------------------------------// + // Response HANDLING + // -----------------------------------------------------------// + // Signals from Memory cuts + input logic [N_SLAVE-1:0] data_r_valid_i, + input logic [N_SLAVE-1:0][DATA_WIDTH-1:0] data_r_rdata_i, + input logic [N_SLAVE-1:0] data_r_opc_i, + + // Output of the ResponseTree Block + output logic data_r_valid_o, + output logic [DATA_WIDTH-1:0] data_r_rdata_o, + output logic data_r_opc_o, + + // -----------------------------------------------------------// + // Request HANDLING + // -----------------------------------------------------------// + input logic data_req_i, + input logic [ADDR_WIDTH-1:0] data_add_i, + `ifdef GNT_BASED_FC + output logic data_gnt_o, + `else + output logic data_stall_o, + `endif + + + output logic [N_SLAVE-1:0] data_req_o, + `ifdef GNT_BASED_FC + input logic [N_SLAVE-1:0] data_gnt_i, + `else + input logic [N_SLAVE-1:0] data_stall_i, + `endif + output logic [ID_WIDTH-1:0] data_ID_o +); + + + + // Response Tree + ResponseTree_PE + #( + .N_SLAVE(N_SLAVE), + .DATA_WIDTH(DATA_WIDTH) + ) + i_ResponseTree_PE + ( + // Response Input Channel + .data_r_valid_i(data_r_valid_i), + .data_r_rdata_i(data_r_rdata_i), + .data_r_opc_i(data_r_opc_i), + // Response Output Channel + .data_r_valid_o(data_r_valid_o), + .data_r_rdata_o(data_r_rdata_o), + .data_r_opc_o(data_r_opc_o) + ); + + + AddressDecoder_PE_Req + #( + .ID_WIDTH ( ID_WIDTH ), + .ID ( ID ), + .N_SLAVE ( N_SLAVE ), + .LOG_CLUSTER ( LOG_CLUSTER ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .PE_ROUTING_LSB ( PE_ROUTING_LSB ), + .PE_ROUTING_MSB ( PE_ROUTING_MSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .CLUSTER_ALIAS_BASE (CLUSTER_ALIAS_BASE) + ) + i_AddressDecoder_PE_Req + ( + .CLUSTER_ID(CLUSTER_ID), // CLUSTER_ID is an input!! no Longer a parameter!!! + // MASTER SIDE + .data_req_i(data_req_i), // Request from MASTER + .data_add_i(data_add_i), // Address from MASTER + `ifdef GNT_BASED_FC + .data_gnt_o(data_gnt_o), // Grant delivered to MASTER + .data_gnt_i(data_gnt_i), // Grant Array: one for each memory on ARB TREE SIDE + `else + .data_stall_o(data_stall_o), // Stall delivered to MASTER + .data_stall_i(data_stall_i), // Stall Array: one for each memory on ARB TREE SIDE + `endif + // ARB TREE SIDE + .data_req_o(data_req_o), // Request Array: one for each memory + .data_ID_o(data_ID_o) // ID is sent whit the request (like a PID) + ); + + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/ResponseTree_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/ResponseTree_PE.sv new file mode 100644 index 0000000..d737bd7 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/ResponseTree_PE.sv @@ -0,0 +1,177 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 02/07/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: ResponseTree_PE // +// Language: SystemVerilog // +// // +// Description: Peripheral Response tree: This block performs the Routing // +// between N_SLAVE requests. There is no arbitration in this // +// block. Since there is no chanche of request collision on // +// same master. Response latencies are deterministic therefore// +// the response arrive always in the same order they are sent.// +// // +// Revision: // +// Revision v0.1 02/07/2011 - File Created // +// v0.2 15/08/2012 - Improved the Interface Structure, // +// Changed the routing mechanism // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + + +module ResponseTree_PE +#( + parameter N_SLAVE = 16, + parameter DATA_WIDTH = 32 +) +( + // Response Input Channel 0 + input logic [N_SLAVE-1:0] data_r_valid_i, + input logic [N_SLAVE-1:0][DATA_WIDTH-1:0] data_r_rdata_i, + input logic [N_SLAVE-1:0] data_r_opc_i, + // Response Output Channel + output logic data_r_valid_o, + output logic [DATA_WIDTH-1:0] data_r_rdata_o, + output logic data_r_opc_o +); + + localparam LOG_SLAVE = `log2(N_SLAVE-1); + localparam N_WIRE = N_SLAVE - 2; + + genvar j,k; + + generate + + if(N_SLAVE == 2) + begin : INCR // START of N_SLAVE == 2 + // ---------------- FAN IN PRIMITIVE RESP ------------------------- + FanInPrimitive_PE_Resp + #( + .DATA_WIDTH(DATA_WIDTH) + ) + i_FanInPrimitive_PE_Resp + ( + // RIGTH SIDE + .data_r_rdata0_i ( data_r_rdata_i[0] ), + .data_r_rdata1_i ( data_r_rdata_i[1] ), + .data_r_valid0_i ( data_r_valid_i[0] ), + .data_r_valid1_i ( data_r_valid_i[1] ), + .data_r_opc0_i ( data_r_opc_i[0] ), + .data_r_opc1_i ( data_r_opc_i[1] ), + // LEFT SIDE + .data_r_rdata_o ( data_r_rdata_o ), + .data_r_valid_o ( data_r_valid_o ), + .data_r_opc_o ( data_r_opc_o ) + ); + end // END OF N_SLAVE == 2 + else // More than two master + begin : BINARY_TREE + //// ---------------------------------------------------------------------- //// + //// ------- REQ ARBITRATION TREE WIRES ----------- //// + //// ---------------------------------------------------------------------- //// + logic [DATA_WIDTH-1:0] data_r_rdata_LEVEL[N_WIRE-1:0]; + logic data_r_valid_LEVEL[N_WIRE-1:0]; + logic data_r_opc_LEVEL[N_WIRE-1:0]; + + for(j=0; j < LOG_SLAVE; j++) // Iteration for the number of the stages minus one + begin : STAGE + for(k=0; k<2**j; k=k+1) // Iteration needed to create the binary tree + begin : INCR_VERT + + if (j == 0 ) // LAST NODE, drives the module outputs + begin : LAST_NODE + FanInPrimitive_PE_Resp + #( + .DATA_WIDTH(DATA_WIDTH) + ) + i_FanInPrimitive_PE_Resp + ( + // RIGTH SIDE + .data_r_rdata0_i(data_r_rdata_LEVEL[2*k]), + .data_r_rdata1_i(data_r_rdata_LEVEL[2*k+1]), + .data_r_valid0_i(data_r_valid_LEVEL[2*k]), + .data_r_valid1_i(data_r_valid_LEVEL[2*k+1]), + .data_r_opc0_i(data_r_opc_LEVEL[2*k]), + .data_r_opc1_i(data_r_opc_LEVEL[2*k+1]), + // RIGTH SIDE + .data_r_rdata_o(data_r_rdata_o), + .data_r_valid_o(data_r_valid_o), + .data_r_opc_o(data_r_opc_o) + ); + end + else if ( j < LOG_SLAVE - 1) // Middle Nodes + begin : MIDDLE_NODES // START of MIDDLE LEVELS Nodes + FanInPrimitive_PE_Resp + #( + .DATA_WIDTH(DATA_WIDTH) + ) + i_FanInPrimitive_PE_Resp + ( + // RIGTH SIDE + .data_r_rdata0_i(data_r_rdata_LEVEL[((2**j)*2-2) + 2*k]), + .data_r_rdata1_i(data_r_rdata_LEVEL[((2**j)*2-2) + 2*k +1]), + .data_r_valid0_i(data_r_valid_LEVEL[((2**j)*2-2) + 2*k]), + .data_r_valid1_i(data_r_valid_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_r_opc0_i(data_r_opc_LEVEL[((2**j)*2-2) + 2*k]), + .data_r_opc1_i(data_r_opc_LEVEL[((2**j)*2-2) + 2*k+1]), + // LEFT SIDE + .data_r_rdata_o(data_r_rdata_LEVEL[((2**(j-1))*2-2) + k]), + .data_r_valid_o(data_r_valid_LEVEL[((2**(j-1))*2-2) + k]), + .data_r_opc_o(data_r_opc_LEVEL[((2**(j-1))*2-2) + k]) + ); + end // END of MIDDLE LEVELS Nodes + else // First stage (connected with the Main inputs ) --> ( j == N_SLAVE - 1 ) + begin : LEAF_NODES // START of FIRST LEVEL Nodes (LEAF) + FanInPrimitive_PE_Resp + #( + .DATA_WIDTH(DATA_WIDTH) + ) + i_FanInPrimitive_PE_Resp + ( + // RIGTH SIDE + .data_r_rdata0_i(data_r_rdata_i[2*k]), + .data_r_rdata1_i(data_r_rdata_i[2*k+1]), + .data_r_valid0_i(data_r_valid_i[2*k]), + .data_r_valid1_i(data_r_valid_i[2*k+1]), + .data_r_opc0_i(data_r_opc_i[2*k]), + .data_r_opc1_i(data_r_opc_i[2*k+1]), + // LEFT SIDE + .data_r_rdata_o(data_r_rdata_LEVEL[((2**(j-1))*2-2) + k]), + .data_r_valid_o(data_r_valid_LEVEL[((2**(j-1))*2-2) + k]), + .data_r_opc_o(data_r_opc_LEVEL[((2**(j-1))*2-2) + k]) + ); + end // End of FIRST LEVEL Nodes (LEAF) + end + + end + end + endgenerate + + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/peripheral_interco/XBAR_PE.sv b/hw/deps/cluster_interconnect/rtl/peripheral_interco/XBAR_PE.sv new file mode 100644 index 0000000..5cc119d --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/peripheral_interco/XBAR_PE.sv @@ -0,0 +1,316 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 03/07/2011 // +// Design Name: LOG_INTERCONNECT // +// Module Name: XBAR_PE // +// Language: SystemVerilog // +// // +// Description: Top level for the PERIPH Crossbar. It includes both the // +// Request and response Blocks. // +// // +// Revision: // +// Revision v0.1 02/07/2011 - File Created // +// v0.2 15/08/2012 - Improved the Interface Structure, // +// Changed the routing mechanism // +// v0.3 09/03/2015 - Improved identation // +// // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "parameters.v" + +module XBAR_PE +#( + parameter int N_CH0 = 16, //--> CH0 + parameter int N_CH1 = 0, //--> CH1 + parameter int N_SLAVE = 16, + parameter int ID_WIDTH = N_CH0+N_CH1, + + parameter int PE_LSB = 2, + parameter int PE_MSB = 31, + + parameter int LOG_CLUSTER = 5, + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 32, + parameter int BE_WIDTH = DATA_WIDTH/8, + + parameter int PE_ROUTING_LSB = 16, + parameter int PE_ROUTING_MSB = 19, + + parameter bit CLUSTER_ALIAS = 1'b0, + parameter int CLUSTER_ALIAS_BASE = 12'h000, + + parameter int ADDR_PE_WIDTH = PE_MSB - PE_LSB + 1 +) +( + input [LOG_CLUSTER-1:0] CLUSTER_ID, + // ---------------- MASTER CH0+CH1 SIDE -------------------------- + // Req + input logic [N_CH0+N_CH1-1:0] data_req_i, // Data request + input logic [N_CH0+N_CH1-1:0][ADDR_WIDTH-1:0] data_add_i, // Data request Address + input logic [N_CH0+N_CH1-1:0] data_wen_i, // Data request type : 0--> Store, 1 --> Load + input logic [N_CH0+N_CH1-1:0][5:0] data_atop_i, // Data request atomic operation + input logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0] data_wdata_i, // Data request Write data + input logic [N_CH0+N_CH1-1:0][BE_WIDTH-1:0] data_be_i, // Data request Byte enable +`ifdef GNT_BASED_FC + output logic [N_CH0+N_CH1-1:0] data_gnt_o, // Data request Grant +`else + output logic [N_CH0+N_CH1-1:0] data_stall_o, // Data request stall +`endif + // Resp + output logic [N_CH0+N_CH1-1:0] data_r_valid_o, // Data Response Valid (For LOAD/STORE commands) + output logic [N_CH0+N_CH1-1:0][DATA_WIDTH-1:0] data_r_rdata_o, // Data Response DATA (For LOAD commands) + output logic [N_CH0+N_CH1-1:0] data_r_opc_o, // Response Error + + + // ---------------- MM_SIDE (Interleaved) -------------------------- + // Req --> to Mem + output logic [N_SLAVE-1:0] data_req_o, // Data request + output logic [N_SLAVE-1:0][ADDR_PE_WIDTH-1:0] data_add_o, // Data request Address + output logic [N_SLAVE-1:0] data_wen_o, // Data request type : 0--> Store, 1 --> Load + output logic [N_SLAVE-1:0][5:0] data_atop_o, // Data request atomic operation + output logic [N_SLAVE-1:0][DATA_WIDTH-1:0] data_wdata_o, // Data request Wrire data + output logic [N_SLAVE-1:0][BE_WIDTH-1:0] data_be_o, // Data request Byte enable + output logic [N_SLAVE-1:0][ID_WIDTH-1:0] data_ID_o, +`ifdef GNT_BASED_FC + input logic [N_SLAVE-1:0] data_gnt_i, // Data request : input on slave side +`else + input logic [N_SLAVE-1:0] data_stall_i, // Data request stall : input on slave side +`endif + // Resp --> From Mem + input logic [N_SLAVE-1:0][DATA_WIDTH-1:0] data_r_rdata_i, // Data Response DATA (For LOAD commands) + input logic [N_SLAVE-1:0] data_r_valid_i, // Data Response: Command is Committed + input logic [N_SLAVE-1:0][ID_WIDTH-1:0] data_r_ID_i, // Data Response ID: To backroute Response + input logic [N_SLAVE-1:0] data_r_opc_i, // Data Response: Error + + input logic clk, // Clock + input logic rst_n // Active Low Reset +); + + // DATA ID array FORM address decoders to Request tree. + logic [N_CH0+N_CH1-1:0][ID_WIDTH-1:0] data_ID; + +`ifdef GNT_BASED_FC + logic [N_CH0+N_CH1-1:0] data_gnt_from_MEM[N_SLAVE-1:0]; +`else + logic [N_CH0+N_CH1-1:0] data_stall_from_MEM[N_SLAVE-1:0]; +`endif + logic [N_SLAVE-1:0] data_req_from_MASTER[N_CH0+N_CH1-1:0]; + logic [N_CH0+N_CH1-1:0] data_r_valid_from_MEM[N_SLAVE-1:0]; + + logic [N_SLAVE-1:0] data_r_valid_to_MASTER[N_CH0+N_CH1-1:0]; + logic [N_CH0+N_CH1-1:0] data_req_to_MEM[N_SLAVE-1:0]; +`ifdef GNT_BASED_FC + logic [N_SLAVE-1:0] data_gnt_to_MASTER[N_CH0+N_CH1-1:0]; +`else + logic [N_SLAVE-1:0] data_stall_to_MASTER[N_CH0+N_CH1-1:0]; +`endif + + logic [N_CH0+N_CH1-1:0][ADDR_PE_WIDTH-1:0] data_add; + + + genvar j,k; + + generate + + for (k=0; k (example: Used for cores) + .data_req_CH0_i(data_req_to_MEM[j][N_CH0-1:0]), + .data_add_CH0_i(data_add[N_CH0-1:0]), + .data_wen_CH0_i(data_wen_i[N_CH0-1:0]), + .data_atop_CH0_i(data_atop_i[N_CH0-1:0]), + .data_wdata_CH0_i(data_wdata_i[N_CH0-1:0]), + .data_be_CH0_i(data_be_i[N_CH0-1:0]), + .data_ID_CH0_i(data_ID[N_CH0-1:0]), + `ifdef GNT_BASED_FC + .data_gnt_CH0_o(data_gnt_from_MEM[j][N_CH0-1:0]), + `else + .data_stall_CH0_o(data_stall_from_MEM[j][N_CH0-1:0]), + `endif + // CHANNEL CH1 --> (example: Used for DMAs) + .data_req_CH1_i(data_req_to_MEM[j][N_CH1+N_CH0-1:N_CH0]), + .data_add_CH1_i(data_add[N_CH1+N_CH0-1:N_CH0]), + .data_wen_CH1_i(data_wen_i[N_CH1+N_CH0-1:N_CH0]), + .data_atop_CH1_i(data_atop_i[N_CH1+N_CH0-1:N_CH0]), + .data_wdata_CH1_i(data_wdata_i[N_CH1+N_CH0-1:N_CH0]), + .data_be_CH1_i(data_be_i[N_CH1+N_CH0-1:N_CH0]), + .data_ID_CH1_i(data_ID[N_CH1+N_CH0-1:N_CH0]), + `ifdef GNT_BASED_FC + .data_gnt_CH1_o(data_gnt_from_MEM[j][N_CH1+N_CH0-1:N_CH0]), + `else + .data_stall_CH1_o(data_stall_from_MEM[j][N_CH1+N_CH0-1:N_CH0]), + `endif + // ----------------- MEMORY ------------------- + // ---------------- RequestBlock OUTPUT (Connected to MEMORY) ---------------- + .data_req_o(data_req_o[j]), + .data_add_o(data_add_o[j]), + .data_wen_o(data_wen_o[j]), + .data_atop_o(data_atop_o[j]), + .data_wdata_o(data_wdata_o[j]), + .data_be_o(data_be_o[j]), + .data_ID_o(data_ID_o[j]), + `ifdef GNT_BASED_FC + .data_gnt_i(data_gnt_i[j]), + `else + .data_stall_i(data_stall_i[j]), + `endif + .data_r_valid_i(data_r_valid_i[j]), + .data_r_ID_i(data_r_ID_i[j]), + + // GEN VALID_SIGNALS in the response path + .data_r_valid_CH0_o(data_r_valid_from_MEM[j][N_CH0-1:0]), // N_CH0 Bit + .data_r_valid_CH1_o(data_r_valid_from_MEM[j][N_CH0+N_CH1-1:N_CH0]), // N_CH1 Bit + .clk(clk), + .rst_n(rst_n) + ); + end + else + begin : CH0_ONLY + RequestBlock1CH_PE + #( + .ADDR_WIDTH(ADDR_PE_WIDTH), + .N_CH0(N_CH0), + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BE_WIDTH(DATA_WIDTH/8) + ) + i_RequestBlock1CH_PE + ( + // CHANNEL CH0 --> (example: Used for cores) + .data_req_CH0_i(data_req_to_MEM[j]), + .data_add_CH0_i(data_add), + .data_wen_CH0_i(data_wen_i), + .data_atop_CH0_i(data_atop_i), + .data_wdata_CH0_i(data_wdata_i), + .data_be_CH0_i(data_be_i), + .data_ID_CH0_i(data_ID), + `ifdef GNT_BASED_FC + .data_gnt_CH0_o(data_gnt_from_MEM[j]), + `else + .data_stall_CH0_o(data_stall_from_MEM[j]), + `endif + // ----------------- MEMORY ------------------- + // ---------------- RequestBlock OUTPUT (Connected to MEMORY) ---------------- + .data_req_o(data_req_o[j]), + .data_add_o(data_add_o[j]), + .data_wen_o(data_wen_o[j]), + .data_atop_o(data_atop_o[j]), + .data_wdata_o(data_wdata_o[j]), + .data_be_o(data_be_o[j]), + .data_ID_o(data_ID_o[j]), + `ifdef GNT_BASED_FC + .data_gnt_i(data_gnt_i[j]), + `else + .data_stall_i(data_stall_i[j]), + `endif + .data_r_valid_i(data_r_valid_i[j]), + .data_r_ID_i(data_r_ID_i[j]), + // GEN VALID_SIGNALS in the response path + .data_r_valid_CH0_o(data_r_valid_from_MEM[j]), // N_CH0 Bit + .clk(clk), + .rst_n(rst_n) + ); + end + end + + for (j=0; j< N_CH0+N_CH1; j++) + begin : ResponseBlock_PE_Block + ResponseBlock_PE + #( + .ID ( 2**j ), + .ID_WIDTH ( ID_WIDTH ), + .N_SLAVE ( N_SLAVE ), + .DATA_WIDTH ( DATA_WIDTH ), + .LOG_CLUSTER ( LOG_CLUSTER ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .PE_ROUTING_LSB ( PE_ROUTING_LSB ), + .PE_ROUTING_MSB ( PE_ROUTING_MSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .CLUSTER_ALIAS_BASE (CLUSTER_ALIAS_BASE) + ) + i_ResponseBlock_PE + ( + .CLUSTER_ID(CLUSTER_ID), + // Signals from Memory cuts + .data_r_valid_i(data_r_valid_to_MASTER[j]), + .data_r_rdata_i(data_r_rdata_i), + .data_r_opc_i(data_r_opc_i), + // Output of the ResponseTree Block + .data_r_valid_o(data_r_valid_o[j]), + .data_r_rdata_o(data_r_rdata_o[j]), + .data_r_opc_o(data_r_opc_o[j]), + // Inputs form MAsters + .data_req_i(data_req_i[j]), + .data_add_i(data_add_i[j]), + `ifdef GNT_BASED_FC + .data_gnt_o(data_gnt_o[j]), // grant to master port + .data_gnt_i(data_gnt_to_MASTER[j]), // Signal from Request Block + `else + .data_stall_o(data_stall_o[j]), // stall to master port + .data_stall_i(data_stall_to_MASTER[j]), // Signal from Request Block + `endif + // Signal to/from Request Block + .data_req_o(data_req_from_MASTER[j]), + // Generated ID + .data_ID_o(data_ID[j]) + ); + end + + endgenerate + +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/addr_dec_resp_mux.sv b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/addr_dec_resp_mux.sv new file mode 100644 index 0000000..1bbc5f7 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/addr_dec_resp_mux.sv @@ -0,0 +1,184 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 06.03.2019 +// Description: address decoder and response mux for full crossbar. + +module addr_dec_resp_mux #( + parameter int unsigned NumOut = 32, + parameter int unsigned ReqDataWidth = 32, + parameter int unsigned RespDataWidth = 32, + parameter int unsigned RespLat = 1, // response latency of slaves + parameter bit WriteRespOn = 1'b1, // determines whether writes should return a response or not + parameter bit BroadCastOn = 1'b0 // perform broadcast +) ( + input logic clk_i, + input logic rst_ni, + // master side + input logic req_i, // request from this master + input logic [$clog2(NumOut)-1:0] add_i, // bank selection index to be decoded + input logic wen_i, // write enable + input logic [ReqDataWidth-1:0] data_i, // data to be transported to slaves + output logic gnt_o, // grant to master + output logic vld_o, // read/write response + output logic [RespDataWidth-1:0] rdata_o, // read response + // slave side + /* verilator lint_off UNOPTFLAT */ + output logic [NumOut-1:0] req_o, // request signals after decoding + /* verilator lint_on UNOPTFLAT */ + input logic [NumOut-1:0] gnt_i, // grants from slaves + output logic [NumOut-1:0][ReqDataWidth-1:0] data_o, // data to be transported to slaves + input logic [NumOut-1:0][RespDataWidth-1:0] rdata_i // read responses from slaves +); + +logic [RespLat-1:0] vld_d, vld_q; + +//////////////////////////////////////////////////////////////////////// +// degenerate case +//////////////////////////////////////////////////////////////////////// +if (NumOut == unsigned'(1)) begin : gen_one_output + + assign data_o[0] = data_i; + assign gnt_o = gnt_i[0]; + assign req_o[0] = req_i; + assign rdata_o = rdata_i[0]; + assign vld_o = vld_q[$high(vld_q)]; + + if (RespLat > unsigned'(1)) begin : gen_lat_gt1 + assign vld_d = {vld_q[$high(vld_q)-1:0], gnt_o & (~wen_i | WriteRespOn)}; + end else begin : gen_lat_le1 + assign vld_d = gnt_o & (~wen_i | WriteRespOn); + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg + if (!rst_ni) begin + vld_q <= '0; + end else begin + vld_q <= vld_d; + end + end + +//////////////////////////////////////////////////////////////////////// +// normal case +//////////////////////////////////////////////////////////////////////// +end else begin : gen_several_outputs + + // address decoder + always_comb begin : p_addr_dec + req_o = '0; + if (BroadCastOn) begin + if (req_i) begin + req_o = '1; + end + end else begin + req_o[add_i] = req_i; + end + end + + // connect data outputs + assign data_o = {NumOut{data_i}}; + + // aggregate grant signals + assign gnt_o = |gnt_i; + assign vld_o = vld_q[$high(vld_q)]; + + // response path in case of broadcasts + if (BroadCastOn) begin : gen_bcast + logic [NumOut-1:0] gnt_d, gnt_q; + logic [$clog2(NumOut)-1:0] bank_sel; + + assign gnt_d = gnt_i; + + // determine index from + // one-hot grant vector + lzc #( + .WIDTH(NumOut) + ) lzc_i ( + .in_i(gnt_q), + .cnt_o(bank_sel), + .empty_o() + ); + + if (RespLat > unsigned'(1)) begin : gen_lat_gt1 + logic [RespLat-2:0][$clog2(NumOut)-1:0] bank_sel_d, bank_sel_q; + + assign rdata_o = rdata_i[bank_sel_q[$high(bank_sel_q)]]; + assign vld_d = {vld_q[$high(vld_q)-1:0], gnt_o & (~wen_i | WriteRespOn)}; + + if (RespLat == unsigned'(2)) begin : gen_lat_eq2 + assign bank_sel_d = {bank_sel_q[$high(bank_sel_q)-2:0], bank_sel, bank_sel}; + end else begin : gen_lat_le2 + assign bank_sel_d = bank_sel; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg + if (!rst_ni) begin + bank_sel_q <= '0; + end else begin + bank_sel_q <= bank_sel_d; + end + end + + end else begin : gen_lat_eq1 + assign rdata_o = rdata_i[bank_sel]; + assign vld_d = gnt_o & (~wen_i | WriteRespOn); + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg + if (!rst_ni) begin + gnt_q <= '0; + vld_q <= '0; + end else begin + gnt_q <= gnt_d; + vld_q <= vld_d; + end + end + + // non-broadcast case + end else begin : gen_no_broadcast + logic [RespLat-1:0][$clog2(NumOut)-1:0] bank_sel_d, bank_sel_q; + + assign rdata_o = rdata_i[bank_sel_q[$high(bank_sel_q)]]; + + if (RespLat > unsigned'(1)) begin : gen_lat_gt1 + assign bank_sel_d = {bank_sel_q[$high(bank_sel_q)-1:0], add_i}; + assign vld_d = {vld_q[$high(vld_q)-1:0], gnt_o & (~wen_i | WriteRespOn)}; + end else begin : gen_lat_le1 + assign bank_sel_d = add_i; + assign vld_d = gnt_o & (~wen_i | WriteRespOn); + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg + if (!rst_ni) begin + bank_sel_q <= '0; + vld_q <= '0; + end else begin + bank_sel_q <= bank_sel_d; + vld_q <= vld_d; + end + end + end +end + +//////////////////////////////////////////////////////////////////////// +// assertions +//////////////////////////////////////////////////////////////////////// + +// pragma translate_off +initial begin + assert (RespLat > 0) else + $fatal(1,"RespLat must be greater than 0"); + assert (NumOut > 0) else + $fatal(1,"NumOut must be greater than 0"); +end +// pragma translate_on + +endmodule // addr_dec_resp_mux diff --git a/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/amo_shim.sv b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/amo_shim.sv new file mode 100644 index 0000000..cdd439c --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/amo_shim.sv @@ -0,0 +1,333 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Description: Governs atomic memory oeprations. This module needs to be instantiated +/// in front of an SRAM. It needs to have exclusive access over it. + +/// Author: Florian Zaruba +/// Superbank Patches: Thomas Benz +module amo_shim #( + parameter int unsigned AddrMemWidth = -1, + parameter int unsigned DataWidth = -1 +) ( + input logic clk_i, + input logic rst_ni, + // master side + input logic in_req_i, // Bank request + output logic in_gnt_o, // Bank grant + input logic [AddrMemWidth-1:0] in_add_i, // Address + input logic [3:0] in_amo_i, // Atomic Memory Operation + input logic in_wen_i, // 1: Store, 0: Load + input logic [DataWidth-1:0] in_wdata_i, // Write data + input logic [DataWidth/8-1:0] in_be_i, // Byte enable + output logic [DataWidth-1:0] in_rdata_o, // Read data + // slave side + output logic out_req_o, // Bank request + output logic [AddrMemWidth-1:0] out_add_o, // Address + output logic out_wen_o, // 1: Store, 0: Load + output logic [DataWidth-1:0] out_wdata_o, // Write data + output logic [DataWidth/8-1:0] out_be_o, // Byte enable + input logic [DataWidth-1:0] out_rdata_i, // Read data + // dma ports + input logic dma_access_i, // Current Access is a DMA access -> bypass amo, abort current op + output logic amo_conflict_o // Throw an error if DMA access occured on amo mem location +); + + typedef enum logic [3:0] { + AMONone = 4'h0, + AMOSwap = 4'h1, + AMOAdd = 4'h2, + AMOAnd = 4'h3, + AMOOr = 4'h4, + AMOXor = 4'h5, + AMOMax = 4'h6, + AMOMaxu = 4'h7, + AMOMin = 4'h8, + AMOMinu = 4'h9, + AMOCAS = 4'hA + } amo_op_t; + + enum logic [1:0] { + Idle, DoAMO, ProlongAMO + } state_q, state_d, state_qq; + + amo_op_t amo_op_q, amo_op_qq; + + logic load_amo; + + logic [AddrMemWidth-1:0] addr_q; + + logic [31:0] amo_operand_a; + logic [31:0] amo_operand_a_d, amo_operand_a_q; + logic [31:0] amo_operand_b_q; + // requested amo should be performed on upper 32 bit + logic upper_word_q; + logic [DataWidth/8-1:0] be_q; + logic [31:0] swap_value_q; + logic [31:0] amo_result; + + logic out_req_d, out_req_q; + logic [AddrMemWidth-1:0] out_add_d, out_add_q; + logic out_wen_d, out_wen_q; + logic [DataWidth/8-1:0] out_be_d, out_be_q; + logic [DataWidth-1:0] out_wdata_d, out_wdata_q; + logic [DataWidth-1:0] in_rdata_d, in_rdata_q; + + always_comb begin + // feed-through + out_req_o = in_req_i; + in_gnt_o = in_req_i; + out_add_o = in_add_i; + out_wen_o = in_wen_i; + out_wdata_o = in_wdata_i; + out_be_o = in_be_i; + in_rdata_o = out_rdata_i; + + // default + out_req_d = out_req_q; + out_add_d = out_add_q; + out_wen_d = out_wen_q; + out_be_d = out_be_q; + out_wdata_d = out_wdata_q; + in_rdata_d = in_rdata_q; + + // assume no error happened + if (DataWidth == 64) begin : gen_op_a_64 + /* verilator lint_off SELRANGE */ + amo_operand_a = upper_word_q ? out_rdata_i[63:32] : out_rdata_i[31:0]; + /* verilator lint_on SELRANGE */ + end else begin : gen_op_a_32 + amo_operand_a = out_rdata_i[31:0]; + end + amo_conflict_o = 1'b0; + state_d = state_q; + load_amo = 1'b0; + amo_operand_a_d = amo_operand_a; + + unique case (state_q) + Idle: begin + if (in_req_i && amo_op_t'(in_amo_i) != AMONone) begin + load_amo = 1'b1; + state_d = DoAMO; + out_wen_o = 1'b0; + end + end + // Claim the memory interface + DoAMO: begin + + // check if amo op was prolonged, if so use previous results + if(state_qq == ProlongAMO) begin + amo_operand_a = amo_operand_a_q; + end + + in_gnt_o = 1'b0; + state_d = Idle; + // Commit AMO + out_req_o = 1'b1; + out_be_o = be_q; + out_wen_o = |be_q; + out_add_o = addr_q; + // shift up if the address was pointing to the upper 32 bits + if (DataWidth == 64) begin + if (upper_word_q) begin + out_wdata_o = {amo_result, 32'b0}; + in_rdata_o = {amo_operand_a, 32'b0}; + end else begin + out_wdata_o = {32'b0, amo_result}; + in_rdata_o = {32'b0, amo_operand_a}; + end + end else begin + out_wdata_o = amo_result; + in_rdata_o = amo_operand_a; + end + + // overrule amo shim if dma is active + if (dma_access_i) begin + // store output of shim + out_req_d = out_req_o; + out_add_d = out_add_o; + out_wen_d = out_wen_o; + out_be_d = out_be_o; + out_wdata_d = out_wdata_o; + in_rdata_d = in_rdata_o; + + // dma data + out_req_o = in_req_i; + in_gnt_o = in_req_i; + out_add_o = in_add_i; + out_wen_o = in_wen_i; + out_wdata_o = in_wdata_i; + out_be_o = in_be_i; + in_rdata_o = out_rdata_i; + // something dangerous happend, inform programmer + amo_conflict_o = (addr_q == in_add_i); + // prolong the amo state + state_d = ProlongAMO; + end + end + // AMO was interrupted by DMA transfer and therefore prolonged + ProlongAMO: begin + state_d = dma_access_i ? ProlongAMO : Idle; + in_gnt_o = dma_access_i; + amo_operand_a_d = amo_operand_a_q; + // prolong + out_req_d = out_req_q; + out_add_d = out_add_q; + out_wen_d = out_wen_q; + out_be_d = out_be_q; + out_wdata_d = out_wdata_q; + in_rdata_d = in_rdata_q; + + if (~dma_access_i) begin + // replay + out_req_o = out_req_q; + out_add_o = out_add_q; + out_wen_o = out_wen_q; + out_be_o = out_be_q; + out_wdata_o = out_wdata_q; + in_rdata_o = in_rdata_q; + end + + end + + default:; + endcase + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + state_q <= Idle; + amo_op_q <= amo_op_t'('0); + addr_q <= '0; + amo_operand_b_q <= '0; + amo_operand_a_q <= '0; + be_q <= '0; + swap_value_q <= '0; + upper_word_q <= '0; + amo_op_qq <= amo_op_t'('0); + + out_req_q <= '0; + out_add_q <= '0; + out_wen_q <= '0; + out_be_q <= '0; + out_wdata_q <= '0; + in_rdata_q <= '0; + end else begin + + out_req_q <= out_req_d; + out_add_q <= out_add_d; + out_wen_q <= out_wen_d; + out_be_q <= out_be_d; + out_wdata_q <= out_wdata_d; + in_rdata_q <= in_rdata_d; + + state_q <= state_d; + state_qq <= state_q; + amo_op_qq <= amo_op_q; + amo_operand_a_q <= amo_operand_a_d; + if (load_amo) begin + amo_op_q <= amo_op_t'(in_amo_i); + addr_q <= in_add_i; + be_q <= in_be_i; + if (DataWidth == 64) begin + if (!in_be_i[0]) begin + /* verilator lint_off SELRANGE */ + amo_operand_b_q <= in_wdata_i[63:32]; + /* verilator lint_on SELRANGE */ + end + /* verilator lint_off SELRANGE */ + upper_word_q <= in_be_i[4]; + /* verilator lint_on SELRANGE */ + // swap value is located in the upper word + /* verilator lint_off SELRANGE */ + swap_value_q <= in_wdata_i[63:32]; + /* verilator lint_on SELRANGE */ + end else begin + amo_operand_b_q <= in_wdata_i[31:0]; + end + // on DMA access, keep last op in memory + end else if(dma_access_i) begin + amo_op_q <= amo_op_q; + end else begin + amo_op_q <= AMONone; + end + end + end + + // ---------------- + // AMO ALU + // ---------------- + logic [33:0] adder_sum; + logic [32:0] adder_operand_a, adder_operand_b; + + assign adder_sum = adder_operand_a + adder_operand_b; + /* verilator lint_off WIDTH */ + always_comb begin : amo_alu + + adder_operand_a = 33'($signed(amo_operand_a)); + adder_operand_b = 33'($signed(amo_operand_b_q)); + + amo_result = amo_operand_b_q; + + unique case (state_qq == ProlongAMO ? amo_op_qq : amo_op_q) + // the default is to output operand_b + AMOSwap:; + AMOAdd: amo_result = adder_sum[31:0]; + AMOAnd: amo_result = amo_operand_a & amo_operand_b_q; + AMOOr: amo_result = amo_operand_a | amo_operand_b_q; + AMOXor: amo_result = amo_operand_a ^ amo_operand_b_q; + AMOMax: begin + adder_operand_b = -$signed(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_b_q : amo_operand_a; + end + AMOMin: begin + adder_operand_b = -$signed(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_a : amo_operand_b_q; + end + AMOMaxu: begin + adder_operand_a = 33'($unsigned(amo_operand_a)); + adder_operand_b = -$unsigned(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_b_q : amo_operand_a; + end + AMOMinu: begin + adder_operand_a = 33'($unsigned(amo_operand_a)); + adder_operand_b = -$unsigned(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_a : amo_operand_b_q; + end + AMOCAS: begin + if (DataWidth == 64) begin + adder_operand_b = -$signed(amo_operand_b_q); + // values are equal -> update + if (adder_sum == '0) begin + amo_result = swap_value_q; + // values are not euqal -> don't update + end else begin + /* verilator lint_off SELRANGE */ + amo_result = upper_word_q ? out_rdata_i[63:32] : out_rdata_i[31:0]; + /* verilator lint_on SELRANGE */ + end + end else begin + $error("AMOCAS not supported for DataWidth = 32 bit"); + end + end + default: amo_result = '0; + endcase + end + /* verilator lint_on WIDTH */ + + `ifndef VERILATOR + // pragma translate_off + initial begin + assert (DataWidth == 32 || DataWidth == 64) + else $fatal(1, "Unsupported data width!"); + end + // pragma translate_on + `endif +endmodule diff --git a/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/superbank_addr_decoder.sv b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/superbank_addr_decoder.sv new file mode 100644 index 0000000..d1d35e5 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/superbank_addr_decoder.sv @@ -0,0 +1,114 @@ +/// Copyright (c) 2020 ETH Zurich, University of Bologna +/// All rights reserved. +/// +/// This code is under development and not yet released to the public. +/// Until it is released, the code is under the copyright of ETH Zurich and +/// the University of Bologna, and may contain confidential and/or unpublished +/// work. Any reuse/redistribution is strictly forbidden without written +/// permission from ETH Zurich. +/// +/// Superbank address decoder +/// groups a number of banks in the TCDM to superbanks. One superbank can be served by the DMA +/// in one cycle. + +/// Author: Thomas Benz + +module superbank_addr_decoder #( + parameter int unsigned TCDMAddrWidth = -1, + parameter int unsigned DMAAddrWidth = -1, + parameter int unsigned BanksPerSuperbank = -1, + parameter int unsigned NrSuperBanks = -1, + parameter int unsigned DMADataWidth = -1, + parameter int unsigned AmoWidth = -1, + parameter int unsigned MemoryLatency = -1 +) ( + + input logic clk_i, + input logic rst_i, + + // single port towards dma + input logic dma_req_i, // Bank request + output logic dma_gnt_o, // Bank grant + input logic [DMAAddrWidth-1:0 ] dma_add_i, // Address + input logic [AmoWidth-1:0 ] dma_amo_i, // Atomic Memory Operation + input logic dma_wen_i, // 1: Store, 0: Load + input logic [DMADataWidth-1:0 ] dma_wdata_i, // Write data + input logic [DMADataWidth/8-1:0 ] dma_be_i, // Byte enable + output logic [DMADataWidth-1:0 ] dma_rdata_o, // Read data + + // dma side + output logic [NrSuperBanks-1:0] super_bank_req_o, // Bank request + input logic [NrSuperBanks-1:0] super_bank_gnt_i, // Bank grant + output logic [NrSuperBanks-1:0][TCDMAddrWidth-1:0 ] super_bank_add_o, // Address + output logic [NrSuperBanks-1:0][AmoWidth-1:0 ] super_bank_amo_o, // Atomic Memory Operation + output logic [NrSuperBanks-1:0] super_bank_wen_o, // 1: Store, 0: Load + output logic [NrSuperBanks-1:0][DMADataWidth-1:0 ] super_bank_wdata_o, // Write data + output logic [NrSuperBanks-1:0][DMADataWidth/8-1:0 ] super_bank_be_o, // Byte enable + input logic [NrSuperBanks-1:0][DMADataWidth-1:0 ] super_bank_rdata_i // Read data +); + + localparam SBWidth = $clog2(NrSuperBanks); + localparam DMADataWidthBytes = DMADataWidth / 8; + localparam NumBitsDMATrans = $clog2(DMADataWidthBytes); // example case: 6 + + // case for 512 bits, 32 banks, 4 superbanks, 1024 words per bank, 256kiB, 64bit system + // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + // 00000000000000000000000000000000000000000|-----------------------------|-----|--------|--------| + // zero or ignored tcdm line address superbank byte in bank + // subbank + + localparam TCDMUpper = SBWidth + NumBitsDMATrans + TCDMAddrWidth; + + // super bank address + logic [SBWidth-1:0] super_bank; + logic [TCDMAddrWidth-1:0] tcdm_line_address; + // have to keep the last choosen bank to correctly route response (rdata back) + // the memory can have a parametrizable amount of delay. + logic [MemoryLatency-1:0][SBWidth-1:0] super_bank_q; + + // divide the address + assign super_bank = dma_add_i[SBWidth+NumBitsDMATrans-1:NumBitsDMATrans]; + assign tcdm_line_address = dma_add_i[TCDMUpper-1:TCDMUpper-TCDMAddrWidth]; + + + // create the mux inthe forward and backwords direction + always_comb begin : proc_dma_addr_decoder + + // unused ports are set to 0 + super_bank_req_o = '0; + super_bank_add_o = '0; + super_bank_amo_o = '0; + super_bank_wen_o = '0; + super_bank_wdata_o = '0; + super_bank_be_o = '0; + + // mux + super_bank_req_o [super_bank] = dma_req_i; + super_bank_add_o [super_bank] = tcdm_line_address; + super_bank_amo_o [super_bank] = dma_amo_i; + super_bank_wen_o [super_bank] = dma_wen_i; + super_bank_wdata_o [super_bank] = dma_wdata_i; + super_bank_be_o [super_bank] = dma_be_i; + + dma_gnt_o = super_bank_gnt_i [super_bank]; + + // backwards path has be delayed by one, as memory has one cycle latency + dma_rdata_o = super_bank_rdata_i [super_bank_q[MemoryLatency-1]]; + + end + + always_ff @(posedge clk_i) begin : proc_delay_bank_choice + if (rst_i) begin + super_bank_q<= 0; + end else begin + super_bank_q[0] <= super_bank; + // implement the shift for the delay + if (MemoryLatency > 1) begin + for (int i = 1; i < MemoryLatency; i++) begin + super_bank_q[i] <= super_bank_q[i-1]; + end + end + end + end + +endmodule : superbank_addr_decoder diff --git a/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv new file mode 100644 index 0000000..0b4025f --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv @@ -0,0 +1,323 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 06.03.2019 +// Description: TCDM interconnect with different network topologies. Currently +// supported are: full crossbar, radix-2/4 butterflies and clos networks. +// Note that only the full crossbar allows NumIn/NumOut configurations that are not +// aligned to a power of 2. + +module tcdm_interconnect #( + /////////////////////////// + // global parameters + parameter int unsigned NumIn = 32, // number of initiator ports (must be aligned with power of 2 for bfly and clos) + parameter int unsigned NumOut = 64, // number of TCDM banks (must be aligned with power of 2 for bfly and clos) + parameter int unsigned AddrWidth = 32, // address width on initiator side + parameter int unsigned DataWidth = 32, // word width of data + parameter int unsigned BeWidth = DataWidth/8, // width of corresponding byte enables + parameter int unsigned AddrMemWidth = 12, // number of address bits per TCDM bank + parameter bit WriteRespOn = 1, // defines whether the interconnect returns a write response + parameter int unsigned RespLat = 1, // TCDM read latency, usually 1 cycle + // determines the width of the byte offset in a memory word. normally this can be left at the default vaule, + // but sometimes it needs to be overridden (e.g. when meta-data is supplied to the memory via the wdata signal). + parameter int unsigned ByteOffWidth = $clog2(DataWidth-1)-3, + + // topology can be: LIC, BFLY2, BFLY4, CLOS + parameter tcdm_interconnect_pkg::topo_e Topology = tcdm_interconnect_pkg::LIC, + // number of parallel butterfly's to use, only relevant for BFLY topologies + parameter int unsigned NumPar = 1, + // this detemines which Clos config to use, only relevant for CLOS topologies + // 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n + parameter int unsigned ClosConfig = 2 + /////////////////////////// +) ( + input logic clk_i, + input logic rst_ni, + // master side + input logic [NumIn-1:0] req_i, // request signal + input logic [NumIn-1:0][AddrWidth-1:0] add_i, // tcdm address + input logic [NumIn-1:0] wen_i, // 1: store, 0: load + input logic [NumIn-1:0][DataWidth-1:0] wdata_i, // write data + input logic [NumIn-1:0][BeWidth-1:0] be_i, // byte enable + output logic [NumIn-1:0] gnt_o, // grant (combinationally dependent on req_i and add_i + output logic [NumIn-1:0] vld_o, // response valid, also asserted if write responses ar + output logic [NumIn-1:0][DataWidth-1:0] rdata_o, // data response (for load commands) + // slave side + output logic [NumOut-1:0] req_o, // request out + input logic [NumOut-1:0] gnt_i, // grant input + output logic [NumOut-1:0][AddrMemWidth-1:0] add_o, // address within bank + output logic [NumOut-1:0] wen_o, // write enable + output logic [NumOut-1:0][DataWidth-1:0] wdata_o, // write data + output logic [NumOut-1:0][BeWidth-1:0] be_o, // byte enable + input logic [NumOut-1:0][DataWidth-1:0] rdata_i // data response (for load commands) +); + +//////////////////////////////////////////////////////////////////////// +// localparams and stacking of address, wen and payload data +//////////////////////////////////////////////////////////////////////// + +localparam int unsigned NumOutLog2 = $clog2(NumOut); +localparam int unsigned AggDataWidth = 1+BeWidth+AddrMemWidth+DataWidth; +logic [NumIn-1:0][AggDataWidth-1:0] data_agg_in; +logic [NumOut-1:0][AggDataWidth-1:0] data_agg_out; +logic [NumIn-1:0][NumOutLog2-1:0] bank_sel; + +for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs + // extract bank index + assign bank_sel[j] = add_i[j][ByteOffWidth+NumOutLog2-1:ByteOffWidth]; + // aggregate data to be routed to slaves + assign data_agg_in[j] = {wen_i[j], be_i[j], add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1:ByteOffWidth+NumOutLog2], wdata_i[j]}; +end + +// disaggregate data +for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs + assign {wen_o[k], be_o[k], add_o[k], wdata_o[k]} = data_agg_out[k]; +end + +//////////////////////////////////////////////////////////////////////// +// tuned logarithmic interconnect architecture, based on rr_arb_tree primitives +//////////////////////////////////////////////////////////////////////// +if (Topology == tcdm_interconnect_pkg::LIC) begin : gen_lic + xbar #( + .NumIn ( NumIn ), + .NumOut ( NumOut ), + .ReqDataWidth ( AggDataWidth ), + .RespDataWidth ( DataWidth ), + .RespLat ( RespLat ), + .WriteRespOn ( WriteRespOn ) + ) i_xbar ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req_i ), + .add_i ( bank_sel ), + .wen_i ( wen_i ), + .wdata_i ( data_agg_in ), + .gnt_o ( gnt_o ), + .rdata_o ( rdata_o ), + .rr_i ( '0 ), + .vld_o ( vld_o ), + .gnt_i ( gnt_i ), + .req_o ( req_o ), + .wdata_o ( data_agg_out ), + .rdata_i ( rdata_i ) + ); +//////////////////////////////////////////////////////////////////////// +// butterfly network (radix 2 or 4) with parallelization option +// (NumPar>1 results in a hybrid between lic and bfly) +//////////////////////////////////////////////////////////////////////// +end else if (Topology == tcdm_interconnect_pkg::BFLY2 || Topology == tcdm_interconnect_pkg::BFLY4) begin : gen_bfly + localparam int unsigned NumPerSlice = NumIn/NumPar; + localparam int unsigned Radix = 2**Topology; + logic [NumOut-1:0][NumPar-1:0][AggDataWidth-1:0] data1; + logic [NumOut-1:0][NumPar-1:0][DataWidth-1:0] rdata1; + logic [NumOut-1:0][NumPar-1:0] gnt1, req1; + + logic [NumPar-1:0][NumOut-1:0][AggDataWidth-1:0] data1_trsp; + logic [NumPar-1:0][NumOut-1:0][DataWidth-1:0] rdata1_trsp; + logic [NumPar-1:0][NumOut-1:0] gnt1_trsp, req1_trsp; + + logic [$clog2(NumIn)-1:0] rr; + logic [NumOutLog2-1:0] rr1; + + // Although round robin arbitration works in some cases, it + // it is quite likely that it interferes with linear access patterns + // hence we use a relatively long LFSR + block cipher here to create a + // pseudo random sequence with good randomness. the block cipher layers + // are used to break shift register linearity. + lfsr #( + .LfsrWidth(64), + .OutWidth($clog2(NumIn)), + .CipherLayers(3), + .CipherReg(1'b1) + ) lfsr_i ( + .clk_i, + .rst_ni, + .en_i(|(gnt_i & req_o)), + .out_o(rr) + ); + + // // this performs a density estimation of the lfsr output + // // in order to assess the quality of the pseudo random sequence + // // ideally this should be flat + // // pragma translate_off + // int unsigned cnt [0:NumOut-1]; + // int unsigned cycle; + // always_ff @(posedge clk_i or negedge rst_ni) begin : p_stats + // if(!rst_ni) begin + // cnt <= '{default:0}; + // cycle <= 0; + // end else begin + // if (|(gnt_i & req_o)) begin + // cnt[rr] <= cnt[rr]+1; + // cycle <= cycle + 1; + // if ((cycle % 9500) == 0 && (cycle>0)) begin + // $display("------------------------"); + // $display("--- LFSR Binning: ---"); + // $display("------------------------"); + // for (int unsigned k=0; k unsigned'(1)) begin : gen_rr_arb + + logic [$clog2(NumPar)-1:0] rr2; + assign rr2 = $clog2(NumPar)'(rr[$clog2(NumPar)-1:0]); + + for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_par + rr_arb_tree #( + .NumIn ( NumPar ), + .DataWidth ( AggDataWidth ), + .ExtPrio ( 1'b1 ) + ) i_rr_arb_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .rr_i ( rr2 ), + .req_i ( req1[k] ), + .gnt_o ( gnt1[k] ), + .data_i ( data1[k] ), + .gnt_i ( gnt_i[k] ), + .req_o ( req_o[k] ), + .data_o ( data_agg_out[k] ), + .idx_o ( )// disabled + ); + end + end else begin : gen_no_rr_arb + // just connect through in this case + assign data_agg_out = data1; + assign req_o = req1; + assign gnt1 = gnt_i; + end + // pragma translate_off + initial begin + assert(NumPar >= unsigned'(1)) else + $fatal(1,"NumPar must be greater or equal 1."); + end + // pragma translate_on +//////////////////////////////////////////////////////////////////////// +// clos network +//////////////////////////////////////////////////////////////////////// +end else if (Topology == tcdm_interconnect_pkg::CLOS) begin : gen_clos + clos_net #( + .NumIn ( NumIn ), + .NumOut ( NumOut ), + .ReqDataWidth ( AggDataWidth ), + .RespDataWidth ( DataWidth ), + .RespLat ( RespLat ), + .WriteRespOn ( WriteRespOn ), + .ClosConfig ( ClosConfig ) + ) i_clos_net ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req_i ), + .gnt_o ( gnt_o ), + .add_i ( bank_sel ), + .wen_i ( wen_i ), + .wdata_i ( data_agg_in ), + .rdata_o ( rdata_o ), + .vld_o ( vld_o ), + .req_o ( req_o ), + .gnt_i ( gnt_i ), + .wdata_o ( data_agg_out ), + .rdata_i ( rdata_i ) + ); +//////////////////////////////////////////////////////////////////////// +end else begin : gen_unknown + // pragma translate_off + initial begin + $fatal(1,"Unknown TCDM configuration %d.", Topology); + end + // pragma translate_on +end +//////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////// +// assertions +//////////////////////////////////////////////////////////////////////// + +// pragma translate_off +initial begin + assert(AddrMemWidth+NumOutLog2 <= AddrWidth) else + $fatal(1,"Address not wide enough to accomodate the requested TCDM configuration."); + assert(NumOut >= NumIn) else + $fatal(1,"NumOut < NumIn is not supported."); +end +// pragma translate_on + +endmodule // tcdm_interconnect diff --git a/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv new file mode 100644 index 0000000..7bdd0ed --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv @@ -0,0 +1,73 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 28.05.2019 +// Description: Package with important constants and lookup tables for TCDM +// interconnect. + +package tcdm_interconnect_pkg; + +typedef enum logic [1:0] { LIC, BFLY2, BFLY4, CLOS } topo_e; + +//////////////////////////////////////////////////////////////////////// +// LUT params for Clos net with configs: 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n, +// to be indexed with [config_idx][$clog2(BankingFact)][$clog2(NumBanks)] +// generated with MATLAB script gen_clos_params.m +//////////////////////////////////////////////////////////////////////// +localparam logic [3:1][4:0][12:2][15:0] ClosNLut = {16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2}; +localparam logic [3:1][4:0][12:2][15:0] ClosMLut = {16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1,16'd1}; +localparam logic [3:1][4:0][12:2][15:0] ClosRLut = {16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2}; + + + +endpackage : tcdm_interconnect_pkg diff --git a/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_superbank_mux.sv b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_superbank_mux.sv new file mode 100644 index 0000000..418e183 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_superbank_mux.sv @@ -0,0 +1,184 @@ +/// Copyright (c) 2020 ETH Zurich, University of Bologna +/// All rights reserved. +/// +/// This code is under development and not yet released to the public. +/// Until it is released, the code is under the copyright of ETH Zurich and +/// the University of Bologna, and may contain confidential and/or unpublished +/// work. Any reuse/redistribution is strictly forbidden without written +/// permission from ETH Zurich. +/// +/// Description: Mux between the DMA and the interconnect. 1 DMA access +/// occupies N banks. + +/// Author: Thomas Benz + +module tcdm_superbank_mux #( + + parameter int unsigned AddrMemWidth = -1, + parameter int unsigned BanksPerSuperbank = -1, + parameter int unsigned DMADataWidth = -1, + parameter int unsigned DataWidth = -1, + parameter int unsigned AmoWidth = -1 +) ( + + input logic clk_i, + input logic rst_i, + + // interconnect side + input logic [BanksPerSuperbank-1:0] ic_req_i, // Bank request + output logic [BanksPerSuperbank-1:0] ic_gnt_o, // Bank grant + input logic [BanksPerSuperbank-1:0][AddrMemWidth-1:0 ] ic_add_i, // Address + input logic [BanksPerSuperbank-1:0][AmoWidth-1:0 ] ic_amo_i, // Atomic Memory Operation + input logic [BanksPerSuperbank-1:0] ic_wen_i, // 1: Store, 0: Load + input logic [BanksPerSuperbank-1:0][DataWidth-1:0 ] ic_wdata_i, // Write data + input logic [BanksPerSuperbank-1:0][DataWidth/8-1:0 ] ic_be_i, // Byte enable + output logic [BanksPerSuperbank-1:0][DataWidth-1:0 ] ic_rdata_o, // Read data + + // dma a side + input logic dma_a_req_i, // Bank request + output logic dma_a_gnt_o, // Bank grant + input logic [AddrMemWidth-1:0 ] dma_a_add_i, // Address + input logic [AmoWidth-1:0 ] dma_a_amo_i, // Atomic Memory Operation + input logic dma_a_wen_i, // 1: Store, 0: Load + input logic [DMADataWidth-1:0 ] dma_a_wdata_i, // Write data + input logic [DMADataWidth/8-1:0 ] dma_a_be_i, // Byte enable + output logic [DMADataWidth-1:0 ] dma_a_rdata_o, // Read data + + // dma b side + input logic dma_b_req_i, // Bank request + output logic dma_b_gnt_o, // Bank grant + input logic [AddrMemWidth-1:0 ] dma_b_add_i, // Address + input logic [AmoWidth-1:0 ] dma_b_amo_i, // Atomic Memory Operation + input logic dma_b_wen_i, // 1: Store, 0: Load + input logic [DMADataWidth-1:0 ] dma_b_wdata_i, // Write data + input logic [DMADataWidth/8-1:0 ] dma_b_be_i, // Byte enable + output logic [DMADataWidth-1:0 ] dma_b_rdata_o, // Read data + + // to memory/amo ports + output logic [BanksPerSuperbank-1:0] amo_req_o, // Bank request + input logic [BanksPerSuperbank-1:0] amo_gnt_i, // Bank grant + output logic [BanksPerSuperbank-1:0][AddrMemWidth-1:0] amo_add_o, // Address + output logic [BanksPerSuperbank-1:0][AmoWidth-1:0 ] amo_amo_o, // Atomic Memory Operation + output logic [BanksPerSuperbank-1:0] amo_wen_o, // 1: Store, 0: Load + output logic [BanksPerSuperbank-1:0][DataWidth-1:0 ] amo_wdata_o, // Write data + output logic [BanksPerSuperbank-1:0][DataWidth/8-1:0 ] amo_be_o, // Byte enable + input logic [BanksPerSuperbank-1:0][DataWidth-1:0 ] amo_rdata_i, // Read data + + // general inputs + input logic sel_dma_a_i, // 0: use ic port, 1: use dma port + input logic sel_dma_b_i // 0: use ic port, 1: use dma port +); + + typedef struct packed { + logic [AddrMemWidth-1:0 ] add; + logic [AmoWidth-1:0 ] amo; + logic wen; + logic [DMADataWidth-1:0 ] wdata; + logic [DMADataWidth/8-1:0 ] be; + } payload_t; + + // arbitrated signals + logic dma_rr_req, dma_rr_gnt; + payload_t dma_payload_a, dma_payload_b, dma_payload_rr; + logic dma_port_used; + + // dma active signal + logic sel_dma; + + // response is always delayed: + logic sel_dma_q; + + // arbitrate the two DMA ports + rr_arb_tree #( + .NumIn ( 2 ), + .DataType ( payload_t ) + ) i_rr_arb_tree ( + .clk_i ( clk_i ), + .rst_ni ( ~rst_i ), + .flush_i ( '0 ), + .rr_i ( '0 ), + .req_i ( { dma_a_req_i, dma_b_req_i } ), + .gnt_o ( { dma_a_gnt_o, dma_b_gnt_o } ), + .data_i ( { dma_payload_a, dma_payload_b } ), + .req_o ( dma_rr_req ), + .gnt_i ( dma_rr_gnt ), + .data_o ( dma_payload_rr ), + .idx_o ( ) + ); + + // one of the two DMA ports is active + assign sel_dma = sel_dma_a_i | sel_dma_b_i; + + // pack a and b ports + assign dma_payload_a.add = dma_a_add_i; + assign dma_payload_a.amo = dma_a_amo_i; + assign dma_payload_a.wen = dma_a_wen_i; + assign dma_payload_a.wdata = dma_a_wdata_i; + assign dma_payload_a.be = dma_a_be_i; + + assign dma_payload_b.add = dma_b_add_i; + assign dma_payload_b.amo = dma_b_amo_i; + assign dma_payload_b.wen = dma_b_wen_i; + assign dma_payload_b.wdata = dma_b_wdata_i; + assign dma_payload_b.be = dma_b_be_i; + + // forwards channel DMA to memory. + always_comb begin : proc_tcdm_mux + + // default -> feed trough ic requests + ic_gnt_o = amo_gnt_i; + amo_req_o = ic_req_i; + amo_add_o = ic_add_i; + amo_amo_o = ic_amo_i; + amo_wen_o = ic_wen_i; + amo_wdata_o = ic_wdata_i; + amo_be_o = ic_be_i; + + // tie dma gnt port to 0 + dma_rr_gnt = 'b0; + + + if(sel_dma) begin + // block access from tcdm + ic_gnt_o = 'b0; + amo_req_o = {{BanksPerSuperbank}{dma_rr_req}}; + amo_add_o = {{BanksPerSuperbank}{dma_payload_rr.add}}; + amo_amo_o = {{BanksPerSuperbank}{dma_payload_rr.amo}}; + amo_wen_o = {{BanksPerSuperbank}{dma_payload_rr.wen}}; + amo_wdata_o = dma_payload_rr.wdata; + amo_be_o = dma_payload_rr.be; + + // we need permission from all banks + dma_rr_gnt = 1'b1; + for(int i = 0; i < BanksPerSuperbank; i++) begin + dma_rr_gnt = dma_rr_gnt & amo_gnt_i; + end + end + end + + // backwards channel memory to DMA, this will be one cycle delayed. + always_comb begin : proc_tcdm_mux_backwards_channel + + // default: get response from DMA + ic_rdata_o = amo_rdata_i; + dma_a_rdata_o = 'b0; + dma_b_rdata_o = 'b0; + + // dma did last request -> get now the response + if(sel_dma_q) begin + ic_rdata_o = 'b0; + dma_a_rdata_o = amo_rdata_i; + dma_b_rdata_o = amo_rdata_i; + end + end + + // delay dma accesses by one for the response channel + always_ff @(posedge clk_i) begin : proc_delay_dma_sel + if(rst_i) begin + sel_dma_q <= 1'b0; + end else begin + sel_dma_q <= sel_dma; + end + end + +endmodule : tcdm_superbank_mux diff --git a/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv new file mode 100644 index 0000000..428f1c6 --- /dev/null +++ b/hw/deps/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv @@ -0,0 +1,132 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 07.03.2019 +// Description: Full crossbar, implemented as logarithmic interconnect. + +module xbar #( + parameter int unsigned NumIn = 4, // number of requestors + parameter int unsigned NumOut = 4, // number of targets + parameter int unsigned ReqDataWidth = 32, // word width of data + parameter int unsigned RespDataWidth = 32, // word width of data + parameter int unsigned RespLat = 1, // response latency of slaves + parameter bit WriteRespOn = 1'b1, // defines whether the interconnect returns a write response + parameter bit BroadCastOn = 1'b0, // perform broadcast + parameter bit ExtPrio = 1'b0 // use external arbiter priority flags +) ( + input logic clk_i, + input logic rst_ni, + // external prio flag input + input logic [NumOut-1:0][$clog2(NumIn)-1:0] rr_i, // external prio input + // master side + input logic [NumIn-1:0] req_i, // request signal + input logic [NumIn-1:0][$clog2(NumOut)-1:0] add_i, // bank Address + input logic [NumIn-1:0] wen_i, // 1: store, 0: load + input logic [NumIn-1:0][ReqDataWidth-1:0] wdata_i, // write data + output logic [NumIn-1:0] gnt_o, // grant (combinationally dependent on req_i and add_i) + output logic [NumIn-1:0] vld_o, // response valid, also asserted if write responses are enabled + output logic [NumIn-1:0][RespDataWidth-1:0] rdata_o, // data response (for load commands) + // slave side + input logic [NumOut-1:0] gnt_i, // request out + output logic [NumOut-1:0] req_o, // grant input + /* verilator lint_off UNOPTFLAT */ + output logic [NumOut-1:0][ReqDataWidth-1:0] wdata_o, // write data + /* verilator lint_on UNOPTFLAT */ + input logic [NumOut-1:0][RespDataWidth-1:0] rdata_i // data response (for load commands) +); + +//////////////////////////////////////////////////////////////////////// +// inter-level wires +//////////////////////////////////////////////////////////////////////// + +logic [NumOut-1:0][NumIn-1:0][ReqDataWidth-1:0] sl_data; +logic [NumIn-1:0][NumOut-1:0][ReqDataWidth-1:0] ma_data; +logic [NumOut-1:0][NumIn-1:0] sl_gnt, sl_req; +logic [NumIn-1:0][NumOut-1:0] ma_gnt, ma_req; + +//////////////////////////////////////////////////////////////////////// +// instantiate bank address decoder/resp mux for each master +//////////////////////////////////////////////////////////////////////// +for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs + addr_dec_resp_mux #( + .NumOut ( NumOut ), + .ReqDataWidth ( ReqDataWidth ), + .RespDataWidth ( RespDataWidth ), + .RespLat ( RespLat ), + .BroadCastOn ( BroadCastOn ), + .WriteRespOn ( WriteRespOn ) + ) i_addr_dec_resp_mux ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req_i[j] ), + .add_i ( add_i[j] ), + .wen_i ( wen_i[j] ), + .data_i ( wdata_i[j] ), + .gnt_o ( gnt_o[j] ), + .vld_o ( vld_o[j] ), + .rdata_o ( rdata_o[j] ), + .req_o ( ma_req[j] ), + .gnt_i ( ma_gnt[j] ), + .data_o ( ma_data[j] ), + .rdata_i ( rdata_i ) + ); + + // reshape connections between M/S + for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_reshape + assign sl_req[k][j] = ma_req[j][k]; + assign ma_gnt[j][k] = sl_gnt[k][j]; + assign sl_data[k][j] = ma_data[j][k]; + end +end + +//////////////////////////////////////////////////////////////////////// +// instantiate an RR arbiter for each endpoint +//////////////////////////////////////////////////////////////////////// +for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs + if (NumIn == unsigned'(1)) begin + assign req_o[k] = sl_req[k][0]; + assign sl_gnt[k][0] = gnt_i[k]; + assign wdata_o[k] = sl_data[k][0]; + end else begin : gen_rr_arb_tree + rr_arb_tree #( + .NumIn ( NumIn ), + .DataWidth ( ReqDataWidth ), + .ExtPrio ( ExtPrio ) + ) i_rr_arb_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .rr_i ( rr_i[k] ), + .req_i ( sl_req[k] ), + .gnt_o ( sl_gnt[k] ), + .data_i ( sl_data[k] ), + .gnt_i ( gnt_i[k] ), + .req_o ( req_o[k] ), + .data_o ( wdata_o[k] ), + .idx_o ( )// disabled + ); + end +end + +//////////////////////////////////////////////////////////////////////// +// assertion +//////////////////////////////////////////////////////////////////////// + +// pragma translate_off +initial begin + assert(NumIn > 0) else + $fatal(1,"NumIn needs to be larger than 0."); + assert(NumOut > 0) else + $fatal(1,"NumOut needs to be larger than 0."); +end +// pragma translate_on + +endmodule // xbar diff --git a/hw/deps/cluster_peripherals/cluster_control_unit/cluster_control_unit.sv b/hw/deps/cluster_peripherals/cluster_control_unit/cluster_control_unit.sv new file mode 100644 index 0000000..f046e68 --- /dev/null +++ b/hw/deps/cluster_peripherals/cluster_control_unit/cluster_control_unit.sv @@ -0,0 +1,393 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Company: Multitherman Laboratory @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Davide Rossi - davide.rossi@unibo.it // +// // +// Additional contributions by: // +// Andreas Traber - atraber@iis.ee.ethz.ch // +// Stefan Mach - smach@iis.ee.ethz.ch // +// // +// Create Date: 13/02/2013 // +// Design Name: ULPSoC // +// Module Name: ulpcluster_top // +// Project Name: ULPSoC // +// Language: SystemVerilog // +// // +// Description: ULPSoC cluster // +// // +// Revision: // +// Revision v0.1 - File Created // +// Revision v0.2 - Added DVS-DVSE support for memories // +// Revision v0.3 - Cleand Code, added non-blocking assign in the always_ff // +// Revision v0.4 - Updated the address range from [4:3] to[3:2] // +// Revision v0.5 - Restored Back Addr range [4:3], because of TB issues // +// Revision v0.6 - 29/05/15 : removed DVS-DVSE, added HS,LS,RM,WM // +// LS is default 1, other are '0 by default // +// Revision v? - Added fregfile_disable to the cluster control register // +// // +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Memory Map +// +// 0x000: EoC. Write to bit 0 sets the eoc signal +// 0x008: Fetch Enable. Each core has its own bit, starts from LSB +// 0x010: Event. Bit 0 triggers an event. Usually not connected +// 0x018: Cluster Config. RM, WM, HS, LS, HWPE_SEL, FREGFILE_DIS +// 0x020: Cluster Clock Gate. Bit 0 enables it +// 0x028: Debug Status/Resume. Each core has its own bit, starts from LSB +// On read: Bit is set when core is halted +// On write: Resume core x when bit x is set +// 0x038: Debug Halt Mask. Each core has its own bit, starts from LSB +// When bit is set, core will be part of mask group and stopped +// when one of the members of the group stops +// 0x040-0x07F: Boot Addresses. Each core has its own 32-bit boot address +// 0x80: TCDM arbitration configuration CH0 (CORE) +// 0x88: TCDM arbitration configuration CH1 (DMA HWCE) +//////////////////////////////////////////////////////////////////////////////// + +module cluster_control_unit +#( + parameter NB_CORES = 4, + parameter PER_ID_WIDTH = 5, + parameter ROM_BOOT_ADDR = 32'h1A000000, + parameter BOOT_ADDR = 32'h1C000000 +) +( + input logic clk_i, + input logic rst_ni, + input logic en_sa_boot_i, + input logic fetch_en_i, + XBAR_PERIPH_BUS.Slave speriph_slave, + + output logic event_o, + output logic eoc_o, + + output logic cluster_cg_en_o, + + output logic hwpe_sel_o, + output logic hwpe_en_o, + + output logic fregfile_disable_o, + + input logic [NB_CORES-1:0] core_halted_i, // cores are in halted mode (which means debugging) + output logic [NB_CORES-1:0] core_halt_o, // halt the core + output logic [NB_CORES-1:0] core_resume_o, // resume the core + + output logic [NB_CORES-1:0] fetch_enable_o, + output logic [NB_CORES-1:0][31:0] boot_addr_o, + output logic [1:0] TCDM_arb_policy_o +); + + localparam OFFSET_1 = 4; // It was RM + localparam OFFSET_2 = 4; // It was WM + + logic rvalid_q, rvalid_n; + logic [PER_ID_WIDTH-1:0] id_q, id_n; + logic [31:0] rdata_q, rdata_n; + logic [NB_CORES-1:0] fetch_en_q, fetch_en_n; + + logic [NB_CORES-1:0] dbg_halt_mask_q, dbg_halt_mask_n; + logic core_halted_any_q, core_halted_any_n; + + logic eoc_n; + logic event_n; + + logic hwpe_sel_n; + logic hwpe_en_n; + + logic fregfile_disable_n; + + logic [NB_CORES-1:0][31:0] boot_addr_n; + + logic [1:0] fetch_en_sync; + logic start_fetch; + logic start_boot; + logic cluster_cg_en_n; + + logic [1:0] TCDM_arb_policy_n; + + logic core_halt_rising_edge; + + enum logic [1:0] { RESET, BOOT, WAIT_FETCH, LIMBO } boot_cs, boot_ns; + + assign fetch_enable_o = fetch_en_q; + + always_comb + begin + boot_ns = boot_cs; + start_boot = 1'b0; + start_fetch = 1'b0; + + case (boot_cs) + RESET: begin + boot_ns = BOOT; + end + + BOOT: begin + boot_ns = WAIT_FETCH; + if (en_sa_boot_i) + start_boot = 1'b1; + end + + WAIT_FETCH: begin + if (fetch_en_sync[1]) begin + start_fetch = 1'b1; + boot_ns = LIMBO; + end + end + + LIMBO: begin + boot_ns = LIMBO; + end + endcase + end + + ////////ASYNCH SIGNAL SYNCHRONIZER + EDGE DETECTOR\\\\\\\\ + always_ff @(posedge clk_i, negedge rst_ni) + begin + if(rst_ni == 1'b0) + begin + fetch_en_sync <= 2'b0; + boot_cs <= RESET; + end + else + begin + fetch_en_sync <= {fetch_en_sync[0],fetch_en_i}; + boot_cs <= boot_ns; + end + end + + // read logic + always_comb + begin + rdata_n = '0; + + if (speriph_slave.req && speriph_slave.wen) + begin + + case (speriph_slave.add[7:6]) + 2'b00: begin + case (speriph_slave.add[5:3]) + 3'b000: + begin + rdata_n[0] = eoc_o; + end + + 3'b001: + begin + rdata_n[NB_CORES-1:0] = fetch_en_q; + end + + 3'b011: + // +---------------------------------------------------------+ + // ADDR | unused | fregfile_dis | hwpe_en | hwpe_sel | unused | + // 0x18 | 31..13 | 12 | 11 | 10 | 9..0 | + // +---------------------------------------------------------+ + begin + rdata_n[OFFSET_2+OFFSET_1+1] = 0; + rdata_n[OFFSET_2+OFFSET_1 ] = 0; + rdata_n[OFFSET_2+OFFSET_1-1:OFFSET_1] = 0; + rdata_n[OFFSET_1-1:0] = 0; + rdata_n[OFFSET_2+OFFSET_1+2] = hwpe_sel_o; + rdata_n[OFFSET_2+OFFSET_1+3] = hwpe_en_o; + rdata_n[OFFSET_2+OFFSET_1+4] = fregfile_disable_o; + end + + 3'b100: rdata_n[0] = cluster_cg_en_o; + 3'b101: rdata_n[NB_CORES-1:0] = core_halted_i[NB_CORES-1:0]; + 3'b111: rdata_n[NB_CORES-1:0] = dbg_halt_mask_q[NB_CORES-1:0]; + + default:; + endcase + end + + 2'b01: + begin + rdata_n = boot_addr_n[speriph_slave.add[5:2]]; + end + + 2'b10, 2'b11: + begin + case(speriph_slave.add[3]) + 1'b0: + begin + rdata_n[0] = TCDM_arb_policy_o[0]; + end + + 1'b1: + begin + rdata_n[0] = TCDM_arb_policy_o[1]; + end + endcase // speriph_slave.add[3] + end + + endcase // speriph_slave.add[7:6] + end + end + + // write logic + always_comb + begin + hwpe_sel_n = hwpe_sel_o; + hwpe_en_n = hwpe_en_o; + + fregfile_disable_n = fregfile_disable_o; + + fetch_en_n = fetch_en_q; + eoc_n = eoc_o; + event_n = event_o; + + boot_addr_n = boot_addr_o; + cluster_cg_en_n = cluster_cg_en_o; + + TCDM_arb_policy_n = TCDM_arb_policy_o; + + core_resume_o = '0; + dbg_halt_mask_n = dbg_halt_mask_q; + + if (speriph_slave.req && (~speriph_slave.wen)) + begin + + case (speriph_slave.add[7:6]) + 2'b00: + begin + case (speriph_slave.add[5:3]) + 3'b000: begin + eoc_n = speriph_slave.wdata[0]; + end + + 3'b001: begin + fetch_en_n[NB_CORES-1:0] = speriph_slave.wdata[NB_CORES-1:0]; + end + + 3'b010: begin + event_n = speriph_slave.wdata[0]; + end + + 3'b011: begin + hwpe_sel_n = speriph_slave.wdata[OFFSET_2+OFFSET_1+2]; + hwpe_en_n = speriph_slave.wdata[OFFSET_2+OFFSET_1+3]; + fregfile_disable_n = speriph_slave.wdata[OFFSET_2+OFFSET_1+4]; + end + 3'b100: begin + cluster_cg_en_n = speriph_slave.wdata[0]; + end + 3'b101: begin // Debug Status/Resume + core_resume_o = speriph_slave.wdata[NB_CORES-1:0]; + end + 3'b111: begin // Debug Halt Mask + dbg_halt_mask_n = speriph_slave.wdata[NB_CORES-1:0]; + end + endcase + end + 2'b01: + begin + boot_addr_n[speriph_slave.add[5:2]] = speriph_slave.wdata; + end + + 2'b11,2'b10: + begin + case (speriph_slave.add[5:3]) + 3'b000: TCDM_arb_policy_n[0] = speriph_slave.wdata[0]; + 3'b001: TCDM_arb_policy_n[1] = speriph_slave.wdata[0]; + endcase + end + endcase // speriph_slave.add[7:6] + end + end + + + always_ff @(posedge clk_i, negedge rst_ni) + begin + if(rst_ni == 1'b0) + begin + rdata_q <= '0; + id_q <= '0; + rvalid_q <= 1'b0; + + hwpe_sel_o <= 1'b1; + hwpe_en_o <= 1'b0; + + fregfile_disable_o<= 1'b0; + + fetch_en_q <= '0; + eoc_o <= 1'b0; + event_o <= 1'b0; + + dbg_halt_mask_q <= '0; + core_halted_any_q <= 1'b0; + + cluster_cg_en_o <= 1'b0; + TCDM_arb_policy_o <= 2'b00; + + boot_addr_o <= '{default: BOOT_ADDR}; + end + else + begin + rvalid_q <= rvalid_n; + + if (rvalid_n) + begin + rdata_q <= rdata_n; + id_q <= id_n; + end + + hwpe_sel_o <= hwpe_sel_n; + hwpe_en_o <= hwpe_en_n; + + fregfile_disable_o<= fregfile_disable_n; + + cluster_cg_en_o <= cluster_cg_en_n; + + eoc_o <= eoc_n; + event_o <= event_n; + + dbg_halt_mask_q <= dbg_halt_mask_n; + core_halted_any_q <= core_halted_any_n; + + boot_addr_o <= boot_addr_n; + + TCDM_arb_policy_o <= TCDM_arb_policy_n; + + if (start_fetch) + fetch_en_q <= '1; + else + fetch_en_q <= fetch_en_n; + + if (start_boot) begin + boot_addr_o[0] <= ROM_BOOT_ADDR; + fetch_en_q[0] <= 1'b1; + end + end + end + + // debug halt mode handling + assign core_halted_any_n = (|(core_halted_i & dbg_halt_mask_q)) & (~core_resume_o); + assign core_halt_rising_edge = (~core_halted_any_q) & core_halted_any_n; + + assign core_halt_o = {NB_CORES{core_halt_rising_edge}} & dbg_halt_mask_q; + + // to check with igor + assign speriph_slave.gnt = 1'b1; + assign speriph_slave.r_valid = rvalid_q; + assign speriph_slave.r_opc = 1'b0; + assign speriph_slave.r_id = id_q; + assign speriph_slave.r_rdata = rdata_q; + + assign rvalid_n = speriph_slave.req; + assign id_n = speriph_slave.id; + +endmodule diff --git a/hw/deps/cluster_peripherals/icache_ctrl_unit/interfaces/mp_pf_icache_ctrl_unit_bus.sv b/hw/deps/cluster_peripherals/icache_ctrl_unit/interfaces/mp_pf_icache_ctrl_unit_bus.sv new file mode 100644 index 0000000..975ad28 --- /dev/null +++ b/hw/deps/cluster_peripherals/icache_ctrl_unit/interfaces/mp_pf_icache_ctrl_unit_bus.sv @@ -0,0 +1,55 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +interface MP_PF_ICACHE_CTRL_UNIT_BUS #( + parameter int NB_CORES = 4 +); + + logic bypass_req; + logic [NB_CORES:0] bypass_ack; // NB_CORES + 1 + logic flush_req; + logic flush_ack; + + logic sel_flush_req; + logic [31:0] sel_flush_addr; + logic sel_flush_ack; + + logic [31:0] pf_addr; + logic [7:0] pf_size; + logic pf_req; + logic pf_ack; + logic pf_done; + + logic [31:0] global_hit_count; + logic [31:0] global_trans_count; + logic [31:0] global_miss_count; + + logic [NB_CORES-1:0][31:0] bank_hit_count; + logic [NB_CORES-1:0][31:0] bank_trans_count; + logic [NB_CORES-1:0][31:0] bank_miss_count; + + logic ctrl_clear_regs; + logic ctrl_enable_regs; + + modport Master ( + output bypass_req, flush_req, sel_flush_req, sel_flush_addr, pf_addr, pf_size, pf_req, + ctrl_clear_regs, ctrl_enable_regs, + input bypass_ack, flush_ack, sel_flush_ack, pf_ack, pf_done, global_hit_count, + global_trans_count, global_miss_count, bank_hit_count, bank_trans_count, bank_miss_count + ); + + modport Slave ( + input bypass_req, flush_req, sel_flush_req, sel_flush_addr, pf_addr, pf_size, pf_req, + ctrl_clear_regs, ctrl_enable_regs, + output bypass_ack, flush_ack, sel_flush_ack, pf_ack, pf_done, global_hit_count, + global_trans_count, global_miss_count, bank_hit_count, bank_trans_count, bank_miss_count + ); + +endinterface diff --git a/hw/deps/cluster_peripherals/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv b/hw/deps/cluster_peripherals/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv new file mode 100644 index 0000000..72adb04 --- /dev/null +++ b/hw/deps/cluster_peripherals/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv @@ -0,0 +1,432 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// ============================================================================= // +// Company: Multitherman Laboratory @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// Create Date: 18/08/2014 // +// Design Name: icache_ctrl_unit // +// Module Name: icache_ctrl_unit // +// Project Name: PULP // +// Language: SystemVerilog // +// // +// Description: ICACHE control Unit, used to enable/disable icache banks // +// flush operations, and to debug the status og cache banks // +// // +// Revision: // +// Revision v0.1 - File Created // +// // +// ============================================================================= // + + `define ENABLE_ICACHE 6'b00_0000 + `define FLUSH_ICACHE 6'b00_0001 + `define SEL_FLUSH_ICACHE 6'b00_0011 + + `define PF_SIZE 6'b00_1000 + `define PF_ADDR 6'b00_1001 + + `define CLEAR_CNTS 6'b00_0100 + `define ENABLE_CNTS 6'b00_0101 + + `define READ_ICACHE_HIT_CORES 6'b01_0000 // R Only + `define READ_ICACHE_TRANS_CORES 6'b01_0001 // R Only + `define READ_ICACHE_MISS_CORES 6'b01_0001 // R Only + +//-----------------------------------// + + +module mp_pf_icache_ctrl_unit +#( + parameter int NB_CACHE_BANKS = 4, + parameter int NB_CORES = 4, + parameter int ID_WIDTH = 5, + parameter bit FEATURE_STAT = 1'b0 +) +( + input logic clk_i, + input logic rst_ni, + + XBAR_PERIPH_BUS.Slave speriph_slave, + MP_PF_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_master_if, + + output logic pf_event_o +); + + int unsigned i,j,k,x,y; + + localparam NUM_REGS = 16; + + logic icache_bypass_req_o; + logic [NB_CORES:0] icache_bypass_ack_i; + + logic icache_flush_req_o; + logic icache_flush_ack_i; + + logic icache_sel_flush_req_o; + logic [31:0] icache_sel_flush_addr_o; + logic icache_sel_flush_ack_i; + + logic [31:0] pf_addr_o; + logic [7:0] pf_size_o; + logic pf_req_o; + logic pf_ack_i; + logic pf_done_i; + + + logic [31:0] ICACHE_CTRL_REGS[NUM_REGS]; + + // State of the main FSM + enum logic [2:0] { IDLE, ENABLE_ICACHE, DISABLE_ICACHE, FLUSH_ICACHE_CHECK, SEL_FLUSH_ICACHE, + CLEAR_STAT_REGS, ENABLE_STAT_REGS, TRIGGER_PF } CS, NS; + + // Exploded Interface --> PERIPHERAL INTERFACE + logic req; + logic [31:0] addr; + logic wen; + logic [31:0] wdata; + logic [3:0] be; + logic gnt; + logic [ID_WIDTH-1:0] id; + logic r_valid; + logic r_opc; + logic [ID_WIDTH-1:0] r_id; + logic [31:0] r_rdata; + + + // Internal FSM signals --> responses + logic r_valid_int; + logic [31:0] r_rdata_int; + + logic [NB_CORES-1:0] [31:0] hit_count; + logic [NB_CORES-1:0] [31:0] trans_count; + logic [NB_CORES-1:0] [31:0] miss_count; + logic [NB_CORES-1:0] clear_regs; + logic [NB_CORES-1:0] enable_regs; + + logic [31:0] global_hit_count; + logic [31:0] global_trans_count; + logic [31:0] global_miss_count; + + logic [7:0][31:0] bank_hit_count; + logic [7:0][31:0] bank_trans_count; + logic [7:0][31:0] bank_miss_count; + + logic is_write; + logic deliver_response; + logic clear_flush_reg; + + + // Interface binding + assign speriph_slave.gnt = gnt; + assign req = speriph_slave.req; + assign addr = speriph_slave.add; + assign wen = speriph_slave.wen; + assign wdata = speriph_slave.wdata; + assign be = speriph_slave.be; + assign id = speriph_slave.id; + assign speriph_slave.r_valid = r_valid; + assign speriph_slave.r_opc = r_opc; + assign speriph_slave.r_id = r_id; + assign speriph_slave.r_rdata = r_rdata; + + + + + genvar index; + + assign IC_ctrl_unit_master_if.pf_addr = pf_addr_o; + assign IC_ctrl_unit_master_if.pf_size = pf_size_o; + assign IC_ctrl_unit_master_if.pf_req = pf_req_o; + assign pf_ack_i = IC_ctrl_unit_master_if.pf_ack; + assign pf_done_i = IC_ctrl_unit_master_if.pf_done; + + assign IC_ctrl_unit_master_if.bypass_req = icache_bypass_req_o; + assign icache_bypass_ack_i = IC_ctrl_unit_master_if.bypass_ack; + assign IC_ctrl_unit_master_if.flush_req = icache_flush_req_o; + assign icache_flush_ack_i = IC_ctrl_unit_master_if.flush_ack; + + assign IC_ctrl_unit_master_if.sel_flush_req = icache_sel_flush_req_o; + assign IC_ctrl_unit_master_if.sel_flush_addr = icache_sel_flush_addr_o; + assign icache_sel_flush_ack_i = IC_ctrl_unit_master_if.sel_flush_ack; + + + if (FEATURE_STAT) begin + assign IC_ctrl_unit_master_if.ctrl_clear_regs = clear_regs; + assign IC_ctrl_unit_master_if.ctrl_enable_regs = enable_regs; + + assign global_hit_count = IC_ctrl_unit_master_if.global_hit_count; + assign global_trans_count = IC_ctrl_unit_master_if.global_trans_count; + assign global_miss_count = IC_ctrl_unit_master_if.global_miss_count; + + assign bank_hit_count[NB_CORES-1:0] = IC_ctrl_unit_master_if.bank_hit_count; + assign bank_trans_count[NB_CORES-1:0] = IC_ctrl_unit_master_if.bank_trans_count; + assign bank_miss_count[NB_CORES-1:0] = IC_ctrl_unit_master_if.bank_miss_count; + end + + + always_comb + begin : REGISTER_BIND_OUT + icache_bypass_req_o = ~ICACHE_CTRL_REGS[`ENABLE_ICACHE]; + icache_flush_req_o = ICACHE_CTRL_REGS[`FLUSH_ICACHE]; + icache_sel_flush_addr_o = ICACHE_CTRL_REGS[`SEL_FLUSH_ICACHE]; + + pf_addr_o = ICACHE_CTRL_REGS[`PF_ADDR][31:0]; + pf_size_o = ICACHE_CTRL_REGS[`PF_SIZE][7:0]; + + if (FEATURE_STAT) begin + enable_regs = ICACHE_CTRL_REGS[`ENABLE_CNTS][NB_CACHE_BANKS-1:0]; + end + end + + + + always_ff @(posedge clk_i, negedge rst_ni) + begin : SEQ_PROC + if(rst_ni == 1'b0) + begin + CS <= IDLE; + r_id <= '0; + r_valid <= 1'b0; + r_rdata <= '0; + r_opc <= '0; + + for(i=0;i all bypassed; 00000 --> all enabled + begin + NS = IDLE; + deliver_response = 1'b1; + end + else + begin + NS = ENABLE_ICACHE; + end + end //~ENABLE_ICACHE + + + + DISABLE_ICACHE: + begin + gnt = 1'b0; + + if(&icache_bypass_ack_i == 1'b1) //11111 --> all bypassed; 00000 --> all enabled + begin + NS = IDLE; + deliver_response = 1'b1; + end + else + begin + NS = DISABLE_ICACHE; + end + end //~DIABLE_ICACHE + + + + + FLUSH_ICACHE_CHECK: + begin + gnt = 1'b0; + + if(icache_flush_ack_i) + begin + NS = IDLE; + deliver_response = 1'b1; + clear_flush_reg = 1'b1; + end + else + begin + NS = FLUSH_ICACHE_CHECK; + end + end + + + SEL_FLUSH_ICACHE: + begin + + if(icache_sel_flush_ack_i) + begin + gnt = 1'b1; + NS = IDLE; + + deliver_response = 1'b1; + end + else + begin + NS = SEL_FLUSH_ICACHE; + end + end + + TRIGGER_PF: + begin + pf_req_o = 1'b1; + + if(pf_ack_i) + begin + NS = IDLE; + deliver_response = 1'b1; + end + else + begin + NS = TRIGGER_PF; + end + end + + + default : + begin + NS = IDLE; + end + endcase + end + + assign pf_event_o = pf_done_i; + +endmodule diff --git a/hw/deps/common_cells/src/addr_decode.sv b/hw/deps/common_cells/src/addr_decode.sv new file mode 100644 index 0000000..0b25a89 --- /dev/null +++ b/hw/deps/common_cells/src/addr_decode.sv @@ -0,0 +1,159 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +/// Address Decoder: Maps the input address combinatorially to an index. +/// The address map `addr_map_i` is a packed array of rule_t structs. +/// The ranges of any two rules may overlap. If so, the rule at the higher (more significant) +/// position in `addr_map_i` prevails. +/// +/// There can be an arbitrary number of address rules. There can be multiple +/// ranges defined for the same index. The start address has to be less than the end address. +/// +/// There is the possibility to add a default mapping: +/// `en_default_idx_i`: Driving this port to `1'b1` maps all input addresses +/// for which no rule in `addr_map_i` exists to the default index specified by +/// `default_idx_i`. In this case, `dec_error_o` is always `1'b0`. +/// +/// Assertions: The module checks every time there is a change in the address mapping +/// if the resulting map is valid. It fatals if `start_addr` is higher than `end_addr` +/// or if a mapping targets an index that is outside the number of allowed indices. +/// It issues warnings if the address regions of any two mappings overlap. +module addr_decode #( + /// Highest index which can happen in a rule. + parameter int unsigned NoIndices = 32'd0, + /// Total number of rules. + parameter int unsigned NoRules = 32'd0, + /// Address type inside the rules and to decode. + parameter type addr_t = logic, + /// Rule packed struct type. + /// The address decoder expects three fields in `rule_t`: + /// + /// typedef struct packed { + /// int unsigned idx; + /// addr_t start_addr; + /// addr_t end_addr; + /// } rule_t; + /// + /// - `idx`: index of the rule, has to be < `NoIndices` + /// - `start_addr`: start address of the range the rule describes, value is included in range + /// - `end_addr`: end address of the range the rule describes, value is NOT included in range + parameter type rule_t = logic, + /// Dependent parameter, do **not** overwite! + /// + /// Width of the `idx_o` output port. + parameter int unsigned IdxWidth = cf_math_pkg::idx_width(NoIndices), + /// Dependent parameter, do **not** overwite! + /// + /// Type of the `idx_o` output port. + parameter type idx_t = logic [IdxWidth-1:0] +) ( + /// Address to decode. + input addr_t addr_i, + /// Address map: rule with the highest array position wins on collision + input rule_t [NoRules-1:0] addr_map_i, + /// Decoded index. + output idx_t idx_o, + /// Decode is valid. + output logic dec_valid_o, + /// Decode is not valid, no matching rule found. + output logic dec_error_o, + /// Enable default port mapping. + /// + /// When not used, tie to `0`. + input logic en_default_idx_i, + /// Default port index. + /// + /// When `en_default_idx_i` is `1`, this will be the index when no rule matches. + /// + /// When not used, tie to `0`. + input idx_t default_idx_i +); + + logic [NoRules-1:0] matched_rules; // purely for address map debugging + + always_comb begin + // default assignments + matched_rules = '0; + dec_valid_o = 1'b0; + dec_error_o = (en_default_idx_i) ? 1'b0 : 1'b1; + idx_o = (en_default_idx_i) ? default_idx_i : '0; + + // match the rules + for (int unsigned i = 0; i < NoRules; i++) begin + if ((addr_i >= addr_map_i[i].start_addr) && (addr_i < addr_map_i[i].end_addr)) begin + matched_rules[i] = 1'b1; + dec_valid_o = 1'b1; + dec_error_o = 1'b0; + idx_o = idx_t'(addr_map_i[i].idx); + end + end + end + + // Assumptions and assertions + `ifndef VERILATOR + // pragma translate_off + initial begin : proc_check_parameters + assume ($bits(addr_i) == $bits(addr_map_i[0].start_addr)) else + $warning($sformatf("Input address has %d bits and address map has %d bits.", + $bits(addr_i), $bits(addr_map_i[0].start_addr))); + assume (NoRules > 0) else + $fatal(1, $sformatf("At least one rule needed")); + assume (NoIndices > 0) else + $fatal(1, $sformatf("At least one index needed")); + end + + assert final ($onehot0(matched_rules)) else + $warning("More than one bit set in the one-hot signal, matched_rules"); + + // These following assumptions check the validity of the address map. + // The assumptions gets generated for each distinct pair of rules. + // Each assumption is present two times, as they rely on one rules being + // effectively ordered. Only one of the rules with the same function is + // active at a time for a given pair. + // check_start: Enforces a smaller start than end address. + // check_idx: Enforces a valid index in the rule. + // check_overlap: Warns if there are overlapping address regions. + always @(addr_map_i) #0 begin : proc_check_addr_map + if (!$isunknown(addr_map_i)) begin + for (int unsigned i = 0; i < NoRules; i++) begin + check_start : assume (addr_map_i[i].start_addr < addr_map_i[i].end_addr) else + $fatal(1, $sformatf("This rule has a higher start than end address!!!\n\ + Violating rule %d.\n\ + Rule> IDX: %h START: %h END: %h\n\ + #####################################################", + i ,addr_map_i[i].idx, addr_map_i[i].start_addr, addr_map_i[i].end_addr)); + // check the SLV ids + check_idx : assume (addr_map_i[i].idx < NoIndices) else + $fatal(1, $sformatf("This rule has a IDX that is not allowed!!!\n\ + Violating rule %d.\n\ + Rule> IDX: %h START: %h END: %h\n\ + Rule> MAX_IDX: %h\n\ + #####################################################", + i, addr_map_i[i].idx, addr_map_i[i].start_addr, addr_map_i[i].end_addr, + (NoIndices-1))); + for (int unsigned j = i + 1; j < NoRules; j++) begin + // overlap check + check_overlap : assume (!((addr_map_i[j].start_addr < addr_map_i[i].end_addr) && + (addr_map_i[j].end_addr > addr_map_i[i].start_addr))) else + $warning($sformatf("Overlapping address region found!!!\n\ + Rule %d: IDX: %h START: %h END: %h\n\ + Rule %d: IDX: %h START: %h END: %h\n\ + #####################################################", + i, addr_map_i[i].idx, addr_map_i[i].start_addr, addr_map_i[i].end_addr, + j, addr_map_i[j].idx, addr_map_i[j].start_addr, addr_map_i[j].end_addr)); + end + end + end + end + // pragma translate_on + `endif +endmodule diff --git a/hw/deps/common_cells/src/cf_math_pkg.sv b/hw/deps/common_cells/src/cf_math_pkg.sv new file mode 100644 index 0000000..c957dcf --- /dev/null +++ b/hw/deps/common_cells/src/cf_math_pkg.sv @@ -0,0 +1,85 @@ +// Copyright 2016 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// cf_math_pkg: Constant Function Implementations of Mathematical Functions for HDL Elaboration +/// +/// This package contains a collection of mathematical functions that are commonly used when defining +/// the value of constants in HDL code. These functions are implemented as Verilog constants +/// functions. Introduced in Verilog 2001 (IEEE Std 1364-2001), a constant function (§ 10.3.5) is a +/// function whose value can be evaluated at compile time or during elaboration. A constant function +/// must be called with arguments that are constants. +package cf_math_pkg; + + /// Ceiled Division of Two Natural Numbers + /// + /// Returns the quotient of two natural numbers, rounded towards plus infinity. + function automatic integer ceil_div (input longint dividend, input longint divisor); + automatic longint remainder; + + // pragma translate_off + `ifndef VERILATOR + if (dividend < 0) begin + $fatal(1, "Dividend %0d is not a natural number!", dividend); + end + + if (divisor < 0) begin + $fatal(1, "Divisor %0d is not a natural number!", divisor); + end + + if (divisor == 0) begin + $fatal(1, "Division by zero!"); + end + `endif + // pragma translate_on + + remainder = dividend; + for (ceil_div = 0; remainder > 0; ceil_div++) begin + remainder = remainder - divisor; + end + endfunction + + /// Index width required to be able to represent up to `num_idx` indices as a binary + /// encoded signal. + /// Ensures that the minimum width if an index signal is `1`, regardless of parametrization. + /// + /// Sample usage in type definition: + /// As parameter: + /// `parameter type idx_t = logic[cf_math_pkg::idx_width(NumIdx)-1:0]` + /// As typedef: + /// `typedef logic [cf_math_pkg::idx_width(NumIdx)-1:0] idx_t` + function automatic integer unsigned idx_width (input integer unsigned num_idx); + return (num_idx > 32'd1) ? unsigned'($clog2(num_idx)) : 32'd1; + endfunction + + /// Ceiled Binary Logarithm of a Natural Number + /// + /// Returns the binary logarithm (i.e., the logarithm to the base 2) of a natural number rounded + /// towards plus infinity. + /// + /// Use this as drop-in replacement for the `$clog2` system function where the latter is not + /// supported by your toolchain. + function integer clog2 (input longint unsigned val); + automatic longint unsigned tmp; + + // pragma translate_off + `ifndef VERILATOR + if (val == 0) begin + $fatal(1, "Logarithm of 0 cannot be represented!"); + end + `endif + // pragma translate_on + + tmp = val - 1; + for (clog2 = 0; tmp > 0; clog2++) begin + tmp = tmp >> 1; + end + endfunction + +endpackage diff --git a/hw/deps/common_cells/src/counter.sv b/hw/deps/common_cells/src/counter.sv new file mode 100644 index 0000000..43392e4 --- /dev/null +++ b/hw/deps/common_cells/src/counter.sv @@ -0,0 +1,43 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba +// Description: Generic up/down counter + +module counter #( + parameter int unsigned WIDTH = 4, + parameter bit STICKY_OVERFLOW = 1'b0 +)( + input logic clk_i, + input logic rst_ni, + input logic clear_i, // synchronous clear + input logic en_i, // enable the counter + input logic load_i, // load a new value + input logic down_i, // downcount, default is up + input logic [WIDTH-1:0] d_i, + output logic [WIDTH-1:0] q_o, + output logic overflow_o +); + delta_counter #( + .WIDTH (WIDTH), + .STICKY_OVERFLOW (STICKY_OVERFLOW) + ) i_counter ( + .clk_i, + .rst_ni, + .clear_i, + .en_i, + .load_i, + .down_i, + .delta_i({{WIDTH-1{1'b0}}, 1'b1}), + .d_i, + .q_o, + .overflow_o + ); +endmodule diff --git a/hw/deps/common_cells/src/delta_counter.sv b/hw/deps/common_cells/src/delta_counter.sv new file mode 100644 index 0000000..90b5cff --- /dev/null +++ b/hw/deps/common_cells/src/delta_counter.sv @@ -0,0 +1,74 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Up/down counter with variable delta + +module delta_counter #( + parameter int unsigned WIDTH = 4, + parameter bit STICKY_OVERFLOW = 1'b0 +)( + input logic clk_i, + input logic rst_ni, + input logic clear_i, // synchronous clear + input logic en_i, // enable the counter + input logic load_i, // load a new value + input logic down_i, // downcount, default is up + input logic [WIDTH-1:0] delta_i, + input logic [WIDTH-1:0] d_i, + output logic [WIDTH-1:0] q_o, + output logic overflow_o +); + logic [WIDTH:0] counter_q, counter_d; + if (STICKY_OVERFLOW) begin : gen_sticky_overflow + logic overflow_d, overflow_q; + always_ff @(posedge clk_i or negedge rst_ni) overflow_q <= ~rst_ni ? 1'b0 : overflow_d; + always_comb begin + overflow_d = overflow_q; + if (clear_i || load_i) begin + overflow_d = 1'b0; + end else if (!overflow_q && en_i) begin + if (down_i) begin + overflow_d = delta_i > counter_q[WIDTH-1:0]; + end else begin + overflow_d = counter_q[WIDTH-1:0] > ({WIDTH{1'b1}} - delta_i); + end + end + end + assign overflow_o = overflow_q; + end else begin : gen_transient_overflow + // counter overflowed if the MSB is set + assign overflow_o = counter_q[WIDTH]; + end + assign q_o = counter_q[WIDTH-1:0]; + + always_comb begin + counter_d = counter_q; + + if (clear_i) begin + counter_d = '0; + end else if (load_i) begin + counter_d = {1'b0, d_i}; + end else if (en_i) begin + if (down_i) begin + counter_d = counter_q - delta_i; + end else begin + counter_d = counter_q + delta_i; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + counter_q <= '0; + end else begin + counter_q <= counter_d; + end + end +endmodule diff --git a/hw/deps/common_cells/src/deprecated/fifo_v1.sv b/hw/deps/common_cells/src/deprecated/fifo_v1.sv new file mode 100644 index 0000000..31295e8 --- /dev/null +++ b/hw/deps/common_cells/src/deprecated/fifo_v1.sv @@ -0,0 +1,57 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba + +/* verilator lint_off DECLFILENAME */ +module fifo #( + parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic + parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 + parameter int unsigned THRESHOLD = 1, // fill count until when to assert threshold_o + parameter type dtype = logic [DATA_WIDTH-1:0] +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the queue + input logic testmode_i, // test_mode to bypass clock gating + // status flags + output logic full_o, // queue is full + output logic empty_o, // queue is empty + output logic threshold_o, // the FIFO is above the specified threshold + // as long as the queue is not full we can push new data + input dtype data_i, // data to push into the queue + input logic push_i, // data is valid and can be pushed to the queue + // as long as the queue is not empty we can pop new elements + output dtype data_o, // output data + input logic pop_i // pop head from queue +); + fifo_v2 #( + .FALL_THROUGH ( FALL_THROUGH ), + .DATA_WIDTH ( DATA_WIDTH ), + .DEPTH ( DEPTH ), + .ALM_FULL_TH ( THRESHOLD ), + .dtype ( dtype ) + ) impl ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( flush_i ), + .testmode_i ( testmode_i ), + .full_o ( full_o ), + .empty_o ( empty_o ), + .alm_full_o ( threshold_o ), + .alm_empty_o ( ), + .data_i ( data_i ), + .push_i ( push_i ), + .data_o ( data_o ), + .pop_i ( pop_i ) + ); +endmodule +/* verilator lint_on DECLFILENAME */ diff --git a/hw/deps/common_cells/src/deprecated/fifo_v2.sv b/hw/deps/common_cells/src/deprecated/fifo_v2.sv new file mode 100644 index 0000000..9c87ed9 --- /dev/null +++ b/hw/deps/common_cells/src/deprecated/fifo_v2.sv @@ -0,0 +1,79 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba + +module fifo_v2 #( + parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic + parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 + parameter int unsigned ALM_EMPTY_TH = 1, // almost empty threshold (when to assert alm_empty_o) + parameter int unsigned ALM_FULL_TH = 1, // almost full threshold (when to assert alm_full_o) + parameter type dtype = logic [DATA_WIDTH-1:0], + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the queue + input logic testmode_i, // test_mode to bypass clock gating + // status flags + output logic full_o, // queue is full + output logic empty_o, // queue is empty + output logic alm_full_o, // FIFO fillstate >= the specified threshold + output logic alm_empty_o, // FIFO fillstate <= the specified threshold + // as long as the queue is not full we can push new data + input dtype data_i, // data to push into the queue + input logic push_i, // data is valid and can be pushed to the queue + // as long as the queue is not empty we can pop new elements + output dtype data_o, // output data + input logic pop_i // pop head from queue +); + + logic [ADDR_DEPTH-1:0] usage; + + // generate threshold parameters + if (DEPTH == 0) begin + assign alm_full_o = 1'b0; // that signal does not make any sense in a FIFO of depth 0 + assign alm_empty_o = 1'b0; // that signal does not make any sense in a FIFO of depth 0 + end else begin + assign alm_full_o = (usage >= ALM_FULL_TH[ADDR_DEPTH-1:0]); + assign alm_empty_o = (usage <= ALM_EMPTY_TH[ADDR_DEPTH-1:0]); + end + + fifo_v3 #( + .FALL_THROUGH ( FALL_THROUGH ), + .DATA_WIDTH ( DATA_WIDTH ), + .DEPTH ( DEPTH ), + .dtype ( dtype ) + ) i_fifo_v3 ( + .clk_i, + .rst_ni, + .flush_i, + .testmode_i, + .full_o, + .empty_o, + .usage_o (usage), + .data_i, + .push_i, + .data_o, + .pop_i + ); + + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (ALM_FULL_TH <= DEPTH) else $error("ALM_FULL_TH can't be larger than the DEPTH."); + assert (ALM_EMPTY_TH <= DEPTH) else $error("ALM_EMPTY_TH can't be larger than the DEPTH."); + end + `endif + // pragma translate_on + +endmodule // fifo_v2 diff --git a/hw/deps/common_cells/src/deprecated/generic_LFSR_8bit.sv b/hw/deps/common_cells/src/deprecated/generic_LFSR_8bit.sv new file mode 100644 index 0000000..fb0080a --- /dev/null +++ b/hw/deps/common_cells/src/deprecated/generic_LFSR_8bit.sv @@ -0,0 +1,64 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Igor Loi + +module generic_LFSR_8bit + #( + parameter OH_WIDTH = 4, + parameter BIN_WIDTH = $clog2(OH_WIDTH), + parameter SEED = 8'b00000000 + ) + ( + output logic [OH_WIDTH-1:0] data_OH_o, // One hot encoding + output logic [BIN_WIDTH-1:0] data_BIN_o, // Binary encoding + input logic enable_i, // + input logic clk, // + input logic rst_n // + ); + + logic [7:0] out; + logic linear_feedback; + logic [BIN_WIDTH-1:0] temp_ref_way; + + + //-------------Code Starts Here------- + assign linear_feedback = !(out[7] ^ out[3] ^ out[2] ^ out[1]); // TAPS for XOR feedback + + assign data_BIN_o = temp_ref_way; + + always_ff @(posedge clk, negedge rst_n) + begin + if (rst_n == 1'b0) + begin + out <= SEED ; + end + else if (enable_i) + begin + out <= {out[6],out[5],out[4],out[3],out[2],out[1],out[0], linear_feedback}; + end + end + + generate + + if(OH_WIDTH == 2) + assign temp_ref_way = out[1]; + else + assign temp_ref_way = out[BIN_WIDTH:1]; + endgenerate + + // Bin to One Hot Encoder + always_comb + begin + data_OH_o = '0; + data_OH_o[temp_ref_way] = 1'b1; + end + +endmodule diff --git a/hw/deps/common_cells/src/deprecated/generic_fifo.sv b/hw/deps/common_cells/src/deprecated/generic_fifo.sv new file mode 100644 index 0000000..ece4aac --- /dev/null +++ b/hw/deps/common_cells/src/deprecated/generic_fifo.sv @@ -0,0 +1,274 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// ============================================================================= // +// Company: Multitherman Laboratory @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 01/02/2014 // +// Design Name: MISC // +// Module Name: generic_fifo // +// Project Name: PULP // +// Language: SystemVerilog // +// // +// Description: A simple FIFO used in the D_address_decoder, and D_allocator // +// to store the destinations ports // +// // +// Revision: // +// Revision v0.1 - 01/02/2014 : File Created // +// Revision v0.2 - 02/09/2015 : Updated with a global CG cell // +// // +// ============================================================================= // + +module generic_fifo +#( + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned DATA_DEPTH = 8 +) +( + input logic clk, + input logic rst_n, + //PUSH SIDE + input logic [DATA_WIDTH-1:0] data_i, + input logic valid_i, + output logic grant_o, + //POP SIDE + output logic [DATA_WIDTH-1:0] data_o, + output logic valid_o, + input logic grant_i, + + input logic test_mode_i +); + + + // Local Parameter + localparam int unsigned ADDR_DEPTH = $clog2(DATA_DEPTH); + enum logic [1:0] { EMPTY, FULL, MIDDLE } CS, NS; + // Internal Signals + + logic gate_clock; + logic clk_gated; + + logic [ADDR_DEPTH-1:0] Pop_Pointer_CS, Pop_Pointer_NS; + logic [ADDR_DEPTH-1:0] Push_Pointer_CS, Push_Pointer_NS; + logic [DATA_WIDTH-1:0] FIFO_REGISTERS[DATA_DEPTH-1:0]; + int unsigned i; + + // Parameter Check + // synopsys translate_off + initial begin : parameter_check + integer param_err_flg; + param_err_flg = 0; + + if (DATA_WIDTH < 1) begin + param_err_flg = 1; + $display("ERROR: %m :\n Invalid value (%d) for parameter DATA_WIDTH (legal range: greater than 1)", DATA_WIDTH ); + end + + if (DATA_DEPTH < 1) begin + param_err_flg = 1; + $display("ERROR: %m :\n Invalid value (%d) for parameter DATA_DEPTH (legal range: greater than 1)", DATA_DEPTH ); + end + end + // synopsys translate_on + +`ifndef PULP_FPGA_EMUL + cluster_clock_gating cg_cell + ( + .clk_i ( clk ), + .en_i (~gate_clock ), + .test_en_i ( test_mode_i ), + .clk_o ( clk_gated ) + ); +`else + assign clk_gated = clk; +`endif + + // UPDATE THE STATE + always_ff @(posedge clk, negedge rst_n) + begin + if(rst_n == 1'b0) + begin + CS <= EMPTY; + Pop_Pointer_CS <= {ADDR_DEPTH {1'b0}}; + Push_Pointer_CS <= {ADDR_DEPTH {1'b0}}; + end + else + begin + CS <= NS; + Pop_Pointer_CS <= Pop_Pointer_NS; + Push_Pointer_CS <= Push_Pointer_NS; + end + end + + + // Compute Next State + always_comb + begin + gate_clock = 1'b0; + + case(CS) + + EMPTY: + begin + grant_o = 1'b1; + valid_o = 1'b0; + + case(valid_i) + 1'b0 : + begin + NS = EMPTY; + Push_Pointer_NS = Push_Pointer_CS; + Pop_Pointer_NS = Pop_Pointer_CS; + gate_clock = 1'b1; + end + + 1'b1: + begin + NS = MIDDLE; + Push_Pointer_NS = Push_Pointer_CS + 1'b1; + Pop_Pointer_NS = Pop_Pointer_CS; + end + + endcase + end//~EMPTY + + MIDDLE: + begin + grant_o = 1'b1; + valid_o = 1'b1; + + case({valid_i,grant_i}) + + 2'b01: + begin + gate_clock = 1'b1; + + if((Pop_Pointer_CS == Push_Pointer_CS -1 ) || ((Pop_Pointer_CS == DATA_DEPTH-1) && (Push_Pointer_CS == 0) )) + NS = EMPTY; + else + NS = MIDDLE; + + Push_Pointer_NS = Push_Pointer_CS; + + if(Pop_Pointer_CS == DATA_DEPTH-1) + Pop_Pointer_NS = 0; + else + Pop_Pointer_NS = Pop_Pointer_CS + 1'b1; + end + + 2'b00 : + begin + gate_clock = 1'b1; + NS = MIDDLE; + Push_Pointer_NS = Push_Pointer_CS; + Pop_Pointer_NS = Pop_Pointer_CS; + end + + 2'b11: + begin + NS = MIDDLE; + + if(Push_Pointer_CS == DATA_DEPTH-1) + Push_Pointer_NS = 0; + else + Push_Pointer_NS = Push_Pointer_CS + 1'b1; + + if(Pop_Pointer_CS == DATA_DEPTH-1) + Pop_Pointer_NS = 0; + else + Pop_Pointer_NS = Pop_Pointer_CS + 1'b1; + end + + 2'b10: + begin + if(( Push_Pointer_CS == Pop_Pointer_CS - 1) || ( (Push_Pointer_CS == DATA_DEPTH-1) && (Pop_Pointer_CS == 0) )) + NS = FULL; + else + NS = MIDDLE; + + if(Push_Pointer_CS == DATA_DEPTH - 1) + Push_Pointer_NS = 0; + else + Push_Pointer_NS = Push_Pointer_CS + 1'b1; + + Pop_Pointer_NS = Pop_Pointer_CS; + end + + endcase + end + + FULL: + begin + grant_o = 1'b0; + valid_o = 1'b1; + gate_clock = 1'b1; + + case(grant_i) + 1'b1: + begin + NS = MIDDLE; + + Push_Pointer_NS = Push_Pointer_CS; + + if(Pop_Pointer_CS == DATA_DEPTH-1) + Pop_Pointer_NS = 0; + else + Pop_Pointer_NS = Pop_Pointer_CS + 1'b1; + end + + 1'b0: + begin + NS = FULL; + Push_Pointer_NS = Push_Pointer_CS; + Pop_Pointer_NS = Pop_Pointer_CS; + end + endcase + + end // end of FULL + + default : + begin + gate_clock = 1'b1; + grant_o = 1'b0; + valid_o = 1'b0; + NS = EMPTY; + Pop_Pointer_NS = 0; + Push_Pointer_NS = 0; + end + + endcase + end + + always_ff @(posedge clk_gated, negedge rst_n) + begin + if(rst_n == 1'b0) + begin + for (i=0; i< DATA_DEPTH; i++) + FIFO_REGISTERS[i] <= {DATA_WIDTH {1'b0}}; + end + else + begin + if((grant_o == 1'b1) && (valid_i == 1'b1)) + FIFO_REGISTERS[Push_Pointer_CS] <= data_i; + end + end + + assign data_o = FIFO_REGISTERS[Pop_Pointer_CS]; + +endmodule // generic_fifo diff --git a/hw/deps/common_cells/src/edge_propagator_tx.sv b/hw/deps/common_cells/src/edge_propagator_tx.sv new file mode 100644 index 0000000..0274a43 --- /dev/null +++ b/hw/deps/common_cells/src/edge_propagator_tx.sv @@ -0,0 +1,40 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Antonio Pullini + +module edge_propagator_tx ( + input logic clk_i, + input logic rstn_i, + input logic valid_i, + input logic ack_i, + output logic valid_o +); + + logic [1:0] sync_a; + + logic r_input_reg; + logic s_input_reg_next; + + assign s_input_reg_next = valid_i | (r_input_reg & ~sync_a[0]); + + always @(negedge rstn_i or posedge clk_i) begin + if (~rstn_i) begin + r_input_reg <= 1'b0; + sync_a <= 2'b00; + end else begin + r_input_reg <= s_input_reg_next; + sync_a <= {ack_i,sync_a[1]}; + end + end + + assign valid_o = r_input_reg; + +endmodule diff --git a/hw/deps/common_cells/src/fall_through_register.sv b/hw/deps/common_cells/src/fall_through_register.sv new file mode 100644 index 0000000..fcbbe31 --- /dev/null +++ b/hw/deps/common_cells/src/fall_through_register.sv @@ -0,0 +1,58 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Fall-through register with a simple stream-like ready/valid handshake. +// This register does not cut combinatorial paths on any signals: in case the module at its output +// is ready to accept data within the same clock cycle, they are forwarded. Use this module to get a +// 'default ready' behavior towards the input. +module fall_through_register #( + parameter type T = logic // Vivado requires a default value for type parameters. +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous active-low reset + input logic clr_i, // Synchronous clear + input logic testmode_i, // Test mode to bypass clock gating + // Input port + input logic valid_i, + output logic ready_o, + input T data_i, + // Output port + output logic valid_o, + input logic ready_i, + output T data_o +); + + logic fifo_empty, + fifo_full; + + fifo_v2 #( + .FALL_THROUGH (1'b1), + .DATA_WIDTH ($size(T)), + .DEPTH (1), + .dtype (T) + ) i_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (clr_i), + .testmode_i (testmode_i), + .full_o (fifo_full), + .empty_o (fifo_empty), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i (data_i), + .push_i (valid_i & ~fifo_full), + .data_o (data_o), + .pop_i (ready_i & ~fifo_empty) + ); + + assign ready_o = ~fifo_full; + assign valid_o = ~fifo_empty; + +endmodule diff --git a/hw/deps/common_cells/src/fifo_v3.sv b/hw/deps/common_cells/src/fifo_v3.sv new file mode 100644 index 0000000..6da3268 --- /dev/null +++ b/hw/deps/common_cells/src/fifo_v3.sv @@ -0,0 +1,155 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba + +module fifo_v3 #( + parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic + parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 + parameter type dtype = logic [DATA_WIDTH-1:0], + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the queue + input logic testmode_i, // test_mode to bypass clock gating + // status flags + output logic full_o, // queue is full + output logic empty_o, // queue is empty + output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer + // as long as the queue is not full we can push new data + input dtype data_i, // data to push into the queue + input logic push_i, // data is valid and can be pushed to the queue + // as long as the queue is not empty we can pop new elements + output dtype data_o, // output data + input logic pop_i // pop head from queue +); + // local parameter + // FIFO depth - handle the case of pass-through, synthesizer will do constant propagation + localparam int unsigned FIFO_DEPTH = (DEPTH > 0) ? DEPTH : 1; + // clock gating control + logic gate_clock; + // pointer to the read and write section of the queue + logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q; + // keep a counter to keep track of the current queue status + logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q; // this integer will be truncated by the synthesis tool + // actual memory + dtype [FIFO_DEPTH - 1:0] mem_n, mem_q; + + assign usage_o = status_cnt_q[ADDR_DEPTH-1:0]; + + if (DEPTH == 0) begin + assign empty_o = ~push_i; + assign full_o = ~pop_i; + end else begin + assign full_o = (status_cnt_q == FIFO_DEPTH[ADDR_DEPTH:0]); + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + // status flags + + // read and write queue logic + always_comb begin : read_write_comb + // default assignment + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + status_cnt_n = status_cnt_q; + data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q]; + mem_n = mem_q; + gate_clock = 1'b1; + + // push a new element to the queue + if (push_i && ~full_o) begin + // push the data onto the queue + mem_n[write_pointer_q] = data_i; + // un-gate the clock, we want to write something + gate_clock = 1'b0; + // increment the write counter + if (write_pointer_q == FIFO_DEPTH[ADDR_DEPTH-1:0] - 1) + write_pointer_n = '0; + else + write_pointer_n = write_pointer_q + 1; + // increment the overall counter + status_cnt_n = status_cnt_q + 1; + end + + if (pop_i && ~empty_o) begin + // read from the queue is a default assignment + // but increment the read pointer... + if (read_pointer_n == FIFO_DEPTH[ADDR_DEPTH-1:0] - 1) + read_pointer_n = '0; + else + read_pointer_n = read_pointer_q + 1; + // ... and decrement the overall count + status_cnt_n = status_cnt_q - 1; + end + + // keep the count pointer stable if we push and pop at the same time + if (push_i && pop_i && ~full_o && ~empty_o) + status_cnt_n = status_cnt_q; + + // FIFO is in pass through mode -> do not change the pointers + if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin + data_o = data_i; + if (pop_i) begin + status_cnt_n = status_cnt_q; + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + end + end + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + end else begin + if (flush_i) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + end else begin + read_pointer_q <= read_pointer_n; + write_pointer_q <= write_pointer_n; + status_cnt_q <= status_cnt_n; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + /* verilator lint_off WIDTHCONCAT */ + mem_q <= '0; + /* verilator lint_on WIDTHCONCAT */ + end else if (!gate_clock) begin + mem_q <= mem_n; + end + end + +// pragma translate_off +`ifndef VERILATOR + initial begin + assert (DEPTH > 0) else $error("DEPTH must be greater than 0."); + end + + full_write : assert property( + @(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i)) + else $fatal (1, "Trying to push new data although the FIFO is full."); + + empty_read : assert property( + @(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i)) + else $fatal (1, "Trying to pop data although the FIFO is empty."); +`endif +// pragma translate_on + +endmodule // fifo_v3 diff --git a/hw/deps/common_cells/src/id_queue.sv b/hw/deps/common_cells/src/id_queue.sv new file mode 100644 index 0000000..f67d166 --- /dev/null +++ b/hw/deps/common_cells/src/id_queue.sv @@ -0,0 +1,277 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// ID Queue +// +// In an ID queue, every element has a numeric ID. Among all elements that have the same ID, the ID +// queue preserves FIFO order. +// +// This ID queue implementation allows to either push (through the `inp_*` signals) or pop (through +// the `oup_*` signals) one element per clock cycle. The `inp_` port has priority and grants a +// request iff the queue is not full. The `oup_` port dequeues an element iff `oup_pop_i` is +// asserted during an `oup_` handshake; otherwise, it performs a non-destructive read. `oup_data_o` +// is valid iff `oup_data_valid_o` is asserted during an `oup_` handshake. If `oup_data_valid_o` is +// not asserted, the queue did not contain an element with the provided ID. +// +// This ID queue additionally provides the `exists_` port, which searches for an element anywhere in +// the queue. The comparison performed during the search can be masked: for every bit that is +// asserted in `exists_mask_i`, the corresponding bit in the queue element and in `exists_data_i` +// must be equal for a match; the other bits are not compared. If masking is not required, tie +// `exists_mask_i_ to `'1` and the synthesizer should simplify the comparisons to unmasked ones. The +// `exists_` port operates independently of the `inp_` and `oup_` ports. If the `exists_` port is +// unused, tie `exists_req_i` to `1'b0` and the synthesizer should remove the internal comparators. +// +// This ID queue can store at most `CAPACITY` elements, independent of their ID. Let +// - C = `CAPACITY` +// - B = $bits(data_t) +// - I = 2**`ID_WIDTH` +// Then +// - the queue element storage requires O(C * (B + log2(C))) bit +// - the ID table requires O(H * log2(C)) bit, where H = min(C, I) +// +// Maintainers: +// - Andreas Kurth + +module id_queue #( + parameter int ID_WIDTH = 0, + parameter int CAPACITY = 0, + parameter type data_t = logic, + // Dependent parameters, DO NOT OVERRIDE! + localparam type id_t = logic[ID_WIDTH-1:0], + localparam type mask_t = logic[$bits(data_t)-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + input id_t inp_id_i, + input data_t inp_data_i, + input logic inp_req_i, + output logic inp_gnt_o, + + input data_t exists_data_i, + input mask_t exists_mask_i, + input logic exists_req_i, + output logic exists_o, + output logic exists_gnt_o, + + input id_t oup_id_i, + input logic oup_pop_i, + input logic oup_req_i, + output data_t oup_data_o, + output logic oup_data_valid_o, + output logic oup_gnt_o +); + + // Capacity of the head-tail table, which associates an ID with corresponding head and tail + // indices. + localparam int N_IDS = 2**ID_WIDTH; + localparam int HT_CAPACITY = (N_IDS <= CAPACITY) ? N_IDS : CAPACITY; + localparam int unsigned HT_IDX_WIDTH = HT_CAPACITY == 1 ? 1 : $clog2(HT_CAPACITY); + localparam int unsigned LD_IDX_WIDTH = CAPACITY == 1 ? 1 : $clog2(CAPACITY); + + // Type for indexing the head-tail table. + typedef logic [HT_IDX_WIDTH-1:0] ht_idx_t; + + // Type for indexing the lined data table. + typedef logic [LD_IDX_WIDTH-1:0] ld_idx_t; + + // Type of an entry in the head-tail table. + typedef struct packed { + id_t id; + ld_idx_t head, + tail; + logic free; + } head_tail_t; + + // Type of an entry in the linked data table. + typedef struct packed { + data_t data; + ld_idx_t next; + logic free; + } linked_data_t; + + head_tail_t [HT_CAPACITY-1:0] head_tail_d, head_tail_q; + + linked_data_t [CAPACITY-1:0] linked_data_d, linked_data_q; + + logic full, + match_id_valid, + no_id_match; + + logic [HT_CAPACITY-1:0] head_tail_free, + idx_matches_id; + + logic [CAPACITY-1:0] exists_match, + linked_data_free; + + id_t match_id; + + ht_idx_t head_tail_free_idx, + match_idx; + + ld_idx_t linked_data_free_idx; + + // Find the index in the head-tail table that matches a given ID. + for (genvar i = 0; i < HT_CAPACITY; i++) begin: gen_idx_match + assign idx_matches_id[i] = match_id_valid && (head_tail_q[i].id == match_id) && + !head_tail_q[i].free; + end + assign no_id_match = !(|idx_matches_id); + onehot_to_bin #( + .ONEHOT_WIDTH (HT_CAPACITY) + ) i_id_ohb ( + .onehot (idx_matches_id), + .bin (match_idx) + ); + + // Find the first free index in the head-tail table. + for (genvar i = 0; i < HT_CAPACITY; i++) begin: gen_head_tail_free + assign head_tail_free[i] = head_tail_q[i].free; + end + lzc #( + .WIDTH (HT_CAPACITY), + .MODE (0) // Start at index 0. + ) i_ht_free_lzc ( + .in_i (head_tail_free), + .cnt_o (head_tail_free_idx), + .empty_o () + ); + + // Find the first free index in the linked data table. + for (genvar i = 0; i < CAPACITY; i++) begin: gen_linked_data_free + assign linked_data_free[i] = linked_data_q[i].free; + end + lzc #( + .WIDTH (CAPACITY), + .MODE (0) // Start at index 0. + ) i_ld_free_lzc ( + .in_i (linked_data_free), + .cnt_o (linked_data_free_idx), + .empty_o () + ); + + // The queue is full if and only if there are no free items in the linked data structure. + assign full = !(|linked_data_free); + + assign inp_gnt_o = ~full; + always_comb begin + match_id = 'x; + match_id_valid = 1'b0; + head_tail_d = head_tail_q; + linked_data_d = linked_data_q; + oup_gnt_o = 1'b0; + oup_data_o = data_t'('x); + oup_data_valid_o = 1'b0; + if (inp_req_i && !full) begin + match_id = inp_id_i; + match_id_valid = 1'b1; + // If the ID does not yet exist in the queue, add a new ID entry. + if (no_id_match) begin + head_tail_d[head_tail_free_idx] = head_tail_t'{ + id: inp_id_i, + head: linked_data_free_idx, + tail: linked_data_free_idx, + free: 1'b0 + }; + // Otherwise append it to the existing ID subqueue. + end else begin + linked_data_d[head_tail_q[match_idx].tail].next = linked_data_free_idx; + head_tail_d[match_idx].tail = linked_data_free_idx; + end + linked_data_d[linked_data_free_idx] = linked_data_t'{ + data: inp_data_i, + next: 'x, + free: 1'b0 + }; + end else if (oup_req_i) begin + match_id = oup_id_i; + match_id_valid = 1'b1; + if (!no_id_match) begin + oup_data_o = data_t'(linked_data_q[head_tail_q[match_idx].head].data); + oup_data_valid_o = 1'b1; + if (oup_pop_i) begin + // Set free bit of linked data entry, all other bits are don't care. + linked_data_d[head_tail_q[match_idx].head] = 'x; + linked_data_d[head_tail_q[match_idx].head][0] = 1'b1; + if (head_tail_q[match_idx].head == head_tail_q[match_idx].tail) begin + head_tail_d[match_idx] = head_tail_t'{free: 1'b1, default: 'x}; + end else begin + head_tail_d[match_idx].head = linked_data_q[head_tail_q[match_idx].head].next; + end + end + end + // Always grant the output request. If there was no match, the default, invalid entry + // will be returned. + oup_gnt_o = 1'b1; + end + end + + // Exists Lookup + for (genvar i = 0; i < CAPACITY; i++) begin: gen_lookup + mask_t exists_match_bits; + for (genvar j = 0; j < $bits(data_t); j++) begin: gen_mask + always_comb begin + if (linked_data_q[i].free) begin + exists_match_bits[j] = 1'b0; + end else begin + if (!exists_mask_i[j]) begin + exists_match_bits[j] = 1'b1; + end else begin + exists_match_bits[j] = (linked_data_q[i].data[j] == exists_data_i[j]); + end + end + end + end + assign exists_match[i] = (&exists_match_bits); + end + always_comb begin + exists_gnt_o = 1'b0; + exists_o = 'x; + if (exists_req_i) begin + exists_gnt_o = 1'b1; + exists_o = (|exists_match); + end + end + + // Registers + for (genvar i = 0; i < HT_CAPACITY; i++) begin: gen_ht_ffs + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + head_tail_q[i] <= head_tail_t'{free: 1'b1, default: 'x}; + end else begin + head_tail_q[i] <= head_tail_d[i]; + end + end + end + for (genvar i = 0; i < CAPACITY; i++) begin: gen_data_ffs + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + // Set free bit of linked data entries, all other bits are don't care. + linked_data_q[i] <= 'x; + linked_data_q[i][0] <= 1'b1; + end else begin + linked_data_q[i] <= linked_data_d[i]; + end + end + end + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (ID_WIDTH >= 1) + else $fatal("The ID must at least be one bit wide!"); + assert (CAPACITY >= 1) + else $fatal("The queue must have capacity of at least one entry!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/common_cells/src/lzc.sv b/hw/deps/common_cells/src/lzc.sv new file mode 100644 index 0000000..90657f5 --- /dev/null +++ b/hw/deps/common_cells/src/lzc.sv @@ -0,0 +1,109 @@ +// Copyright (c) 2018 - 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +/// A trailing zero counter / leading zero counter. +/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB) +/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB) +/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains +/// the maximum number of zeros - 1. For example: +/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0) +/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0) +/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0) +/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only). +/// This speeds up simulation significantly. +module lzc #( + /// The width of the input vector. + parameter int unsigned WIDTH = 2, + /// Mode selection: 0 -> trailing zero, 1 -> leading zero + parameter bit MODE = 1'b0, + /// Dependent parameter. Do **not** change! + /// + /// Width of the output signal with the zero count. + parameter int unsigned CNT_WIDTH = cf_math_pkg::idx_width(WIDTH) +) ( + /// Input vector to be counted. + input logic [WIDTH-1:0] in_i, + /// Count of the leading / trailing zeros. + output logic [CNT_WIDTH-1:0] cnt_o, + /// Counter is empty: Asserted if all bits in in_i are zero. + output logic empty_o +); + + if (WIDTH == 1) begin: gen_degenerate_lzc + + assign cnt_o[0] = !in_i[0]; + assign empty_o = !in_i[0]; + + end else begin: gen_lzc + + localparam int unsigned NUM_LEVELS = $clog2(WIDTH); + + // pragma translate_off + initial begin + assert(WIDTH > 0) else $fatal(1, "input must be at least one bit wide"); + end + // pragma translate_on + + logic [WIDTH-1:0][NUM_LEVELS-1:0] index_lut; + logic [2**NUM_LEVELS-1:0] sel_nodes /* verilator split_var */; + logic [2**NUM_LEVELS-1:0][NUM_LEVELS-1:0] index_nodes /* verilator split_var */; + + logic [WIDTH-1:0] in_tmp; + + // reverse vector if required + always_comb begin : flip_vector + for (int unsigned i = 0; i < WIDTH; i++) begin + in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i]; + end + end + + for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut + assign index_lut[j] = (NUM_LEVELS)'(unsigned'(j)); + end + + for (genvar level = 0; unsigned'(level) < NUM_LEVELS; level++) begin : g_levels + if (unsigned'(level) == NUM_LEVELS-1) begin : g_last_level + for (genvar k = 0; k < 2**level; k++) begin : g_level + // if two successive indices are still in the vector... + if (unsigned'(k) * 2 < WIDTH-1) begin + assign sel_nodes[2**level-1+k] = in_tmp[k*2] | in_tmp[k*2+1]; + assign index_nodes[2**level-1+k] = (in_tmp[k*2] == 1'b1) ? index_lut[k*2] : + index_lut[k*2+1]; + end + // if only the first index is still in the vector... + if (unsigned'(k) * 2 == WIDTH-1) begin + assign sel_nodes[2**level-1+k] = in_tmp[k*2]; + assign index_nodes[2**level-1+k] = index_lut[k*2]; + end + // if index is out of range + if (unsigned'(k) * 2 > WIDTH-1) begin + assign sel_nodes[2**level-1+k] = 1'b0; + assign index_nodes[2**level-1+k] = '0; + end + end + end else begin + for (genvar l = 0; l < 2**level; l++) begin : g_level + assign sel_nodes[2**level-1+l] = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1]; + assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ? index_nodes[2**(level+1)-1+l*2] : + index_nodes[2**(level+1)-1+l*2+1]; + end + end + end + + assign cnt_o = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : {($clog2(WIDTH)){1'b0}}; + assign empty_o = NUM_LEVELS > unsigned'(0) ? ~sel_nodes[0] : ~(|in_i); + + end : gen_lzc + +endmodule : lzc diff --git a/hw/deps/common_cells/src/onehot_to_bin.sv b/hw/deps/common_cells/src/onehot_to_bin.sv new file mode 100644 index 0000000..272add4 --- /dev/null +++ b/hw/deps/common_cells/src/onehot_to_bin.sv @@ -0,0 +1,38 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Franceco Conti + +module onehot_to_bin #( + parameter int unsigned ONEHOT_WIDTH = 16, + // Do Not Change + parameter int unsigned BIN_WIDTH = ONEHOT_WIDTH == 1 ? 1 : $clog2(ONEHOT_WIDTH) +) ( + input logic [ONEHOT_WIDTH-1:0] onehot, + output logic [BIN_WIDTH-1:0] bin +); + + for (genvar j = 0; j < BIN_WIDTH; j++) begin : jl + logic [ONEHOT_WIDTH-1:0] tmp_mask; + for (genvar i = 0; i < ONEHOT_WIDTH; i++) begin : il + logic [BIN_WIDTH-1:0] tmp_i; + assign tmp_i = i; + assign tmp_mask[i] = tmp_i[j]; + end + assign bin[j] = |(tmp_mask & onehot); + end + +// pragma translate_off +`ifndef VERILATOR + //assert final ($onehot0(onehot)) else + // $fatal(1, "[onehot_to_bin] More than two bit set in the one-hot signal"); +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/common_cells/src/rr_arb_tree.sv b/hw/deps/common_cells/src/rr_arb_tree.sv new file mode 100644 index 0000000..7bdc7ae --- /dev/null +++ b/hw/deps/common_cells/src/rr_arb_tree.sv @@ -0,0 +1,341 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Wolfgang Roenninger , ETH Zurich +// Date: 02.04.2019 +// Description: logarithmic arbitration tree with round robin arbitration scheme. + +/// The rr_arb_tree employs non-starving round robin-arbitration - i.e., the priorities +/// rotate each cycle. +/// +/// ## Fair vs. unfair Arbitration +/// +/// This refers to fair throughput distribution when not all inputs have active requests. +/// This module has an internal state `rr_q` which defines the highest priority input. (When +/// `ExtPrio` is `1'b1` this state is provided from the outside.) The arbitration tree will +/// choose the input with the same index as currently defined by the state if it has an active +/// request. Otherwise a *random* other active input is selected. The parameter `FairArb` is used +/// to distinguish between two methods of calculating the next state. +/// * `1'b0`: The next state is calculated by advancing the current state by one. This leads to the +/// state being calculated without the context of the active request. Leading to an +/// unfair throughput distribution if not all inputs have active requests. +/// * `1'b1`: The next state jumps to the next unserved request with higher index. +/// This is achieved by using two trailing-zero-counters (`lzc`). The upper has the masked +/// `req_i` signal with all indices which will have a higher priority in the next state. +/// The trailing zero count defines the input index with the next highest priority after +/// the current one is served. When the upper is empty the lower `lzc` provides the +/// wrapped index if there are outstanding requests with lower or same priority. +/// The implication of throughput fairness on the module timing are: +/// * The trailing zero counter (`lzc`) has a loglog relation of input to output timing. This means +/// that in this module the input to register path scales with Log(Log(`NumIn`)). +/// * The `rr_arb_tree` data multiplexing scales with Log(`NumIn`). This means that the input to output +/// timing path of this module also scales scales with Log(`NumIn`). +/// This implies that in this module the input to output path is always longer than the input to +/// register path. As the output data usually also terminates in a register the parameter `FairArb` +/// only has implications on the area. When it is `1'b0` a static plus one adder is instantiated. +/// If it is `1'b1` two `lzc`, a masking logic stage and a two input multiplexer are instantiated. +/// However these are small in respect of the data multiplexers needed, as the width of the `req_i` +/// signal is usually less as than `DataWidth`. +module rr_arb_tree #( + /// Number of inputs to be arbitrated. + parameter int unsigned NumIn = 64, + /// Data width of the payload in bits. Not needed if `DataType` is overwritten. + parameter int unsigned DataWidth = 32, + /// Data type of the payload, can be overwritten with custom type. Only use of `DataWidth`. + parameter type DataType = logic [DataWidth-1:0], + /// The `ExtPrio` option allows to override the internal round robin counter via the + /// `rr_i` signal. This can be useful in case multiple arbiters need to have + /// rotating priorities that are operating in lock-step. If static priority arbitration + /// is needed, just connect `rr_i` to '0. + /// + /// Set to 1'b1 to enable. + parameter bit ExtPrio = 1'b0, + /// If `AxiVldRdy` is set, the req/gnt signals are compliant with the AXI style vld/rdy + /// handshake. Namely, upstream vld (req) must not depend on rdy (gnt), as it can be deasserted + /// again even though vld is asserted. Enabling `AxiVldRdy` leads to a reduction of arbiter + /// delay and area. + /// + /// Set to `1'b1` to treat req/gnt as vld/rdy. + parameter bit AxiVldRdy = 1'b0, + /// The `LockIn` option prevents the arbiter from changing the arbitration + /// decision when the arbiter is disabled. I.e., the index of the first request + /// that wins the arbitration will be locked in case the destination is not + /// able to grant the request in the same cycle. + /// + /// Set to `1'b1` to enable. + parameter bit LockIn = 1'b0, + /// When set, ensures that throughput gets distributed evenly between all inputs. + /// + /// Set to `1'b0` to disable. + parameter bit FairArb = 1'b1, + /// Dependent parameter, do **not** overwrite. + /// Width of the arbitration priority signal and the arbitrated index. + parameter int unsigned IdxWidth = (NumIn > 32'd1) ? unsigned'($clog2(NumIn)) : 32'd1, + /// Dependent parameter, do **not** overwrite. + /// Type for defining the arbitration priority and arbitrated index signal. + parameter type idx_t = logic [IdxWidth-1:0] +) ( + /// Clock, positive edge triggered. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Clears the arbiter state. Only used if `ExtPrio` is `1'b0` or `LockIn` is `1'b1`. + input logic flush_i, + /// External round-robin priority. Only used if `ExtPrio` is `1'b1.` + input idx_t rr_i, + /// Input requests arbitration. + input logic [NumIn-1:0] req_i, + /* verilator lint_off UNOPTFLAT */ + /// Input request is granted. + output logic [NumIn-1:0] gnt_o, + /* verilator lint_on UNOPTFLAT */ + /// Input data for arbitration. + input DataType [NumIn-1:0] data_i, + /// Output request is valid. + output logic req_o, + /// Output request is granted. + input logic gnt_i, + /// Output data. + output DataType data_o, + /// Index from which input the data came from. + output idx_t idx_o +); + + // pragma translate_off + `ifndef VERILATOR + // Default SVA reset + default disable iff (!rst_ni || flush_i); + `endif + // pragma translate_on + + // just pass through in this corner case + if (NumIn == unsigned'(1)) begin + assign req_o = req_i[0]; + assign gnt_o[0] = gnt_i; + assign data_o = data_i[0]; + assign idx_o = '0; + // non-degenerate cases + end else begin + localparam int unsigned NumLevels = unsigned'($clog2(NumIn)); + + /* verilator lint_off UNOPTFLAT */ + idx_t [2**NumLevels-2:0] index_nodes; // used to propagate the indices + DataType [2**NumLevels-2:0] data_nodes; // used to propagate the data + logic [2**NumLevels-2:0] gnt_nodes; // used to propagate the grant to masters + logic [2**NumLevels-2:0] req_nodes; // used to propagate the requests to slave + /* lint_off */ + idx_t rr_q; + logic [NumIn-1:0] req_d; + + // the final arbitration decision can be taken from the root of the tree + assign req_o = req_nodes[0]; + assign data_o = data_nodes[0]; + assign idx_o = index_nodes[0]; + + if (ExtPrio) begin : gen_ext_rr + assign rr_q = rr_i; + assign req_d = req_i; + end else begin : gen_int_rr + idx_t rr_d; + + // lock arbiter decision in case we got at least one req and no acknowledge + if (LockIn) begin : gen_lock + logic lock_d, lock_q; + logic [NumIn-1:0] req_q; + + assign lock_d = req_o & ~gnt_i; + assign req_d = (lock_q) ? req_q : req_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + if (!rst_ni) begin + lock_q <= '0; + end else begin + if (flush_i) begin + lock_q <= '0; + end else begin + lock_q <= lock_d; + end + end + end + + // pragma translate_off + `ifndef VERILATOR + lock: assert property( + @(posedge clk_i) LockIn |-> req_o && !gnt_i |=> idx_o == $past(idx_o)) else + $fatal (1, "Lock implies same arbiter decision in next cycle if output is not \ + ready."); + + logic [NumIn-1:0] req_tmp; + assign req_tmp = req_q & req_i; + lock_req: assume property( + @(posedge clk_i) LockIn |-> lock_d |=> req_tmp == req_q) else + $fatal (1, "It is disallowed to deassert unserved request signals when LockIn is \ + enabled."); + `endif + // pragma translate_on + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_req_regs + if (!rst_ni) begin + req_q <= '0; + end else begin + if (flush_i) begin + req_q <= '0; + end else begin + req_q <= req_d; + end + end + end + end else begin : gen_no_lock + assign req_d = req_i; + end + + if (FairArb) begin : gen_fair_arb + logic [NumIn-1:0] upper_mask, lower_mask; + idx_t upper_idx, lower_idx, next_idx; + logic upper_empty, lower_empty; + + for (genvar i = 0; i < NumIn; i++) begin : gen_mask + assign upper_mask[i] = (i > rr_q) ? req_d[i] : 1'b0; + assign lower_mask[i] = (i <= rr_q) ? req_d[i] : 1'b0; + end + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_upper ( + .in_i ( upper_mask ), + .cnt_o ( upper_idx ), + .empty_o ( upper_empty ) + ); + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_lower ( + .in_i ( lower_mask ), + .cnt_o ( lower_idx ), + .empty_o ( /*unused*/ ) + ); + + assign next_idx = upper_empty ? lower_idx : upper_idx; + assign rr_d = (gnt_i && req_o) ? next_idx : rr_q; + + end else begin : gen_unfair_arb + assign rr_d = (gnt_i && req_o) ? ((rr_q == idx_t'(NumIn-1)) ? '0 : rr_q + 1'b1) : rr_q; + end + + // this holds the highest priority + always_ff @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + if (!rst_ni) begin + rr_q <= '0; + end else begin + if (flush_i) begin + rr_q <= '0; + end else begin + rr_q <= rr_d; + end + end + end + end + + assign gnt_nodes[0] = gnt_i; + + // arbiter tree + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : gen_levels + for (genvar l = 0; l < 2**level; l++) begin : gen_level + // local select signal + logic sel; + // index calcs + localparam int unsigned idx0 = 2**level-1+l;// current node + localparam int unsigned idx1 = 2**(level+1)-1+l*2; + ////////////////////////////////////////////////////////////// + // uppermost level where data is fed in from the inputs + if (unsigned'(level) == NumLevels-1) begin : gen_first_level + // if two successive indices are still in the vector... + if (unsigned'(l) * 2 < NumIn-1) begin + assign req_nodes[idx0] = req_d[l*2] | req_d[l*2+1]; + + // arbitration: round robin + assign sel = ~req_d[l*2] | req_d[l*2+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[idx0] = idx_t'(sel); + assign data_nodes[idx0] = (sel) ? data_i[l*2+1] : data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[idx0] & (AxiVldRdy | req_d[l*2]) & ~sel; + assign gnt_o[l*2+1] = gnt_nodes[idx0] & (AxiVldRdy | req_d[l*2+1]) & sel; + end + // if only the first index is still in the vector... + if (unsigned'(l) * 2 == NumIn-1) begin + assign req_nodes[idx0] = req_d[l*2]; + assign index_nodes[idx0] = '0;// always zero in this case + assign data_nodes[idx0] = data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[idx0] & (AxiVldRdy | req_d[l*2]); + end + // if index is out of range, fill up with zeros (will get pruned) + if (unsigned'(l) * 2 > NumIn-1) begin + assign req_nodes[idx0] = 1'b0; + assign index_nodes[idx0] = DataType'('0); + assign data_nodes[idx0] = DataType'('0); + end + ////////////////////////////////////////////////////////////// + // general case for other levels within the tree + end else begin : gen_other_levels + assign req_nodes[idx0] = req_nodes[idx1] | req_nodes[idx1+1]; + + // arbitration: round robin + assign sel = ~req_nodes[idx1] | req_nodes[idx1+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[idx0] = (sel) ? idx_t'({1'b1, index_nodes[idx1+1][NumLevels-unsigned'(level)-2:0]}) : + idx_t'({1'b0, index_nodes[idx1][NumLevels-unsigned'(level)-2:0]}); + assign data_nodes[idx0] = (sel) ? data_nodes[idx1+1] : data_nodes[idx1]; + assign gnt_nodes[idx1] = gnt_nodes[idx0] & ~sel; + assign gnt_nodes[idx1+1] = gnt_nodes[idx0] & sel; + end + ////////////////////////////////////////////////////////////// + end + end + + // pragma translate_off + `ifndef VERILATOR + initial begin : p_assert + assert(NumIn) + else $fatal(1, "Input must be at least one element wide."); + assert(!(LockIn && ExtPrio)) + else $fatal(1,"Cannot use LockIn feature together with external ExtPrio."); + end + + hot_one : assert property( + @(posedge clk_i) $onehot0(gnt_o)) + else $fatal (1, "Grant signal must be hot1 or zero."); + + gnt0 : assert property( + @(posedge clk_i) |gnt_o |-> gnt_i) + else $fatal (1, "Grant out implies grant in."); + + gnt1 : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> |gnt_o) + else $fatal (1, "Req out and grant in implies grant out."); + + gnt_idx : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> gnt_o[idx_o]) + else $fatal (1, "Idx_o / gnt_o do not match."); + + req0 : assert property( + @(posedge clk_i) |req_i |-> req_o) + else $fatal (1, "Req in implies req out."); + + req1 : assert property( + @(posedge clk_i) req_o |-> |req_i) + else $fatal (1, "Req out implies req in."); + `endif + // pragma translate_on + end + +endmodule : rr_arb_tree diff --git a/hw/deps/common_cells/src/rstgen.sv b/hw/deps/common_cells/src/rstgen.sv new file mode 100644 index 0000000..a7dccc6 --- /dev/null +++ b/hw/deps/common_cells/src/rstgen.sv @@ -0,0 +1,30 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module rstgen ( + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + output logic rst_no, + output logic init_no +); + + rstgen_bypass i_rstgen_bypass ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .rst_test_mode_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .rst_no ( rst_no ), + .init_no ( init_no ) + ); + +endmodule diff --git a/hw/deps/common_cells/src/rstgen_bypass.sv b/hw/deps/common_cells/src/rstgen_bypass.sv new file mode 100644 index 0000000..64102d8 --- /dev/null +++ b/hw/deps/common_cells/src/rstgen_bypass.sv @@ -0,0 +1,57 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Florian Zaruba +// Description: This module is a reset synchronizer with a dedicated reset bypass pin for testmode reset. +// Pro Tip: The wise Dr. Schaffner recommends at least 4 registers! + +module rstgen_bypass #( + parameter NumRegs = 4 +) ( + input logic clk_i, + input logic rst_ni, + input logic rst_test_mode_ni, + input logic test_mode_i, + output logic rst_no, + output logic init_no +); + + // internal reset + logic rst_n; + + logic [NumRegs-1:0] synch_regs_q; + // bypass mode + always_comb begin + if (test_mode_i == 1'b0) begin + rst_n = rst_ni; + rst_no = synch_regs_q[NumRegs-1]; + init_no = synch_regs_q[NumRegs-1]; + end else begin + rst_n = rst_test_mode_ni; + rst_no = rst_test_mode_ni; + init_no = 1'b1; + end + end + + always @(posedge clk_i or negedge rst_n) begin + if (~rst_n) begin + synch_regs_q <= 0; + end else begin + synch_regs_q <= {synch_regs_q[NumRegs-2:0], 1'b1}; + end + end + // pragma translate_off + `ifndef VERILATOR + initial begin : p_assertions + if (NumRegs < 1) $fatal(1, "At least one register is required."); + end + `endif + // pragma translate_on +endmodule diff --git a/hw/deps/common_cells/src/spill_register.sv b/hw/deps/common_cells/src/spill_register.sv new file mode 100644 index 0000000..d6f8d30 --- /dev/null +++ b/hw/deps/common_cells/src/spill_register.sv @@ -0,0 +1,95 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Fabian Schuiki + + +/// A register with handshakes that completely cuts any combinational paths +/// between the input and output. +module spill_register #( + parameter type T = logic, + parameter bit Bypass = 1'b0 // make this spill register transparent +) ( + input logic clk_i , + input logic rst_ni , + input logic valid_i , + output logic ready_o , + input T data_i , + output logic valid_o , + input logic ready_i , + output T data_o +); + + if (Bypass) begin : gen_bypass + assign valid_o = valid_i; + assign ready_o = ready_i; + assign data_o = data_i; + end else begin : gen_spill_reg + // The A register. + T a_data_q; + logic a_full_q; + logic a_fill, a_drain; + logic a_en, a_en_data; + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_data + if (!rst_ni) + a_data_q <= '0; + else if (a_fill) + a_data_q <= data_i; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_full + if (!rst_ni) + a_full_q <= 0; + else if (a_fill || a_drain) + a_full_q <= a_fill; + end + + // The B register. + T b_data_q; + logic b_full_q; + logic b_fill, b_drain; + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_data + if (!rst_ni) + b_data_q <= '0; + else if (b_fill) + b_data_q <= a_data_q; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_full + if (!rst_ni) + b_full_q <= 0; + else if (b_fill || b_drain) + b_full_q <= b_fill; + end + + // Fill the A register when the A or B register is empty. Drain the A register + // whenever it is full and being filled. + assign a_fill = valid_i && ready_o; + assign a_drain = a_full_q && !b_full_q; + + // Fill the B register whenever the A register is drained, but the downstream + // circuit is not ready. Drain the B register whenever it is full and the + // downstream circuit is ready. + assign b_fill = a_drain && !ready_i; + assign b_drain = b_full_q && ready_i; + + // We can accept input as long as register B is not full. + assign ready_o = !a_full_q || !b_full_q; + + // The unit provides output as long as one of the registers is filled. + assign valid_o = a_full_q | b_full_q; + + // We empty the spill register before the slice register. + assign data_o = b_full_q ? b_data_q : a_data_q; + end +endmodule diff --git a/hw/deps/common_cells/src/stream_arbiter.sv b/hw/deps/common_cells/src/stream_arbiter.sv new file mode 100644 index 0000000..c8ca2a8 --- /dev/null +++ b/hw/deps/common_cells/src/stream_arbiter.sv @@ -0,0 +1,49 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready +// handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is +// asserted, `oup_data_o` remains invariant until the output handshake has occurred. The +// arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details. + +module stream_arbiter #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. + parameter ARBITER = "rr" // "rr" or "prio" +) ( + input logic clk_i, + input logic rst_ni, + + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + stream_arbiter_flushable #( + .DATA_T (DATA_T), + .N_INP (N_INP), + .ARBITER (ARBITER) + ) i_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .inp_data_i (inp_data_i), + .inp_valid_i (inp_valid_i), + .inp_ready_o (inp_ready_o), + .oup_data_o (oup_data_o), + .oup_valid_o (oup_valid_o), + .oup_ready_i (oup_ready_i) + ); + +endmodule diff --git a/hw/deps/common_cells/src/stream_arbiter_flushable.sv b/hw/deps/common_cells/src/stream_arbiter_flushable.sv new file mode 100644 index 0000000..32946e6 --- /dev/null +++ b/hw/deps/common_cells/src/stream_arbiter_flushable.sv @@ -0,0 +1,82 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready +// handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is +// asserted, `oup_data_o` remains invariant until the output handshake has occurred. The +// arbitration scheme is fair round-robin tree, see `rr_arb_tree` for details. + +module stream_arbiter_flushable #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. + parameter ARBITER = "rr" // "rr" or "prio" +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + if (ARBITER == "rr") begin : gen_rr_arb + rr_arb_tree #( + .NumIn (N_INP), + .DataType (DATA_T), + .ExtPrio (1'b0), + .AxiVldRdy (1'b1), + .LockIn (1'b1) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ('0), + .req_i (inp_valid_i), + .gnt_o (inp_ready_o), + .data_i (inp_data_i), + .gnt_i (oup_ready_i), + .req_o (oup_valid_o), + .data_o (oup_data_o), + .idx_o () + ); + + end else if (ARBITER == "prio") begin : gen_prio_arb + rr_arb_tree #( + .NumIn (N_INP), + .DataType (DATA_T), + .ExtPrio (1'b1), + .AxiVldRdy (1'b1), + .LockIn (1'b1) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ('0), + .req_i (inp_valid_i), + .gnt_o (inp_ready_o), + .data_i (inp_data_i), + .gnt_i (oup_ready_i), + .req_o (oup_valid_o), + .data_o (oup_data_o), + .idx_o () + ); + + end else begin : gen_arb_error + // pragma translate_off + $fatal(1, "Invalid value for parameter 'ARBITER'!"); + // pragma translate_on + end + +endmodule diff --git a/hw/deps/common_cells/src/stream_demux.sv b/hw/deps/common_cells/src/stream_demux.sv new file mode 100644 index 0000000..69ad309 --- /dev/null +++ b/hw/deps/common_cells/src/stream_demux.sv @@ -0,0 +1,36 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Connects the input stream (valid-ready) handshake to one of `N_OUP` output stream handshakes. +/// +/// This module has no data ports because stream data does not need to be demultiplexed: the data of +/// the input stream can just be applied at all output streams. +module stream_demux #( + /// Number of connected outputs. + parameter int unsigned N_OUP = 32'd1, + /// Dependent parameters, DO NOT OVERRIDE! + parameter int unsigned LOG_N_OUP = (N_OUP > 32'd1) ? unsigned'($clog2(N_OUP)) : 1'b1 +) ( + input logic inp_valid_i, + output logic inp_ready_o, + + input logic [LOG_N_OUP-1:0] oup_sel_i, + + output logic [N_OUP-1:0] oup_valid_o, + input logic [N_OUP-1:0] oup_ready_i +); + + always_comb begin + oup_valid_o = '0; + oup_valid_o[oup_sel_i] = inp_valid_i; + end + assign inp_ready_o = oup_ready_i[oup_sel_i]; + +endmodule diff --git a/hw/deps/common_cells/src/stream_fifo.sv b/hw/deps/common_cells/src/stream_fifo.sv new file mode 100644 index 0000000..e7c60e5 --- /dev/null +++ b/hw/deps/common_cells/src/stream_fifo.sv @@ -0,0 +1,66 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Georg Rutishauser + +module stream_fifo #( + /// FIFO is in fall-through mode + parameter bit FALL_THROUGH = 1'b0, + /// Default data width if the fifo is of type logic + parameter int unsigned DATA_WIDTH = 32, + /// Depth can be arbitrary from 0 to 2**32 + parameter int unsigned DEPTH = 8, + parameter type T = logic [DATA_WIDTH-1:0], + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the fifo + input logic testmode_i, // test_mode to bypass clock gating + output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer + // input interface + input T data_i, // data to push into the fifo + input logic valid_i, // input data valid + output logic ready_o, // fifo is not full + // output interface + output T data_o, // output data + output logic valid_o, // fifo is not empty + input logic ready_i // pop head from fifo +); + + logic push, pop; + logic empty, full; + + assign push = valid_i & ~full; + assign pop = ready_i & ~empty; + assign ready_o = ~full; + assign valid_o = ~empty; + + fifo_v3 #( + .FALL_THROUGH (FALL_THROUGH), + .DATA_WIDTH (DATA_WIDTH), + .DEPTH (DEPTH), + .dtype(T) + ) fifo_i ( + .clk_i, + .rst_ni, + .flush_i, + .testmode_i, + .full_o (full), + .empty_o (empty), + .usage_o, + .data_i, + .push_i (push), + .data_o, + .pop_i (pop) + ); + +endmodule diff --git a/hw/deps/common_cells/src/stream_filter.sv b/hw/deps/common_cells/src/stream_filter.sv new file mode 100644 index 0000000..52a5835 --- /dev/null +++ b/hw/deps/common_cells/src/stream_filter.sv @@ -0,0 +1,26 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream filter: If `drop_i` is `1`, signal `ready` to the upstream regardless of the downstream, +// and do not propagate `valid` downstream. Otherwise, connect upstream to downstream. +module stream_filter ( + input logic valid_i, + output logic ready_o, + + input logic drop_i, + + output logic valid_o, + input logic ready_i +); + + assign valid_o = drop_i ? 1'b0 : valid_i; + assign ready_o = drop_i ? 1'b1 : ready_i; + +endmodule diff --git a/hw/deps/common_cells/src/stream_fork.sv b/hw/deps/common_cells/src/stream_fork.sv new file mode 100644 index 0000000..aebb0f5 --- /dev/null +++ b/hw/deps/common_cells/src/stream_fork.sv @@ -0,0 +1,133 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream fork: Connects the input stream (ready-valid) handshake to *all* of `N_OUP` output stream +// handshakes. For each input stream handshake, every output stream handshakes exactly once. The +// input stream only handshakes when all output streams have handshaked, but the output streams do +// not have to handshake simultaneously. +// +// This module has no data ports because stream data does not need to be forked: the data of the +// input stream can just be applied at all output streams. + +module stream_fork #( + parameter int unsigned N_OUP = 0 // Synopsys DC requires a default value for parameters. +) ( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + output logic ready_o, + output logic [N_OUP-1:0] valid_o, + input logic [N_OUP-1:0] ready_i +); + + typedef enum logic {READY, WAIT} state_t; + + logic [N_OUP-1:0] oup_ready, + all_ones; + + state_t inp_state_d, inp_state_q; + + // Input control FSM + always_comb begin + // ready_o = 1'b0; + inp_state_d = inp_state_q; + + unique case (inp_state_q) + READY: begin + if (valid_i) begin + if (valid_o == all_ones && ready_i == all_ones) begin + // If handshake on all outputs, handshake on input. + ready_o = 1'b1; + end else begin + ready_o = 1'b0; + // Otherwise, wait for inputs that did not handshake yet. + inp_state_d = WAIT; + end + end else begin + ready_o = 1'b0; + end + end + WAIT: begin + if (valid_i && oup_ready == all_ones) begin + ready_o = 1'b1; + inp_state_d = READY; + end else begin + ready_o = 1'b0; + end + end + default: begin + inp_state_d = READY; + ready_o = 1'b0; + end + endcase + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + inp_state_q <= READY; + end else begin + inp_state_q <= inp_state_d; + end + end + + // Output control FSM + for (genvar i = 0; i < N_OUP; i++) begin: gen_oup_state + state_t oup_state_d, oup_state_q; + + always_comb begin + oup_ready[i] = 1'b1; + valid_o[i] = 1'b0; + oup_state_d = oup_state_q; + + unique case (oup_state_q) + READY: begin + if (valid_i) begin + valid_o[i] = 1'b1; + if (ready_i[i]) begin // Output handshake + if (!ready_o) begin // No input handshake yet + oup_state_d = WAIT; + end + end else begin // No output handshake + oup_ready[i] = 1'b0; + end + end + end + WAIT: begin + if (valid_i && ready_o) begin // Input handshake + oup_state_d = READY; + end + end + default: begin + oup_state_d = READY; + end + endcase + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + oup_state_q <= READY; + end else begin + oup_state_q <= oup_state_d; + end + end + end + + assign all_ones = '1; // Synthesis fix for Vivado, which does not correctly compute the width + // of the '1 literal when assigned to a port of parametrized width. + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (N_OUP >= 1) else $fatal("Number of outputs must be at least 1!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/common_cells/src/stream_fork_dynamic.sv b/hw/deps/common_cells/src/stream_fork_dynamic.sv new file mode 100644 index 0000000..e4720f7 --- /dev/null +++ b/hw/deps/common_cells/src/stream_fork_dynamic.sv @@ -0,0 +1,95 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Authors: +// - Andreas Kurth + +/// Dynamic stream fork: Connects the input stream (ready-valid) handshake to a combination of output +/// stream handshake. The combination is determined dynamically through another stream, which +/// provides a bitmask for the fork. For each input stream handshake, every output stream handshakes +/// exactly once. The input stream only handshakes when all output streams have handshaked, but the +/// output streams do not have to handshake simultaneously. +/// +/// This module has no data ports because stream data does not need to be forked: the data of the +/// input stream can just be applied at all output streams. +module stream_fork_dynamic #( + /// Number of output streams + parameter int unsigned N_OUP = 32'd0 // Synopsys DC requires a default value for parameters. +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Input stream valid handshake, + input logic valid_i, + /// Input stream ready handshake + output logic ready_o, + /// Selection mask for the output handshake + input logic [N_OUP-1:0] sel_i, + /// Selection mask valid + input logic sel_valid_i, + /// Selection mask ready + output logic sel_ready_o, + /// Output streams valid handshakes + output logic [N_OUP-1:0] valid_o, + /// Output streams ready handshakes + input logic [N_OUP-1:0] ready_i +); + + logic int_inp_valid, int_inp_ready; + logic [N_OUP-1:0] int_oup_valid, int_oup_ready; + + // Output handshaking + for (genvar i = 0; i < N_OUP; i++) begin : gen_oups + always_comb begin + valid_o[i] = 1'b0; + int_oup_ready[i] = 1'b0; + if (sel_valid_i) begin + if (sel_i[i]) begin + valid_o[i] = int_oup_valid[i]; + int_oup_ready[i] = ready_i[i]; + end else begin + int_oup_ready[i] = 1'b1; + end + end + end + end + + // Input handshaking + always_comb begin + int_inp_valid = 1'b0; + ready_o = 1'b0; + sel_ready_o = 1'b0; + if (sel_valid_i) begin + int_inp_valid = valid_i; + ready_o = int_inp_ready; + sel_ready_o = int_inp_ready; + end + end + + stream_fork #( + .N_OUP ( N_OUP ) + ) i_fork ( + .clk_i, + .rst_ni, + .valid_i ( int_inp_valid ), + .ready_o ( int_inp_ready ), + .valid_o ( int_oup_valid ), + .ready_i ( int_oup_ready ) + ); + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (N_OUP >= 1) else $fatal(1, "N_OUP must be at least 1!"); + end +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/common_cells/src/stream_join.sv b/hw/deps/common_cells/src/stream_join.sv new file mode 100644 index 0000000..2f210bc --- /dev/null +++ b/hw/deps/common_cells/src/stream_join.sv @@ -0,0 +1,43 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Authors: +// - Andreas Kurth + +/// Stream join: Joins a parametrizable number of input streams (i.e., valid-ready handshaking with +/// dependency rules as in AXI4) to a single output stream. The output handshake happens only once +/// all inputs are valid. The data channel flows outside of this module. +module stream_join #( + /// Number of input streams + parameter int unsigned N_INP = 32'd0 // Synopsys DC requires a default value for parameters. +) ( + /// Input streams valid handshakes + input logic [N_INP-1:0] inp_valid_i, + /// Input streams ready handshakes + output logic [N_INP-1:0] inp_ready_o, + /// Output stream valid handshake + output logic oup_valid_o, + /// Output stream ready handshake + input logic oup_ready_i +); + + assign oup_valid_o = (&inp_valid_i); + for (genvar i = 0; i < N_INP; i++) begin : gen_inp_ready + assign inp_ready_o[i] = oup_valid_o & oup_ready_i; + end + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (N_INP >= 1) else $fatal(1, "N_INP must be at least 1!"); + end +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/common_cells/src/stream_mux.sv b/hw/deps/common_cells/src/stream_mux.sv new file mode 100644 index 0000000..156c572 --- /dev/null +++ b/hw/deps/common_cells/src/stream_mux.sv @@ -0,0 +1,46 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Stream multiplexer: connects the output to one of `N_INP` data streams with valid-ready +/// handshaking. + +module stream_mux #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = 0, // Synopsys DC requires a default value for value parameters. + /// Dependent parameters, DO NOT OVERRIDE! + parameter integer LOG_N_INP = $clog2(N_INP) +) ( + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + input logic [LOG_N_INP-1:0] inp_sel_i, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + always_comb begin + inp_ready_o = '0; + inp_ready_o[inp_sel_i] = oup_ready_i; + end + assign oup_data_o = inp_data_i[inp_sel_i]; + assign oup_valid_o = inp_valid_i[inp_sel_i]; + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (N_INP >= 1) else $fatal ("The number of inputs must be at least 1!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/hw/deps/common_cells/src/stream_register.sv b/hw/deps/common_cells/src/stream_register.sv new file mode 100644 index 0000000..e83228b --- /dev/null +++ b/hw/deps/common_cells/src/stream_register.sv @@ -0,0 +1,57 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Register with a simple stream-like ready/valid handshake. +/// This register does not cut combinatorial paths on all control signals; if you need a complete +/// cut, use the `spill_register`. +module stream_register #( + parameter type T = logic // Vivado requires a default value for type parameters. +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous active-low reset + input logic clr_i, // Synchronous clear + input logic testmode_i, // Test mode to bypass clock gating + // Input port + input logic valid_i, + output logic ready_o, + input T data_i, + // Output port + output logic valid_o, + input logic ready_i, + output T data_o +); + + logic fifo_empty, + fifo_full; + + fifo_v2 #( + .FALL_THROUGH (1'b0), + .DATA_WIDTH ($size(T)), + .DEPTH (1), + .dtype (T) + ) i_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (clr_i), + .testmode_i (testmode_i), + .full_o (fifo_full), + .empty_o (fifo_empty), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i (data_i), + .push_i (valid_i & ~fifo_full), + .data_o (data_o), + .pop_i (ready_i & ~fifo_empty) + ); + + assign ready_o = ~fifo_full; + assign valid_o = ~fifo_empty; + +endmodule diff --git a/hw/deps/common_cells/src/stream_to_mem.sv b/hw/deps/common_cells/src/stream_to_mem.sv new file mode 100644 index 0000000..00c3086 --- /dev/null +++ b/hw/deps/common_cells/src/stream_to_mem.sv @@ -0,0 +1,134 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Authors: +// - Andreas Kurth + +/// `stream_to_mem`: Allows to use memories with flow control (`valid`/`ready`) for requests but without flow +/// control for output data to be used in streams. +`include "common_cells/registers.svh" +module stream_to_mem #( + /// Memory request payload type, usually write enable, write data, etc. + parameter type mem_req_t = logic, + /// Memory response payload type, usually read data + parameter type mem_resp_t = logic, + /// Number of buffered responses (fall-through, thus no additional latency). This defines the + /// maximum number of outstanding requests on the memory interface. If the attached memory + /// responds in the same cycle a request is applied, this MUST be 0. If the attached memory + /// responds at least one cycle after a request, this MUST be >= 1 and should be equal to the + /// response latency of the memory to saturate bandwidth. + parameter int unsigned BufDepth = 32'd1 +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Request stream interface, payload + input mem_req_t req_i, + /// Request stream interface, payload is valid for transfer + input logic req_valid_i, + /// Request stream interface, payload can be accepted + output logic req_ready_o, + /// Response stream interface, payload + output mem_resp_t resp_o, + /// Response stream interface, payload is valid for transfer + output logic resp_valid_o, + /// Response stream interface, payload can be accepted + input logic resp_ready_i, + /// Memory request interface, payload + output mem_req_t mem_req_o, + /// Memory request interface, payload is valid for transfer + output logic mem_req_valid_o, + /// Memory request interface, payload can be accepted + input logic mem_req_ready_i, + /// Memory response interface, payload + input mem_resp_t mem_resp_i, + /// Memory response interface, payload is valid + input logic mem_resp_valid_i +); + + typedef logic [$clog2(BufDepth+1):0] cnt_t; + + cnt_t cnt_d, cnt_q; + logic buf_ready, + req_ready; + + if (BufDepth > 0) begin : gen_buf + // Count number of outstanding requests. + always_comb begin + cnt_d = cnt_q; + if (req_valid_i && req_ready_o) begin + cnt_d++; + end + if (resp_valid_o && resp_ready_i) begin + cnt_d--; + end + end + + // Can issue another request if the counter is not at its limit or a response is delivered in + // the current cycle. + assign req_ready = (cnt_q < BufDepth) | (resp_valid_o & resp_ready_i); + + // Control request and memory request interface handshakes. + assign req_ready_o = mem_req_ready_i & req_ready; + assign mem_req_valid_o = req_valid_i & req_ready; + + // Buffer responses. + stream_fifo #( + .FALL_THROUGH ( 1'b1 ), + .DEPTH ( BufDepth ), + .T ( mem_resp_t ) + ) i_resp_buf ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .data_i ( mem_resp_i ), + .valid_i ( mem_resp_valid_i ), + .ready_o ( buf_ready ), + .data_o ( resp_o ), + .valid_o ( resp_valid_o ), + .ready_i ( resp_ready_i ), + .usage_o ( /* unused */ ) + ); + + // Register + `FFARN(cnt_q, cnt_d, '0, clk_i, rst_ni) + + end else begin : gen_no_buf + // Control request, memory request, and response interface handshakes. + assign mem_req_valid_o = req_valid_i; + assign resp_valid_o = mem_req_valid_o & mem_req_ready_i & mem_resp_valid_i; + assign req_ready_o = resp_ready_i & resp_valid_o; + + // Forward responses. + assign resp_o = mem_resp_i; + end + + // Forward requests. + assign mem_req_o = req_i; + +// Assertions +// pragma translate_off +`ifndef VERILATOR + if (BufDepth > 0) begin : gen_buf_asserts + assert property (@(posedge clk_i) mem_resp_valid_i |-> buf_ready) + else $error("Memory response lost!"); + assert property (@(posedge clk_i) cnt_q == '0 |=> cnt_q != '1) + else $error("Counter underflowed!"); + assert property (@(posedge clk_i) cnt_q == BufDepth |=> cnt_q != BufDepth + 1) + else $error("Counter overflowed!"); + end else begin : gen_no_buf_asserts + assume property (@(posedge clk_i) mem_req_valid_o & mem_req_ready_i |-> mem_resp_valid_i) + else $error("Without BufDepth = 0, the memory must respond in the same cycle!"); + end +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/event_unit_flex/event_unit_core.sv b/hw/deps/event_unit_flex/event_unit_core.sv new file mode 100644 index 0000000..b7d294c --- /dev/null +++ b/hw/deps/event_unit_flex/event_unit_core.sv @@ -0,0 +1,577 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module event_unit_core +#( + parameter NB_CORES = 4, + parameter NB_SW_EVT = 8, + parameter NB_BARR = NB_CORES/2, + parameter NB_HW_MUT = 2, + parameter MUTEX_MSG_W = 32, + parameter PER_ID_WIDTH = 5 +) +( + // clock and reset + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + + // master event lines, partially private for a specific core + input logic [31:0] master_event_lines_i, + + // sw event generation output + output logic [NB_SW_EVT-1:0] core_sw_events_o, + output logic [NB_CORES-1:0] core_sw_events_mask_o, + + // barrier trigger output + output logic [NB_BARR-1:0] hw_barr_id_o, + + // request and message for mutex units + output logic [NB_HW_MUT-1:0] mutex_rd_req_o, + output logic [NB_HW_MUT-1:0] mutex_wr_req_o, + output logic [NB_HW_MUT-1:0][MUTEX_MSG_W-1:0] mutex_msg_wdata_o, + input logic [NB_HW_MUT-1:0][MUTEX_MSG_W-1:0] mutex_msg_rdata_i, + + // signals for entry point dispatch + output logic dispatch_pop_req_o, + output logic dispatch_pop_ack_o, + input logic [31:0] dispatch_value_i, + + output logic dispatch_w_req_o, + output logic [31:0] dispatch_w_data_o, + output logic [1:0] dispatch_reg_sel_o, + + // clock and interrupt request to core + output logic core_irq_req_o, + output logic [4:0] core_irq_id_o, + input logic core_irq_ack_i, + input logic [4:0] core_irq_ack_id_i, + + input logic core_busy_i, + output logic core_clock_en_o, + + // periph bus slave for regular register access + XBAR_PERIPH_BUS.Slave periph_int_bus_slave, + // demuxed periph for fast register access and event trigger + XBAR_PERIPH_BUS.Slave eu_direct_link_slave + +); + + // registers + logic [31:0] event_mask_DP, event_mask_DN; + logic [31:0] irq_mask_DP, irq_mask_DN; + logic [31:0] event_buffer_DP, event_buffer_DN; + + logic irq_req_del_SP, irq_req_del_SN; + + logic [NB_CORES-1:0] sw_events_mask_DP, sw_events_mask_DN; + logic wait_clear_access_SP, wait_clear_access_SN; + + // calculated write data + logic [31:0] wdata_event_mask_demux, wdata_event_mask_interc; + logic [31:0] wdata_irq_mask_demux, wdata_irq_mask_interc; + logic [31:0] wdata_event_buffer_demux, wdata_event_buffer_interc; + + logic [NB_CORES-1:0] wdata_sw_events_mask_demux, wdata_sw_events_mask_interc; + + // write control + logic [3:0] we_demux, we_interc; + + // combinational signals + logic [31:0] event_buffer_masked, irq_buffer_masked; + logic write_conflict, demux_add_is_sleep, demux_add_is_clear, replay_sleep_req; + logic stop_core_clock, core_clock_en, wait_core_idle; + + logic [31:0] irq_clear_mask; + logic [4:0] irq_sel_id; + logic irq_pending; + logic irq_mask_fsm; + + + // multiple sources for sw events (write to trigger and read from wait regs) + logic [NB_SW_EVT-1:0] sw_events_reg, sw_events_wait; + logic [NB_CORES-1:0] sw_events_mask_reg, sw_events_mask_wait; + + // (delayed) bus signals + logic p_interc_vld_SP, p_interc_vld_SN; + logic p_interc_gnt; + logic p_interc_req_del_SP, p_interc_req_del_SN; + logic p_interc_wen_del_SP, p_interc_wen_del_SN; + logic [3:0] p_interc_add_del_SP, p_interc_add_del_SN; + + logic p_demux_vld_SP, p_demux_vld_SN; + logic p_demux_gnt, p_demux_gnt_sleep_fsm; + logic p_demux_req_del_SP, p_demux_req_del_SN; + logic p_demux_wen_del_SP, p_demux_wen_del_SN; + logic [7:0] p_demux_add_del_SP, p_demux_add_del_SN; + + logic inhibit_req; + + // core clock FSM + enum logic [2:0] { ACTIVE, SLEEP, WAKEUP_SLEEP, WAKEUP_SLEEP_DEL, WAKEUP_IRQ, IRQ_WHILE_SLEEP } core_clock_CS, core_clock_NS; + + // ORing of sw event sources + assign core_sw_events_o = sw_events_reg | sw_events_wait; + assign core_sw_events_mask_o = sw_events_mask_reg | sw_events_mask_wait; + + // masking and reduction of buffer + assign event_buffer_masked = event_buffer_DP & event_mask_DP; + assign irq_buffer_masked = event_buffer_DP & irq_mask_DP; + + // calculation of one-hot clear mask for interrupts + assign irq_pending = |irq_buffer_masked; + assign irq_clear_mask = (core_irq_ack_i) ? ~(1'b1 << core_irq_ack_id_i) : '1; + + // new req/ack handling scheme for interrupts + assign irq_mask_fsm = stop_core_clock & ((core_clock_CS == ACTIVE) | (core_clock_CS == WAKEUP_SLEEP) | (core_clock_CS == WAKEUP_SLEEP_DEL)) & ~irq_req_del_SP; + assign irq_req_del_SN = irq_pending & ~irq_mask_fsm; + assign core_irq_req_o = irq_req_del_SN; + assign core_irq_id_o = irq_sel_id; + + // handle sleeping requests and conflicting write accesses + assign demux_add_is_sleep = ( ({eu_direct_link_slave.add[9:8],eu_direct_link_slave.add[5:3]} == 5'b00_111) || // core regs _wait and _wait_clear + ( eu_direct_link_slave.add[9:6] == 4'b0_101) || // sw events _wait + ( eu_direct_link_slave.add[9:6] == 4'b0_110) || // sw events _wait_clear + ({eu_direct_link_slave.add[9],eu_direct_link_slave.add[4:2]} == 4'b1_110) || // barriers _wait + ({eu_direct_link_slave.add[9],eu_direct_link_slave.add[4:2]} == 4'b1_111) || // barriers _wait_clear + ( eu_direct_link_slave.add[9:6] == 4'b0_011) || // hw mutexes + ({eu_direct_link_slave.add[9:6],eu_direct_link_slave.add[3:2]} == 6'b0010_00 ) ); // hw dispatch fifo_read + + assign demux_add_is_clear = ( ( eu_direct_link_slave.add[9:2] == 8'b00_0011_11) || // core regs _wait_clear + ( eu_direct_link_slave.add[9:6] == 4'b01_10) || // sw events _wait_clear + ({eu_direct_link_slave.add[9],eu_direct_link_slave.add[4:2]} == 4'b1_111) || // barriers _wait_clear + ( eu_direct_link_slave.add[9:6] == 4'b00_11) || // hw mutex units - always _wait_clear + ({eu_direct_link_slave.add[9:6],eu_direct_link_slave.add[3:2]} == 6'b0010_00 ) ); // hw dispatch fifo_read + + assign stop_core_clock = ( (eu_direct_link_slave.req == 1'b1) && (eu_direct_link_slave.wen == 1'b1) && (demux_add_is_sleep == 1'b1) ); + + assign write_conflict = ( ({periph_int_bus_slave.req, eu_direct_link_slave.req} == 2'b11) && + ({periph_int_bus_slave.wen, eu_direct_link_slave.wen} == 2'b00) ); + + // link from peripheral demux + assign p_demux_gnt = eu_direct_link_slave.req & p_demux_gnt_sleep_fsm; + assign p_demux_vld_SN = p_demux_gnt; + + assign eu_direct_link_slave.gnt = p_demux_gnt; + assign eu_direct_link_slave.r_id = '0; + assign eu_direct_link_slave.r_opc = 1'b0; + assign eu_direct_link_slave.r_valid = p_demux_vld_SP; + + assign p_demux_req_del_SN = eu_direct_link_slave.req; + assign p_demux_wen_del_SN = eu_direct_link_slave.wen; + assign p_demux_add_del_SN = eu_direct_link_slave.add[9:2]; + + + // link from peripheral interconnect + assign p_interc_gnt = ( (periph_int_bus_slave.req == 1'b1) && (write_conflict == 1'b0) ); + assign p_interc_vld_SN = p_interc_gnt; + + assign periph_int_bus_slave.gnt = p_interc_gnt; + assign periph_int_bus_slave.r_opc = 1'b0; + assign periph_int_bus_slave.r_valid = p_interc_vld_SP; + assign periph_int_bus_slave.r_id = '0; + + assign p_interc_req_del_SN = periph_int_bus_slave.req; + assign p_interc_wen_del_SN = periph_int_bus_slave.wen; + assign p_interc_add_del_SN = periph_int_bus_slave.add[5:2]; + + assign inhibit_req = (core_clock_CS == SLEEP) || (core_clock_CS == WAKEUP_SLEEP) || + (core_clock_CS == WAKEUP_IRQ) || (wait_core_idle == 1'b1); + + //write logic for demux and interconnect port + always_comb begin + // default register DN data + event_mask_DN = event_mask_DP; + irq_mask_DN = irq_mask_DP; + sw_events_mask_DN = sw_events_mask_DP; + // keep old buffer state and buffer newly triggered events + event_buffer_DN = (event_buffer_DP | master_event_lines_i) & irq_clear_mask; + + // default: don't write any register + we_demux = '0; + wdata_event_mask_demux = '0; + wdata_irq_mask_demux = '0; + wdata_event_buffer_demux = '0; + wdata_sw_events_mask_demux = '0; + + we_interc = '0; + wdata_event_mask_interc = '0; + wdata_irq_mask_interc = '0; + wdata_event_buffer_interc = '0; + wdata_sw_events_mask_interc = '0; + + // default: don't trigger any sw event or barrier + sw_events_reg = '0; + sw_events_mask_reg = '0; + + // default: don't unlock (write) a mutex + mutex_wr_req_o = '0; + mutex_msg_wdata_o = '0; + + // default: don't push a value to or configure the HW dispatch + dispatch_w_req_o = 1'b0; + dispatch_w_data_o = '0; + dispatch_reg_sel_o = '0; + + // periph demux write access + if ( (eu_direct_link_slave.req == 1'b1) && (eu_direct_link_slave.wen == 1'b0) ) begin + casex (eu_direct_link_slave.add[9:6]) // decode reg group + 4'b00_00: begin + // eu core registers + case (eu_direct_link_slave.add[5:2]) + 4'h0: begin we_demux[0] = 1'b1; wdata_event_mask_demux = eu_direct_link_slave.wdata; end + 4'h1: begin we_demux[0] = 1'b1; wdata_event_mask_demux = event_mask_DP & ~eu_direct_link_slave.wdata; end + 4'h2: begin we_demux[0] = 1'b1; wdata_event_mask_demux = event_mask_DP | eu_direct_link_slave.wdata; end + 4'h3: begin we_demux[1] = 1'b1; wdata_irq_mask_demux = eu_direct_link_slave.wdata; end + 4'h4: begin we_demux[1] = 1'b1; wdata_irq_mask_demux = irq_mask_DP & ~eu_direct_link_slave.wdata; end + 4'h5: begin we_demux[1] = 1'b1; wdata_irq_mask_demux = irq_mask_DP | eu_direct_link_slave.wdata; end + 4'ha: begin we_demux[2] = 1'b1; wdata_event_buffer_demux = event_buffer_DP & ~eu_direct_link_slave.wdata; end + 4'hb: begin we_demux[3] = 1'b1; wdata_sw_events_mask_demux = eu_direct_link_slave.wdata[NB_CORES-1:0]; end + 4'hc: begin we_demux[3] = 1'b1; wdata_sw_events_mask_demux = sw_events_mask_DP & ~eu_direct_link_slave.wdata[NB_CORES-1:0]; end + 4'hd: begin we_demux[3] = 1'b1; wdata_sw_events_mask_demux = sw_events_mask_DP | eu_direct_link_slave.wdata[NB_CORES-1:0]; end + endcase + end + 4'b00_10: begin + // hw dispatch + dispatch_w_req_o = 1'b1; + dispatch_w_data_o = eu_direct_link_slave.wdata; + dispatch_reg_sel_o = eu_direct_link_slave.add[3:2]; + end + 4'b00_11: begin + // hw mutexes + mutex_wr_req_o[eu_direct_link_slave.add[5:2]] = 1'b1; + mutex_msg_wdata_o[eu_direct_link_slave.add[5:2]] = eu_direct_link_slave.wdata; + end + 4'b01_??: begin + // handle sw event triggering + if ( eu_direct_link_slave.add[7:6] == 2'b00 ) begin + sw_events_reg[eu_direct_link_slave.add[4:2]] = 1'b1; + // use all-0 state to trigger all cores + if ( eu_direct_link_slave.wdata[NB_CORES-1:0] == '0 ) + sw_events_mask_reg = '1; + else + sw_events_mask_reg = eu_direct_link_slave.wdata[NB_CORES-1:0]; + end + end + endcase + end + + // periph interconnect write access + if ( (periph_int_bus_slave.req == 1'b1) && (periph_int_bus_slave.wen == 1'b0) ) begin + case (periph_int_bus_slave.add[5:2]) + 4'h0: begin we_interc[0] = 1'b1; wdata_event_mask_interc = periph_int_bus_slave.wdata; end + 4'h1: begin we_interc[0] = 1'b1; wdata_event_mask_interc = event_mask_DP & ~periph_int_bus_slave.wdata; end + 4'h2: begin we_interc[0] = 1'b1; wdata_event_mask_interc = event_mask_DP | periph_int_bus_slave.wdata; end + 4'h3: begin we_interc[1] = 1'b1; wdata_irq_mask_interc = periph_int_bus_slave.wdata; end + 4'h4: begin we_interc[1] = 1'b1; wdata_irq_mask_interc = irq_mask_DP & ~periph_int_bus_slave.wdata; end + 4'h5: begin we_interc[1] = 1'b1; wdata_irq_mask_interc = irq_mask_DP | periph_int_bus_slave.wdata; end + 4'ha: begin we_interc[2] = 1'b1; wdata_event_buffer_interc = event_buffer_DP & ~periph_int_bus_slave.wdata; end + 4'hb: begin we_interc[3] = 1'b1; wdata_sw_events_mask_interc = periph_int_bus_slave.wdata[NB_CORES-1:0]; end + 4'hc: begin we_interc[3] = 1'b1; wdata_sw_events_mask_interc = sw_events_mask_DP & ~periph_int_bus_slave.wdata[NB_CORES-1:0]; end + 4'hd: begin we_interc[3] = 1'b1; wdata_sw_events_mask_interc = sw_events_mask_DP | periph_int_bus_slave.wdata[NB_CORES-1:0]; end + endcase + end + + // write arbiters - demux write access takes priority + if ( we_demux[0] == 1'b1 ) + event_mask_DN = wdata_event_mask_demux; + else if ( we_interc[0] == 1'b1 ) + event_mask_DN = wdata_event_mask_interc; + + if ( we_demux[1] == 1'b1 ) + irq_mask_DN = wdata_irq_mask_demux; + else if ( we_interc[1] == 1'b1 ) + irq_mask_DN = wdata_irq_mask_interc; + + + if ( wait_clear_access_SP == 1'b1 ) + event_buffer_DN = ((event_buffer_DP | master_event_lines_i) & ~event_mask_DP) & irq_clear_mask; + else if ( we_demux[2] == 1'b1 ) + event_buffer_DN = (wdata_event_buffer_demux | master_event_lines_i) & irq_clear_mask; + else if ( we_interc[2] == 1'b1 ) + event_buffer_DN = (wdata_event_buffer_interc | master_event_lines_i) & irq_clear_mask; + + + if ( we_demux[3] == 1'b1 ) + sw_events_mask_DN = wdata_sw_events_mask_demux; + else if ( we_interc[3] == 1'b1 ) + sw_events_mask_DN = wdata_sw_events_mask_interc; + + end + + // read muxes for both links + always_comb begin + eu_direct_link_slave.r_rdata = '0; + periph_int_bus_slave.r_rdata = '0; + + // default: don't trigger any sw event or barrier or mutex + sw_events_wait = '0; + sw_events_mask_wait = '0; + hw_barr_id_o = '0; + mutex_rd_req_o = '0; + + // default: dont'r request to pop a value from the dispatch FIFO + dispatch_pop_req_o = 1'b0; + + // read accesses for periph demux port; inclues _wait and _wait_clear regs + if ( (p_demux_req_del_SP == 1'b1) && (p_demux_wen_del_SP == 1'b1) ) begin + case (p_demux_add_del_SP[7:4]) // decode reg group + 4'b00_00: begin // eu core registers + case (p_demux_add_del_SP[3:0]) + 4'h0: eu_direct_link_slave.r_rdata = event_mask_DP; + 4'h3: eu_direct_link_slave.r_rdata = irq_mask_DP; + 4'h6: eu_direct_link_slave.r_rdata = {31'b0, core_clock_en}; + 4'h7: eu_direct_link_slave.r_rdata = event_buffer_DP; + 4'h8: eu_direct_link_slave.r_rdata = event_buffer_masked; + 4'h9: eu_direct_link_slave.r_rdata = irq_buffer_masked; + 4'hb: eu_direct_link_slave.r_rdata = {{(32-NB_CORES){1'b0}}, sw_events_mask_DP}; + 4'he: eu_direct_link_slave.r_rdata = event_buffer_masked; + 4'hf: eu_direct_link_slave.r_rdata = event_buffer_masked; + endcase + end + 4'b00_10: begin // hw dispatch pop request + if ( p_demux_add_del_SP[1:0] == 2'b00 ) + eu_direct_link_slave.r_rdata = dispatch_value_i; + end + // mutex read/lock request + 4'b00_11: eu_direct_link_slave.r_rdata = mutex_msg_rdata_i[p_demux_add_del_SP[3:0]]; + // some wait register for either sw_event or barrier + 4'b0101,4'b0110,4'b1011,4'b1100: eu_direct_link_slave.r_rdata = event_buffer_masked; + endcase + end + + if ( (eu_direct_link_slave.req == 1'b1) && (eu_direct_link_slave.wen == 1'b1) && + (replay_sleep_req == 1'b0) && (inhibit_req == 1'b0) ) begin + // trigger sw_event+read buffer+sleep(+clear) accesses + if ( (eu_direct_link_slave.add[9:6] == 4'b0101) || (eu_direct_link_slave.add[9:6] == 4'b0110) ) begin + sw_events_wait[eu_direct_link_slave.add[4:2]] = 1'b1; + // use all-0 state to trigger all cores + if ( sw_events_mask_DP == '0 ) + sw_events_mask_wait = '1; + else + sw_events_mask_wait = sw_events_mask_DP; + end + + // trigger hw_barrier+read buffer+sleep(+clear) accesses + if ( ({eu_direct_link_slave.add[9],eu_direct_link_slave.add[4:2]} == 4'b1_110) || + ({eu_direct_link_slave.add[9],eu_direct_link_slave.add[4:2]} == 4'b1_111) ) + begin + hw_barr_id_o[eu_direct_link_slave.add[8:5]] = 1'b1; ; + end + + // try to lock a mutex + if ( eu_direct_link_slave.add[9:6] == 4'b0_011 ) + mutex_rd_req_o[eu_direct_link_slave.add[5:2]] = 1'b1; + + // try to pop a value from the dispatch FIFO + if ( eu_direct_link_slave.add[9:2] == 8'b0_01000_00 ) + dispatch_pop_req_o = 1'b1; + + end + + // only regular read accesses for interconnect port + if ( (p_interc_req_del_SP == 1'b1) && (p_interc_wen_del_SP == 1'b1) ) begin + case (p_interc_add_del_SP) + 4'h0: periph_int_bus_slave.r_rdata = event_mask_DP; + 4'h3: periph_int_bus_slave.r_rdata = irq_mask_DP; + 4'h6: periph_int_bus_slave.r_rdata = {31'b0, core_clock_en}; + 4'h7: periph_int_bus_slave.r_rdata = event_buffer_DP; + 4'h8: periph_int_bus_slave.r_rdata = event_buffer_masked; + 4'h9: periph_int_bus_slave.r_rdata = irq_buffer_masked; + 4'hb: periph_int_bus_slave.r_rdata = {{(32-NB_CORES){1'b0}}, sw_events_mask_DP}; + endcase + end + end + + + // FSM for controlling the core clock + always_comb begin + core_clock_NS = core_clock_CS; + core_clock_en = 1'b1; + replay_sleep_req = 1'b0; + p_demux_gnt_sleep_fsm = 1'b1; + wait_clear_access_SN = 1'b0; + wait_core_idle = 1'b0; + dispatch_pop_ack_o = 1'b0; + + case (core_clock_CS) + ACTIVE: begin + // check if there is any sleep request at all + if ( stop_core_clock ) begin + if ( irq_req_del_SP ) + core_clock_NS = IRQ_WHILE_SLEEP; + else begin + // corner-case: event already triggered while going to sleep + if ( |event_buffer_masked ) begin + // inform dispatch that value is consumed + dispatch_pop_ack_o = 1'b1; + // handle buffer clear cases + if ( demux_add_is_clear == 1'b1 ) + wait_clear_access_SN = 1'b1; + end + else begin + p_demux_gnt_sleep_fsm = 1'b0; + if (core_busy_i == 1'b0) + core_clock_NS = SLEEP; + else + wait_core_idle = 1'b1; + end + end + end + end + SLEEP: begin + core_clock_en = 1'b0; + p_demux_gnt_sleep_fsm = 1'b0; + + if ( irq_pending ) begin + core_clock_en = 1'b1; + core_clock_NS = WAKEUP_IRQ; + end + else if ( |event_buffer_masked == 1'b1 ) begin + core_clock_NS = WAKEUP_SLEEP; + end + end + WAKEUP_IRQ: begin + core_clock_NS = IRQ_WHILE_SLEEP; + end + WAKEUP_SLEEP: begin + // we can be sure that dispatch value is consumed + dispatch_pop_ack_o = 1'b1; + // handle buffer clear cases + if ( demux_add_is_clear == 1'b1 ) begin + wait_clear_access_SN = 1'b1; + // allow 1 more cycle to clear event buffer to not skip immediately following sleep requests + core_clock_NS = WAKEUP_SLEEP_DEL; + end + else begin + core_clock_NS = ACTIVE; + end + end + WAKEUP_SLEEP_DEL: begin + // possible that we already have a new sleep request - stall the requesting core 1 cycle + if ( stop_core_clock ) + p_demux_gnt_sleep_fsm = 1'b0; + core_clock_NS = ACTIVE; + end + IRQ_WHILE_SLEEP: begin + if ( stop_core_clock == 1'b1 ) begin + replay_sleep_req = 1'b1; + if ( irq_pending == 1'b0 ) begin + if ( |event_buffer_masked == 1'b1 ) begin + core_clock_NS = WAKEUP_SLEEP; + // handle buffer clear cases + if ( demux_add_is_clear == 1'b1 ) + wait_clear_access_SN = 1'b1; + end + else begin + p_demux_gnt_sleep_fsm = 1'b0; + if (core_busy_i == 1'b0) + core_clock_NS = SLEEP; + end + end + end + end + endcase // core_clock_CS + end + + assign core_clock_en_o = core_clock_en; + + // find first leading 1 for current irq priorization scheme + fl1_loop #( + .WIDTH(32) ) + fl1_loop_i ( + .vector_i(irq_buffer_masked), + .idx_bin_o(irq_sel_id), + .no1_o() + ); + + always_ff @(posedge clk_i, negedge rst_ni) begin + if ( rst_ni == 1'b0 ) begin + core_clock_CS <= ACTIVE; + event_mask_DP <= '0; + irq_mask_DP <= '0; + irq_req_del_SP <= '0; + event_buffer_DP <= '0; + wait_clear_access_SP <= '0; + sw_events_mask_DP <= '0; + + p_demux_vld_SP <= 1'b0; + p_demux_add_del_SP <= '0; + p_demux_req_del_SP <= 1'b0; + p_demux_wen_del_SP <= 1'b0; + p_interc_vld_SP <= 1'b0; + p_interc_add_del_SP <= '0; + p_interc_req_del_SP <= 1'b0; + p_interc_wen_del_SP <= 1'b0; + end + else begin + core_clock_CS <= core_clock_NS; + + if ( we_demux[0] == 1'b1 ) + event_mask_DP <= wdata_event_mask_demux; + else if ( we_interc[0] == 1'b1 ) + event_mask_DP <= wdata_event_mask_interc; + + if ( wait_clear_access_SP | core_irq_ack_i | (|master_event_lines_i) | we_demux[2] | we_interc[2] ) + event_buffer_DP <= event_buffer_DN; + + event_mask_DP <= event_mask_DN; + irq_mask_DP <= irq_mask_DN; + irq_req_del_SP <= irq_req_del_SN; + + wait_clear_access_SP <= wait_clear_access_SN; + sw_events_mask_DP <= sw_events_mask_DN; + + p_demux_vld_SP <= p_demux_vld_SN; + + if(eu_direct_link_slave.req & eu_direct_link_slave.gnt) + p_demux_add_del_SP <= p_demux_add_del_SN; + + p_demux_req_del_SP <= p_demux_req_del_SN; + p_demux_wen_del_SP <= p_demux_wen_del_SN; + p_interc_vld_SP <= p_interc_vld_SN; + + if(periph_int_bus_slave.req & periph_int_bus_slave.gnt) + p_interc_add_del_SP <= p_interc_add_del_SN; + + p_interc_req_del_SP <= p_interc_req_del_SN; + p_interc_wen_del_SP <= p_interc_wen_del_SN; + end + end + +endmodule // event_unit_core + +module fl1_loop +#( + parameter WIDTH = 4 +) +( + input logic [WIDTH-1:0] vector_i, + output logic [$clog2(WIDTH)-1:0] idx_bin_o, + output logic no1_o +); + + assign no1_o = ~(|vector_i); + + logic found; + + always_comb begin + found = 1'b0; + idx_bin_o = '0; + + for (int i = WIDTH-1; i > 0; i--) begin + if ( (vector_i[i] == 1'b1) && (found == 1'b0) ) begin + found = 1'b1; + idx_bin_o = i; + end + end + end + +endmodule diff --git a/hw/deps/event_unit_flex/event_unit_interface_mux.sv b/hw/deps/event_unit_flex/event_unit_interface_mux.sv new file mode 100644 index 0000000..1360689 --- /dev/null +++ b/hw/deps/event_unit_flex/event_unit_interface_mux.sv @@ -0,0 +1,330 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module event_unit_interface_mux +#( + parameter NB_CORES = 4, + parameter NB_BARR = NB_CORES/2, + parameter PER_ID_WIDTH = NB_CORES+1 +) +( + // clock and reset + input logic clk_i, + input logic rst_ni, + + // slave port from periph interconnect, decode requests + XBAR_PERIPH_BUS.Slave speriph_slave, + XBAR_PERIPH_BUS.Master periph_int_bus_master[NB_CORES+NB_BARR+2:0], + + // demuxed slave ports from each core, redistribute to eu_core and barrier units + XBAR_PERIPH_BUS.Slave demux_slave[NB_CORES-1:0], + XBAR_PERIPH_BUS.Master demux_int_bus_core_master[NB_CORES-1:0], + XBAR_PERIPH_BUS.Master demux_int_bus_barrier_master[NB_CORES*NB_BARR-1:0] +); + + + genvar I,J; + + + //*************************************************************// + // // + // ██████╗ ███████╗███╗ ███╗██╗ ██╗██╗ ██╗ // + // ██╔══██╗██╔════╝████╗ ████║██║ ██║╚██╗██╔╝ // + // ██║ ██║█████╗ ██╔████╔██║██║ ██║ ╚███╔╝ // + // ██║ ██║██╔══╝ ██║╚██╔╝██║██║ ██║ ██╔██╗ // + // ██████╔╝███████╗██║ ╚═╝ ██║╚██████╔╝██╔╝ ██╗ // + // ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // + // // + //*************************************************************// + + + // response channel for demux plug + logic [NB_CORES-1:0][4:0] demux_ip_sel_SP, demux_ip_sel_SN; + logic [NB_CORES-1:0] demux_slave_req_del; + logic [NB_CORES-1:0] demux_slave_update; + logic [NB_CORES-1:0] demux_add_is_core; + logic [NB_CORES-1:0] demux_slave_gnt_mux; + + // helper arrays to work around sv dynamic bus index select limitation + logic [NB_CORES-1:0] demux_slaves_core_req; + + logic [NB_CORES*NB_BARR-1:0][31:0] demux_int_bus_barrier_master_rdata; + logic [NB_CORES*NB_BARR-1:0] demux_slaves_barrier_req; + logic [NB_CORES-1:0][NB_BARR-1:0] demux_slv_bar_req_int; + logic [NB_BARR-1:0][NB_CORES-1:0] demux_slv_bar_req_int_transp; + + generate + for ( I = 0; I < NB_CORES; I++ ) begin + // slave->master: output ports to cores + assign demux_slave[I].gnt = demux_slave_gnt_mux[I]; + assign demux_slave[I].r_opc = 1'b0; + assign demux_slave[I].r_id = '0; + // activation condition for responses on each demux plug + assign demux_slave_update[I] = ( (demux_slave[I].req & ~demux_slave_req_del[I]) || + (~demux_slave[I].req & demux_slave_req_del[I]) || + (demux_slave[I].req & demux_slave_gnt_mux[I]) ); + // check if Core I wants to access its private event_unit_core + assign demux_add_is_core[I] = ( ( demux_slave[I].add[9] == 1'b0 ) || // some core reg + ({demux_slave[I].add[9],demux_slave[I].add[4:2]} == 4'b1_110) || // barrier_trigg_wait + ({demux_slave[I].add[9],demux_slave[I].add[4:2]} == 4'b1_111) ); // barrier_trigg_wait_clear + assign demux_ip_sel_SN[I] = demux_add_is_core[I] ? '0 : {1'b1,demux_slave[I].add[8:5]}; + end + endgenerate + + generate + for ( J = 0; J < NB_BARR; J++ ) begin + for ( I = 0; I < NB_CORES; I++ ) assign demux_slv_bar_req_int_transp[J][I] = demux_slv_bar_req_int[I][J]; + assign demux_slaves_barrier_req[(J+1)*NB_CORES-1:J*NB_CORES] = demux_slv_bar_req_int_transp[J]; + end + endgenerate + + generate + for ( I = 0; I < NB_CORES; I++ ) begin + // master->slave + assign demux_int_bus_core_master[I].req = demux_slaves_core_req[I]; + assign demux_int_bus_core_master[I].add = demux_slave[I].add; + assign demux_int_bus_core_master[I].wen = demux_slave[I].wen; + assign demux_int_bus_core_master[I].wdata = demux_slave[I].wdata; + + assign demux_int_bus_core_master[I].id = '0; + assign demux_int_bus_core_master[I].be = '0; + end + endgenerate + + generate + for ( I = 0; I < NB_CORES*NB_BARR; I++ ) begin + // master->slave + assign demux_int_bus_barrier_master[I].req = demux_slaves_barrier_req[I]; + assign demux_int_bus_barrier_master[I].add = demux_slave[I % NB_CORES].add; + assign demux_int_bus_barrier_master[I].wen = demux_slave[I % NB_CORES].wen; + assign demux_int_bus_barrier_master[I].wdata = demux_slave[I % NB_CORES].wdata; + + assign demux_int_bus_barrier_master[I].id = '0; + assign demux_int_bus_barrier_master[I].be = '0; + + // slave->master: intermediate level + assign demux_int_bus_barrier_master_rdata[I] = demux_int_bus_barrier_master[I].r_rdata; + end + endgenerate + + generate + for ( I = 0; I < NB_CORES; I++ ) begin + // decoding of IP select part of address in case of request, selection of correct gnt + always_comb begin + demux_slv_bar_req_int[I] = '0; + + demux_slaves_core_req[I] = 1'b0; + demux_slave_gnt_mux[I] = 1'b0; + + if ( demux_slave[I].req == 1'b1 ) begin + // send request to private core unit, mux gnt back + if ( demux_add_is_core[I] ) begin + demux_slaves_core_req[I] = 1'b1; + demux_slave_gnt_mux[I] = demux_int_bus_core_master[I].gnt; + end + // send request to correct barrier unit, gnt can directly be given + else begin + demux_slv_bar_req_int[I][demux_slave[I].add[8:5]] = 1'b1; + demux_slave_gnt_mux[I] = 1'b1; + end + end + end + + // delayed muxing of correct response + always_comb begin + + // default: silence response channel + demux_slave[I].r_valid = 1'b0; + demux_slave[I].r_rdata = '0; + + if ( demux_slave_req_del[I] ) begin + if ( ~demux_ip_sel_SP[I][4] ) begin + demux_slave[I].r_valid = demux_int_bus_core_master[I].r_valid; + demux_slave[I].r_rdata = demux_int_bus_core_master[I].r_rdata; + end + else begin + demux_slave[I].r_valid = 1'b1; + demux_slave[I].r_rdata = demux_int_bus_barrier_master_rdata[NB_CORES*demux_ip_sel_SP[I][3:0]+I]; + end + end + end + + // 5 FF per core to store the response source + always_ff @(posedge clk_i, negedge rst_ni) + begin + if (~rst_ni) + begin + demux_ip_sel_SP[I] <= '0; + demux_slave_req_del[I] <= 1'b0; + end + else + begin + demux_slave_req_del[I] <= demux_slave[I].req; + if ( demux_slave_update[I] ) + demux_ip_sel_SP[I] <= demux_ip_sel_SN[I]; + end + end + end + endgenerate + + + //*************************************************************// + // // + // ██╗███╗ ██╗████████╗███████╗██████╗ ██████╗ // + // ██║████╗ ██║╚══██╔══╝██╔════╝██╔══██╗██╔════╝ // + // ██║██╔██╗ ██║ ██║ █████╗ ██████╔╝██║ // + // ██║██║╚██╗██║ ██║ ██╔══╝ ██╔══██╗██║ // + // ██║██║ ╚████║ ██║ ███████╗██║ ██║╚██████╗ // + // ╚═╝╚═╝ ╚═══╝ ╚═╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝ // + // // + //*************************************************************// + + // response channel for interconnect plug + logic [5:0] interc_ip_sel_SP, interc_ip_sel_SN; + logic speriph_slave_req_del; + logic speriph_slave_update; + logic speriph_slave_gnt_mux; + + logic [NB_CORES+NB_BARR+2:0] interc_slaves_req; + + // helper arrays to work around sv dynamic bus index select limitation + logic [NB_CORES-1:0][31:0] periph_int_bus_core_rdata; + logic [NB_BARR-1:0][31:0] periph_int_bus_barr_rdata; + logic [NB_CORES-1:0] periph_int_bus_core_rvalid; + logic [NB_BARR-1:0] periph_int_bus_barr_rvalid; + logic [NB_CORES-1:0] periph_int_bus_core_gnt; + logic [NB_BARR-1:0] periph_int_bus_barr_gnt; + + assign interc_ip_sel_SN = speriph_slave.add[10:5]; + + // activation condition for speriph slave responses + assign speriph_slave_update = ( (speriph_slave.req & ~speriph_slave_req_del) || + (~speriph_slave.req & speriph_slave_req_del) || + (speriph_slave.req & speriph_slave_gnt_mux) ); + + // broadcast master->slave signals with exception of req + generate + for ( I = 0; I < NB_CORES+NB_BARR+3; I++ ) begin + assign periph_int_bus_master[I].wdata = speriph_slave.wdata; + assign periph_int_bus_master[I].add = speriph_slave.add; + assign periph_int_bus_master[I].wen = speriph_slave.wen; + assign periph_int_bus_master[I].be = '1; + assign periph_int_bus_master[I].id = '0; + assign periph_int_bus_master[I].req = interc_slaves_req[I]; + end + endgenerate + + // assign slave->master signals + generate + for ( I = 0; I < NB_CORES; I++ ) begin + assign periph_int_bus_core_rdata[I] = periph_int_bus_master[I].r_rdata; + assign periph_int_bus_core_rvalid[I] = periph_int_bus_master[I].r_valid; + assign periph_int_bus_core_gnt[I] = periph_int_bus_master[I].gnt; + end + for ( I = 0; I < NB_BARR; I++ ) begin + assign periph_int_bus_barr_rdata[I] = periph_int_bus_master[NB_CORES+I].r_rdata; + assign periph_int_bus_barr_rvalid[I] = periph_int_bus_master[NB_CORES+I].r_valid; + assign periph_int_bus_barr_gnt[I] = periph_int_bus_master[NB_CORES+I].gnt; + end + endgenerate + + // assign muxed slave->master gnt + assign speriph_slave.gnt = speriph_slave_gnt_mux; + assign speriph_slave.r_opc = 1'b0; + + // decoding of IP select part of address in case of request, selection of correct gnt + always_comb begin + interc_slaves_req = '0; + speriph_slave_gnt_mux = 1'b0; + + if ( speriph_slave.req == 1'b1 ) begin + casex ( speriph_slave.add[10:7] ) + 4'b0???: begin // core units - each 0x40 (16 regs) long, [9:6] decides about which unit + interc_slaves_req[speriph_slave.add[9:6]] = 1'b1; + speriph_slave_gnt_mux = periph_int_bus_core_gnt[speriph_slave.add[9:6]]; + end + 4'b10??: begin // hw barrier - each 0x20 (8 regs) long, [8:5] decides about which unit + interc_slaves_req[NB_CORES+speriph_slave.add[8:5]] = 1'b1; + speriph_slave_gnt_mux = periph_int_bus_barr_gnt[speriph_slave.add[8:5]]; + end + 4'b110?: begin // external sw event triggering + interc_slaves_req[NB_CORES+NB_BARR] = 1'b1; + speriph_slave_gnt_mux = periph_int_bus_master[NB_CORES+NB_BARR].gnt; + end + 4'b1110: begin // soc event FIFO + interc_slaves_req[NB_CORES+NB_BARR+1] = 1'b1; + speriph_slave_gnt_mux = periph_int_bus_master[NB_CORES+NB_BARR+1].gnt; + end + 4'b1111: begin // inter-cluster FIFOs + interc_slaves_req[NB_CORES+NB_BARR+2] = 1'b1; + speriph_slave_gnt_mux = periph_int_bus_master[NB_CORES+NB_BARR+2].gnt; + end + endcase + end + end + + // delayed muxing of correct response + always_comb begin + + // default: silence response channel + speriph_slave.r_valid = 1'b0; + speriph_slave.r_rdata = '0; + + if ( speriph_slave_req_del ) begin + casex ( interc_ip_sel_SP[5:2] ) + 4'b0???: begin // core units + speriph_slave.r_valid = periph_int_bus_core_rvalid[interc_ip_sel_SP[4:1]]; + speriph_slave.r_rdata = periph_int_bus_core_rdata[interc_ip_sel_SP[4:1]]; + end + 4'b10??: begin // barrier units + speriph_slave.r_valid = periph_int_bus_barr_rvalid[interc_ip_sel_SP[3:0]]; + speriph_slave.r_rdata = periph_int_bus_barr_rdata[interc_ip_sel_SP[3:0]]; + end + 4'b110?: begin // external sw event trigger + speriph_slave.r_valid = periph_int_bus_master[NB_CORES+NB_BARR].r_valid; + speriph_slave.r_rdata = periph_int_bus_master[NB_CORES+NB_BARR].r_rdata; + end + 4'b1110: begin // soc event FIFO + speriph_slave.r_valid = periph_int_bus_master[NB_CORES+NB_BARR+1].r_valid; + speriph_slave.r_rdata = periph_int_bus_master[NB_CORES+NB_BARR+1].r_rdata; + end + 4'b1111: begin // inter-cluster FIFOs + speriph_slave.r_valid = periph_int_bus_master[NB_CORES+NB_BARR+2].r_valid; + speriph_slave.r_rdata = periph_int_bus_master[NB_CORES+NB_BARR+2].r_rdata; + end + default: begin + speriph_slave.r_valid = 1'b0; + speriph_slave.r_rdata = '0; + end + endcase + end + + end + + // delay for interconnect signals + always_ff @(posedge clk_i, negedge rst_ni) + begin + if (~rst_ni) begin + speriph_slave.r_id <= '0; + interc_ip_sel_SP <= '0; + speriph_slave_req_del <= 1'b0; + end + else + begin + speriph_slave_req_del <= speriph_slave.req; + if ( speriph_slave_update ) + begin + speriph_slave.r_id <= speriph_slave.id; + interc_ip_sel_SP <= interc_ip_sel_SN; + end + end + end + +endmodule // event_unit_interface_mux diff --git a/hw/deps/event_unit_flex/event_unit_top.sv b/hw/deps/event_unit_flex/event_unit_top.sv new file mode 100644 index 0000000..5b32d84 --- /dev/null +++ b/hw/deps/event_unit_flex/event_unit_top.sv @@ -0,0 +1,338 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module event_unit_top +#( + parameter NB_CORES = 8, + parameter NB_SW_EVT = 8, + parameter NB_BARR = 8, + parameter NB_HW_MUT = 1, + parameter MUTEX_MSG_W = 32, + parameter DISP_FIFO_DEPTH = 8, + parameter PER_ID_WIDTH = 9, + parameter EVNT_WIDTH = 8, + parameter SOC_FIFO_DEPTH = 8 +) +( + // clock and reset + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + + // all kinds of cluster internal events, split into different signals for readability + input logic [NB_CORES-1:0][3:0] acc_events_i, + input logic [NB_CORES-1:0][1:0] dma_events_i, + input logic [NB_CORES-1:0][1:0] timer_events_i, + // usually much less than 32 bit, only for flexibility for different chips + input logic [NB_CORES-1:0][31:0] cluster_events_i, + + output logic [NB_CORES-1:0] core_irq_req_o, + output logic [NB_CORES-1:0][4:0] core_irq_id_o, + input logic [NB_CORES-1:0] core_irq_ack_i, + input logic [NB_CORES-1:0][4:0] core_irq_ack_id_i, + + input logic [NB_CORES-1:0] core_busy_i, + output logic [NB_CORES-1:0] core_clock_en_o, + + // bus slave connections - periph bus and eu_direct_link + XBAR_PERIPH_BUS.Slave speriph_slave, + XBAR_PERIPH_BUS.Slave eu_direct_link[NB_CORES-1:0], + + // soc periph events + input logic soc_periph_evt_valid_i, + output logic soc_periph_evt_ready_o, + input logic [EVNT_WIDTH-1:0] soc_periph_evt_data_i, + + // message bus connections - dummy implementation + MESSAGE_BUS.Master message_master + + ); + + // event lines from soc periph fifo and inter-cluster event dispatch + logic soc_periph_event; + + // sw events and target core mask from each core + logic [NB_SW_EVT-1:0][NB_CORES-1:0] core_sw_events; + logic [NB_CORES-1:0][NB_SW_EVT-1:0] core_sw_events_transp; + logic [NB_CORES-1:0][NB_CORES-1:0] core_sw_events_mask; + logic [NB_CORES-1:0][NB_CORES-1:0] core_sw_events_mask_transp; + logic [NB_CORES-1:0][7:0] sw_events_combined; + // sw events from interconnect + logic [NB_CORES-1:0][NB_SW_EVT-1:0] interc_int_events_sw; + + + // cluster internal event matrix: sw, barr and other cluster events + logic [NB_CORES-1:0][31:0] cluster_int_events; + + // link between hw barrier and eu core units to fast trigger barriers + logic [NB_CORES-1:0][NB_BARR-1:0] hw_barr_trigger; + logic [NB_BARR-1:0][NB_CORES-1:0] hw_barr_trigger_transp; + + // intermediate signals for assigning + logic [NB_CORES-1:0][NB_SW_EVT-1:0] cluster_int_events_sw; + logic [NB_CORES-1:0][NB_BARR-1:0] cluster_int_events_barr; + logic [NB_BARR-1:0][NB_CORES-1:0] cluster_int_events_barr_transp; + logic [NB_CORES-1:0] cluster_int_events_barr_red; + logic [NB_CORES-1:0][NB_HW_MUT-1:0] cluster_int_events_mutex; + logic [NB_HW_MUT-1:0][NB_CORES-1:0] cluster_int_events_mutex_transp; + logic [NB_CORES-1:0] cluster_int_events_mutex_red; + logic [NB_CORES-1:0] cluster_int_events_dispatch; + + // hw mutex related signals + logic [NB_CORES-1:0][NB_HW_MUT-1:0] mutex_lock_req; + logic [NB_HW_MUT-1:0][NB_CORES-1:0] mutex_lock_req_transp; + logic [NB_CORES-1:0][NB_HW_MUT-1:0] mutex_unlock_req; + logic [NB_HW_MUT-1:0][NB_CORES-1:0] mutex_unlock_req_transp; + + logic [NB_HW_MUT-1:0][MUTEX_MSG_W-1:0] mutex_msg_rdata; + logic [NB_CORES-1:0][NB_HW_MUT-1:0][MUTEX_MSG_W-1:0] mutex_msg_wdata; + logic [NB_HW_MUT-1:0][MUTEX_MSG_W-1:0][NB_CORES-1:0] mutex_msg_wdata_transp; + logic [NB_HW_MUT-1:0][MUTEX_MSG_W-1:0] mutex_msg_wdata_transp_red; + + // hw dispatch related signals + logic [NB_CORES-1:0] disp_pop_req; + logic [NB_CORES-1:0] disp_pop_ack; + logic [NB_CORES-1:0][31:0] disp_value; + + logic [NB_CORES-1:0] disp_w_req; + logic [NB_CORES-1:0][31:0] disp_w_data; + logic [NB_CORES-1:0][1:0] disp_reg_sel; + + // periph bus links to all subcomponents + XBAR_PERIPH_BUS periph_int_bus[NB_CORES+NB_BARR+2:0](); + + // demux periph bus to eu_core and barrier units + XBAR_PERIPH_BUS demux_int_bus_core[NB_CORES-1:0](); + XBAR_PERIPH_BUS demux_int_bus_barrier[NB_CORES*NB_BARR-1:0](); + + genvar I,J,K; + + // combination of trigger sources for sw events + generate + for ( I = 0; I < NB_CORES; I++ ) begin : SW_EVENTS_COMBINE + always_comb begin + sw_events_combined[I][7:0] = '0; + sw_events_combined[I][NB_SW_EVT-1:0] = cluster_int_events_sw[I] | interc_int_events_sw[I]; + end + end + endgenerate + + cluster_event_map #( + .NB_CORES ( NB_CORES ) ) + cluster_event_map_i ( + .sw_events_i ( sw_events_combined ), + .barrier_events_i ( cluster_int_events_barr_red ), + .mutex_events_i ( cluster_int_events_mutex_red ), + .dispatch_events_i ( cluster_int_events_dispatch ), + .periph_fifo_event_i ( soc_periph_event ), + + .acc_events_i ( acc_events_i ), + .dma_events_i ( dma_events_i ), + .timer_events_i ( timer_events_i ), + .cluster_events_i ( cluster_events_i ), + + .events_mapped_o ( cluster_int_events ) + ); + + // combinational calculation of every sw event line for every core + // transposing and combinational reduction of barrier and mutex events and signals + generate + for ( I=0; I < NB_CORES; I++ ) begin : EU_LOOP_CORE + assign cluster_int_events_barr_red[I] = |cluster_int_events_barr[I]; + assign cluster_int_events_mutex_red[I] = |cluster_int_events_mutex[I]; + + for ( J=0; J < NB_BARR; J++ ) begin : EU_LOOP_HW_BARR_TRANSP + assign hw_barr_trigger_transp[J][I] = hw_barr_trigger[I][J]; + assign cluster_int_events_barr[I][J] = cluster_int_events_barr_transp[J][I]; + end + + for ( J=0; J < NB_SW_EVT; J++ ) begin : EU_LOOP_SW_EVTS_TRANSP + assign core_sw_events[J][I] = core_sw_events_transp[I][J]; + end + + for ( J=0; J < NB_CORES; J++ ) begin : EU_LOOP_SW_EVTS_MASK_TRANSP + assign core_sw_events_mask[J][I] = core_sw_events_mask_transp[I][J]; + end + + for ( J=0; J < NB_SW_EVT; J++ ) begin : EU_LOOP_SW_EVTS_MASK_APPLY + assign cluster_int_events_sw[I][J] = (core_sw_events[J][NB_CORES-1:0] & core_sw_events_mask[I][NB_CORES-1:0]) != '0; + end + + for ( J=0; J < NB_HW_MUT; J++ ) begin : EU_LOOP_HW_MUTEX_TRANSP + assign cluster_int_events_mutex[I][J] = cluster_int_events_mutex_transp[J][I]; + assign mutex_lock_req_transp[J][I] = mutex_lock_req[I][J]; + assign mutex_unlock_req_transp[J][I] = mutex_unlock_req[I][J]; + for ( K=0; K < MUTEX_MSG_W; K++ ) begin : EU_LOOP_HW_MUTEX_TRANSP_MSG + assign mutex_msg_wdata_transp[J][K][I] = mutex_msg_wdata[I][J][K]; + end + end + end + + for ( J=0; J < NB_HW_MUT; J++ ) begin : EU_LOOP_HW_MUTEX_REDUCE_STG1 + for ( K=0; K < MUTEX_MSG_W; K++ ) begin : EU_LOOP_HW_MUTEX_REDUCE_STG2 + assign mutex_msg_wdata_transp_red[J][K] = |mutex_msg_wdata_transp[J][K]; + end + end + endgenerate + + // dummy assignments + assign periph_int_bus[NB_CORES+NB_BARR+2].gnt = 1'b0; + assign periph_int_bus[NB_CORES+NB_BARR+2].r_opc = 1'b0; + assign periph_int_bus[NB_CORES+NB_BARR+2].r_valid = 1'b0; + assign periph_int_bus[NB_CORES+NB_BARR+2].r_rdata = '0; + assign periph_int_bus[NB_CORES+NB_BARR+2].r_id = '0; + + // will become the master port for cluster messages + assign message_master.wdata = '0; + assign message_master.req = 1'b0; + assign message_master.wen = 1'b1; + assign message_master.add = '0; + assign message_master.be = '0; + assign message_master.id = '0; + + + event_unit_interface_mux #( + .NB_CORES ( NB_CORES ), + .NB_BARR ( NB_BARR ) ) + event_unit_interface_mux_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .speriph_slave ( speriph_slave ), + .periph_int_bus_master ( periph_int_bus ), + + .demux_slave ( eu_direct_link ), + .demux_int_bus_core_master ( demux_int_bus_core ), + .demux_int_bus_barrier_master ( demux_int_bus_barrier ) + ); + + + interc_sw_evt_trig #( + .NB_CORES ( NB_CORES ), + .NB_SW_EVT ( NB_SW_EVT ) ) + interc_sw_evt_trig_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .sw_events_o ( interc_int_events_sw ), + + .periph_int_bus_slave ( periph_int_bus[NB_CORES+NB_BARR] ) + ); + + assign soc_periph_event = '0; + + generate + for ( I=0; I < NB_CORES; I++ ) begin : EU_CORE + event_unit_core #( + .NB_CORES ( NB_CORES ), + .NB_SW_EVT ( NB_SW_EVT ), + .NB_BARR ( NB_BARR ), + .NB_HW_MUT ( NB_HW_MUT ), + .MUTEX_MSG_W ( MUTEX_MSG_W ) ) + event_unit_core_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + + .master_event_lines_i ( cluster_int_events[I] ), + + .core_sw_events_o ( core_sw_events_transp[I][NB_SW_EVT-1:0] ), + .core_sw_events_mask_o ( core_sw_events_mask_transp[I][NB_CORES-1:0] ), + + .hw_barr_id_o ( hw_barr_trigger[I][NB_BARR-1:0] ), + + .mutex_rd_req_o ( mutex_lock_req[I] ), + .mutex_wr_req_o ( mutex_unlock_req[I] ), + .mutex_msg_wdata_o ( mutex_msg_wdata[I] ), + .mutex_msg_rdata_i ( mutex_msg_rdata ), + + .dispatch_pop_req_o ( disp_pop_req[I] ), + .dispatch_pop_ack_o ( disp_pop_ack[I] ), + .dispatch_value_i ( disp_value[I] ), + + .dispatch_w_req_o ( disp_w_req[I] ), + .dispatch_w_data_o ( disp_w_data[I] ), + .dispatch_reg_sel_o ( disp_reg_sel[I] ), + + .core_irq_req_o ( core_irq_req_o[I] ), + .core_irq_id_o ( core_irq_id_o[I] ), + .core_irq_ack_i ( core_irq_ack_i[I] ), + .core_irq_ack_id_i ( core_irq_ack_id_i[I] ), + + .core_busy_i ( core_busy_i[I] ), + .core_clock_en_o ( core_clock_en_o[I] ), + + .periph_int_bus_slave ( periph_int_bus[I] ), + .eu_direct_link_slave ( demux_int_bus_core[I] ) + ); + end + endgenerate + + + // instantiation of NB_BARR barrier units + generate + for ( I = 0; I < NB_BARR; I++ ) begin : HW_BARRIER_UNIT + hw_barrier_unit #( + .NB_CORES ( NB_CORES ) ) + hw_barrier_unit_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .barrier_trigger_core_i ( hw_barr_trigger_transp[I] ), + .barrier_status_o ( ), + .barrier_events_o ( cluster_int_events_barr_transp[I] ), + + .demux_bus_slaves ( demux_int_bus_barrier[(I+1)*NB_CORES-1:I*NB_CORES] ), + .periph_bus_slave ( periph_int_bus[NB_CORES+I] ) + ); + end + endgenerate + + + generate + for ( I=0; I < NB_HW_MUT; I++ ) begin : HW_MUT + hw_mutex_unit #( + .NB_CORES ( NB_CORES ), + .MUTEX_MSG_W ( MUTEX_MSG_W ) ) + hw_mutex_unit_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .lock_req_i ( mutex_lock_req_transp[I] ), + .unlock_req_i ( mutex_unlock_req_transp[I] ), + + .mutex_msg_wdata_i ( mutex_msg_wdata_transp_red[I] ), + .mutex_msg_rdata_o ( mutex_msg_rdata[I] ), + + .mutex_event_o ( cluster_int_events_mutex_transp[I] ) + ); + end + endgenerate + + hw_dispatch #( + .NB_CORES ( NB_CORES ), + .FIFO_DEPTH ( DISP_FIFO_DEPTH ) ) + hw_dispatch_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .pop_req_i ( disp_pop_req ), + .pop_ack_i ( disp_pop_ack ), + + .dispatch_value_o ( disp_value ), + + .w_req_i ( disp_w_req ), + .w_data_i ( disp_w_data ), + .reg_sel_i ( disp_reg_sel ), + + .dispatch_event_o ( cluster_int_events_dispatch ) + ); + +endmodule // event_unit_top diff --git a/hw/deps/event_unit_flex/hw_barrier_unit.sv b/hw/deps/event_unit_flex/hw_barrier_unit.sv new file mode 100644 index 0000000..2ef91d3 --- /dev/null +++ b/hw/deps/event_unit_flex/hw_barrier_unit.sv @@ -0,0 +1,225 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module hw_barrier_unit +#( + parameter NB_CORES = 4 +) +( + // clock and reset + input logic clk_i, + input logic rst_ni, + + // trigger inputs from all cores + input logic [NB_CORES-1:0] barrier_trigger_core_i, + // direct output of status reg for summary status computation in top level + output logic [NB_CORES-1:0] barrier_status_o, + // generated event, masked with target core mask -> to eu_matrix + output logic [NB_CORES-1:0] barrier_events_o, + + // demuxed slave ports from each core + XBAR_PERIPH_BUS.Slave demux_bus_slaves[NB_CORES-1:0], + // single plug from periph interconnect with pre-decoded requests + XBAR_PERIPH_BUS.Slave periph_bus_slave + + ); + + // actual registers + logic [NB_CORES-1:0] trigger_mask_DP, trigger_mask_DN; + logic [NB_CORES-1:0] target_mask_DP, target_mask_DN; + logic [NB_CORES-1:0] trigger_status_DP, trigger_status_DN; + + // combinational signals that need to be ORed in the end + logic [NB_CORES-1:0][NB_CORES-1:0] demux_wdata_trigger_mask, demux_wdata_target_mask; + logic [NB_CORES-1:0][NB_CORES-1:0] demux_wdata_trigger_mask_transp, demux_wdata_target_mask_transp; + logic [NB_CORES-1:0] demux_wdata_trigger_mask_red, demux_wdata_target_mask_red; + logic [NB_CORES+1:0][NB_CORES-1:0] trigger_matrix; // first NB_CORES rows for demuxed ports, then interc, then core_trigger + logic [NB_CORES-1:0][NB_CORES+1:0] trigger_matrix_transp; + logic [NB_CORES-1:0] trigger_matrix_red; + + logic [NB_CORES-1:0] demux_we_trigger_mask, demux_we_target_mask; + logic interc_we_trigger_mask, interc_we_target_mask; + logic [NB_CORES-1:0] demux_bus_req_all; + + // delayed read requests + logic [NB_CORES-1:0][1:0] demux_read_req_del_SP, demux_read_req_del_SN; + logic [1:0] interc_read_req_del_SP, interc_read_req_del_SN; + + logic interc_gnt_del_SP, interc_gnt_del_SN; + logic [NB_CORES-1:0] write_conflict; + + logic barrier_matched; + + genvar I,J; + + // calculation of outputs + assign barrier_status_o = trigger_status_DP; + assign barrier_matched = (trigger_mask_DP != '0) && (trigger_status_DP == trigger_mask_DP); + assign barrier_events_o = (barrier_matched == 1'b1) ? target_mask_DP : '0; + + // bus logic for demuxed ports - replicated NB_CORES times + generate + for ( I = 0; I < NB_CORES; I++ ) begin + // read/write logic for demuxed ports + always_comb begin + demux_we_trigger_mask[I] = 1'b0; + demux_we_target_mask[I] = 1'b0; + demux_read_req_del_SN[I] = 2'b00; + + demux_bus_slaves[I].r_rdata = '0; + demux_bus_slaves[I].r_opc = 1'b0; + demux_bus_slaves[I].r_id = '0; + demux_bus_slaves[I].gnt = 1'b1; + demux_bus_slaves[I].r_valid = 1'b1; + + trigger_matrix[I] = '0; + + if ( demux_bus_slaves[I].req == 1'b1 ) begin + if ( demux_bus_slaves[I].wen == 1'b1 ) begin + // minimal encoding of requested read data + case ( demux_bus_slaves[I].add[4:2] ) + 3'b000: demux_read_req_del_SN[I] = 2'b01; + 3'b001: demux_read_req_del_SN[I] = 2'b10; + 3'b011: demux_read_req_del_SN[I] = 2'b11; + endcase + end + else begin + case ( demux_bus_slaves[I].add[4:2] ) + 3'b000: demux_we_trigger_mask[I] = 1'b1; + 3'b011: demux_we_target_mask[I] = 1'b1; + 3'b100: trigger_matrix[I] = demux_bus_slaves[I].wdata[NB_CORES-1:0]; + endcase + end + end + // evaluate delayed read request + case ( demux_read_req_del_SP[I] ) + 2'b01: demux_bus_slaves[I].r_rdata[NB_CORES-1:0] = trigger_mask_DP; + 2'b10: demux_bus_slaves[I].r_rdata[NB_CORES-1:0] = trigger_status_DP; + 2'b11: demux_bus_slaves[I].r_rdata[NB_CORES-1:0] = target_mask_DP; + endcase + end + + // activation condition for read address + assign demux_bus_req_all[I] = demux_bus_slaves[I].req; + + // each bit represents a write collision between a demux and the interconnect port + assign write_conflict[I] = ( (demux_bus_slaves[I].req == 1'b1) && (periph_bus_slave.req == 1'b1) ) && + ( (demux_bus_slaves[I].wen == 1'b0) && (periph_bus_slave.wen == 1'b0) ) && + ( demux_bus_slaves[I].add == periph_bus_slave.add ); + // assignment of write data + assign demux_wdata_trigger_mask[I] = (demux_we_trigger_mask[I] == 1'b1) ? demux_bus_slaves[I].wdata[NB_CORES-1:0] : '0; + assign demux_wdata_target_mask[I] = (demux_we_target_mask[I] == 1'b1) ? demux_bus_slaves[I].wdata[NB_CORES-1:0] : '0; + for ( J = 0; J < NB_CORES; J++ ) begin + assign demux_wdata_trigger_mask_transp[J][I] = demux_wdata_trigger_mask[I][J]; + assign demux_wdata_target_mask_transp[J][I] = demux_wdata_target_mask[I][J]; + end + assign demux_wdata_trigger_mask_red[I] = |demux_wdata_trigger_mask_transp[I]; + assign demux_wdata_target_mask_red[I] = |demux_wdata_target_mask_transp[I]; + end + endgenerate + + // protocol logic for interconnect port - stall interconnect port on write conflict + assign interc_gnt_del_SN = periph_bus_slave.req && (|write_conflict == 1'b0); + assign periph_bus_slave.gnt = interc_gnt_del_SN; + assign periph_bus_slave.r_valid = interc_gnt_del_SP; + assign periph_bus_slave.r_opc = 1'b0; + assign periph_bus_slave.r_id = '0; + + // read/write logic for interconnect port + always_comb begin + interc_we_trigger_mask = 1'b0; + interc_we_target_mask = 1'b0; + interc_read_req_del_SN = 2'b0; + periph_bus_slave.r_rdata = '0; + trigger_matrix[NB_CORES] = '0; + + if ( periph_bus_slave.req == 1'b1 ) begin + if ( periph_bus_slave.wen == 1'b1 ) begin + case ( periph_bus_slave.add[4:2] ) + 3'b000: interc_read_req_del_SN = 2'b01; + 3'b001: interc_read_req_del_SN = 2'b10; + 3'b011: interc_read_req_del_SN = 2'b11; + endcase + end + else begin + case ( periph_bus_slave.add[4:2] ) + 3'b000: interc_we_trigger_mask = 1'b1; + 3'b011: interc_we_target_mask = 1'b1; + 3'b100: trigger_matrix[NB_CORES] = periph_bus_slave.wdata[NB_CORES-1:0]; + endcase + end + end + // evaluate delayed read request + case ( interc_read_req_del_SP ) + 2'b01: periph_bus_slave.r_rdata[NB_CORES-1:0] = trigger_mask_DP; + 2'b10: periph_bus_slave.r_rdata[NB_CORES-1:0] = trigger_status_DP; + 2'b11: periph_bus_slave.r_rdata[NB_CORES-1:0] = target_mask_DP; + endcase + end + + // combination of all trigger signals and status clear logic + assign trigger_matrix[NB_CORES+1] = barrier_trigger_core_i; + generate + for ( I = 0; I < NB_CORES; I++ ) begin + for ( J = 0; J < NB_CORES+2; J++ ) assign trigger_matrix_transp[I][J] = trigger_matrix[J][I]; + assign trigger_matrix_red[I] = |trigger_matrix_transp[I]; + end + endgenerate + assign trigger_status_DN = (barrier_matched == 1'b1) ? '0 : (trigger_status_DP | trigger_matrix_red); + + // summarization of write data for trigger and target masks + always_comb begin + trigger_mask_DN = trigger_mask_DP; + target_mask_DN = target_mask_DP; + + if ( demux_we_trigger_mask != '0 ) + trigger_mask_DN = demux_wdata_trigger_mask_red; + else if ( interc_we_trigger_mask == 1'b1 ) + trigger_mask_DN = periph_bus_slave.wdata[NB_CORES-1:0]; + + if ( demux_we_target_mask != '0 ) + target_mask_DN = demux_wdata_target_mask_red; + else if ( interc_we_target_mask == 1'b1 ) + target_mask_DN = periph_bus_slave.wdata[NB_CORES-1:0]; + end + + always_ff @(posedge clk_i, negedge rst_ni) + begin + if ( rst_ni == 1'b0 ) + begin + trigger_mask_DP <= '0; + target_mask_DP <= '0; + trigger_status_DP <= '0; + demux_read_req_del_SP <= '0; + interc_read_req_del_SP <= '0; + interc_gnt_del_SP <= '0; + end + else + begin + trigger_mask_DP <= trigger_mask_DN; + target_mask_DP <= target_mask_DN; + + if((barrier_matched == 1'b1)) + trigger_status_DP <= '0; + else if(|trigger_matrix_red) + trigger_status_DP <= (trigger_status_DP | trigger_matrix_red); + + + if ( |demux_bus_req_all ) begin + demux_read_req_del_SP <= demux_read_req_del_SN; + end + if ( periph_bus_slave.req ) begin + interc_read_req_del_SP <= interc_read_req_del_SN; + interc_gnt_del_SP <= interc_gnt_del_SN; + end + end + end + +endmodule // hw_barrier_unit diff --git a/hw/deps/event_unit_flex/hw_dispatch.sv b/hw/deps/event_unit_flex/hw_dispatch.sv new file mode 100644 index 0000000..7f2a19d --- /dev/null +++ b/hw/deps/event_unit_flex/hw_dispatch.sv @@ -0,0 +1,179 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module hw_dispatch +#( + parameter NB_CORES = 4, + parameter FIFO_DEPTH = 4 +) +( + // clock and reset + input logic clk_i, + input logic rst_ni, + + // pop request and ack from each core + input logic [NB_CORES-1:0] pop_req_i, + input logic [NB_CORES-1:0] pop_ack_i, + // current read data for each core + output logic [NB_CORES-1:0][31:0] dispatch_value_o, + + // value push and team configuration by master + input logic [NB_CORES-1:0] w_req_i, + input logic [NB_CORES-1:0][31:0] w_data_i, + input logic [NB_CORES-1:0][1:0] reg_sel_i, + + // event output to flag availability of a value to a specific core + output logic [NB_CORES-1:0] dispatch_event_o + +); + + // registers + logic [FIFO_DEPTH-1:0][31:0] dispatch_fifo_DP, dispatch_fifo_DN; + + logic [NB_CORES-1:0] core_set_conf_DP, core_set_conf_DN; + logic [NB_CORES-1:0] req_in_progr_SP, req_in_progr_SN; + logic [NB_CORES-1:0] incr_rptr_del_SP, incr_rptr_del_SN; + + logic [FIFO_DEPTH-1:0][NB_CORES-1:0] core_set_stat_DP, core_set_stat_DN; + + logic [NB_CORES-1:0][$clog2(FIFO_DEPTH)-1:0] read_ptr_DP, read_ptr_DN; + logic [$clog2(FIFO_DEPTH)-1:0] write_ptr_DP, write_ptr_DN; + + // internal signals + logic [NB_CORES-1:0][1:0][31:0] w_data_int; + logic [1:0][31:0][NB_CORES-1:0] w_data_int_transp; + logic [1:0][31:0] w_data_int_red; + logic [1:0][NB_CORES-1:0] w_req_int; + + logic [NB_CORES-1:0][FIFO_DEPTH-1:0] clr_core_stat; + logic [FIFO_DEPTH-1:0][NB_CORES-1:0] clr_core_stat_transp; + + genvar I,J,K; + + // workaround for language limitation + generate + for (I=0; I CH0; 1 --> CH1 + always_comb + begin + request_o = request_ch0_i | request_ch1_i; + ch_selector = ~request_ch0_i | ( Flag_i & request_ch1_i ); + grant_ch0_o = (( request_ch0_i & ~request_ch1_i) | ( request_ch0_i & ~Flag_i)) & grant_i; + grant_ch1_o = ((~request_ch0_i & request_ch1_i) | ( request_ch1_i & Flag_i)) & grant_i; + case(ch_selector) + 1'b1: begin address_o = address_ch1_i; UID_o = UID_ch1_i; end + 1'b0: begin address_o = address_ch0_i; UID_o = UID_ch0_i; end + endcase + end + +endmodule diff --git a/hw/deps/icache-intc/RoutingBlock_Req_icache_intc.sv b/hw/deps/icache-intc/RoutingBlock_Req_icache_intc.sv new file mode 100644 index 0000000..a50a058 --- /dev/null +++ b/hw/deps/icache-intc/RoutingBlock_Req_icache_intc.sv @@ -0,0 +1,94 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 22/01/2018 // +// Design Name: icache_intc // +// Module Name: RoutingBlock_Req_icache_intc.sv // +// Project Name: MrWolf // +// Language: SystemVerilog // +// // +// Description: Block that embeds the arbitration/routing tree and the // +// decoding logic for the response coming from the memory side // +// // +// Revision v0.1 - 16/02/2018 : File Created // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +module RoutingBlock_Req_icache_intc +#( + parameter int unsigned ADDRESS_WIDTH = 32, + parameter int unsigned N_CORES = 16, + parameter int unsigned UID_WIDTH = N_CORES, + parameter int unsigned N_CACHE_BANKS = 8, + parameter int unsigned DATA_WIDTH = 32 +) +( + input logic clk_i, + input logic rst_ni, + + output logic request_o, + output logic [ADDRESS_WIDTH-1:0] address_o, + output logic [UID_WIDTH-1:0] UID_o, + input logic grant_i, + + input logic [N_CORES-1:0] request_i, + input logic [N_CORES-1:0][ADDRESS_WIDTH-1:0] address_i, + input logic [N_CORES-1:0][UID_WIDTH-1:0] UID_i, + output logic [N_CORES-1:0] grant_o, + + input logic response_i, + input logic [UID_WIDTH-1:0] response_UID_i, + output logic [N_CORES-1:0] response_o +); + assign response_o = {UID_WIDTH{response_i}} & response_UID_i; + + generate + if(N_CORES > 1) + begin : MULTI_CORE + DistributedArbitrationNetwork_Req_icache_intc #( .ADDRESS_WIDTH (ADDRESS_WIDTH), .UID_WIDTH(UID_WIDTH), .N_CORES(N_CORES) ) DistributedArbitrationNetwork_Req_icache_intc_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .request_i ( request_i ), + .address_i ( address_i ), + .UID_i ( UID_i ), + .grant_o ( grant_o ), + .request_o ( request_o ), + .address_o ( address_o ), + .UID_o ( UID_o ), + .grant_i ( grant_i ) + ); + end + else + begin : SINGLE_CORE + assign request_o = request_i; + assign address_o = address_i; + assign UID_o = UID_i; + assign grant_o = grant_i; + end + endgenerate + +endmodule diff --git a/hw/deps/icache-intc/RoutingBlock_Resp_icache_intc.sv b/hw/deps/icache-intc/RoutingBlock_Resp_icache_intc.sv new file mode 100644 index 0000000..b98c01f --- /dev/null +++ b/hw/deps/icache-intc/RoutingBlock_Resp_icache_intc.sv @@ -0,0 +1,86 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 22/01/2018 // +// Design Name: icache_intc // +// Module Name: RoutingBlock_Resp_icache_intc.sv // +// Project Name: MrWolf // +// Language: SystemVerilog // +// // +// Description: Block that embeds the routing tree for the response side // +// and the decoding logic for the request coming from the // +// fetch side. // +// // +// Revision v0.1 - 16/02/2018 : File Created // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +module RoutingBlock_Resp_icache_intc +#( + parameter int unsigned UID_WIDTH = 8, + parameter int unsigned UID = 1, + parameter int unsigned N_CACHE_BANKS = 16, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned DEST_WIDTH = 1 +) +( + input logic [N_CACHE_BANKS-1:0] response_i, + input logic [N_CACHE_BANKS-1:0][DATA_WIDTH-1:0] read_data_i, + + output logic response_o, + output logic [DATA_WIDTH-1:0] read_data_o, + + input logic request_i, + input logic [DEST_WIDTH-1:0] destination_i, + output logic grant_o, + + output logic [N_CACHE_BANKS-1:0] request_o, + input logic [N_CACHE_BANKS-1:0] grant_i, + output logic [UID_WIDTH-1:0] UID_o +); + typedef logic [UID_WIDTH-1:0] logic_uid_type; + + DistributedArbitrationNetwork_Resp_icache_intc #( .N_CACHE_BANKS(N_CACHE_BANKS), .DATA_WIDTH(DATA_WIDTH) ) DistributedArbitrationNetwork_Resp_icache_intc_i + ( + .response_i ( response_i ), + .read_data_i ( read_data_i ), + .response_o ( response_o ), + .read_data_o ( read_data_o ) + ); + + + // Decoding Logic + always @(*) + begin + request_o = '0; + request_o [destination_i] = request_i; + grant_o = grant_i[destination_i]; + UID_o = logic_uid_type'(UID); + end + + + +endmodule diff --git a/hw/deps/icache-intc/icache_intc.sv b/hw/deps/icache-intc/icache_intc.sv new file mode 100644 index 0000000..2d36a1c --- /dev/null +++ b/hw/deps/icache-intc/icache_intc.sv @@ -0,0 +1,170 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 22/01/2018 // +// Design Name: icache_intc // +// Module Name: icache_intc.sv // +// Project Name: MrWolf // +// Language: SystemVerilog // +// // +// Description: top_level, that instanciates the routing and response // +// blocks. It is fully parametric, and it is possible to // +// to have N+M Channels where M and N are integers, powerof 2 // +// fair arbitration is provided through distrubuted Round // +// robin arbiters. // +// // +// Revision: // +// Revision v0.1 - 16/02/2018 : File Created // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + + +module icache_intc +#( + parameter ADDRESS_WIDTH = 32, + parameter N_CORES = 8, + parameter N_AUX_CHANNEL = 0, + parameter UID_WIDTH = N_CORES+N_AUX_CHANNEL, + parameter DATA_WIDTH = 32, + parameter N_CACHE_BANKS = 16, + parameter OFFSET = $clog2(DATA_WIDTH)-3 +) +( + input logic clk_i, + input logic rst_ni, + + input logic [N_CORES+N_AUX_CHANNEL-1:0] request_i, + input logic [N_CORES+N_AUX_CHANNEL-1:0][ADDRESS_WIDTH-1:0] address_i, + output logic [N_CORES+N_AUX_CHANNEL-1:0] grant_o, + output logic [N_CORES+N_AUX_CHANNEL-1:0] response_o, + output logic [N_CORES+N_AUX_CHANNEL-1:0][DATA_WIDTH-1:0] read_data_o, + + output logic [N_CACHE_BANKS-1:0] request_o, + output logic [N_CACHE_BANKS-1:0][ADDRESS_WIDTH-1:0] address_o, + output logic [N_CACHE_BANKS-1:0][UID_WIDTH-1:0] UID_o, + input logic [N_CACHE_BANKS-1:0] grant_i, + + input logic [N_CACHE_BANKS-1:0][DATA_WIDTH-1:0] read_data_i, + input logic [N_CACHE_BANKS-1:0] response_i, + input logic [N_CACHE_BANKS-1:0][UID_WIDTH-1:0] response_UID_i +); + localparam DEST_WIDTH = (N_CACHE_BANKS == 1) ? 1'b1 : $clog2(N_CACHE_BANKS); + + logic [N_CORES+N_AUX_CHANNEL-1:0][UID_WIDTH-1:0] UID_int; + logic [N_CORES+N_AUX_CHANNEL-1:0] grant_from_CB [N_CACHE_BANKS-1:0]; + + logic [N_CACHE_BANKS-1:0] request_from_CORE [N_CORES+N_AUX_CHANNEL-1:0]; + logic [N_CORES+N_AUX_CHANNEL-1:0] response_from_CB [N_CACHE_BANKS-1:0]; + logic [N_CACHE_BANKS-1:0] response_to_CORE [N_CORES+N_AUX_CHANNEL-1:0]; + logic [N_CORES+N_AUX_CHANNEL-1:0] request_to_CB [N_CACHE_BANKS-1:0]; + logic [N_CACHE_BANKS-1:0] grant_to_CORE [N_CORES+N_AUX_CHANNEL-1:0]; + logic [N_CORES+N_AUX_CHANNEL-1:0][DEST_WIDTH-1:0] destination; + + genvar j,k; + generate + for (k=0; k TAG SCM Unified PORT + output logic SCM_TAG_write_req_o, + output logic [SCM_ADDR_WIDTH-1:0] SCM_TAG_write_addr_o, + output logic [$clog2(NB_BANKS)-1:0] SCM_TAG_write_dest_o, + output logic [SCM_TAG_WIDTH-1:0] SCM_TAG_write_wdata_o, + output logic [NB_WAYS-1:0] SCM_TAG_write_way_o, + + // interface with WRITE PORT --> DATA SCM Unified PORT + output logic SCM_DATA_write_req_o, + output logic [SCM_ADDR_WIDTH-1:0] SCM_DATA_write_addr_o, // double number of rows with respect TAG SCM ARRAY + output logic [$clog2(NB_BANKS)-1:0] SCM_DATA_write_dest_o, + output logic [SCM_DATA_WIDTH-1:0] SCM_DATA_write_wdata_o, + output logic [NB_WAYS-1:0] SCM_DATA_write_way_o, + + //AXI read address bus ------------------------------------------- + output logic [AXI_ID-1:0] axi_master_arid_o, + output logic [AXI_ADDR-1:0] axi_master_araddr_o, + output logic [7:0] axi_master_arlen_o, //burst length - 1 to 16 + output logic [2:0] axi_master_arsize_o, //size of each transfer in burst + output logic [1:0] axi_master_arburst_o, //for bursts>1, accept only incr burst=01 + output logic axi_master_arlock_o, //only normal access supported axs_awlock=00 + output logic [3:0] axi_master_arcache_o, + output logic [2:0] axi_master_arprot_o, + output logic [3:0] axi_master_arregion_o, // + output logic [AXI_USER-1:0] axi_master_aruser_o, // + output logic [3:0] axi_master_arqos_o, // + output logic axi_master_arvalid_o, //master addr valid + input logic axi_master_arready_i, //slave ready to accept + // --------------------------------------------------------------- + + + //AXI BACKWARD read data bus ---------------------------------------------- + input logic [AXI_ID-1:0] axi_master_rid_i, + input logic [AXI_DATA-1:0] axi_master_rdata_i, + input logic [1:0] axi_master_rresp_i, + input logic axi_master_rlast_i, //last transfer in burst + input logic [AXI_USER-1:0] axi_master_ruser_i, + input logic axi_master_rvalid_i, //slave data valid + output logic axi_master_rready_o //master ready to accept +); + + localparam DEPTH = NB_CORES; + localparam LOG2_DEPTH = $clog2(DEPTH); + + // FSM State declaration + enum logic {IDLE_COMP, DISP_COMP } CS_COMP, NS_COMP; + + // interface with CTRL WRITE PORT --> SCM DATA + logic ctrl_SCM_write_req; + logic [$clog2(NB_BANKS)-1:0] ctrl_SCM_write_dest; + logic [SCM_ADDR_WIDTH-1:0] ctrl_SCM_write_addr; + logic [SCM_TAG_WIDTH-1:0] ctrl_SCM_write_wdata; + logic [NB_WAYS-1:0] ctrl_SCM_write_way; + + // interface with REFILL WRITE PORT --> SCM DATA + logic refill_TAG_SCM_write_req; + logic [$clog2(NB_BANKS)-1:0] refill_TAG_SCM_write_dest; + logic [SCM_ADDR_WIDTH-1:0] refill_TAG_SCM_write_addr; + logic [SCM_TAG_WIDTH-1:0] refill_TAG_SCM_write_wdata; + logic [NB_WAYS-1:0] refill_TAG_SCM_write_way; + + // interface with REFILL WRITE PORT --> SCM DATA + logic refill_DATA_SCM_write_req; + logic [$clog2(NB_BANKS)-1:0] refill_DATA_SCM_write_dest; + logic [SCM_ADDR_WIDTH:0] refill_DATA_SCM_write_addr; + logic [SCM_DATA_WIDTH-1:0] refill_DATA_SCM_write_wdata; + logic [NB_WAYS-1:0] refill_DATA_SCM_write_way; + + + + logic [NB_WAYS-1:0] refill_way_int; + logic [FETCH_ADDR_WIDTH-1:0] refill_address_int; + + + logic fetch_req_int; + logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_int; + logic [NB_WAYS-1:0] fetch_way_int; + + logic [NB_CORES-1:0] fetch_ID_OH_int; // ID is one hot --> NB_CORES bit + logic [$clog2(NB_CORES)-1:0] fetch_ID_BIN_int; // ID is one hot --> NB_CORES bit + logic fetch_gnt_int; + + logic fetch_rvalid_int; + logic [FETCH_DATA_WIDTH-1:0] fetch_rdata_int; + logic [NB_CORES:0] fetch_rID_OH_int; // ID is one hot --> NB_CORES bit + + logic [NB_CORES-1:0][FETCH_ADDR_WIDTH+NB_WAYS-1:0] compact_data_add_i; + + logic [$clog2(FETCH_DATA_WIDTH/AXI_DATA)-1:0] rel_chunk_CS, rel_chunk_NS; + logic [FETCH_DATA_WIDTH/AXI_DATA-1:0][AXI_DATA-1:0] axi_master_rdata_int; + logic [AXI_ID-1:0] axi_master_rid_int; + logic axi_master_rvalid_int; + logic sample_rdata; + + logic fetch_rvalid_core, fetch_rvalid_pf; + logic fetch_req_muxed; + logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_muxed; + logic [NB_WAYS-1:0] fetch_way_muxed; + logic fetch_gnt_muxed; + logic [NB_CORES:0] fetch_ID_OH_muxed; // ID is one hot --> NB_CORES bit + logic [$clog2(NB_CORES+1)-1:0] fetch_ID_BIN_muxed; // ID is one hot --> NB_CORES bit + + + // Compact data sent along the address of the LOG interco: { FETCH_WAY, FETCH_ADDR } + genvar i; + generate + for(i=0; i SCM Unified PORT + .SCM_TAG_write_req_o ( SCM_TAG_write_req_o ), + .SCM_TAG_write_addr_o ( SCM_TAG_write_addr_o ), + .SCM_TAG_write_dest_o ( SCM_TAG_write_dest_o ), + .SCM_TAG_write_wdata_o ( SCM_TAG_write_wdata_o ), + .SCM_TAG_write_way_o ( SCM_TAG_write_way_o ), + + // interface with WRITE PORT --> SCM Unified PORT + .SCM_DATA_write_req_o ( SCM_DATA_write_req_o ), + .SCM_DATA_write_addr_o ( SCM_DATA_write_addr_o ), // DATA SCM has double number of rows + .SCM_DATA_write_dest_o ( SCM_DATA_write_dest_o ), + .SCM_DATA_write_wdata_o ( SCM_DATA_write_wdata_o ), + .SCM_DATA_write_way_o ( SCM_DATA_write_way_o ) + ); + if (AXI_ADDR > FETCH_ADDR_WIDTH) begin : gen_zero_extend_araddr + assign axi_master_araddr_o[AXI_ADDR-1:FETCH_ADDR_WIDTH] = '0; + end + + //always accept read data + assign axi_master_rready_o = 1'b1; + assign axi_master_arlen_o = 8'h01; // FIXME for different cache line sizes + assign axi_master_arsize_o = 3'b011; // FIXME for different cache line sizes + assign axi_master_arburst_o = 2'b01; //for bursts>1, accept only incr burst=01 + assign axi_master_arlock_o = 1'b0; //only normal access supported axs_awlock=00 + assign axi_master_arcache_o = 4'b0000; + assign axi_master_arprot_o = 3'b000; + assign axi_master_arregion_o = '0; + assign axi_master_aruser_o = '0; + assign axi_master_arqos_o = 4'b0000; + + + + onehot_to_bin #( .ONEHOT_WIDTH(NB_CORES+1) ) ID_OH_to_BIN (.onehot(fetch_ID_OH_muxed), .bin(fetch_ID_BIN_muxed) ); + + ///////////////////////////////////////////////////////////////////////////////////////////////////////// + // █████╗ ██╗ ██╗██╗ ███████╗██╗███████╗███████╗ ██████╗ ██████╗ ███╗ ██╗██╗ ██╗ /// + // ██╔══██╗╚██╗██╔╝██║ ██╔════╝██║╚══███╔╝██╔════╝ ██╔════╝██╔═══██╗████╗ ██║██║ ██║ /// + // ███████║ ╚███╔╝ ██║ ███████╗██║ ███╔╝ █████╗ ██║ ██║ ██║██╔██╗ ██║██║ ██║ /// + // ██╔══██║ ██╔██╗ ██║ ╚════██║██║ ███╔╝ ██╔══╝ ██║ ██║ ██║██║╚██╗██║╚██╗ ██╔╝ /// + // ██║ ██║██╔╝ ██╗██║███████╗███████║██║███████╗███████╗███████╗╚██████╗╚██████╔╝██║ ╚████║ ╚████╔╝ /// + // ╚═╝ ╚═╝╚═╝ ╚═╝╚═╝╚══════╝╚══════╝╚═╝╚══════╝╚══════╝╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═══╝ ╚═══╝ /// + ///////////////////////////////////////////////////////////////////////////////////////////////////////// + // AXI COMPACTOR 64 bit to 128 bit!!! Data comes back as 64 bit chunks. + // This logic creates atomic responses (same with as the cache line size --> 128bit ) + always_ff @(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + CS_COMP <= IDLE_COMP; + rel_chunk_CS <= '0; + + axi_master_rdata_int <= '0; + axi_master_rid_int <= '0; + end + else + begin + CS_COMP <= NS_COMP; + rel_chunk_CS <= rel_chunk_NS; + + if(sample_rdata) + begin + axi_master_rdata_int[rel_chunk_CS] <= axi_master_rdata_i; + axi_master_rid_int <= axi_master_rid_i; + end + + end + end + + assign sample_rdata = axi_master_rvalid_i; + + always_comb + begin + rel_chunk_NS = rel_chunk_CS; + NS_COMP = CS_COMP; + + case (CS_COMP) + IDLE_COMP: + begin + axi_master_rvalid_int = 1'b0; + + if(axi_master_rvalid_i) + begin + if(axi_master_rlast_i) + begin + NS_COMP = DISP_COMP; + rel_chunk_NS = '0; + end + else + begin + NS_COMP = IDLE_COMP; + rel_chunk_NS = rel_chunk_CS + 1'b1; + end + end + else + begin + NS_COMP = IDLE_COMP; + rel_chunk_NS = rel_chunk_CS; + end + + end + + DISP_COMP: + begin + axi_master_rvalid_int = 1'b1; + NS_COMP = IDLE_COMP; + + if(axi_master_rvalid_i) + begin + if(axi_master_rlast_i) + begin + NS_COMP = DISP_COMP; + rel_chunk_NS = '0; + end + else + begin + NS_COMP = IDLE_COMP; + rel_chunk_NS = 1; + end + end + else + begin + NS_COMP = IDLE_COMP; + rel_chunk_NS = '0; + end + end + + default: + begin + NS_COMP = IDLE_COMP; + end + endcase + + end + + + +endmodule diff --git a/hw/deps/icache_mp_128_pf/RTL/central_controller_128.sv b/hw/deps/icache_mp_128_pf/RTL/central_controller_128.sv new file mode 100644 index 0000000..e158a1c --- /dev/null +++ b/hw/deps/icache_mp_128_pf/RTL/central_controller_128.sv @@ -0,0 +1,508 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 22/01/2018 // +// Design Name: ICACHE_MP_128_PF // +// Module Name: central_controller_128 // +// Project Name: MrWolf // +// Language: SystemVerilog // +// // +// Description: This block represents the master cache controller that // +// receives the requests (multiplexed) from different cache // +// banks or HW prefetchre and checks if there are pending // +// refill on that cache line, it also handles the writes on // +// tag and data arrays. // +// // +// // +// Revision: // +// Revision v0.1 - 22/01/2018 : File Created // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + + +module central_controller_128 +#( + parameter ID_WIDTH = 9, + parameter LOG2_ID_WIDTH = $clog2(ID_WIDTH), + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 128, + parameter DEPTH = 16, + parameter LOG2_DEPTH = $clog2(DEPTH), + + parameter SCM_ADDR_WIDTH = 6, + parameter SCM_TAG_WIDTH = 6, + parameter SCM_DATA_WIDTH = 128, + parameter NB_BANKS = 4, + parameter NB_WAYS = 4, + parameter NB_CORES = 8, + + parameter ADDR_CHECK_LSB = 4, + parameter ADDR_CHECK_MSB = ADDR_WIDTH-1, + + parameter ID_LSB = 6, + parameter ID_MSB = 11, + parameter TAG_LSB = 12, + parameter TAG_MSB = SCM_TAG_WIDTH+TAG_LSB-2, + parameter DEST_LSB = 4, + parameter DEST_MSB = 5 +) +( + input logic clk, + input logic rst_n, + input logic test_en_i, + + input logic bypass_icache_i, + output logic cache_bypassed_o, + input logic [NB_CORES:0] bypass_status_i, + + input logic flush_icache_i, + output logic flush_ack_o, + + input logic sel_flush_req_i, + input logic [ADDR_WIDTH-1:0] sel_flush_addr_i, + output logic sel_flush_ack_o, + + output logic empty_fifo_o, + output logic [ID_WIDTH-1:0] retry_fetch_o, + + + output logic [ID_WIDTH-1:0] notify_refill_done_o, + + + input logic fetch_req_i, + input logic [LOG2_ID_WIDTH-1:0] fetch_ID_BIN_i, + input logic [ID_WIDTH-1:0] fetch_ID_OH_i, + input logic [ADDR_WIDTH-1:0] fetch_addr_i, + input logic [NB_WAYS-1:0] fetch_way_i, + output logic fetch_gnt_o, + + output logic fetch_rvalid_o, + output logic [DATA_WIDTH-1:0] fetch_rdata_o, + output logic [ID_WIDTH-1:0] fetch_rID_o, + + + + output logic AXI_req_o, + output logic [ADDR_WIDTH-1:0] AXI_addr_o, + output logic [LOG2_DEPTH-1:0] AXI_ID_o, + input logic AXI_gnt_i, + + input logic AXI_rvalid_i, + input logic [LOG2_DEPTH-1:0] AXI_rID_i, + input logic [DATA_WIDTH-1:0] AXI_rdata_i, + + output logic SCM_TAG_write_req_o, + output logic [SCM_ADDR_WIDTH-1:0] SCM_TAG_write_addr_o, + output logic [$clog2(NB_BANKS)-1:0] SCM_TAG_write_dest_o, + output logic [SCM_TAG_WIDTH-1:0] SCM_TAG_write_wdata_o, + output logic [NB_WAYS-1:0] SCM_TAG_write_way_o, + + // interface with WRITE PORT --> SCM Unified PORT + output logic SCM_DATA_write_req_o, + output logic [SCM_ADDR_WIDTH-1:0] SCM_DATA_write_addr_o, // DATA SCM has double number of rows + output logic [$clog2(NB_BANKS)-1:0] SCM_DATA_write_dest_o, + output logic [SCM_DATA_WIDTH-1:0] SCM_DATA_write_wdata_o, + output logic [NB_WAYS-1:0] SCM_DATA_write_way_o + +); + + // STATE ENCODING + enum logic [2:0] {INVALIDATE, BYPASSED, WAIT_EMPTY_BYPASS_FIFO, ENABLED, GOING_BYPASS, FLUSH_SET_ID } CS, NS; + + // signals declaration + logic [$clog2(NB_BANKS)+SCM_ADDR_WIDTH-1:0] counter_CS, counter_NS; + + logic CAM_empty; + //TO REFILL CAM + logic CAM_grant; + logic CAM_fetch_req; + // From CAM to AXI MUX + logic CAM_AXI_req; + logic [ADDR_WIDTH-1:0] CAM_AXI_addr; + logic [LOG2_DEPTH-1:0] CAM_AXI_ID; + + // for refill PURPOSE ONLY + logic [ADDR_WIDTH-1:0] CAM_refill_addr; + logic [ID_WIDTH-1:0] CAM_refill_ID; + logic [NB_WAYS-1:0] CAM_refill_way; + + logic fifo_rel_chunk_gnt; + logic fifo_rel_chunk_valid; + + // Notify to different cache bank as soon the refill is committed in the DAT/TAG. + // A new fetch attempt will be performed + assign notify_refill_done_o = (~cache_bypassed_o & AXI_rvalid_i) ? CAM_refill_ID : '0; + + // CS and Counters Flip Flops + always_ff @(posedge clk or negedge rst_n) + begin : Seq_CS_counters + if(~rst_n) + begin + CS <= INVALIDATE; + counter_CS <= '0; + end + else + begin + CS <= NS; + counter_CS <= counter_NS; + end + end + + + always_comb + begin : Comb_logic_main_FSM + + // Default values for FSM outputs + NS = CS; + counter_NS = counter_CS; + + fetch_gnt_o = 1'b0; + + fetch_rvalid_o = 1'b0; + + fetch_rdata_o = AXI_rdata_i; + fetch_rID_o = 1< sel_flush_addr_i[ID_MSB:ID_LSB]; + SCM_TAG_write_req_o = 1'b1; + SCM_TAG_write_addr_o = sel_flush_addr_i[ID_MSB:ID_LSB]; + SCM_TAG_write_dest_o = sel_flush_addr_i[DEST_MSB:DEST_LSB]; + SCM_TAG_write_wdata_o = '0; + SCM_TAG_write_way_o = '1; + cache_bypassed_o = 1'b0; + + sel_flush_ack_o = 1'b1; + + // at any point in time check if there are Bypass request. + // In case, just serve it and go in the proper state + if(bypass_icache_i) + NS = BYPASSED; + else + NS = ENABLED; + end + + + // State used to invalidate the cache + INVALIDATE: + begin + // Invalidate all cache Lines + SCM_TAG_write_req_o = 1'b1; + SCM_TAG_write_addr_o = counter_CS[SCM_ADDR_WIDTH-1:0]; + SCM_TAG_write_dest_o = counter_CS[$clog2(NB_BANKS)+SCM_ADDR_WIDTH-1:SCM_ADDR_WIDTH]; + SCM_TAG_write_wdata_o = '0; + SCM_TAG_write_way_o = '1; + cache_bypassed_o = 1'b1; + + // Iterate on all cache lines (not in parallel, one cache line at the time) + if(counter_CS < NB_BANKS * (2**SCM_ADDR_WIDTH) -1 ) + begin + NS = INVALIDATE; + counter_NS = counter_CS + 1'b1; + end + else + begin + flush_ack_o = 1'b1; + + if(bypass_icache_i) + NS = BYPASSED; + else + NS = ENABLED; + + counter_NS = '0; + end + end + + //Main state for cache bypassed (not enabled). + BYPASSED: + begin + cache_bypassed_o = 1'b1; + flush_ack_o = 1'b1; + sel_flush_ack_o = 1'b1; + + fetch_rvalid_o = AXI_rvalid_i; + fetch_gnt_o = AXI_gnt_i & fifo_rel_chunk_gnt; + + AXI_req_o = fetch_req_i & fifo_rel_chunk_gnt; + AXI_addr_o = fetch_addr_i & 32'hFFFF_FFF0; // Mast bits from [3:0] --> 128 bit access + + // DEPTH > ID_WIDTH + if(LOG2_DEPTH == LOG2_ID_WIDTH) + AXI_ID_o = fetch_ID_BIN_i; + else + AXI_ID_o = { {(LOG2_DEPTH-LOG2_ID_WIDTH){1'b0}} , fetch_ID_BIN_i}; + + + + // Check if there is a bypass req, a flush or a selective FLush + // If one of these signals is 1, then thre is nothing to do + // cache is already bypassed, so flush or selective flush does + // not perform any further action. + if(bypass_icache_i) + NS = BYPASSED; + else + NS = WAIT_EMPTY_BYPASS_FIFO; + end + + + // Stay in this state untill the + WAIT_EMPTY_BYPASS_FIFO: + begin + cache_bypassed_o = 1'b1; + + fetch_rvalid_o = AXI_rvalid_i; + + + fetch_gnt_o = 1'b0; + if(fifo_rel_chunk_valid == 1'b0) // no longer transactions in the BYPASS FIFO. + begin + NS = INVALIDATE; + end + else + begin + NS = WAIT_EMPTY_BYPASS_FIFO; + end + end + + + // Main State When cache is Enabled + ENABLED: + begin + cache_bypassed_o = 1'b0; + + AXI_req_o = CAM_AXI_req; + AXI_addr_o = CAM_AXI_addr; + AXI_ID_o = CAM_AXI_ID; + + fetch_gnt_o = CAM_grant; + fetch_rvalid_o = 1'b0; + + + // Check if there is a bypass req, a flush or a selective FLush + // If one of these signals is 1, then the controller performs the + // right action + if( bypass_icache_i | flush_icache_i | sel_flush_req_i ) + begin + NS = GOING_BYPASS; + end + else + begin + NS = ENABLED ; + end + + + + // Handle teh Backwrite of the refill in the SCM banks + SCM_DATA_write_way_o = CAM_refill_way; + SCM_DATA_write_addr_o = CAM_refill_addr[ID_MSB:ID_LSB]; + SCM_DATA_write_dest_o = CAM_refill_addr[DEST_MSB:DEST_LSB] ; + SCM_DATA_write_wdata_o = AXI_rdata_i; + + SCM_TAG_write_way_o = CAM_refill_way; + SCM_TAG_write_addr_o = CAM_refill_addr[ID_MSB:ID_LSB]; + SCM_TAG_write_dest_o = CAM_refill_addr[DEST_MSB:DEST_LSB]; + + if(AXI_rvalid_i) + begin + SCM_DATA_write_req_o = ~cache_bypassed_o; + SCM_TAG_write_req_o = ~cache_bypassed_o; + SCM_TAG_write_wdata_o = {1'b1, CAM_refill_addr[TAG_MSB:TAG_LSB]}; + end + else // AXI_rvalid_i == 0 + begin + SCM_DATA_write_req_o = '0; + SCM_TAG_write_req_o = '0; + SCM_TAG_write_wdata_o = '0; + end + + end + + // Cache is Enabled but there was a Request to Disable, + // Empty the refill storage before switching + GOING_BYPASS: + begin + fetch_gnt_o = 1'b0; + cache_bypassed_o = 1'b0; + + // Handle teh Backwrite of the refill in the SCM banks + SCM_DATA_write_way_o = CAM_refill_way; + SCM_DATA_write_addr_o = CAM_refill_addr[ID_MSB:ID_LSB]; + SCM_DATA_write_dest_o = CAM_refill_addr[DEST_MSB:DEST_LSB] ; + SCM_DATA_write_wdata_o = AXI_rdata_i; + + SCM_TAG_write_way_o = CAM_refill_way; + SCM_TAG_write_addr_o = CAM_refill_addr[ID_MSB:ID_LSB]; + SCM_TAG_write_dest_o = CAM_refill_addr[DEST_MSB:DEST_LSB]; + + if(AXI_rvalid_i) + begin + SCM_DATA_write_req_o = ~cache_bypassed_o; + SCM_TAG_write_req_o = ~cache_bypassed_o; + SCM_TAG_write_wdata_o = {1'b1, CAM_refill_addr[TAG_MSB:TAG_LSB]}; + end + else // AXI_rvalid_i == 0 + begin + SCM_DATA_write_req_o = '0; + SCM_TAG_write_req_o = '0; + SCM_TAG_write_wdata_o = '0; + end + + + //Finally , if the CAM is EMpty, switch to BYPASSED state + if(CAM_empty) + begin + if( flush_icache_i ) + begin + NS = INVALIDATE; + end + else if( sel_flush_req_i ) + begin + NS = FLUSH_SET_ID; + end + else + begin + NS = BYPASSED; + end + end + else // CAM is not empty + begin + NS = GOING_BYPASS; + end + end + + + default: + begin + // In case something goes wrong, commute to Invalidated then --> Bypass or Enabled + cache_bypassed_o = 1'b1; + NS = INVALIDATE; + end + + endcase + end + + + // This FIFO holds information about in fligth fetches when cache is bypassed + generic_fifo + #( + .DATA_WIDTH ( 1 ), + .DATA_DEPTH ( DEPTH ) + ) + REL_CHUNK_FIFO + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .data_i ( ), + .valid_i ( fetch_req_i & AXI_gnt_i & (CS == BYPASSED) ), // cache in bypass mode, LOOKUPTABLE empty + .grant_o ( fifo_rel_chunk_gnt ), + + .data_o ( ), + .valid_o ( fifo_rel_chunk_valid ), + .grant_i ( AXI_rvalid_i ), + + .test_mode_i ( test_en_i ) + ); + + + + // This storage is a CAM, that stores pending refills: + // REfills are merged toghether if they compete to the same cache line. + // in case multiple cache banks have requested to the same cache line (in different moments) + // this cam updates these infos, and as soon the refill from axi side arrives, the master cache + // controller updates DATA/TAG and then notifies to those cache master to retry a fetch. + merge_refill_cam_128_16 + #( + .NB_WAYS ( NB_WAYS ), + .ID_WIDTH ( ID_WIDTH ), + .LOG2_ID_WIDTH ( LOG2_ID_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .DEPTH ( 16 ), + .LOG2_DEPTH ( 4 ), + .ADDR_CHECK_LSB ( ADDR_CHECK_LSB ), + .ADDR_CHECK_MSB ( ADDR_CHECK_MSB ) + ) + MERGE_CAM + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .empty_o ( CAM_empty ), + .retry_fetch_o ( retry_fetch_o ), + + .fetch_req_i ( fetch_req_i & fetch_gnt_o & ~cache_bypassed_o ), + .fetch_ID_BIN_i ( fetch_ID_BIN_i ), + .fetch_ID_OH_i ( fetch_ID_OH_i ), + .fetch_addr_i ( fetch_addr_i ), + .fetch_way_i ( fetch_way_i ), + .fetch_gnt_o ( CAM_grant ), + + .AXI_rvalid_i ( AXI_rvalid_i ), + .AXI_rID_i ( AXI_rID_i ), + + .AXI_req_o ( CAM_AXI_req ), + .AXI_addr_o ( CAM_AXI_addr ), + .AXI_ID_o ( CAM_AXI_ID ), + .AXI_gnt_i ( AXI_gnt_i ), + + + .refill_addr_o ( CAM_refill_addr ), + .refill_ID_o ( CAM_refill_ID ), + .refill_way_o ( CAM_refill_way ) + ); + + + assign empty_fifo_o = CAM_empty & ~fifo_rel_chunk_valid; + + +endmodule // central_controller diff --git a/hw/deps/icache_mp_128_pf/RTL/icache_bank_mp_128.sv b/hw/deps/icache_mp_128_pf/RTL/icache_bank_mp_128.sv new file mode 100644 index 0000000..149fd3c --- /dev/null +++ b/hw/deps/icache_mp_128_pf/RTL/icache_bank_mp_128.sv @@ -0,0 +1,610 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 22/01/2018 // +// Design Name: ICACHE_MP_128_PF // +// Module Name: icache_bank_mp_128 // +// Project Name: MrWolf // +// Language: SystemVerilog // +// // +// Description: This block represents private cache controller that // +// receives the requests from the process fetch unit // +// and perform TAG access for TAG hit check. In case of MISS // +// the refill is forwarded to the main cache controller (TOP) // +// // +// // +// Revision: // +// Revision v0.1 - 22/01/2018 : File Created // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +`define USE_REQ_BUFFER + +module icache_bank_mp_128 +#( + parameter int FETCH_ADDR_WIDTH = 32, + parameter int FETCH_DATA_WIDTH = 128, + + parameter int NB_CORES = 4, + parameter int BANK_ID = 0, + parameter int NB_BANKS = 4, + parameter int NB_WAYS = 4, + parameter int CACHE_LINE = 1, + + parameter int SCM_ADDR_WIDTH = 16, + parameter int SCM_TAG_WIDTH = 6, + parameter int SCM_DATA_WIDTH = 128, + + parameter int SET_ID_LSB = $clog2(NB_BANKS)+$clog2(SCM_DATA_WIDTH*CACHE_LINE)-3, + parameter int SET_ID_MSB = SET_ID_LSB + SCM_ADDR_WIDTH - 1, + parameter int TAG_LSB = SET_ID_MSB + 1, + parameter int TAG_MSB = TAG_LSB + SCM_TAG_WIDTH - 2, + + parameter bit FEATURE_STAT = 1'b0, + + parameter int AXI_ID = 4, + parameter int AXI_ADDR = FETCH_ADDR_WIDTH, + parameter int AXI_USER = 6, + parameter int AXI_DATA = 64 +) +( + input logic clk, + input logic rst_n, + input logic test_en_i, + + input logic notify_refill_done_i, + input logic bypass_icache_i, + input logic empty_fifo_i, + output logic cache_is_bypassed_o, + input logic [NB_CORES:0] bypass_status_i, + input logic retry_fetch_i, + + // interface with processor + input logic fetch_req_i, + input logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_i, + output logic fetch_gnt_o, + output logic fetch_rvalid_o, + output logic [FETCH_DATA_WIDTH-1:0] fetch_rdata_o, + + + // interface with READ PORT --> SCM DATA + output logic [NB_BANKS-1:0] DATA_read_req_o, + output logic [SCM_ADDR_WIDTH-1:0] DATA_read_addr_o, + input logic [NB_BANKS-1:0][NB_WAYS-1:0][SCM_DATA_WIDTH-1:0] DATA_read_rdata_i, + + // interface with READ PORT --> SCM TAG + output logic [NB_BANKS-1:0] TAG_read_req_o, + output logic [SCM_ADDR_WIDTH-1:0] TAG_read_addr_o, + input logic [NB_BANKS-1:0][NB_WAYS-1:0][SCM_TAG_WIDTH-1:0] TAG_read_rdata_i, + + + + + + // Interface to cache_controller_to_axi + output logic fetch_req_o, + output logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_o, + output logic [NB_WAYS-1:0] fetch_way_o, + input logic fetch_gnt_i, + input logic fetch_rvalid_i, + input logic [FETCH_DATA_WIDTH-1:0] fetch_rdata_i, + output logic [31:0] ctrl_hit_count_icache_o, + output logic [31:0] ctrl_trans_count_icache_o, + output logic [31:0] ctrl_miss_count_icache_o, + input logic ctrl_clear_regs_icache_i, + input logic ctrl_enable_regs_icache_i +); + + + localparam OFFSET = $clog2(SCM_DATA_WIDTH*CACHE_LINE)-3; + + // Finite State declaration: PS is Past State, used only for Statistic (perf Counters) + enum logic [2:0] { DISABLED_ICACHE, WAIT_NOTIFICATION, OPERATIVE, REQ_REFILL , WAIT_EMPTY_FIFOS, ENTER_BYPASS } CS, NS, PS; + + // signals declaration + logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_Q; + logic fetch_req_Q; + + logic save_fetch; + logic save_pipe_status; + logic clear_pipe; + logic enable_pipe; + + logic [$clog2(NB_BANKS)-1:0] fetch_dest_Q; //Target BANK + logic [NB_WAYS-1:0][SCM_DATA_WIDTH-1:0] DATA_read_rdata_int; + logic [NB_WAYS-1:0][SCM_TAG_WIDTH-1:0] TAG_read_rdata_int; + + + logic [NB_WAYS-1:0] way_match; + logic [NB_WAYS-1:0] way_valid; + logic [NB_WAYS-1:0] way_match_bin; + logic [NB_WAYS-1:0] way_match_Q; + logic [NB_WAYS-1:0] way_valid_Q; + + logic [NB_WAYS-1:0] random_way; + logic [$clog2(NB_WAYS)-1:0] first_available_way; + logic [NB_WAYS-1:0] first_available_way_OH; + + logic [$clog2(NB_WAYS)-1:0] HIT_WAY; + + assign first_available_way_OH = 1 << first_available_way; + + + + int unsigned i,j,index; + + + logic update_lfsr; + + logic [31:0] Count_Evictions; + + logic fetch_req_int; + logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_int; + logic [NB_WAYS-1:0] fetch_way_int; + logic fetch_gnt_int; +`ifdef USE_REQ_BUFFER + logic [FETCH_ADDR_WIDTH+NB_WAYS-1:0] s_data_in; + logic [FETCH_ADDR_WIDTH+NB_WAYS-1:0] s_data_out; +`endif + + + // Sequential Logic (state, counters and registrered signals) + always_ff @(posedge clk, negedge rst_n) + begin : Seq_logic + if(~rst_n) + begin + CS <= DISABLED_ICACHE; + PS <= DISABLED_ICACHE; + fetch_addr_Q <= '0; + fetch_req_Q <= 1'b0; + way_match_Q <= '0; + way_valid_Q <= '0; + if (FEATURE_STAT) begin + ctrl_hit_count_icache_o <= '0; + ctrl_trans_count_icache_o <= '0; + ctrl_miss_count_icache_o <= '0; + Count_Evictions <= '0; + ctrl_miss_count_icache_o <= '0; + end + end + else + begin + CS <= NS; + PS <= CS; + + + if (FEATURE_STAT) begin + if(ctrl_clear_regs_icache_i) + begin + ctrl_hit_count_icache_o <= '0; + ctrl_trans_count_icache_o <= '0; + Count_Evictions <= '0; + ctrl_miss_count_icache_o <= '0; + end + else + if(ctrl_enable_regs_icache_i) + begin + // Count incoming transactions + if(fetch_req_i & fetch_gnt_o) + ctrl_trans_count_icache_o <= ctrl_trans_count_icache_o + 1'b1; + + if( (CS == OPERATIVE) & fetch_req_Q & (|way_match) & (PS != WAIT_NOTIFICATION)) + ctrl_hit_count_icache_o <= ctrl_hit_count_icache_o + 1'b1; + + if( update_lfsr ) + Count_Evictions <= Count_Evictions + 1'b1; + + if( (CS == REQ_REFILL ) & fetch_gnt_int ) + ctrl_miss_count_icache_o<= ctrl_miss_count_icache_o + 1'b1; + + end + end + + if(save_pipe_status) + begin + way_match_Q <= way_match; + way_valid_Q <= way_valid; + end + + + if(enable_pipe) + begin + fetch_req_Q <= 1'b1; + fetch_addr_Q <= fetch_addr_i; + end + else if(clear_pipe) + begin + fetch_req_Q <= '0; + end + + end + end + + + + assign fetch_dest_Q = fetch_addr_Q[$clog2(NB_BANKS)+OFFSET-1:OFFSET]; + assign TAG_read_rdata_int = TAG_read_rdata_i[fetch_dest_Q] ; + assign DATA_read_rdata_int = DATA_read_rdata_i[fetch_dest_Q] ; + + + + + // Logic to check TAG HIT/MISS + // --------------------- // + // TAG CHECK MULTI WAY // + // --------------------- // + genvar k; + generate + for(k=0; k SCM TAG + output logic [NB_BANKS-1:0] TAG_read_req_o, + output logic [SCM_ADDR_WIDTH-1:0] TAG_read_addr_o, + input logic [NB_BANKS-1:0][NB_WAYS-1:0][SCM_TAG_WIDTH-1:0] TAG_read_rdata_i, + + + // Interface to cache_controller_to_axi + output logic fetch_req_o, + output logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_o, + output logic [NB_WAYS-1:0] fetch_way_o, + input logic fetch_gnt_i, + input logic fetch_rvalid_i +); + + + localparam OFFSET = $clog2(SCM_DATA_WIDTH*CACHE_LINE)-3; + + // Finite State declaration: PS is Past State, used only for Statistic (perf Counters) + enum logic [2:0] { DISABLED_ICACHE, WAIT_NOTIFICATION, OPERATIVE, REQ_REFILL , WAIT_EMPTY_FIFOS, ENTER_BYPASS } CS, NS, PS; + + // signals declaration + logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_Q; + logic fetch_req_Q; + + logic save_fetch; + logic save_pipe_status; + logic clear_pipe; + logic enable_pipe; + + logic [$clog2(NB_BANKS)-1:0] fetch_dest_Q; //Target BANK + logic [NB_WAYS-1:0][SCM_TAG_WIDTH-1:0] TAG_read_rdata_int; + + logic [NB_WAYS-1:0] way_match; + logic [NB_WAYS-1:0] way_valid; + logic [NB_WAYS-1:0] way_match_bin; + logic [NB_WAYS-1:0] way_match_Q; + logic [NB_WAYS-1:0] way_valid_Q; + + logic [NB_WAYS-1:0] random_way; // In case of Way replacement // Driven By LFSR + logic [$clog2(NB_WAYS)-1:0] first_available_way; + logic [NB_WAYS-1:0] first_available_way_OH; + + logic [$clog2(NB_WAYS)-1:0] HIT_WAY; + + assign first_available_way_OH = 1 << first_available_way; + + + + int unsigned i,j,index; + + + logic update_lfsr; + + + logic fetch_req_int; + logic [FETCH_ADDR_WIDTH-1:0] fetch_addr_int; + logic [NB_WAYS-1:0] fetch_way_int; + logic fetch_gnt_int; +`ifdef USE_REQ_BUFFER + logic [FETCH_ADDR_WIDTH+NB_WAYS-1:0] s_data_in; + logic [FETCH_ADDR_WIDTH+NB_WAYS-1:0] s_data_out; +`endif + + + + // Sequential Logic (state, counters and registrered signals) + always_ff @(posedge clk, negedge rst_n) + begin : Seq_logic + if(~rst_n) + begin + CS <= DISABLED_ICACHE; + PS <= DISABLED_ICACHE; + fetch_addr_Q <= '0; + fetch_req_Q <= 1'b0; + way_match_Q <= '0; + way_valid_Q <= '0; + end + else + begin + CS <= NS; + PS <= CS; + + if(save_pipe_status) + begin + way_match_Q <= way_match; + way_valid_Q <= way_valid; + end + + + if(enable_pipe) + begin + fetch_req_Q <= 1'b1; + fetch_addr_Q <= fetch_addr_i; + end + else if(clear_pipe) + begin + fetch_req_Q <= '0; + end + + end + end + + + + assign fetch_dest_Q = fetch_addr_Q[$clog2(NB_BANKS)+OFFSET-1:OFFSET]; + assign TAG_read_rdata_int = TAG_read_rdata_i[fetch_dest_Q] ; + + + + // Logic to check TAG HIT/MISS + // --------------------- // + // TAG CHECK MULTI WAY // + // --------------------- // + genvar k; + generate + for(k=0; k1, accept only incr burst=01 + output logic axi_master_arlock_o, //only normal access supported axs_awlock=00 + output logic [ 3:0] axi_master_arcache_o, + output logic [ 2:0] axi_master_arprot_o, + output logic [ 3:0] axi_master_arregion_o, // + output logic [ AXI_USER-1:0] axi_master_aruser_o, // + output logic [ 3:0] axi_master_arqos_o, // + output logic axi_master_arvalid_o, //master addr valid + input logic axi_master_arready_i, //slave ready to accept + // --------------------------------------------------------------- + + + //AXI BACKWARD read data bus ---------------------------------------------- + input logic [AXI_ID-1:0] axi_master_rid_i, + input logic [AXI_DATA-1:0] axi_master_rdata_i, + input logic [1:0] axi_master_rresp_i, + input logic axi_master_rlast_i, //last transfer in burst + input logic [AXI_USER-1:0] axi_master_ruser_i, + input logic axi_master_rvalid_i, //slave data valid + output logic axi_master_rready_o, //master ready to accept + + // NOT USED ---------------------------------------------- + output logic [AXI_ID-1:0] axi_master_awid_o, + output logic [AXI_ADDR-1:0] axi_master_awaddr_o, + output logic [ 7:0] axi_master_awlen_o, + output logic [ 2:0] axi_master_awsize_o, + output logic [ 1:0] axi_master_awburst_o, + output logic axi_master_awlock_o, + output logic [ 3:0] axi_master_awcache_o, + output logic [ 2:0] axi_master_awprot_o, + output logic [ 3:0] axi_master_awregion_o, + output logic [ AXI_USER-1:0] axi_master_awuser_o, + output logic [ 3:0] axi_master_awqos_o, + output logic axi_master_awvalid_o, + input logic axi_master_awready_i, + + // NOT USED ---------------------------------------------- + output logic [AXI_DATA-1:0] axi_master_wdata_o, + output logic [AXI_DATA/8-1:0] axi_master_wstrb_o, + output logic axi_master_wlast_o, + output logic [ AXI_USER-1:0] axi_master_wuser_o, + output logic axi_master_wvalid_o, + input logic axi_master_wready_i, + // --------------------------------------------------------------- + + // NOT USED ---------------------------------------------- + input logic [AXI_ID-1:0] axi_master_bid_i, + input logic [ 1:0] axi_master_bresp_i, + input logic [ AXI_USER-1:0] axi_master_buser_i, + input logic axi_master_bvalid_i, + output logic axi_master_bready_o, + // --------------------------------------------------------------- + + MP_PF_ICACHE_CTRL_UNIT_BUS.Slave IC_ctrl_unit_slave_if +); + + // Parameter to reduce the TAG bits (cachin only L2 and not on 4GB memory space) + // The assumption is that During ROM reading cache is Disabled. + localparam REDUCE_TAG_WIDTH = $clog2(L2_SIZE/CACHE_SIZE)+$clog2(NB_WAYS); + + localparam OFFSET = $clog2(FETCH_DATA_WIDTH)-3; // log2(128)-3 = 4; + localparam BANK_SIZE = CACHE_SIZE/NB_BANKS; + localparam WAY_SIZE = BANK_SIZE/NB_WAYS; + localparam SCM_NUM_ROWS = WAY_SIZE/(CACHE_LINE*FETCH_DATA_WIDTH/8); // TAG + localparam SCM_TAG_ADDR_WIDTH = $clog2(SCM_NUM_ROWS); + + localparam TAG_WIDTH = USE_REDUCED_TAG ? REDUCE_TAG_WIDTH : (FETCH_ADDR_WIDTH - SCM_TAG_ADDR_WIDTH - $clog2(NB_BANKS) - $clog2(CACHE_LINE) - OFFSET + 1); + + localparam DATA_WIDTH = FETCH_DATA_WIDTH; + localparam SCM_DATA_ADDR_WIDTH = SCM_TAG_ADDR_WIDTH; + + localparam AXI_ID_INT = $clog2(NB_CORES+1); + + localparam SET_ID_LSB = $clog2(NB_BANKS)+$clog2(FETCH_DATA_WIDTH*CACHE_LINE)-3; + localparam SET_ID_MSB = SET_ID_LSB + SCM_TAG_ADDR_WIDTH - 1; + localparam TAG_LSB = SET_ID_MSB + 1; + localparam TAG_MSB = TAG_LSB + TAG_WIDTH - 2 ; //1 bit is count for valid + + + // interface with READ PORT --> SCM DATA + logic [NB_CORES-1:0][NB_BANKS-1:0] DATA_read_req_int; + logic [NB_CORES-1:0][SCM_DATA_ADDR_WIDTH-1:0] DATA_read_addr_int; + logic [NB_BANKS-1:0][NB_WAYS-1:0][NB_CORES-1:0][FETCH_DATA_WIDTH-1:0] DATA_read_rdata_int; + + // interface with READ PORT --> SCM TAG + logic [NB_CORES:0][NB_BANKS-1:0] TAG_read_req_int; + logic [NB_CORES:0][SCM_TAG_ADDR_WIDTH-1:0] TAG_read_addr_int; + logic [NB_BANKS-1:0][NB_WAYS-1:0][NB_CORES:0][TAG_WIDTH-1:0] TAG_read_rdata_int; + + + // interface with WRITE PORT --> TAG SCM UNIFIED + logic SCM_TAG_write_req_int; + logic [SCM_TAG_ADDR_WIDTH-1:0] SCM_TAG_write_addr_int; + logic [$clog2(NB_BANKS)-1:0] SCM_TAG_write_dest_int; + logic [TAG_WIDTH-1:0] SCM_TAG_write_wdata_int; + logic [NB_WAYS-1:0] SCM_TAG_write_way_int; + + // interface with WRITE PORT --> DATA SCM UNIFIED + logic SCM_DATA_write_req_int; + logic [SCM_DATA_ADDR_WIDTH-1:0] SCM_DATA_write_addr_int; + logic [$clog2(NB_BANKS)-1:0] SCM_DATA_write_dest_int; + logic [FETCH_DATA_WIDTH-1:0] SCM_DATA_write_wdata_int; + logic [NB_WAYS-1:0] SCM_DATA_write_way_int; + + + + logic [NB_BANKS-1:0] [NB_CORES:0] TAG_ReadEnable; + logic [NB_BANKS-1:0] [NB_CORES-1:0] DATA_ReadEnable; + logic [NB_CORES:0] [NB_BANKS-1:0][NB_WAYS-1:0] [TAG_WIDTH-1:0] TAG_ReadData; + logic [NB_CORES-1:0] [NB_BANKS-1:0][NB_WAYS-1:0] [FETCH_DATA_WIDTH-1:0] DATA_ReadData; + + logic [NB_CORES:0] notify_refill_done; + + logic [NB_CORES-1:0][NB_WAYS-1:0] fetch_way_int; + + logic [NB_CORES-1:0] fetch_req_int; + logic [NB_CORES-1:0][FETCH_ADDR_WIDTH-1:0] fetch_addr_int; + logic [NB_CORES-1:0] fetch_gnt_int; + logic [NB_CORES-1:0] fetch_rvalid_int; + logic [NB_CORES-1:0][FETCH_DATA_WIDTH-1:0] fetch_rdata_int; + + logic [NB_BANKS-1:0] SCM_TAG_write_dest_OH_int; + logic [NB_BANKS-1:0] SCM_DATA_write_dest_OH_int; + logic [NB_CORES+1:0] cache_is_bypassed; // NB_CORES+CENTRL_CACHE_CTRL+HW prefetcher + + logic [NB_CORES:0] retry_fetch; + + + logic bypass_icache; + logic empty_fifo; + logic flush_icache; + logic flush_ack; + logic sel_flush_req; + logic [FETCH_ADDR_WIDTH-1:0] sel_flush_addr; + logic sel_flush_ack; + + + logic [AXI_ID_INT-1:0] axi_master_arid_int; + logic [AXI_ADDR-1:0] axi_master_araddr_int; + logic [ 7:0] axi_master_arlen_int; + logic [ 2:0] axi_master_arsize_int; + logic [ 1:0] axi_master_arburst_int; + logic axi_master_arlock_int; + logic [ 3:0] axi_master_arcache_int; + logic [ 2:0] axi_master_arprot_int; + logic [ 3:0] axi_master_arregion_int; + logic [ AXI_USER-1:0] axi_master_aruser_int; + logic [ 3:0] axi_master_arqos_int; + logic axi_master_arvalid_int; + logic axi_master_arready_int; + + + logic [AXI_ID_INT-1:0] axi_master_rid_int; + logic [AXI_DATA-1:0] axi_master_rdata_int; + logic [1:0] axi_master_rresp_int; + logic axi_master_rlast_int; + logic [AXI_USER-1:0] axi_master_ruser_int; + logic axi_master_rvalid_int; + logic axi_master_rready_int; + + + // Signals from Prefetcher control unit to HW prefetcher Block + logic pf_req_to_cc; + logic [31:0] pf_addr_to_cc; + logic pf_gnt_from_cc; + logic pf_rvalid_from_cc; + + // Signal from HW prefetcher to main cache controller + logic pf_req_to_master_cc; + logic [31:0] pf_addr_to_master_cc; + logic [NB_WAYS-1:0] pf_way_to_master_cc; + logic pf_gnt_from_master_cc; + logic pf_rvalid_from_master_cc; + + + + + // Performamce counters + logic [31:0] total_hit_count; + logic [31:0] total_trans_count; + logic [31:0] total_miss_count; + + logic [NB_CORES-1:0][31:0] bank_hit_count; + logic [NB_CORES-1:0][31:0] bank_trans_count; + logic [NB_CORES-1:0][31:0] bank_miss_count; + + assign SCM_TAG_write_dest_OH_int = (1 << SCM_TAG_write_dest_int); + assign SCM_DATA_write_dest_OH_int = (1 << SCM_DATA_write_dest_int); + + genvar i,j,k,z; + int unsigned index; + + + assign bypass_icache = IC_ctrl_unit_slave_if.bypass_req; + assign IC_ctrl_unit_slave_if.bypass_ack = cache_is_bypassed; + assign flush_icache = IC_ctrl_unit_slave_if.flush_req; + assign IC_ctrl_unit_slave_if.flush_ack = flush_ack; + + assign sel_flush_req = IC_ctrl_unit_slave_if.sel_flush_req; + assign sel_flush_addr = IC_ctrl_unit_slave_if.sel_flush_addr; + assign IC_ctrl_unit_slave_if.sel_flush_ack = sel_flush_ack; + + // Performamce counters + if (FEATURE_STAT) begin + assign IC_ctrl_unit_slave_if.global_hit_count = total_hit_count; + assign IC_ctrl_unit_slave_if.global_trans_count = total_trans_count; + assign IC_ctrl_unit_slave_if.global_miss_count = total_miss_count; + + always_comb + begin + total_hit_count = '0; + total_trans_count = '0; + for (index=0; index SCM DATA + .DATA_read_req_o ( DATA_read_req_int[i] ), + .DATA_read_addr_o ( DATA_read_addr_int[i] ), + .DATA_read_rdata_i ( DATA_ReadData[i] ), + + // interface with READ PORT --> SCM TAG + .TAG_read_req_o ( TAG_read_req_int[i] ), + .TAG_read_addr_o ( TAG_read_addr_int[i] ), + .TAG_read_rdata_i ( TAG_ReadData[i] ), + + // interface to CC to AXI bridge + .fetch_req_o ( fetch_req_int[i] ), + .fetch_addr_o ( fetch_addr_int[i] ), + .fetch_way_o ( fetch_way_int[i] ), + + .fetch_gnt_i ( fetch_gnt_int[i] ), + .fetch_rvalid_i ( fetch_rvalid_int[i] ), + .fetch_rdata_i ( fetch_rdata_int[i] ), + .ctrl_hit_count_icache_o ( bank_hit_count[i] ), + .ctrl_trans_count_icache_o ( bank_trans_count[i] ), + .ctrl_miss_count_icache_o ( bank_miss_count[i] ), + .ctrl_clear_regs_icache_i ( IC_ctrl_unit_slave_if.ctrl_clear_regs ), + .ctrl_enable_regs_icache_i ( IC_ctrl_unit_slave_if.ctrl_enable_regs ) + ); + end + + + + + for(i=0;i TAG SCM Unified PORT + .SCM_TAG_write_req_o ( SCM_TAG_write_req_int ), + .SCM_TAG_write_addr_o ( SCM_TAG_write_addr_int ), + .SCM_TAG_write_dest_o ( SCM_TAG_write_dest_int ), + .SCM_TAG_write_wdata_o ( SCM_TAG_write_wdata_int ), + .SCM_TAG_write_way_o ( SCM_TAG_write_way_int ), + + // interface with WRITE PORT --> DATA SCM Unified PORT + .SCM_DATA_write_req_o ( SCM_DATA_write_req_int ), + .SCM_DATA_write_addr_o ( SCM_DATA_write_addr_int ), // double number of rows with respect TAG SCM ARRAY + .SCM_DATA_write_dest_o ( SCM_DATA_write_dest_int ), + .SCM_DATA_write_wdata_o( SCM_DATA_write_wdata_int ), + .SCM_DATA_write_way_o ( SCM_DATA_write_way_int ), + + //AXI read address bus ------------------------------------------- + .axi_master_arid_o ( axi_master_arid_int[AXI_ID_INT-1:0] ), + .axi_master_araddr_o ( axi_master_araddr_int ), + .axi_master_arlen_o ( axi_master_arlen_int ), + .axi_master_arsize_o ( axi_master_arsize_int ), + .axi_master_arburst_o ( axi_master_arburst_int ), + .axi_master_arlock_o ( axi_master_arlock_int ), + .axi_master_arcache_o ( axi_master_arcache_int ), + .axi_master_arprot_o ( axi_master_arprot_int ), + .axi_master_arregion_o ( axi_master_arregion_int ), + .axi_master_aruser_o ( axi_master_aruser_int ), + .axi_master_arqos_o ( axi_master_arqos_int ), + .axi_master_arvalid_o ( axi_master_arvalid_int ), + .axi_master_arready_i ( axi_master_arready_int ), + // --------------------------------------------------------------- + + + //AXI BACKWARD read data bus ---------------------------------------------- + .axi_master_rid_i ( axi_master_rid_int[AXI_ID_INT-1:0] ), + .axi_master_rdata_i ( axi_master_rdata_int ), + .axi_master_rresp_i ( axi_master_rresp_int ), + .axi_master_rlast_i ( axi_master_rlast_int ), + .axi_master_ruser_i ( axi_master_ruser_int ), + .axi_master_rvalid_i ( axi_master_rvalid_int ), + .axi_master_rready_o ( axi_master_rready_int ) + ); + + + + // Axi Write Channels tied to 0 + + assign axi_master_arid_o[AXI_ID-1:AXI_ID_INT] = '0; + + assign axi_master_awid_o = '0; + assign axi_master_awaddr_o = '0; + assign axi_master_awlen_o = '0; + assign axi_master_awsize_o = '0; + assign axi_master_awburst_o = '0; + assign axi_master_awlock_o = '0; + assign axi_master_awcache_o = '0; + assign axi_master_awprot_o = '0; + assign axi_master_awregion_o = '0; + assign axi_master_awuser_o = '0; + assign axi_master_awqos_o = '0; + assign axi_master_awvalid_o = '0; + assign axi_master_wdata_o = '0; + assign axi_master_wstrb_o = '0; + assign axi_master_wlast_o = '0; + assign axi_master_wuser_o = '0; + assign axi_master_wvalid_o = '0; + assign axi_master_bready_o = '0; + + +`ifdef USE_AXI_SLICES + + //////////////////////////////////////////////////////////////////////// + // █████╗ ██╗ ██╗██╗ ███████╗██╗ ██╗ ██████╗███████╗███████╗ // + // ██╔══██╗╚██╗██╔╝██║ ██╔════╝██║ ██║██╔════╝██╔════╝██╔════╝ // + // ███████║ ╚███╔╝ ██║ ███████╗██║ ██║██║ █████╗ ███████╗ // + // ██╔══██║ ██╔██╗ ██║ ╚════██║██║ ██║██║ ██╔══╝ ╚════██║ // + // ██║ ██║██╔╝ ██╗██║ ███████║███████╗██║╚██████╗███████╗███████║ // + // ╚═╝ ╚═╝╚═╝ ╚═╝╚═╝ ╚══════╝╚══════╝╚═╝ ╚═════╝╚══════╝╚══════╝ // + //////////////////////////////////////////////////////////////////////// + // to alleviate pressure on AXI side, this SLice can be added or not + // by defining the USE_AXI_SLICES macro. It will insert a AR and R slice on the AXI plug + axi_ar_buffer + #( + .ID_WIDTH ( AXI_ID_INT ), + .ADDR_WIDTH ( AXI_ADDR ), + .USER_WIDTH ( AXI_USER ), + .BUFFER_DEPTH ( 2 ) + ) + i_AXI_AR_BUFFER + ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( axi_master_arvalid_int ), + .slave_addr_i ( axi_master_araddr_int ), + .slave_prot_i ( axi_master_arprot_int ), + .slave_region_i ( axi_master_arregion_int ), + .slave_len_i ( axi_master_arlen_int ), + .slave_size_i ( axi_master_arsize_int ), + .slave_burst_i ( axi_master_arburst_int ), + .slave_lock_i ( axi_master_arlock_int ), + .slave_cache_i ( axi_master_arcache_int ), + .slave_qos_i ( axi_master_arqos_int ), + .slave_id_i ( axi_master_arid_int[AXI_ID_INT-1:0] ), + .slave_user_i ( axi_master_aruser_int ), + .slave_ready_o ( axi_master_arready_int ), + + .master_valid_o ( axi_master_arvalid_o ), + .master_addr_o ( axi_master_araddr_o ), + .master_prot_o ( axi_master_arprot_o ), + .master_region_o ( axi_master_arregion_o ), + .master_len_o ( axi_master_arlen_o ), + .master_size_o ( axi_master_arsize_o ), + .master_burst_o ( axi_master_arburst_o ), + .master_lock_o ( axi_master_arlock_o ), + .master_cache_o ( axi_master_arcache_o ), + .master_qos_o ( axi_master_arqos_o ), + .master_id_o ( axi_master_arid_o[AXI_ID_INT-1:0] ), + .master_user_o ( axi_master_aruser_o ), + .master_ready_i ( axi_master_arready_i ) + ); + + axi_r_buffer + #( + .ID_WIDTH ( AXI_ID_INT ), + .DATA_WIDTH ( AXI_DATA ), + .USER_WIDTH ( AXI_USER ), + .BUFFER_DEPTH ( 2 ) + ) + i_AXI_R_BUFFER + ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( axi_master_rvalid_i ), + .slave_data_i ( axi_master_rdata_i ), + .slave_resp_i ( axi_master_rresp_i ), + .slave_user_i ( axi_master_ruser_i ), + .slave_id_i ( axi_master_rid_i[AXI_ID_INT-1:0] ), + .slave_last_i ( axi_master_rlast_i ), + .slave_ready_o ( axi_master_rready_o ), + + .master_valid_o ( axi_master_rvalid_int ), + .master_data_o ( axi_master_rdata_int ), + .master_resp_o ( axi_master_rresp_int ), + .master_user_o ( axi_master_ruser_int ), + .master_id_o ( axi_master_rid_int[AXI_ID_INT-1:0] ), + .master_last_o ( axi_master_rlast_int ), + .master_ready_i ( axi_master_rready_int ) +); + +`else + assign axi_master_rvalid_int = axi_master_rvalid_i ; + assign axi_master_rdata_int = axi_master_rdata_i ; + assign axi_master_rresp_int = axi_master_rresp_i ; + assign axi_master_ruser_int = axi_master_ruser_i ; + assign axi_master_rid_int[AXI_ID_INT-1:0] = axi_master_rid_i[AXI_ID_INT-1:0] ; + assign axi_master_rlast_int = axi_master_rlast_i ; + assign axi_master_rready_o = axi_master_rready_int ; + + assign axi_master_arvalid_o = axi_master_arvalid_int ; + assign axi_master_araddr_o = axi_master_araddr_int ; + assign axi_master_arprot_o = axi_master_arprot_int ; + assign axi_master_arregion_o = axi_master_arregion_int ; + assign axi_master_arlen_o = axi_master_arlen_int ; + assign axi_master_arsize_o = axi_master_arsize_int ; + assign axi_master_arburst_o = axi_master_arburst_int ; + assign axi_master_arlock_o = axi_master_arlock_int ; + assign axi_master_arcache_o = axi_master_arcache_int ; + assign axi_master_arqos_o = axi_master_arqos_int ; + assign axi_master_arid_o[AXI_ID_INT-1:0] = axi_master_arid_int[AXI_ID_INT-1:0] ; + assign axi_master_aruser_o = axi_master_aruser_int ; + assign axi_master_arready_int = axi_master_arready_i ; +`endif + + + + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + // ██████╗ ██████╗ ███████╗███████╗███████╗████████╗ ██████╗██╗ ██╗███████╗██████╗ ██████╗ ██████╗ // + // ██╔══██╗██╔══██╗██╔════╝██╔════╝██╔════╝╚══██╔══╝██╔════╝██║ ██║██╔════╝██╔══██╗ ██╔════╝██╔════╝ // + // ██████╔╝██████╔╝█████╗ █████╗ █████╗ ██║ ██║ ███████║█████╗ ██████╔╝ ██║ ██║ // + // ██╔═══╝ ██╔══██╗██╔══╝ ██╔══╝ ██╔══╝ ██║ ██║ ██╔══██║██╔══╝ ██╔══██╗ ██║ ██║ // + // ██║ ██║ ██║███████╗██║ ███████╗ ██║ ╚██████╗██║ ██║███████╗██║ ██║ ╚██████╗╚██████╗ // + // ╚═╝ ╚═╝ ╚═╝╚══════╝╚═╝ ╚══════╝ ╚═╝ ╚═════╝╚═╝ ╚═╝╚══════╝╚═╝ ╚═╝ ╚═════╝ ╚═════╝ // + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + + icache_bank_mp_128_PF + #( + .FETCH_ADDR_WIDTH ( FETCH_ADDR_WIDTH ), + .FETCH_DATA_WIDTH ( FETCH_DATA_WIDTH ), + + .NB_CORES ( NB_CORES+1 ), + .BANK_ID ( NB_CORES ), + .NB_BANKS ( NB_BANKS ), + .NB_WAYS ( NB_WAYS ), + .CACHE_LINE ( CACHE_LINE ), + + .SCM_ADDR_WIDTH ( SCM_TAG_ADDR_WIDTH ), + .SCM_TAG_WIDTH ( TAG_WIDTH ), + .SCM_DATA_WIDTH ( FETCH_DATA_WIDTH ), + + .SET_ID_LSB ( SET_ID_LSB ), + .SET_ID_MSB ( SET_ID_MSB ), + .TAG_LSB ( TAG_LSB ), + .TAG_MSB ( TAG_MSB ), + + .AXI_ID ( AXI_ID ), + .AXI_ADDR ( AXI_ADDR ), + .AXI_USER ( AXI_USER ), + .AXI_DATA ( AXI_DATA ) + ) + pf_cc + ( + .clk ( clk ), + .rst_n ( rst_n ), + .test_en_i ( test_en_i ), + + .notify_refill_done_i ( notify_refill_done[NB_CORES] ), + .bypass_icache_i ( bypass_icache ), + .empty_fifo_i ( empty_fifo ), + .cache_is_bypassed_o ( cache_is_bypassed[NB_CORES] ), + .bypass_status_i ( cache_is_bypassed ), + .retry_fetch_i ( retry_fetch[NB_CORES] ), + + + .fetch_req_i ( pf_req_to_cc ), + .fetch_addr_i ( pf_addr_to_cc ), + .fetch_gnt_o ( pf_gnt_from_cc ), + .fetch_rvalid_o ( pf_rvalid_from_cc ), + + .TAG_read_req_o ( TAG_read_req_int[NB_CORES] ), + .TAG_read_addr_o ( TAG_read_addr_int[NB_CORES] ), + .TAG_read_rdata_i ( TAG_ReadData[NB_CORES] ), + + + // To be multiplexed at the output of the XBAR_ICACHE + .fetch_req_o ( pf_req_to_master_cc ), + .fetch_addr_o ( pf_addr_to_master_cc ), + .fetch_way_o ( pf_way_to_master_cc ), + .fetch_gnt_i ( pf_gnt_from_master_cc ), + .fetch_rvalid_i ( pf_rvalid_from_master_cc ) + ); + + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////// + // ██╗ ██╗██╗ ██╗ ██████╗ ██████╗ ███████╗███████╗███████╗████████╗ ██████╗██╗ ██╗███████╗██████╗ // + // ██║ ██║██║ ██║ ██╔══██╗██╔══██╗██╔════╝██╔════╝██╔════╝╚══██╔══╝██╔════╝██║ ██║██╔════╝██╔══██╗ // + // ███████║██║ █╗ ██║ ██████╔╝██████╔╝█████╗ █████╗ █████╗ ██║ ██║ ███████║█████╗ ██████╔╝ // + // ██╔══██║██║███╗██║ ██╔═══╝ ██╔══██╗██╔══╝ ██╔══╝ ██╔══╝ ██║ ██║ ██╔══██║██╔══╝ ██╔══██╗ // + // ██║ ██║╚███╔███╔╝ ██║ ██║ ██║███████╗██║ ███████╗ ██║ ╚██████╗██║ ██║███████╗██║ ██║ // + // ╚═╝ ╚═╝ ╚══╝╚══╝ ╚═╝ ╚═╝ ╚═╝╚══════╝╚═╝ ╚══════╝ ╚═╝ ╚═════╝╚═╝ ╚═╝╚══════╝╚═╝ ╚═╝ // + ///////////////////////////////////////////////////////////////////////////////////////////////////////////// + + prefetcher_if sw_prefetcher_if + ( + .clk ( clk ), + .rst_n ( rst_n ), + .test_en_i ( test_en_i ), + + + .pf_addr_i ( IC_ctrl_unit_slave_if.pf_addr ), + .pf_size_i ( IC_ctrl_unit_slave_if.pf_size ), + .pf_req_i ( IC_ctrl_unit_slave_if.pf_req ), + .pf_ack_o ( IC_ctrl_unit_slave_if.pf_ack ), + .pf_done_o ( IC_ctrl_unit_slave_if.pf_done ), + + + .pf_req_o ( pf_req_to_cc ), + .pf_addr_o ( pf_addr_to_cc ), + .pf_gnt_i ( pf_gnt_from_cc ), + .pf_rvalid_i ( pf_rvalid_from_cc ) + ); +endmodule // icache_top_scm_mp diff --git a/hw/deps/icache_mp_128_pf/RTL/merge_refill_cam_128_16.sv b/hw/deps/icache_mp_128_pf/RTL/merge_refill_cam_128_16.sv new file mode 100644 index 0000000..c9c7bd6 --- /dev/null +++ b/hw/deps/icache_mp_128_pf/RTL/merge_refill_cam_128_16.sv @@ -0,0 +1,544 @@ +//////////////////////////////////////////////////////////////////////////////// +// // +// Copyright 2018 ETH Zurich and University of Bologna. // +// Copyright and related rights are licensed under the Solderpad Hardware // +// License, Version 0.51 (the "License"); you may not use this file except in // +// compliance with the License. You may obtain a copy of the License at // +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // +// or agreed to in writing, software, hardware and materials distributed under// +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // +// CONDITIONS OF ANY KIND, either express or implied. See the License for the // +// specific language governing permissions and limitations under the License. // +// // +// Company: Micrel Lab @ DEIS - University of Bologna // +// Viale Risorgimento 2 40136 // +// Bologna - fax 0512093785 - // +// // +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 22/01/2018 // +// Design Name: ICACHE_MP_128_PF // +// Module Name: merge_refill_cam_128_16 // +// Project Name: MrWolf // +// Language: SystemVerilog // +// // +// Description: This block implemets a CAM with 16 slots, used to track // +// outstanding refills. Anytime a refill is required, the // +// main CC first checks that there is not yet a pending refill// +// on that cache line. If yes, it simply updated that Entry // +// of the cam. In case there is no valid entry, it pushed // +// refill info in the CAM , and it assertd a refill. // +// When Refill is Back from AXI port, the related entry is // +// popped, and all the related processor are notified. // +// // +// // +// Revision: // +// Revision v0.1 - 22/01/2018 : File Created // +// Additional Comments: // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + + +module merge_refill_cam_128_16 +#( + parameter NB_WAYS = 4, + parameter ID_WIDTH = 4, + parameter LOG2_ID_WIDTH = $clog2(ID_WIDTH), + parameter ADDR_WIDTH = 32, + parameter DEPTH = 16, + parameter LOG2_DEPTH = $clog2(DEPTH), + parameter ADDR_CHECK_LSB = 4, + parameter ADDR_CHECK_MSB = ADDR_WIDTH-1 +) +( + input logic clk, + input logic rst_n, + + output logic empty_o, + + input logic fetch_req_i, + input logic [LOG2_ID_WIDTH-1:0] fetch_ID_BIN_i, + input logic [ID_WIDTH-1:0] fetch_ID_OH_i, + input logic [ADDR_WIDTH-1:0] fetch_addr_i, + input logic [NB_WAYS-1:0] fetch_way_i, + output logic fetch_gnt_o, + output logic [ID_WIDTH-1:0] retry_fetch_o, + + input logic AXI_rvalid_i, + input logic [LOG2_DEPTH-1:0] AXI_rID_i, + + output logic AXI_req_o, + output logic [ADDR_WIDTH-1:0] AXI_addr_o, + output logic [LOG2_DEPTH-1:0] AXI_ID_o, + input logic AXI_gnt_i, + + + // for refill PURPOSE ONLY + output logic [ADDR_WIDTH-1:0] refill_addr_o, + output logic [ID_WIDTH-1:0] refill_ID_o, + output logic [NB_WAYS-1:0] refill_way_o +); + + + logic [DEPTH-1:0] LOOKUP_TABLE; + logic [ID_WIDTH-1:0] ID_TABLE [DEPTH-1:0]; + logic [NB_WAYS+ADDR_WIDTH-1:0] ADDR_TABLE [DEPTH-1:0]; + + logic [DEPTH-1:0] check_push_Match_addr; + logic [$clog2(DEPTH)-1:0] push_MATCH_index; + + logic [ADDR_WIDTH-1:0] last_refill_addr; + logic last_refill_valid; + logic FIFO_full; + + + + assign FIFO_full = (&LOOKUP_TABLE) ? 1'b1 : 1'b0; + assign empty_o = (|LOOKUP_TABLE) ? 1'b0 : 1'b1; + + + assign refill_addr_o = {ADDR_TABLE[AXI_rID_i][ADDR_WIDTH-1:0]}; + assign refill_way_o = ADDR_TABLE[AXI_rID_i][NB_WAYS+ADDR_WIDTH-1:ADDR_WIDTH]; + assign refill_ID_o = ID_TABLE[AXI_rID_i]; + + + int unsigned i,j,k; + + + always_ff @(posedge clk or negedge rst_n) + begin + if(~rst_n) + begin + for(i=0; i + +module per2axi +#( + parameter NB_CORES = 4, + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3, + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 +) +( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + // PERIPHERAL INTERCONNECT SLAVE + //*************************************** + //REQUEST CHANNEL + input logic per_slave_req_i, + input logic [PER_ADDR_WIDTH-1:0] per_slave_add_i, + input logic per_slave_we_i, + input logic [5:0] per_slave_atop_i, + input logic [31:0] per_slave_wdata_i, + input logic [3:0] per_slave_be_i, + input logic [PER_ID_WIDTH-1:0] per_slave_id_i, + output logic per_slave_gnt_o, + + //RESPONSE CHANNEL + output logic per_slave_r_valid_o, + output logic per_slave_r_opc_o, + output logic [PER_ID_WIDTH-1:0] per_slave_r_id_o, + output logic [31:0] per_slave_r_rdata_o, + + // TRYX CTRL + input logic [NB_CORES-1:0][AXI_USER_WIDTH-1:0] axi_axuser_i, + output logic [NB_CORES-1:0] axi_xresp_decerr_o, + output logic [NB_CORES-1:0] axi_xresp_slverr_o, + output logic [NB_CORES-1:0] axi_xresp_valid_o, + + // AXI4 MASTER + //*************************************** + // WRITE ADDRESS CHANNEL + output logic axi_master_aw_valid_o, + output logic [AXI_ADDR_WIDTH-1:0] axi_master_aw_addr_o, + output logic [2:0] axi_master_aw_prot_o, + output logic [3:0] axi_master_aw_region_o, + output logic [7:0] axi_master_aw_len_o, + output logic [2:0] axi_master_aw_size_o, + output logic [1:0] axi_master_aw_burst_o, + output logic axi_master_aw_lock_o, + output logic [5:0] axi_master_aw_atop_o, + output logic [3:0] axi_master_aw_cache_o, + output logic [3:0] axi_master_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] axi_master_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_master_aw_user_o, + input logic axi_master_aw_ready_i, + + // READ ADDRESS CHANNEL + output logic axi_master_ar_valid_o, + output logic [AXI_ADDR_WIDTH-1:0] axi_master_ar_addr_o, + output logic [2:0] axi_master_ar_prot_o, + output logic [3:0] axi_master_ar_region_o, + output logic [7:0] axi_master_ar_len_o, + output logic [2:0] axi_master_ar_size_o, + output logic [1:0] axi_master_ar_burst_o, + output logic axi_master_ar_lock_o, + output logic [3:0] axi_master_ar_cache_o, + output logic [3:0] axi_master_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] axi_master_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_master_ar_user_o, + input logic axi_master_ar_ready_i, + + // WRITE DATA CHANNEL + output logic axi_master_w_valid_o, + output logic [AXI_DATA_WIDTH-1:0] axi_master_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] axi_master_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] axi_master_w_user_o, + output logic axi_master_w_last_o, + input logic axi_master_w_ready_i, + + // READ DATA CHANNEL + input logic axi_master_r_valid_i, + input logic [AXI_DATA_WIDTH-1:0] axi_master_r_data_i, + input logic [1:0] axi_master_r_resp_i, + input logic axi_master_r_last_i, + input logic [AXI_ID_WIDTH-1:0] axi_master_r_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_master_r_user_i, + output logic axi_master_r_ready_o, + + // WRITE RESPONSE CHANNEL + input logic axi_master_b_valid_i, + input logic [1:0] axi_master_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] axi_master_b_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_master_b_user_i, + output logic axi_master_b_ready_o, + + // BUSY SIGNAL + output logic busy_o + ); + + // SIGNAL DECLARATION + logic s_aw_valid; + logic [AXI_ADDR_WIDTH-1:0] s_aw_addr; + logic [2:0] s_aw_prot; + logic [3:0] s_aw_region; + logic [7:0] s_aw_len; + logic [2:0] s_aw_size; + logic [1:0] s_aw_burst; + logic s_aw_lock; + logic [5:0] s_aw_atop; + logic [3:0] s_aw_cache; + logic [3:0] s_aw_qos; + logic [AXI_ID_WIDTH-1:0] s_aw_id; + logic [AXI_USER_WIDTH-1:0] s_aw_user; + logic s_aw_ready; + + logic s_ar_valid; + logic [AXI_ADDR_WIDTH-1:0] s_ar_addr; + logic [2:0] s_ar_prot; + logic [3:0] s_ar_region; + logic [7:0] s_ar_len; + logic [2:0] s_ar_size; + logic [1:0] s_ar_burst; + logic s_ar_lock; + logic [3:0] s_ar_cache; + logic [3:0] s_ar_qos; + logic [AXI_ID_WIDTH-1:0] s_ar_id; + logic [AXI_USER_WIDTH-1:0] s_ar_user; + logic s_ar_ready; + + logic s_w_valid; + logic [AXI_DATA_WIDTH-1:0] s_w_data; + logic [AXI_STRB_WIDTH-1:0] s_w_strb; + logic [AXI_USER_WIDTH-1:0] s_w_user; + logic s_w_last; + logic s_w_ready; + + logic s_r_valid; + logic [AXI_DATA_WIDTH-1:0] s_r_data; + logic [1:0] s_r_resp; + logic s_r_last; + logic [AXI_ID_WIDTH-1:0] s_r_id; + logic [AXI_USER_WIDTH-1:0] s_r_user; + logic s_r_ready; + + logic s_b_valid; + logic [1:0] s_b_resp; + logic [AXI_ID_WIDTH-1:0] s_b_id; + logic [AXI_USER_WIDTH-1:0] s_b_user; + logic s_b_ready; + + logic s_atop_req; + logic [AXI_ID_WIDTH-1:0] s_atop_id; + logic [AXI_ADDR_WIDTH-1:0] s_atop_add; + + logic s_trans_req; + logic [AXI_ID_WIDTH-1:0] s_trans_id; + logic [AXI_ADDR_WIDTH-1:0] s_trans_add; + + + // PER2AXI REQUEST CHANNEL + per2axi_req_channel + #( + .NB_CORES ( NB_CORES ), + .PER_ID_WIDTH ( PER_ID_WIDTH ), + .PER_ADDR_WIDTH ( PER_ADDR_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + ) + req_channel_i + ( + .clk_i, + .rst_ni, + .per_slave_req_i ( per_slave_req_i ), + .per_slave_add_i ( per_slave_add_i ), + .per_slave_we_i ( per_slave_we_i ), + .per_slave_atop_i ( per_slave_atop_i ), + .per_slave_wdata_i ( per_slave_wdata_i ), + .per_slave_be_i ( per_slave_be_i ), + .per_slave_id_i ( per_slave_id_i ), + .per_slave_gnt_o ( per_slave_gnt_o ), + + .axi_axuser_i ( axi_axuser_i ), + + .axi_master_aw_valid_o ( s_aw_valid ), + .axi_master_aw_addr_o ( s_aw_addr ), + .axi_master_aw_prot_o ( s_aw_prot ), + .axi_master_aw_region_o ( s_aw_region ), + .axi_master_aw_len_o ( s_aw_len ), + .axi_master_aw_size_o ( s_aw_size ), + .axi_master_aw_burst_o ( s_aw_burst ), + .axi_master_aw_lock_o ( s_aw_lock ), + .axi_master_aw_atop_o ( s_aw_atop ), + .axi_master_aw_cache_o ( s_aw_cache ), + .axi_master_aw_qos_o ( s_aw_qos ), + .axi_master_aw_id_o ( s_aw_id ), + .axi_master_aw_user_o ( s_aw_user ), + .axi_master_aw_ready_i ( s_aw_ready ), + + .axi_master_ar_valid_o ( s_ar_valid ), + .axi_master_ar_addr_o ( s_ar_addr ), + .axi_master_ar_prot_o ( s_ar_prot ), + .axi_master_ar_region_o ( s_ar_region ), + .axi_master_ar_len_o ( s_ar_len ), + .axi_master_ar_size_o ( s_ar_size ), + .axi_master_ar_burst_o ( s_ar_burst ), + .axi_master_ar_lock_o ( s_ar_lock ), + .axi_master_ar_cache_o ( s_ar_cache ), + .axi_master_ar_qos_o ( s_ar_qos ), + .axi_master_ar_id_o ( s_ar_id ), + .axi_master_ar_user_o ( s_ar_user ), + .axi_master_ar_ready_i ( s_ar_ready ), + + .axi_master_w_valid_o ( s_w_valid ), + .axi_master_w_data_o ( s_w_data ), + .axi_master_w_strb_o ( s_w_strb ), + .axi_master_w_user_o ( s_w_user ), + .axi_master_w_last_o ( s_w_last ), + .axi_master_w_ready_i ( s_w_ready ), + + .atop_req_o ( s_atop_req ), + .atop_id_o ( s_atop_id ), + .atop_add_o ( s_atop_add ), + + .trans_req_o ( s_trans_req ), + .trans_id_o ( s_trans_id ), + .trans_add_o ( s_trans_add ) + ); + + // PER2AXI RESPONSE CHANNEL + per2axi_res_channel + #( + .NB_CORES ( NB_CORES ), + .PER_ID_WIDTH ( PER_ID_WIDTH ), + .PER_ADDR_WIDTH ( PER_ADDR_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) + res_channel_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .per_slave_r_valid_o ( per_slave_r_valid_o ), + .per_slave_r_opc_o ( per_slave_r_opc_o ), + .per_slave_r_id_o ( per_slave_r_id_o ), + .per_slave_r_rdata_o ( per_slave_r_rdata_o ), + + .axi_xresp_decerr_o ( axi_xresp_decerr_o ), + .axi_xresp_slverr_o ( axi_xresp_slverr_o ), + .axi_xresp_valid_o ( axi_xresp_valid_o ), + + .axi_master_r_valid_i ( s_r_valid ), + .axi_master_r_data_i ( s_r_data ), + .axi_master_r_resp_i ( s_r_resp ), + .axi_master_r_last_i ( s_r_last ), + .axi_master_r_id_i ( s_r_id ), + .axi_master_r_user_i ( s_r_user ), + .axi_master_r_ready_o ( s_r_ready ), + + .axi_master_b_valid_i ( s_b_valid ), + .axi_master_b_resp_i ( s_b_resp ), + .axi_master_b_id_i ( s_b_id ), + .axi_master_b_user_i ( s_b_user ), + .axi_master_b_ready_o ( s_b_ready ), + + .atop_req_i ( s_atop_req ), + .atop_id_i ( s_atop_id ), + .atop_add_i ( s_atop_add ), + + .trans_req_i ( s_trans_req ), + .trans_id_i ( s_trans_id ), + .trans_add_i ( s_trans_add ) + ); + + // BUSY UNIT + per2axi_busy_unit busy_unit_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + // WRITE INTERFACE + .aw_sync_i ( s_aw_valid & s_aw_ready ), + .b_sync_i ( s_b_valid & s_b_ready ), + + // READ INTERFACE + .ar_sync_i ( s_ar_valid & s_ar_ready ), + .r_sync_i ( s_r_valid & s_r_ready & s_r_last ), + + // BUSY SIGNAL + .busy_o ( busy_o ) + ); + + // AXI WRITE ADDRESS CHANNEL BUFFER + axi_aw_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( NB_CORES ) + ) + aw_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( s_aw_valid ), + .slave_addr_i ( s_aw_addr ), + .slave_prot_i ( s_aw_prot ), + .slave_region_i ( s_aw_region ), + .slave_len_i ( s_aw_len ), + .slave_size_i ( s_aw_size ), + .slave_burst_i ( s_aw_burst ), + .slave_lock_i ( s_aw_lock ), + .slave_atop_i ( s_aw_atop ), + .slave_cache_i ( s_aw_cache ), + .slave_qos_i ( s_aw_qos ), + .slave_id_i ( s_aw_id ), + .slave_user_i ( s_aw_user ), + .slave_ready_o ( s_aw_ready ), + + .master_valid_o ( axi_master_aw_valid_o ), + .master_addr_o ( axi_master_aw_addr_o ), + .master_prot_o ( axi_master_aw_prot_o ), + .master_region_o ( axi_master_aw_region_o ), + .master_len_o ( axi_master_aw_len_o ), + .master_size_o ( axi_master_aw_size_o ), + .master_burst_o ( axi_master_aw_burst_o ), + .master_lock_o ( axi_master_aw_lock_o ), + .master_atop_o ( axi_master_aw_atop_o ), + .master_cache_o ( axi_master_aw_cache_o ), + .master_qos_o ( axi_master_aw_qos_o ), + .master_id_o ( axi_master_aw_id_o ), + .master_user_o ( axi_master_aw_user_o ), + .master_ready_i ( axi_master_aw_ready_i ) + ); + + // AXI READ ADDRESS CHANNEL BUFFER + axi_ar_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( NB_CORES ) + ) + ar_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( s_ar_valid ), + .slave_addr_i ( s_ar_addr ), + .slave_prot_i ( s_ar_prot ), + .slave_region_i ( s_ar_region ), + .slave_len_i ( s_ar_len ), + .slave_size_i ( s_ar_size ), + .slave_burst_i ( s_ar_burst ), + .slave_lock_i ( s_ar_lock ), + .slave_cache_i ( s_ar_cache ), + .slave_qos_i ( s_ar_qos ), + .slave_id_i ( s_ar_id ), + .slave_user_i ( s_ar_user ), + .slave_ready_o ( s_ar_ready ), + + .master_valid_o ( axi_master_ar_valid_o ), + .master_addr_o ( axi_master_ar_addr_o ), + .master_prot_o ( axi_master_ar_prot_o ), + .master_region_o ( axi_master_ar_region_o ), + .master_len_o ( axi_master_ar_len_o ), + .master_size_o ( axi_master_ar_size_o ), + .master_burst_o ( axi_master_ar_burst_o ), + .master_lock_o ( axi_master_ar_lock_o ), + .master_cache_o ( axi_master_ar_cache_o ), + .master_qos_o ( axi_master_ar_qos_o ), + .master_id_o ( axi_master_ar_id_o ), + .master_user_o ( axi_master_ar_user_o ), + .master_ready_i ( axi_master_ar_ready_i ) + ); + + // WRITE DATA CHANNEL BUFFER + axi_w_buffer + #( + .DATA_WIDTH ( AXI_DATA_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( NB_CORES ) + ) + w_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( s_w_valid ), + .slave_data_i ( s_w_data ), + .slave_strb_i ( s_w_strb ), + .slave_user_i ( s_w_user ), + .slave_last_i ( s_w_last ), + .slave_ready_o ( s_w_ready ), + + .master_valid_o ( axi_master_w_valid_o ), + .master_data_o ( axi_master_w_data_o ), + .master_strb_o ( axi_master_w_strb_o ), + .master_user_o ( axi_master_w_user_o ), + .master_last_o ( axi_master_w_last_o ), + .master_ready_i ( axi_master_w_ready_i ) + ); + + // READ DATA CHANNEL BUFFER + axi_r_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .DATA_WIDTH ( AXI_DATA_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( 2 ) + ) + r_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( axi_master_r_valid_i ), + .slave_data_i ( axi_master_r_data_i ), + .slave_resp_i ( axi_master_r_resp_i ), + .slave_user_i ( axi_master_r_user_i ), + .slave_id_i ( axi_master_r_id_i ), + .slave_last_i ( axi_master_r_last_i ), + .slave_ready_o ( axi_master_r_ready_o ), + + .master_valid_o ( s_r_valid ), + .master_data_o ( s_r_data ), + .master_resp_o ( s_r_resp ), + .master_user_o ( s_r_user ), + .master_id_o ( s_r_id ), + .master_last_o ( s_r_last ), + .master_ready_i ( s_r_ready ) + ); + + // WRITE RESPONSE CHANNEL BUFFER + axi_b_buffer + #( + .ID_WIDTH ( AXI_ID_WIDTH ), + .USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_DEPTH ( 2 ) + ) + b_buffer_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .slave_valid_i ( axi_master_b_valid_i ), + .slave_resp_i ( axi_master_b_resp_i ), + .slave_id_i ( axi_master_b_id_i ), + .slave_user_i ( axi_master_b_user_i ), + .slave_ready_o ( axi_master_b_ready_o ), + + .master_valid_o ( s_b_valid ), + .master_resp_o ( s_b_resp ), + .master_id_o ( s_b_id ), + .master_user_o ( s_b_user ), + .master_ready_i ( s_b_ready ) + ); + +endmodule diff --git a/hw/deps/per2axi/src/per2axi_busy_unit.sv b/hw/deps/per2axi/src/per2axi_busy_unit.sv new file mode 100644 index 0000000..315567e --- /dev/null +++ b/hw/deps/per2axi/src/per2axi_busy_unit.sv @@ -0,0 +1,72 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module per2axi_busy_unit +( + input logic clk_i, + input logic rst_ni, + + // WRITE INTERFACE + input logic aw_sync_i, + input logic b_sync_i, + + // READ INTERFACE + input logic ar_sync_i, + input logic r_sync_i, + + // BUSY SIGNAL + output logic busy_o +); + + logic [3:0] s_aw_trans_count; + logic [3:0] s_ar_trans_count; + + //COUNTER FOR NUMBER OF AW TRANSACTIONS + always_ff @ (posedge clk_i, negedge rst_ni) + begin + if(rst_ni == 1'b0) + s_aw_trans_count <= '0; + else + if ( aw_sync_i == 1'b1 && b_sync_i == 1'b0 ) + s_aw_trans_count <= s_aw_trans_count+1; + else + if ( aw_sync_i == 1'b0 && b_sync_i == 1'b1 ) + s_aw_trans_count <= s_aw_trans_count-1; + else + s_aw_trans_count <= s_aw_trans_count; + end + + //COUNTER FOR NUMBER OF AR TRANSACTIONS + always_ff @ (posedge clk_i, negedge rst_ni) + begin + if(rst_ni == 1'b0) + s_ar_trans_count <= '0; + else + if ( ar_sync_i == 1'b1 && r_sync_i == 1'b0 ) + s_ar_trans_count <= s_ar_trans_count+1; + else + if ( ar_sync_i == 1'b0 && r_sync_i == 1'b1 ) + s_ar_trans_count <= s_ar_trans_count-1; + else + s_ar_trans_count <= s_ar_trans_count; + end + + // GENERATION OF BUSY SIGNAL + always_comb + begin + if ( s_ar_trans_count == 0 && s_aw_trans_count == 0 ) + busy_o = 1'b0; + else + busy_o = 1'b1; + end + +endmodule diff --git a/hw/deps/per2axi/src/per2axi_req_channel.sv b/hw/deps/per2axi/src/per2axi_req_channel.sv new file mode 100644 index 0000000..6dce9ad --- /dev/null +++ b/hw/deps/per2axi/src/per2axi_req_channel.sv @@ -0,0 +1,309 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +import riscv_defines::*; + +module per2axi_req_channel +#( + // PARAMETERS + parameter NB_CORES = 4, + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3, + // LOCAL PARAMETERS --> DO NOT OVERRIDE + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 // DO NOT OVERRIDE +) +( + input logic clk_i, + input logic rst_ni, + + // PERIPHERAL INTERCONNECT SLAVE + //*************************************** + //REQUEST CHANNEL + input logic per_slave_req_i, + input logic [PER_ADDR_WIDTH-1:0] per_slave_add_i, + input logic per_slave_we_i, + input logic [5:0] per_slave_atop_i, + input logic [31:0] per_slave_wdata_i, + input logic [3:0] per_slave_be_i, + input logic [PER_ID_WIDTH-1:0] per_slave_id_i, + output logic per_slave_gnt_o, + + // TRYX CTRL + input logic [NB_CORES-1:0][AXI_USER_WIDTH-1:0] axi_axuser_i, + + // AXI4 MASTER + //*************************************** + // WRITE ADDRESS CHANNEL + output logic axi_master_aw_valid_o, + output logic [AXI_ADDR_WIDTH-1:0] axi_master_aw_addr_o, + output logic [2:0] axi_master_aw_prot_o, + output logic [3:0] axi_master_aw_region_o, + output logic [7:0] axi_master_aw_len_o, + output logic [2:0] axi_master_aw_size_o, + output logic [1:0] axi_master_aw_burst_o, + output logic axi_master_aw_lock_o, + output logic [5:0] axi_master_aw_atop_o, + output logic [3:0] axi_master_aw_cache_o, + output logic [3:0] axi_master_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] axi_master_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_master_aw_user_o, + input logic axi_master_aw_ready_i, + + // READ ADDRESS CHANNEL + output logic axi_master_ar_valid_o, + output logic [AXI_ADDR_WIDTH-1:0] axi_master_ar_addr_o, + output logic [2:0] axi_master_ar_prot_o, + output logic [3:0] axi_master_ar_region_o, + output logic [7:0] axi_master_ar_len_o, + output logic [2:0] axi_master_ar_size_o, + output logic [1:0] axi_master_ar_burst_o, + output logic axi_master_ar_lock_o, + output logic [3:0] axi_master_ar_cache_o, + output logic [3:0] axi_master_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] axi_master_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] axi_master_ar_user_o, + input logic axi_master_ar_ready_i, + + // WRITE DATA CHANNEL + output logic axi_master_w_valid_o, + output logic [AXI_DATA_WIDTH-1:0] axi_master_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] axi_master_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] axi_master_w_user_o, + output logic axi_master_w_last_o, + input logic axi_master_w_ready_i, + + // CONTROL SIGNALS + output logic atop_req_o, + output logic [AXI_ID_WIDTH-1:0] atop_id_o, + output logic [AXI_ADDR_WIDTH-1:0] atop_add_o, + + output logic trans_req_o, + output logic [AXI_ID_WIDTH-1:0] trans_id_o, + output logic [AXI_ADDR_WIDTH-1:0] trans_add_o +); + + integer i; + + // AWATOP signal for AXI-5 + // TODO: When upgrading to AXI-5 declare as output + logic [5:0] awatop; + + // Input data signal + logic [31:0] per_slave_wdata; + logic inv_wdata; + + // Atomic operation defines + parameter AWATOP_SWAP = 6'b110000; + parameter AWATOP_COMPARE = 6'b110001; + + parameter AWATOP_STORE = 3'b010; + parameter AWATOP_LOAD = 3'b100; + + parameter AWATOP_ADD = 3'b000; + parameter AWATOP_CLR = 3'b001; + parameter AWATOP_XOR = 3'b010; + parameter AWATOP_SET = 3'b011; + parameter AWATOP_SMAX = 3'b100; + parameter AWATOP_SMIN = 3'b101; + parameter AWATOP_UMAX = 3'b110; + parameter AWATOP_UMIN = 3'b111; + + assign axi_master_aw_atop_o = awatop; + + // AXI REQUEST GENERATION + always_comb + begin + axi_master_ar_valid_o = 1'b0; + axi_master_aw_valid_o = 1'b0; + axi_master_w_valid_o = 1'b0; + axi_master_w_last_o = 1'b0; + + if (per_slave_req_i == 1'b1 && // REQUEST FROM PERIPHERAL INTERCONNECT + per_slave_we_i == 1'b0 && // WRITE OPERATION + axi_master_aw_ready_i == 1'b1 && // AXI WRITE ADDRESS CHANNEL AVAILABLE + axi_master_w_ready_i == 1'b1 ) // AXI WRITE DATA CHANNEL AVAILABLE + begin + axi_master_aw_valid_o = 1'b1; + axi_master_w_valid_o = 1'b1; + axi_master_w_last_o = 1'b1; + end + else + if (per_slave_req_i == 1'b1 && // REQUEST FROM PERIPHERAL INTERCONNECT + per_slave_we_i == 1'b1 && // READ OPERATION + axi_master_ar_ready_i == 1'b1) // AXI WRITE ADDRESS CHANNEL AVAILABLE + begin + axi_master_ar_valid_o = 1'b1; + end + end + + // AXI ATOMIC ACCESS LOCK GENERATION + always_comb + begin + axi_master_aw_lock_o = 1'b0; + axi_master_ar_lock_o = 1'b0; + awatop = 6'b000000; + inv_wdata = 1'b0; + + if (per_slave_atop_i[5] == 1'b1) begin + unique case (per_slave_atop_i[4:0]) + AMO_LR: begin // ATOMIC LOAD-RESERVED OPERATION + axi_master_ar_lock_o = 1'b1; + end + AMO_SC: begin // ATOMIC STORE-CONDITIONAL OPERATION + axi_master_aw_lock_o = 1'b1; + end + AMO_SWAP: begin + awatop = AWATOP_SWAP; + end + AMO_ADD: begin + awatop = {AWATOP_LOAD, AWATOP_ADD}; + end + AMO_XOR: begin + awatop = {AWATOP_LOAD, AWATOP_XOR}; + end + AMO_AND: begin + awatop = {AWATOP_LOAD, AWATOP_CLR}; + inv_wdata = 1'b1; // Invert data to emulate an AND with a clear + end + AMO_OR: begin + awatop = {AWATOP_LOAD, AWATOP_SET}; + end + AMO_MIN: begin + awatop = {AWATOP_LOAD, AWATOP_SMIN}; + end + AMO_MAX: begin + awatop = {AWATOP_LOAD, AWATOP_SMAX}; + end + AMO_MINU: begin + awatop = {AWATOP_LOAD, AWATOP_UMIN}; + end + AMO_MAXU: begin + awatop = {AWATOP_LOAD, AWATOP_UMAX}; + end + default : begin end + endcase + end + end + + // AXI ADDRESS GENERATION + assign axi_master_aw_addr_o = per_slave_add_i; + assign axi_master_ar_addr_o = per_slave_add_i; + + // AXI ID GENERATION - ONEHOT TO BIN DECODING + always_comb + begin + axi_master_aw_id_o = '0; + axi_master_ar_id_o = '0; + for ( i=0; i per_slave_be_i[per_slave_add_i[1:0]]) + else $error("Byte enable of addressed byte must be active"); + logic [1:0] be_trailing_zeros; + lzc #( + .WIDTH (4), + .MODE (1'b0) + ) i_lzc_be_trailing ( + .in_i (per_slave_be_i), + .cnt_o (be_trailing_zeros), + .empty_o (/* unused */) + ); + assume property (@(posedge clk_i) per_slave_req_i + |-> per_slave_add_i[1:0] == be_trailing_zeros) + else $error("No byte enable below addressed byte may be active!"); + `endif + `endif + + // use FIXED burst type, length is anyway 0 + assign axi_master_aw_burst_o = 2'b00; + assign axi_master_ar_burst_o = 2'b00; + + // TRANSACTION REQUEST GENERATION + assign trans_req_o = axi_master_ar_valid_o; + assign trans_id_o = axi_master_ar_id_o; + assign trans_add_o = axi_master_ar_addr_o; + + assign atop_req_o = (axi_master_aw_atop_o[5:3] == AWATOP_STORE) ? 1'b0 : |axi_master_aw_atop_o; + assign atop_id_o = axi_master_aw_id_o; + assign atop_add_o = axi_master_aw_addr_o; + + // UNUSED SIGNALS + assign axi_master_aw_prot_o = '0; + assign axi_master_aw_region_o = '0; + assign axi_master_aw_len_o = '0; + assign axi_master_aw_cache_o = '0; + assign axi_master_aw_qos_o = 4'b0001; + assign axi_master_aw_user_o = axi_axuser_i[axi_master_aw_id_o]; + + assign axi_master_ar_prot_o = '0; + assign axi_master_ar_region_o = '0; + assign axi_master_ar_len_o = '0; + assign axi_master_ar_cache_o = '0; + assign axi_master_ar_qos_o = 4'b0001; + assign axi_master_ar_user_o = axi_axuser_i[axi_master_aw_id_o]; + + assign axi_master_w_user_o = '0; + +endmodule diff --git a/hw/deps/per2axi/src/per2axi_res_channel.sv b/hw/deps/per2axi/src/per2axi_res_channel.sv new file mode 100644 index 0000000..a5e8c23 --- /dev/null +++ b/hw/deps/per2axi/src/per2axi_res_channel.sv @@ -0,0 +1,213 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module per2axi_res_channel +#( + // PARAMETERS + parameter NB_CORES = 4, + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 3 +) +( + input logic clk_i, + input logic rst_ni, + + // PERIPHERAL INTERCONNECT SLAVE + //*************************************** + //RESPONSE CHANNEL + output logic per_slave_r_valid_o, + output logic per_slave_r_opc_o, + output logic [PER_ID_WIDTH-1:0] per_slave_r_id_o, + output logic [31:0] per_slave_r_rdata_o, + + // TRYX CTRL + output logic [NB_CORES-1:0] axi_xresp_decerr_o, + output logic [NB_CORES-1:0] axi_xresp_slverr_o, + output logic [NB_CORES-1:0] axi_xresp_valid_o, + + // AXI4 MASTER + //*************************************** + // READ DATA CHANNEL + input logic axi_master_r_valid_i, + input logic [AXI_DATA_WIDTH-1:0] axi_master_r_data_i, + input logic [1:0] axi_master_r_resp_i, + input logic axi_master_r_last_i, + input logic [AXI_ID_WIDTH-1:0] axi_master_r_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_master_r_user_i, + output logic axi_master_r_ready_o, + + // WRITE RESPONSE CHANNEL + input logic axi_master_b_valid_i, + input logic [1:0] axi_master_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] axi_master_b_id_i, + input logic [AXI_USER_WIDTH-1:0] axi_master_b_user_i, + output logic axi_master_b_ready_o, + + // CONTROL SIGNALS + input logic atop_req_i, + input logic [AXI_ID_WIDTH-1:0] atop_id_i, + input logic [AXI_ADDR_WIDTH-1:0] atop_add_i, + + input logic trans_req_i, + input logic [AXI_ID_WIDTH-1:0] trans_id_i, + input logic [AXI_ADDR_WIDTH-1:0] trans_add_i +); + + logic [31:0] s_per_slave_r_data; + logic [PER_ID_WIDTH-1:0] s_read_add_buf; + + typedef enum logic [1:0] { NONE, REQUEST, WAIT_R, WAIT_B } atop_res_t; + atop_res_t [PER_ID_WIDTH-1:0] atop_state_d, atop_state_q; + + // Handle responses. + always_comb begin + axi_master_b_ready_o = 1'b0; + axi_master_r_ready_o = 1'b0; + axi_xresp_decerr_o = '0; + axi_xresp_slverr_o = '0; + axi_xresp_valid_o = '0; + per_slave_r_id_o = '0; + per_slave_r_opc_o = '0; + per_slave_r_rdata_o = '0; + per_slave_r_valid_o = 1'b0; + + if (axi_master_r_valid_i) begin + axi_master_r_ready_o = 1'b1; + per_slave_r_id_o[axi_master_r_id_i] = 1'b1; + per_slave_r_rdata_o = s_per_slave_r_data; + per_slave_r_valid_o = 1'b1; + if (axi_master_r_resp_i[1]) begin // error + axi_xresp_valid_o[axi_master_r_id_i] = 1'b1; + if (axi_master_r_resp_i[0]) begin // decoding error + axi_xresp_decerr_o[axi_master_r_id_i] = 1'b1; + end else begin // slave error (e.g. RAB miss) + axi_xresp_slverr_o[axi_master_r_id_i] = 1'b1; + end + end + end else if (axi_master_b_valid_i) begin + axi_master_b_ready_o = 1'b1; + if (atop_state_q[axi_master_b_id_i] == NONE) begin + per_slave_r_valid_o = 1'b1; + per_slave_r_id_o[axi_master_b_id_i] = 1'b1; + + // Forward response/error to core. + // axi_master_b_resp_i[1:0] -> per_slave_r_rdata_o[1:0] + // 00 -> 01, 01 -> 00, 10 -> 10, 11 -> 11 + per_slave_r_rdata_o + = {30'b0, axi_master_b_resp_i[1], axi_master_b_resp_i[1] ~^ axi_master_b_resp_i[0]}; + if (axi_master_b_resp_i[1]) begin // error + axi_xresp_valid_o [axi_master_b_id_i] = 1'b1; + if (axi_master_b_resp_i[0]) begin // decoding error + axi_xresp_decerr_o[axi_master_b_id_i] = 1'b1; + end else begin // slave error (e.g. RAB miss) + axi_xresp_slverr_o[axi_master_b_id_i] = 1'b1; + end + end + end + end + end + + // Atomic memory operations + + generate + for (genvar i = 0; i < PER_ID_WIDTH; i++) begin + always_comb begin + atop_state_d[i] = atop_state_q[i]; + + unique case (atop_state_q[i]) + NONE: begin + if (atop_req_i && (atop_id_i == i)) begin + atop_state_d[i] = REQUEST; + end + end + + REQUEST: begin + if (axi_master_r_valid_i && axi_master_r_ready_o && (axi_master_r_id_i == i)) begin + atop_state_d[i] = WAIT_B; + end + if (axi_master_b_valid_i && axi_master_b_ready_o && (axi_master_b_id_i == i)) begin + atop_state_d[i] = WAIT_R; + end + if (axi_master_r_valid_i && axi_master_r_ready_o && (axi_master_r_id_i == i) && + axi_master_b_valid_i && axi_master_b_ready_o && (axi_master_b_id_i == i)) begin + atop_state_d[i] = NONE; + end + end + + WAIT_R: begin + if (axi_master_r_valid_i && axi_master_r_ready_o && (axi_master_r_id_i == i)) begin + atop_state_d[i] = NONE; + end + end + + WAIT_B: begin + if (axi_master_b_valid_i && axi_master_b_ready_o && (axi_master_b_id_i == i)) begin + atop_state_d[i] = NONE; + end + end + + default : /* default */; + endcase + + + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + atop_state_q[i] <= NONE; + end else begin + atop_state_q[i] <= atop_state_d[i]; + end + end + + end + endgenerate + + + // STORES REQUEST ADDRESS BIT 2 ONLY IF A READ OPERATION OCCURS + always_ff @ (posedge clk_i, negedge rst_ni) + begin + if(rst_ni == 1'b0) + begin + s_read_add_buf <= '0; + end + else + begin + if(trans_req_i == 1'b1) + begin + s_read_add_buf[trans_id_i] <= trans_add_i[2]; + end + if(atop_req_i == 1'b1) + begin + s_read_add_buf[atop_id_i] <= atop_add_i[2]; + end + end + end + + // FORWARD 32-bit AXI MSBs or LSBs TO THE PERIPHERAL INTERCONNECT DEPENDING ON THE REQUEST ADDRESS + always_comb + begin + if ( s_read_add_buf[axi_master_r_id_i] == 1'b0 ) + begin + s_per_slave_r_data = axi_master_r_data_i[31:0]; + end + else + begin + s_per_slave_r_data = axi_master_r_data_i[63:32]; + end + end + +endmodule diff --git a/hw/deps/pulp_cluster/packages/apu_package.sv b/hw/deps/pulp_cluster/packages/apu_package.sv new file mode 100644 index 0000000..32aeec0 --- /dev/null +++ b/hw/deps/pulp_cluster/packages/apu_package.sv @@ -0,0 +1,52 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * apu_package.sv + * Michael Gautschi + */ + +package apu_package; + + import apu_core_package::*; + + parameter FPU = 1; + + parameter SHARED_FP = 1; + parameter SHARED_DSP_MULT = SHARED_FP ? 1 : 0; // only available with shared FPU + parameter SHARED_INT_DIV = SHARED_FP ? 0 : 0; // only available with shared FPU + + // Shared div/sqrt implementation 0=none, 1=pipelined version, 2=iterative shared unit + parameter SHARED_FP_DIVSQRT = 2; + + //////////////////////////////////////////////////////////////////////////////////////// + // IMPORTANT!! // + //////////////////////////////////////////////////////////////////////////////////////// + // THESE PARAMETERS HAVE TO MATCH THE ones in ips/riscv/includes/apu_core_package.sv // + //////////////////////////////////////////////////////////////////////////////////////// + + // CPU side / general params + parameter NARGS_CPU = 3; + parameter WOP_CPU = 6; + parameter NUSFLAGS_CPU = 5; + parameter NDSFLAGS_CPU = 15; + ///////////////////////////////////////////////////////////////////////////// + // until here // + ///////////////////////////////////////////////////////////////////////////// + + // FP-general + parameter APUTYPE_FP = (SHARED_FP) ? SHARED_DSP_MULT + SHARED_INT_MULT + SHARED_INT_DIV : 0; + + // generated values + parameter C_APUTYPES = (SHARED_FP) ? (SHARED_FP_DIVSQRT==1) ? APUTYPE_FP+6 : (SHARED_FP_DIVSQRT==2) ? APUTYPE_FP+5 : APUTYPE_FP+4 : SHARED_DSP_MULT + SHARED_INT_DIV + SHARED_INT_MULT; + + parameter WAPUTYPE = $clog2(C_APUTYPES); + +endpackage diff --git a/hw/deps/pulp_cluster/packages/pulp_cluster_package.sv b/hw/deps/pulp_cluster/packages/pulp_cluster_package.sv new file mode 100644 index 0000000..def2e22 --- /dev/null +++ b/hw/deps/pulp_cluster/packages/pulp_cluster_package.sv @@ -0,0 +1,43 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * pulp_cluster_package.sv + * Davide Rossi + * Michael Gautschi + */ + +package pulp_cluster_package; + + parameter NB_SPERIPH_PLUGS_EU = 2; + + // position of peripherals on slave port of periph interconnect + parameter SPER_EOC_ID = 0; + parameter SPER_TIMER_ID = 1; + parameter SPER_EVENT_U_ID = 2; + parameter SPER_HWPE_ID = 4; + parameter SPER_ICACHE_CTRL = 5; + parameter SPER_DMA_ID = 6; + parameter SPER_EXT_ID = 7; + + // if set to 1, then instantiate APU in the cluster + parameter APU_CLUSTER = 0; + + // // if set to 1, the 0x0000_0000 to 0x0040_0000 is the alias of the current cluster address space (eg cluster 0 is from 0x1000_0000 to 0x1040_0000) + // parameter CLUSTER_ALIAS = 1; + + // // if set to 1, the DEMUX peripherals (EU, MCHAN) are placed right before the test and set region. + // // This will steal 16KB from the 1MB TCDM reegion. + // // EU is mapped from 0x10100000 - 0x400 + // // MCHAN regs are mapped from 0x10100000 - 0x800 + // // remember to change the defines in the pulp.h as well to be coherent with this approach + // parameter DEM_PER_BEFORE_TCDM_TS = 0; + +endpackage diff --git a/hw/deps/pulp_cluster/rtl/axi2per_wrap.sv b/hw/deps/pulp_cluster/rtl/axi2per_wrap.sv new file mode 100644 index 0000000..0e0d19c --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/axi2per_wrap.sv @@ -0,0 +1,120 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * axi2per_wrap.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +module axi2per_wrap +#( + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 6, + parameter BUFFER_DEPTH = 2, + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 +) +( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input logic [5:0] cluster_id_i, + AXI_BUS.Slave axi_slave, + XBAR_TCDM_BUS.Master periph_master, + output logic busy_o +); + + axi2per #( + .PER_ADDR_WIDTH ( PER_ADDR_WIDTH ), + .PER_ID_WIDTH ( PER_ID_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH ), + .BUFFER_DEPTH ( BUFFER_DEPTH ) + ) axi2per_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .cluster_id_i ( cluster_id_i ), + + .axi_slave_aw_valid_i ( axi_slave.aw_valid ), + .axi_slave_aw_addr_i ( axi_slave.aw_addr ), + .axi_slave_aw_prot_i ( axi_slave.aw_prot ), + .axi_slave_aw_region_i ( axi_slave.aw_region ), + .axi_slave_aw_len_i ( axi_slave.aw_len ), + .axi_slave_aw_size_i ( axi_slave.aw_size ), + .axi_slave_aw_burst_i ( axi_slave.aw_burst ), + .axi_slave_aw_lock_i ( axi_slave.aw_lock ), + .axi_slave_aw_atop_i ( axi_slave.aw_atop ), + .axi_slave_aw_cache_i ( axi_slave.aw_cache ), + .axi_slave_aw_qos_i ( axi_slave.aw_qos ), + .axi_slave_aw_id_i ( axi_slave.aw_id ), + .axi_slave_aw_user_i ( axi_slave.aw_user ), + .axi_slave_aw_ready_o ( axi_slave.aw_ready ), + + .axi_slave_ar_valid_i ( axi_slave.ar_valid ), + .axi_slave_ar_addr_i ( axi_slave.ar_addr ), + .axi_slave_ar_prot_i ( axi_slave.ar_prot ), + .axi_slave_ar_region_i ( axi_slave.ar_region ), + .axi_slave_ar_len_i ( axi_slave.ar_len ), + .axi_slave_ar_size_i ( axi_slave.ar_size ), + .axi_slave_ar_burst_i ( axi_slave.ar_burst ), + .axi_slave_ar_lock_i ( axi_slave.ar_lock ), + .axi_slave_ar_cache_i ( axi_slave.ar_cache ), + .axi_slave_ar_qos_i ( axi_slave.ar_qos ), + .axi_slave_ar_id_i ( axi_slave.ar_id ), + .axi_slave_ar_user_i ( axi_slave.ar_user ), + .axi_slave_ar_ready_o ( axi_slave.ar_ready ), + + .axi_slave_w_valid_i ( axi_slave.w_valid ), + .axi_slave_w_data_i ( axi_slave.w_data ), + .axi_slave_w_strb_i ( axi_slave.w_strb ), + .axi_slave_w_user_i ( axi_slave.w_user ), + .axi_slave_w_last_i ( axi_slave.w_last ), + .axi_slave_w_ready_o ( axi_slave.w_ready ), + + .axi_slave_r_valid_o ( axi_slave.r_valid ), + .axi_slave_r_data_o ( axi_slave.r_data ), + .axi_slave_r_resp_o ( axi_slave.r_resp ), + .axi_slave_r_last_o ( axi_slave.r_last ), + .axi_slave_r_id_o ( axi_slave.r_id ), + .axi_slave_r_user_o ( axi_slave.r_user ), + .axi_slave_r_ready_i ( axi_slave.r_ready ), + + .axi_slave_b_valid_o ( axi_slave.b_valid ), + .axi_slave_b_resp_o ( axi_slave.b_resp ), + .axi_slave_b_id_o ( axi_slave.b_id ), + .axi_slave_b_user_o ( axi_slave.b_user ), + .axi_slave_b_ready_i ( axi_slave.b_ready ), + + .per_master_req_o ( periph_master.req ), + .per_master_add_o ( periph_master.add ), + .per_master_we_no ( periph_master.wen ), + .per_master_atop_o ( /* unused */ ), + .per_master_wdata_o ( periph_master.wdata ), + .per_master_be_o ( periph_master.be ), + .per_master_gnt_i ( periph_master.gnt ), + + .per_master_r_valid_i ( periph_master.r_valid ), + .per_master_r_opc_i ( periph_master.r_opc ), + .per_master_r_rdata_i ( periph_master.r_rdata ), + + .busy_o(busy_o) + ); + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/cluster_bus_wrap.sv b/hw/deps/pulp_cluster/rtl/cluster_bus_wrap.sv new file mode 100644 index 0000000..8b000e8 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/cluster_bus_wrap.sv @@ -0,0 +1,121 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * cluster_bus_wrap.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + * Andreas Kurth + */ + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module cluster_bus_wrap +#( + parameter NB_CORES = 4 , + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_ID_IN_WIDTH = 4 , + parameter AXI_ID_OUT_WIDTH = 6 , + parameter AXI_USER_WIDTH = 6 +) +( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input logic [5:0] cluster_id_i, + + AXI_BUS.Slave data_slave, + AXI_BUS.Slave dma_slave, + AXI_BUS.Slave ext_slave, + + AXI_BUS.Master tcdm_master, + AXI_BUS.Master periph_master, + AXI_BUS.Master ext_master +); + + localparam int unsigned NumRules = 2; + typedef axi_pkg::xbar_rule_32_t xbar_rule_t; + axi_pkg::xbar_rule_32_t [NumRules-1:0] addr_map; + logic [31:0] cluster_base_addr; + assign cluster_base_addr = 32'h1000_0000 + (cluster_id_i << 22); + assign addr_map = '{ + '{ // TCDM + start_addr: cluster_base_addr + 24'h00_0000, + end_addr: cluster_base_addr + 24'h10_0000, + idx: 0 + }, + '{ // Peripherals + start_addr: cluster_base_addr + 24'h20_0000, + end_addr: cluster_base_addr + 24'h40_0000, + idx: 1 + } + }; + localparam NumMstPorts = 3; + localparam NumSlvPorts = 3; + /* verilator lint_off WIDTHCONCAT */ + localparam axi_pkg::xbar_cfg_t XbarCfg = '{ + NoSlvPorts: NumSlvPorts, + NoMstPorts: NumMstPorts, + MaxMstTrans: 16, + MaxSlvTrans: 32, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, + AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, + AxiAddrWidth: AXI_ADDR_WIDTH, + AxiDataWidth: AXI_DATA_WIDTH, + NoAddrRules: NumRules + }; + /* verilator lint_on WIDTHCONCAT */ + + AXI_BUS #( + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_OUT_WIDTH), + .AXI_USER_WIDTH(AXI_USER_WIDTH) + ) mst_ports [2:0] (); + + AXI_BUS #( + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_IN_WIDTH), + .AXI_USER_WIDTH(AXI_USER_WIDTH) + ) slv_ports [2:0] (); + + `AXI_ASSIGN (ext_master, mst_ports[2]) + `AXI_ASSIGN (periph_master, mst_ports[1]) + `AXI_ASSIGN (tcdm_master, mst_ports[0]) + + `AXI_ASSIGN (slv_ports[2], data_slave) + `AXI_ASSIGN (slv_ports[1], dma_slave) + `AXI_ASSIGN (slv_ports[0], ext_slave) + + logic [$clog2(NumMstPorts)-1:0] default_mst_port; + assign default_mst_port = 2; // default to external master + axi_xbar_intf #( + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .Cfg ( XbarCfg ), + .rule_t ( xbar_rule_t ) + ) i_axi_xbar ( + .clk_i, + .rst_ni, + .test_i ( test_en_i ), + .slv_ports ( slv_ports ), + .mst_ports ( mst_ports ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '1 ), + .default_mst_port_i ( {NumSlvPorts{default_mst_port}} ) + ); + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/cluster_event_map.sv b/hw/deps/pulp_cluster/rtl/cluster_event_map.sv new file mode 100644 index 0000000..a204154 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/cluster_event_map.sv @@ -0,0 +1,58 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * cluster_event_map.sv + * Florian Glaser + */ + +module cluster_event_map +#( + parameter NB_CORES = 4 +) +( + // events generated inside event unit + input logic [NB_CORES-1:0][7:0] sw_events_i, + input logic [NB_CORES-1:0] barrier_events_i, + input logic [NB_CORES-1:0] mutex_events_i, + input logic [NB_CORES-1:0] dispatch_events_i, + input logic periph_fifo_event_i, + + // events from cluster blocks + input logic [NB_CORES-1:0][3:0] acc_events_i, + input logic [NB_CORES-1:0][1:0] dma_events_i, + input logic [NB_CORES-1:0][1:0] timer_events_i, + input logic [NB_CORES-1:0][31:0] cluster_events_i, + + output logic [NB_CORES-1:0][31:0] events_mapped_o +); + + genvar I; + + generate + for ( I = 0; I < NB_CORES; I++ ) begin : CL_EVENT_MAP + assign events_mapped_o[I][31:28] = '0; + assign events_mapped_o[I][27] = periph_fifo_event_i; + assign events_mapped_o[I][26:24] = '0; + assign events_mapped_o[I][23:22] = cluster_events_i[I][1:0]; + assign events_mapped_o[I][21:19] = '0; + + assign events_mapped_o[I][18] = dispatch_events_i[I]; + assign events_mapped_o[I][17] = mutex_events_i[I]; + assign events_mapped_o[I][16] = barrier_events_i[I]; + + assign events_mapped_o[I][15:12] = acc_events_i[I]; + assign events_mapped_o[I][11:10] = timer_events_i[I]; + assign events_mapped_o[I][9:8] = dma_events_i[I]; + assign events_mapped_o[I][7:0] = sw_events_i[I]; + end + endgenerate + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/cluster_interconnect_wrap.sv b/hw/deps/pulp_cluster/rtl/cluster_interconnect_wrap.sv new file mode 100644 index 0000000..3518ad4 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/cluster_interconnect_wrap.sv @@ -0,0 +1,672 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * cluster_interconnect_wrap.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + * Thomas Benz + */ + +module cluster_interconnect_wrap +#( + parameter NB_CORES = 8, + parameter NB_HWACC_PORTS = 4, + parameter NB_DMAS = 4, + parameter NB_EXT = 4, + parameter NB_MPERIPHS = 1, + parameter NB_TCDM_BANKS = 16, + parameter NB_SPERIPHS = 3, + parameter DATA_WIDTH = 32, + parameter ADDR_WIDTH = 32, + parameter BE_WIDTH = DATA_WIDTH/8, + //TCDM PARAMETERS + parameter TEST_SET_BIT = 20, + parameter ADDR_MEM_WIDTH = 11, + parameter LOG_CLUSTER = 5, + parameter PE_ROUTING_LSB = 16, + parameter PE_ROUTING_MSB = 19, + parameter CLUSTER_ALIAS = 1'b0, + parameter CLUSTER_ALIAS_BASE = 12'h000 +) +( + input logic clk_i, + input logic rst_ni, + XBAR_TCDM_BUS.Slave core_tcdm_slave[NB_CORES+NB_HWACC_PORTS-1:0], + input logic [NB_CORES-1:0][5:0] core_tcdm_slave_atop, + XBAR_PERIPH_BUS.Slave core_periph_slave[NB_CORES-1:0], + input logic [NB_CORES-1:0][5:0] core_periph_slave_atop, + XBAR_TCDM_BUS.Slave ext_slave[NB_EXT-1:0], + input logic [NB_EXT-1:0][5:0] ext_slave_atop, + XBAR_TCDM_BUS.Slave dma_slave[NB_DMAS-1:0], + XBAR_TCDM_BUS.Slave mperiph_slave[NB_MPERIPHS-1:0], + TCDM_BANK_MEM_BUS.Master tcdm_sram_master[NB_TCDM_BANKS-1:0], + XBAR_PERIPH_BUS.Master speriph_master[NB_SPERIPHS-1:0], + output logic [NB_SPERIPHS-1:0][5:0] speriph_master_atop, + input logic [1:0] TCDM_arb_policy_i, + WIDE_DMA_TCDM_BUS.Slave s_wide_dma_a_superbanks, + WIDE_DMA_TCDM_BUS.Slave s_wide_dma_b_superbanks +); + + localparam TCDM_ID_WIDTH = NB_CORES+NB_DMAS+NB_EXT+NB_HWACC_PORTS; + + localparam DMA_DATA_WIDTH = 512; + localparam DMA_ADDR_WIDTH = 64; + localparam BANKS_PER_SUPERBANK = DMA_DATA_WIDTH / DATA_WIDTH; + localparam NB_SUPERBANKS = NB_TCDM_BANKS / BANKS_PER_SUPERBANK; + + // DMA --> LOGARITHMIC INTERCONNECT BUS SIGNALS + logic [NB_EXT+NB_DMAS-1:0][DATA_WIDTH-1:0] s_dma_bus_wdata; + logic [NB_EXT+NB_DMAS-1:0][ADDR_WIDTH-1:0] s_dma_bus_add; + logic [NB_EXT+NB_DMAS-1:0] s_dma_bus_req; + logic [NB_EXT+NB_DMAS-1:0] s_dma_bus_wen; + logic [NB_EXT+NB_DMAS-1:0][BE_WIDTH-1:0] s_dma_bus_be; + logic [NB_EXT+NB_DMAS-1:0] s_dma_bus_gnt; + logic [NB_EXT+NB_DMAS-1:0][DATA_WIDTH-1:0] s_dma_bus_r_rdata; + logic [NB_EXT+NB_DMAS-1:0] s_dma_bus_r_valid; + + // MASTER PERIPHERALS --> PERIPHERAL INTERCONNECT BUS SIGNALS + logic [NB_MPERIPHS-1:0][DATA_WIDTH-1:0] s_mperiph_bus_wdata; + logic [NB_MPERIPHS-1:0][ADDR_WIDTH-1:0] s_mperiph_bus_add; + logic [NB_MPERIPHS-1:0] s_mperiph_bus_req; + logic [NB_MPERIPHS-1:0] s_mperiph_bus_wen; + logic [NB_MPERIPHS-1:0][BE_WIDTH-1:0] s_mperiph_bus_be; + logic [NB_MPERIPHS-1:0] s_mperiph_bus_gnt ; + logic [NB_MPERIPHS-1:0] s_mperiph_bus_r_opc; + logic [NB_MPERIPHS-1:0][DATA_WIDTH-1:0] s_mperiph_bus_r_rdata; + logic [NB_MPERIPHS-1:0] s_mperiph_bus_r_valid; + + // DEMUX --> LOGARITHMIC INTERCONNECT BUS SIGNALS + logic [NB_CORES+NB_HWACC_PORTS-1:0][DATA_WIDTH-1:0] s_core_tcdm_bus_wdata; + logic [NB_CORES+NB_HWACC_PORTS-1:0][ADDR_WIDTH-1:0] s_core_tcdm_bus_add; + logic [NB_CORES+NB_HWACC_PORTS-1:0] s_core_tcdm_bus_req; + logic [NB_CORES+NB_HWACC_PORTS-1:0] s_core_tcdm_bus_wen; + logic [NB_CORES+NB_HWACC_PORTS-1:0][BE_WIDTH-1:0] s_core_tcdm_bus_be; + logic [NB_CORES+NB_HWACC_PORTS-1:0] s_core_tcdm_bus_gnt; + logic [NB_CORES+NB_HWACC_PORTS-1:0][DATA_WIDTH-1:0] s_core_tcdm_bus_r_rdata; + logic [NB_CORES+NB_HWACC_PORTS-1:0] s_core_tcdm_bus_r_valid; + + // DEMUX --> PERIPHERAL INTERCONNECT BUS SIGNALS + logic [NB_CORES-1:0][ADDR_WIDTH-1:0] s_core_periph_bus_add; + logic [NB_CORES-1:0] s_core_periph_bus_req; + logic [NB_CORES-1:0][DATA_WIDTH-1:0] s_core_periph_bus_wdata; + logic [NB_CORES-1:0] s_core_periph_bus_wen; + logic [NB_CORES-1:0][5:0] s_core_periph_bus_atop; + logic [NB_CORES-1:0][BE_WIDTH-1:0] s_core_periph_bus_be; + logic [NB_CORES-1:0] s_core_periph_bus_gnt; + logic [NB_CORES-1:0] s_core_periph_bus_r_opc; + logic [NB_CORES-1:0] s_core_periph_bus_r_valid; + logic [NB_CORES-1:0][DATA_WIDTH-1:0] s_core_periph_bus_r_rdata; + + // LOGARITHMIC INTERCONNECT --> Superbank MUX + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][ADDR_MEM_WIDTH-1:0] s_tcdm_bus_sb_mux_add; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0] s_tcdm_bus_sb_mux_req; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0] s_tcdm_bus_sb_mux_gnt; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0] s_tcdm_bus_sb_mux_wen; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][5:0] s_tcdm_bus_sb_mux_atop; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][DATA_WIDTH-1:0] s_tcdm_bus_sb_mux_wdata; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][BE_WIDTH-1:0] s_tcdm_bus_sb_mux_be; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][DATA_WIDTH-1:0] s_tcdm_bus_sb_mux_rdata; + + // Superbank MUX --> Amo Shims + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][ADDR_MEM_WIDTH-1:0] s_sb_mux_amo_shim_add; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0] s_sb_mux_amo_shim_req; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0] s_sb_mux_amo_shim_gnt; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0] s_sb_mux_amo_shim_wen; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][5:0] s_sb_mux_amo_shim_atop; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][DATA_WIDTH-1:0] s_sb_mux_amo_shim_wdata; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][BE_WIDTH-1:0] s_sb_mux_amo_shim_be; + logic [NB_SUPERBANKS-1:0][BANKS_PER_SUPERBANK-1:0][DATA_WIDTH-1:0] s_sb_mux_amo_shim_rdata; + + // DMA Superbank Decoder -> Superbank MUX + logic [NB_SUPERBANKS-1:0] s_decoder_sb_a_mux_req; + logic [NB_SUPERBANKS-1:0] s_decoder_sb_a_mux_gnt; + logic [NB_SUPERBANKS-1:0][ADDR_MEM_WIDTH-1:0] s_decoder_sb_a_mux_add; + logic [NB_SUPERBANKS-1:0][5:0] s_decoder_sb_a_mux_amo; + logic [NB_SUPERBANKS-1:0] s_decoder_sb_a_mux_wen; + logic [NB_SUPERBANKS-1:0][DMA_DATA_WIDTH-1:0] s_decoder_sb_a_mux_wdata; + logic [NB_SUPERBANKS-1:0][DMA_DATA_WIDTH/8-1:0] s_decoder_sb_a_mux_be; + logic [NB_SUPERBANKS-1:0][DMA_DATA_WIDTH-1:0] s_decoder_sb_a_mux_rdata; + + // DMA Superbank Decoder -> Superbank MUX + logic [NB_SUPERBANKS-1:0] s_decoder_sb_b_mux_req; + logic [NB_SUPERBANKS-1:0] s_decoder_sb_b_mux_gnt; + logic [NB_SUPERBANKS-1:0][ADDR_MEM_WIDTH-1:0] s_decoder_sb_b_mux_add; + logic [NB_SUPERBANKS-1:0][5:0] s_decoder_sb_b_mux_amo; + logic [NB_SUPERBANKS-1:0] s_decoder_sb_b_mux_wen; + logic [NB_SUPERBANKS-1:0][DMA_DATA_WIDTH-1:0] s_decoder_sb_b_mux_wdata; + logic [NB_SUPERBANKS-1:0][DMA_DATA_WIDTH/8-1:0] s_decoder_sb_b_mux_be; + logic [NB_SUPERBANKS-1:0][DMA_DATA_WIDTH-1:0] s_decoder_sb_b_mux_rdata; + + // DMA -> DMA Superbank Decoder a + logic s_dma_decoder_a_req; + logic s_dma_decoder_a_gnt; + logic [DMA_ADDR_WIDTH-1:0] s_dma_decoder_a_add; + logic [5:0] s_dma_decoder_a_amo; + logic s_dma_decoder_a_wen; + logic [DMA_DATA_WIDTH-1:0] s_dma_decoder_a_wdata; + logic [DMA_DATA_WIDTH/8-1:0] s_dma_decoder_a_be; + logic [DMA_DATA_WIDTH-1:0] s_dma_decoder_a_rdata; + + // DMA -> DMA Superbank Decoder b + logic s_dma_decoder_b_req; + logic s_dma_decoder_b_gnt; + logic [DMA_ADDR_WIDTH-1:0] s_dma_decoder_b_add; + logic [5:0] s_dma_decoder_b_amo; + logic s_dma_decoder_b_wen; + logic [DMA_DATA_WIDTH-1:0] s_dma_decoder_b_wdata; + logic [DMA_DATA_WIDTH/8-1:0] s_dma_decoder_b_be; + logic [DMA_DATA_WIDTH-1:0] s_dma_decoder_b_rdata; + + // PERIPHERAL INTERCONNECT INTERCONNECT --> SLAVE PERIPHERALS BUS SIGNALS + logic [NB_SPERIPHS-1:0][DATA_WIDTH-1:0] s_speriph_bus_wdata; + logic [NB_SPERIPHS-1:0][ADDR_WIDTH-1:0] s_speriph_bus_add; + logic [NB_SPERIPHS-1:0] s_speriph_bus_req; + logic [NB_SPERIPHS-1:0] s_speriph_bus_wen; + logic [NB_SPERIPHS-1:0][5:0] s_speriph_bus_atop; + logic [NB_SPERIPHS-1:0][BE_WIDTH-1:0] s_speriph_bus_be; + logic [NB_SPERIPHS-1:0][NB_CORES+NB_MPERIPHS-1:0] s_speriph_bus_id; + logic [NB_SPERIPHS-1:0] s_speriph_bus_gnt ; + logic [NB_SPERIPHS-1:0] s_speriph_bus_r_opc; + logic [NB_SPERIPHS-1:0][NB_CORES+NB_MPERIPHS-1:0] s_speriph_bus_r_id; + logic [NB_SPERIPHS-1:0][DATA_WIDTH-1:0] s_speriph_bus_r_rdata; + logic [NB_SPERIPHS-1:0] s_speriph_bus_r_valid; + + //******************************************************** + //****** BINDING INTERFACES TO INTERNAL BUS SINGALS ****** + //******************************************************** + generate + for (genvar i=0; i + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +import pulp_cluster_package::*; + +module cluster_peripherals +#( + parameter NB_CORES = 4, + parameter NB_MPERIPHS = 1, + parameter NB_CACHE_BANKS = 4, + parameter NB_SPERIPHS = 8, + parameter NB_TCDM_BANKS = 8, + parameter NB_HWPE_PORTS = 1, + parameter ROM_BOOT_ADDR = 32'h1A000000, + parameter BOOT_ADDR = 32'h1C000000, + parameter EVNT_WIDTH = 8, + parameter FEATURE_DEMUX_MAPPED = 1 +) +( + input logic clk_i, + input logic rst_ni, + input logic ref_clk_i, + input logic test_mode_i, + + input logic [NB_CORES-1:0] dma_events_i, + input logic [NB_CORES-1:0] dma_irq_i, + input logic en_sa_boot_i, + input logic fetch_en_i, + input logic [NB_CORES-1:0] core_busy_i, + output logic [NB_CORES-1:0] core_clk_en_o, + output logic fregfile_disable_o, + + output logic [NB_CORES-1:0][31:0] boot_addr_o, + + output logic cluster_cg_en_o, + + output logic busy_o, + + XBAR_PERIPH_BUS.Slave speriph_slave[NB_SPERIPHS-2:0], + XBAR_PERIPH_BUS.Slave core_eu_direct_link[NB_CORES-1:0], + + XBAR_PERIPH_BUS.Master dma_cfg_master, + input logic dma_pe_irq_i, + output logic pf_event_o, + + output logic soc_periph_evt_ready_o, + input logic soc_periph_evt_valid_i, + input logic [EVNT_WIDTH-1:0] soc_periph_evt_data_i, + + input logic [NB_CORES-1:0] dbg_core_halted_i, + output logic [NB_CORES-1:0] dbg_core_halt_o, + output logic [NB_CORES-1:0] dbg_core_resume_o, + + output logic eoc_o, + output logic [NB_CORES-1:0] fetch_enable_reg_o, //fetch enable driven by the internal register + output logic [NB_CORES-1:0][4:0] irq_id_o, + input logic [NB_CORES-1:0][4:0] irq_ack_id_i, + output logic [NB_CORES-1:0] irq_req_o, + input logic [NB_CORES-1:0] irq_ack_i, + + // SRAM SPEED REGULATION --> TCDM + output logic [1:0] TCDM_arb_policy_o, + + XBAR_PERIPH_BUS.Master hwce_cfg_master, + input logic [NB_CORES-1:0][3:0] hwacc_events_i, + output logic hwpe_sel_o, + output logic hwpe_en_o, + + // Control ports + MP_PF_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus +); + + logic s_timer_out_lo_event; + logic s_timer_out_hi_event; + logic s_timer_in_lo_event; + logic s_timer_in_hi_event; + + logic [NB_CORES-1:0][31:0] s_cluster_events; + logic [NB_CORES-1:0][3:0] s_acc_events; + logic [NB_CORES-1:0][1:0] s_timer_events; + logic [NB_CORES-1:0][1:0] s_dma_events; + + logic [NB_CORES-1:0] s_fetch_en_cc; + + logic [NB_SPERIPH_PLUGS_EU-1:0] eu_speriph_plug_req; + logic [NB_SPERIPH_PLUGS_EU-1:0][31:0] eu_speriph_plug_add; + logic [NB_SPERIPH_PLUGS_EU-1:0] eu_speriph_plug_wen; + logic [NB_SPERIPH_PLUGS_EU-1:0][31:0] eu_speriph_plug_wdata; + logic [NB_SPERIPH_PLUGS_EU-1:0][3:0] eu_speriph_plug_be; + logic [NB_SPERIPH_PLUGS_EU-1:0][NB_CORES:0] eu_speriph_plug_id; + + logic soc_periph_evt_valid, soc_periph_evt_ready; + logic [7:0] soc_periph_evt_data; + + // internal speriph bus to combine multiple plugs to new event unit + XBAR_PERIPH_BUS speriph_slave_eu_comb(); + MESSAGE_BUS eu_message_master(); + + // decide between common or core-specific event sources + generate + for (genvar I=0; I + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +module cluster_timer_wrap + #( + parameter ID_WIDTH = 2 + ) + ( + input logic clk_i, + input logic rst_ni, + input logic ref_clk_i, + + XBAR_PERIPH_BUS.Slave periph_slave, + + input logic event_lo_i, + input logic event_hi_i, + + output logic irq_lo_o, + output logic irq_hi_o, + + output logic busy_o + ); + + timer_unit + #( + .ID_WIDTH ( ID_WIDTH ) + ) + timer_unit_i + ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .ref_clk_i ( ref_clk_i ), + + .req_i ( periph_slave.req ), + .addr_i ( periph_slave.add ), + .wen_i ( periph_slave.wen ), + .wdata_i ( periph_slave.wdata ), + .be_i ( periph_slave.be ), + .id_i ( periph_slave.id ), + .gnt_o ( periph_slave.gnt ), + + .r_valid_o ( periph_slave.r_valid ), + .r_opc_o ( periph_slave.r_opc ), + .r_id_o ( periph_slave.r_id ), + .r_rdata_o ( periph_slave.r_rdata ), + + .event_lo_i ( event_lo_i ), + .event_hi_i ( event_hi_i ), + + .irq_lo_o ( irq_lo_o ), + .irq_hi_o ( irq_hi_o ), + + .busy_o ( busy_o ) + ); + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/core_demux.sv b/hw/deps/pulp_cluster/rtl/core_demux.sv new file mode 100644 index 0000000..f9e6cdd --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/core_demux.sv @@ -0,0 +1,568 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * core_demux.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +//`define PERF_CNT + +module core_demux +#( + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 32, + parameter int BYTE_ENABLE_BIT = DATA_WIDTH/8, + parameter bit CLUSTER_ALIAS = 1'b1, + parameter int CLUSTER_ALIAS_BASE = 12'h000, + parameter bit DEM_PER_BEFORE_TCDM_TS = 1'b0, + parameter bit REMAP_ADDRESS = 1'b0 +) +( + input logic clk, + input logic rst_ni, + input logic test_en_i, + input logic [3:0] base_addr_i, + + // CORE SIDE + input logic data_req_i, + input logic [ADDR_WIDTH - 1:0] data_add_i, + input logic data_wen_i, + input logic [5:0] data_atop_i, + input logic [DATA_WIDTH - 1:0] data_wdata_i, + input logic [BYTE_ENABLE_BIT - 1:0] data_be_i, + output logic data_gnt_o, + + input logic data_r_gnt_i, // Data Response Grant (For LOAD/STORE commands) + output logic data_r_valid_o, // Data Response Valid (For LOAD/STORE commands) + output logic [DATA_WIDTH - 1:0] data_r_rdata_o, // Data Response DATA (For LOAD commands) + output logic data_r_opc_o, // Data Response Error + + // Low Latency log interconnect + output logic data_req_o_SH, + output logic [ADDR_WIDTH - 1:0] data_add_o_SH, + output logic data_wen_o_SH, + output logic [5:0] data_atop_o_SH, + output logic [DATA_WIDTH - 1:0] data_wdata_o_SH, + output logic [BYTE_ENABLE_BIT - 1:0] data_be_o_SH, + input logic data_gnt_i_SH, + input logic data_r_valid_i_SH, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_SH, + + // externally memory-mapped peripherals + output logic data_req_o_EXT, + output logic [ADDR_WIDTH - 1:0] data_add_o_EXT, + output logic data_wen_o_EXT, + output logic [DATA_WIDTH - 1:0] data_wdata_o_EXT, + output logic [BYTE_ENABLE_BIT - 1:0] data_be_o_EXT, + input logic data_gnt_i_EXT, + input logic data_r_valid_i_EXT, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_EXT, + input logic data_r_opc_i_EXT, + + // Peripheral interconnect + output logic data_req_o_PE, + output logic [ADDR_WIDTH - 1:0] data_add_o_PE, + output logic data_wen_o_PE, + output logic [5:0] data_atop_o_PE, + output logic [DATA_WIDTH - 1:0] data_wdata_o_PE, + output logic [BYTE_ENABLE_BIT - 1:0] data_be_o_PE, + input logic data_gnt_i_PE, + input logic data_r_valid_i_PE, + input logic data_r_opc_i_PE, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_PE, + + // Performance Counters + output logic perf_l2_ld_o, // nr of L2 loads + output logic perf_l2_st_o, // nr of L2 stores + output logic perf_l2_ld_cyc_o, // cycles used for L2 loads + output logic perf_l2_st_cyc_o, // cycles used for L2 stores + + input logic [5:0] CLUSTER_ID +); + + logic [10:0] CLUSTER_ALIAS_BASE_11; + logic [11:0] CLUSTER_ALIAS_BASE_12, + CLUSTER_ALIAS_TCDM_RW, + CLUSTER_ALIAS_TCDM_TS, + CLUSTER_ALIAS_DEM_PER; + + logic s_data_req_PE; + logic s_data_gnt_PE; + logic [DATA_WIDTH - 1:0] s_data_r_data_PE; + logic s_data_r_valid_PE; + logic s_data_r_opc_PE; + logic [DATA_WIDTH - 1:0] s_data_r_data_PE_0; + logic s_data_r_valid_PE_0; + logic s_data_r_opc_PE_0; + + enum logic [1:0] { TRANS_IDLE, TRANS_PENDING, TRANS_GRANTED } CS, NS; + + // From L1 Arbiter + logic data_req_to_L2; + logic [ADDR_WIDTH - 1:0] data_add_to_L2; + logic data_wen_to_L2; + logic [DATA_WIDTH - 1:0] data_wdata_to_L2; + logic [BYTE_ENABLE_BIT - 1:0] data_be_to_L2; + logic data_gnt_from_L2; + + enum logic [1:0] {SH, PE, EXT } request_destination, destination; + + logic [ADDR_WIDTH - 1:0] data_add_int; + + // Signal to PERIPH FIFO + logic data_busy_PE_fifo; + logic data_req_PE_fifo; + logic [ADDR_WIDTH - 1:0] data_add_PE_fifo; + logic data_wen_PE_fifo; + logic [5:0] data_atop_PE_fifo; + logic [DATA_WIDTH - 1:0] data_wdata_PE_fifo; + logic [BYTE_ENABLE_BIT - 1:0] data_be_PE_fifo; + logic data_gnt_PE_fifo; + + logic data_r_valid_PE_fifo; + logic data_r_opc_PE_fifo; + logic [DATA_WIDTH - 1:0] data_r_rdata_PE_fifo; + + logic [11:0] TCDM_RW; + logic [11:0] TCDM_TS; + logic [11:0] DEM_PER; + + assign CLUSTER_ALIAS_BASE_12 = CLUSTER_ALIAS_BASE; + assign CLUSTER_ALIAS_BASE_11 = CLUSTER_ALIAS_BASE_12[11:1]; + assign CLUSTER_ALIAS_TCDM_RW = CLUSTER_ALIAS_BASE_12 + 0; + assign CLUSTER_ALIAS_TCDM_TS = CLUSTER_ALIAS_BASE_12 + 1; + assign CLUSTER_ALIAS_DEM_PER = CLUSTER_ALIAS_BASE_12 + 2; + + assign TCDM_RW = 12'h100 + (CLUSTER_ID << 2) + 0; + assign TCDM_TS = 12'h100 + (CLUSTER_ID << 2) + 1; + assign DEM_PER = 12'h100 + (CLUSTER_ID << 2) + 2; + + // This section is used to swap the 4 most significant bits of the address + // with the ones that are provided by the base_addr_i + // If data_add_i[31:28] == base_addr_i then data_add_i[31:28] are changed in 4'b0001 + // If data_add_i[31:28] == 4'b0001 --> then th data_add_i[31:28] is changed in base_addr_i + // In the other cases, the address is unchanged + + assign data_add_int[27:0] = data_add_i[27:0]; + + if (REMAP_ADDRESS) begin : gen_remap_address + always_comb begin + if (data_add_i[31:28] == base_addr_i) begin + data_add_int[31:28] = 4'b0001; + end else if (data_add_int[31:28] == 4'b0001) begin + data_add_int[31:28] = base_addr_i; + end else begin + data_add_int[31:28] = data_add_i[31:28]; + end + end + end else begin : gen_no_remap_address + assign data_add_int[31:28] = data_add_i[31:28]; + end + + // level 1 request arbiter + assign data_add_o_SH = data_add_int; + assign data_wen_o_SH = data_wen_i; + assign data_atop_o_SH = data_atop_i; + assign data_wdata_o_SH = data_wdata_i; + assign data_be_o_SH = data_be_i; + + assign data_add_to_L2 = data_add_int; + assign data_wen_to_L2 = data_wen_i; + assign data_wdata_to_L2 = data_wdata_i; + assign data_be_to_L2 = data_be_i; + + always_ff @(posedge clk, negedge rst_ni) + begin : _UPDATE_RESPONSE_DESTINATION_ + if(rst_ni == 1'b0) begin + request_destination <= SH; + end + else if (data_req_i) begin + if (DEM_PER_BEFORE_TCDM_TS) begin + + + case ({CLUSTER_ALIAS, data_add_int[31:20]}) + {1'b0, TCDM_RW}, + {1'b1, TCDM_RW}, + {1'b1, CLUSTER_ALIAS_TCDM_RW}: begin + if (data_add_int[19:14] == 6'b11_1111) begin + request_destination <= EXT; + end else begin + request_destination <= SH; + end + end + + {1'b0, TCDM_TS}, + {1'b1, TCDM_TS}, + {1'b1, CLUSTER_ALIAS_TCDM_TS}: begin + request_destination <= SH; + end + + {1'b0, DEM_PER}, + {1'b1, DEM_PER}, + {1'b1, CLUSTER_ALIAS_DEM_PER}: begin + request_destination <= PE; + end + + default: request_destination <= PE; + endcase + + + end else begin + case ({CLUSTER_ALIAS, data_add_int[31:20]}) + {1'b0, TCDM_RW}, + {1'b1, TCDM_RW}, + {1'b1, CLUSTER_ALIAS_TCDM_RW}, + {1'b0, TCDM_TS}, + {1'b1, TCDM_TS}, + {1'b1, CLUSTER_ALIAS_TCDM_TS}: begin + request_destination <= SH; + end + + {1'b0, DEM_PER}, + {1'b1, DEM_PER}, + {1'b1, CLUSTER_ALIAS_DEM_PER}: begin + if (data_add_int[14]) begin // DEMUX PERIPHERALS + request_destination <= EXT; + end else begin + request_destination <= PE; + end + end + + default: request_destination <= PE; + endcase + end + end + end + + always_comb + begin : _UPDATE_REQUEST_DESTINATION_ + if (DEM_PER_BEFORE_TCDM_TS) begin + case ({CLUSTER_ALIAS, data_add_int[31:20]}) + {1'b0, TCDM_RW}, + {1'b1, TCDM_RW}, + {1'b1, CLUSTER_ALIAS_TCDM_RW}: begin + if (data_add_int[19:14] == 6'b11_1111) begin + destination = EXT; + end else begin + destination = SH; + end + end // CLUSTER or DEM peripherals (mappping based on Germain suggestion) + + {1'b0, TCDM_TS}, + {1'b1, TCDM_TS}, + {1'b1, CLUSTER_ALIAS_TCDM_TS}: begin + destination = SH; + end + + {1'b0, DEM_PER}, + {1'b1, DEM_PER}, + {1'b1, CLUSTER_ALIAS_DEM_PER}: begin + destination = PE; + end + + default: begin + destination = PE; + end // CLUSTER PERIPHERAL and rest of the memory map + + endcase + end else begin + case ({CLUSTER_ALIAS, data_add_int[31:20]}) + {1'b0, TCDM_RW}, + {1'b1, TCDM_RW}, + {1'b1, CLUSTER_ALIAS_TCDM_RW}, + {1'b0, TCDM_TS}, + {1'b1, TCDM_TS}, + {1'b1, CLUSTER_ALIAS_TCDM_TS}: begin + destination = SH; + end + + {1'b0, DEM_PER}, + {1'b1, DEM_PER}, + {1'b1, CLUSTER_ALIAS_DEM_PER}: begin + if(data_add_int[14]) begin // DEMUX PERIPHERALS + destination = EXT; + end else begin + destination = PE; + end + end + + default: begin + destination = PE; + end + endcase + end + end + + always_comb + begin : L1_REQUEST_ARBITER + if (DEM_PER_BEFORE_TCDM_TS) begin + if (data_add_int[31:21] == TCDM_RW[11:1] || //LOGARITHMIC INTERCONNECT --> 31:20 --> 0x100 or 0x101 + (CLUSTER_ALIAS && data_add_int[31:21] == CLUSTER_ALIAS_BASE_11) //LOGARITHMIC INTERCONNECT --> 31:20 --> 0x100 or 0x101 or ALIAS (0x000 or 0x001) or DEM PERIPH + ) begin: _TO_DEM_PER_L2_ + if (data_add_int[19:14] == 6'b11_1111) begin + data_req_o_SH = 1'b0; + data_req_to_L2 = data_req_i; + data_gnt_o = data_gnt_from_L2; + end else begin: _TO_CLUSTER_L1_ + data_req_o_SH = data_req_i; + data_req_to_L2 = 1'b0; + data_gnt_o = data_gnt_i_SH; + end + end else begin: _DPBTT_TO_L2_LEVEL_ + data_req_o_SH = 1'b0; + data_req_to_L2 = data_req_i; + data_gnt_o = data_gnt_from_L2; + end + end else begin + if (data_add_int[31:21] == TCDM_RW[11:1] || //LOGARITHMIC INTERCONNECT --> 31:20 --> 0x100 or 0x101 + (CLUSTER_ALIAS && data_add_int[31:21] == CLUSTER_ALIAS_BASE_11) //LOGARITHMIC INTERCONNECT --> 31:20 --> 0x100 or 0x101 or ALIAS (0x000 or 0x001) or DEM PERIPH + ) begin: _TO_CLUSTER_ + data_req_o_SH = data_req_i; + data_req_to_L2 = 1'b0; + data_gnt_o = data_gnt_i_SH; + end else begin: _TO_L2_LEVEL_ + data_req_o_SH = 1'b0; + data_req_to_L2 = data_req_i; + data_gnt_o = data_gnt_from_L2; + end + end + end + + // level 2 request arbiter + assign data_add_PE_fifo = data_add_int; + assign data_wen_PE_fifo = data_wen_i; + assign data_atop_PE_fifo = data_atop_i; + assign data_wdata_PE_fifo = data_wdata_i; + assign data_be_PE_fifo = data_be_i; + + assign data_add_o_EXT = data_add_int; + assign data_wen_o_EXT = data_wen_i; + assign data_wdata_o_EXT = data_wdata_i; + assign data_be_o_EXT = data_be_i; + + always_comb + begin : _L2_REQUEST_ARBITER_ + if (DEM_PER_BEFORE_TCDM_TS) begin + if (data_add_int[19:14] == 6'b11_1111 && ( + ( CLUSTER_ALIAS && ( + data_add_int[31:20] == TCDM_RW || data_add_int[31:20] == CLUSTER_ALIAS_TCDM_RW) + ) || + (!CLUSTER_ALIAS && data_add_int[31:20] == DEM_PER) + )) begin: _DPBTT_TO_DEMUX_PERIPH_ //Peripheral --> add_i[31:0] --> 0x100F_FC00 to 0x100F_FFFF + data_req_PE_fifo = 1'b0; + data_req_o_EXT = data_req_to_L2; + data_gnt_from_L2 = data_gnt_i_EXT; + end else begin: _DPBTT_TO_PERIPHERAL_INTERCO_ + data_req_PE_fifo = s_data_req_PE; + data_req_o_EXT = 1'b0; + data_gnt_from_L2 = s_data_gnt_PE; + end + end else begin + if (data_add_int[14] && ( + data_add_int[31:20] == DEM_PER || + (CLUSTER_ALIAS && data_add_int[31:20] == CLUSTER_ALIAS_DEM_PER) + )) begin: _TO_DEMUX_PERIPH_ //Peripheral --> add_i[31:0] --> 0x1020_4000 to 0x1020_7FFF + data_req_PE_fifo = 1'b0; + data_req_o_EXT = data_req_to_L2; + data_gnt_from_L2 = data_gnt_i_EXT; + end else begin: _TO_PERIPHERAL_INTERCO_ + data_req_PE_fifo = s_data_req_PE; + data_req_o_EXT = 1'b0; + data_gnt_from_L2 = s_data_gnt_PE; + end + end + end + + // response arbiter + always_comb + begin: _RESPONSE_ARBITER_ + case(request_destination) + SH : begin + data_r_valid_o = data_r_valid_i_SH; + data_r_rdata_o = data_r_rdata_i_SH; + data_r_opc_o = 1'b0; + end + + PE : begin + data_r_valid_o = s_data_r_valid_PE; + data_r_rdata_o = s_data_r_data_PE; + data_r_opc_o = s_data_r_opc_PE; + end + + EXT : begin + data_r_valid_o = data_r_valid_i_EXT; + data_r_rdata_o = data_r_rdata_i_EXT; + data_r_opc_o = data_r_opc_i_EXT; + end + + default : begin + data_r_valid_o = 1'b0; + data_r_rdata_o = 'x; + data_r_opc_o = 1'b0; + end + endcase + end + + // pe interface + always_ff @(posedge clk, negedge rst_ni) + begin + if(rst_ni == 1'b0) begin + CS <= TRANS_IDLE; + end + else begin + CS <= NS; + end + end + + always_comb + begin + s_data_gnt_PE = 1'b0; + s_data_req_PE = 1'b0; + case(CS) + TRANS_IDLE : begin + if( ( data_req_i == 1'b1 ) && ( destination == PE ) ) begin + s_data_req_PE = 1'b1; + if (data_gnt_PE_fifo == 1'b1) begin + NS = TRANS_PENDING; + end + else begin + NS = TRANS_IDLE; + end + end + else begin + NS = TRANS_IDLE; + end + end + TRANS_PENDING : begin + if (data_r_valid_PE_fifo == 1'b1) begin + NS = TRANS_GRANTED; + end + else begin + NS = TRANS_PENDING; + end + end + TRANS_GRANTED : begin + s_data_gnt_PE = 1'b1; + NS = TRANS_IDLE; + end + default : begin + NS = TRANS_IDLE; + end + endcase + end + + // periph response generation + always_ff @(posedge clk, negedge rst_ni) + begin + if(rst_ni == 1'b0) begin + s_data_r_valid_PE_0 <= '0; + s_data_r_data_PE_0 <= '0; + s_data_r_opc_PE_0 <= '0; + end + else begin + s_data_r_valid_PE_0 <= data_r_valid_PE_fifo; + if(data_r_valid_PE_fifo) begin + s_data_r_data_PE_0 <= data_r_rdata_PE_fifo; + s_data_r_opc_PE_0 <= data_r_opc_PE_fifo; + end + end + end + + always_ff @(posedge clk, negedge rst_ni) begin + if(rst_ni == 1'b0) begin + s_data_r_valid_PE <= '0; + s_data_r_data_PE <= '0; + s_data_r_opc_PE <= '0; + end + else begin + s_data_r_valid_PE <= s_data_r_valid_PE_0; + if(s_data_r_valid_PE_0) begin + s_data_r_data_PE <= s_data_r_data_PE_0; + s_data_r_opc_PE <= s_data_r_opc_PE_0; + end + end + end + + periph_FIFO #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BYTE_ENABLE_BIT ( DATA_WIDTH/8 ) + ) periph_FIFO_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + //Input SIde REQ + .data_req_i ( data_req_PE_fifo ), + .data_add_i ( data_add_PE_fifo ), + .data_wen_i ( data_wen_PE_fifo ), + .data_atop_i ( data_atop_PE_fifo ), + .data_wdata_i ( data_wdata_PE_fifo ), + .data_be_i ( data_be_PE_fifo ), + .data_gnt_o ( data_gnt_PE_fifo ), + + //Output side REQ + .data_req_o ( data_req_o_PE ), + .data_add_o ( data_add_o_PE ), + .data_wen_o ( data_wen_o_PE ), + .data_atop_o ( data_atop_o_PE ), + .data_wdata_o ( data_wdata_o_PE ), + .data_be_o ( data_be_o_PE ), + .data_gnt_i ( data_gnt_i_PE ), + + //Input Side RESP + .data_r_valid_i ( data_r_valid_i_PE ), + .data_r_opc_i ( data_r_opc_i_PE ), + .data_r_rdata_i ( data_r_rdata_i_PE ), + + //Output Side RESP + .data_r_valid_o ( data_r_valid_PE_fifo ), + .data_r_opc_o ( data_r_opc_PE_fifo ), + .data_r_rdata_o ( data_r_rdata_PE_fifo ) + ); + + // Performance Counters + assign perf_l2_ld_o = data_req_to_L2 & data_gnt_from_L2 & data_wen_i; + assign perf_l2_st_o = data_req_to_L2 & data_gnt_from_L2 & (~data_wen_i); + assign perf_l2_ld_cyc_o = data_req_to_L2 & data_wen_i; + assign perf_l2_st_cyc_o = data_req_to_L2 & (~data_wen_i); + +`ifdef PERF_CNT + logic [31:0] STALL_TCDM; + logic [31:0] STALL_L2; + + logic clear_regs, enable_regs; + + always_ff @(posedge clk or negedge rst_ni) + begin + if(~rst_ni) begin + STALL_TCDM <= '0; + STALL_L2 <= '0; + end + else begin + if(clear_regs) begin + STALL_TCDM <= '0; + STALL_L2 <= '0; + end + else if(enable_regs) begin + if( data_req_o_SH & ~data_gnt_i_SH ) + STALL_TCDM <= STALL_TCDM + 1'b1; + if( data_req_to_L2 & ~data_gnt_from_L2 ) + STALL_L2 <= STALL_L2 + 1'b1; + end + end + end +`endif + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/core_region.sv b/hw/deps/pulp_cluster/rtl/core_region.sv new file mode 100644 index 0000000..1b1fcad --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/core_region.sv @@ -0,0 +1,573 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * core_region.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +import apu_package::*; + +/* verilator tracing_on */ + +// USER DEFINED MACROS to improve self-testing capabilities +`ifndef PULP_FPGA_SIM + `define DEBUG_FETCH_INTERFACE +`endif +//`define DATA_MISS +//`define DUMP_INSTR_FETCH + +module core_region +#( + // CORE PARAMETERS + parameter int CORE_ID = 0, + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 32, + parameter int INSTR_RDATA_WIDTH = 32, + parameter bit CLUSTER_ALIAS = 1'b1, + parameter int CLUSTER_ALIAS_BASE = 12'h000, + parameter int REMAP_ADDRESS = 0, + parameter bit DEM_PER_BEFORE_TCDM_TS = 1'b0, + parameter int INTER_CORE_FIFO_DEPTH = 0, + parameter int N_PMP_ENTRIES = 16 +`ifndef SYNTHESIS + , + parameter string L2_SLM_FILE = "./slm_files/l2_stim.slm", + parameter string ROM_SLM_FILE = "../sw/apps/boot/slm_files/l2_stim.slm" +`endif +) +( + input logic clk_i, + input logic rst_ni, + input logic init_ni, + + input logic [3:0] base_addr_i, // FOR CLUSTER VIRTUALIZATION + + input logic [5:0] cluster_id_i, + + input logic irq_req_i, + output logic irq_ack_o, + input logic [4:0] irq_id_i, + output logic [4:0] irq_ack_id_o, + + input logic clock_en_i, + input logic fetch_en_i, + input logic fregfile_disable_i, + + input logic [31:0] boot_addr_i, + + input logic test_mode_i, + + output logic core_busy_o, + + // Interface to Instruction Logarithmic interconnect (Req->grant handshake) + output logic instr_req_o, + input logic instr_gnt_i, + output logic [31:0] instr_addr_o, + input logic [INSTR_RDATA_WIDTH-1:0] instr_r_rdata_i, + input logic instr_r_valid_i, + + XBAR_TCDM_BUS.Slave debug_bus, + output logic debug_core_halted_o, + input logic debug_core_halt_i, + input logic debug_core_resume_i, + + output logic unaligned_o, + + // Interface for DEMUX to TCDM INTERCONNECT ,PERIPHERAL INTERCONNECT and DMA CONTROLLER + XBAR_TCDM_BUS.Master tcdm_data_master, + output logic [5:0] tcdm_data_master_atop, + XBAR_TCDM_BUS.Master dma_ctrl_master, + XBAR_PERIPH_BUS.Master eu_ctrl_master, + XBAR_PERIPH_BUS.Master periph_data_master, + output logic [5:0] periph_data_master_atop, + + XBAR_PERIPH_BUS.Slave this_fifo_slave, + XBAR_PERIPH_BUS.Master next_fifo_master, + + XBAR_PERIPH_BUS.Master hpu_driver_master, + + // APU interconnect interface + cpu_marx_if.cpu apu_master, + + //interface for configuring PMP from external + input logic pmp_conf_override_i, + input logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_i, + input logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_i +); + + XBAR_DEMUX_BUS s_core_bus(); // Internal interface between CORE <--> DEMUX + XBAR_PERIPH_BUS periph_demux_bus(); // Internal interface between CORE_DEMUX <--> PERIPHERAL DEMUX + XBAR_PERIPH_BUS this_fifo(); + XBAR_PERIPH_BUS periph_data(), periph_data_buf(); + + logic core_buffer; + logic [5:0] periph_data_atop, + periph_data_buf_atop; + + logic [4:0] perf_counters; + logic clk_int; + + // clock gate of the core_region less the core itself + cluster_clock_gating clock_gate_i ( + .clk_i ( clk_i ), + .en_i ( clock_en_i ), + .test_en_i ( test_mode_i ), + .clk_o ( clk_int ) + ); + + + logic [31:0] hart_id; + always_comb begin + hart_id = '0; + hart_id[3:0] = CORE_ID[3:0]; + hart_id[10:5] = cluster_id_i; + end + logic [5:0] irq_ack_id; + assign irq_ack_id_o = irq_ack_id[4:0]; + assert property (@(posedge clk_i) irq_ack_o |-> !irq_ack_id[5]); + riscv_core #( + .N_EXT_PERF_COUNTERS ( 5 ), + .FPU ( FPU ), + .SHARED_FP ( SHARED_FP ), + .SHARED_DSP_MULT ( SHARED_DSP_MULT ), + .SHARED_INT_DIV ( SHARED_INT_DIV ), + .SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ), + .WAPUTYPE ( WAPUTYPE ), + .PULP_HWLP ( 1 ), + .N_PMP_ENTRIES ( N_PMP_ENTRIES ) + ) RISCV_CORE ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .clock_en_i ( clock_en_i ), + .scan_cg_en_i ( test_mode_i ), + + .boot_addr_i ( boot_addr_i ), + .dm_halt_addr_i ( '0 ), + .hart_id_i ( hart_id ), + + .instr_req_o ( instr_req_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_r_valid_i ), + .instr_addr_o ( instr_addr_o ), + .instr_rdata_i ( instr_r_rdata_i ), + + .data_req_o ( s_core_bus.req ), + .data_gnt_i ( s_core_bus.gnt ), + .data_rvalid_i ( s_core_bus.r_valid ), + .data_we_o ( s_core_bus.we ), + .data_be_o ( s_core_bus.be ), + .data_addr_o ( s_core_bus.add ), + .data_wdata_o ( s_core_bus.wdata ), + .data_rdata_i ( s_core_bus.r_rdata ), + + .data_atop_o ( s_core_bus.atop ), + .data_buffer_o ( core_buffer ), + .data_unaligned_o ( unaligned_o ), + + // apu-interconnect + // handshake signals + .apu_master_req_o ( /* unused */ ), + .apu_master_ready_o ( /* unused */ ), + .apu_master_gnt_i ( '0 ), + // request channel + .apu_master_operands_o ( /* unused */ ), + .apu_master_op_o ( /* unused */ ), + .apu_master_type_o ( /* unused */ ), + .apu_master_flags_o ( /* unused */ ), + // response channel + .apu_master_valid_i ( '0 ), + .apu_master_result_i ( '0 ), + .apu_master_flags_i ( '0 ), + + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_ack_id ), + + .irq_software_i ( '0 ), + .irq_timer_i ( '0 ), + .irq_external_i ( '0 ), + .irq_fast_i ( '0 ), + + .debug_req_i ( debug_bus.req ), + + .fetch_enable_i ( fetch_en_i ), + .core_busy_o ( core_busy_o ), + + .pmp_conf_override_i ( pmp_conf_override_i ), + .pmp_cfg_i ( pmp_cfg_i ), + .pmp_addr_i ( pmp_addr_i ) + ); + + assign debug_bus.r_opc = 1'b0; + + // Bind to 0 Unused Signals in CORE interface + assign s_core_bus.r_gnt = 1'b0; + assign s_core_bus.barrier = 1'b0; + assign s_core_bus.exec_cancel = 1'b0; + assign s_core_bus.exec_stall = 1'b0; + + // Performance Counters + assign perf_counters[4] = tcdm_data_master.req & (~tcdm_data_master.gnt); // Cycles lost due to contention + + // demuxes to TCDM & memory hierarchy + core_demux #( + .ADDR_WIDTH ( 32 ), + .DATA_WIDTH ( 32 ), + .BYTE_ENABLE_BIT ( DATA_WIDTH/8 ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ), + .DEM_PER_BEFORE_TCDM_TS ( DEM_PER_BEFORE_TCDM_TS ), + .REMAP_ADDRESS ( REMAP_ADDRESS ) + ) core_demux_i ( + .clk ( clk_int ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .base_addr_i ( base_addr_i ), + + .data_req_i ( s_core_bus.req ), + .data_add_i ( s_core_bus.add ), + .data_wen_i ( ~s_core_bus.we ), //inverted when using OR10N + .data_atop_i ( s_core_bus.atop ), + .data_wdata_i ( s_core_bus.wdata ), + .data_be_i ( s_core_bus.be ), + .data_gnt_o ( s_core_bus.gnt ), + .data_r_gnt_i ( s_core_bus.r_gnt ), + .data_r_valid_o ( s_core_bus.r_valid ), + .data_r_opc_o ( ), + .data_r_rdata_o ( s_core_bus.r_rdata ), + + .data_req_o_SH ( tcdm_data_master.req ), + .data_add_o_SH ( tcdm_data_master.add ), + .data_wen_o_SH ( tcdm_data_master.wen ), + .data_atop_o_SH ( tcdm_data_master_atop ), + .data_wdata_o_SH ( tcdm_data_master.wdata ), + .data_be_o_SH ( tcdm_data_master.be ), + .data_gnt_i_SH ( tcdm_data_master.gnt ), + .data_r_valid_i_SH ( tcdm_data_master.r_valid ), + .data_r_rdata_i_SH ( tcdm_data_master.r_rdata ), + + .data_req_o_EXT ( periph_demux_bus.req ), + .data_add_o_EXT ( periph_demux_bus.add ), + .data_wen_o_EXT ( periph_demux_bus.wen ), + .data_wdata_o_EXT ( periph_demux_bus.wdata ), + .data_be_o_EXT ( periph_demux_bus.be ), + .data_gnt_i_EXT ( periph_demux_bus.gnt ), + .data_r_valid_i_EXT ( periph_demux_bus.r_valid ), + .data_r_rdata_i_EXT ( periph_demux_bus.r_rdata ), + .data_r_opc_i_EXT ( periph_demux_bus.r_opc ), + + .data_req_o_PE ( periph_data.req ), + .data_add_o_PE ( periph_data.add ), + .data_wen_o_PE ( periph_data.wen ), + .data_atop_o_PE ( periph_data_atop ), + .data_wdata_o_PE ( periph_data.wdata ), + .data_be_o_PE ( periph_data.be ), + .data_gnt_i_PE ( periph_data.gnt ), + .data_r_valid_i_PE ( periph_data.r_valid ), + .data_r_rdata_i_PE ( periph_data.r_rdata ), + .data_r_opc_i_PE ( periph_data.r_opc ), + + .perf_l2_ld_o ( perf_counters[0] ), + .perf_l2_st_o ( perf_counters[1] ), + .perf_l2_ld_cyc_o ( perf_counters[2] ), + .perf_l2_st_cyc_o ( perf_counters[3] ), + .CLUSTER_ID ( cluster_id_i ) + ); + + riscv_store_buffer #( + .Depth (16), + .AddrWidth (32), + .DataWidth (32) + ) i_store_buf ( + .clk_i ( clk_int ), + .rst_ni, + // Upstream + .addr_i ( periph_data.add ), + .we_ni ( periph_data.wen ), + .buffer_i ( core_buffer ), + .be_i ( periph_data.be ), + .wdata_i ( periph_data.wdata ), + .atop_i ( periph_data_atop ), + .req_i ( periph_data.req ), + .gnt_o ( periph_data.gnt ), + .rdata_o ( periph_data.r_rdata ), + .rvalid_o ( periph_data.r_valid ), + // Downstream + .addr_o ( periph_data_buf.add ), + .we_no ( periph_data_buf.wen ), + .be_o ( periph_data_buf.be ), + .wdata_o ( periph_data_buf.wdata ), + .atop_o ( periph_data_buf_atop ), + .req_o ( periph_data_buf.req ), + .gnt_i ( periph_data_buf.gnt ), + .rdata_i ( periph_data_buf.r_rdata ), + .rvalid_i ( periph_data_buf.r_valid ) + ); + assign periph_data.r_id = '0; + assign periph_data.r_opc = 1'b0; + assign periph_data_buf.id = periph_data.id; + + periph_demux #( + .DEM_PER_BEFORE_TCDM_TS (DEM_PER_BEFORE_TCDM_TS) + ) periph_demux_i ( + .clk ( clk_int ), + .rst_ni ( rst_ni ), + + .data_req_i ( periph_demux_bus.req ), + .data_add_i ( periph_demux_bus.add ), + .data_wen_i ( periph_demux_bus.wen ), + .data_wdata_i ( periph_demux_bus.wdata ), + .data_be_i ( periph_demux_bus.be ), + .data_gnt_o ( periph_demux_bus.gnt ), + + .data_r_valid_o ( periph_demux_bus.r_valid ), + .data_r_opc_o ( periph_demux_bus.r_opc ), + .data_r_rdata_o ( periph_demux_bus.r_rdata ), + + .data_req_o_MH ( dma_ctrl_master.req ), + .data_add_o_MH ( dma_ctrl_master.add ), + .data_wen_o_MH ( dma_ctrl_master.wen ), + .data_wdata_o_MH ( dma_ctrl_master.wdata ), + .data_be_o_MH ( dma_ctrl_master.be ), + .data_gnt_i_MH ( dma_ctrl_master.gnt ), + + .data_r_valid_i_MH ( dma_ctrl_master.r_valid ), + .data_r_rdata_i_MH ( dma_ctrl_master.r_rdata ), + .data_r_opc_i_MH ( dma_ctrl_master.r_opc ), + + .data_req_o_EU ( eu_ctrl_master.req ), + .data_add_o_EU ( eu_ctrl_master.add ), + .data_wen_o_EU ( eu_ctrl_master.wen ), + .data_wdata_o_EU ( eu_ctrl_master.wdata ), + .data_be_o_EU ( eu_ctrl_master.be ), + .data_gnt_i_EU ( eu_ctrl_master.gnt ), + + .data_r_valid_i_EU ( eu_ctrl_master.r_valid ), + .data_r_rdata_i_EU ( eu_ctrl_master.r_rdata ), + .data_r_opc_i_EU ( eu_ctrl_master.r_opc ), + + .data_req_o_MYF ( this_fifo.req ), + .data_add_o_MYF ( this_fifo.add ), + .data_wen_o_MYF ( this_fifo.wen ), + .data_wdata_o_MYF ( this_fifo.wdata ), + .data_be_o_MYF ( this_fifo.be ), + .data_gnt_i_MYF ( this_fifo.gnt ), + + .data_r_valid_i_MYF( this_fifo.r_valid ), + .data_r_rdata_i_MYF( this_fifo.r_rdata ), + .data_r_opc_i_MYF ( this_fifo.r_opc ), + + .data_req_o_NBF ( next_fifo_master.req ), + .data_add_o_NBF ( next_fifo_master.add ), + .data_wen_o_NBF ( next_fifo_master.wen ), + .data_wdata_o_NBF ( next_fifo_master.wdata ), + .data_be_o_NBF ( next_fifo_master.be ), + .data_gnt_i_NBF ( next_fifo_master.gnt ), + + .data_r_valid_i_NBF( next_fifo_master.r_valid ), + .data_r_rdata_i_NBF( next_fifo_master.r_rdata ), + .data_r_opc_i_NBF ( next_fifo_master.r_opc ), + + .data_req_o_HDRV ( hpu_driver_master.req ), + .data_add_o_HDRV ( hpu_driver_master.add ), + .data_wen_o_HDRV ( hpu_driver_master.wen ), + .data_wdata_o_HDRV ( hpu_driver_master.wdata), + .data_be_o_HDRV ( hpu_driver_master.be ), + .data_gnt_i_HDRV ( hpu_driver_master.gnt ), + + .data_r_valid_i_HDRV( hpu_driver_master.r_valid ), + .data_r_rdata_i_HDRV( hpu_driver_master.r_rdata ), + .data_r_opc_i_HDRV ( hpu_driver_master.r_opc ) + + + ); + + if (INTER_CORE_FIFO_DEPTH > 0) begin : gen_inter_core_fifo + inter_core_fifo #( + .Depth (INTER_CORE_FIFO_DEPTH) + ) i_inter_core_fifo ( + .clk_i, + .rst_ni, + .push_slv (this_fifo_slave), + .pop_slv (this_fifo) + ); + end else begin : gen_no_inter_core_fifo + assign this_fifo_slave.gnt = 1'b1; + assign this_fifo_slave.r_valid = 1'b1; + assign this_fifo_slave.r_rdata = '0; + assign this_fifo_slave.r_opc = '0; + assign this_fifo.gnt = 1'b1; + assign this_fifo.r_valid = 1'b1; + assign this_fifo.r_rdata = '0; + assign this_fifo.r_opc = '0; + end + + virtual_stdout_demux #( + .CoreId (CORE_ID) + ) i_stdout ( + .clk_i (clk_int), + .rst_ni, + .cluster_id_i, + .periph_slv (periph_data_buf), + .periph_slv_atop_i (periph_data_buf_atop), + .periph_mst (periph_data_master), + .periph_mst_atop_o (periph_data_master_atop) + ); + + /* debug stuff */ + //synopsys translate_off + + // COMPARE THE output of the instruction CACHE with the slm files generated by the compiler +`ifdef DEBUG_FETCH_INTERFACE + integer FILE; + string FILENAME; + string FILE_ID; + + logic instr_gnt_L2; + logic instr_gnt_ROM; + logic [INSTR_RDATA_WIDTH-1:0] instr_r_rdata_ROM; + logic instr_r_valid_ROM; + logic [INSTR_RDATA_WIDTH-1:0] instr_r_rdata_L2; + logic instr_r_valid_L2; + logic destination; //--> 0 fetch from BOOT_ROM, 1--> fetch from L2_MEMORY + + initial + begin + FILE_ID.itoa(CORE_ID); + FILENAME = {"FETCH_CORE_", FILE_ID, ".log" }; + FILE=$fopen(FILENAME,"w"); + end + + // BOOT code is loaded in this dummy ROM_MEMORY +/* -----\/----- EXCLUDED -----\/----- + generate + case(INSTR_RDATA_WIDTH) + 128: begin + ibus_lint_memory_128 #( + .addr_width ( 16 ), + .INIT_MEM_FILE ( ROM_SLM_FILE ) + ) ROM_MEMORY ( + .clk ( clk_i ), + .rst_n ( rst_ni ), + .lint_req_i ( instr_req_o ), + .lint_grant_o ( instr_gnt_ROM ), + .lint_addr_i ( instr_addr_o[19:4] ), //instr_addr_o[17:2] --> 2^17 bytes max program + .lint_r_rdata_o ( instr_r_rdata_ROM ), + .lint_r_valid_o ( instr_r_valid_ROM ) + ); + + // application code is loaded in this dummy L2_MEMORY + ibus_lint_memory_128 #( + .addr_width ( 16 ), + .INIT_MEM_FILE ( L2_SLM_FILE ) + ) L2_MEMORY ( + .clk ( clk_i ), + .rst_n ( rst_ni ), + .lint_req_i ( instr_req_o ), + .lint_grant_o ( instr_gnt_L2 ), + .lint_addr_i ( instr_addr_o[19:4] ), //instr_addr_o[17:2] --> 2^17 bytes max program + .lint_r_rdata_o ( instr_r_rdata_L2 ), + .lint_r_valid_o ( instr_r_valid_L2 ) + ); + end + 32: begin + ibus_lint_memory #( + .addr_width ( 16 ), + .INIT_MEM_FILE ( ROM_SLM_FILE ) + ) ROM_MEMORY ( + .clk ( clk_i ), + .rst_n ( rst_ni ), + .lint_req_i ( instr_req_o ), + .lint_grant_o ( instr_gnt_ROM ), + .lint_addr_i ( instr_addr_o[17:2] ), //instr_addr_o[17:2] --> 2^17 bytes max program + .lint_r_rdata_o ( instr_r_rdata_ROM ), + .lint_r_valid_o ( instr_r_valid_ROM ) + ); + + // application code is loaded in this dummy L2_MEMORY + ibus_lint_memory #( + .addr_width ( 16 ), + .INIT_MEM_FILE ( L2_SLM_FILE ) + ) L2_MEMORY ( + .clk ( clk_i ), + .rst_n ( rst_ni ), + .lint_req_i ( instr_req_o ), + .lint_grant_o ( instr_gnt_L2 ), + .lint_addr_i ( instr_addr_o[17:2] ), //instr_addr_o[17:2] --> 2^17 bytes max program + .lint_r_rdata_o ( instr_r_rdata_L2 ), + .lint_r_valid_o ( instr_r_valid_L2 ) + ); + end + endcase // INSTR_RDATA_WIDTH + endgenerate + -----/\----- EXCLUDED -----/\----- */ + + // SELF CHECK ROUTINES TO compare isntruction fetches with slm files + always_ff @(posedge clk_i) + begin + if(instr_r_valid_i) begin + $fwrite( FILE , "\t --> %8h\n",instr_r_rdata_i); + case(destination) + 1'b1: begin + // Not active by default as it is wrong once the code is dynamically modified + //if(instr_r_rdata_i !== instr_r_rdata_L2) + //begin + // $warning("Error DURING L2 fetch: %x != %x", instr_r_rdata_i, instr_r_rdata_L2); + // $stop(); + //end + end + 1'b0: begin + if(instr_r_rdata_i !== instr_r_rdata_ROM) begin + $warning("Error DURING ROM Fetch: %x != %x", instr_r_rdata_i, instr_r_rdata_ROM); + $stop(); + end + end + endcase + end + //DUMP TO FILE every transaction to instruction cache + if(instr_req_o & instr_gnt_i) begin + if(instr_addr_o[31:24] == 8'h1A) + destination <= 1'b0; + else + destination <= 1'b1; +`ifdef DUMP_INSTR_FETCH + $fwrite( FILE , "%t [ns]: FETCH at address %8h",$time/1000, instr_addr_o); +`endif + end + end +`endif + +`ifdef DATA_MISS + logic data_hit; + logic req; +`endif + logic reg_cache_refill; + + always_ff @(posedge clk_i , negedge rst_ni) + begin + if ( rst_ni == 1'b0 ) begin + reg_cache_refill <= 1'b0; + end + else begin + if (instr_req_o) + reg_cache_refill <= 1'b1; + else if(instr_r_valid_i && !instr_req_o) + reg_cache_refill <= 1'b0; + end + end +//synopsys translate_on + +/* verilator tracing_off */ + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/cpu_marx_if.sv b/hw/deps/pulp_cluster/rtl/cpu_marx_if.sv new file mode 100644 index 0000000..971d8dd --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/cpu_marx_if.sv @@ -0,0 +1,63 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +interface cpu_marx_if #( + parameter WOP_CPU = 0, + parameter WAPUTYPE = 0, + parameter NUSFLAGS_CPU = 1, + parameter NDSFLAGS_CPU = 1, + parameter WRESULT = 32, + parameter WARG = 32, + parameter NARGS_CPU = 3 +); + + // Downstream + logic req_ds_s; + logic ack_ds_s; + logic [WAPUTYPE-1:0] type_ds_d; + logic [WARG-1:0] operands_ds_d [NARGS_CPU-1:0]; + logic [WOP_CPU-1:0] op_ds_d; + logic [NDSFLAGS_CPU-1:0] flags_ds_d; + + // Upstream + logic valid_us_s; + logic ready_us_s; + logic [WRESULT-1:0] result_us_d; + logic [NUSFLAGS_CPU-1:0] flags_us_d; + + // The interface from the perspective of the core. + modport cpu ( + output req_ds_s, + output type_ds_d, + output operands_ds_d, + output op_ds_d, + output flags_ds_d, + output ready_us_s, + input ack_ds_s, + input valid_us_s, + input result_us_d, + input flags_us_d + ); + + // The interface from the perspective of the interconnect. + modport marx ( + input req_ds_s, + input type_ds_d, + input operands_ds_d, + input op_ds_d, + input ready_us_s, + input flags_ds_d, + output ack_ds_s, + output valid_us_s, + output result_us_d, + output flags_us_d + ); + +endinterface diff --git a/hw/deps/pulp_cluster/rtl/dmac_wrap.sv b/hw/deps/pulp_cluster/rtl/dmac_wrap.sv new file mode 100644 index 0000000..21eea72 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/dmac_wrap.sv @@ -0,0 +1,359 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * dmac_wrap.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + * Thomas Benz + */ + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module dmac_wrap +#( + parameter NB_CORES = 4, + parameter NB_OUTSND_BURSTS = 8, + parameter MCHAN_BURST_LENGTH = 256, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 4, + parameter PE_ID_WIDTH = 1, + parameter TCDM_ADD_WIDTH = 13, + parameter DATA_WIDTH = 32, + parameter ADDR_WIDTH = 32, + parameter BE_WIDTH = DATA_WIDTH/8, + parameter DMA_AXI_AW_WIDTH = 32, + parameter DMA_AXI_DW_WIDTH = 512, + parameter DMA_AXI_ID_WIDTH = 4, + parameter DMA_AXI_UW_WIDTH = 4, + parameter TF_REQ_FIFO_DEPTH = 4, + + parameter type dma_transf_descr_t = logic +) +( + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + input logic [5:0] cluster_id_i, + XBAR_PERIPH_BUS.Slave pe_ctrl_slave, + XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0], + XBAR_TCDM_BUS.Master tcdm_master[3:0], + AXI_BUS.Master ext_master, + AXI_BUS.Master s_wide_dma_soc, + WIDE_DMA_TCDM_BUS.Master s_wide_dma_superbanks, + output logic [NB_CORES-1:0] term_event_o, + output logic [NB_CORES-1:0] term_irq_o, + output logic term_event_pe_o, + output logic term_irq_pe_o, + output logic busy_o, + + input logic ext_dma_req_valid_i, + output logic ext_dma_req_ready_o, + input dma_transf_descr_t ext_dma_req_i, + + output logic ext_dma_rsp_valid_o, + + output logic [NB_CORES-1:0] no_req_pending_o + +); + + // CORE --> MCHAN CTRL INTERFACE BUS SIGNALS + logic [NB_CORES-1:0][DATA_WIDTH-1:0] s_ctrl_bus_wdata; + logic [NB_CORES-1:0][ADDR_WIDTH-1:0] s_ctrl_bus_add; + logic [NB_CORES-1:0] s_ctrl_bus_req; + logic [NB_CORES-1:0] s_ctrl_bus_wen; + logic [NB_CORES-1:0][BE_WIDTH-1:0] s_ctrl_bus_be; + logic [NB_CORES-1:0] s_ctrl_bus_gnt; + logic [NB_CORES-1:0][DATA_WIDTH-1:0] s_ctrl_bus_r_rdata; + logic [NB_CORES-1:0] s_ctrl_bus_r_valid; + + // MCHAN TCDM INIT --> TCDM MEMORY BUS SIGNALS + logic [3:0][DATA_WIDTH-1:0] s_tcdm_bus_wdata; + logic [3:0][ADDR_WIDTH-1:0] s_tcdm_bus_add; + logic [3:0] s_tcdm_bus_req; + logic [3:0] s_tcdm_bus_wen; + logic [3:0][BE_WIDTH-1:0] s_tcdm_bus_be; + logic [3:0] s_tcdm_bus_gnt; + logic [3:0][DATA_WIDTH-1:0] s_tcdm_bus_r_rdata; + logic [3:0] s_tcdm_bus_r_valid; + + generate + for (genvar i=0; i this delay needs to be explicitly + // calculated. + logic ext_dma_vld; + always_ff @(posedge clk_i) begin : proc_delay_gnt_by_one + if(~rst_ni) begin + ext_dma_vld <= 0; + end else begin + ext_dma_vld <= s_wide_dma_superbanks.gnt & s_wide_dma_superbanks.req; + end + end + + axi_to_mem_interleaved #( + .axi_req_t ( axi_dma_req_t ), + .axi_resp_t ( axi_dma_resp_t ), + .AddrWidth ( DMA_AXI_AW_WIDTH ), + .DataWidth ( DMA_AXI_DW_WIDTH ), + .IdWidth ( DMA_AXI_ID_WIDTH ), + .NumBanks ( 1 ), // Needs to be 1 + .BufDepth ( 4 ) // TODO: tune me + ) i_axi_to_mem ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .busy_o ( ), + .axi_req_i ( axi_dma_tcdm_req ), + .axi_resp_o ( axi_dma_tcdm_res ), + .mem_req_o ( s_wide_dma_superbanks.req ), + .mem_gnt_i ( s_wide_dma_superbanks.gnt ), + .mem_addr_o ( s_wide_dma_superbanks.add ), + .mem_wdata_o ( s_wide_dma_superbanks.wdata ), + .mem_strb_o ( s_wide_dma_superbanks.be ), + .mem_atop_o ( ), + .mem_we_o ( s_wide_dma_superbanks.wen ), + .mem_rvalid_i ( ext_dma_vld ), + .mem_rdata_i ( s_wide_dma_superbanks.r_rdata ) + ); + + // tie-off unused pulp ports + assign s_tcdm_bus_req = '0; + assign s_tcdm_bus_add = '0; + assign s_tcdm_bus_wen = '0; + assign s_tcdm_bus_be = '0; + assign s_tcdm_bus_wdata = '0; + assign internal.aw_valid = '0; + assign internal.aw_addr = '0; + assign internal.aw_prot = '0; + assign internal.aw_region = '0; + assign internal.aw_atop = '0; + assign internal.aw_len = '0; + assign internal.aw_size = '0; + assign internal.aw_burst = '0; + assign internal.aw_lock = '0; + assign internal.aw_cache = '0; + assign internal.aw_qos = '0; + assign internal.aw_id[AXI_ID_WIDTH-1:0] = '0; + assign internal.aw_user = '0; + assign internal.ar_valid = '0; + assign internal.ar_addr = '0; + assign internal.ar_prot = '0; + assign internal.ar_region = '0; + assign internal.ar_len = '0; + assign internal.ar_size = '0; + assign internal.ar_burst = '0; + assign internal.ar_lock = '0; + assign internal.ar_cache = '0; + assign internal.ar_qos = '0; + assign internal.ar_id[AXI_ID_WIDTH-1:0] = '0; + assign internal.ar_user = '0; + assign internal.w_valid = '0; + assign internal.w_data = '0; + assign internal.w_strb = '0; + assign internal.w_user = '0; + assign internal.r_ready = '0; + assign internal.b_ready = '0; + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/inter_core_fifo.sv b/hw/deps/pulp_cluster/rtl/inter_core_fifo.sv new file mode 100644 index 0000000..6eff249 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/inter_core_fifo.sv @@ -0,0 +1,116 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "common_cells/registers.svh" + +module inter_core_fifo #( + parameter int unsigned Depth = 32'd0 +) ( + input logic clk_i, + input logic rst_ni, + XBAR_PERIPH_BUS.Slave push_slv, + XBAR_PERIPH_BUS.Slave pop_slv +); + + localparam int unsigned CntWidth = (Depth > 1) ? $clog2(Depth) : 1; + localparam int unsigned DataWidth = 32; + + typedef logic [CntWidth-1:0] cnt_t; + typedef logic [DataWidth-1:0] data_t; + + cnt_t usage; + data_t pop_data; + logic pop_rvalid_d, pop_rvalid_q, + push_rvalid_d, push_rvalid_q, + push_valid, + push_ready, + pop_valid, + pop_ready; + enum logic {Data, Usage} + pop_rdata_src_d, pop_rdata_src_q; + + stream_fifo #( + .FALL_THROUGH (1'b0), + .DEPTH (Depth), + .T (data_t) + ) i_fifo ( + .clk_i, + .rst_ni, + .flush_i (1'b0), + .testmode_i (1'b0), + .data_i (push_slv.wdata), + .valid_i (push_valid), + .ready_o (push_ready), + .data_o (pop_data), + .valid_o (pop_valid), + .ready_i (pop_ready), + .usage_o (usage) + ); + + // Handle push interface. + assign push_slv.r_rdata = {{DataWidth-CntWidth{1'b0}}, usage}; + assign push_slv.r_opc = '0; + assign push_slv.r_id = '0; + assign push_slv.r_valid = push_rvalid_q; + always_comb begin + push_rvalid_d = 1'b0; + push_slv.gnt = 1'b0; + push_valid = 1'b0; + if (push_slv.req) begin + unique case ({push_slv.wen, push_slv.add[3:0]}) + {1'b0, 4'h0}: begin // write to push address + push_valid = 1'b1; + push_slv.gnt = push_ready; + if (push_ready) begin + push_rvalid_d = 1'b1; + end + end + default: begin // all reads and other writes return the current fill count + push_slv.gnt = 1'b1; + push_rvalid_d = 1'b1; + end + endcase + end + end + + // Handle pop interface. + assign pop_ready = pop_rvalid_q; + assign pop_slv.r_valid = pop_rvalid_q; + assign pop_slv.r_rdata = pop_rdata_src_q == Data ? pop_data : {{DataWidth-CntWidth{1'b0}}, usage}; + always_comb begin + pop_rdata_src_d = Data; + pop_rvalid_d = 1'b0; + pop_slv.gnt = 1'b0; + if (pop_slv.req) begin + unique case ({pop_slv.wen, pop_slv.add[3:0]}) + {1'b1, 4'h0}: begin // read from pop address + // Since the actual pop happens in the next cycle, we need to prevent an underrun by + // accepting two consecutive pop requests if the current usage is 1. So if the usage is + // one, we require that we are not popping in the current cycle. + if (pop_valid && (usage != 1 || !pop_ready)) begin + pop_slv.gnt = 1'b1; + pop_rvalid_d = 1'b1; + end + end + default: begin // all writes and other reads return the current fill count + pop_slv.gnt = 1'b1; + pop_rdata_src_d = Usage; + pop_rvalid_d = 1'b1; + end + endcase + end + end + + `FFARN(pop_rdata_src_q, pop_rdata_src_d, Data, clk_i, rst_ni) + `FFARN(pop_rvalid_q, pop_rvalid_d, 1'b0, clk_i, rst_ni) + `FFARN(push_rvalid_q, push_rvalid_d, 1'b0, clk_i, rst_ni) + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/nhi_port_wrap.sv b/hw/deps/pulp_cluster/rtl/nhi_port_wrap.sv new file mode 100644 index 0000000..7a469f6 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/nhi_port_wrap.sv @@ -0,0 +1,86 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module nhi_port_wrap +#( + parameter DMA_AXI_AW_WIDTH = 32, + parameter DMA_AXI_DW_WIDTH = 512, + parameter DMA_AXI_ID_WIDTH = 4, + parameter DMA_AXI_UW_WIDTH = 4 +) ( + input logic clk_i, + input logic rst_ni, + + WIDE_DMA_TCDM_BUS.Master s_wide_dma_superbanks, + AXI_BUS.Slave s_wide_dma_nhi +); + + // axi definition + typedef logic [DMA_AXI_AW_WIDTH-1 :0] addr_t; + typedef logic [DMA_AXI_DW_WIDTH-1 :0] data_t; + typedef logic [DMA_AXI_ID_WIDTH-1 :0] id_oup_t; + typedef logic [DMA_AXI_DW_WIDTH/8-1:0] strb_t; + typedef logic [DMA_AXI_UW_WIDTH-1 :0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_oup_t, user_t); + `AXI_TYPEDEF_W_CHAN_T (w_chan_t, data_t, strb_t, user_t); + `AXI_TYPEDEF_B_CHAN_T (b_chan_t, id_oup_t, user_t); + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_oup_t, user_t); + `AXI_TYPEDEF_R_CHAN_T (r_chan_t, data_t, id_oup_t, user_t); + `AXI_TYPEDEF_REQ_T (axi_dma_req_t, aw_chan_t, w_chan_t, ar_chan_t); + `AXI_TYPEDEF_RESP_T (axi_dma_resp_t, b_chan_t, r_chan_t); + axi_dma_req_t axi_dma_tcdm_req; + axi_dma_resp_t axi_dma_tcdm_res; + + // connect to external AXI + `AXI_ASSIGN_TO_REQ(axi_dma_tcdm_req, s_wide_dma_nhi); + `AXI_ASSIGN_FROM_RESP (s_wide_dma_nhi, axi_dma_tcdm_res); + + // the data returned by the memories is always valid 1 cycle later + // this is usually handled by the TCDM interconnect correctly + // we bypass TCDM ic here -> this delay needs to be explicitly + // calculated. + logic ext_dma_vld; + always_ff @(posedge clk_i) begin : proc_delay_gnt_by_one + if(~rst_ni) begin + ext_dma_vld <= 0; + end else begin + ext_dma_vld <= s_wide_dma_superbanks.gnt & s_wide_dma_superbanks.req; + end + end + + axi_to_mem_interleaved #( + .axi_req_t ( axi_dma_req_t ), + .axi_resp_t ( axi_dma_resp_t ), + .AddrWidth ( DMA_AXI_AW_WIDTH ), + .DataWidth ( DMA_AXI_DW_WIDTH ), + .IdWidth ( DMA_AXI_ID_WIDTH ), + .NumBanks ( 1 ), // Needs to be 1 + .BufDepth ( 4 ) // TODO: tune me + ) i_axi_to_mem_nhi ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .busy_o ( ), + .axi_req_i ( axi_dma_tcdm_req ), + .axi_resp_o ( axi_dma_tcdm_res ), + .mem_req_o ( s_wide_dma_superbanks.req ), + .mem_gnt_i ( s_wide_dma_superbanks.gnt ), + .mem_addr_o ( s_wide_dma_superbanks.add ), + .mem_wdata_o ( s_wide_dma_superbanks.wdata ), + .mem_strb_o ( s_wide_dma_superbanks.be ), + .mem_atop_o ( ), + .mem_we_o ( s_wide_dma_superbanks.wen ), + .mem_rvalid_i ( ext_dma_vld ), + .mem_rdata_i ( s_wide_dma_superbanks.r_rdata ) + ); + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/per2axi_wrap.sv b/hw/deps/pulp_cluster/rtl/per2axi_wrap.sv new file mode 100644 index 0000000..76d4557 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/per2axi_wrap.sv @@ -0,0 +1,129 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * per2axi_wrap.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +module per2axi_wrap +#( + parameter NB_CORES = 4, + parameter PER_ADDR_WIDTH = 32, + parameter PER_ID_WIDTH = 5, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_DATA_WIDTH = 64, + parameter AXI_USER_WIDTH = 6, + parameter AXI_ID_WIDTH = 4, + parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 +) +( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + XBAR_PERIPH_BUS.Slave periph_slave, + input logic [5:0] periph_slave_atop_i, + input logic [NB_CORES-1:0][AXI_USER_WIDTH-1:0] axi_axuser_i, + output logic [NB_CORES-1:0] axi_xresp_decerr_o, + output logic [NB_CORES-1:0] axi_xresp_slverr_o, + output logic [NB_CORES-1:0] axi_xresp_valid_o, + AXI_BUS.Master axi_master, + output logic busy_o +); + + per2axi #( + .NB_CORES ( NB_CORES ), + .PER_ADDR_WIDTH ( PER_ADDR_WIDTH ), + .PER_ID_WIDTH ( PER_ID_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + ) per2axi_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + + .per_slave_req_i ( periph_slave.req ), + .per_slave_add_i ( periph_slave.add ), + .per_slave_we_i ( periph_slave.wen ), + .per_slave_atop_i ( periph_slave_atop_i ), + .per_slave_wdata_i ( periph_slave.wdata ), + .per_slave_be_i ( periph_slave.be ), + .per_slave_id_i ( periph_slave.id[PER_ID_WIDTH-1:0] ), + .per_slave_gnt_o ( periph_slave.gnt ), + + .per_slave_r_valid_o ( periph_slave.r_valid ), + .per_slave_r_opc_o ( periph_slave.r_opc ), + .per_slave_r_id_o ( periph_slave.r_id[PER_ID_WIDTH-1:0] ), + .per_slave_r_rdata_o ( periph_slave.r_rdata ), + + .axi_axuser_i ( axi_axuser_i ), + .axi_xresp_decerr_o ( axi_xresp_decerr_o ), + .axi_xresp_slverr_o ( axi_xresp_slverr_o ), + .axi_xresp_valid_o ( axi_xresp_valid_o ), + + .axi_master_aw_valid_o ( axi_master.aw_valid ), + .axi_master_aw_addr_o ( axi_master.aw_addr ), + .axi_master_aw_prot_o ( axi_master.aw_prot ), + .axi_master_aw_region_o ( axi_master.aw_region ), + .axi_master_aw_len_o ( axi_master.aw_len ), + .axi_master_aw_size_o ( axi_master.aw_size ), + .axi_master_aw_burst_o ( axi_master.aw_burst ), + .axi_master_aw_lock_o ( axi_master.aw_lock ), + .axi_master_aw_atop_o ( axi_master.aw_atop ), + .axi_master_aw_cache_o ( axi_master.aw_cache ), + .axi_master_aw_qos_o ( axi_master.aw_qos ), + .axi_master_aw_id_o ( axi_master.aw_id[AXI_ID_WIDTH-1:0] ), + .axi_master_aw_user_o ( axi_master.aw_user ), + .axi_master_aw_ready_i ( axi_master.aw_ready ), + + .axi_master_ar_valid_o ( axi_master.ar_valid ), + .axi_master_ar_addr_o ( axi_master.ar_addr ), + .axi_master_ar_prot_o ( axi_master.ar_prot ), + .axi_master_ar_region_o ( axi_master.ar_region ), + .axi_master_ar_len_o ( axi_master.ar_len ), + .axi_master_ar_size_o ( axi_master.ar_size ), + .axi_master_ar_burst_o ( axi_master.ar_burst ), + .axi_master_ar_lock_o ( axi_master.ar_lock ), + .axi_master_ar_cache_o ( axi_master.ar_cache ), + .axi_master_ar_qos_o ( axi_master.ar_qos ), + .axi_master_ar_id_o ( axi_master.ar_id[AXI_ID_WIDTH-1:0] ), + .axi_master_ar_user_o ( axi_master.ar_user ), + .axi_master_ar_ready_i ( axi_master.ar_ready ), + + .axi_master_w_valid_o ( axi_master.w_valid ), + .axi_master_w_data_o ( axi_master.w_data ), + .axi_master_w_strb_o ( axi_master.w_strb ), + .axi_master_w_user_o ( axi_master.w_user ), + .axi_master_w_last_o ( axi_master.w_last ), + .axi_master_w_ready_i ( axi_master.w_ready ), + + .axi_master_r_valid_i ( axi_master.r_valid ), + .axi_master_r_data_i ( axi_master.r_data ), + .axi_master_r_resp_i ( axi_master.r_resp ), + .axi_master_r_last_i ( axi_master.r_last ), + .axi_master_r_id_i ( axi_master.r_id[AXI_ID_WIDTH-1:0] ), + .axi_master_r_user_i ( axi_master.r_user ), + .axi_master_r_ready_o ( axi_master.r_ready ), + + .axi_master_b_valid_i ( axi_master.b_valid ), + .axi_master_b_resp_i ( axi_master.b_resp ), + .axi_master_b_id_i ( axi_master.b_id[AXI_ID_WIDTH-1:0] ), + .axi_master_b_user_i ( axi_master.b_user ), + .axi_master_b_ready_o ( axi_master.b_ready ), + + .busy_o ( busy_o ) + ); + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/per_demux_wrap.sv b/hw/deps/pulp_cluster/rtl/per_demux_wrap.sv new file mode 100644 index 0000000..fc7bee2 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/per_demux_wrap.sv @@ -0,0 +1,75 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * per_demux_wrap.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +module per_demux_wrap +#( + parameter NB_MASTERS = 2, + parameter ADDR_OFFSET = 10 +) +( + input logic clk_i, + input logic rst_ni, + XBAR_TCDM_BUS.Slave slave, + XBAR_TCDM_BUS.Master masters[NB_MASTERS-1:0] +); + + localparam NB_MASTERS_LOG = $clog2(NB_MASTERS); + + logic [NB_MASTERS_LOG-1:0] dest_q, dest_n; + + // need to explode the interfaces here because SystemVerilog does not allow + // to use it directly...... + logic [NB_MASTERS-1:0] masters_gnt; + logic [NB_MASTERS-1:0] masters_r_valid; + logic [NB_MASTERS-1:0] masters_r_opc; + logic [NB_MASTERS-1:0][31:0] masters_r_data; + + generate + for (genvar i = 0; i < NB_MASTERS; i++) begin + assign masters[i].req = (dest_n == i) ? slave.req : 1'b0; + assign masters[i].add = slave.add; + assign masters[i].wen = slave.wen; + assign masters[i].wdata = slave.wdata; + assign masters[i].be = slave.be; + + // for exploded interface + assign masters_gnt[i] = masters[i].gnt; + assign masters_r_valid[i] = masters[i].r_valid; + assign masters_r_opc[i] = masters[i].r_opc; + assign masters_r_data[i] = masters[i].r_rdata; + end + endgenerate + + assign slave.gnt = masters_gnt[dest_n]; + assign slave.r_valid = masters_r_valid[dest_q]; + assign slave.r_opc = masters_r_opc[dest_q]; + assign slave.r_rdata = masters_r_data[dest_q]; + + assign dest_n = slave.add[NB_MASTERS_LOG-1+ADDR_OFFSET:ADDR_OFFSET]; + + always_ff @(posedge clk_i, negedge rst_ni) + begin + if (~rst_ni) begin + dest_q <= '0; + end + else begin + dest_q <= dest_n; + end + end + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/periph_FIFO.sv b/hw/deps/pulp_cluster/rtl/periph_FIFO.sv new file mode 100644 index 0000000..e5500df --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/periph_FIFO.sv @@ -0,0 +1,86 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * periph_FIFO.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +module periph_FIFO +#( + parameter ADDR_WIDTH=32, + parameter DATA_WIDTH=32, + parameter BYTE_ENABLE_BIT=DATA_WIDTH/8 +) +( + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + + //Input SIde REQ + input logic data_req_i, + input logic [ADDR_WIDTH - 1:0] data_add_i, + input logic data_wen_i, + input logic [5:0] data_atop_i, + input logic [DATA_WIDTH - 1:0] data_wdata_i, + input logic [BYTE_ENABLE_BIT - 1:0] data_be_i, + output logic data_gnt_o, + + //Output side REQ + output logic data_req_o, + output logic [ADDR_WIDTH - 1:0] data_add_o, + output logic data_wen_o, + output logic [5:0] data_atop_o, + output logic [DATA_WIDTH - 1:0] data_wdata_o, + output logic [BYTE_ENABLE_BIT - 1:0] data_be_o, + input logic data_gnt_i, + + //Input SIde RESP + input logic data_r_valid_i, + input logic data_r_opc_i, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i, + + //Output SIde RESP + output logic data_r_valid_o, + output logic data_r_opc_o, + output logic [DATA_WIDTH - 1:0] data_r_rdata_o +); + + localparam FIFO_DW = ADDR_WIDTH + 1 + 6 + DATA_WIDTH + BYTE_ENABLE_BIT; + + logic [FIFO_DW-1:0] DATA_IN; + logic [FIFO_DW-1:0] DATA_OUT; + + assign DATA_IN = { data_add_i, data_wen_i, data_atop_i, data_wdata_i, data_be_i }; + assign { data_add_o, data_wen_o, data_atop_o, data_wdata_o, data_be_o } = DATA_OUT; + + generic_fifo #( + .DATA_WIDTH ( FIFO_DW ), + .DATA_DEPTH ( 2 ) + ) FIFO_REQ ( + .clk ( clk_i ), + .rst_n ( rst_ni ), + .test_mode_i ( test_en_i ), + .data_i ( DATA_IN ), + .valid_i ( data_req_i ), + .grant_o ( data_gnt_o ), + .data_o ( DATA_OUT ), + .valid_o ( data_req_o ), + .grant_i ( data_gnt_i ) + ); + + assign data_r_valid_o = data_r_valid_i; + assign data_r_opc_o = data_r_opc_i; + assign data_r_rdata_o = data_r_rdata_i; + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/periph_demux.sv b/hw/deps/pulp_cluster/rtl/periph_demux.sv new file mode 100644 index 0000000..1c3a293 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/periph_demux.sv @@ -0,0 +1,267 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * periph_demux.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + */ + +module periph_demux +#( + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 32, + parameter int BE_WIDTH = DATA_WIDTH/8, + parameter bit DEM_PER_BEFORE_TCDM_TS = 1'b0 +) +( + input logic clk, + input logic rst_ni, + + // CORE SIDE + input logic data_req_i, + input logic [ADDR_WIDTH - 1:0] data_add_i, + input logic data_wen_i, + input logic [DATA_WIDTH - 1:0] data_wdata_i, + input logic [BE_WIDTH - 1:0] data_be_i, + output logic data_gnt_o, + + output logic data_r_valid_o, // Data Response Valid (For LOAD/STORE commands) + output logic [DATA_WIDTH - 1:0] data_r_rdata_o, // Data Response DATA (For LOAD commands) + output logic data_r_opc_o, // Data Response Error + + // Low Latency log interconnect SIDE + output logic data_req_o_MH, + output logic [ADDR_WIDTH - 1:0] data_add_o_MH, + output logic data_wen_o_MH, + output logic [DATA_WIDTH - 1:0] data_wdata_o_MH, + output logic [BE_WIDTH - 1:0] data_be_o_MH, + input logic data_gnt_i_MH, + input logic data_r_valid_i_MH, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_MH, + input logic data_r_opc_i_MH, + + //low latency event unit access, sleep_req,clear buffer_req + output logic data_req_o_EU, + output logic [ADDR_WIDTH - 1:0] data_add_o_EU, + output logic data_wen_o_EU, + output logic [DATA_WIDTH - 1:0] data_wdata_o_EU, + output logic [BE_WIDTH - 1:0] data_be_o_EU, + input logic data_gnt_i_EU, + input logic data_r_valid_i_EU, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_EU, + input logic data_r_opc_i_EU, + + // my FIFO + output logic data_req_o_MYF, + output logic [ADDR_WIDTH - 1:0] data_add_o_MYF, + output logic data_wen_o_MYF, + output logic [DATA_WIDTH - 1:0] data_wdata_o_MYF, + output logic [BE_WIDTH - 1:0] data_be_o_MYF, + input logic data_gnt_i_MYF, + input logic data_r_valid_i_MYF, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_MYF, + input logic data_r_opc_i_MYF, + + // neighbor FIFO + output logic data_req_o_NBF, + output logic [ADDR_WIDTH - 1:0] data_add_o_NBF, + output logic data_wen_o_NBF, + output logic [DATA_WIDTH - 1:0] data_wdata_o_NBF, + output logic [BE_WIDTH - 1:0] data_be_o_NBF, + input logic data_gnt_i_NBF, + input logic data_r_valid_i_NBF, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_NBF, + input logic data_r_opc_i_NBF, + + // HPU driver + output logic data_req_o_HDRV, + output logic [ADDR_WIDTH - 1:0] data_add_o_HDRV, + output logic data_wen_o_HDRV, + output logic [DATA_WIDTH - 1:0] data_wdata_o_HDRV, + output logic [BE_WIDTH - 1:0] data_be_o_HDRV, + input logic data_gnt_i_HDRV, + input logic data_r_valid_i_HDRV, + input logic [DATA_WIDTH - 1:0] data_r_rdata_i_HDRV, + input logic data_r_opc_i_HDRV +); + + enum logic [2:0] {MH, EU, MYF, NBF, HDRV, UNMAPPED } request_destination; + + always_ff @(posedge clk, negedge rst_ni) begin : _UPDATE_RESPONSE_DESTINATION_ + if(rst_ni == 1'b0) begin + request_destination <= MH; + end + else begin + if (data_req_i) begin + if (DEM_PER_BEFORE_TCDM_TS) begin + case(data_add_i[13:10]) + 4'b1111 : begin : _DPBTT_EVENT_UNIT_REGS + request_destination <= EU; + end + 4'b1110 : begin : _DPBTT_MCHAN_REGISTERS_ + request_destination <= MH; + end + default: begin : _DPBTT_UNMAPPED_REGION_ + request_destination <= UNMAPPED; + end + endcase // data_add_i[13:10] + end else begin + if( (data_add_i[19:14] == 6'b000001 ) ) begin // this means 0x1020_4000 to 1020_7FFF + case(data_add_i[13:10]) + 0 : begin : _EVENT_UNIT_REGS + request_destination <= EU; + end + 1 : begin : _MCHAN_REGISTERS_ + request_destination <= MH; + end + 2 : begin + request_destination <= MYF; + end + 3 : begin + request_destination <= NBF; + end + 4 : begin + request_destination <= HDRV; + end + default : begin : _UNMAPPED_REGION_ + request_destination <= UNMAPPED; + end + endcase // data_add_i[10:13] + end + end + end + end + end + + assign data_add_o_MH = data_add_i; + assign data_wen_o_MH = data_wen_i; + assign data_wdata_o_MH = data_wdata_i; + assign data_be_o_MH = data_be_i; + + assign data_add_o_EU = data_add_i; + assign data_wen_o_EU = data_wen_i; + assign data_wdata_o_EU = data_wdata_i; + assign data_be_o_EU = data_be_i; + + assign data_add_o_MYF = data_add_i; + assign data_wen_o_MYF = data_wen_i; + assign data_wdata_o_MYF = data_wdata_i; + assign data_be_o_MYF = data_be_i; + + assign data_add_o_NBF = data_add_i; + assign data_wen_o_NBF = data_wen_i; + assign data_wdata_o_NBF = data_wdata_i; + assign data_be_o_NBF = data_be_i; + + assign data_add_o_HDRV = data_add_i; + assign data_wen_o_HDRV = data_wen_i; + assign data_wdata_o_HDRV = data_wdata_i; + assign data_be_o_HDRV = data_be_i; + + always_comb + begin : _HANDLE_REQ_ + data_req_o_MH = 1'b0; + data_req_o_EU = 1'b0; + data_req_o_MYF = 1'b0; + data_req_o_NBF = 1'b0; + data_req_o_HDRV = 1'b0; + data_gnt_o = 1'b0; + if (DEM_PER_BEFORE_TCDM_TS) begin + case(data_add_i[13:10]) + 4'b1111 : begin + data_req_o_EU = data_req_i; + data_gnt_o = data_gnt_i_EU; + end + 4'b1110 : begin + data_req_o_MH = data_req_i; + data_gnt_o = data_gnt_i_MH; + end + default : begin : _TO_UNMAPPED_REGION_ + data_req_o_MH = 1'b0; + data_req_o_EU = 1'b0; + data_gnt_o = 1'b0; + end + endcase // data_add_i[13:10] + end else begin + if( (data_add_i[19:14] == 6'b000001 ) ) begin // this means 0x1020_4000 to 1020_7FFF + case(data_add_i[13:10]) + 0 : begin + data_req_o_EU = data_req_i; + data_gnt_o = data_gnt_i_EU; + end + 1 : begin + data_req_o_MH = data_req_i; + data_gnt_o = data_gnt_i_MH; + end + 2 : begin + data_req_o_MYF = data_req_i; + data_gnt_o = data_gnt_i_MYF; + end + 3 : begin + data_req_o_NBF = data_req_i; + data_gnt_o = data_gnt_i_NBF; + end + 4 : begin + data_req_o_HDRV = data_req_i; + data_gnt_o = data_gnt_i_HDRV; + end + default : begin + data_req_o_MH = 1'b0; + data_req_o_EU = 1'b0; + data_req_o_MYF = 1'b0; + data_req_o_NBF = 1'b0; + data_req_o_HDRV = 1'b0; + data_gnt_o = 1'b0; + end + endcase // data_add_i[10:13] + end + end + end + + always_comb + begin : _HANDLE_RESP_ + case(request_destination) + MH : begin : _RESP_FROM_MCHAN_ + data_r_valid_o = data_r_valid_i_MH; + data_r_rdata_o = data_r_rdata_i_MH; + data_r_opc_o = 1'b0; + end + EU : begin : _RESP_FROM_EVENT_UNIT_ + data_r_valid_o = data_r_valid_i_EU; + data_r_rdata_o = data_r_rdata_i_EU; + data_r_opc_o = 1'b0; + end + MYF: begin + data_r_valid_o = data_r_valid_i_MYF; + data_r_rdata_o = data_r_rdata_i_MYF; + data_r_opc_o = 1'b0; + end + NBF: begin + data_r_valid_o = data_r_valid_i_NBF; + data_r_rdata_o = data_r_rdata_i_NBF; + data_r_opc_o = 1'b0; + end + HDRV: begin + data_r_valid_o = data_r_valid_i_HDRV; + data_r_rdata_o = data_r_rdata_i_HDRV; + data_r_opc_o = 1'b0; + end + default : begin : _UNMAPPED_RESP_ + data_r_valid_o = 1'b0; + data_r_rdata_o = '0; + data_r_opc_o = 1'b0; + end + endcase + end + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/pulp_cluster.sv b/hw/deps/pulp_cluster/rtl/pulp_cluster.sv new file mode 100644 index 0000000..cf2a312 --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/pulp_cluster.sv @@ -0,0 +1,1844 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + * pulp_cluster.sv + * Davide Rossi + * Antonio Pullini + * Igor Loi + * Francesco Conti + * Thomas Benz + */ + +import pulp_cluster_package::*; +import apu_package::*; + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module pulp_cluster +#( + // cluster parameters + parameter bit ASYNC_INTF = 1'b1, + parameter int NB_CORES = 8, + parameter int NB_HWACC_PORTS = 0, + parameter int NB_DMAS = 4, + parameter int NB_EXT2MEM = 2, + parameter int NB_MPERIPHS = 1, + parameter int NB_SPERIPHS = 8, + parameter bit CLUSTER_ALIAS = 1'b1, + parameter int CLUSTER_ALIAS_BASE = 12'h1B0, + parameter int TCDM_SIZE = 256*1024, // [B], must be 2**N + parameter int NB_TCDM_BANKS = 16, // must be 2**N + parameter int TCDM_BANK_SIZE = TCDM_SIZE/NB_TCDM_BANKS, // [B] + parameter int TCDM_NUM_ROWS = TCDM_BANK_SIZE/4, // [words] + parameter bit XNE_PRESENT = 0, // set to 1 if XNE is present in the cluster + + // I$ parameters + parameter int SET_ASSOCIATIVE = 4, + parameter int NB_CACHE_BANKS = 4, + parameter int CACHE_LINE = 1, + parameter int CACHE_SIZE = 4096, + parameter int ICACHE_DATA_WIDTH = 128, + parameter int L2_SIZE = 256*1024, + parameter bit USE_REDUCED_TAG = 1'b1, + + // core parameters + parameter bit DEM_PER_BEFORE_TCDM_TS = 1'b0, + parameter int ROM_BOOT_ADDR = 32'h1A000000, + parameter int BOOT_ADDR = 32'h1C000000, + parameter int INSTR_RDATA_WIDTH = 128, + + // AXI parameters + parameter int AXI_ADDR_WIDTH = 32, + parameter int AXI_DATA_C2S_WIDTH = 64, + parameter int AXI_DATA_S2C_WIDTH = 64, + parameter int AXI_USER_WIDTH = 6, + parameter int AXI_ID_IN_WIDTH = 4, + parameter int AXI_ID_OUT_WIDTH = 6, + parameter int AXI_STRB_C2S_WIDTH = AXI_DATA_C2S_WIDTH/8, + parameter int AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8, + parameter int DC_SLICE_BUFFER_WIDTH = 8, + + // TCDM and log interconnect parameters + parameter int DATA_WIDTH = 32, + parameter int ADDR_WIDTH = 32, + parameter int BE_WIDTH = DATA_WIDTH/8, + parameter int TEST_SET_BIT = 20, // bit used to indicate a test-and-set operation during a load in TCDM + parameter int ADDR_MEM_WIDTH = $clog2(TCDM_BANK_SIZE/4), // WORD address width per TCDM bank (the word width is 32 bits) + + // DMA parameters + parameter int TCDM_ADD_WIDTH = ADDR_MEM_WIDTH + $clog2(NB_TCDM_BANKS) + 2, // BYTE address width TCDM + parameter int NB_OUTSND_BURSTS = 8, + parameter int MCHAN_BURST_LENGTH = 256, + + // peripheral and periph interconnect parameters + parameter int LOG_CLUSTER = 5, // unused + parameter int PE_ROUTING_LSB = 10, // LSB used as routing BIT in periph interco + parameter int PE_ROUTING_MSB = 13, // MSB used as routing BIT in periph interco + parameter int EVNT_WIDTH = 8, // size of the event bus + parameter int REMAP_ADDRESS = 0, // for cluster virtualization + + // WIDE DMA parameters + parameter int DMA_AXI_ID_WIDTH = 4, // + parameter int DMA_AXI_AW_WIDTH = 32, // DON'T CHANGE + parameter int DMA_AXI_DW_WIDTH = 512,// DON'T CHANGE + parameter int DMA_AXI_UW_WIDTH = 4 // +) +( + input logic clk_i, + input logic rst_ni, + input logic ref_clk_i, + input logic pmu_mem_pwdn_i, + + input logic [3:0] base_addr_i, + + input logic test_mode_i, + + input logic en_sa_boot_i, + + input logic [5:0] cluster_id_i, + + input logic fetch_en_i, + + output logic eoc_o, + + output logic busy_o, + + input logic [DC_SLICE_BUFFER_WIDTH-1:0] ext_events_writetoken_i, + output logic [DC_SLICE_BUFFER_WIDTH-1:0] ext_events_readpointer_o, + input logic [EVNT_WIDTH-1:0] ext_events_dataasync_i, + + input logic dma_pe_evt_ack_i, + output logic dma_pe_evt_valid_o, + + input logic dma_pe_irq_ack_i, + output logic dma_pe_irq_valid_o, + + input logic pf_evt_ack_i, + output logic pf_evt_valid_o, + + // AXI4 SLAVE + //*************************************** + // WRITE ADDRESS CHANNEL + input logic [AXI_ADDR_WIDTH-1:0] data_slave_aw_addr_i, + input axi_pkg::prot_t data_slave_aw_prot_i, + input axi_pkg::region_t data_slave_aw_region_i, + input axi_pkg::len_t data_slave_aw_len_i, + input axi_pkg::size_t data_slave_aw_size_i, + input axi_pkg::burst_t data_slave_aw_burst_i, + input logic data_slave_aw_lock_i, + input axi_pkg::atop_t data_slave_aw_atop_i, + input axi_pkg::cache_t data_slave_aw_cache_i, + input axi_pkg::qos_t data_slave_aw_qos_i, + input logic [AXI_ID_IN_WIDTH-1:0] data_slave_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] data_slave_aw_user_i, + // used if ASYNC_INTF + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_aw_writetoken_i, + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_aw_readpointer_o, + // used if !ASYNC_INTF + input logic data_slave_aw_valid_i, + output logic data_slave_aw_ready_o, + + // READ ADDRESS CHANNEL + input logic [AXI_ADDR_WIDTH-1:0] data_slave_ar_addr_i, + input axi_pkg::prot_t data_slave_ar_prot_i, + input axi_pkg::region_t data_slave_ar_region_i, + input axi_pkg::len_t data_slave_ar_len_i, + input axi_pkg::size_t data_slave_ar_size_i, + input axi_pkg::burst_t data_slave_ar_burst_i, + input logic data_slave_ar_lock_i, + input axi_pkg::cache_t data_slave_ar_cache_i, + input axi_pkg::qos_t data_slave_ar_qos_i, + input logic [AXI_ID_IN_WIDTH-1:0] data_slave_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] data_slave_ar_user_i, + // used if ASYNC_INTF + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_ar_writetoken_i, + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_ar_readpointer_o, + // used if !ASYNC_INTF + input logic data_slave_ar_valid_i, + output logic data_slave_ar_ready_o, + + // WRITE DATA CHANNEL + input logic [AXI_DATA_S2C_WIDTH-1:0] data_slave_w_data_i, + input logic [AXI_STRB_S2C_WIDTH-1:0] data_slave_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] data_slave_w_user_i, + input logic data_slave_w_last_i, + // used if ASYNC_INTF + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_w_writetoken_i, + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_w_readpointer_o, + // used if !ASYNC_INTF + input logic data_slave_w_valid_i, + output logic data_slave_w_ready_o, + + // READ DATA CHANNEL + output logic [AXI_DATA_S2C_WIDTH-1:0] data_slave_r_data_o, + output axi_pkg::resp_t data_slave_r_resp_o, + output logic data_slave_r_last_o, + output logic [AXI_ID_IN_WIDTH-1:0] data_slave_r_id_o, + output logic [AXI_USER_WIDTH-1:0] data_slave_r_user_o, + // used if ASYNC_INTF + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_r_writetoken_o, + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_r_readpointer_i, + // used if !ASYNC_INTF + output logic data_slave_r_valid_o, + input logic data_slave_r_ready_i, + + // WRITE RESPONSE CHANNEL + output axi_pkg::resp_t data_slave_b_resp_o, + output logic [AXI_ID_IN_WIDTH-1:0] data_slave_b_id_o, + output logic [AXI_USER_WIDTH-1:0] data_slave_b_user_o, + // used if ASYNC_INTF + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_b_writetoken_o, + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_slave_b_readpointer_i, + // used if !ASYNC_INTF + output logic data_slave_b_valid_o, + input logic data_slave_b_ready_i, + + // AXI4 MASTER + //*************************************** + // WRITE ADDRESS CHANNEL + output logic [AXI_ADDR_WIDTH-1:0] data_master_aw_addr_o, + output axi_pkg::prot_t data_master_aw_prot_o, + output axi_pkg::region_t data_master_aw_region_o, + output axi_pkg::len_t data_master_aw_len_o, + output axi_pkg::size_t data_master_aw_size_o, + output axi_pkg::burst_t data_master_aw_burst_o, + output logic data_master_aw_lock_o, + output axi_pkg::atop_t data_master_aw_atop_o, + output axi_pkg::cache_t data_master_aw_cache_o, + output axi_pkg::qos_t data_master_aw_qos_o, + output logic [AXI_ID_OUT_WIDTH-1:0] data_master_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] data_master_aw_user_o, + // used if ASYNC_INTF + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_aw_writetoken_o, + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_aw_readpointer_i, + // used if !ASYNC_INTF + output logic data_master_aw_valid_o, + input logic data_master_aw_ready_i, + + // READ ADDRESS CHANNEL + output logic [AXI_ADDR_WIDTH-1:0] data_master_ar_addr_o, + output axi_pkg::prot_t data_master_ar_prot_o, + output axi_pkg::region_t data_master_ar_region_o, + output axi_pkg::len_t data_master_ar_len_o, + output axi_pkg::size_t data_master_ar_size_o, + output axi_pkg::burst_t data_master_ar_burst_o, + output logic data_master_ar_lock_o, + output axi_pkg::cache_t data_master_ar_cache_o, + output axi_pkg::qos_t data_master_ar_qos_o, + output logic [AXI_ID_OUT_WIDTH-1:0] data_master_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] data_master_ar_user_o, + // used if ASYNC_INTF + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_ar_writetoken_o, + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_ar_readpointer_i, + // used if !ASYNC_INTF + output logic data_master_ar_valid_o, + input logic data_master_ar_ready_i, + + // WRITE DATA CHANNEL + output logic [AXI_DATA_C2S_WIDTH-1:0] data_master_w_data_o, + output logic [AXI_STRB_C2S_WIDTH-1:0] data_master_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] data_master_w_user_o, + output logic data_master_w_last_o, + // used if ASYNC_INTF + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_w_writetoken_o, + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_w_readpointer_i, + // used if !ASYNC_INTF + output logic data_master_w_valid_o, + input logic data_master_w_ready_i, + + // READ DATA CHANNEL + input logic [AXI_DATA_C2S_WIDTH-1:0] data_master_r_data_i, + input axi_pkg::resp_t data_master_r_resp_i, + input logic data_master_r_last_i, + input logic [AXI_ID_OUT_WIDTH-1:0] data_master_r_id_i, + input logic [AXI_USER_WIDTH-1:0] data_master_r_user_i, + // used if ASYNC_INTF + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_r_writetoken_i, + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_r_readpointer_o, + // used if !ASYNC_INTF + input logic data_master_r_valid_i, + output logic data_master_r_ready_o, + + // WRITE RESPONSE CHANNEL + input axi_pkg::resp_t data_master_b_resp_i, + input logic [AXI_ID_OUT_WIDTH-1:0] data_master_b_id_i, + input logic [AXI_USER_WIDTH-1:0] data_master_b_user_i, + // used if ASYNC_INTF + input logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_b_writetoken_i, + output logic [DC_SLICE_BUFFER_WIDTH-1:0] data_master_b_readpointer_o, + // used if !ASYNC_INTF + input logic data_master_b_valid_i, + output logic data_master_b_ready_o, + + // AXI4 DMA MASTER + //*************************************** + // WRITE ADDRESS CHANNEL + output logic [DMA_AXI_AW_WIDTH-1:0] dma_aw_addr_o, + output axi_pkg::prot_t dma_aw_prot_o, + output axi_pkg::region_t dma_aw_region_o, + output axi_pkg::len_t dma_aw_len_o, + output axi_pkg::size_t dma_aw_size_o, + output axi_pkg::burst_t dma_aw_burst_o, + output logic dma_aw_lock_o, + output axi_pkg::atop_t dma_aw_atop_o, + output axi_pkg::cache_t dma_aw_cache_o, + output axi_pkg::qos_t dma_aw_qos_o, + output logic [DMA_AXI_ID_WIDTH-1:0] dma_aw_id_o, + output logic [DMA_AXI_UW_WIDTH-1:0] dma_aw_user_o, + output logic dma_aw_valid_o, + input logic dma_aw_ready_i, + + // READ ADDRESS CHANNEL + output logic [DMA_AXI_AW_WIDTH-1:0] dma_ar_addr_o, + output axi_pkg::prot_t dma_ar_prot_o, + output axi_pkg::region_t dma_ar_region_o, + output axi_pkg::len_t dma_ar_len_o, + output axi_pkg::size_t dma_ar_size_o, + output axi_pkg::burst_t dma_ar_burst_o, + output logic dma_ar_lock_o, + output axi_pkg::cache_t dma_ar_cache_o, + output axi_pkg::qos_t dma_ar_qos_o, + output logic [DMA_AXI_ID_WIDTH-1:0] dma_ar_id_o, + output logic [DMA_AXI_UW_WIDTH-1:0] dma_ar_user_o, + output logic dma_ar_valid_o, + input logic dma_ar_ready_i, + + // WRITE DATA CHANNEL + output logic [DMA_AXI_DW_WIDTH-1:0] dma_w_data_o, + output logic [DMA_AXI_DW_WIDTH/8-1:0] dma_w_strb_o, + output logic [DMA_AXI_UW_WIDTH-1:0] dma_w_user_o, + output logic dma_w_last_o, + output logic dma_w_valid_o, + input logic dma_w_ready_i, + + // READ DATA CHANNEL + input logic [DMA_AXI_DW_WIDTH-1:0] dma_r_data_i, + input axi_pkg::resp_t dma_r_resp_i, + input logic dma_r_last_i, + input logic [DMA_AXI_ID_WIDTH-1:0] dma_r_id_i, + input logic [DMA_AXI_UW_WIDTH-1:0] dma_r_user_i, + input logic dma_r_valid_i, + output logic dma_r_ready_o, + + // WRITE RESPONSE CHANNEL + input axi_pkg::resp_t dma_b_resp_i, + input logic [DMA_AXI_ID_WIDTH-1:0] dma_b_id_i, + input logic [DMA_AXI_UW_WIDTH-1:0] dma_b_user_i, + input logic dma_b_valid_i, + output logic dma_b_ready_o, + + // AXI4 NIC-HOST-Interconnect (NHI) SLAVE + //*************************************** + // WRITE ADDRESS CHANNEL + input logic [DMA_AXI_AW_WIDTH-1:0] nhi_aw_addr_i, + input axi_pkg::prot_t nhi_aw_prot_i, + input axi_pkg::region_t nhi_aw_region_i, + input axi_pkg::len_t nhi_aw_len_i, + input axi_pkg::size_t nhi_aw_size_i, + input axi_pkg::burst_t nhi_aw_burst_i, + input logic nhi_aw_lock_i, + input axi_pkg::atop_t nhi_aw_atop_i, + input axi_pkg::cache_t nhi_aw_cache_i, + input axi_pkg::qos_t nhi_aw_qos_i, + input logic [DMA_AXI_ID_WIDTH-1:0] nhi_aw_id_i, + input logic [DMA_AXI_UW_WIDTH-1:0] nhi_aw_user_i, + input logic nhi_aw_valid_i, + output logic nhi_aw_ready_o, + + // READ ADDRESS CHANNEL + input logic [DMA_AXI_AW_WIDTH-1:0] nhi_ar_addr_i, + input axi_pkg::prot_t nhi_ar_prot_i, + input axi_pkg::region_t nhi_ar_region_i, + input axi_pkg::len_t nhi_ar_len_i, + input axi_pkg::size_t nhi_ar_size_i, + input axi_pkg::burst_t nhi_ar_burst_i, + input logic nhi_ar_lock_i, + input axi_pkg::cache_t nhi_ar_cache_i, + input axi_pkg::qos_t nhi_ar_qos_i, + input logic [DMA_AXI_ID_WIDTH-1:0] nhi_ar_id_i, + input logic [DMA_AXI_UW_WIDTH-1:0] nhi_ar_user_i, + input logic nhi_ar_valid_i, + output logic nhi_ar_ready_o, + + // WRITE DATA CHANNEL + input logic [DMA_AXI_DW_WIDTH-1:0] nhi_w_data_i, + input logic [DMA_AXI_DW_WIDTH/8-1:0] nhi_w_strb_i, + input logic [DMA_AXI_UW_WIDTH-1:0] nhi_w_user_i, + input logic nhi_w_last_i, + input logic nhi_w_valid_i, + output logic nhi_w_ready_o, + + // READ DATA CHANNEL + output logic [DMA_AXI_DW_WIDTH-1:0] nhi_r_data_o, + output axi_pkg::resp_t nhi_r_resp_o, + output logic nhi_r_last_o, + output logic [DMA_AXI_ID_WIDTH-1:0] nhi_r_id_o, + output logic [DMA_AXI_UW_WIDTH-1:0] nhi_r_user_o, + output logic nhi_r_valid_o, + input logic nhi_r_ready_i, + + // WRITE RESPONSE CHANNEL + output axi_pkg::resp_t nhi_b_resp_o, + output logic [DMA_AXI_ID_WIDTH-1:0] nhi_b_id_o, + output logic [DMA_AXI_UW_WIDTH-1:0] nhi_b_user_o, + output logic nhi_b_valid_o, + input logic nhi_b_ready_i, + + // Instruction Cache Master Port + output pulp_cluster_cfg_pkg::addr_t icache_aw_addr_o, + output axi_pkg::prot_t icache_aw_prot_o, + output axi_pkg::region_t icache_aw_region_o, + output axi_pkg::len_t icache_aw_len_o, + output axi_pkg::size_t icache_aw_size_o, + output axi_pkg::burst_t icache_aw_burst_o, + output logic icache_aw_lock_o, + output axi_pkg::atop_t icache_aw_atop_o, + output axi_pkg::cache_t icache_aw_cache_o, + output axi_pkg::qos_t icache_aw_qos_o, + output pulp_cluster_cfg_pkg::id_icache_t icache_aw_id_o, + output pulp_cluster_cfg_pkg::user_t icache_aw_user_o, + output logic icache_aw_valid_o, + input logic icache_aw_ready_i, + + output pulp_cluster_cfg_pkg::addr_t icache_ar_addr_o, + output axi_pkg::prot_t icache_ar_prot_o, + output axi_pkg::region_t icache_ar_region_o, + output axi_pkg::len_t icache_ar_len_o, + output axi_pkg::size_t icache_ar_size_o, + output axi_pkg::burst_t icache_ar_burst_o, + output logic icache_ar_lock_o, + output axi_pkg::cache_t icache_ar_cache_o, + output axi_pkg::qos_t icache_ar_qos_o, + output pulp_cluster_cfg_pkg::id_icache_t icache_ar_id_o, + output pulp_cluster_cfg_pkg::user_t icache_ar_user_o, + output logic icache_ar_valid_o, + input logic icache_ar_ready_i, + + output pulp_cluster_cfg_pkg::data_icache_t icache_w_data_o, + output pulp_cluster_cfg_pkg::strb_icache_t icache_w_strb_o, + output pulp_cluster_cfg_pkg::user_t icache_w_user_o, + output logic icache_w_last_o, + output logic icache_w_valid_o, + input logic icache_w_ready_i, + + input pulp_cluster_cfg_pkg::data_icache_t icache_r_data_i, + input axi_pkg::resp_t icache_r_resp_i, + input logic icache_r_last_i, + input pulp_cluster_cfg_pkg::id_icache_t icache_r_id_i, + input pulp_cluster_cfg_pkg::user_t icache_r_user_i, + input logic icache_r_valid_i, + output logic icache_r_ready_o, + + input axi_pkg::resp_t icache_b_resp_i, + input pulp_cluster_cfg_pkg::id_icache_t icache_b_id_i, + input pulp_cluster_cfg_pkg::user_t icache_b_user_i, + input logic icache_b_valid_i, + output logic icache_b_ready_o, + + //task from scheduler + input logic task_valid_i, + output logic task_ready_o, + input pspin_cfg_pkg::handler_task_t task_descr_i, + + //feedback to scheduler + output logic feedback_valid_o, + input logic feedback_ready_i, + output pspin_cfg_pkg::feedback_descr_t feedback_o, + + //signal if the cluster is ready to accept tasks + output logic cluster_active_o, + + //commands out + input logic cmd_ready_i, + output logic cmd_valid_o, + output pspin_cfg_pkg::pspin_cmd_t cmd_o, + + //command response + input logic cmd_resp_valid_i, + input pspin_cfg_pkg::pspin_cmd_resp_t cmd_resp_i +); + + logic [NB_CORES-1:0] fetch_enable_reg_int; + logic [NB_CORES-1:0] fetch_en_int; + logic s_rst_n; + logic s_init_n; + logic [NB_CORES-1:0][31:0] boot_addr; + logic [NB_CORES-1:0] dbg_core_halt; + logic [NB_CORES-1:0] dbg_core_resume; + logic [NB_CORES-1:0] dbg_core_halted; + logic hwpe_sel; + logic hwpe_en; + + logic [NB_CORES-1:0][AXI_USER_WIDTH-1:0] tryx_axuser; + logic [NB_CORES-1:0] tryx_xresp_decerr; + logic [NB_CORES-1:0] tryx_xresp_slverr; + logic [NB_CORES-1:0] tryx_xresp_valid; + + logic s_cluster_periphs_busy; + logic s_axi_to_mem_busy; + logic s_per2axi_busy; + logic s_axi2per_busy; + logic s_dmac_busy; + logic s_cluster_cg_en; + logic [NB_CORES-1:0] s_dma_event; + logic [NB_CORES-1:0] s_dma_irq; + logic [NB_CORES-1:0][3:0] s_hwacc_events; + logic [NB_CORES-1:0][1:0] s_xne_evt; + logic s_xne_busy; + + logic [NB_CORES-1:0] clk_core_en; + logic clk_cluster; + + // CLK reset, and other control signals + + logic s_cluster_int_busy; + logic s_fregfile_disable; + + logic [NB_CORES-1:0] core_busy; + + logic s_incoming_req; + logic s_isolate_cluster; + logic s_events_async; + + logic s_events_valid; + logic s_events_ready; + logic [EVNT_WIDTH-1:0] s_events_data; + + // Signals Between CORE_ISLAND and INSTRUCTION CACHES + logic [NB_CORES-1:0] instr_req; + logic [NB_CORES-1:0][31:0] instr_addr; + logic [NB_CORES-1:0] instr_gnt; + logic [NB_CORES-1:0] instr_r_valid; + logic [NB_CORES-1:0][INSTR_RDATA_WIDTH-1:0] instr_r_rdata; + + logic [1:0] s_TCDM_arb_policy; + logic tcdm_sleep; + + logic s_dma_pe_event; + logic s_dma_pe_irq; + logic s_pf_event; + + logic[NB_CORES-1:0][4:0] irq_id; + logic[NB_CORES-1:0][4:0] irq_ack_id; + logic[NB_CORES-1:0] irq_req; + logic[NB_CORES-1:0] irq_ack; + + + /* asynchronous AXI interfaces at CLUSTER/SOC interface, driven iff `ASYNC_INTF` */ + AXI_BUS_ASYNC #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_WIDTH ( DC_SLICE_BUFFER_WIDTH ) + ) s_data_slave_async(); + + AXI_BUS_ASYNC #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .BUFFER_WIDTH ( DC_SLICE_BUFFER_WIDTH ) + ) s_data_master_async(); + + /* synchronously cut (no combinatorial paths) AXI interfaces, driven iff `!ASYNC_INTF` */ + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_data_slave_cut(); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_data_master_cut(); + + /* synchronous AXI interfaces at CLUSTER/SOC interface */ + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_data_slave(); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_data_master(); + + /* synchronous AXI interfaces internal to the cluster */ + // core per2axi -> ext + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_core_ext_bus(); + + // DMA -> ext + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_dma_ext_bus(); + + // WIDE DMA -> SoC + AXI_BUS #( + .AXI_ADDR_WIDTH ( DMA_AXI_AW_WIDTH ), + .AXI_DATA_WIDTH ( DMA_AXI_DW_WIDTH ), + .AXI_ID_WIDTH ( DMA_AXI_ID_WIDTH ), + .AXI_USER_WIDTH ( DMA_AXI_UW_WIDTH ) + ) s_wide_dma_soc(); + + // WIDE NHI -> TCDM (supprbanks) + AXI_BUS #( + .AXI_ADDR_WIDTH ( DMA_AXI_AW_WIDTH ), + .AXI_DATA_WIDTH ( DMA_AXI_DW_WIDTH ), + .AXI_ID_WIDTH ( DMA_AXI_ID_WIDTH ), + .AXI_USER_WIDTH ( DMA_AXI_UW_WIDTH ) + ) s_wide_nhi_superbanks(); + + // ext -> axi_to_mem + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_ext_tcdm_bus(); + + // cluster bus -> axi2per + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) s_ext_mperiph_bus(); + + /* logarithmic and peripheral interconnect interfaces */ + // wide dma -> superbanks a + WIDE_DMA_TCDM_BUS #( + .ADDR_WIDTH ( DMA_AXI_AW_WIDTH ), + .DATA_WIDTH ( DMA_AXI_DW_WIDTH ) + ) s_wide_dma_a_superbanks(); + + // NHI interconnect -> superbanks b + WIDE_DMA_TCDM_BUS #( + .ADDR_WIDTH ( DMA_AXI_AW_WIDTH ), + .DATA_WIDTH ( DMA_AXI_DW_WIDTH ) + ) s_wide_dma_b_superbanks(); + + + // ext -> log interconnect + XBAR_TCDM_BUS s_ext_xbar_bus[NB_EXT2MEM-1:0](); + + // periph interconnect -> slave peripherals + XBAR_PERIPH_BUS s_xbar_speriph_bus[NB_SPERIPHS-1:0](); + logic [NB_SPERIPHS-1:0][5:0] s_xbar_speriph_atop; + + // periph interconnect -> XNE + XBAR_PERIPH_BUS s_xne_cfg_bus(); + + // DMA -> log interconnect + XBAR_TCDM_BUS s_dma_xbar_bus[NB_DMAS-1:0](); + + // ext -> xbar periphs FIXME + XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); + + // periph demux + XBAR_TCDM_BUS s_mperiph_bus(); + XBAR_TCDM_BUS s_mperiph_demux_bus[1:0](); + + // cores & accelerators -> log interconnect + XBAR_TCDM_BUS s_core_xbar_bus[NB_CORES+NB_HWACC_PORTS-1:0](); + + // cores -> periph interconnect + XBAR_PERIPH_BUS s_core_periph_bus[NB_CORES-1:0](); + XBAR_PERIPH_BUS s_inter_core_fifo[NB_CORES-1:0](); + XBAR_PERIPH_BUS s_hpu_driver_bus[NB_CORES-1:0](); + logic [NB_CORES-1:0][5:0] s_core_periph_bus_atop, s_core_xbar_bus_atop; + + // cores -> tryx control + XBAR_PERIPH_BUS s_core_periph_tryx[NB_CORES-1:0](); + + // periph interconnect -> DMA + XBAR_PERIPH_BUS s_periph_dma_bus(); + + // debug + XBAR_TCDM_BUS s_debug_bus[NB_CORES-1:0](); + + /* other interfaces */ + // cores -> DMA ctrl + XBAR_TCDM_BUS s_core_dmactrl_bus[NB_CORES-1:0](); + + // cores -> event unit ctrl + XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); + + // I$ ctrl unit <-> I$, L0, I$ interconnect + MP_PF_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus(); + + // log interconnect -> TCDM memory banks (SRAM) + TCDM_BANK_MEM_BUS s_tcdm_bus_sram[NB_TCDM_BANKS-1:0](); + + // cluster_scheduler -> dma_wrap + logic ext_dma_req_valid; + logic ext_dma_req_ready; + pspin_cfg_pkg::transf_descr_32_t ext_dma_req; + + // dma_wrap -> cluster_scheduler + logic ext_dma_rsp_valid; + + // cluster_schedulers -> hpu_drivers + logic [NB_CORES-1:0] hpu_task_valid; + logic [NB_CORES-1:0] hpu_task_ready; + pspin_cfg_pkg::hpu_handler_task_t hpu_task; + + // hpu_drivers -> cluster_schedulers + logic [NB_CORES-1:0] hpu_feedback_valid; + logic [NB_CORES-1:0] hpu_feedback_ready; + pspin_cfg_pkg::task_feedback_descr_t [NB_CORES-1:0] hpu_feedback; + + logic [NB_CORES-1:0] hpu_active; + + logic [NB_CORES-1:0] core_cmd_ready; + logic [NB_CORES-1:0] core_cmd_valid; + pspin_cfg_pkg::pspin_cmd_t [NB_CORES-1:0] core_cmd; + + // cores -> APU + cpu_marx_if #( + .WOP_CPU ( WOP_CPU ), + .WAPUTYPE ( WAPUTYPE ), + .NUSFLAGS_CPU ( NUSFLAGS_CPU ), + .NDSFLAGS_CPU ( NDSFLAGS_CPU ), + .NARGS_CPU ( NARGS_CPU ) + ) apu_cluster_bus [NB_CORES-1:0] (); + + /* reset generator */ + rstgen rstgen_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i( test_mode_i ), + .rst_no ( s_rst_n ), + .init_no ( s_init_n ) + ); + + /* fetch & busy genertion */ + assign s_cluster_int_busy = s_cluster_periphs_busy | s_per2axi_busy | s_axi2per_busy | s_axi_to_mem_busy | s_dmac_busy | s_xne_busy; + assign busy_o = s_cluster_int_busy | (|core_busy); + assign fetch_en_int = fetch_enable_reg_int; + + /* cluster bus and attached peripherals */ + cluster_bus_wrap #( + .NB_CORES ( NB_CORES ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ) + ) cluster_bus_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .cluster_id_i ( cluster_id_i ), + .data_slave ( s_core_ext_bus ), + .dma_slave ( s_dma_ext_bus ), + .ext_slave ( s_data_slave ), + .tcdm_master ( s_ext_tcdm_bus ), + .periph_master ( s_ext_mperiph_bus ), + .ext_master ( s_data_master ) + ); + + logic [NB_EXT2MEM-1:0] s_ext_xbar_bus_req, s_ext_xbar_bus_gnt, + s_ext_xbar_bus_wen, + s_ext_xbar_bus_rvalid; + logic [NB_EXT2MEM-1:0][31:0] s_ext_xbar_bus_addr, + s_ext_xbar_bus_rdata, + s_ext_xbar_bus_wdata; + logic [NB_EXT2MEM-1:0][ 3:0] s_ext_xbar_bus_be; + logic [NB_EXT2MEM-1:0][ 5:0] s_ext_xbar_bus_atop; + + // Fall-through register on AW due to protocol violation by upstream (dependency on aw_ready for + // w_valid). + typedef logic [31:0] addr_t; + typedef logic [AXI_DATA_C2S_WIDTH-1:0] data_t; + typedef logic [AXI_ID_OUT_WIDTH-1:0] id_oup_t; + typedef logic [AXI_DATA_C2S_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_oup_t, user_t); + `AXI_TYPEDEF_W_CHAN_T (w_chan_t, data_t, strb_t, user_t); + `AXI_TYPEDEF_B_CHAN_T (b_chan_t, id_oup_t, user_t); + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_oup_t, user_t); + `AXI_TYPEDEF_R_CHAN_T (r_chan_t, data_t, id_oup_t, user_t); + `AXI_TYPEDEF_REQ_T (axi_req_t, aw_chan_t, w_chan_t, ar_chan_t); + `AXI_TYPEDEF_RESP_T (axi_resp_t, b_chan_t, r_chan_t); + axi_req_t ext_tcdm_req, ext_tcdm_req_buf; + axi_resp_t ext_tcdm_resp, ext_tcdm_resp_buf; + `AXI_ASSIGN_TO_REQ(ext_tcdm_req, s_ext_tcdm_bus); + `AXI_ASSIGN_FROM_RESP(s_ext_tcdm_bus, ext_tcdm_resp); + always_comb begin + ext_tcdm_req_buf.w = ext_tcdm_req.w; + ext_tcdm_req_buf.w_valid = ext_tcdm_req.w_valid; + ext_tcdm_resp.w_ready = ext_tcdm_resp_buf.w_ready; + ext_tcdm_req_buf.ar = ext_tcdm_req.ar; + ext_tcdm_req_buf.ar_valid = ext_tcdm_req.ar_valid; + ext_tcdm_resp.ar_ready = ext_tcdm_resp_buf.ar_ready; + ext_tcdm_resp.b = ext_tcdm_resp_buf.b; + ext_tcdm_resp.b_valid = ext_tcdm_resp_buf.b_valid; + ext_tcdm_req_buf.b_ready = ext_tcdm_req.b_ready; + ext_tcdm_resp.r = ext_tcdm_resp_buf.r; + ext_tcdm_resp.r_valid = ext_tcdm_resp_buf.r_valid; + ext_tcdm_req_buf.r_ready = ext_tcdm_req.r_ready; + end + fall_through_register #( + .T (aw_chan_t) + ) i_axi_to_mem_aw_ft_reg ( + .clk_i (clk_cluster), + .rst_ni, + .clr_i (1'b0), + .testmode_i (1'b0), + .valid_i (ext_tcdm_req.aw_valid), + .ready_o (ext_tcdm_resp.aw_ready), + .data_i (ext_tcdm_req.aw), + .valid_o (ext_tcdm_req_buf.aw_valid), + .ready_i (ext_tcdm_resp_buf.aw_ready), + .data_o (ext_tcdm_req_buf.aw) + ); + + axi_to_mem #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .AddrWidth ( 32 ), + .DataWidth ( AXI_DATA_C2S_WIDTH ), + .IdWidth ( AXI_ID_OUT_WIDTH ), + .NumBanks ( NB_EXT2MEM ) + ) i_axi_to_mem ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .busy_o ( s_axi_to_mem_busy ), + .axi_req_i ( ext_tcdm_req_buf ), + .axi_resp_o ( ext_tcdm_resp_buf ), + .mem_req_o ( s_ext_xbar_bus_req ), + .mem_gnt_i ( s_ext_xbar_bus_gnt ), + .mem_addr_o ( s_ext_xbar_bus_addr ), + .mem_wdata_o ( s_ext_xbar_bus_wdata ), + .mem_strb_o ( s_ext_xbar_bus_be ), + .mem_atop_o ( s_ext_xbar_bus_atop ), + .mem_we_o ( s_ext_xbar_bus_wen ), + .mem_rvalid_i ( s_ext_xbar_bus_rvalid ), + .mem_rdata_i ( s_ext_xbar_bus_rdata ) + ); + for (genvar i = 0; i < NB_EXT2MEM; i++) begin : gen_ext_xbar_bus + assign s_ext_xbar_bus[i].req = s_ext_xbar_bus_req[i]; + assign s_ext_xbar_bus_gnt[i] = s_ext_xbar_bus[i].gnt; + assign s_ext_xbar_bus[i].add = s_ext_xbar_bus_addr[i]; + assign s_ext_xbar_bus[i].wdata = s_ext_xbar_bus_wdata[i]; + assign s_ext_xbar_bus[i].be = s_ext_xbar_bus_be[i]; + assign s_ext_xbar_bus[i].wen = ~s_ext_xbar_bus_wen[i]; // active low + assign s_ext_xbar_bus_rvalid[i] = s_ext_xbar_bus[i].r_valid; + assign s_ext_xbar_bus_rdata[i] = s_ext_xbar_bus[i].r_rdata; + end + + axi2per_wrap #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) axi2per_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .cluster_id_i ( cluster_id_i ), + .axi_slave ( s_ext_mperiph_bus ), + .periph_master ( s_mperiph_bus ), + .busy_o ( s_axi2per_busy ) + ); + + per_demux_wrap #( + .NB_MASTERS ( 2 ), + .ADDR_OFFSET ( 20 ) + ) per_demux_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .slave ( s_mperiph_bus ), + .masters ( s_mperiph_demux_bus ) + ); + + assign s_mperiph_xbar_bus[NB_MPERIPHS-1].req = s_mperiph_demux_bus[0].req; + assign s_mperiph_xbar_bus[NB_MPERIPHS-1].add = s_mperiph_demux_bus[0].add; + assign s_mperiph_xbar_bus[NB_MPERIPHS-1].wen = s_mperiph_demux_bus[0].wen; + assign s_mperiph_xbar_bus[NB_MPERIPHS-1].wdata = s_mperiph_demux_bus[0].wdata; + assign s_mperiph_xbar_bus[NB_MPERIPHS-1].be = s_mperiph_demux_bus[0].be; + + assign s_mperiph_demux_bus[0].gnt = s_mperiph_xbar_bus[NB_MPERIPHS-1].gnt; + assign s_mperiph_demux_bus[0].r_valid = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_valid; + assign s_mperiph_demux_bus[0].r_opc = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_opc; + assign s_mperiph_demux_bus[0].r_rdata = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_rdata; + + per_demux_wrap #( + .NB_MASTERS ( NB_CORES ), + .ADDR_OFFSET ( 15 ) + ) debug_interconect_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .slave ( s_mperiph_demux_bus[1] ), + .masters ( s_debug_bus ) + ); + + per2axi_wrap #( + .NB_CORES ( NB_CORES ), + .PER_ADDR_WIDTH ( 32 ), + .PER_ID_WIDTH ( NB_CORES+NB_MPERIPHS ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ) + ) per2axi_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .test_en_i ( test_mode_i ), + .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), + .periph_slave_atop_i ( s_xbar_speriph_atop[SPER_EXT_ID] ), + .axi_axuser_i ( tryx_axuser ), + .axi_xresp_decerr_o ( tryx_xresp_decerr ), + .axi_xresp_slverr_o ( tryx_xresp_slverr ), + .axi_xresp_valid_o ( tryx_xresp_valid ), + .axi_master ( s_core_ext_bus ), + .busy_o ( s_per2axi_busy ) + ); + + tryx_ctrl #( + .NB_CORES ( NB_CORES ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) tryx_ctrl_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .axi_axuser_o ( tryx_axuser ), + .axi_xresp_decerr_i ( tryx_xresp_decerr ), + .axi_xresp_slverr_i ( tryx_xresp_slverr ), + .axi_xresp_valid_i ( tryx_xresp_valid ), + .periph_data_slave ( s_core_periph_bus ), + .periph_data_master ( s_core_periph_tryx ) + ); + + /* cluster (log + periph) interconnect and attached peripherals */ + cluster_interconnect_wrap #( + .NB_CORES ( NB_CORES ), + .NB_HWACC_PORTS ( NB_HWACC_PORTS ), + .NB_DMAS ( NB_DMAS ), + .NB_EXT ( NB_EXT2MEM ), + .NB_MPERIPHS ( NB_MPERIPHS ), + .NB_TCDM_BANKS ( NB_TCDM_BANKS ), + .NB_SPERIPHS ( NB_SPERIPHS ), + .DATA_WIDTH ( DATA_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .TEST_SET_BIT ( TEST_SET_BIT ), + .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH ), + .LOG_CLUSTER ( LOG_CLUSTER ), + .PE_ROUTING_LSB ( PE_ROUTING_LSB ), + .PE_ROUTING_MSB ( PE_ROUTING_MSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ) + ) cluster_interconnect_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .core_tcdm_slave ( s_core_xbar_bus ), + .core_tcdm_slave_atop ( s_core_xbar_bus_atop ), + .core_periph_slave ( s_core_periph_tryx ), + .core_periph_slave_atop ( s_core_periph_bus_atop ), + .ext_slave ( s_ext_xbar_bus ), + .ext_slave_atop ( s_ext_xbar_bus_atop ), + .dma_slave ( s_dma_xbar_bus ), + .mperiph_slave ( s_mperiph_xbar_bus[NB_MPERIPHS-1:0] ), + .tcdm_sram_master ( s_tcdm_bus_sram ), + .speriph_master ( s_xbar_speriph_bus ), + .speriph_master_atop ( s_xbar_speriph_atop ), + .TCDM_arb_policy_i ( s_TCDM_arb_policy ), + .s_wide_dma_a_superbanks( s_wide_dma_a_superbanks ), + .s_wide_dma_b_superbanks( s_wide_dma_b_superbanks ) + ); + + logic [NB_CORES-1:0] s_no_req_pending; + + dmac_wrap #( + .NB_CORES ( NB_CORES ), + .NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), + .MCHAN_BURST_LENGTH ( MCHAN_BURST_LENGTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .PE_ID_WIDTH ( NB_CORES + 1 ), + .TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .dma_transf_descr_t ( pspin_cfg_pkg::transf_descr_32_t ), + .DMA_AXI_AW_WIDTH ( DMA_AXI_AW_WIDTH ), + .DMA_AXI_DW_WIDTH ( DMA_AXI_DW_WIDTH ), + .DMA_AXI_ID_WIDTH ( DMA_AXI_ID_WIDTH ), + .DMA_AXI_UW_WIDTH ( DMA_AXI_UW_WIDTH ), + .TF_REQ_FIFO_DEPTH ( pspin_cfg_pkg::BUFFERED_HERS_PER_CLUSTER ) + ) dmac_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .cluster_id_i ( cluster_id_i ), + .test_mode_i ( test_mode_i ), + .ctrl_slave ( s_core_dmactrl_bus ), + .pe_ctrl_slave ( s_periph_dma_bus ), + .tcdm_master ( s_dma_xbar_bus ), + .ext_master ( s_dma_ext_bus ), + .s_wide_dma_soc ( s_wide_dma_soc ), + .s_wide_dma_superbanks ( s_wide_dma_a_superbanks ), + .term_event_o ( s_dma_event ), + .term_irq_o ( s_dma_irq ), + .term_event_pe_o ( s_dma_pe_event ), + .term_irq_pe_o ( s_dma_pe_irq ), + .busy_o ( s_dmac_busy ), + .ext_dma_req_valid_i ( ext_dma_req_valid ), + .ext_dma_req_ready_o ( ext_dma_req_ready ), + .ext_dma_req_i ( ext_dma_req ), + .ext_dma_rsp_valid_o ( ext_dma_rsp_valid ), + .no_req_pending_o ( s_no_req_pending ) + ); + + nhi_port_wrap #( + .DMA_AXI_AW_WIDTH ( DMA_AXI_AW_WIDTH ), + .DMA_AXI_DW_WIDTH ( DMA_AXI_DW_WIDTH ), + .DMA_AXI_ID_WIDTH ( DMA_AXI_ID_WIDTH ), + .DMA_AXI_UW_WIDTH ( DMA_AXI_UW_WIDTH ) + ) nhi_port_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .s_wide_dma_superbanks ( s_wide_dma_b_superbanks ), + .s_wide_dma_nhi ( s_wide_nhi_superbanks ) + ); + + cluster_peripherals #( + .NB_CORES ( NB_CORES ), + .NB_MPERIPHS ( NB_MPERIPHS ), + .NB_CACHE_BANKS ( NB_CACHE_BANKS ), + .NB_SPERIPHS ( NB_SPERIPHS ), + .NB_TCDM_BANKS ( NB_TCDM_BANKS ), + .NB_HWPE_PORTS ( 1 ), + .ROM_BOOT_ADDR ( ROM_BOOT_ADDR ), + .BOOT_ADDR ( BOOT_ADDR ), + .EVNT_WIDTH ( EVNT_WIDTH ) + ) cluster_peripherals_i ( + .clk_i ( clk_cluster ), + .rst_ni ( rst_ni ), + .ref_clk_i ( ref_clk_i ), + .test_mode_i ( test_mode_i ), + .busy_o ( s_cluster_periphs_busy ), + .dma_events_i ( s_dma_event ), + .dma_irq_i ( s_dma_irq ), + .en_sa_boot_i ( en_sa_boot_i ), + .fetch_en_i ( fetch_en_i ), + .boot_addr_o ( boot_addr ), + .core_busy_i ( core_busy ), + .core_clk_en_o ( clk_core_en ), + .fregfile_disable_o ( s_fregfile_disable ), + .speriph_slave ( s_xbar_speriph_bus[NB_SPERIPHS-2:0]), + .core_eu_direct_link ( s_core_euctrl_bus ), + .dma_cfg_master ( s_periph_dma_bus ), + .dma_pe_irq_i ( s_dma_pe_irq ), + .pf_event_o ( s_pf_event ), + .soc_periph_evt_ready_o ( s_events_ready ), + .soc_periph_evt_valid_i ( s_events_valid ), + .soc_periph_evt_data_i ( s_events_data ), + .dbg_core_halt_o ( dbg_core_halt ), + .dbg_core_halted_i ( dbg_core_halted ), + .dbg_core_resume_o ( dbg_core_resume ), + .eoc_o ( eoc_o ), + .cluster_cg_en_o ( s_cluster_cg_en ), + .fetch_enable_reg_o ( fetch_enable_reg_int ), + .irq_id_o ( irq_id ), + .irq_ack_id_i ( irq_ack_id ), + .irq_req_o ( irq_req ), + .irq_ack_i ( irq_ack ), + .TCDM_arb_policy_o ( s_TCDM_arb_policy ), + .hwce_cfg_master ( s_xne_cfg_bus ), + .hwacc_events_i ( s_hwacc_events ), + .hwpe_sel_o ( hwpe_sel ), + .hwpe_en_o ( hwpe_en ), + .IC_ctrl_unit_bus ( IC_ctrl_unit_bus ) + ); + + + /* Cluster scheduler */ + cluster_scheduler #( + .NUM_HERS_PER_CLUSTER (pspin_cfg_pkg::NUM_HERS_PER_CLUSTER), + .L1_PKT_BUFF_SIZE (pspin_cfg_pkg::L1_PKT_BUFF_SIZE), + .L1_CLUSTER_BASE (pspin_cfg_pkg::L1_CLUSTER_BASE), + .L1_CLUSTER_MEM_SIZE (pspin_cfg_pkg::L1_CLUSTER_MEM_SIZE), + .L1_RUNTIME_OFFSET (pspin_cfg_pkg::L1_RUNTIME_OFFSET) + ) i_cluster_scheduler ( + .rst_ni (rst_ni), + .clk_i (clk_cluster), + + .cluster_id_i (cluster_id_i), + + // from scheduler + .task_valid_i (task_valid_i), + .task_ready_o (task_ready_o), + .task_descr_i (task_descr_i), + + // to scheduler + .feedback_valid_o (feedback_valid_o), + .feedback_ready_i (feedback_ready_i), + .feedback_o (feedback_o), + + // to DMA + .dma_xfer_valid_o (ext_dma_req_valid), + .dma_xfer_ready_i (ext_dma_req_ready), + .dma_xfer_o (ext_dma_req), + + // from DMA + .dma_resp_i (ext_dma_rsp_valid), + + // to HPU drivers + .hpu_task_valid_o (hpu_task_valid), + .hpu_task_ready_i (hpu_task_ready), + .hpu_task_o (hpu_task), + + // from HPU drivers + .hpu_feedback_valid_i (hpu_feedback_valid), + .hpu_feedback_ready_o (hpu_feedback_ready), + .hpu_feedback_i (hpu_feedback), + + .hpu_active_i (hpu_active), + .cluster_active_o (cluster_active_o) + ); + + + /* cluster-local command unit */ + cluster_cmd #( + .NUM_CORES (NB_CORES) + ) i_cluster_cmd ( + .clk_i (clk_cluster), + .rst_ni (rst_ni), + + .cmd_ready_o (core_cmd_ready), + .cmd_valid_i (core_cmd_valid), + .cmd_i (core_cmd), + + .cmd_ready_i (cmd_ready_i), + .cmd_valid_o (cmd_valid_o), + .cmd_o (cmd_o) + ); + + /* cluster cores + core-coupled accelerators / shared execution units */ + localparam int N_PMP_ENTRIES = 16; + generate + for (genvar i=0; i 0) else $fatal(1, "NB_CORES not set!"); + end + // pragma translate_on + `endif + +endmodule diff --git a/hw/deps/pulp_cluster/rtl/virtual_stdout_demux.sv b/hw/deps/pulp_cluster/rtl/virtual_stdout_demux.sv new file mode 100644 index 0000000..ba7329b --- /dev/null +++ b/hw/deps/pulp_cluster/rtl/virtual_stdout_demux.sv @@ -0,0 +1,106 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module virtual_stdout_demux #( + parameter int unsigned CoreId = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic [5:0] cluster_id_i, + XBAR_PERIPH_BUS.Slave periph_slv, + input logic [5:0] periph_slv_atop_i, + XBAR_PERIPH_BUS.Master periph_mst, + output logic [5:0] periph_mst_atop_o +); + + `ifndef TARGET_SYNTHESIS + `define VIRTUAL_STDOUT + `endif + + `ifndef VIRTUAL_STDOUT + // When synthesizing, feed signals through to real stdout device. + assign periph_mst.req = periph_slv.req; + assign periph_mst.add = periph_slv.add; + assign periph_mst.wen = periph_slv.wen; + assign periph_mst_atop_o = periph_slv_atop_i; + assign periph_mst.wdata = periph_slv.wdata; + assign periph_mst.be = periph_slv.be; + assign periph_slv.gnt = periph_mst.gnt; + assign periph_slv.r_valid = periph_mst.r_valid; + assign periph_slv.r_rdata = periph_mst.r_rdata; + assign periph_slv.r_opc = periph_mst.r_opc; + `else + // When not synthesizing, insert virtual stdout device that is close to the core for fast and + // interference-free printing. + + byte buffer [$]; + + function void flush(); + automatic string s; + for (int i_char = 0; i_char < buffer.size(); i_char++) begin + s = $sformatf("%s%c", s, buffer[i_char]); + end + if (s.len() > 0) begin + $display("[%01d,%01d] %s", cluster_id_i, CoreId, s); + end + buffer.delete(); + endfunction + + function void append(byte ch); + if (ch == 8'hA) begin + flush(); + end else begin + buffer.push_back(ch); + end + endfunction + + logic resp_inj_d, resp_inj_q; + always_comb begin + // Feed through by default. + periph_mst.req = periph_slv.req; + periph_mst.add = periph_slv.add; + periph_mst.wen = periph_slv.wen; + periph_mst_atop_o = periph_slv_atop_i; + periph_mst.wdata = periph_slv.wdata; + periph_mst.be = periph_slv.be; + periph_slv.gnt = periph_mst.gnt; + periph_slv.r_valid = periph_mst.r_valid; + periph_slv.r_rdata = periph_mst.r_rdata; + periph_slv.r_opc = periph_mst.r_opc; + resp_inj_d = resp_inj_q; + // Inject responses by stdout device. + if (resp_inj_q) begin + periph_slv.r_valid = 1'b1; + periph_slv.r_rdata = '0; + periph_slv.r_opc = 1'b0; + resp_inj_d = 1'b0; + end + // Intercept accesses to stdout device. + if (periph_slv.req && periph_slv.add[31:12] == 20'h1A104) begin + periph_mst.req = 1'b0; + periph_slv.gnt = 1'b1; + resp_inj_d = 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + flush(); + resp_inj_q <= 1'b0; + end else begin + resp_inj_q <= resp_inj_d; + if (resp_inj_d) begin + append(periph_slv.wdata & 32'hFF); + end + end + end + `endif + +endmodule diff --git a/hw/deps/riscv/include/apu_core_package.sv b/hw/deps/riscv/include/apu_core_package.sv new file mode 100644 index 0000000..ddba25d --- /dev/null +++ b/hw/deps/riscv/include/apu_core_package.sv @@ -0,0 +1,77 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch // +// // +// Design Name: APU-core package // +// Project Name: RISC-V // +// Language: SystemVerilog // +// // +// Description: core package of RISC-V core for shared APU // +// // +//////////////////////////////////////////////////////////////////////////////// + +package apu_core_package; + + ///////////////////////////////////////////////////////////////////////////// + // IMPORTANT!! // + ///////////////////////////////////////////////////////////////////////////// + // THESE PARAMETERS HAVE TO MATCH THE ones in ulpcluster/apu_package.sv // + ///////////////////////////////////////////////////////////////////////////// + + // by default set to 0 + parameter SHARED_INT_MULT = 0; + + ///////////////////////////////////////////////////////////////////////////// + // until here // + ///////////////////////////////////////////////////////////////////////////// + + // APU interface + parameter WAPUTYPE = 0; + parameter APU_NARGS_CPU = 3; + parameter APU_WOP_CPU = 6; + parameter APU_NDSFLAGS_CPU = 15; + parameter APU_NUSFLAGS_CPU = 5; + + // FP-general + parameter APU_FLAGS_FP = 2; + parameter APU_FLAGS_FPNEW = 3; + + // DSP-Mult + parameter PIPE_REG_DSP_MULT = 1; + parameter APU_FLAGS_DSP_MULT = 0; + + // Int-Mult + parameter APU_FLAGS_INT_MULT = 1; + + // Int-div + + // addsub + parameter PIPE_REG_ADDSUB = 1; + + // mult + parameter PIPE_REG_MULT = 1; + + // casts + parameter PIPE_REG_CAST = 1; + + // mac + parameter PIPE_REG_MAC = 2; + + // div + parameter PIPE_REG_DIV = 4; + + // sqrt + parameter PIPE_REG_SQRT = 5; + + // iter divsqrt + +endpackage // apu_core_package diff --git a/hw/deps/riscv/include/fpnew_pkg.sv b/hw/deps/riscv/include/fpnew_pkg.sv new file mode 100644 index 0000000..6065054 --- /dev/null +++ b/hw/deps/riscv/include/fpnew_pkg.sv @@ -0,0 +1,484 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Stefan Mach + +package fpnew_pkg; + + // --------- + // FP TYPES + // --------- + // | Enumerator | Format | Width | EXP_BITS | MAN_BITS + // |:----------:|------------------|-------:|:--------:|:--------: + // | FP32 | IEEE binary32 | 32 bit | 8 | 23 + // | FP64 | IEEE binary64 | 64 bit | 11 | 52 + // | FP16 | IEEE binary16 | 16 bit | 5 | 10 + // | FP8 | binary8 | 8 bit | 5 | 2 + // | FP16ALT | binary16alt | 16 bit | 8 | 7 + // *NOTE:* Add new formats only at the end of the enumeration for backwards compatibilty! + + // Encoding for a format + typedef struct packed { + int unsigned exp_bits; + int unsigned man_bits; + } fp_encoding_t; + + localparam int unsigned NUM_FP_FORMATS = 5; // change me to add formats + localparam int unsigned FP_FORMAT_BITS = $clog2(NUM_FP_FORMATS); + + // FP formats + typedef enum logic [FP_FORMAT_BITS-1:0] { + FP32 = 'd0, + FP64 = 'd1, + FP16 = 'd2, + FP8 = 'd3, + FP16ALT = 'd4 + // add new formats here + } fp_format_e; + + // Encodings for supported FP formats + localparam fp_encoding_t [0:NUM_FP_FORMATS-1] FP_ENCODINGS = '{ + '{8, 23}, // IEEE binary32 (single) + '{11, 52}, // IEEE binary64 (double) + '{5, 10}, // IEEE binary16 (half) + '{5, 2}, // custom binary8 + '{8, 7} // custom binary16alt + // add new formats here + }; + + typedef logic [0:NUM_FP_FORMATS-1] fmt_logic_t; // Logic indexed by FP format (for masks) + typedef logic [0:NUM_FP_FORMATS-1][31:0] fmt_unsigned_t; // Unsigned indexed by FP format + + localparam fmt_logic_t CPK_FORMATS = 5'b11000; // FP32 and FP64 can provide CPK only + + // --------- + // INT TYPES + // --------- + // | Enumerator | Width | + // |:----------:|-------:| + // | INT8 | 8 bit | + // | INT16 | 16 bit | + // | INT32 | 32 bit | + // | INT64 | 64 bit | + // *NOTE:* Add new formats only at the end of the enumeration for backwards compatibilty! + + localparam int unsigned NUM_INT_FORMATS = 4; // change me to add formats + localparam int unsigned INT_FORMAT_BITS = $clog2(NUM_INT_FORMATS); + + // Int formats + typedef enum logic [INT_FORMAT_BITS-1:0] { + INT8, + INT16, + INT32, + INT64 + // add new formats here + } int_format_e; + + // Returns the width of an INT format by index + function automatic int unsigned int_width(int_format_e ifmt); + unique case (ifmt) + INT8: return 8; + INT16: return 16; + INT32: return 32; + INT64: return 64; + endcase + endfunction + + typedef logic [0:NUM_INT_FORMATS-1] ifmt_logic_t; // Logic indexed by INT format (for masks) + + // -------------- + // FP OPERATIONS + // -------------- + localparam int unsigned NUM_OPGROUPS = 4; + + // Each FP operation belongs to an operation group + typedef enum logic [1:0] { + ADDMUL, DIVSQRT, NONCOMP, CONV + } opgroup_e; + + localparam int unsigned OP_BITS = 4; + + typedef enum logic [OP_BITS-1:0] { + FMADD, FNMSUB, ADD, MUL, // ADDMUL operation group + DIV, SQRT, // DIVSQRT operation group + SGNJ, MINMAX, CMP, CLASSIFY, // NONCOMP operation group + F2F, F2I, I2F, CPKAB, CPKCD // CONV operation group + } operation_e; + + // ------------------- + // RISC-V FP-SPECIFIC + // ------------------- + // Rounding modes + typedef enum logic [2:0] { + RNE = 3'b000, + RTZ = 3'b001, + RDN = 3'b010, + RUP = 3'b011, + RMM = 3'b100, + DYN = 3'b111 + } roundmode_e; + + // Status flags + typedef struct packed { + logic NV; // Invalid + logic DZ; // Divide by zero + logic OF; // Overflow + logic UF; // Underflow + logic NX; // Inexact + } status_t; + + // Information about a floating point value + typedef struct packed { + logic is_normal; // is the value normal + logic is_subnormal; // is the value subnormal + logic is_zero; // is the value zero + logic is_inf; // is the value infinity + logic is_nan; // is the value NaN + logic is_signalling; // is the value a signalling NaN + logic is_quiet; // is the value a quiet NaN + logic is_boxed; // is the value properly NaN-boxed (RISC-V specific) + } fp_info_t; + + // Classification mask + typedef enum logic [9:0] { + NEGINF = 10'b00_0000_0001, + NEGNORM = 10'b00_0000_0010, + NEGSUBNORM = 10'b00_0000_0100, + NEGZERO = 10'b00_0000_1000, + POSZERO = 10'b00_0001_0000, + POSSUBNORM = 10'b00_0010_0000, + POSNORM = 10'b00_0100_0000, + POSINF = 10'b00_1000_0000, + SNAN = 10'b01_0000_0000, + QNAN = 10'b10_0000_0000 + } classmask_e; + + // ------------------ + // FPU configuration + // ------------------ + // Pipelining registers can be inserted (at elaboration time) into operational units + typedef enum logic [1:0] { + BEFORE, // registers are inserted at the inputs of the unit + AFTER, // registers are inserted at the outputs of the unit + INSIDE, // registers are inserted at predetermined (suboptimal) locations in the unit + DISTRIBUTED // registers are evenly distributed, INSIDE >= AFTER >= BEFORE + } pipe_config_t; + + // Arithmetic units can be arranged in parallel (per format), merged (multi-format) or not at all. + typedef enum logic [1:0] { + DISABLED, // arithmetic units are not generated + PARALLEL, // arithmetic units are generated in prallel slices, one for each format + MERGED // arithmetic units are contained within a merged unit holding multiple formats + } unit_type_t; + + // Array of unit types indexed by format + typedef unit_type_t [0:NUM_FP_FORMATS-1] fmt_unit_types_t; + + // Array of format-specific unit types by opgroup + typedef fmt_unit_types_t [0:NUM_OPGROUPS-1] opgrp_fmt_unit_types_t; + // same with unsigned + typedef fmt_unsigned_t [0:NUM_OPGROUPS-1] opgrp_fmt_unsigned_t; + + // FPU configuration: features + typedef struct packed { + int unsigned Width; + logic EnableVectors; + logic EnableNanBox; + fmt_logic_t FpFmtMask; + ifmt_logic_t IntFmtMask; + } fpu_features_t; + + localparam fpu_features_t RV64D = '{ + Width: 64, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11000, + IntFmtMask: 4'b0011 + }; + + localparam fpu_features_t RV32D = '{ + Width: 64, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11000, + IntFmtMask: 4'b0010 + }; + + localparam fpu_features_t RV32F = '{ + Width: 32, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10000, + IntFmtMask: 4'b0010 + }; + + localparam fpu_features_t RV64D_Xsflt = '{ + Width: 64, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11111, + IntFmtMask: 4'b1111 + }; + + localparam fpu_features_t RV32F_Xsflt = '{ + Width: 32, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10111, + IntFmtMask: 4'b1110 + }; + + localparam fpu_features_t RV32F_Xf16alt_Xfvec = '{ + Width: 32, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10001, + IntFmtMask: 4'b0110 + }; + + + // FPU configuraion: implementation + typedef struct packed { + opgrp_fmt_unsigned_t PipeRegs; + opgrp_fmt_unit_types_t UnitTypes; + pipe_config_t PipeConfig; + } fpu_implementation_t; + + localparam fpu_implementation_t DEFAULT_NOREGS = '{ + PipeRegs: '{default: 0}, + UnitTypes: '{'{default: PARALLEL}, // ADDMUL + '{default: MERGED}, // DIVSQRT + '{default: PARALLEL}, // NONCOMP + '{default: MERGED}}, // CONV + PipeConfig: BEFORE + }; + + localparam fpu_implementation_t DEFAULT_SNITCH = '{ + PipeRegs: '{default: 1}, + UnitTypes: '{'{default: PARALLEL}, // ADDMUL + '{default: DISABLED}, // DIVSQRT + '{default: PARALLEL}, // NONCOMP + '{default: MERGED}}, // CONV + PipeConfig: BEFORE + }; + + // ----------------------- + // Synthesis optimization + // ----------------------- + localparam logic DONT_CARE = 1'b1; // the value to assign as don't care + + // ------------------------- + // General helper functions + // ------------------------- + function automatic int minimum(int a, int b); + return (a < b) ? a : b; + endfunction + + function automatic int maximum(int a, int b); + return (a > b) ? a : b; + endfunction + + // ------------------------------------------- + // Helper functions for FP formats and values + // ------------------------------------------- + // Returns the width of a FP format + function automatic int unsigned fp_width(fp_format_e fmt); + return FP_ENCODINGS[fmt].exp_bits + FP_ENCODINGS[fmt].man_bits + 1; + endfunction + + // Returns the widest FP format present + function automatic int unsigned max_fp_width(fmt_logic_t cfg); + automatic int unsigned res = 0; + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i]) + res = unsigned'(maximum(res, fp_width(fp_format_e'(i)))); + return res; + endfunction + + // Returns the narrowest FP format present + function automatic int unsigned min_fp_width(fmt_logic_t cfg); + automatic int unsigned res = max_fp_width(cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i]) + res = unsigned'(minimum(res, fp_width(fp_format_e'(i)))); + return res; + endfunction + + // Returns the number of expoent bits for a format + function automatic int unsigned exp_bits(fp_format_e fmt); + return FP_ENCODINGS[fmt].exp_bits; + endfunction + + // Returns the number of mantissa bits for a format + function automatic int unsigned man_bits(fp_format_e fmt); + return FP_ENCODINGS[fmt].man_bits; + endfunction + + // Returns the bias value for a given format (as per IEEE 754-2008) + function automatic int unsigned bias(fp_format_e fmt); + return unsigned'(2**(FP_ENCODINGS[fmt].exp_bits-1)-1); // symmetrical bias + endfunction + + function automatic fp_encoding_t super_format(fmt_logic_t cfg); + automatic fp_encoding_t res; + res = '0; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + if (cfg[fmt]) begin // only active format + res.exp_bits = unsigned'(maximum(res.exp_bits, exp_bits(fp_format_e'(fmt)))); + res.man_bits = unsigned'(maximum(res.man_bits, man_bits(fp_format_e'(fmt)))); + end + return res; + endfunction + + // ------------------------------------------- + // Helper functions for INT formats and values + // ------------------------------------------- + // Returns the widest INT format present + function automatic int unsigned max_int_width(ifmt_logic_t cfg); + automatic int unsigned res = 0; + for (int ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin + if (cfg[ifmt]) res = maximum(res, int_width(int_format_e'(ifmt))); + end + return res; + endfunction + + // -------------------------------------------------- + // Helper functions for operations and FPU structure + // -------------------------------------------------- + // Returns the operation group of the given operation + function automatic opgroup_e get_opgroup(operation_e op); + unique case (op) + FMADD, FNMSUB, ADD, MUL: return ADDMUL; + DIV, SQRT: return DIVSQRT; + SGNJ, MINMAX, CMP, CLASSIFY: return NONCOMP; + F2F, F2I, I2F, CPKAB, CPKCD: return CONV; + default: return NONCOMP; + endcase + endfunction + + // Returns the number of operands by operation group + function automatic int unsigned num_operands(opgroup_e grp); + unique case (grp) + ADDMUL: return 3; + DIVSQRT: return 2; + NONCOMP: return 2; + CONV: return 3; // vectorial casts use 3 operands + default: return 0; + endcase + endfunction + + // Returns the number of lanes according to width, format and vectors + function automatic int unsigned num_lanes(int unsigned width, fp_format_e fmt, logic vec); + return vec ? width / fp_width(fmt) : 1; // if no vectors, only one lane + endfunction + + // Returns the maximum number of lanes in the FPU according to width, format config and vectors + function automatic int unsigned max_num_lanes(int unsigned width, fmt_logic_t cfg, logic vec); + return vec ? width / min_fp_width(cfg) : 1; // if no vectors, only one lane + endfunction + + // Returns a mask of active FP formats that are present in lane lane_no of a multiformat slice + function automatic fmt_logic_t get_lane_formats(int unsigned width, + fmt_logic_t cfg, + int unsigned lane_no); + automatic fmt_logic_t res; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active formats with the number of lanes for that format + res[fmt] = cfg[fmt] & (width / fp_width(fp_format_e'(fmt)) > lane_no); + return res; + endfunction + + // Returns a mask of active INT formats that are present in lane lane_no of a multiformat slice + function automatic ifmt_logic_t get_lane_int_formats(int unsigned width, + fmt_logic_t cfg, + ifmt_logic_t icfg, + int unsigned lane_no); + automatic ifmt_logic_t res; + automatic fmt_logic_t lanefmts; + res = '0; + lanefmts = get_lane_formats(width, cfg, lane_no); + + for (int unsigned ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active int formats with the width of the float formats + if ((fp_width(fp_format_e'(fmt)) == int_width(int_format_e'(ifmt)))) + res[ifmt] |= icfg[ifmt] && lanefmts[fmt]; + return res; + endfunction + + // Returns a mask of active FP formats that are present in lane lane_no of a CONV slice + function automatic fmt_logic_t get_conv_lane_formats(int unsigned width, + fmt_logic_t cfg, + int unsigned lane_no); + automatic fmt_logic_t res; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active formats with the number of lanes for that format, CPK at least twice + res[fmt] = cfg[fmt] && ((width / fp_width(fp_format_e'(fmt)) > lane_no) || + (CPK_FORMATS[fmt] && (lane_no < 2))); + return res; + endfunction + + // Returns a mask of active INT formats that are present in lane lane_no of a CONV slice + function automatic ifmt_logic_t get_conv_lane_int_formats(int unsigned width, + fmt_logic_t cfg, + ifmt_logic_t icfg, + int unsigned lane_no); + automatic ifmt_logic_t res; + automatic fmt_logic_t lanefmts; + res = '0; + lanefmts = get_conv_lane_formats(width, cfg, lane_no); + + for (int unsigned ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active int formats with the width of the float formats + res[ifmt] |= icfg[ifmt] && lanefmts[fmt] && + (fp_width(fp_format_e'(fmt)) == int_width(int_format_e'(ifmt))); + return res; + endfunction + + // Return whether any active format is set as MERGED + function automatic logic any_enabled_multi(fmt_unit_types_t types, fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i] && types[i] == MERGED) + return 1'b1; + return 1'b0; + endfunction + + // Return whether the given format is the first active one set as MERGED + function automatic logic is_first_enabled_multi(fp_format_e fmt, + fmt_unit_types_t types, + fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) begin + if (cfg[i] && types[i] == MERGED) return (fp_format_e'(i) == fmt); + end + return 1'b0; + endfunction + + // Returns the first format that is active and is set as MERGED + function automatic fp_format_e get_first_enabled_multi(fmt_unit_types_t types, fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i] && types[i] == MERGED) + return fp_format_e'(i); + return fp_format_e'(0); + endfunction + + // Returns the largest number of regs that is active and is set as MERGED + function automatic int unsigned get_num_regs_multi(fmt_unsigned_t regs, + fmt_unit_types_t types, + fmt_logic_t cfg); + automatic int unsigned res = 0; + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) begin + if (cfg[i] && types[i] == MERGED) res = maximum(res, regs[i]); + end + return res; + endfunction + +endpackage diff --git a/hw/deps/riscv/include/riscv_defines.sv b/hw/deps/riscv/include/riscv_defines.sv new file mode 100644 index 0000000..b8556a5 --- /dev/null +++ b/hw/deps/riscv/include/riscv_defines.sv @@ -0,0 +1,675 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Matthias Baer - baermatt@student.ethz.ch // +// // +// Additional contributions by: // +// Sven Stucki - svstucki@student.ethz.ch // +// // +// // +// Design Name: RISC-V processor core // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Defines for various constants used by the processor core. // +// // +//////////////////////////////////////////////////////////////////////////////// + +package riscv_defines; + +//////////////////////////////////////////////// +// ___ ____ _ // +// / _ \ _ __ / ___|___ __| | ___ ___ // +// | | | | '_ \| | / _ \ / _` |/ _ \/ __| // +// | |_| | |_) | |__| (_) | (_| | __/\__ \ // +// \___/| .__/ \____\___/ \__,_|\___||___/ // +// |_| // +//////////////////////////////////////////////// + +parameter OPCODE_SYSTEM = 7'h73; +parameter OPCODE_FENCE = 7'h0f; +parameter OPCODE_OP = 7'h33; +parameter OPCODE_OPIMM = 7'h13; +parameter OPCODE_STORE = 7'h23; +parameter OPCODE_BSW = 7'h6b; +parameter OPCODE_LOAD = 7'h03; +parameter OPCODE_BRANCH = 7'h63; +parameter OPCODE_JALR = 7'h67; +parameter OPCODE_JAL = 7'h6f; +parameter OPCODE_AUIPC = 7'h17; +parameter OPCODE_LUI = 7'h37; +parameter OPCODE_OP_FP = 7'h53; +parameter OPCODE_OP_FMADD = 7'h43; +parameter OPCODE_OP_FNMADD = 7'h4f; +parameter OPCODE_OP_FMSUB = 7'h47; +parameter OPCODE_OP_FNMSUB = 7'h4b; +parameter OPCODE_STORE_FP = 7'h27; +parameter OPCODE_LOAD_FP = 7'h07; +parameter OPCODE_AMO = 7'h2F; + +// those opcodes are now used for PULP custom instructions +// parameter OPCODE_CUST0 = 7'h0b +// parameter OPCODE_CUST1 = 7'h2b + +// PULP custom +parameter OPCODE_LOAD_POST = 7'h0b; +parameter OPCODE_STORE_POST = 7'h2b; +parameter OPCODE_STORE_BUF = 7'b11_010_11; +parameter OPCODE_STORE_POST_BUF = 7'b11_101_11; +parameter OPCODE_PULP_OP = 7'h5b; +parameter OPCODE_VECOP = 7'h57; +parameter OPCODE_HWLOOP = 7'h7b; + +parameter REGC_S1 = 2'b10; +parameter REGC_S4 = 2'b00; +parameter REGC_RD = 2'b01; +parameter REGC_ZERO = 2'b11; + + +////////////////////////////////////////////////////////////////////////////// +// _ _ _ _ ___ _ _ // +// / \ | | | | | | / _ \ _ __ ___ _ __ __ _| |_(_) ___ _ __ ___ // +// / _ \ | | | | | | | | | | '_ \ / _ \ '__/ _` | __| |/ _ \| '_ \/ __| // +// / ___ \| |__| |_| | | |_| | |_) | __/ | | (_| | |_| | (_) | | | \__ \ // +// /_/ \_\_____\___/ \___/| .__/ \___|_| \__,_|\__|_|\___/|_| |_|___/ // +// |_| // +////////////////////////////////////////////////////////////////////////////// + +parameter ALU_OP_WIDTH = 7; + +parameter ALU_ADD = 7'b0011000; +parameter ALU_SUB = 7'b0011001; +parameter ALU_ADDU = 7'b0011010; +parameter ALU_SUBU = 7'b0011011; +parameter ALU_ADDR = 7'b0011100; +parameter ALU_SUBR = 7'b0011101; +parameter ALU_ADDUR = 7'b0011110; +parameter ALU_SUBUR = 7'b0011111; + +parameter ALU_XOR = 7'b0101111; +parameter ALU_OR = 7'b0101110; +parameter ALU_AND = 7'b0010101; + +// Shifts +parameter ALU_SRA = 7'b0100100; +parameter ALU_SRL = 7'b0100101; +parameter ALU_ROR = 7'b0100110; +parameter ALU_SLL = 7'b0100111; + +// bit manipulation +parameter ALU_BEXT = 7'b0101000; +parameter ALU_BEXTU = 7'b0101001; +parameter ALU_BINS = 7'b0101010; +parameter ALU_BCLR = 7'b0101011; +parameter ALU_BSET = 7'b0101100; +parameter ALU_BREV = 7'b1001001; + +// Bit counting +parameter ALU_FF1 = 7'b0110110; +parameter ALU_FL1 = 7'b0110111; +parameter ALU_CNT = 7'b0110100; +parameter ALU_CLB = 7'b0110101; + +// Sign-/zero-extensions +parameter ALU_EXTS = 7'b0111110; +parameter ALU_EXT = 7'b0111111; + +// Comparisons +parameter ALU_LTS = 7'b0000000; +parameter ALU_LTU = 7'b0000001; +parameter ALU_LES = 7'b0000100; +parameter ALU_LEU = 7'b0000101; +parameter ALU_GTS = 7'b0001000; +parameter ALU_GTU = 7'b0001001; +parameter ALU_GES = 7'b0001010; +parameter ALU_GEU = 7'b0001011; +parameter ALU_EQ = 7'b0001100; +parameter ALU_NE = 7'b0001101; + +// Set Lower Than operations +parameter ALU_SLTS = 7'b0000010; +parameter ALU_SLTU = 7'b0000011; +parameter ALU_SLETS = 7'b0000110; +parameter ALU_SLETU = 7'b0000111; + +// Absolute value +parameter ALU_ABS = 7'b0010100; +parameter ALU_CLIP = 7'b0010110; +parameter ALU_CLIPU = 7'b0010111; + +// Insert/extract +parameter ALU_INS = 7'b0101101; + +// min/max +parameter ALU_MIN = 7'b0010000; +parameter ALU_MINU = 7'b0010001; +parameter ALU_MAX = 7'b0010010; +parameter ALU_MAXU = 7'b0010011; + +// div/rem +parameter ALU_DIVU = 7'b0110000; // bit 0 is used for signed mode, bit 1 is used for remdiv +parameter ALU_DIV = 7'b0110001; // bit 0 is used for signed mode, bit 1 is used for remdiv +parameter ALU_REMU = 7'b0110010; // bit 0 is used for signed mode, bit 1 is used for remdiv +parameter ALU_REM = 7'b0110011; // bit 0 is used for signed mode, bit 1 is used for remdiv + +parameter ALU_SHUF = 7'b0111010; +parameter ALU_SHUF2 = 7'b0111011; +parameter ALU_PCKLO = 7'b0111000; +parameter ALU_PCKHI = 7'b0111001; + +// fpu +parameter ALU_FKEEP = 7'b1111111; // hack, to support fcvt.s.d +parameter ALU_FSGNJ = 7'b1000000; +parameter ALU_FSGNJN = 7'b1000001; +parameter ALU_FSGNJX = 7'b1000010; +parameter ALU_FEQ = 7'b1000011; +parameter ALU_FLT = 7'b1000100; +parameter ALU_FLE = 7'b1000101; +parameter ALU_FMAX = 7'b1000110; +parameter ALU_FMIN = 7'b1000111; +parameter ALU_FCLASS = 7'b1001000; + +parameter MUL_MAC32 = 3'b000; +parameter MUL_MSU32 = 3'b001; +parameter MUL_I = 3'b010; +parameter MUL_IR = 3'b011; +parameter MUL_DOT8 = 3'b100; +parameter MUL_DOT16 = 3'b101; +parameter MUL_H = 3'b110; + +// vector modes +parameter VEC_MODE32 = 2'b00; +parameter VEC_MODE16 = 2'b10; +parameter VEC_MODE8 = 2'b11; + + + // FSM state encoding + typedef enum logic [4:0] { RESET, BOOT_SET, SLEEP, WAIT_SLEEP, FIRST_FETCH, + DECODE, + IRQ_TAKEN_ID, IRQ_TAKEN_IF, IRQ_FLUSH, IRQ_FLUSH_ELW, ELW_EXE, + FLUSH_EX, FLUSH_WB, XRET_JUMP, + DBG_TAKEN_ID, DBG_TAKEN_IF, DBG_FLUSH, DBG_WAIT_BRANCH } ctrl_state_e; + + +///////////////////////////////////////////////////////// +// ____ ____ ____ _ _ // +// / ___/ ___| | _ \ ___ __ _(_)___| |_ ___ _ __ // +// | | \___ \ | |_) / _ \/ _` | / __| __/ _ \ '__| // +// | |___ ___) | | _ < __/ (_| | \__ \ || __/ | // +// \____|____/ |_| \_\___|\__, |_|___/\__\___|_| // +// |___/ // +///////////////////////////////////////////////////////// + +// CSRs mnemonics +// imported form IBEX, some regs may be still not implemented +typedef enum logic[11:0] { + // Machine information + CSR_MVENDORID = 12'hF11, + CSR_MARCHID = 12'hF12, + CSR_MIMPID = 12'hF13, + CSR_MHARTID = 12'hF14, + + // Machine trap setup + CSR_MSTATUS = 12'h300, + CSR_MISA = 12'h301, + CSR_MIE = 12'h304, + CSR_MTVEC = 12'h305, + CSR_MIE1 = 12'h7D0, + + // Machine trap handling + CSR_MSCRATCH = 12'h340, + CSR_MEPC = 12'h341, + CSR_MCAUSE = 12'h342, + CSR_MTVAL = 12'h343, + CSR_MIP = 12'h344, + CSR_MCOUNTEREN= 12'h306, + CSR_MIP1 = 12'h7D2, + + // User trap setup + CSR_USTATUS = 12'h000, + CSR_UTVEC = 12'h005, + + // User trap handling + CSR_UEPC = 12'h041, + CSR_UCAUSE = 12'h042, + + // Physical memory protection + CSR_PMPCFG0 = 12'h3A0, + CSR_PMPCFG1 = 12'h3A1, + CSR_PMPCFG2 = 12'h3A2, + CSR_PMPCFG3 = 12'h3A3, + CSR_PMPADDR0 = 12'h3B0, + CSR_PMPADDR1 = 12'h3B1, + CSR_PMPADDR2 = 12'h3B2, + CSR_PMPADDR3 = 12'h3B3, + CSR_PMPADDR4 = 12'h3B4, + CSR_PMPADDR5 = 12'h3B5, + CSR_PMPADDR6 = 12'h3B6, + CSR_PMPADDR7 = 12'h3B7, + CSR_PMPADDR8 = 12'h3B8, + CSR_PMPADDR9 = 12'h3B9, + CSR_PMPADDR10 = 12'h3BA, + CSR_PMPADDR11 = 12'h3BB, + CSR_PMPADDR12 = 12'h3BC, + CSR_PMPADDR13 = 12'h3BD, + CSR_PMPADDR14 = 12'h3BE, + CSR_PMPADDR15 = 12'h3BF, + + // Trigger + CSR_TSELECT = 12'h7A0, + CSR_TDATA1 = 12'h7A1, + CSR_TDATA2 = 12'h7A2, + CSR_TDATA3 = 12'h7A3, + CSR_MCONTEXT = 12'h7A8, + CSR_SCONTEXT = 12'h7AA, + + // Debug/trace + CSR_DCSR = 12'h7b0, + CSR_DPC = 12'h7b1, + + // Debug + CSR_DSCRATCH0 = 12'h7b2, + CSR_DSCRATCH1 = 12'h7b3, + + // Floating Point + CSR_FFLAGS = 12'h001, + CSR_FRM = 12'h002, + CSR_FCSR = 12'h003, + + // Hardware Performance Monitor + CSR_MCYCLE = 12'hb00, + CSR_MINSTRET = 12'hb02, + CSR_MHPMCOUNTER3 = 12'hb03, + CSR_MHPMCOUNTER4 = 12'hb04, + CSR_MHPMCOUNTER5 = 12'hb05, + CSR_MHPMCOUNTER6 = 12'hb06, + CSR_MHPMCOUNTER7 = 12'hb07, + CSR_MHPMCOUNTER8 = 12'hb08, + CSR_MHPMCOUNTER9 = 12'hb09, + CSR_MHPMCOUNTER10 = 12'hb0a, + CSR_MHPMCOUNTER11 = 12'hb0b, + CSR_MHPMCOUNTER12 = 12'hb0c, + CSR_MHPMCOUNTER13 = 12'hb0d, + CSR_MHPMCOUNTER14 = 12'hb0e, + CSR_MHPMCOUNTER15 = 12'hb0f, + CSR_MHPMCOUNTER16 = 12'hb10, + CSR_MHPMCOUNTER17 = 12'hb11, + CSR_MHPMCOUNTER18 = 12'hb12, + CSR_MHPMCOUNTER19 = 12'hb13, + CSR_MHPMCOUNTER20 = 12'hb14, + CSR_MHPMCOUNTER21 = 12'hb15, + CSR_MHPMCOUNTER22 = 12'hb16, + CSR_MHPMCOUNTER23 = 12'hb17, + CSR_MHPMCOUNTER24 = 12'hb18, + CSR_MHPMCOUNTER25 = 12'hb19, + CSR_MHPMCOUNTER26 = 12'hb1a, + CSR_MHPMCOUNTER27 = 12'hb1b, + CSR_MHPMCOUNTER28 = 12'hb1c, + CSR_MHPMCOUNTER29 = 12'hb1d, + CSR_MHPMCOUNTER30 = 12'hb1e, + CSR_MHPMCOUNTER31 = 12'hb1f, + + CSR_MCYCLEH = 12'hb80, + CSR_MINSTRETH = 12'hb82, + CSR_MHPMCOUNTER3H = 12'hb83, + CSR_MHPMCOUNTER4H = 12'hb84, + CSR_MHPMCOUNTER5H = 12'hb85, + CSR_MHPMCOUNTER6H = 12'hb86, + CSR_MHPMCOUNTER7H = 12'hb87, + CSR_MHPMCOUNTER8H = 12'hb88, + CSR_MHPMCOUNTER9H = 12'hb89, + CSR_MHPMCOUNTER10H = 12'hb8a, + CSR_MHPMCOUNTER11H = 12'hb8b, + CSR_MHPMCOUNTER12H = 12'hb8c, + CSR_MHPMCOUNTER13H = 12'hb8d, + CSR_MHPMCOUNTER14H = 12'hb8e, + CSR_MHPMCOUNTER15H = 12'hb8f, + CSR_MHPMCOUNTER16H = 12'hb90, + CSR_MHPMCOUNTER17H = 12'hb91, + CSR_MHPMCOUNTER18H = 12'hb92, + CSR_MHPMCOUNTER19H = 12'hb93, + CSR_MHPMCOUNTER20H = 12'hb94, + CSR_MHPMCOUNTER21H = 12'hb95, + CSR_MHPMCOUNTER22H = 12'hb96, + CSR_MHPMCOUNTER23H = 12'hb97, + CSR_MHPMCOUNTER24H = 12'hb98, + CSR_MHPMCOUNTER25H = 12'hb99, + CSR_MHPMCOUNTER26H = 12'hb9a, + CSR_MHPMCOUNTER27H = 12'hb9b, + CSR_MHPMCOUNTER28H = 12'hb9c, + CSR_MHPMCOUNTER29H = 12'hb9d, + CSR_MHPMCOUNTER30H = 12'hb9e, + CSR_MHPMCOUNTER31H = 12'hb9f, + + CSR_MCOUNTINHIBIT = 12'h320, + + CSR_MHPMEVENT3 = 12'h323, + CSR_MHPMEVENT4 = 12'h324, + CSR_MHPMEVENT5 = 12'h325, + CSR_MHPMEVENT6 = 12'h326, + CSR_MHPMEVENT7 = 12'h327, + CSR_MHPMEVENT8 = 12'h328, + CSR_MHPMEVENT9 = 12'h329, + CSR_MHPMEVENT10 = 12'h32a, + CSR_MHPMEVENT11 = 12'h32b, + CSR_MHPMEVENT12 = 12'h32c, + CSR_MHPMEVENT13 = 12'h32d, + CSR_MHPMEVENT14 = 12'h32e, + CSR_MHPMEVENT15 = 12'h32f, + CSR_MHPMEVENT16 = 12'h330, + CSR_MHPMEVENT17 = 12'h331, + CSR_MHPMEVENT18 = 12'h332, + CSR_MHPMEVENT19 = 12'h333, + CSR_MHPMEVENT20 = 12'h334, + CSR_MHPMEVENT21 = 12'h335, + CSR_MHPMEVENT22 = 12'h336, + CSR_MHPMEVENT23 = 12'h337, + CSR_MHPMEVENT24 = 12'h338, + CSR_MHPMEVENT25 = 12'h339, + CSR_MHPMEVENT26 = 12'h33a, + CSR_MHPMEVENT27 = 12'h33b, + CSR_MHPMEVENT28 = 12'h33c, + CSR_MHPMEVENT29 = 12'h33d, + CSR_MHPMEVENT30 = 12'h33e, + CSR_MHPMEVENT31 = 12'h33f + +} csr_num_e; + +// CSR operations +parameter CSR_OP_READ = 2'b00; +parameter CSR_OP_WRITE = 2'b01; +parameter CSR_OP_SET = 2'b10; +parameter CSR_OP_CLEAR = 2'b11; + +// CSR interrupt pending/enable bits +parameter int unsigned CSR_MSIX_BIT = 3; +parameter int unsigned CSR_MTIX_BIT = 7; +parameter int unsigned CSR_MEIX_BIT = 11; +parameter int unsigned CSR_MFIX_BIT_LOW = 16; +parameter int unsigned CSR_MFIX_BIT_HIGH = 31; + +// SPR for debugger, not accessible by CPU +parameter SP_DVR0 = 16'h3000; +parameter SP_DCR0 = 16'h3008; +parameter SP_DMR1 = 16'h3010; +parameter SP_DMR2 = 16'h3011; + +parameter SP_DVR_MSB = 8'h00; +parameter SP_DCR_MSB = 8'h01; +parameter SP_DMR_MSB = 8'h02; +parameter SP_DSR_MSB = 8'h04; + +// Privileged mode +typedef enum logic[1:0] { + PRIV_LVL_M = 2'b11, + PRIV_LVL_H = 2'b10, + PRIV_LVL_S = 2'b01, + PRIV_LVL_U = 2'b00 +} PrivLvl_t; + +/////////////////////////////////////////////// +// ___ ____ ____ _ // +// |_ _| _ \ / ___|| |_ __ _ __ _ ___ // +// | || | | | \___ \| __/ _` |/ _` |/ _ \ // +// | || |_| | ___) | || (_| | (_| | __/ // +// |___|____/ |____/ \__\__,_|\__, |\___| // +// |___/ // +/////////////////////////////////////////////// + +// forwarding operand mux +parameter SEL_REGFILE = 2'b00; +parameter SEL_FW_EX = 2'b01; +parameter SEL_FW_WB = 2'b10; + +// operand a selection +parameter OP_A_REGA_OR_FWD = 3'b000; +parameter OP_A_CURRPC = 3'b001; +parameter OP_A_IMM = 3'b010; +parameter OP_A_REGB_OR_FWD = 3'b011; +parameter OP_A_REGC_OR_FWD = 3'b100; + +// immediate a selection +parameter IMMA_Z = 1'b0; +parameter IMMA_ZERO = 1'b1; + +// operand b selection +parameter OP_B_REGB_OR_FWD = 3'b000; +parameter OP_B_REGC_OR_FWD = 3'b001; +parameter OP_B_IMM = 3'b010; +parameter OP_B_REGA_OR_FWD = 3'b011; +parameter OP_B_BMASK = 3'b100; + +// immediate b selection +parameter IMMB_I = 4'b0000; +parameter IMMB_S = 4'b0001; +parameter IMMB_U = 4'b0010; +parameter IMMB_PCINCR = 4'b0011; +parameter IMMB_S2 = 4'b0100; +parameter IMMB_S3 = 4'b0101; +parameter IMMB_VS = 4'b0110; +parameter IMMB_VU = 4'b0111; +parameter IMMB_SHUF = 4'b1000; +parameter IMMB_CLIP = 4'b1001; +parameter IMMB_BI = 4'b1011; + +// bit mask selection +parameter BMASK_A_ZERO = 1'b0; +parameter BMASK_A_S3 = 1'b1; + +parameter BMASK_B_S2 = 2'b00; +parameter BMASK_B_S3 = 2'b01; +parameter BMASK_B_ZERO = 2'b10; +parameter BMASK_B_ONE = 2'b11; + +parameter BMASK_A_REG = 1'b0; +parameter BMASK_A_IMM = 1'b1; +parameter BMASK_B_REG = 1'b0; +parameter BMASK_B_IMM = 1'b1; + + +// multiplication immediates +parameter MIMM_ZERO = 1'b0; +parameter MIMM_S3 = 1'b1; + +// operand c selection +parameter OP_C_REGC_OR_FWD = 2'b00; +parameter OP_C_REGB_OR_FWD = 2'b01; +parameter OP_C_JT = 2'b10; + +// branch types +parameter BRANCH_NONE = 2'b00; +parameter BRANCH_JAL = 2'b01; +parameter BRANCH_JALR = 2'b10; +parameter BRANCH_COND = 2'b11; // conditional branches + +// jump target mux +parameter JT_JAL = 2'b01; +parameter JT_JALR = 2'b10; +parameter JT_COND = 2'b11; + +// Atomic operations +parameter AMO_LR = 5'b00010; +parameter AMO_SC = 5'b00011; +parameter AMO_SWAP = 5'b00001; +parameter AMO_ADD = 5'b00000; +parameter AMO_XOR = 5'b00100; +parameter AMO_AND = 5'b01100; +parameter AMO_OR = 5'b01000; +parameter AMO_MIN = 5'b10000; +parameter AMO_MAX = 5'b10100; +parameter AMO_MINU = 5'b11000; +parameter AMO_MAXU = 5'b11100; + +/////////////////////////////////////////////// +// ___ _____ ____ _ // +// |_ _| ___| / ___|| |_ __ _ __ _ ___ // +// | || |_ \___ \| __/ _` |/ _` |/ _ \ // +// | || _| ___) | || (_| | (_| | __/ // +// |___|_| |____/ \__\__,_|\__, |\___| // +// |___/ // +/////////////////////////////////////////////// + +// PC mux selector defines +parameter PC_BOOT = 3'b000; +parameter PC_JUMP = 3'b010; +parameter PC_BRANCH = 3'b011; +parameter PC_EXCEPTION = 3'b100; +parameter PC_FENCEI = 3'b001; +parameter PC_MRET = 3'b101; +parameter PC_URET = 3'b110; +parameter PC_DRET = 3'b111; + +// Exception PC mux selector defines +parameter EXC_PC_EXCEPTION = 3'b000; +parameter EXC_PC_IRQ = 3'b001; + +parameter EXC_PC_DBD = 3'b010; + +// Exception Cause +parameter EXC_CAUSE_INSTR_FAULT = 6'h01; +parameter EXC_CAUSE_ILLEGAL_INSN = 6'h02; +parameter EXC_CAUSE_BREAKPOINT = 6'h03; +parameter EXC_CAUSE_LOAD_FAULT = 6'h05; +parameter EXC_CAUSE_STORE_FAULT = 6'h07; +parameter EXC_CAUSE_ECALL_UMODE = 6'h08; +parameter EXC_CAUSE_ECALL_MMODE = 6'h0B; + +parameter int unsigned IRQ_ID_BITS = 6; +parameter int unsigned IRQ_LINES_NUM = 51; // number of physical irq lines to core +// Interrupt lines struct +typedef struct packed { + logic irq_software; + logic irq_timer; + logic irq_external; + logic [15:0] irq_fast; +} Interrupts_t; + + +// Trap mux selector +parameter TRAP_MACHINE = 2'b00; +parameter TRAP_USER = 2'b01; + +// Debug Cause +parameter DBG_CAUSE_NONE = 3'h0; +parameter DBG_CAUSE_EBREAK = 3'h1; +parameter DBG_CAUSE_TRIGGER = 3'h2; +parameter DBG_CAUSE_HALTREQ = 3'h3; +parameter DBG_CAUSE_STEP = 3'h4; +parameter DBG_CAUSE_RSTHALTREQ = 3'h5; + +// Debug module +parameter DBG_SETS_W = 6; + +parameter DBG_SETS_IRQ = 5; +parameter DBG_SETS_ECALL = 4; +parameter DBG_SETS_EILL = 3; +parameter DBG_SETS_ELSU = 2; +parameter DBG_SETS_EBRK = 1; +parameter DBG_SETS_SSTE = 0; + +parameter DBG_CAUSE_HALT = 6'h1F; + +// Constants for the dcsr.xdebugver fields +typedef enum logic[3:0] { + XDEBUGVER_NO = 4'd0, // no external debug support + XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec + XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec +} x_debug_ver_e; + + +///////////////////////////////////// +// THIS PART IS OBSOLETED BY FPNEW // +///////////////////////////////////// +// // private FPU +// parameter C_CMD = 4; +// parameter C_FPU_ADD_CMD = 4'h0; +// parameter C_FPU_SUB_CMD = 4'h1; +// parameter C_FPU_MUL_CMD = 4'h2; +// parameter C_FPU_DIV_CMD = 4'h3; +// parameter C_FPU_I2F_CMD = 4'h4; +// parameter C_FPU_F2I_CMD = 4'h5; +// parameter C_FPU_SQRT_CMD = 4'h6; +// parameter C_FPU_NOP_CMD = 4'h7; +// parameter C_FPU_FMADD_CMD = 4'h8; +// parameter C_FPU_FMSUB_CMD = 4'h9; +// parameter C_FPU_FNMADD_CMD = 4'hA; +// parameter C_FPU_FNMSUB_CMD = 4'hB; + +// Floating-point extensions configuration +parameter bit C_RVF = 1'b1; // Is F extension enabled +parameter bit C_RVD = 1'b0; // Is D extension enabled - NOT SUPPORTED CURRENTLY + +// Transprecision floating-point extensions configuration +parameter bit C_XF16 = 1'b0; // Is half-precision float extension (Xf16) enabled +parameter bit C_XF16ALT = 1'b0; // Is alternative half-precision float extension (Xf16alt) enabled +parameter bit C_XF8 = 1'b0; // Is quarter-precision float extension (Xf8) enabled +parameter bit C_XFVEC = 1'b0; // Is vectorial float extension (Xfvec) enabled + +// FPnew configuration +parameter C_FPNEW_OPBITS = fpnew_pkg::OP_BITS; +parameter C_FPNEW_FMTBITS = fpnew_pkg::FP_FORMAT_BITS; +parameter C_FPNEW_IFMTBITS = fpnew_pkg::INT_FORMAT_BITS; + +// Latency of FP operations: 0 = no pipe registers, 1 = 1 pipe register etc. +parameter int unsigned C_LAT_FP64 = 'd0; +parameter int unsigned C_LAT_FP32 = 'd0; +parameter int unsigned C_LAT_FP16 = 'd0; +parameter int unsigned C_LAT_FP16ALT = 'd0; +parameter int unsigned C_LAT_FP8 = 'd0; +parameter int unsigned C_LAT_DIVSQRT = 'd1; // divsqrt post-processing pipe +parameter int unsigned C_LAT_CONV = 'd0; +parameter int unsigned C_LAT_NONCOMP = 'd0; + +// General FPU-specific defines + +// Length of widest floating-point format = width of fp regfile +parameter C_FLEN = C_RVD ? 64 : // D ext. + C_RVF ? 32 : // F ext. + C_XF16 ? 16 : // Xf16 ext. + C_XF16ALT ? 16 : // Xf16alt ext. + C_XF8 ? 8 : // Xf8 ext. + 0; // Unused in case of no FP + +parameter C_FFLAG = 5; +parameter C_RM = 3; + +parameter C_PC = 5; + + + +///////////////////////////////////////////////////////// +// ____ ____ ____ // +// / ___/ ___| | _ \ // +// | | \___ \ | |_) | MAPPING // +// | |___ ___) | | _ < // +// \____|____/ |_| \_\ // +// // +///////////////////////////////////////////////////////// + +//Hardware Loop +parameter HWLoop0_START = 12'h7C0; //NON standard read/write (Machine CSRs). Old address 12'h7B0; +parameter HWLoop0_END = 12'h7C1; //NON standard read/write (Machine CSRs). Old address 12'h7B1; +parameter HWLoop0_COUNTER = 12'h7C2; //NON standard read/write (Machine CSRs). Old address 12'h7B2; +parameter HWLoop1_START = 12'h7C4; //NON standard read/write (Machine CSRs). Old address 12'h7B4; +parameter HWLoop1_END = 12'h7C5; //NON standard read/write (Machine CSRs). Old address 12'h7B5; +parameter HWLoop1_COUNTER = 12'h7C6; //NON standard read/write (Machine CSRs). Old address 12'h7B6; + +//Custom Hart and Priveledge +parameter UHARTID = 12'h014; //NON standard read/write (Machine CSRs) - User Hart ID +parameter PRIVLV = 12'hC10; //NON standard read/write (Machine CSRs) - Privilege Level +//Custom Floating Point +parameter FPREC = 12'h006; //NON standard read/write (Machine CSRs) - Floating Point + +//PMP Range +parameter CSR_PMPADDR_RANGE_X = CSR_PMPADDR0 | 12'b0000_0000_xxxx; +parameter CSR_PMPCFG_RANGE_X = CSR_PMPCFG0 | 12'b0000_0000_00xx; + +endpackage diff --git a/hw/deps/riscv/include/riscv_tracer_defines.sv b/hw/deps/riscv/include/riscv_tracer_defines.sv new file mode 100644 index 0000000..aac4b83 --- /dev/null +++ b/hw/deps/riscv/include/riscv_tracer_defines.sv @@ -0,0 +1,203 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + + +package riscv_tracer_defines; +import riscv_defines::*; + +// settings +parameter bit SymbolicRegs = 0; // show abi names for registers + +// instruction masks (for tracer) +// parameter INSTR_CUSTOM0 = { 25'b?, OPCODE_CUST0 }; +// parameter INSTR_CUSTOM1 = { 25'b?, OPCODE_CUST1 }; +parameter INSTR_LUI = { 25'b?, OPCODE_LUI }; +parameter INSTR_AUIPC = { 25'b?, OPCODE_AUIPC }; +parameter INSTR_JAL = { 25'b?, OPCODE_JAL }; +parameter INSTR_JALR = { 17'b?, 3'b000, 5'b?, OPCODE_JALR }; +// BRANCH +parameter INSTR_BEQ = { 17'b?, 3'b000, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BNE = { 17'b?, 3'b001, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BLT = { 17'b?, 3'b100, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BGE = { 17'b?, 3'b101, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BLTU = { 17'b?, 3'b110, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BGEU = { 17'b?, 3'b111, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BEQIMM = { 17'b?, 3'b010, 5'b?, OPCODE_BRANCH }; +parameter INSTR_BNEIMM = { 17'b?, 3'b011, 5'b?, OPCODE_BRANCH }; +// OPIMM +parameter INSTR_ADDI = { 17'b?, 3'b000, 5'b?, OPCODE_OPIMM }; +parameter INSTR_SLTI = { 17'b?, 3'b010, 5'b?, OPCODE_OPIMM }; +parameter INSTR_SLTIU = { 17'b?, 3'b011, 5'b?, OPCODE_OPIMM }; +parameter INSTR_XORI = { 17'b?, 3'b100, 5'b?, OPCODE_OPIMM }; +parameter INSTR_ORI = { 17'b?, 3'b110, 5'b?, OPCODE_OPIMM }; +parameter INSTR_ANDI = { 17'b?, 3'b111, 5'b?, OPCODE_OPIMM }; +parameter INSTR_SLLI = { 7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OPIMM }; +parameter INSTR_SRLI = { 7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM }; +parameter INSTR_SRAI = { 7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OPIMM }; +// OP +parameter INSTR_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, OPCODE_OP }; +parameter INSTR_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, OPCODE_OP }; +parameter INSTR_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, OPCODE_OP }; +parameter INSTR_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, OPCODE_OP }; +parameter INSTR_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, OPCODE_OP }; +parameter INSTR_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, OPCODE_OP }; +parameter INSTR_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, OPCODE_OP }; +parameter INSTR_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, OPCODE_OP }; +parameter INSTR_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, OPCODE_OP }; +parameter INSTR_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, OPCODE_OP }; + + +parameter INSTR_FF1 = { 7'b0001000, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_FL1 = { 7'b0001000, 5'b0, 5'b?, 3'b001, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_CLB = { 7'b0001000, 5'b0, 5'b?, 3'b010, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_CNT = { 7'b0001000, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_OP }; // pulp specific + +parameter INSTR_EXTHS = { 7'b0001000, 10'b?, 3'b100, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_EXTHZ = { 7'b0001000, 10'b?, 3'b101, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_EXTBS = { 7'b0001000, 10'b?, 3'b110, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_EXTBZ = { 7'b0001000, 10'b?, 3'b111, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PAVG = { 7'b0000010, 10'b?, 3'b000, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PAVGU = { 7'b0000010, 10'b?, 3'b001, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PADDN = { 2'b00, 15'b?, 3'b010, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PADDUN = { 2'b10, 15'b?, 3'b010, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PADDRN = { 2'b00, 15'b?, 3'b110, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PADDURN = { 2'b10, 15'b?, 3'b110, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBN = { 2'b00, 15'b?, 3'b011, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBUN = { 2'b10, 15'b?, 3'b011, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBRN = { 2'b00, 15'b?, 3'b111, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBURN = { 2'b10, 15'b?, 3'b111, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PADDNR = { 2'b01, 15'b?, 3'b010, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PADDUNR = { 2'b11, 15'b?, 3'b010, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PADDRNR = { 2'b01, 15'b?, 3'b110, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PADDURNR = { 2'b11, 15'b?, 3'b110, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBNR = { 2'b01, 15'b?, 3'b011, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBUNR = { 2'b11, 15'b?, 3'b011, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBRNR = { 2'b01, 15'b?, 3'b111, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PSUBURNR = { 2'b11, 15'b?, 3'b111, 5'b?, OPCODE_PULP_OP }; // pulp specific + +parameter INSTR_PABS = { 7'b0001010, 10'b?, 3'b000, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PCLIP = { 7'b0001010, 10'b?, 3'b001, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PCLIPU = { 7'b0001010, 10'b?, 3'b010, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PCLIPR = { 7'b0001010, 10'b?, 3'b101, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PCLIPUR = { 7'b0001010, 10'b?, 3'b110, 5'b?, OPCODE_OP }; // pulp specific + +parameter INSTR_PSLET = { 7'b0000010, 10'b?, 3'b010, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PSLETU = { 7'b0000010, 10'b?, 3'b011, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PMIN = { 7'b0000010, 10'b?, 3'b100, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PMINU = { 7'b0000010, 10'b?, 3'b101, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PMAX = { 7'b0000010, 10'b?, 3'b110, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PMAXU = { 7'b0000010, 10'b?, 3'b111, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_ROR = { 7'b0000100, 10'b?, 3'b101, 5'b?, OPCODE_OP }; // pulp specific + +parameter INSTR_PBEXT = { 2'b11, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBEXTU = { 2'b11, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBINS = { 2'b11, 5'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBCLR = { 2'b11, 5'b?, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBSET = { 2'b11, 5'b?, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBREV = { 2'b11, 5'b?, 5'b?, 5'b?, 3'b101, 5'b?, OPCODE_OP }; // pulp specific + + +parameter INSTR_PBEXTR = { 2'b10, 5'b?, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBEXTUR = { 2'b10, 5'b?, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBINSR = { 2'b10, 5'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBCLRR = { 2'b10, 5'b?, 5'b?, 5'b?, 3'b011, 5'b?, OPCODE_OP }; // pulp specific +parameter INSTR_PBSETR = { 2'b10, 5'b?, 5'b?, 5'b?, 3'b100, 5'b?, OPCODE_OP }; // pulp specific + +// FENCE +parameter INSTR_FENCE = { 4'b0, 8'b?, 13'b0, OPCODE_FENCE }; +parameter INSTR_FENCEI = { 17'b0, 3'b001, 5'b0, OPCODE_FENCE }; +// SYSTEM +parameter INSTR_CSRRW = { 17'b?, 3'b001, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRRS = { 17'b?, 3'b010, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRRC = { 17'b?, 3'b011, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, OPCODE_SYSTEM }; +parameter INSTR_ECALL = { 12'b000000000000, 13'b0, OPCODE_SYSTEM }; +parameter INSTR_EBREAK = { 12'b000000000001, 13'b0, OPCODE_SYSTEM }; +parameter INSTR_URET = { 12'b000000000010, 13'b0, OPCODE_SYSTEM }; +parameter INSTR_SRET = { 12'b000100000010, 13'b0, OPCODE_SYSTEM }; +parameter INSTR_MRET = { 12'b001100000010, 13'b0, OPCODE_SYSTEM }; +parameter INSTR_DRET = { 12'b011110110010, 13'b0, OPCODE_SYSTEM }; +parameter INSTR_WFI = { 12'b000100000101, 13'b0, OPCODE_SYSTEM }; + +// RV32M +parameter INSTR_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, OPCODE_OP }; +parameter INSTR_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, OPCODE_OP }; +parameter INSTR_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, OPCODE_OP }; +parameter INSTR_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, OPCODE_OP }; +parameter INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, OPCODE_OP }; +parameter INSTR_PMUH = { 7'b0000001, 10'b?, 3'b001, 5'b?, OPCODE_OP }; +parameter INSTR_PMULHSU = { 7'b0000001, 10'b?, 3'b010, 5'b?, OPCODE_OP }; +parameter INSTR_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, OPCODE_OP }; +parameter INSTR_PMAC = { 7'b0100001, 10'b?, 3'b000, 5'b?, OPCODE_OP }; +parameter INSTR_PMSU = { 7'b0100001, 10'b?, 3'b001, 5'b?, OPCODE_OP }; + +//PULP MUL +parameter INSTR_PMULS = { 2'b10, 5'b? ,10'b?, 3'b000, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMULHLSN = { 2'b11, 5'b?, 10'b?, 3'b000, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMULRS = { 2'b10, 5'b? ,10'b?, 3'b100, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMULRHLSN = { 2'b11, 5'b?, 10'b?, 3'b100, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMULU = { 2'b00, 5'b? ,10'b?, 3'b000, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMULUHLU = { 2'b01, 5'b? ,10'b?, 3'b000, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMULRU = { 2'b00, 5'b? ,10'b?, 3'b100, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMULRUHLU = { 2'b01, 5'b? ,10'b?, 3'b100, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACS = { 2'b10, 5'b? ,10'b?, 3'b001, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACHLSN = { 2'b11, 5'b?, 10'b?, 3'b001, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACRS = { 2'b10, 5'b? ,10'b?, 3'b101, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACRHLSN = { 2'b11, 5'b?, 10'b?, 3'b101, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACU = { 2'b00, 5'b? ,10'b?, 3'b001, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACUHLU = { 2'b01, 5'b? ,10'b?, 3'b001, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACRU = { 2'b00, 5'b? ,10'b?, 3'b101, 5'b?, OPCODE_PULP_OP }; // pulp specific +parameter INSTR_PMACRUHLU = { 2'b01, 5'b? ,10'b?, 3'b101, 5'b?, OPCODE_PULP_OP }; // pulp specific + +// RV32F +parameter INSTR_FMADD = { 5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMADD }; +parameter INSTR_FMSUB = { 5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FMSUB }; +parameter INSTR_FNMSUB = { 5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMSUB }; +parameter INSTR_FNMADD = { 5'b?, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FNMADD }; + +parameter INSTR_FADD = { 5'b00000, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FSUB = { 5'b00001, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FMUL = { 5'b00010, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FDIV = { 5'b00011, 2'b00, 10'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FSQRT = { 5'b01011, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FSGNJS = { 5'b00100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FSGNJNS = { 5'b00100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FSGNJXS = { 5'b00100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FMIN = { 5'b00101, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FMAX = { 5'b00101, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FCVTWS = { 5'b11000, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FCVTWUS = { 5'b11000, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FMVXS = { 5'b11100, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FEQS = { 5'b10100, 2'b00, 10'b?, 3'b010, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FLTS = { 5'b10100, 2'b00, 10'b?, 3'b001, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FLES = { 5'b10100, 2'b00, 10'b?, 3'b000, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FCLASS = { 5'b11100, 2'b00, 5'b0, 5'b?, 3'b001, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FCVTSW = { 5'b11010, 2'b00, 5'b0, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FCVTSWU = { 5'b11010, 2'b00, 5'b1, 5'b?, 3'b?, 5'b?, OPCODE_OP_FP }; +parameter INSTR_FMVSX = { 5'b11110, 2'b00, 5'b0, 5'b?, 3'b000, 5'b?, OPCODE_OP_FP }; + +// RV32A +parameter INSTR_LR = { AMO_LR , 2'b?, 5'b0, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_SC = { AMO_SC , 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOSWAP = { AMO_SWAP, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOADD = { AMO_ADD , 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOXOR = { AMO_XOR , 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOAND = { AMO_AND , 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOOR = { AMO_OR , 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOMIN = { AMO_MIN , 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOMAX = { AMO_MAX , 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOMINU = { AMO_MINU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; +parameter INSTR_AMOMAXU = { AMO_MAXU, 2'b?, 5'b?, 5'b?, 3'b010, 5'b?, OPCODE_AMO }; + +// to be used in tracer! + +endpackage diff --git a/hw/deps/riscv/riscv_L0_buffer.sv b/hw/deps/riscv/riscv_L0_buffer.sv new file mode 100644 index 0000000..4a2903a --- /dev/null +++ b/hw/deps/riscv/riscv_L0_buffer.sv @@ -0,0 +1,282 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module riscv_L0_buffer +#( + parameter RDATA_IN_WIDTH = 128 +) +( + input logic clk, + input logic rst_n, + + input logic prefetch_i, + input logic [31:0] prefetch_addr_i, + + input logic branch_i, + input logic [31:0] branch_addr_i, + + input logic hwlp_i, + input logic [31:0] hwlp_addr_i, + + + output logic fetch_gnt_o, + output logic fetch_valid_o, + + output logic valid_o, + output logic [RDATA_IN_WIDTH/32-1:0][31:0] rdata_o, + output logic [31:0] addr_o, + + // goes to instruction memory / instruction cache + output logic instr_req_o, + output logic [31:0] instr_addr_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + input logic [RDATA_IN_WIDTH/32-1:0][31:0] instr_rdata_i, + + output logic busy_o +); + + enum logic [2:0] { EMPTY, VALID_L0, WAIT_GNT, WAIT_RVALID, ABORTED_BRANCH, WAIT_HWLOOP } CS, NS; + + logic [3:0][31:0] L0_buffer; + logic [31:0] addr_q, instr_addr_int; + logic valid; + // logic fetch_gnt_int, send_rvalid_int; + // logic fetch_valid_int; + + ////////////////////////////////////////////////////////////////////////////// + // FSM + ////////////////////////////////////////////////////////////////////////////// + + always_comb + begin + NS = CS; + valid = 1'b0; + instr_req_o = 1'b0; + instr_addr_int = '0; + fetch_valid_o = 1'b0; + //fetch_gnt_int = 1'b0; + //send_rvalid_int = 1'b0; + + case(CS) + + // wait for the first branch request before fetching any instructions + EMPTY: + begin + if (branch_i) + instr_addr_int = branch_addr_i; + else if (hwlp_i) + instr_addr_int = hwlp_addr_i; + else + instr_addr_int = prefetch_addr_i; + + if (branch_i | hwlp_i | prefetch_i) // make the request to icache + begin + instr_req_o = 1'b1; + + if (instr_gnt_i) + NS = WAIT_RVALID; + else + NS = WAIT_GNT; + end + end //~EMPTY + + WAIT_GNT: + begin + if (branch_i) + instr_addr_int = branch_addr_i; + else if (hwlp_i) + instr_addr_int = hwlp_addr_i; + else + instr_addr_int = addr_q; + + if (branch_i) + begin + instr_req_o = 1'b1; + + if (instr_gnt_i) + NS = WAIT_RVALID; + else + NS = WAIT_GNT; + end + else + begin + instr_req_o = 1'b1; + + if (instr_gnt_i) + NS = WAIT_RVALID; + else + NS = WAIT_GNT; + end + end //~WAIT_GNT + + + WAIT_RVALID: + begin + valid = instr_rvalid_i; + + if (branch_i) + instr_addr_int = branch_addr_i; + else if (hwlp_i) + instr_addr_int = hwlp_addr_i; + else + instr_addr_int = prefetch_addr_i; + + if (branch_i) + begin + if (instr_rvalid_i) + begin + fetch_valid_o = 1'b1; + instr_req_o = 1'b1; + + if (instr_gnt_i) + NS = WAIT_RVALID; + else + NS = WAIT_GNT; + end else begin + NS = ABORTED_BRANCH; // TODO: THIS STATE IS IDENTICAL WITH THIS ONE + end + + end + else + begin + + if (instr_rvalid_i) + begin + fetch_valid_o = 1'b1; + + if (prefetch_i | hwlp_i) // we are receiving the last packet, then prefetch the next one + begin + instr_req_o = 1'b1; + + if (instr_gnt_i) + NS = WAIT_RVALID; + else + NS = WAIT_GNT; + end + else // not the last chunk + begin + NS = VALID_L0; + end + end + end + end //~WAIT_RVALID + + VALID_L0: + begin + valid = 1'b1; + //fetch_valid_o = fetch_valid_int; + + if (branch_i) + instr_addr_int = branch_addr_i; + else if (hwlp_i) + instr_addr_int = hwlp_addr_i; + else + instr_addr_int = prefetch_addr_i; + + if (branch_i | hwlp_i | prefetch_i) + begin + + //if(instr_addr_int[31:4] != addr_q[31:4]) + //begin + instr_req_o = 1'b1; + + if (instr_gnt_i) + NS = WAIT_RVALID; + else + NS = WAIT_GNT; + //end + // else + // begin + // // Cache line is already in the L0 BUFFER, NO NEED TO prefetch + // instr_req_o = 1'b0; + // fetch_gnt_int = 1'b1; // Grant the Loop or the prefetcher + // send_rvalid_int = 1'b1; // data is ready! + // NS = VALID_L0; + // end + + end + end //~VALID_L0 + + ABORTED_BRANCH: + begin + + // prepare address even if we don't need it + // this removes the dependency for instr_addr_o on instr_rvalid_i + if (branch_i) + instr_addr_int = branch_addr_i; + else + instr_addr_int = addr_q; + + if (instr_rvalid_i) + begin + instr_req_o = 1'b1; + + if (instr_gnt_i) + NS = WAIT_RVALID; + else + NS = WAIT_GNT; + end + end //~ABORTED_BRANCH + + default: + begin + NS = EMPTY; + end + endcase //~CS + end + + + ////////////////////////////////////////////////////////////////////////////// + // registers + ////////////////////////////////////////////////////////////////////////////// + + always_ff @(posedge clk, negedge rst_n) + begin + if (~rst_n) + begin + CS <= EMPTY; + L0_buffer <= '0; + addr_q <= '0; + //fetch_valid_int <= '0; + end + else + begin + CS <= NS; + + //fetch_valid_int <= send_rvalid_int; + + if (instr_rvalid_i) + begin + L0_buffer <= instr_rdata_i; + end + + if (branch_i | hwlp_i | prefetch_i) + addr_q <= instr_addr_int; + end + end + + + ////////////////////////////////////////////////////////////////////////////// + // output ports + ////////////////////////////////////////////////////////////////////////////// + + assign instr_addr_o = { instr_addr_int[31:4], 4'b0000 }; + + assign rdata_o = (instr_rvalid_i) ? instr_rdata_i : L0_buffer; + assign addr_o = addr_q; + + assign valid_o = valid & (~branch_i); + + assign busy_o = (CS != EMPTY) && (CS != VALID_L0) || instr_req_o; + + assign fetch_gnt_o = instr_gnt_i /*| fetch_gnt_int*/; + +endmodule \ No newline at end of file diff --git a/hw/deps/riscv/riscv_alu.sv b/hw/deps/riscv/riscv_alu.sv new file mode 100644 index 0000000..3ddbdc8 --- /dev/null +++ b/hw/deps/riscv/riscv_alu.sv @@ -0,0 +1,1155 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Matthias Baer - baermatt@student.ethz.ch // +// // +// Additional contributions by: // +// Igor Loi - igor.loi@unibo.it // +// Andreas Traber - atraber@student.ethz.ch // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: ALU // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Arithmetic logic unit of the pipelined processor // +// supports FP-comparisons, classifications if FPU is defined // +// // +//////////////////////////////////////////////////////////////////////////////// + +import riscv_defines::*; + +module riscv_alu +#( + parameter SHARED_INT_DIV = 0, + parameter FPU = 0 +)( + input logic clk, + input logic rst_n, + input logic enable_i, + input logic [ALU_OP_WIDTH-1:0] operator_i, + input logic [31:0] operand_a_i, + input logic [31:0] operand_b_i, + input logic [31:0] operand_c_i, + + input logic [ 1:0] vector_mode_i, + input logic [ 4:0] bmask_a_i, + input logic [ 4:0] bmask_b_i, + input logic [ 1:0] imm_vec_ext_i, + + input logic is_clpx_i, + input logic is_subrot_i, + input logic [ 1:0] clpx_shift_i, + + output logic [31:0] result_o, + output logic comparison_result_o, + + output logic ready_o, + input logic ex_ready_i +); + + + logic [31:0] operand_a_rev; + logic [31:0] operand_a_neg; + logic [31:0] operand_a_neg_rev; + + assign operand_a_neg = ~operand_a_i; + + // bit reverse operand_a for left shifts and bit counting + generate + genvar k; + for(k = 0; k < 32; k++) + begin + assign operand_a_rev[k] = operand_a_i[31-k]; + end + endgenerate + + // bit reverse operand_a_neg for left shifts and bit counting + generate + genvar m; + for(m = 0; m < 32; m++) + begin + assign operand_a_neg_rev[m] = operand_a_neg[31-m]; + end + endgenerate + + logic [31:0] operand_b_neg; + + assign operand_b_neg = ~operand_b_i; + + + logic [5:0] div_shift; + logic div_valid; + logic [31:0] bmask; + + ////////////////////////////////////////////////////////////////////////////////////////// + // ____ _ _ _ _ _ _ _ _ // + // | _ \ __ _ _ __| |_(_) |_(_) ___ _ __ ___ __| | / \ __| | __| | ___ _ __ // + // | |_) / _` | '__| __| | __| |/ _ \| '_ \ / _ \/ _` | / _ \ / _` |/ _` |/ _ \ '__| // + // | __/ (_| | | | |_| | |_| | (_) | | | | __/ (_| | / ___ \ (_| | (_| | __/ | // + // |_| \__,_|_| \__|_|\__|_|\___/|_| |_|\___|\__,_| /_/ \_\__,_|\__,_|\___|_| // + // // + ////////////////////////////////////////////////////////////////////////////////////////// + + logic adder_op_b_negate; + logic [31:0] adder_op_a, adder_op_b; + logic [35:0] adder_in_a, adder_in_b; + logic [31:0] adder_result; + logic [36:0] adder_result_expanded; + + + assign adder_op_b_negate = (operator_i == ALU_SUB) || (operator_i == ALU_SUBR) || + (operator_i == ALU_SUBU) || (operator_i == ALU_SUBUR) || is_subrot_i; + + // prepare operand a + assign adder_op_a = (operator_i == ALU_ABS) ? operand_a_neg : ( is_subrot_i ? {operand_b_i[15:0], operand_a_i[31:16]} : operand_a_i ); + + // prepare operand b + assign adder_op_b = adder_op_b_negate ? ( is_subrot_i ? ~{operand_a_i[15:0], operand_b_i[31:16]} : operand_b_neg ) : operand_b_i; + + // prepare carry + always_comb + begin + adder_in_a[ 0] = 1'b1; + adder_in_a[ 8: 1] = adder_op_a[ 7: 0]; + adder_in_a[ 9] = 1'b1; + adder_in_a[17:10] = adder_op_a[15: 8]; + adder_in_a[ 18] = 1'b1; + adder_in_a[26:19] = adder_op_a[23:16]; + adder_in_a[ 27] = 1'b1; + adder_in_a[35:28] = adder_op_a[31:24]; + + adder_in_b[ 0] = 1'b0; + adder_in_b[ 8: 1] = adder_op_b[ 7: 0]; + adder_in_b[ 9] = 1'b0; + adder_in_b[17:10] = adder_op_b[15: 8]; + adder_in_b[ 18] = 1'b0; + adder_in_b[26:19] = adder_op_b[23:16]; + adder_in_b[ 27] = 1'b0; + adder_in_b[35:28] = adder_op_b[31:24]; + + if (adder_op_b_negate || (operator_i == ALU_ABS || operator_i == ALU_CLIP)) begin + // special case for subtractions and absolute number calculations + adder_in_b[0] = 1'b1; + + case (vector_mode_i) + VEC_MODE16: begin + adder_in_b[18] = 1'b1; + end + + VEC_MODE8: begin + adder_in_b[ 9] = 1'b1; + adder_in_b[18] = 1'b1; + adder_in_b[27] = 1'b1; + end + endcase + + end else begin + // take care of partitioning the adder for the addition case + case (vector_mode_i) + VEC_MODE16: begin + adder_in_a[18] = 1'b0; + end + + VEC_MODE8: begin + adder_in_a[ 9] = 1'b0; + adder_in_a[18] = 1'b0; + adder_in_a[27] = 1'b0; + end + endcase + end + end + + // actual adder + assign adder_result_expanded = $signed(adder_in_a) + $signed(adder_in_b); + assign adder_result = {adder_result_expanded[35:28], + adder_result_expanded[26:19], + adder_result_expanded[17:10], + adder_result_expanded[8:1]}; + + + // normalization stage + logic [31:0] adder_round_value; + logic [31:0] adder_round_result; + + assign adder_round_value = ((operator_i == ALU_ADDR) || (operator_i == ALU_SUBR) || + (operator_i == ALU_ADDUR) || (operator_i == ALU_SUBUR)) ? + {1'b0, bmask[31:1]} : '0; + assign adder_round_result = adder_result + adder_round_value; + + + //////////////////////////////////////// + // ____ _ _ ___ _____ _____ // + // / ___|| | | |_ _| ___|_ _| // + // \___ \| |_| || || |_ | | // + // ___) | _ || || _| | | // + // |____/|_| |_|___|_| |_| // + // // + //////////////////////////////////////// + + logic shift_left; // should we shift left + logic shift_use_round; + logic shift_arithmetic; + + logic [31:0] shift_amt_left; // amount of shift, if to the left + logic [31:0] shift_amt; // amount of shift, to the right + logic [31:0] shift_amt_int; // amount of shift, used for the actual shifters + logic [31:0] shift_amt_norm; // amount of shift, used for normalization + logic [31:0] shift_op_a; // input of the shifter + logic [31:0] shift_result; + logic [31:0] shift_right_result; + logic [31:0] shift_left_result; + logic [15:0] clpx_shift_ex; + + // shifter is also used for preparing operand for division + assign shift_amt = div_valid ? div_shift : operand_b_i; + + // by reversing the bits of the input, we also have to reverse the order of shift amounts + always_comb + begin + case(vector_mode_i) + VEC_MODE16: + begin + shift_amt_left[15: 0] = shift_amt[31:16]; + shift_amt_left[31:16] = shift_amt[15: 0]; + end + + VEC_MODE8: + begin + shift_amt_left[ 7: 0] = shift_amt[31:24]; + shift_amt_left[15: 8] = shift_amt[23:16]; + shift_amt_left[23:16] = shift_amt[15: 8]; + shift_amt_left[31:24] = shift_amt[ 7: 0]; + end + + default: // VEC_MODE32 + begin + shift_amt_left[31: 0] = shift_amt[31: 0]; + end + endcase + end + + // ALU_FL1 and ALU_CBL are used for the bit counting ops later + assign shift_left = (operator_i == ALU_SLL) || (operator_i == ALU_BINS) || + (operator_i == ALU_FL1) || (operator_i == ALU_CLB) || + (operator_i == ALU_DIV) || (operator_i == ALU_DIVU) || + (operator_i == ALU_REM) || (operator_i == ALU_REMU) || + (operator_i == ALU_BREV); + + assign shift_use_round = (operator_i == ALU_ADD) || (operator_i == ALU_SUB) || + (operator_i == ALU_ADDR) || (operator_i == ALU_SUBR) || + (operator_i == ALU_ADDU) || (operator_i == ALU_SUBU) || + (operator_i == ALU_ADDUR) || (operator_i == ALU_SUBUR); + + assign shift_arithmetic = (operator_i == ALU_SRA) || (operator_i == ALU_BEXT) || + (operator_i == ALU_ADD) || (operator_i == ALU_SUB) || + (operator_i == ALU_ADDR) || (operator_i == ALU_SUBR); + + // choose the bit reversed or the normal input for shift operand a + assign shift_op_a = shift_left ? operand_a_rev : + (shift_use_round ? adder_round_result : operand_a_i); + assign shift_amt_int = shift_use_round ? shift_amt_norm : + (shift_left ? shift_amt_left : shift_amt); + + assign shift_amt_norm = is_clpx_i ? {clpx_shift_ex,clpx_shift_ex} : {4{3'b000, bmask_b_i}}; + + assign clpx_shift_ex = $unsigned(clpx_shift_i); + + // right shifts, we let the synthesizer optimize this + logic [63:0] shift_op_a_32; + + assign shift_op_a_32 = (operator_i == ALU_ROR) ? {shift_op_a, shift_op_a} : $signed({ {32{shift_arithmetic & shift_op_a[31]}}, shift_op_a}); + + always_comb + begin + case(vector_mode_i) + VEC_MODE16: + begin + shift_right_result[31:16] = $signed( {shift_arithmetic & shift_op_a[31], shift_op_a[31:16] }) >>> shift_amt_int[19:16]; + shift_right_result[15: 0] = $signed( {shift_arithmetic & shift_op_a[15], shift_op_a[15: 0] }) >>> shift_amt_int[ 3: 0]; + end + + VEC_MODE8: + begin + shift_right_result[31:24] = $signed( {shift_arithmetic & shift_op_a[31], shift_op_a[31:24] }) >>> shift_amt_int[26:24]; + shift_right_result[23:16] = $signed( {shift_arithmetic & shift_op_a[23], shift_op_a[23:16] }) >>> shift_amt_int[18:16]; + shift_right_result[15: 8] = $signed( {shift_arithmetic & shift_op_a[15], shift_op_a[15: 8] }) >>> shift_amt_int[10: 8]; + shift_right_result[ 7: 0] = $signed( {shift_arithmetic & shift_op_a[ 7], shift_op_a[ 7: 0] }) >>> shift_amt_int[ 2: 0]; + end + + default: // VEC_MODE32 + begin + shift_right_result = shift_op_a_32 >> shift_amt_int[4:0]; + end + endcase; // case (vec_mode_i) + end + + // bit reverse the shift_right_result for left shifts + genvar j; + generate + for(j = 0; j < 32; j++) + begin + assign shift_left_result[j] = shift_right_result[31-j]; + end + endgenerate + + assign shift_result = shift_left ? shift_left_result : shift_right_result; + + + ////////////////////////////////////////////////////////////////// + // ____ ___ __ __ ____ _ ____ ___ ____ ___ _ _ // + // / ___/ _ \| \/ | _ \ / \ | _ \|_ _/ ___| / _ \| \ | | // + // | | | | | | |\/| | |_) / _ \ | |_) || |\___ \| | | | \| | // + // | |__| |_| | | | | __/ ___ \| _ < | | ___) | |_| | |\ | // + // \____\___/|_| |_|_| /_/ \_\_| \_\___|____/ \___/|_| \_| // + // // + ////////////////////////////////////////////////////////////////// + + logic [3:0] is_equal; + logic [3:0] is_greater; // handles both signed and unsigned forms + logic [3:0] f_is_greater; // for floats, only signed and *no vectors*, + // inverted for two negative numbers + + // 8-bit vector comparisons, basic building blocks + logic [3:0] cmp_signed; + logic [3:0] is_equal_vec; + logic [3:0] is_greater_vec; + logic [31:0] operand_b_eq; + logic is_equal_clip; + + + //second == comparator for CLIP instructions + always_comb + begin + operand_b_eq = operand_b_neg; + if(operator_i == ALU_CLIPU) + operand_b_eq = '0; + else + operand_b_eq = operand_b_neg; + end + assign is_equal_clip = operand_a_i == operand_b_eq; + + always_comb + begin + cmp_signed = 4'b0; + + unique case (operator_i) + ALU_GTS, + ALU_GES, + ALU_LTS, + ALU_LES, + ALU_SLTS, + ALU_SLETS, + ALU_MIN, + ALU_MAX, + ALU_ABS, + ALU_CLIP, + ALU_CLIPU, + ALU_FLE, + ALU_FLT, + ALU_FMAX, + ALU_FMIN: begin + case (vector_mode_i) + VEC_MODE8: cmp_signed[3:0] = 4'b1111; + VEC_MODE16: cmp_signed[3:0] = 4'b1010; + default: cmp_signed[3:0] = 4'b1000; + endcase + end + + default:; + endcase + end + + // generate vector equal and greater than signals, cmp_signed decides if the + // comparison is done signed or unsigned + genvar i; + generate + for(i = 0; i < 4; i++) + begin + assign is_equal_vec[i] = (operand_a_i[8*i+7:8*i] == operand_b_i[8*i+7:i*8]); + assign is_greater_vec[i] = $signed({operand_a_i[8*i+7] & cmp_signed[i], operand_a_i[8*i+7:8*i]}) + > + $signed({operand_b_i[8*i+7] & cmp_signed[i], operand_b_i[8*i+7:i*8]}); + end + endgenerate + + // generate the real equal and greater than signals that take the vector + // mode into account + always_comb + begin + // 32-bit mode + is_equal[3:0] = {4{is_equal_vec[3] & is_equal_vec[2] & is_equal_vec[1] & is_equal_vec[0]}}; + is_greater[3:0] = {4{is_greater_vec[3] | (is_equal_vec[3] & (is_greater_vec[2] + | (is_equal_vec[2] & (is_greater_vec[1] + | (is_equal_vec[1] & (is_greater_vec[0]))))))}}; + + case(vector_mode_i) + VEC_MODE16: + begin + is_equal[1:0] = {2{is_equal_vec[0] & is_equal_vec[1]}}; + is_equal[3:2] = {2{is_equal_vec[2] & is_equal_vec[3]}}; + is_greater[1:0] = {2{is_greater_vec[1] | (is_equal_vec[1] & is_greater_vec[0])}}; + is_greater[3:2] = {2{is_greater_vec[3] | (is_equal_vec[3] & is_greater_vec[2])}}; + end + + VEC_MODE8: + begin + is_equal[3:0] = is_equal_vec[3:0]; + is_greater[3:0] = is_greater_vec[3:0]; + end + + default:; // see default assignment + endcase + end + + // generate the floating point greater signal, inverted for two negative numbers + // (but not for identical numbers) + assign f_is_greater[3:0] = {4{is_greater[3] ^ (operand_a_i[31] & operand_b_i[31] & !is_equal[3])}}; + + // generate comparison result + logic [3:0] cmp_result; + logic f_is_qnan; + logic f_is_snan; + logic [3:0] f_is_nan; + + always_comb + begin + cmp_result = is_equal; + f_is_nan = {4{(f_is_qnan | f_is_snan)}}; + unique case (operator_i) + ALU_EQ: cmp_result = is_equal; + ALU_NE: cmp_result = ~is_equal; + ALU_GTS, ALU_GTU: cmp_result = is_greater; + ALU_GES, ALU_GEU: cmp_result = is_greater | is_equal; + ALU_LTS, ALU_SLTS, + ALU_LTU, ALU_SLTU: cmp_result = ~(is_greater | is_equal); + ALU_SLETS, + ALU_SLETU, + ALU_LES, ALU_LEU: cmp_result = ~is_greater; + ALU_FEQ: cmp_result = is_equal & ~f_is_nan; + ALU_FLE: cmp_result = ~f_is_greater & ~f_is_nan; + ALU_FLT: cmp_result = ~(f_is_greater | is_equal) & ~f_is_nan; + + default: ; + endcase + end + + assign comparison_result_o = cmp_result[3]; + + + // min/max/abs handling + logic [31:0] result_minmax; + logic [31:0] fp_canonical_nan; + logic [ 3:0] sel_minmax; + logic do_min; + logic minmax_is_fp_special; + logic [31:0] minmax_b; + + assign minmax_b = (operator_i == ALU_ABS) ? adder_result : operand_b_i; + + assign do_min = (operator_i == ALU_MIN) || (operator_i == ALU_MINU) || + (operator_i == ALU_CLIP) || (operator_i == ALU_CLIPU) || + (operator_i == ALU_FMIN); + + assign sel_minmax[3:0] = ((operator_i == ALU_FMIN || operator_i == ALU_FMAX) ? f_is_greater : is_greater) ^ {4{do_min}}; + + assign result_minmax[31:24] = (sel_minmax[3] == 1'b1) ? operand_a_i[31:24] : minmax_b[31:24]; + assign result_minmax[23:16] = (sel_minmax[2] == 1'b1) ? operand_a_i[23:16] : minmax_b[23:16]; + assign result_minmax[15: 8] = (sel_minmax[1] == 1'b1) ? operand_a_i[15: 8] : minmax_b[15: 8]; + assign result_minmax[ 7: 0] = (sel_minmax[0] == 1'b1) ? operand_a_i[ 7: 0] : minmax_b[ 7: 0]; + + ////////////////////////////////////////////////// + // Float classification + ////////////////////////////////////////////////// + logic [31:0] fclass_result; + + if (FPU == 1) begin + logic [7:0] fclass_exponent; + logic [22:0] fclass_mantiassa; + logic fclass_ninf; + logic fclass_pinf; + logic fclass_normal; + logic fclass_subnormal; + logic fclass_nzero; + logic fclass_pzero; + logic fclass_is_negative; + logic fclass_snan_a; + logic fclass_qnan_a; + logic fclass_snan_b; + logic fclass_qnan_b; + + assign fclass_exponent = operand_a_i[30:23]; + assign fclass_mantiassa = operand_a_i[22:0]; + assign fclass_is_negative = operand_a_i[31]; + + assign fclass_ninf = operand_a_i == 32'hFF800000; + assign fclass_pinf = operand_a_i == 32'h7F800000; + assign fclass_normal = fclass_exponent != 0 && fclass_exponent != 255; + assign fclass_subnormal = fclass_exponent == 0 && fclass_mantiassa != 0; + assign fclass_nzero = operand_a_i == 32'h80000000; + assign fclass_pzero = operand_a_i == 32'h00000000; + assign fclass_snan_a = operand_a_i[30:0] == 32'h7fa00000; + assign fclass_qnan_a = operand_a_i[30:0] == 32'h7fc00000; + assign fclass_snan_b = operand_b_i[30:0] == 32'h7fa00000; + assign fclass_qnan_b = operand_b_i[30:0] == 32'h7fc00000; + + assign fclass_result[31:0] = {{22{1'b0}}, + fclass_qnan_a, + fclass_snan_a, + fclass_pinf, + (fclass_normal && !fclass_is_negative), + (fclass_subnormal && !fclass_is_negative), + fclass_pzero, + fclass_nzero, + (fclass_subnormal && fclass_is_negative), + (fclass_normal && fclass_is_negative), + fclass_ninf}; + + + // float special cases + assign f_is_qnan = fclass_qnan_a | fclass_qnan_b; + assign f_is_snan = fclass_snan_a | fclass_snan_b; + + assign minmax_is_fp_special = (operator_i == ALU_FMIN || operator_i == ALU_FMAX) & (f_is_snan | f_is_qnan); + assign fp_canonical_nan = 32'h7fc00000; + end else begin // (FPU == 0) + assign minmax_is_fp_special = '0; + assign f_is_qnan = '0; + assign f_is_snan = '0; + assign fclass_result = '0; + assign fp_canonical_nan = '0; + end + + + ////////////////////////////////////////////////// + // Float sign injection + ////////////////////////////////////////////////// + logic [31:0] f_sign_inject_result; + + + always_comb + begin + if (FPU == 1) begin + f_sign_inject_result[30:0] = operand_a_i[30:0]; + f_sign_inject_result[31] = operand_a_i[31]; + + unique case(operator_i) + ALU_FKEEP: f_sign_inject_result[31] = operand_a_i[31]; + ALU_FSGNJ: f_sign_inject_result[31] = operand_b_i[31]; + ALU_FSGNJN: f_sign_inject_result[31] = !operand_b_i[31]; + ALU_FSGNJX: f_sign_inject_result[31] = operand_a_i[31] ^ operand_b_i[31]; + default: ; + endcase + end + else + f_sign_inject_result = '0; + end + + ////////////////////////////////////////////////// + // Clip + ////////////////////////////////////////////////// + logic [31:0] clip_result; // result of clip and clip + + always_comb + begin + clip_result = result_minmax; + if(operator_i == ALU_CLIPU) begin + if(operand_a_i[31] || is_equal_clip) begin + clip_result = '0; + end else begin + clip_result = result_minmax; + end + end else begin + //CLIP + if(adder_result_expanded[36] || is_equal_clip) begin + clip_result = operand_b_neg; + end else begin + clip_result = result_minmax; + end + end + + end + + ////////////////////////////////////////////////// + // ____ _ _ _ _ _____ _____ _ _____ // + // / ___|| | | | | | | ___| ___| | | ____| // + // \___ \| |_| | | | | |_ | |_ | | | _| // + // ___) | _ | |_| | _| | _| | |___| |___ // + // |____/|_| |_|\___/|_| |_| |_____|_____| // + // // + ////////////////////////////////////////////////// + + logic [ 3: 0][1:0] shuffle_byte_sel; // select byte in register: 31:24, 23:16, 15:8, 7:0 + logic [ 3: 0] shuffle_reg_sel; // select register: rD/rS2 or rS1 + logic [ 1: 0] shuffle_reg1_sel; // select register rD or rS2 for next stage + logic [ 1: 0] shuffle_reg0_sel; + logic [ 3: 0] shuffle_through; + + logic [31: 0] shuffle_r1, shuffle_r0; + logic [31: 0] shuffle_r1_in, shuffle_r0_in; + logic [31: 0] shuffle_result; + logic [31: 0] pack_result; + + + always_comb + begin + shuffle_reg_sel = '0; + shuffle_reg1_sel = 2'b01; + shuffle_reg0_sel = 2'b10; + shuffle_through = '1; + + unique case(operator_i) + ALU_EXT, ALU_EXTS: begin + if (operator_i == ALU_EXTS) + shuffle_reg1_sel = 2'b11; + + if (vector_mode_i == VEC_MODE8) begin + shuffle_reg_sel[3:1] = 3'b111; + shuffle_reg_sel[0] = 1'b0; + end else begin + shuffle_reg_sel[3:2] = 2'b11; + shuffle_reg_sel[1:0] = 2'b00; + end + end + + ALU_PCKLO: begin + shuffle_reg1_sel = 2'b00; + + if (vector_mode_i == VEC_MODE8) begin + shuffle_through = 4'b0011; + shuffle_reg_sel = 4'b0001; + end else begin + shuffle_reg_sel = 4'b0011; + end + end + + ALU_PCKHI: begin + shuffle_reg1_sel = 2'b00; + + if (vector_mode_i == VEC_MODE8) begin + shuffle_through = 4'b1100; + shuffle_reg_sel = 4'b0100; + end else begin + shuffle_reg_sel = 4'b0011; + end + end + + ALU_SHUF2: begin + unique case (vector_mode_i) + VEC_MODE8: begin + shuffle_reg_sel[3] = ~operand_b_i[26]; + shuffle_reg_sel[2] = ~operand_b_i[18]; + shuffle_reg_sel[1] = ~operand_b_i[10]; + shuffle_reg_sel[0] = ~operand_b_i[ 2]; + end + + VEC_MODE16: begin + shuffle_reg_sel[3] = ~operand_b_i[17]; + shuffle_reg_sel[2] = ~operand_b_i[17]; + shuffle_reg_sel[1] = ~operand_b_i[ 1]; + shuffle_reg_sel[0] = ~operand_b_i[ 1]; + end + default:; + endcase + end + + ALU_INS: begin + unique case (vector_mode_i) + VEC_MODE8: begin + shuffle_reg0_sel = 2'b00; + unique case (imm_vec_ext_i) + 2'b00: begin + shuffle_reg_sel[3:0] = 4'b1110; + end + 2'b01: begin + shuffle_reg_sel[3:0] = 4'b1101; + end + 2'b10: begin + shuffle_reg_sel[3:0] = 4'b1011; + end + 2'b11: begin + shuffle_reg_sel[3:0] = 4'b0111; + end + default:; + endcase + end + VEC_MODE16: begin + shuffle_reg0_sel = 2'b01; + shuffle_reg_sel[3] = ~imm_vec_ext_i[ 0]; + shuffle_reg_sel[2] = ~imm_vec_ext_i[ 0]; + shuffle_reg_sel[1] = imm_vec_ext_i[ 0]; + shuffle_reg_sel[0] = imm_vec_ext_i[ 0]; + end + default:; + endcase + end + + default:; + endcase + end + + always_comb + begin + shuffle_byte_sel = '0; + + // byte selector + unique case (operator_i) + ALU_EXTS, + ALU_EXT: begin + unique case (vector_mode_i) + VEC_MODE8: begin + shuffle_byte_sel[3] = imm_vec_ext_i[1:0]; + shuffle_byte_sel[2] = imm_vec_ext_i[1:0]; + shuffle_byte_sel[1] = imm_vec_ext_i[1:0]; + shuffle_byte_sel[0] = imm_vec_ext_i[1:0]; + end + + VEC_MODE16: begin + shuffle_byte_sel[3] = {imm_vec_ext_i[0], 1'b1}; + shuffle_byte_sel[2] = {imm_vec_ext_i[0], 1'b1}; + shuffle_byte_sel[1] = {imm_vec_ext_i[0], 1'b1}; + shuffle_byte_sel[0] = {imm_vec_ext_i[0], 1'b0}; + end + + default:; + endcase + end + + ALU_PCKLO: begin + unique case (vector_mode_i) + VEC_MODE8: begin + shuffle_byte_sel[3] = 2'b00; + shuffle_byte_sel[2] = 2'b00; + shuffle_byte_sel[1] = 2'b00; + shuffle_byte_sel[0] = 2'b00; + end + + VEC_MODE16: begin + shuffle_byte_sel[3] = 2'b01; + shuffle_byte_sel[2] = 2'b00; + shuffle_byte_sel[1] = 2'b01; + shuffle_byte_sel[0] = 2'b00; + end + + default:; + endcase + end + + ALU_PCKHI: begin + unique case (vector_mode_i) + VEC_MODE8: begin + shuffle_byte_sel[3] = 2'b00; + shuffle_byte_sel[2] = 2'b00; + shuffle_byte_sel[1] = 2'b00; + shuffle_byte_sel[0] = 2'b00; + end + + VEC_MODE16: begin + shuffle_byte_sel[3] = 2'b11; + shuffle_byte_sel[2] = 2'b10; + shuffle_byte_sel[1] = 2'b11; + shuffle_byte_sel[0] = 2'b10; + end + + default:; + endcase + end + + ALU_SHUF2, + ALU_SHUF: begin + unique case (vector_mode_i) + VEC_MODE8: begin + shuffle_byte_sel[3] = operand_b_i[25:24]; + shuffle_byte_sel[2] = operand_b_i[17:16]; + shuffle_byte_sel[1] = operand_b_i[ 9: 8]; + shuffle_byte_sel[0] = operand_b_i[ 1: 0]; + end + + VEC_MODE16: begin + shuffle_byte_sel[3] = {operand_b_i[16], 1'b1}; + shuffle_byte_sel[2] = {operand_b_i[16], 1'b0}; + shuffle_byte_sel[1] = {operand_b_i[ 0], 1'b1}; + shuffle_byte_sel[0] = {operand_b_i[ 0], 1'b0}; + end + default:; + endcase + end + + ALU_INS: begin + shuffle_byte_sel[3] = 2'b11; + shuffle_byte_sel[2] = 2'b10; + shuffle_byte_sel[1] = 2'b01; + shuffle_byte_sel[0] = 2'b00; + end + + default:; + endcase + end + + assign shuffle_r0_in = shuffle_reg0_sel[1] ? + operand_a_i : + (shuffle_reg0_sel[0] ? {2{operand_a_i[15:0]}} : {4{operand_a_i[7:0]}}); + + assign shuffle_r1_in = shuffle_reg1_sel[1] ? + {{8{operand_a_i[31]}}, {8{operand_a_i[23]}}, {8{operand_a_i[15]}}, {8{operand_a_i[7]}}} : + (shuffle_reg1_sel[0] ? operand_c_i : operand_b_i); + + assign shuffle_r0[31:24] = shuffle_byte_sel[3][1] ? + (shuffle_byte_sel[3][0] ? shuffle_r0_in[31:24] : shuffle_r0_in[23:16]) : + (shuffle_byte_sel[3][0] ? shuffle_r0_in[15: 8] : shuffle_r0_in[ 7: 0]); + assign shuffle_r0[23:16] = shuffle_byte_sel[2][1] ? + (shuffle_byte_sel[2][0] ? shuffle_r0_in[31:24] : shuffle_r0_in[23:16]) : + (shuffle_byte_sel[2][0] ? shuffle_r0_in[15: 8] : shuffle_r0_in[ 7: 0]); + assign shuffle_r0[15: 8] = shuffle_byte_sel[1][1] ? + (shuffle_byte_sel[1][0] ? shuffle_r0_in[31:24] : shuffle_r0_in[23:16]) : + (shuffle_byte_sel[1][0] ? shuffle_r0_in[15: 8] : shuffle_r0_in[ 7: 0]); + assign shuffle_r0[ 7: 0] = shuffle_byte_sel[0][1] ? + (shuffle_byte_sel[0][0] ? shuffle_r0_in[31:24] : shuffle_r0_in[23:16]) : + (shuffle_byte_sel[0][0] ? shuffle_r0_in[15: 8] : shuffle_r0_in[ 7: 0]); + + assign shuffle_r1[31:24] = shuffle_byte_sel[3][1] ? + (shuffle_byte_sel[3][0] ? shuffle_r1_in[31:24] : shuffle_r1_in[23:16]) : + (shuffle_byte_sel[3][0] ? shuffle_r1_in[15: 8] : shuffle_r1_in[ 7: 0]); + assign shuffle_r1[23:16] = shuffle_byte_sel[2][1] ? + (shuffle_byte_sel[2][0] ? shuffle_r1_in[31:24] : shuffle_r1_in[23:16]) : + (shuffle_byte_sel[2][0] ? shuffle_r1_in[15: 8] : shuffle_r1_in[ 7: 0]); + assign shuffle_r1[15: 8] = shuffle_byte_sel[1][1] ? + (shuffle_byte_sel[1][0] ? shuffle_r1_in[31:24] : shuffle_r1_in[23:16]) : + (shuffle_byte_sel[1][0] ? shuffle_r1_in[15: 8] : shuffle_r1_in[ 7: 0]); + assign shuffle_r1[ 7: 0] = shuffle_byte_sel[0][1] ? + (shuffle_byte_sel[0][0] ? shuffle_r1_in[31:24] : shuffle_r1_in[23:16]) : + (shuffle_byte_sel[0][0] ? shuffle_r1_in[15: 8] : shuffle_r1_in[ 7: 0]); + + assign shuffle_result[31:24] = shuffle_reg_sel[3] ? shuffle_r1[31:24] : shuffle_r0[31:24]; + assign shuffle_result[23:16] = shuffle_reg_sel[2] ? shuffle_r1[23:16] : shuffle_r0[23:16]; + assign shuffle_result[15: 8] = shuffle_reg_sel[1] ? shuffle_r1[15: 8] : shuffle_r0[15: 8]; + assign shuffle_result[ 7: 0] = shuffle_reg_sel[0] ? shuffle_r1[ 7: 0] : shuffle_r0[ 7: 0]; + + assign pack_result[31:24] = shuffle_through[3] ? shuffle_result[31:24] : operand_c_i[31:24]; + assign pack_result[23:16] = shuffle_through[2] ? shuffle_result[23:16] : operand_c_i[23:16]; + assign pack_result[15: 8] = shuffle_through[1] ? shuffle_result[15: 8] : operand_c_i[15: 8]; + assign pack_result[ 7: 0] = shuffle_through[0] ? shuffle_result[ 7: 0] : operand_c_i[ 7: 0]; + + + ///////////////////////////////////////////////////////////////////// + // ____ _ _ ____ _ ___ // + // | __ )(_) |_ / ___|___ _ _ _ __ | |_ / _ \ _ __ ___ // + // | _ \| | __| | | / _ \| | | | '_ \| __| | | | | '_ \/ __| // + // | |_) | | |_ | |__| (_) | |_| | | | | |_ | |_| | |_) \__ \_ // + // |____/|_|\__| \____\___/ \__,_|_| |_|\__| \___/| .__/|___(_) // + // |_| // + ///////////////////////////////////////////////////////////////////// + + logic [31:0] ff_input; // either op_a_i or its bit reversed version + logic [5:0] cnt_result; // population count + logic [5:0] clb_result; // count leading bits + logic [4:0] ff1_result; // holds the index of the first '1' + logic ff_no_one; // if no ones are found + logic [4:0] fl1_result; // holds the index of the last '1' + logic [5:0] bitop_result; // result of all bitop operations muxed together + + riscv_popcnt alu_popcnt_i + ( + .in_i ( operand_a_i ), + .result_o ( cnt_result ) + ); + + always_comb + begin + ff_input = '0; + + case (operator_i) + ALU_FF1: ff_input = operand_a_i; + + ALU_DIVU, + ALU_REMU, + ALU_FL1: ff_input = operand_a_rev; + + ALU_DIV, + ALU_REM, + ALU_CLB: begin + if (operand_a_i[31]) + ff_input = operand_a_neg_rev; + else + ff_input = operand_a_rev; + end + endcase + end + + riscv_ff_one alu_ff_i + ( + .in_i ( ff_input ), + .first_one_o ( ff1_result ), + .no_ones_o ( ff_no_one ) + ); + + // special case if ff1_res is 0 (no 1 found), then we keep the 0 + // this is done in the result mux + assign fl1_result = 5'd31 - ff1_result; + assign clb_result = ff1_result - 5'd1; + + always_comb + begin + bitop_result = '0; + case (operator_i) + ALU_FF1: bitop_result = ff_no_one ? 6'd32 : {1'b0, ff1_result}; + ALU_FL1: bitop_result = ff_no_one ? 6'd32 : {1'b0, fl1_result}; + ALU_CNT: bitop_result = cnt_result; + ALU_CLB: begin + if (ff_no_one) begin + if (operand_a_i[31]) + bitop_result = 6'd31; + else + bitop_result = '0; + end else begin + bitop_result = clb_result; + end + end + default:; + endcase + end + + + //////////////////////////////////////////////// + // ____ _ _ __ __ _ // + // | __ )(_) |_ | \/ | __ _ _ __ (_)_ __ // + // | _ \| | __| | |\/| |/ _` | '_ \| | '_ \ // + // | |_) | | |_ | | | | (_| | | | | | |_) | // + // |____/|_|\__| |_| |_|\__,_|_| |_|_| .__/ // + // |_| // + //////////////////////////////////////////////// + + logic extract_is_signed; + logic extract_sign; + logic [31:0] bmask_first, bmask_inv; + logic [31:0] bextins_and; + logic [31:0] bextins_result, bclr_result, bset_result; + + + // construct bit mask for insert/extract/bclr/bset + // bmask looks like this 00..0011..1100..00 + assign bmask_first = {32'hFFFFFFFE} << bmask_a_i; + assign bmask = (~bmask_first) << bmask_b_i; + assign bmask_inv = ~bmask; + + assign bextins_and = (operator_i == ALU_BINS) ? operand_c_i : {32{extract_sign}}; + + assign extract_is_signed = (operator_i == ALU_BEXT); + assign extract_sign = extract_is_signed & shift_result[bmask_a_i]; + + assign bextins_result = (bmask & shift_result) | (bextins_and & bmask_inv); + + assign bclr_result = operand_a_i & bmask_inv; + assign bset_result = operand_a_i | bmask; + + ///////////////////////////////////////////////////////////////////////////////// + // ____ _____ _______ _____ ________ ________ _____ _____ ______ // + // | _ \_ _|__ __| | __ \| ____\ \ / / ____| __ \ / ____| ____| // + // | |_) || | | |______| |__) | |__ \ \ / /| |__ | |__) | (___ | |__ // + // | _ < | | | |______| _ /| __| \ \/ / | __| | _ / \___ \| __| // + // | |_) || |_ | | | | \ \| |____ \ / | |____| | \ \ ____) | |____ // + // |____/_____| |_| |_| \_\______| \/ |______|_| \_\_____/|______| // + // // + ///////////////////////////////////////////////////////////////////////////////// + + logic [31:0] radix_2_rev; + logic [31:0] radix_4_rev; + logic [31:0] radix_8_rev; + logic [31:0] reverse_result; + logic [1:0] radix_mux_sel; + + assign radix_mux_sel = bmask_a_i[1:0]; + + generate + // radix-2 bit reverse + for(j = 0; j < 32; j++) + begin + assign radix_2_rev[j] = shift_result[31-j]; + end + // radix-4 bit reverse + for(j = 0; j < 16; j++) + begin + assign radix_4_rev[2*j+1:2*j] = shift_result[31-j*2:31-j*2-1]; + end + // radix-8 bit reverse + for(j = 0; j < 10; j++) + begin + assign radix_8_rev[3*j+2:3*j] = shift_result[31-j*3:31-j*3-2]; + end + assign radix_8_rev[31:30] = 2'b0; + endgenerate + + always_comb + begin + reverse_result = '0; + + unique case (radix_mux_sel) + 2'b00: reverse_result = radix_2_rev; + 2'b01: reverse_result = radix_4_rev; + 2'b10: reverse_result = radix_8_rev; + + default: reverse_result = radix_2_rev; + endcase + end + + //////////////////////////////////////////////////// + // ____ _____ __ __ ____ _____ __ __ // + // | _ \_ _\ \ / / / / | _ \| ____| \/ | // + // | | | | | \ \ / / / / | |_) | _| | |\/| | // + // | |_| | | \ V / / / | _ <| |___| | | | // + // |____/___| \_/ /_/ |_| \_\_____|_| |_| // + // // + //////////////////////////////////////////////////// + + logic [31:0] result_div; + logic div_ready; + + if (SHARED_INT_DIV == 1) begin + + assign result_div = '0; + assign div_ready = '1; + assign div_valid = '0; + + end else begin : int_div + + logic div_signed; + logic div_op_a_signed; + logic div_op_b_signed; + logic [5:0] div_shift_int; + + assign div_signed = operator_i[0]; + + assign div_op_a_signed = operand_a_i[31] & div_signed; + assign div_op_b_signed = operand_b_i[31] & div_signed; + + assign div_shift_int = ff_no_one ? 6'd31 : clb_result; + assign div_shift = div_shift_int + (div_op_a_signed ? 6'd0 : 6'd1); + + assign div_valid = enable_i & ((operator_i == ALU_DIV) || (operator_i == ALU_DIVU) || + (operator_i == ALU_REM) || (operator_i == ALU_REMU)); + + + // inputs A and B are swapped + riscv_alu_div div_i + ( + .Clk_CI ( clk ), + .Rst_RBI ( rst_n ), + + // input IF + .OpA_DI ( operand_b_i ), + .OpB_DI ( shift_left_result ), + .OpBShift_DI ( div_shift ), + .OpBIsZero_SI ( (cnt_result == 0) ), + + .OpBSign_SI ( div_op_a_signed ), + .OpCode_SI ( operator_i[1:0] ), + + .Res_DO ( result_div ), + + // Hand-Shake + .InVld_SI ( div_valid ), + .OutRdy_SI ( ex_ready_i ), + .OutVld_SO ( div_ready ) + ); + end + + //////////////////////////////////////////////////////// + // ____ _ _ __ __ // + // | _ \ ___ ___ _ _| | |_ | \/ |_ ___ __ // + // | |_) / _ \/ __| | | | | __| | |\/| | | | \ \/ / // + // | _ < __/\__ \ |_| | | |_ | | | | |_| |> < // + // |_| \_\___||___/\__,_|_|\__| |_| |_|\__,_/_/\_\ // + // // + //////////////////////////////////////////////////////// + + always_comb + begin + result_o = '0; + + unique case (operator_i) + // Standard Operations + ALU_AND: result_o = operand_a_i & operand_b_i; + ALU_OR: result_o = operand_a_i | operand_b_i; + ALU_XOR: result_o = operand_a_i ^ operand_b_i; + + // Shift Operations + ALU_ADD, ALU_ADDR, ALU_ADDU, ALU_ADDUR, + ALU_SUB, ALU_SUBR, ALU_SUBU, ALU_SUBUR, + ALU_SLL, + ALU_SRL, ALU_SRA, + ALU_ROR: result_o = shift_result; + + // bit manipulation instructions + ALU_BINS, + ALU_BEXT, + ALU_BEXTU: result_o = bextins_result; + + ALU_BCLR: result_o = bclr_result; + ALU_BSET: result_o = bset_result; + + // Bit reverse instruction + ALU_BREV: result_o = reverse_result; + + // pack and shuffle operations + ALU_SHUF, ALU_SHUF2, + ALU_PCKLO, ALU_PCKHI, + ALU_EXT, ALU_EXTS, + ALU_INS: result_o = pack_result; + + // Min/Max/Ins + ALU_MIN, ALU_MINU, + ALU_MAX, ALU_MAXU, + ALU_FMIN, + ALU_FMAX: result_o = minmax_is_fp_special ? fp_canonical_nan : result_minmax; + + //Abs/Cplxconj , ABS is used to do 0 - A for Cplxconj + ALU_ABS: result_o = is_clpx_i ? {adder_result[31:16], operand_a_i[15:0]} : result_minmax; + + ALU_CLIP, ALU_CLIPU: result_o = clip_result; + + // Comparison Operations + ALU_EQ, ALU_NE, + ALU_GTU, ALU_GEU, + ALU_LTU, ALU_LEU, + ALU_GTS, ALU_GES, + ALU_LTS, ALU_LES: begin + result_o[31:24] = {8{cmp_result[3]}}; + result_o[23:16] = {8{cmp_result[2]}}; + result_o[15: 8] = {8{cmp_result[1]}}; + result_o[ 7: 0] = {8{cmp_result[0]}}; + end + // Non-vector comparisons + ALU_FEQ, ALU_FLT, + ALU_FLE, + ALU_SLTS, ALU_SLTU, + ALU_SLETS, ALU_SLETU: result_o = {31'b0, comparison_result_o}; + + ALU_FF1, ALU_FL1, ALU_CLB, ALU_CNT: result_o = {26'h0, bitop_result[5:0]}; + + // Division Unit Commands + ALU_DIV, ALU_DIVU, + ALU_REM, ALU_REMU: result_o = result_div; + + // fclass + ALU_FCLASS: result_o = fclass_result; + + // float sign injection + ALU_FSGNJ, ALU_FSGNJN, + ALU_FSGNJX, ALU_FKEEP: result_o = f_sign_inject_result; + + default: ; // default case to suppress unique warning + endcase + end + + assign ready_o = div_ready; + +endmodule diff --git a/hw/deps/riscv/riscv_alu_div.sv b/hw/deps/riscv/riscv_alu_div.sv new file mode 100644 index 0000000..6fc49f9 --- /dev/null +++ b/hw/deps/riscv/riscv_alu_div.sv @@ -0,0 +1,216 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/////////////////////////////////////////////////////////////////////////////// +// File : Simple Serial Divider +// Ver : 1.0 +// Date : 15.03.2016 +/////////////////////////////////////////////////////////////////////////////// +// +// Description: this is a simple serial divider for signed integers (int32). +// +/////////////////////////////////////////////////////////////////////////////// +// +// Authors : Michael Schaffner (schaffner@iis.ee.ethz.ch) +// Andreas Traber (atraber@iis.ee.ethz.ch) +// +/////////////////////////////////////////////////////////////////////////////// + +module riscv_alu_div +#( + parameter C_WIDTH = 32, + parameter C_LOG_WIDTH = 6 +) +( + input logic Clk_CI, + input logic Rst_RBI, + // input IF + input logic [C_WIDTH-1:0] OpA_DI, + input logic [C_WIDTH-1:0] OpB_DI, + input logic [C_LOG_WIDTH-1:0] OpBShift_DI, + input logic OpBIsZero_SI, + // + input logic OpBSign_SI, // gate this to 0 in case of unsigned ops + input logic [1:0] OpCode_SI, // 0: udiv, 2: urem, 1: div, 3: rem + // handshake + input logic InVld_SI, + // output IF + input logic OutRdy_SI, + output logic OutVld_SO, + output logic [C_WIDTH-1:0] Res_DO + ); + + /////////////////////////////////////////////////////////////////////////////// + // signal declarations + /////////////////////////////////////////////////////////////////////////////// + + logic [C_WIDTH-1:0] ResReg_DP, ResReg_DN; + logic [C_WIDTH-1:0] ResReg_DP_rev; + logic [C_WIDTH-1:0] AReg_DP, AReg_DN; + logic [C_WIDTH-1:0] BReg_DP, BReg_DN; + + logic RemSel_SN, RemSel_SP; + logic CompInv_SN, CompInv_SP; + logic ResInv_SN, ResInv_SP; + + logic [C_WIDTH-1:0] AddMux_D; + logic [C_WIDTH-1:0] AddOut_D; + logic [C_WIDTH-1:0] AddTmp_D; + logic [C_WIDTH-1:0] BMux_D; + logic [C_WIDTH-1:0] OutMux_D; + + logic [C_LOG_WIDTH-1:0] Cnt_DP, Cnt_DN; + logic CntZero_S; + + logic ARegEn_S, BRegEn_S, ResRegEn_S, ABComp_S, PmSel_S, LoadEn_S; + + enum logic [1:0] {IDLE, DIVIDE, FINISH} State_SN, State_SP; + + + /////////////////////////////////////////////////////////////////////////////// + // datapath + /////////////////////////////////////////////////////////////////////////////// + + assign PmSel_S = LoadEn_S & ~(OpCode_SI[0] & (OpA_DI[$high(OpA_DI)] ^ OpBSign_SI)); + + // muxes + assign AddMux_D = (LoadEn_S) ? OpA_DI : BReg_DP; + + // attention: logical shift in case of negative operand B! + assign BMux_D = (LoadEn_S) ? OpB_DI : {CompInv_SP, (BReg_DP[$high(BReg_DP):1])}; + + assign ResReg_DP_rev = {<<{ResReg_DP}}; + assign OutMux_D = (RemSel_SP) ? AReg_DP : ResReg_DP_rev; + + // invert if necessary + assign Res_DO = (ResInv_SP) ? -$signed(OutMux_D) : OutMux_D; + + // main comparator + assign ABComp_S = ((AReg_DP == BReg_DP) | ((AReg_DP > BReg_DP) ^ CompInv_SP)) & ((|AReg_DP) | OpBIsZero_SI); + + // main adder + assign AddTmp_D = (LoadEn_S) ? 0 : AReg_DP; + assign AddOut_D = (PmSel_S) ? AddTmp_D + AddMux_D : AddTmp_D - $signed(AddMux_D); + + /////////////////////////////////////////////////////////////////////////////// + // counter + /////////////////////////////////////////////////////////////////////////////// + + assign Cnt_DN = (LoadEn_S) ? OpBShift_DI : + (~CntZero_S) ? Cnt_DP - 1 : Cnt_DP; + + assign CntZero_S = ~(|Cnt_DP); + + /////////////////////////////////////////////////////////////////////////////// + // FSM + /////////////////////////////////////////////////////////////////////////////// + + always_comb + begin : p_fsm + // default + State_SN = State_SP; + + OutVld_SO = 1'b0; + + LoadEn_S = 1'b0; + + ARegEn_S = 1'b0; + BRegEn_S = 1'b0; + ResRegEn_S = 1'b0; + + case (State_SP) + ///////////////////////////////// + IDLE: begin + OutVld_SO = 1'b1; + + if(InVld_SI) begin + OutVld_SO = 1'b0; + ARegEn_S = 1'b1; + BRegEn_S = 1'b1; + LoadEn_S = 1'b1; + State_SN = DIVIDE; + end + end + ///////////////////////////////// + DIVIDE: begin + + ARegEn_S = ABComp_S; + BRegEn_S = 1'b1; + ResRegEn_S = 1'b1; + + // calculation finished + // one more divide cycle (32nd divide cycle) + if (CntZero_S) begin + State_SN = FINISH; + end + end + ///////////////////////////////// + FINISH: begin + OutVld_SO = 1'b1; + + if(OutRdy_SI) begin + State_SN = IDLE; + end + end + ///////////////////////////////// + default : /* default */ ; + ///////////////////////////////// + endcase + end + + + /////////////////////////////////////////////////////////////////////////////// + // regs + /////////////////////////////////////////////////////////////////////////////// + + // get flags + assign RemSel_SN = (LoadEn_S) ? OpCode_SI[1] : RemSel_SP; + assign CompInv_SN = (LoadEn_S) ? OpBSign_SI : CompInv_SP; + assign ResInv_SN = (LoadEn_S) ? (~OpBIsZero_SI | OpCode_SI[1]) & OpCode_SI[0] & (OpA_DI[$high(OpA_DI)] ^ OpBSign_SI) : ResInv_SP; + + assign AReg_DN = (ARegEn_S) ? AddOut_D : AReg_DP; + assign BReg_DN = (BRegEn_S) ? BMux_D : BReg_DP; + assign ResReg_DN = (LoadEn_S) ? '0 : + (ResRegEn_S) ? {ABComp_S, ResReg_DP[$high(ResReg_DP):1]} : ResReg_DP; + + always_ff @(posedge Clk_CI or negedge Rst_RBI) begin : p_regs + if(~Rst_RBI) begin + State_SP <= IDLE; + AReg_DP <= '0; + BReg_DP <= '0; + ResReg_DP <= '0; + Cnt_DP <= '0; + RemSel_SP <= 1'b0; + CompInv_SP <= 1'b0; + ResInv_SP <= 1'b0; + end else begin + State_SP <= State_SN; + AReg_DP <= AReg_DN; + BReg_DP <= BReg_DN; + ResReg_DP <= ResReg_DN; + Cnt_DP <= Cnt_DN; + RemSel_SP <= RemSel_SN; + CompInv_SP <= CompInv_SN; + ResInv_SP <= ResInv_SN; + end + end + + /////////////////////////////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////////////////////////////// + +`ifndef SYNTHESIS + initial + begin : p_assertions + assert (C_LOG_WIDTH == $clog2(C_WIDTH+1)) else $error("C_LOG_WIDTH must be $clog2(C_WIDTH+1)"); + end +`endif + +endmodule // serDiv diff --git a/hw/deps/riscv/riscv_apu_disp.sv b/hw/deps/riscv/riscv_apu_disp.sv new file mode 100644 index 0000000..b1ee545 --- /dev/null +++ b/hw/deps/riscv/riscv_apu_disp.sv @@ -0,0 +1,248 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Lukas Mueller - lukasmue@student.ethz.ch // +// // +// Additional contributions by: // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// // +// Design Name: Simple APU dispatcher // +// Project Name: PULP // +// Language: SystemVerilog // +// // +// Description: Dispatcher for sending instructions to the Marx // +// interconnect. // +//////////////////////////////////////////////////////////////////////////////// + +`include "apu_macros.sv" + +module riscv_apu_disp ( + input logic clk_i, + input logic rst_ni, + + // request input + input logic enable_i, + input logic [1:0] apu_lat_i, + input logic [5:0] apu_waddr_i, + + // response output + output logic [5:0] apu_waddr_o, + output logic apu_multicycle_o, + output logic apu_singlecycle_o, + + // active signal + output logic active_o, + + // stall signals + output logic stall_o, + + // dependency checks + input logic [2:0][5:0] read_regs_i, + input logic [2:0] read_regs_valid_i, + output logic read_dep_o, + + input logic [1:0][5:0] write_regs_i, + input logic [1:0] write_regs_valid_i, + output logic write_dep_o, + + // perf counter stuff + output logic perf_type_o, + output logic perf_cont_o, + + // apu-interconnect + // handshake signals + output logic apu_master_req_o, + output logic apu_master_ready_o, + input logic apu_master_gnt_i, + // response channel + input logic apu_master_valid_i + + ); + + logic [5:0] addr_req, addr_inflight, addr_waiting; + logic [5:0] addr_inflight_dn, addr_waiting_dn; + logic valid_req, valid_inflight, valid_waiting; + logic valid_inflight_dn, valid_waiting_dn; + logic returned_req, returned_inflight, returned_waiting; + + logic req_accepted; + logic active; + logic [1:0] apu_lat; + + + logic [2:0] read_deps_req, read_deps_inflight, read_deps_waiting; + logic [1:0] write_deps_req, write_deps_inflight, write_deps_waiting; + logic read_dep_req, read_dep_inflight, read_dep_waiting; + logic write_dep_req, write_dep_inflight, write_dep_waiting; + + logic stall_full, stall_type, stall_nack; + + // Generate request signal; do not generate request if stalled unless it's a nack stall + assign valid_req = enable_i & !(stall_full | stall_type); + assign addr_req = apu_waddr_i; + + assign req_accepted = valid_req & apu_master_gnt_i; + + // + // In-flight instructions + // + // Check whether the instructions have returned + assign returned_req = valid_req & apu_master_valid_i & !valid_inflight & !valid_waiting; + assign returned_inflight = valid_inflight & (apu_master_valid_i) & !valid_waiting; + assign returned_waiting = valid_waiting & (apu_master_valid_i); + + // Inflight and waiting registers + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + valid_inflight <= 1'b0; + valid_waiting <= 1'b0; + addr_inflight <= '0; + addr_waiting <= '0; + end else begin + valid_inflight <= valid_inflight_dn; + valid_waiting <= valid_waiting_dn; + addr_inflight <= addr_inflight_dn; + addr_waiting <= addr_waiting_dn; + end + end + + always_comb begin + valid_inflight_dn = valid_inflight; + valid_waiting_dn = valid_waiting; + addr_inflight_dn = addr_inflight; + addr_waiting_dn = addr_waiting; + + if (req_accepted & !returned_req) begin // this is a multicycle request + valid_inflight_dn = 1'b1; + addr_inflight_dn = addr_req; + if (valid_inflight & !(returned_inflight)) begin // we already have an inflight instruction! + valid_waiting_dn = 1'b1; + addr_waiting_dn = addr_inflight; + end + if (returned_waiting) begin // we have received a new request and waiting goes out of the pipe but will be refilled + valid_waiting_dn = 1'b1; + addr_waiting_dn = addr_inflight; + end + end // no new request + else if (returned_inflight) begin // multicycle request has returned + valid_inflight_dn = '0; + valid_waiting_dn = '0; + addr_inflight_dn = '0; + addr_waiting_dn = '0; + end + else if (returned_waiting) begin // multicycle request has returned + valid_waiting_dn = '0; + addr_waiting_dn = '0; + end + end + + // + // Active type + // + // Dispatcher is active when there is an unreturned instruction + assign active = valid_inflight | valid_waiting; + + // Store the latency type whenever there is a request + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + apu_lat <= '0; + end else begin + if(valid_req) begin + apu_lat <= apu_lat_i; + end + end + end + + // + // Dependency checks + // + // There is a dependency if the register is equal to one of the instructions + generate + for (genvar i = 0; i < 3; i++) begin + assign read_deps_req[i] = (read_regs_i[i] == addr_req) & read_regs_valid_i[i]; + assign read_deps_inflight[i] = (read_regs_i[i] == addr_inflight) & read_regs_valid_i[i]; + assign read_deps_waiting[i] = (read_regs_i[i] == addr_waiting) & read_regs_valid_i[i]; + end + endgenerate + + generate + for (genvar i = 0; i < 2; i++) begin + assign write_deps_req[i] = (write_regs_i[i] == addr_req) & write_regs_valid_i[i]; + assign write_deps_inflight[i] = (write_regs_i[i] == addr_inflight) & write_regs_valid_i[i]; + assign write_deps_waiting[i] = (write_regs_i[i] == addr_waiting) & write_regs_valid_i[i]; + end + endgenerate + + // Reduce the individual dependency signals into one read and one write dependency + assign read_dep_req = |read_deps_req & valid_req & !returned_req; + assign read_dep_inflight = |read_deps_inflight & valid_inflight & !returned_inflight; + assign read_dep_waiting = |read_deps_waiting & valid_waiting & !returned_waiting; + assign write_dep_req = |write_deps_req & valid_req & !returned_req; + assign write_dep_inflight = |write_deps_inflight & valid_inflight & !returned_inflight; + assign write_dep_waiting = |write_deps_waiting & valid_waiting & !returned_waiting; + + assign read_dep_o = read_dep_req | read_dep_inflight | read_dep_waiting; + assign write_dep_o = write_dep_req | write_dep_inflight | write_dep_waiting; + + // + // Stall signals + // + // Stall if we cannot store any more outstanding requests + assign stall_full = valid_inflight & valid_waiting; + // Stall if there is a type conflict. if apu is active we can only issue requests with a larger or equal latency + // than the latency of the inflight operation (apu_lat_i>=apu_lat). otherwise operations would overtake each other! + // so we stall if: (apu_lat_i = 1 & apu_lat = 2/3) | (apu_lat_i = 2 & apu_lat = 3) | (apu_lat_i = 3 (multicycle)) + assign stall_type = enable_i & active & ((apu_lat_i==2'h1) | ((apu_lat_i==2'h2) & (apu_lat==2'h3)) | (apu_lat_i==2'h3)); + assign stall_nack = valid_req & !apu_master_gnt_i; + assign stall_o = stall_full | stall_type | stall_nack; + + // + // Generate Apu_master request + // + assign apu_master_req_o = valid_req; + + // + // Use Apu_master response + // + assign apu_master_ready_o = 1'b1; + + // Determine write register based on where the instruction returned. + always_comb begin + apu_waddr_o = '0; + if(returned_req) + apu_waddr_o = addr_req; + if(returned_inflight) + apu_waddr_o = addr_inflight; + if(returned_waiting) + apu_waddr_o = addr_waiting; + end + + // Output active signal + assign active_o = active; + + // Performance counter signals + assign perf_type_o = stall_type; + assign perf_cont_o = stall_nack; + + assign apu_multicycle_o = (apu_lat == 2'h3); + assign apu_singlecycle_o = ~(valid_inflight | valid_waiting); + + // + // Assertions + // + +`ifndef VERILATOR + assert property ( + @(posedge clk_i) (apu_master_valid_i) |-> (valid_req | valid_inflight | valid_waiting)) + else $warning("[APU Dispatcher] instruction returned while no instruction is in-flight"); +`endif + +endmodule \ No newline at end of file diff --git a/hw/deps/riscv/riscv_compressed_decoder.sv b/hw/deps/riscv/riscv_compressed_decoder.sv new file mode 100644 index 0000000..50ecf56 --- /dev/null +++ b/hw/deps/riscv/riscv_compressed_decoder.sv @@ -0,0 +1,299 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Sven Stucki - svstucki@student.ethz.ch // +// // +// Additional contributions by: // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// // +// Design Name: Compressed instruction decoder // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Decodes RISC-V compressed instructions into their RV32 // +// equivalent. This module is fully combinatorial. // +// Float extensions added // +// // +//////////////////////////////////////////////////////////////////////////////// + + +import riscv_defines::*; + +module riscv_compressed_decoder +#( + parameter FPU = 0 +) +( + input logic [31:0] instr_i, + output logic [31:0] instr_o, + output logic is_compressed_o, + output logic illegal_instr_o +); + + ////////////////////////////////////////////////////////////////////////////////////////////////////// + // ____ _ ____ _ // + // / ___|___ _ __ ___ _ __ _ __ ___ ___ ___ ___ __| | | _ \ ___ ___ ___ __| | ___ _ __ // + // | | / _ \| '_ ` _ \| '_ \| '__/ _ \/ __/ __|/ _ \/ _` | | | | |/ _ \/ __/ _ \ / _` |/ _ \ '__| // + // | |__| (_) | | | | | | |_) | | | __/\__ \__ \ __/ (_| | | |_| | __/ (_| (_) | (_| | __/ | // + // \____\___/|_| |_| |_| .__/|_| \___||___/___/\___|\__,_| |____/ \___|\___\___/ \__,_|\___|_| // + // |_| // + ////////////////////////////////////////////////////////////////////////////////////////////////////// + + generate + + always_comb + begin + illegal_instr_o = 1'b0; + instr_o = '0; + + unique case (instr_i[1:0]) + // C0 + 2'b00: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.addi4spn -> addi rd', x2, imm + instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], OPCODE_OPIMM}; + if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1; + end + + 3'b001: begin + // c.fld -> fld rd', imm(rs1') + if (FPU==1) // instr_i[12:10]-> offset[5:3], instr_i[6:5]-> offset[7:6] + instr_o = {4'b0, instr_i[6:5], instr_i[12:10], 3'b000, 2'b01, instr_i[9:7], 3'b011, 2'b01, instr_i[4:2], OPCODE_LOAD_FP}; + else + illegal_instr_o = 1'b1; + end + + 3'b010: begin + // c.lw -> lw rd', imm(rs1') + instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], OPCODE_LOAD}; + end + + 3'b011: begin + // c.flw -> flw rd', imm(rs1') + if (FPU==1) + instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], OPCODE_LOAD_FP}; + else + illegal_instr_o = 1'b1; + end + + 3'b101: begin + // c.fsd -> fsd rs2', imm(rs1') + if (FPU==1) // instr_i[12:10] -> offset[5:3], instr_i[6:5] -> offset[7:6] + instr_o = {4'b0, instr_i[6:5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b011, instr_i[11:10], 3'b000, OPCODE_STORE_FP}; + else + illegal_instr_o = 1'b1; + end + + 3'b110: begin + // c.sw -> sw rs2', imm(rs1') + instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, OPCODE_STORE}; + end + + 3'b111: begin + // c.fsw -> fsw rs2', imm(rs1') + if (FPU==1) + instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, OPCODE_STORE_FP}; + else + illegal_instr_o = 1'b1; + end + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + + // C1 + 2'b01: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.addi -> addi rd, rd, nzimm + // c.nop + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OPIMM}; + end + + 3'b001, 3'b101: begin + // 001: c.jal -> jal x1, imm + // 101: c.j -> jal x0, imm + instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0, ~instr_i[15], OPCODE_JAL}; + end + + 3'b010: begin + // c.li -> addi rd, x0, nzimm + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], OPCODE_OPIMM}; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end + + 3'b011: begin + // c.lui -> lui rd, imm + instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], OPCODE_LUI}; + + if (instr_i[11:7] == 5'h02) begin + // c.addi16sp -> addi x2, x2, nzimm + instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, OPCODE_OPIMM}; + end else if (instr_i[11:7] == 5'b0) begin + illegal_instr_o = 1'b1; + end + + if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1; + end + + 3'b100: begin + unique case (instr_i[11:10]) + 2'b00, + 2'b01: begin + // 00: c.srli -> srli rd, rd, shamt + // 01: c.srai -> srai rd, rd, shamt + instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], OPCODE_OPIMM}; + if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1; + if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1; + end + + 2'b10: begin + // c.andi -> andi rd, rd, imm + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OPIMM}; + end + + 2'b11: begin + unique case ({instr_i[12], instr_i[6:5]}) + 3'b000: begin + // c.sub -> sub rd', rd', rs2' + instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP}; + end + + 3'b001: begin + // c.xor -> xor rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], OPCODE_OP}; + end + + 3'b010: begin + // c.or -> or rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], OPCODE_OP}; + end + + 3'b011: begin + // c.and -> and rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OP}; + end + + 3'b100, + 3'b101, + 3'b110, + 3'b111: begin + // 100: c.subw + // 101: c.addw + illegal_instr_o = 1'b1; + end + endcase + end + endcase + end + + 3'b110, 3'b111: begin + // 0: c.beqz -> beq rs1', x0, imm + // 1: c.bnez -> bne rs1', x0, imm + instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], OPCODE_BRANCH}; + end + endcase + end + + // C2 + 2'b10: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.slli -> slli rd, rd, shamt + instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], OPCODE_OPIMM}; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + if (instr_i[12] == 1'b1 || instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1; + end + + 3'b001: begin + // c.fldsp -> fld rd, imm(x2) + if (FPU==1) // instr_i[6:5] -> offset[4:3], instr_i[4:2] -> offset[8:6], instr_i[12] -> offset[5] + instr_o = {3'b0, instr_i[4:2], instr_i[12], instr_i[6:5], 3'b000, 5'h02, 3'b011, instr_i[11:7], OPCODE_LOAD_FP}; + else + illegal_instr_o = 1'b1; + end + + 3'b010: begin + // c.lwsp -> lw rd, imm(x2) + instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], OPCODE_LOAD}; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end + + 3'b011: begin + // c.flwsp -> flw rd, imm(x2) + if (FPU==1) + instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], OPCODE_LOAD_FP}; + else + illegal_instr_o = 1'b1; + end + + 3'b100: begin + if (instr_i[12] == 1'b0) begin + // c.mv -> add rd/rs1, x0, rs2 + instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], OPCODE_OP}; + + if (instr_i[6:2] == 5'b0) begin + // c.jr -> jalr x0, rd/rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, OPCODE_JALR}; + end + end else begin + // c.add -> add rd, rd, rs2 + instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], OPCODE_OP}; + + if (instr_i[11:7] == 5'b0) begin + // c.ebreak -> ebreak + instr_o = {32'h00_10_00_73}; + if (instr_i[6:2] != 5'b0) + illegal_instr_o = 1'b1; + end else if (instr_i[6:2] == 5'b0) begin + // c.jalr -> jalr x1, rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, OPCODE_JALR}; + end + end + end + + 3'b101: begin + // c.fsdsp -> fsd rs2, imm(x2) + if (FPU==1) // instr_i[12:10] -> offset[5:3], instr_i[9:7] -> offset[8:6] + instr_o = {3'b0, instr_i[9:7], instr_i[12], instr_i[6:2], 5'h02, 3'b011, instr_i[11:10], 3'b000, OPCODE_STORE_FP}; + else + illegal_instr_o = 1'b1; + end + 3'b110: begin + // c.swsp -> sw rs2, imm(x2) + instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, OPCODE_STORE}; + end + + 3'b111: begin + // c.fswsp -> fsw rs2, imm(x2) + if (FPU==1) + instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, OPCODE_STORE_FP}; + else + illegal_instr_o = 1'b1; + end + endcase + end + + default: begin + // 32 bit (or more) instruction + instr_o = instr_i; + end + endcase + end + + endgenerate + + assign is_compressed_o = (instr_i[1:0] != 2'b11); + +endmodule diff --git a/hw/deps/riscv/riscv_controller.sv b/hw/deps/riscv/riscv_controller.sv new file mode 100644 index 0000000..8813796 --- /dev/null +++ b/hw/deps/riscv/riscv_controller.sv @@ -0,0 +1,1138 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Matthias Baer - baermatt@student.ethz.ch // +// // +// Additional contributions by: // +// Igor Loi - igor.loi@unibo.it // +// Andreas Traber - atraber@student.ethz.ch // +// Sven Stucki - svstucki@student.ethz.ch // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// Robert Balas - balasr@iis.ee.ethz.ch // +// Andrea Bettati - andrea.bettati@studenti.unipr.it // +// // +// Design Name: Main controller // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Main CPU controller of the processor // +// // +//////////////////////////////////////////////////////////////////////////////// + +import riscv_defines::*; + +module riscv_controller +#( + parameter FPU = 0 +) +( + input logic clk, + input logic rst_n, + + input logic fetch_enable_i, // Start the decoding + output logic ctrl_busy_o, // Core is busy processing instructions + output logic first_fetch_o, // Core is at the FIRST FETCH stage + output logic is_decoding_o, // Core is in decoding state + input logic is_fetch_failed_i, + + // decoder related signals + output logic deassert_we_o, // deassert write enable for next instruction + + input logic illegal_insn_i, // decoder encountered an invalid instruction + input logic ecall_insn_i, // ecall encountered an mret instruction + input logic mret_insn_i, // decoder encountered an mret instruction + input logic uret_insn_i, // decoder encountered an uret instruction + + input logic dret_insn_i, // decoder encountered an dret instruction + + input logic mret_dec_i, + input logic uret_dec_i, + input logic dret_dec_i, + + input logic pipe_flush_i, // decoder wants to do a pipe flush + input logic ebrk_insn_i, // decoder encountered an ebreak instruction + input logic fencei_insn_i, // decoder encountered an fence.i instruction + input logic csr_status_i, // decoder encountered an csr status instruction + input logic instr_multicycle_i, // true when multiple cycles are decoded + + output logic hwloop_mask_o, //prevent writes on the hwloop instructions in case interrupt are taken + + // from IF/ID pipeline + input logic instr_valid_i, // instruction coming from IF/ID pipeline is valid + + // from prefetcher + output logic instr_req_o, // Start fetching instructions + + // to prefetcher + output logic pc_set_o, // jump to address set by pc_mux + output logic [2:0] pc_mux_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...) + output logic [2:0] exc_pc_mux_o, // Selects target PC for exception + output logic [1:0] trap_addr_mux_o, // Selects trap address base + + // LSU + input logic data_req_ex_i, // data memory access is currently performed in EX stage + input logic data_we_ex_i, + input logic data_misaligned_i, + input logic data_load_event_i, + input logic data_err_i, + output logic data_err_ack_o, + + // from ALU + input logic mult_multicycle_i, // multiplier is taken multiple cycles and uses op c as storage + + // APU dependency checks + input logic apu_en_i, + input logic apu_read_dep_i, + input logic apu_write_dep_i, + + output logic apu_stall_o, + + // jump/branch signals + input logic branch_taken_ex_i, // branch taken signal from EX ALU + input logic [1:0] jump_in_id_i, // jump is being calculated in ALU + input logic [1:0] jump_in_dec_i, // jump is being calculated in ALU + + // Interrupt Controller Signals + input logic irq_pending_i, + input logic irq_req_ctrl_i, + input logic irq_sec_ctrl_i, + input logic [5:0] irq_id_ctrl_i, + input logic m_IE_i, // interrupt enable bit from CSR (M mode) + input logic u_IE_i, // interrupt enable bit from CSR (U mode) + input PrivLvl_t current_priv_lvl_i, + + output logic irq_ack_o, + output logic [5:0] irq_id_o, + + output logic [5:0] exc_cause_o, + output logic exc_ack_o, + output logic exc_kill_o, + + // Debug Signal + output logic debug_mode_o, + output logic [2:0] debug_cause_o, + output logic debug_csr_save_o, + input logic debug_req_i, + input logic debug_single_step_i, + input logic debug_ebreakm_i, + input logic debug_ebreaku_i, + input logic trigger_match_i, + + output logic csr_save_if_o, + output logic csr_save_id_o, + output logic csr_save_ex_o, + output logic [6:0] csr_cause_o, + output logic csr_irq_sec_o, + output logic csr_restore_mret_id_o, + output logic csr_restore_uret_id_o, + + output logic csr_restore_dret_id_o, + + output logic csr_save_cause_o, + + + // Regfile target + input logic regfile_we_id_i, // currently decoded we enable + input logic [5:0] regfile_alu_waddr_id_i, // currently decoded target address + + // Forwarding signals from regfile + input logic regfile_we_ex_i, // FW: write enable from EX stage + input logic [5:0] regfile_waddr_ex_i, // FW: write address from EX stage + input logic regfile_we_wb_i, // FW: write enable from WB stage + input logic regfile_alu_we_fw_i, // FW: ALU/MUL write enable from EX stage + + // forwarding signals + output logic [1:0] operand_a_fw_mux_sel_o, // regfile ra data selector form ID stage + output logic [1:0] operand_b_fw_mux_sel_o, // regfile rb data selector form ID stage + output logic [1:0] operand_c_fw_mux_sel_o, // regfile rc data selector form ID stage + + // forwarding detection signals + input logic reg_d_ex_is_reg_a_i, + input logic reg_d_ex_is_reg_b_i, + input logic reg_d_ex_is_reg_c_i, + input logic reg_d_wb_is_reg_a_i, + input logic reg_d_wb_is_reg_b_i, + input logic reg_d_wb_is_reg_c_i, + input logic reg_d_alu_is_reg_a_i, + input logic reg_d_alu_is_reg_b_i, + input logic reg_d_alu_is_reg_c_i, + + // stall signals + output logic halt_if_o, + output logic halt_id_o, + + output logic misaligned_stall_o, + output logic jr_stall_o, + output logic load_stall_o, + + input logic id_ready_i, // ID stage is ready + + input logic ex_valid_i, // EX stage is done + + input logic wb_ready_i, // WB stage is ready + + // Performance Counters + output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr) + output logic perf_jr_stall_o, // stall due to jump-register-hazard + output logic perf_ld_stall_o, // stall due to load-use-hazard + output logic perf_pipeline_stall_o // stall due to elw extra cycles +); + + // FSM state encoding + ctrl_state_e ctrl_fsm_cs, ctrl_fsm_ns; + + logic jump_done, jump_done_q, jump_in_dec, branch_in_id; + logic boot_done, boot_done_q; + logic irq_enable_int; + logic data_err_q; + + logic debug_mode_q, debug_mode_n; + logic ebrk_force_debug_mode; + + logic illegal_insn_q, illegal_insn_n; + + logic instr_valid_irq_flush_n, instr_valid_irq_flush_q; + +`ifndef SYNTHESIS + // synopsys translate_off + // make sure we are called later so that we do not generate messages for + // glitches + always_ff @(negedge clk) + begin + // print warning in case of decoding errors + if (is_decoding_o && illegal_insn_i) begin + $display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.hart_id_i[3:0], + riscv_id_stage.pc_id_i); + end + end + // synopsys translate_on +`endif + + + //////////////////////////////////////////////////////////////////////////////////////////// + // ____ ___ ____ _____ ____ ___ _ _ _____ ____ ___ _ _ _____ ____ // + // / ___/ _ \| _ \| ____| / ___/ _ \| \ | |_ _| _ \ / _ \| | | | | ____| _ \ // + // | | | | | | |_) | _| | | | | | | \| | | | | |_) | | | | | | | | _| | |_) | // + // | |__| |_| | _ <| |___ | |__| |_| | |\ | | | | _ <| |_| | |___| |___| |___| _ < // + // \____\___/|_| \_\_____| \____\___/|_| \_| |_| |_| \_\\___/|_____|_____|_____|_| \_\ // + // // + //////////////////////////////////////////////////////////////////////////////////////////// + + always_comb + begin + // Default values + instr_req_o = 1'b1; + + exc_ack_o = 1'b0; + exc_kill_o = 1'b0; + data_err_ack_o = 1'b0; + + csr_save_if_o = 1'b0; + csr_save_id_o = 1'b0; + csr_save_ex_o = 1'b0; + csr_restore_mret_id_o = 1'b0; + csr_restore_uret_id_o = 1'b0; + + csr_restore_dret_id_o = 1'b0; + + csr_save_cause_o = 1'b0; + + exc_cause_o = '0; + exc_pc_mux_o = EXC_PC_IRQ; + trap_addr_mux_o = TRAP_MACHINE; + + csr_cause_o = '0; + csr_irq_sec_o = 1'b0; + + pc_mux_o = PC_BOOT; + pc_set_o = 1'b0; + jump_done = jump_done_q; + + ctrl_fsm_ns = ctrl_fsm_cs; + + ctrl_busy_o = 1'b1; + first_fetch_o = 1'b0; + + halt_if_o = 1'b0; + halt_id_o = 1'b0; + irq_ack_o = 1'b0; + irq_id_o = irq_id_ctrl_i[5:0]; + + boot_done = 1'b0; + jump_in_dec = jump_in_dec_i == BRANCH_JALR || jump_in_dec_i == BRANCH_JAL; + branch_in_id = jump_in_id_i == BRANCH_COND; + irq_enable_int = ((u_IE_i | irq_sec_ctrl_i) & current_priv_lvl_i == PRIV_LVL_U) | (m_IE_i & current_priv_lvl_i == PRIV_LVL_M); + + ebrk_force_debug_mode = (debug_ebreakm_i && current_priv_lvl_i == PRIV_LVL_M) || + (debug_ebreaku_i && current_priv_lvl_i == PRIV_LVL_U); + debug_csr_save_o = 1'b0; + debug_cause_o = DBG_CAUSE_EBREAK; + debug_mode_n = debug_mode_q; + + illegal_insn_n = illegal_insn_q; + // a trap towards the debug unit is generated when one of the + // following conditions are true: + // - ebreak instruction encountered + // - single-stepping mode enabled + // - illegal instruction exception and IIE bit is set + // - IRQ and INTE bit is set and no exception is currently running + // - Debuger requests halt + + perf_pipeline_stall_o = 1'b0; + + + //this signal goes to 1 only registered interrupt requests are killed by exc_kill_o + //so that the current instructions will have the deassert_we_o signal equal to 0 once the controller is back to DECODE + instr_valid_irq_flush_n = 1'b0; + + hwloop_mask_o = 1'b0; + + unique case (ctrl_fsm_cs) + // We were just reset, wait for fetch_enable + RESET: + begin + is_decoding_o = 1'b0; + instr_req_o = 1'b0; + if (fetch_enable_i == 1'b1) + begin + ctrl_fsm_ns = BOOT_SET; + end + end + + // copy boot address to instr fetch address + BOOT_SET: + begin + is_decoding_o = 1'b0; + instr_req_o = 1'b1; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b1; + boot_done = 1'b1; + ctrl_fsm_ns = FIRST_FETCH; + end + + WAIT_SLEEP: + begin + is_decoding_o = 1'b0; + ctrl_busy_o = 1'b0; + instr_req_o = 1'b0; + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = SLEEP; + end + + // instruction in if_stage is already valid + SLEEP: + begin + // we begin execution when an + // interrupt has arrived + is_decoding_o = 1'b0; + ctrl_busy_o = 1'b0; + instr_req_o = 1'b0; + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + + // normal execution flow + // in debug mode or single step mode we leave immediately (wfi=nop) + if (irq_pending_i || (debug_req_i || debug_mode_q || debug_single_step_i || trigger_match_i)) begin + ctrl_fsm_ns = FIRST_FETCH; + end + + end + + FIRST_FETCH: + begin + is_decoding_o = 1'b0; + first_fetch_o = 1'b1; + // Stall because of IF miss + if ((id_ready_i == 1'b1) ) + begin + ctrl_fsm_ns = DECODE; + end + + // handle interrupts + if (irq_req_ctrl_i & irq_enable_int) begin + // This assumes that the pipeline is always flushed before + // going to sleep. + ctrl_fsm_ns = IRQ_TAKEN_IF; + halt_if_o = 1'b1; + halt_id_o = 1'b1; + end + + if ((debug_req_i || trigger_match_i) & (~debug_mode_q)) + begin + ctrl_fsm_ns = DBG_TAKEN_IF; + halt_if_o = 1'b1; + halt_id_o = 1'b1; + end + + end + + DECODE: + begin + + if (branch_taken_ex_i) + begin //taken branch + // there is a branch in the EX stage that is taken + + is_decoding_o = 1'b0; + + pc_mux_o = PC_BRANCH; + pc_set_o = 1'b1; + + // if we want to debug, flush the pipeline + // the current_pc_if will take the value of the next instruction to + // be executed (NPC) + + end //taken branch + + else if (data_err_i) + begin //data error + // the current LW or SW have been blocked by the PMP + + is_decoding_o = 1'b0; + halt_if_o = 1'b1; + halt_id_o = 1'b1; + csr_save_ex_o = 1'b1; + csr_save_cause_o = 1'b1; + data_err_ack_o = 1'b1; + //no jump in this stage as we have to wait one cycle to go to Machine Mode + + csr_cause_o = data_we_ex_i ? EXC_CAUSE_STORE_FAULT : EXC_CAUSE_LOAD_FAULT; + ctrl_fsm_ns = FLUSH_WB; + + end //data error + + else if (is_fetch_failed_i) + begin + + // the current instruction has been blocked by the PMP + + is_decoding_o = 1'b0; + halt_id_o = 1'b1; + halt_if_o = 1'b1; + csr_save_if_o = 1'b1; + csr_save_cause_o = 1'b1; + + //no jump in this stage as we have to wait one cycle to go to Machine Mode + + csr_cause_o = EXC_CAUSE_INSTR_FAULT; + ctrl_fsm_ns = FLUSH_WB; + + + end + // decode and execute instructions only if the current conditional + // branch in the EX stage is either not taken, or there is no + // conditional branch in the EX stage + else if (instr_valid_i || instr_valid_irq_flush_q) //valid block or replay after interrupt speculation + begin // now analyze the current instruction in the ID stage + + is_decoding_o = 1'b1; + + unique case(1'b1) + + //irq_req_ctrl_i comes from a FF in the interrupt controller + //irq_enable_int: check again irq_enable_int because xIE could have changed + //don't serve in debug mode + irq_req_ctrl_i & irq_enable_int & (~debug_req_i) & (~debug_mode_q): + begin + //Serving the external interrupt + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = IRQ_FLUSH; + hwloop_mask_o = 1'b1; + end + + + (debug_req_i || trigger_match_i) & (~debug_mode_q): + begin + //Serving the debug + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = DBG_FLUSH; + end + + + default: + begin + + exc_kill_o = irq_req_ctrl_i ? 1'b1 : 1'b0; + + if(illegal_insn_i) begin + + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = FLUSH_EX; + illegal_insn_n = 1'b1; + end else begin + + //decoding block + unique case (1'b1) + + jump_in_dec: begin + // handle unconditional jumps + // we can jump directly since we know the address already + // we don't need to worry about conditional branches here as they + // will be evaluated in the EX stage + pc_mux_o = PC_JUMP; + // if there is a jr stall, wait for it to be gone + if ((~jr_stall_o) && (~jump_done_q)) begin + pc_set_o = 1'b1; + jump_done = 1'b1; + end + + end + ebrk_insn_i: begin + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + if (debug_mode_q) + // we got back to the park loop in the debug rom + ctrl_fsm_ns = DBG_FLUSH; + + else if (ebrk_force_debug_mode) + // debug module commands us to enter debug mode anyway + ctrl_fsm_ns = DBG_FLUSH; + + else begin + // otherwise just a normal ebreak exception + ctrl_fsm_ns = FLUSH_EX; + end + + end + pipe_flush_i: begin + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = FLUSH_EX; + end + ecall_insn_i: begin + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = FLUSH_EX; + end + fencei_insn_i: begin + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = FLUSH_EX; + end + mret_insn_i | uret_insn_i | dret_insn_i: begin + halt_if_o = 1'b1; + halt_id_o = 1'b1; + ctrl_fsm_ns = FLUSH_EX; + end + csr_status_i: begin + halt_if_o = 1'b1; + ctrl_fsm_ns = id_ready_i ? FLUSH_EX : DECODE; + end + data_load_event_i: begin + ctrl_fsm_ns = id_ready_i ? ELW_EXE : DECODE; + halt_if_o = 1'b1; + end + default:; + + endcase // unique case (1'b1) + end + + if (debug_single_step_i & ~debug_mode_q) begin + // prevent any more instructions from executing + halt_if_o = 1'b1; + + // we don't handle dret here because its should be illegal + // anyway in this context + + // illegal, ecall, ebrk and xrettransition to later to a DBG + // state since we need the return address which is + // determined later + + // TODO: handle ebrk_force_debug_mode plus single stepping over ebreak + if (id_ready_i) begin + // make sure the current instruction has been executed + unique case(1'b1) + illegal_insn_i | ecall_insn_i: + ctrl_fsm_ns = FLUSH_EX; // TODO: flush ex + (~ebrk_force_debug_mode & ebrk_insn_i): + ctrl_fsm_ns = FLUSH_EX; + mret_insn_i | uret_insn_i: + ctrl_fsm_ns = FLUSH_EX; + branch_in_id: + ctrl_fsm_ns = DBG_WAIT_BRANCH; + default: + // regular instruction + ctrl_fsm_ns = DBG_FLUSH; + endcase // unique case (1'b1) + end + end + + end //decoding block + endcase + end //valid block + else begin + is_decoding_o = 1'b0; + perf_pipeline_stall_o = data_load_event_i; + end + end + + + // flush the pipeline, insert NOP into EX stage + FLUSH_EX: + begin + is_decoding_o = 1'b0; + + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + if (data_err_i) + begin //data error + // the current LW or SW have been blocked by the PMP + csr_save_ex_o = 1'b1; + csr_save_cause_o = 1'b1; + data_err_ack_o = 1'b1; + //no jump in this stage as we have to wait one cycle to go to Machine Mode + csr_cause_o = data_we_ex_i ? EXC_CAUSE_STORE_FAULT : EXC_CAUSE_LOAD_FAULT; + ctrl_fsm_ns = FLUSH_WB; + //putting illegal to 0 as if it was 1, the core is going to jump to the exception of the EX stage, + //so the illegal was never executed + illegal_insn_n = 1'b0; + end //data erro + else if (ex_valid_i) begin + //check done to prevent data harzard in the CSR registers + ctrl_fsm_ns = FLUSH_WB; + + if(illegal_insn_q) begin + csr_save_id_o = 1'b1; + csr_save_cause_o = 1'b1; + csr_cause_o = EXC_CAUSE_ILLEGAL_INSN; + end else begin + unique case (1'b1) + ebrk_insn_i: begin + csr_save_id_o = 1'b1; + csr_save_cause_o = 1'b1; + csr_cause_o = EXC_CAUSE_BREAKPOINT; + end + ecall_insn_i: begin + csr_save_id_o = 1'b1; + csr_save_cause_o = 1'b1; + csr_cause_o = current_priv_lvl_i == PRIV_LVL_U ? EXC_CAUSE_ECALL_UMODE : EXC_CAUSE_ECALL_MMODE; + end + default:; + endcase // unique case (1'b1) + end + + end + end + + + IRQ_FLUSH: + begin + is_decoding_o = 1'b0; + + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + if (data_err_i) + begin //data error + // the current LW or SW have been blocked by the PMP + csr_save_ex_o = 1'b1; + csr_save_cause_o = 1'b1; + data_err_ack_o = 1'b1; + //no jump in this stage as we have to wait one cycle to go to Machine Mode + csr_cause_o = data_we_ex_i ? EXC_CAUSE_STORE_FAULT : EXC_CAUSE_LOAD_FAULT; + ctrl_fsm_ns = FLUSH_WB; + + end //data error + else begin + if(irq_pending_i & irq_enable_int) begin + ctrl_fsm_ns = IRQ_TAKEN_ID; + end else begin + // we can go back to decode in case the IRQ is not taken (no ELW REPLAY) + exc_kill_o = 1'b1; + instr_valid_irq_flush_n = 1'b1; + ctrl_fsm_ns = DECODE; + end + end + end + + IRQ_FLUSH_ELW: + begin + is_decoding_o = 1'b0; + + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + perf_pipeline_stall_o = data_load_event_i; + + if(irq_pending_i & irq_enable_int) begin + ctrl_fsm_ns = IRQ_TAKEN_ID; + end else begin + // we can go back to decode in case the IRQ is not taken (no ELW REPLAY) + exc_kill_o = 1'b1; + ctrl_fsm_ns = DECODE; + end + end + + ELW_EXE: + begin + is_decoding_o = 1'b0; + + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + + //if we are here, a elw is executing now in the EX stage + //or if an interrupt has been received + //the ID stage contains the PC_ID of the elw, therefore halt_id is set to invalid the instruction + //If an interrupt occurs, we replay the ELW + //No needs to check irq_int_req_i since in the EX stage there is only the elw, no CSR pendings + if(id_ready_i) + ctrl_fsm_ns = ((debug_req_i || trigger_match_i) & ~debug_mode_q) ? DBG_FLUSH : IRQ_FLUSH_ELW; + // if from the ELW EXE we go to IRQ_FLUSH_ELW, it is assumed that if there was an IRQ req together with the grant and IE was valid, then + // there must be no hazard due to xIE + else + ctrl_fsm_ns = ELW_EXE; + + perf_pipeline_stall_o = data_load_event_i; + end + + IRQ_TAKEN_ID: + begin + is_decoding_o = 1'b0; + + pc_set_o = 1'b1; + pc_mux_o = PC_EXCEPTION; + exc_pc_mux_o = EXC_PC_IRQ; + exc_cause_o = irq_id_ctrl_i; + csr_irq_sec_o = irq_sec_ctrl_i; + + // IRQs (standard plus extension) + irq_ack_o = 1'b1; + if(irq_sec_ctrl_i) + trap_addr_mux_o = TRAP_MACHINE; + else + trap_addr_mux_o = current_priv_lvl_i == PRIV_LVL_U ? TRAP_USER : TRAP_MACHINE; + + csr_save_cause_o = 1'b1; + csr_cause_o = {1'b1,irq_id_ctrl_i}; + csr_save_id_o = 1'b1; + exc_ack_o = 1'b1; + ctrl_fsm_ns = DECODE; + end + + + IRQ_TAKEN_IF: + begin + is_decoding_o = 1'b0; + + pc_set_o = 1'b1; + pc_mux_o = PC_EXCEPTION; + exc_pc_mux_o = EXC_PC_IRQ; + exc_cause_o = irq_id_ctrl_i; + csr_irq_sec_o = irq_sec_ctrl_i; + + // IRQs (standard plus extension) + irq_ack_o = 1'b1; + if(irq_sec_ctrl_i) + trap_addr_mux_o = TRAP_MACHINE; + else + trap_addr_mux_o = current_priv_lvl_i == PRIV_LVL_U ? TRAP_USER : TRAP_MACHINE; + + csr_save_cause_o = 1'b1; + csr_cause_o = {1'b1,irq_id_ctrl_i}; + csr_save_if_o = 1'b1; + exc_ack_o = 1'b1; + ctrl_fsm_ns = DECODE; + end + + + // flush the pipeline, insert NOP into EX and WB stage + FLUSH_WB: + begin + is_decoding_o = 1'b0; + + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + ctrl_fsm_ns = DECODE; + + if(data_err_q) begin + //data_error + pc_mux_o = PC_EXCEPTION; + pc_set_o = 1'b1; + trap_addr_mux_o = TRAP_MACHINE; + //little hack during testing + exc_pc_mux_o = EXC_PC_EXCEPTION; + exc_cause_o = data_we_ex_i ? EXC_CAUSE_LOAD_FAULT : EXC_CAUSE_STORE_FAULT; + + end + else if (is_fetch_failed_i) begin + //data_error + pc_mux_o = PC_EXCEPTION; + pc_set_o = 1'b1; + trap_addr_mux_o = TRAP_MACHINE; + exc_pc_mux_o = EXC_PC_EXCEPTION; + exc_cause_o = EXC_CAUSE_INSTR_FAULT; + + end + else begin + if(illegal_insn_q) begin + //exceptions + pc_mux_o = PC_EXCEPTION; + pc_set_o = 1'b1; + trap_addr_mux_o = TRAP_MACHINE; + exc_pc_mux_o = EXC_PC_EXCEPTION; + illegal_insn_n = 1'b0; + if (debug_single_step_i && ~debug_mode_q) + ctrl_fsm_ns = DBG_TAKEN_IF; + end else begin + unique case(1'b1) + ebrk_insn_i: begin + //ebreak + pc_mux_o = PC_EXCEPTION; + pc_set_o = 1'b1; + trap_addr_mux_o = TRAP_MACHINE; + exc_pc_mux_o = EXC_PC_EXCEPTION; + + if (debug_single_step_i && ~debug_mode_q) + ctrl_fsm_ns = DBG_TAKEN_IF; + end + ecall_insn_i: begin + //ecall + pc_mux_o = PC_EXCEPTION; + pc_set_o = 1'b1; + trap_addr_mux_o = TRAP_MACHINE; + exc_pc_mux_o = EXC_PC_EXCEPTION; + // TODO: why is this here, signal only needed for async exceptions + exc_cause_o = EXC_CAUSE_ECALL_MMODE; + + if (debug_single_step_i && ~debug_mode_q) + ctrl_fsm_ns = DBG_TAKEN_IF; + end + + mret_insn_i: begin + csr_restore_mret_id_o = 1'b1; + ctrl_fsm_ns = XRET_JUMP; + end + uret_insn_i: begin + csr_restore_uret_id_o = 1'b1; + ctrl_fsm_ns = XRET_JUMP; + end + dret_insn_i: begin + csr_restore_dret_id_o = 1'b1; + ctrl_fsm_ns = XRET_JUMP; + end + + csr_status_i: begin + + end + pipe_flush_i: begin + ctrl_fsm_ns = WAIT_SLEEP; + end + fencei_insn_i: begin + // we just jump to instruction after the fence.i since that + // forces the instruction cache to refetch + pc_mux_o = PC_FENCEI; + pc_set_o = 1'b1; + end + default:; + endcase + end + end + + end + + XRET_JUMP: + begin + is_decoding_o = 1'b0; + ctrl_fsm_ns = DECODE; + unique case(1'b1) + mret_dec_i: begin + //mret + pc_mux_o = PC_MRET; + pc_set_o = 1'b1; + end + uret_dec_i: begin + //uret + pc_mux_o = PC_URET; + pc_set_o = 1'b1; + end + dret_dec_i: begin + //dret + //TODO: is illegal when not in debug mode + pc_mux_o = PC_DRET; + pc_set_o = 1'b1; + debug_mode_n = 1'b0; + end + default:; + endcase + + if (debug_single_step_i && ~debug_mode_q) begin + ctrl_fsm_ns = DBG_TAKEN_IF; + end + end + + // a branch was in ID when a trying to go to debug rom wait until we can + // determine branch target address (for saving into dpc) before proceeding + DBG_WAIT_BRANCH: + begin + is_decoding_o = 1'b0; + halt_if_o = 1'b1; + + if (branch_taken_ex_i) begin + // there is a branch in the EX stage that is taken + pc_mux_o = PC_BRANCH; + pc_set_o = 1'b1; + end + + ctrl_fsm_ns = DBG_FLUSH; + end + + // We enter this state when we encounter + // 1. ebreak during debug mode + // 2. ebreak with forced entry into debug mode (ebreakm or ebreaku set). + // 3. halt request during decode + // Regular ebreak's go through FLUSH_EX and FLUSH_WB. + // For 1. we don't update dcsr and dpc while for 2. and 3. we do + // (debug-spec p.39). Critically dpc is set to the address of ebreak and + // not to the next instruction's (which is why we save the pc in id). + DBG_TAKEN_ID: + begin + is_decoding_o = 1'b0; + pc_set_o = 1'b1; + pc_mux_o = PC_EXCEPTION; + exc_pc_mux_o = EXC_PC_DBD; + if (((debug_req_i || trigger_match_i) && (~debug_mode_q)) || + (ebrk_insn_i && ebrk_force_debug_mode && (~debug_mode_q))) begin + csr_save_cause_o = 1'b1; + csr_save_id_o = 1'b1; + debug_csr_save_o = 1'b1; + if (debug_req_i) + debug_cause_o = DBG_CAUSE_HALTREQ; + if (ebrk_insn_i) + debug_cause_o = DBG_CAUSE_EBREAK; + if (trigger_match_i) + debug_cause_o = DBG_CAUSE_TRIGGER; + end + ctrl_fsm_ns = DECODE; + debug_mode_n = 1'b1; + end + + DBG_TAKEN_IF: + begin + is_decoding_o = 1'b0; + pc_set_o = 1'b1; + pc_mux_o = PC_EXCEPTION; + exc_pc_mux_o = EXC_PC_DBD; + csr_save_cause_o = 1'b1; + debug_csr_save_o = 1'b1; + if (debug_single_step_i) + debug_cause_o = DBG_CAUSE_STEP; + if (debug_req_i) + debug_cause_o = DBG_CAUSE_HALTREQ; + if (ebrk_insn_i) + debug_cause_o = DBG_CAUSE_EBREAK; + if (trigger_match_i) + debug_cause_o = DBG_CAUSE_TRIGGER; + csr_save_if_o = 1'b1; + ctrl_fsm_ns = DECODE; + debug_mode_n = 1'b1; + end + + DBG_FLUSH: + begin + is_decoding_o = 1'b0; + + halt_if_o = 1'b1; + halt_id_o = 1'b1; + + perf_pipeline_stall_o = data_load_event_i; + + if (data_err_i) + begin //data error + // the current LW or SW have been blocked by the PMP + csr_save_ex_o = 1'b1; + csr_save_cause_o = 1'b1; + data_err_ack_o = 1'b1; + //no jump in this stage as we have to wait one cycle to go to Machine Mode + csr_cause_o = data_we_ex_i ? EXC_CAUSE_STORE_FAULT : EXC_CAUSE_LOAD_FAULT; + ctrl_fsm_ns = FLUSH_WB; + + end //data error + else begin + if(debug_mode_q) begin //ebreak in debug rom + ctrl_fsm_ns = DBG_TAKEN_ID; + end else if(data_load_event_i) begin + ctrl_fsm_ns = DBG_TAKEN_ID; + end else if (debug_single_step_i) begin + // save the next instruction when single stepping regular insn + ctrl_fsm_ns = DBG_TAKEN_IF; + end else begin + ctrl_fsm_ns = DBG_TAKEN_ID; + end + end + end + // Debug end + + default: begin + is_decoding_o = 1'b0; + instr_req_o = 1'b0; + ctrl_fsm_ns = RESET; + end + endcase + end + + ///////////////////////////////////////////////////////////// + // ____ _ _ _ ____ _ _ // + // / ___|| |_ __ _| | | / ___|___ _ __ | |_ _ __ ___ | | // + // \___ \| __/ _` | | | | | / _ \| '_ \| __| '__/ _ \| | // + // ___) | || (_| | | | | |__| (_) | | | | |_| | | (_) | | // + // |____/ \__\__,_|_|_| \____\___/|_| |_|\__|_| \___/|_| // + // // + ///////////////////////////////////////////////////////////// + always_comb + begin + load_stall_o = 1'b0; + jr_stall_o = 1'b0; + deassert_we_o = 1'b0; + + // deassert WE when the core is not decoding instructions + if (~is_decoding_o) + deassert_we_o = 1'b1; + + // deassert WE in case of illegal instruction + if (illegal_insn_i) + deassert_we_o = 1'b1; + + // Stall because of load operation + if ( + ( (data_req_ex_i == 1'b1) && (regfile_we_ex_i == 1'b1) || + (wb_ready_i == 1'b0) && (regfile_we_wb_i == 1'b1) + ) && + ( (reg_d_ex_is_reg_a_i == 1'b1) || (reg_d_ex_is_reg_b_i == 1'b1) || (reg_d_ex_is_reg_c_i == 1'b1) || + (is_decoding_o && regfile_we_id_i && (regfile_waddr_ex_i == regfile_alu_waddr_id_i)) ) + ) + begin + deassert_we_o = 1'b1; + load_stall_o = 1'b1; + end + + // Stall because of jr path + // - always stall if a result is to be forwarded to the PC + // we don't care about in which state the ctrl_fsm is as we deassert_we + // anyway when we are not in DECODE + if ((jump_in_dec_i == BRANCH_JALR) && + (((regfile_we_wb_i == 1'b1) && (reg_d_wb_is_reg_a_i == 1'b1)) || + ((regfile_we_ex_i == 1'b1) && (reg_d_ex_is_reg_a_i == 1'b1)) || + ((regfile_alu_we_fw_i == 1'b1) && (reg_d_alu_is_reg_a_i == 1'b1))) ) + begin + jr_stall_o = 1'b1; + deassert_we_o = 1'b1; + end + end + + + // stall because of misaligned data access + assign misaligned_stall_o = data_misaligned_i; + + // APU dependency stalls (data hazards) + assign apu_stall_o = apu_read_dep_i | (apu_write_dep_i & ~apu_en_i); + + // Forwarding control unit + always_comb + begin + // default assignements + operand_a_fw_mux_sel_o = SEL_REGFILE; + operand_b_fw_mux_sel_o = SEL_REGFILE; + operand_c_fw_mux_sel_o = SEL_REGFILE; + + // Forwarding WB -> ID + if (regfile_we_wb_i == 1'b1) + begin + if (reg_d_wb_is_reg_a_i == 1'b1) + operand_a_fw_mux_sel_o = SEL_FW_WB; + if (reg_d_wb_is_reg_b_i == 1'b1) + operand_b_fw_mux_sel_o = SEL_FW_WB; + if (reg_d_wb_is_reg_c_i == 1'b1) + operand_c_fw_mux_sel_o = SEL_FW_WB; + end + + // Forwarding EX -> ID + if (regfile_alu_we_fw_i == 1'b1) + begin + if (reg_d_alu_is_reg_a_i == 1'b1) + operand_a_fw_mux_sel_o = SEL_FW_EX; + if (reg_d_alu_is_reg_b_i == 1'b1) + operand_b_fw_mux_sel_o = SEL_FW_EX; + if (reg_d_alu_is_reg_c_i == 1'b1) + operand_c_fw_mux_sel_o = SEL_FW_EX; + end + + // for misaligned memory accesses + if (data_misaligned_i) + begin + operand_a_fw_mux_sel_o = SEL_FW_EX; + operand_b_fw_mux_sel_o = SEL_REGFILE; + end else if (mult_multicycle_i) begin + operand_c_fw_mux_sel_o = SEL_FW_EX; + end + end + + // update registers + always_ff @(posedge clk , negedge rst_n) + begin : UPDATE_REGS + if ( rst_n == 1'b0 ) + begin + ctrl_fsm_cs <= RESET; + jump_done_q <= 1'b0; + boot_done_q <= 1'b0; + data_err_q <= 1'b0; + + debug_mode_q <= 1'b0; + illegal_insn_q <= 1'b0; + + instr_valid_irq_flush_q <= 1'b0; + + end + else + begin + ctrl_fsm_cs <= ctrl_fsm_ns; + boot_done_q <= boot_done | (~boot_done & boot_done_q); + // clear when id is valid (no instruction incoming) + jump_done_q <= jump_done & (~id_ready_i); + + data_err_q <= data_err_i; + + debug_mode_q <= debug_mode_n; + + illegal_insn_q <= illegal_insn_n; + + instr_valid_irq_flush_q <= instr_valid_irq_flush_n; + end + end + + // Performance Counters + assign perf_jump_o = (jump_in_id_i == BRANCH_JAL || jump_in_id_i == BRANCH_JALR); + assign perf_jr_stall_o = jr_stall_o; + assign perf_ld_stall_o = load_stall_o; + + // debug mode + assign debug_mode_o = debug_mode_q; + + + //---------------------------------------------------------------------------- + // Assertions + //---------------------------------------------------------------------------- + // make sure that taken branches do not happen back-to-back, as this is not + // possible without branch prediction in the IF stage + `ifndef VERILATOR + assert property ( + @(posedge clk) (branch_taken_ex_i) |=> (~branch_taken_ex_i) ) else $warning("Two branches back-to-back are taken"); + `endif +endmodule // controller diff --git a/hw/deps/riscv/riscv_core.sv b/hw/deps/riscv/riscv_core.sv new file mode 100644 index 0000000..ffaccf0 --- /dev/null +++ b/hw/deps/riscv/riscv_core.sv @@ -0,0 +1,1284 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Matthias Baer - baermatt@student.ethz.ch // +// // +// Additional contributions by: // +// Igor Loi - igor.loi@unibo.it // +// Andreas Traber - atraber@student.ethz.ch // +// Sven Stucki - svstucki@student.ethz.ch // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: Top level module // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Top level module of the RISC-V core. // +// added APU, FPU parameter to include the APU_dispatcher // +// and the FPU // +// // +//////////////////////////////////////////////////////////////////////////////// + +import apu_core_package::*; + +`include "riscv_config.sv" + +import riscv_defines::*; + +module riscv_core +#( + parameter PULP_HWLP = 0, + parameter INSTR_RDATA_WIDTH = 128, + parameter N_EXT_PERF_COUNTERS = 0, + parameter PULP_CLUSTER = 1, + parameter FPU = 0, + parameter PULP_ZFINX = 0, + parameter NUM_MHPMCOUNTERS = 1, + parameter SHARED_FP = 0, + parameter SHARED_DSP_MULT = 0, + parameter SHARED_INT_DIV = 0, + parameter SHARED_FP_DIVSQRT = 0, + parameter WAPUTYPE = 0, + parameter APU_NARGS_CPU = 3, + parameter APU_WOP_CPU = 6, + parameter APU_NDSFLAGS_CPU = 15, + parameter APU_NUSFLAGS_CPU = 5, + parameter N_PMP_ENTRIES = 16 +) +( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic clock_en_i, // enable clock, otherwise it is gated + input logic scan_cg_en_i, // enable all clock gates for testing + + // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static + input logic [31:0] boot_addr_i, + input logic [31:0] dm_halt_addr_i, + input logic [31:0] hart_id_i, + + // Instruction memory interface + output logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + output logic [31:0] instr_addr_o, + input logic [INSTR_RDATA_WIDTH-1:0] instr_rdata_i, + + // Data memory interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + output logic data_we_o, + output logic [3:0] data_be_o, + output logic [31:0] data_addr_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + + output logic [5:0] data_atop_o, + output logic data_buffer_o, + output logic data_unaligned_o, + + // apu-interconnect + // handshake signals + output logic apu_master_req_o, + output logic apu_master_ready_o, + input logic apu_master_gnt_i, + // request channel + output logic [APU_NARGS_CPU-1:0][31:0] apu_master_operands_o, + output logic [APU_WOP_CPU-1:0] apu_master_op_o, + output logic [WAPUTYPE-1:0] apu_master_type_o, + output logic [APU_NDSFLAGS_CPU-1:0] apu_master_flags_o, + // response channel + input logic apu_master_valid_i, + input logic [31:0] apu_master_result_i, + input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i, + + // Interrupt inputs + output logic irq_ack_o, + output logic [5:0] irq_id_o, + + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [47:0] irq_fast_i, + + // Debug Interface + input logic debug_req_i, + + // CPU Control Signals + input logic fetch_enable_i, + output logic core_busy_o, + + // PMP coonfiguration + // NOTE: when pmp_conf_override_i is high, the pmp configuration is taken from the input + // (i.e., pmp_addr_i and pmp_cfg_i) instead of from the CS registers. + input logic pmp_conf_override_i, + input logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_i, + input logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_i +); + + // Unused parameters and signals (left in code for future design extensions) + localparam PULP_SECURE = 1; + localparam USE_PMP = 1; // if PULP_SECURE is 1, you can still not use the PMP + localparam A_EXTENSION = 1; + localparam FP_DIVSQRT = FPU; + //localparam SHARED_FP = 0; + //localparam SHARED_DSP_MULT = 0; + localparam SHARED_INT_MULT = 0; + //localparam SHARED_INT_DIV = 0; + //localparam SHARED_FP_DIVSQRT = 0; + localparam DEBUG_TRIGGER_EN = 1; + + // Unused signals related to above unused parameters + // Left in code (with their original _i, _o postfixes) for future design extensions; + // these used to be former inputs/outputs of RI5CY + + logic irq_sec_i; + logic sec_lvl_o; + + localparam N_HWLP = 2; + localparam N_HWLP_BITS = $clog2(N_HWLP); + localparam APU = ((SHARED_DSP_MULT==1) | (SHARED_INT_DIV==1) | (FPU==1)) ? 1 : 0; + + + // IF/ID signals + logic is_hwlp_id; + logic [N_HWLP-1:0] hwlp_dec_cnt_id; + logic instr_valid_id; + logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage + logic is_compressed_id; + logic is_fetch_failed_id; + logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage + logic [31:0] pc_if; // Program counter in IF stage + logic [31:0] pc_id; // Program counter in ID stage + + logic clear_instr_valid; + logic pc_set; + logic [2:0] pc_mux_id; // Mux selector for next PC + logic [2:0] exc_pc_mux_id; // Mux selector for exception PC + logic [5:0] m_exc_vec_pc_mux_id; // Mux selector for vectored IRQ PC + logic [5:0] u_exc_vec_pc_mux_id; // Mux selector for vectored IRQ PC + logic [5:0] exc_cause; + logic [1:0] trap_addr_mux; + + // ID performance counter signals + logic is_decoding; + + logic useincr_addr_ex; // Active when post increment + logic data_misaligned; + + logic mult_multicycle; + + // Jump and branch target and decision (EX->IF) + logic [31:0] jump_target_id, jump_target_ex; + logic branch_in_ex; + logic branch_decision; + + logic ctrl_busy; + logic if_busy; + logic lsu_busy; + logic apu_busy; + + logic [31:0] pc_ex; // PC of last executed branch or p.elw + + // ALU Control + logic alu_en_ex; + logic [ALU_OP_WIDTH-1:0] alu_operator_ex; + logic [31:0] alu_operand_a_ex; + logic [31:0] alu_operand_b_ex; + logic [31:0] alu_operand_c_ex; + logic [ 4:0] bmask_a_ex; + logic [ 4:0] bmask_b_ex; + logic [ 1:0] imm_vec_ext_ex; + logic [ 1:0] alu_vec_mode_ex; + logic alu_is_clpx_ex, alu_is_subrot_ex; + logic [ 1:0] alu_clpx_shift_ex; + + // Multiplier Control + logic [ 2:0] mult_operator_ex; + logic [31:0] mult_operand_a_ex; + logic [31:0] mult_operand_b_ex; + logic [31:0] mult_operand_c_ex; + logic mult_en_ex; + logic mult_sel_subword_ex; + logic [ 1:0] mult_signed_mode_ex; + logic [ 4:0] mult_imm_ex; + logic [31:0] mult_dot_op_a_ex; + logic [31:0] mult_dot_op_b_ex; + logic [31:0] mult_dot_op_c_ex; + logic [ 1:0] mult_dot_signed_ex; + logic mult_is_clpx_ex; + logic [ 1:0] mult_clpx_shift_ex; + logic mult_clpx_img_ex; + + // FPU + logic [C_PC-1:0] fprec_csr; + logic [C_RM-1:0] frm_csr; + logic [C_FFLAG-1:0] fflags; + logic [C_FFLAG-1:0] fflags_csr; + logic fflags_we; + + // APU + logic apu_en_ex; + logic [WAPUTYPE-1:0] apu_type_ex; + logic [APU_NDSFLAGS_CPU-1:0] apu_flags_ex; + logic [APU_WOP_CPU-1:0] apu_op_ex; + logic [1:0] apu_lat_ex; + logic [APU_NARGS_CPU-1:0][31:0] apu_operands_ex; + logic [5:0] apu_waddr_ex; + + logic [2:0][5:0] apu_read_regs; + logic [2:0] apu_read_regs_valid; + logic apu_read_dep; + logic [1:0][5:0] apu_write_regs; + logic [1:0] apu_write_regs_valid; + logic apu_write_dep; + + logic perf_apu_type; + logic perf_apu_cont; + logic perf_apu_dep; + logic perf_apu_wb; + + // Register Write Control + logic [5:0] regfile_waddr_ex; + logic regfile_we_ex; + logic [5:0] regfile_waddr_fw_wb_o; // From WB to ID + logic regfile_we_wb; + logic [31:0] regfile_wdata; + + logic [5:0] regfile_alu_waddr_ex; + logic regfile_alu_we_ex; + + logic [5:0] regfile_alu_waddr_fw; + logic regfile_alu_we_fw; + logic [31:0] regfile_alu_wdata_fw; + + // CSR control + logic csr_access_ex; + logic [1:0] csr_op_ex; + logic [23:0] mtvec, utvec; + logic [1:0] mtvec_mode; + logic [1:0] utvec_mode; + + logic csr_access; + logic [1:0] csr_op; + csr_num_e csr_addr; + csr_num_e csr_addr_int; + logic [31:0] csr_rdata; + logic [31:0] csr_wdata; + PrivLvl_t current_priv_lvl; + + // Stack Protection + logic stack_access; + logic [31:0] stack_base, + stack_limit; + + // Data Memory Control: From ID stage (id-ex pipe) <--> load store unit + logic data_we_ex; + logic [5:0] data_atop_ex; + logic data_buffer_ex; + logic [1:0] data_type_ex; + logic [1:0] data_sign_ext_ex; + logic [1:0] data_reg_offset_ex; + logic data_req_ex; + logic data_load_event_ex; + logic data_misaligned_ex; + + logic [31:0] lsu_rdata; + + // stall control + logic halt_if; + logic id_ready; + logic ex_ready; + + logic id_valid; + logic ex_valid; + logic wb_valid; + + logic lsu_ready_ex; + logic lsu_ready_wb; + + logic apu_ready_wb; + + // Signals between instruction core interface and pipe (if and id stages) + logic instr_req_int; // Id stage asserts a req to instruction core interface + + // Interrupts + logic m_irq_enable, u_irq_enable; + logic csr_irq_sec; + logic [31:0] mepc, uepc, depc; + + logic csr_save_cause; + logic csr_save_if; + logic csr_save_id; + logic csr_save_ex; + logic [6:0] csr_cause; + logic csr_restore_mret_id; + logic csr_restore_uret_id; + + logic csr_restore_dret_id; + + // debug mode and dcsr configuration + logic debug_mode; + logic [2:0] debug_cause; + logic debug_csr_save; + logic debug_single_step; + logic debug_ebreakm; + logic debug_ebreaku; + logic trigger_match; + + // Hardware loop controller signals + logic [N_HWLP-1:0] [31:0] hwlp_start; + logic [N_HWLP-1:0] [31:0] hwlp_end; + logic [N_HWLP-1:0] [31:0] hwlp_cnt; + + // used to write from CS registers to hardware loop registers + logic [N_HWLP_BITS-1:0] csr_hwlp_regid; + logic [2:0] csr_hwlp_we; + logic [31:0] csr_hwlp_data; + + // Performance Counters + logic perf_imiss; + logic perf_jump; + logic perf_jr_stall; + logic perf_ld_stall; + logic perf_pipeline_stall; + + //core busy signals + logic core_ctrl_firstfetch, core_busy_int, core_busy_q; + + //pmp signals (sent to PMP) + logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr; + logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg; + + //pmp signal (set by CS) + logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_cs; + logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_cs; + + logic data_req_pmp; + logic [31:0] data_addr_pmp; + logic data_gnt_pmp; + logic data_err_pmp; + logic data_err_ack; + logic instr_req_pmp; + logic instr_gnt_pmp; + logic [31:0] instr_addr_pmp; + logic instr_err_pmp; + + // interrupt signals + logic irq_pending; + logic [5:0] irq_id; + + //Simchecker signal + logic is_interrupt; + assign is_interrupt = (pc_mux_id == PC_EXCEPTION) && (exc_pc_mux_id == EXC_PC_IRQ); + assign m_exc_vec_pc_mux_id = (mtvec_mode == 2'b0) ? 6'h0 : exc_cause; + assign u_exc_vec_pc_mux_id = (utvec_mode == 2'b0) ? 6'h0 : exc_cause; + + // N_EXT_PERF_COUNTERS == 0 + assign ext_perf_counters_i = 'b0; + + // PULP_SECURE == 0 + assign irq_sec_i = 1'b0; + + // APU master signals + generate + if ( SHARED_FP ) begin + assign apu_master_type_o = apu_type_ex; + assign apu_master_flags_o = apu_flags_ex; + assign fflags_csr = apu_master_flags_i; + end + else begin + assign apu_master_type_o = '0; + assign apu_master_flags_o = '0; + assign fflags_csr = fflags; + end + endgenerate + +`ifdef APU_TRACE + + int apu_trace; + string fn; + string apu_waddr_trace; + + + // open/close output file for writing + initial + begin + wait(rst_ni == 1'b1); + // hart_id_i[10:5] and hart_id_i[3:0] mean cluster_id and core_id in PULP + $sformat(fn, "apu_trace_core_%h_%h.log", hart_id_i[10:5], hart_id_i[3:0]); + $display("[APU_TRACER] Output filename is: %s", fn); + apu_trace = $fopen(fn, "w"); + $fwrite(apu_trace, "time register \tresult\n"); + + while(1) begin + + @(negedge clk_i); + if (ex_stage_i.apu_valid == 1'b1) begin + if (ex_stage_i.apu_waddr>31) + $sformat(apu_waddr_trace, "f%d",ex_stage_i.apu_waddr[4:0]); + else + $sformat(apu_waddr_trace, "x%d",ex_stage_i.apu_waddr[4:0]); + $fwrite(apu_trace, "%t %s \t\t%h\n", $time, apu_waddr_trace, ex_stage_i.apu_result); + end + end + + end + + final + begin + $fclose(apu_trace); + end +`endif + + ////////////////////////////////////////////////////////////////////////////////////////////// + // ____ _ _ __ __ _ // + // / ___| | ___ ___| | __ | \/ | __ _ _ __ __ _ __ _ ___ _ __ ___ ___ _ __ | |_ // + // | | | |/ _ \ / __| |/ / | |\/| |/ _` | '_ \ / _` |/ _` |/ _ \ '_ ` _ \ / _ \ '_ \| __| // + // | |___| | (_) | (__| < | | | | (_| | | | | (_| | (_| | __/ | | | | | __/ | | | |_ // + // \____|_|\___/ \___|_|\_\ |_| |_|\__,_|_| |_|\__,_|\__, |\___|_| |_| |_|\___|_| |_|\__| // + // |___/ // + ////////////////////////////////////////////////////////////////////////////////////////////// + + logic clk; + + logic clock_en; + + + logic sleeping; + + + assign core_busy_o = core_ctrl_firstfetch ? 1'b1 : core_busy_q; + + // if we are sleeping on a barrier let's just wait on the instruction + // interface to finish loading instructions + assign core_busy_int = (PULP_CLUSTER & data_load_event_ex & data_req_o) ? (if_busy | apu_busy) : (if_busy | ctrl_busy | lsu_busy | apu_busy); + + assign clock_en = PULP_CLUSTER ? clock_en_i | core_busy_o : irq_pending | debug_req_i | core_busy_o; + + assign sleeping = ~core_busy_o; + + + always_ff @(posedge clk_i, negedge rst_ni) + begin + if (rst_ni == 1'b0) begin + core_busy_q <= 1'b0; + end else begin + core_busy_q <= core_busy_int; + end + end + + // main clock gate of the core + // generates all clocks except the one for the debug unit which is + // independent + cluster_clock_gating core_clock_gate_i + ( + .clk_i ( clk_i ), + .en_i ( clock_en ), + .test_en_i ( scan_cg_en_i ), + .clk_o ( clk ) + ); + + ////////////////////////////////////////////////// + // ___ _____ ____ _____ _ ____ _____ // + // |_ _| ___| / ___|_ _|/ \ / ___| ____| // + // | || |_ \___ \ | | / _ \| | _| _| // + // | || _| ___) || |/ ___ \ |_| | |___ // + // |___|_| |____/ |_/_/ \_\____|_____| // + // // + ////////////////////////////////////////////////// + riscv_if_stage + #( + .N_HWLP ( N_HWLP ), + .RDATA_WIDTH ( INSTR_RDATA_WIDTH ), + .FPU ( FPU ) + ) + if_stage_i + ( + .clk ( clk ), + .rst_n ( rst_ni ), + + // boot address + .boot_addr_i ( boot_addr_i[31:1] ), + + // debug mode halt address + .dm_halt_addr_i ( dm_halt_addr_i[31:2] ), + + // trap vector location + .m_trap_base_addr_i ( mtvec ), + .u_trap_base_addr_i ( utvec ), + .trap_addr_mux_i ( trap_addr_mux ), + + // instruction request control + .req_i ( instr_req_int ), + + // instruction cache interface + .instr_req_o ( instr_req_pmp ), + .instr_addr_o ( instr_addr_pmp ), + .instr_gnt_i ( instr_gnt_pmp ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_pmp_i ( instr_err_pmp ), + + // outputs to ID stage + .hwlp_dec_cnt_id_o ( hwlp_dec_cnt_id ), + .is_hwlp_id_o ( is_hwlp_id ), + .instr_valid_id_o ( instr_valid_id ), + .instr_rdata_id_o ( instr_rdata_id ), + .is_compressed_id_o ( is_compressed_id ), + .illegal_c_insn_id_o ( illegal_c_insn_id ), + .pc_if_o ( pc_if ), + .pc_id_o ( pc_id ), + .is_fetch_failed_o ( is_fetch_failed_id ), + + // control signals + .clear_instr_valid_i ( clear_instr_valid ), + .pc_set_i ( pc_set ), + + .mepc_i ( mepc ), // exception return address + .uepc_i ( uepc ), // exception return address + + .depc_i ( depc ), // debug return address + + .pc_mux_i ( pc_mux_id ), // sel for pc multiplexer + .exc_pc_mux_i ( exc_pc_mux_id ), + .m_exc_vec_pc_mux_i ( m_exc_vec_pc_mux_id ), + .u_exc_vec_pc_mux_i ( u_exc_vec_pc_mux_id ), + + // from hwloop registers + .hwlp_start_i ( hwlp_start ), + .hwlp_end_i ( hwlp_end ), + .hwlp_cnt_i ( hwlp_cnt ), + + + // Jump targets + .jump_target_id_i ( jump_target_id ), + .jump_target_ex_i ( jump_target_ex ), + + // pipeline stalls + .halt_if_i ( halt_if ), + .id_ready_i ( id_ready ), + + .if_busy_o ( if_busy ), + .perf_imiss_o ( perf_imiss ) + ); + + + ///////////////////////////////////////////////// + // ___ ____ ____ _____ _ ____ _____ // + // |_ _| _ \ / ___|_ _|/ \ / ___| ____| // + // | || | | | \___ \ | | / _ \| | _| _| // + // | || |_| | ___) || |/ ___ \ |_| | |___ // + // |___|____/ |____/ |_/_/ \_\____|_____| // + // // + ///////////////////////////////////////////////// + riscv_id_stage + #( + .PULP_HWLP ( PULP_HWLP ), + .N_HWLP ( N_HWLP ), + .PULP_SECURE ( PULP_SECURE ), + .USE_PMP ( USE_PMP ), + .A_EXTENSION ( A_EXTENSION ), + .APU ( APU ), + .FPU ( FPU ), + .PULP_ZFINX ( PULP_ZFINX ), + .FP_DIVSQRT ( FP_DIVSQRT ), + .SHARED_FP ( SHARED_FP ), + .SHARED_DSP_MULT ( SHARED_DSP_MULT ), + .SHARED_INT_MULT ( SHARED_INT_MULT ), + .SHARED_INT_DIV ( SHARED_INT_DIV ), + .SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ), + .WAPUTYPE ( WAPUTYPE ), + .APU_NARGS_CPU ( APU_NARGS_CPU ), + .APU_WOP_CPU ( APU_WOP_CPU ), + .APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ), + .APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU ), + .DEBUG_TRIGGER_EN ( DEBUG_TRIGGER_EN ) + ) + id_stage_i + ( + .clk ( clk ), + .rst_n ( rst_ni ), + + .scan_cg_en_i ( scan_cg_en_i ), + + // Processor Enable + .fetch_enable_i ( fetch_enable_i ), + .ctrl_busy_o ( ctrl_busy ), + .core_ctrl_firstfetch_o ( core_ctrl_firstfetch ), + .is_decoding_o ( is_decoding ), + + // Interface to instruction memory + .hwlp_dec_cnt_i ( hwlp_dec_cnt_id ), + .is_hwlp_i ( is_hwlp_id ), + .instr_valid_i ( instr_valid_id ), + .instr_rdata_i ( instr_rdata_id ), + .instr_req_o ( instr_req_int ), + + // Jumps and branches + .branch_in_ex_o ( branch_in_ex ), + .branch_decision_i ( branch_decision ), + .jump_target_o ( jump_target_id ), + + // IF and ID control signals + .clear_instr_valid_o ( clear_instr_valid ), + .pc_set_o ( pc_set ), + .pc_mux_o ( pc_mux_id ), + .exc_pc_mux_o ( exc_pc_mux_id ), + .exc_cause_o ( exc_cause ), + .trap_addr_mux_o ( trap_addr_mux ), + .illegal_c_insn_i ( illegal_c_insn_id ), + .is_compressed_i ( is_compressed_id ), + .is_fetch_failed_i ( is_fetch_failed_id ), + + .pc_if_i ( pc_if ), + .pc_id_i ( pc_id ), + + // Stalls + .halt_if_o ( halt_if ), + + .id_ready_o ( id_ready ), + .ex_ready_i ( ex_ready ), + .wb_ready_i ( lsu_ready_wb ), + + .id_valid_o ( id_valid ), + .ex_valid_i ( ex_valid ), + + // From the Pipeline ID/EX + .pc_ex_o ( pc_ex ), + + .alu_en_ex_o ( alu_en_ex ), + .alu_operator_ex_o ( alu_operator_ex ), + .alu_operand_a_ex_o ( alu_operand_a_ex ), + .alu_operand_b_ex_o ( alu_operand_b_ex ), + .alu_operand_c_ex_o ( alu_operand_c_ex ), + .bmask_a_ex_o ( bmask_a_ex ), + .bmask_b_ex_o ( bmask_b_ex ), + .imm_vec_ext_ex_o ( imm_vec_ext_ex ), + .alu_vec_mode_ex_o ( alu_vec_mode_ex ), + .alu_is_clpx_ex_o ( alu_is_clpx_ex ), + .alu_is_subrot_ex_o ( alu_is_subrot_ex ), + .alu_clpx_shift_ex_o ( alu_clpx_shift_ex ), + + .regfile_waddr_ex_o ( regfile_waddr_ex ), + .regfile_we_ex_o ( regfile_we_ex ), + + .regfile_alu_we_ex_o ( regfile_alu_we_ex ), + .regfile_alu_waddr_ex_o ( regfile_alu_waddr_ex ), + + // MUL + .mult_operator_ex_o ( mult_operator_ex ), // from ID to EX stage + .mult_en_ex_o ( mult_en_ex ), // from ID to EX stage + .mult_sel_subword_ex_o ( mult_sel_subword_ex ), // from ID to EX stage + .mult_signed_mode_ex_o ( mult_signed_mode_ex ), // from ID to EX stage + .mult_operand_a_ex_o ( mult_operand_a_ex ), // from ID to EX stage + .mult_operand_b_ex_o ( mult_operand_b_ex ), // from ID to EX stage + .mult_operand_c_ex_o ( mult_operand_c_ex ), // from ID to EX stage + .mult_imm_ex_o ( mult_imm_ex ), // from ID to EX stage + + .mult_dot_op_a_ex_o ( mult_dot_op_a_ex ), // from ID to EX stage + .mult_dot_op_b_ex_o ( mult_dot_op_b_ex ), // from ID to EX stage + .mult_dot_op_c_ex_o ( mult_dot_op_c_ex ), // from ID to EX stage + .mult_dot_signed_ex_o ( mult_dot_signed_ex ), // from ID to EX stage + .mult_is_clpx_ex_o ( mult_is_clpx_ex ), // from ID to EX stage + .mult_clpx_shift_ex_o ( mult_clpx_shift_ex ), // from ID to EX stage + .mult_clpx_img_ex_o ( mult_clpx_img_ex ), // from ID to EX stage + + // FPU + .frm_i ( frm_csr ), + + // APU + .apu_en_ex_o ( apu_en_ex ), + .apu_type_ex_o ( apu_type_ex ), + .apu_op_ex_o ( apu_op_ex ), + .apu_lat_ex_o ( apu_lat_ex ), + .apu_operands_ex_o ( apu_operands_ex ), + .apu_flags_ex_o ( apu_flags_ex ), + .apu_waddr_ex_o ( apu_waddr_ex ), + + .apu_read_regs_o ( apu_read_regs ), + .apu_read_regs_valid_o ( apu_read_regs_valid ), + .apu_read_dep_i ( apu_read_dep ), + .apu_write_regs_o ( apu_write_regs ), + .apu_write_regs_valid_o ( apu_write_regs_valid ), + .apu_write_dep_i ( apu_write_dep ), + .apu_perf_dep_o ( perf_apu_dep ), + .apu_busy_i ( apu_busy ), + + // CSR ID/EX + .csr_access_ex_o ( csr_access_ex ), + .csr_op_ex_o ( csr_op_ex ), + .current_priv_lvl_i ( current_priv_lvl ), + .csr_irq_sec_o ( csr_irq_sec ), + .csr_cause_o ( csr_cause ), + .csr_save_if_o ( csr_save_if ), // control signal to save pc + .csr_save_id_o ( csr_save_id ), // control signal to save pc + .csr_save_ex_o ( csr_save_ex ), // control signal to save pc + .csr_restore_mret_id_o ( csr_restore_mret_id ), // control signal to restore pc + .csr_restore_uret_id_o ( csr_restore_uret_id ), // control signal to restore pc + + .csr_restore_dret_id_o ( csr_restore_dret_id ), // control signal to restore pc + + .csr_save_cause_o ( csr_save_cause ), + + // hardware loop signals to IF hwlp controller + .hwlp_start_o ( hwlp_start ), + .hwlp_end_o ( hwlp_end ), + .hwlp_cnt_o ( hwlp_cnt ), + + // hardware loop signals from CSR + .csr_hwlp_regid_i ( csr_hwlp_regid ), + .csr_hwlp_we_i ( csr_hwlp_we ), + .csr_hwlp_data_i ( csr_hwlp_data ), + + // LSU + .data_req_ex_o ( data_req_ex ), // to load store unit + .data_we_ex_o ( data_we_ex ), // to load store unit + .atop_ex_o ( data_atop_ex ), + .buffer_ex_o ( data_buffer_ex ), + .data_type_ex_o ( data_type_ex ), // to load store unit + .data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit + .data_reg_offset_ex_o ( data_reg_offset_ex ), // to load store unit + .data_load_event_ex_o ( data_load_event_ex ), // to load store unit + + .data_misaligned_ex_o ( data_misaligned_ex ), // to load store unit + + .prepost_useincr_ex_o ( useincr_addr_ex ), + .data_misaligned_i ( data_misaligned ), + .data_err_i ( data_err_pmp ), + .data_err_ack_o ( data_err_ack ), + + + // Interrupt Signals + .irq_pending_i ( irq_pending ), // incoming interrupts + .irq_id_i ( irq_id ), + .irq_sec_i ( (PULP_SECURE) ? irq_sec_i : 1'b0 ), + .m_irq_enable_i ( m_irq_enable ), + .u_irq_enable_i ( u_irq_enable ), + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_id_o ), + + // Debug Signal + .debug_mode_o ( debug_mode ), + .debug_cause_o ( debug_cause ), + .debug_csr_save_o ( debug_csr_save ), + .debug_req_i ( debug_req_i ), + .debug_single_step_i ( debug_single_step ), + .debug_ebreakm_i ( debug_ebreakm ), + .debug_ebreaku_i ( debug_ebreaku ), + .trigger_match_i ( trigger_match ), + + // Forward Signals + .regfile_waddr_wb_i ( regfile_waddr_fw_wb_o), // Write address ex-wb pipeline + .regfile_we_wb_i ( regfile_we_wb ), // write enable for the register file + .regfile_wdata_wb_i ( regfile_wdata ), // write data to commit in the register file + + .regfile_alu_waddr_fw_i ( regfile_alu_waddr_fw ), + .regfile_alu_we_fw_i ( regfile_alu_we_fw ), + .regfile_alu_wdata_fw_i ( regfile_alu_wdata_fw ), + + // from ALU + .mult_multicycle_i ( mult_multicycle ), + + // Performance Counters + .perf_jump_o ( perf_jump ), + .perf_jr_stall_o ( perf_jr_stall ), + .perf_ld_stall_o ( perf_ld_stall ), + .perf_pipeline_stall_o ( perf_pipeline_stall ) + ); + + + ///////////////////////////////////////////////////// + // _______ __ ____ _____ _ ____ _____ // + // | ____\ \/ / / ___|_ _|/ \ / ___| ____| // + // | _| \ / \___ \ | | / _ \| | _| _| // + // | |___ / \ ___) || |/ ___ \ |_| | |___ // + // |_____/_/\_\ |____/ |_/_/ \_\____|_____| // + // // + ///////////////////////////////////////////////////// + riscv_ex_stage + #( + .FPU ( FPU ), + .FP_DIVSQRT ( FP_DIVSQRT ), + .SHARED_FP ( SHARED_FP ), + .SHARED_DSP_MULT ( SHARED_DSP_MULT ), + .SHARED_INT_DIV ( SHARED_INT_DIV ), + .APU_NARGS_CPU ( APU_NARGS_CPU ), + .APU_WOP_CPU ( APU_WOP_CPU ), + .APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ), + .APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU ) + ) + ex_stage_i + ( + // Global signals: Clock and active low asynchronous reset + .clk ( clk ), + .rst_n ( rst_ni ), + + // Alu signals from ID stage + .alu_en_i ( alu_en_ex ), + .alu_operator_i ( alu_operator_ex ), // from ID/EX pipe registers + .alu_operand_a_i ( alu_operand_a_ex ), // from ID/EX pipe registers + .alu_operand_b_i ( alu_operand_b_ex ), // from ID/EX pipe registers + .alu_operand_c_i ( alu_operand_c_ex ), // from ID/EX pipe registers + .bmask_a_i ( bmask_a_ex ), // from ID/EX pipe registers + .bmask_b_i ( bmask_b_ex ), // from ID/EX pipe registers + .imm_vec_ext_i ( imm_vec_ext_ex ), // from ID/EX pipe registers + .alu_vec_mode_i ( alu_vec_mode_ex ), // from ID/EX pipe registers + .alu_is_clpx_i ( alu_is_clpx_ex ), // from ID/EX pipe registers + .alu_is_subrot_i ( alu_is_subrot_ex ), // from ID/Ex pipe registers + .alu_clpx_shift_i ( alu_clpx_shift_ex ), // from ID/EX pipe registers + + // Multipler + .mult_operator_i ( mult_operator_ex ), // from ID/EX pipe registers + .mult_operand_a_i ( mult_operand_a_ex ), // from ID/EX pipe registers + .mult_operand_b_i ( mult_operand_b_ex ), // from ID/EX pipe registers + .mult_operand_c_i ( mult_operand_c_ex ), // from ID/EX pipe registers + .mult_en_i ( mult_en_ex ), // from ID/EX pipe registers + .mult_sel_subword_i ( mult_sel_subword_ex ), // from ID/EX pipe registers + .mult_signed_mode_i ( mult_signed_mode_ex ), // from ID/EX pipe registers + .mult_imm_i ( mult_imm_ex ), // from ID/EX pipe registers + .mult_dot_op_a_i ( mult_dot_op_a_ex ), // from ID/EX pipe registers + .mult_dot_op_b_i ( mult_dot_op_b_ex ), // from ID/EX pipe registers + .mult_dot_op_c_i ( mult_dot_op_c_ex ), // from ID/EX pipe registers + .mult_dot_signed_i ( mult_dot_signed_ex ), // from ID/EX pipe registers + .mult_is_clpx_i ( mult_is_clpx_ex ), // from ID/EX pipe registers + .mult_clpx_shift_i ( mult_clpx_shift_ex ), // from ID/EX pipe registers + .mult_clpx_img_i ( mult_clpx_img_ex ), // from ID/EX pipe registers + + .mult_multicycle_o ( mult_multicycle ), // to ID/EX pipe registers + + // FPU + .fpu_prec_i ( fprec_csr ), + .fpu_fflags_o ( fflags ), + .fpu_fflags_we_o ( fflags_we ), + + // APU + .apu_en_i ( apu_en_ex ), + .apu_op_i ( apu_op_ex ), + .apu_lat_i ( apu_lat_ex ), + .apu_operands_i ( apu_operands_ex ), + .apu_waddr_i ( apu_waddr_ex ), + .apu_flags_i ( apu_flags_ex ), + + .apu_read_regs_i ( apu_read_regs ), + .apu_read_regs_valid_i ( apu_read_regs_valid ), + .apu_read_dep_o ( apu_read_dep ), + .apu_write_regs_i ( apu_write_regs ), + .apu_write_regs_valid_i ( apu_write_regs_valid ), + .apu_write_dep_o ( apu_write_dep ), + + .apu_perf_type_o ( perf_apu_type ), + .apu_perf_cont_o ( perf_apu_cont ), + .apu_perf_wb_o ( perf_apu_wb ), + .apu_ready_wb_o ( apu_ready_wb ), + .apu_busy_o ( apu_busy ), + + // apu-interconnect + // handshake signals + .apu_master_req_o ( apu_master_req_o ), + .apu_master_ready_o ( apu_master_ready_o ), + .apu_master_gnt_i ( apu_master_gnt_i ), + // request channel + .apu_master_operands_o ( apu_master_operands_o ), + .apu_master_op_o ( apu_master_op_o ), + // response channel + .apu_master_valid_i ( apu_master_valid_i ), + .apu_master_result_i ( apu_master_result_i ), + + .lsu_en_i ( data_req_ex ), + .lsu_rdata_i ( lsu_rdata ), + + // interface with CSRs + .csr_access_i ( csr_access_ex ), + .csr_rdata_i ( csr_rdata ), + + // From ID Stage: Regfile control signals + .branch_in_ex_i ( branch_in_ex ), + .regfile_alu_waddr_i ( regfile_alu_waddr_ex ), + .regfile_alu_we_i ( regfile_alu_we_ex ), + + .regfile_waddr_i ( regfile_waddr_ex ), + .regfile_we_i ( regfile_we_ex ), + + // Output of ex stage pipeline + .regfile_waddr_wb_o ( regfile_waddr_fw_wb_o ), + .regfile_we_wb_o ( regfile_we_wb ), + .regfile_wdata_wb_o ( regfile_wdata ), + + // To IF: Jump and branch target and decision + .jump_target_o ( jump_target_ex ), + .branch_decision_o ( branch_decision ), + + // To ID stage: Forwarding signals + .regfile_alu_waddr_fw_o ( regfile_alu_waddr_fw ), + .regfile_alu_we_fw_o ( regfile_alu_we_fw ), + .regfile_alu_wdata_fw_o ( regfile_alu_wdata_fw ), + + // stall control + .is_decoding_i ( is_decoding ), + .lsu_ready_ex_i ( lsu_ready_ex ), + .lsu_err_i ( data_err_pmp ), + + .ex_ready_o ( ex_ready ), + .ex_valid_o ( ex_valid ), + .wb_ready_i ( lsu_ready_wb ) + ); + + + //////////////////////////////////////////////////////////////////////////////////////// + // _ ___ _ ____ ____ _____ ___ ____ _____ _ _ _ _ ___ _____ // + // | | / _ \ / \ | _ \ / ___|_ _/ _ \| _ \| ____| | | | | \ | |_ _|_ _| // + // | | | | | |/ _ \ | | | | \___ \ | || | | | |_) | _| | | | | \| || | | | // + // | |__| |_| / ___ \| |_| | ___) || || |_| | _ <| |___ | |_| | |\ || | | | // + // |_____\___/_/ \_\____/ |____/ |_| \___/|_| \_\_____| \___/|_| \_|___| |_| // + // // + //////////////////////////////////////////////////////////////////////////////////////// + + riscv_load_store_unit load_store_unit_i + ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + //output to data memory + .data_req_o ( data_req_pmp ), + .data_gnt_i ( data_gnt_pmp ), + .data_rvalid_i ( data_rvalid_i ), + .data_err_i ( data_err_pmp ), + + .data_addr_o ( data_addr_pmp ), + .data_we_o ( data_we_o ), + .data_atop_o ( data_atop_o ), + .data_be_o ( data_be_o ), + .data_buffer_o ( data_buffer_o ), + .data_wdata_o ( data_wdata_o ), + .data_rdata_i ( data_rdata_i ), + + // signal from ex stage + .data_we_ex_i ( data_we_ex ), + .data_atop_ex_i ( data_atop_ex ), + .data_buffer_ex_i ( data_buffer_ex ), + .data_type_ex_i ( data_type_ex ), + .data_wdata_ex_i ( alu_operand_c_ex ), + .data_reg_offset_ex_i ( data_reg_offset_ex ), + .data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension + + .data_rdata_ex_o ( lsu_rdata ), + .data_req_ex_i ( data_req_ex ), + .operand_a_ex_i ( alu_operand_a_ex ), + .operand_b_ex_i ( alu_operand_b_ex ), + .addr_useincr_ex_i ( useincr_addr_ex ), + + .data_misaligned_ex_i ( data_misaligned_ex ), // from ID/EX pipeline + .data_misaligned_o ( data_misaligned ), + + // control signals + .lsu_ready_ex_o ( lsu_ready_ex ), + .lsu_ready_wb_o ( lsu_ready_wb ), + + .ex_valid_i ( ex_valid ), + .busy_o ( lsu_busy ) + ); + + assign wb_valid = lsu_ready_wb & apu_ready_wb; + + + ////////////////////////////////////// + // ____ ____ ____ // + // / ___/ ___|| _ \ ___ // + // | | \___ \| |_) / __| // + // | |___ ___) | _ <\__ \ // + // \____|____/|_| \_\___/ // + // // + // Control and Status Registers // + ////////////////////////////////////// + + riscv_cs_registers + #( + .A_EXTENSION ( A_EXTENSION ), + .FPU ( FPU ), + .APU ( APU ), + .PULP_SECURE ( PULP_SECURE ), + .USE_PMP ( USE_PMP ), + .N_PMP_ENTRIES ( N_PMP_ENTRIES ), + .NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ), + .PULP_HWLP ( PULP_HWLP ), + .DEBUG_TRIGGER_EN ( DEBUG_TRIGGER_EN ) + ) + cs_registers_i + ( + .clk ( clk ), + .rst_n ( rst_ni ), + + // Hart ID from outside + .hart_id_i ( hart_id_i ), + .mtvec_o ( mtvec ), + .utvec_o ( utvec ), + .mtvec_mode_o ( mtvec_mode ), + .utvec_mode_o ( utvec_mode ), + // boot address + .boot_addr_i ( boot_addr_i[31:1] ), + // Interface to CSRs (SRAM like) + .csr_access_i ( csr_access ), + .csr_addr_i ( csr_addr ), + .csr_wdata_i ( csr_wdata ), + .csr_op_i ( csr_op ), + .csr_rdata_o ( csr_rdata ), + + .frm_o ( frm_csr ), + .fprec_o ( fprec_csr ), + .fflags_i ( fflags_csr ), + .fflags_we_i ( fflags_we ), + + // Interrupt related control signals + .m_irq_enable_o ( m_irq_enable ), + .u_irq_enable_o ( u_irq_enable ), + .csr_irq_sec_i ( csr_irq_sec ), + .sec_lvl_o ( sec_lvl_o ), + .mepc_o ( mepc ), + .uepc_o ( uepc ), + .irq_software_i ( irq_software_i ), + .irq_timer_i ( irq_timer_i ), + .irq_external_i ( irq_external_i ), + .irq_fast_i ( irq_fast_i ), + .irq_pending_o ( irq_pending ), // IRQ to ID/Controller + .irq_id_o ( irq_id ), + // debug + .debug_mode_i ( debug_mode ), + .debug_cause_i ( debug_cause ), + .debug_csr_save_i ( debug_csr_save ), + .depc_o ( depc ), + .debug_single_step_o ( debug_single_step ), + .debug_ebreakm_o ( debug_ebreakm ), + .debug_ebreaku_o ( debug_ebreaku ), + .trigger_match_o ( trigger_match ), + + .priv_lvl_o ( current_priv_lvl ), + + .pmp_addr_o ( pmp_addr_cs ), + .pmp_cfg_o ( pmp_cfg_cs ), + + .pc_if_i ( pc_if ), + .pc_id_i ( pc_id ), + .pc_ex_i ( pc_ex ), + + .csr_save_if_i ( csr_save_if ), + .csr_save_id_i ( csr_save_id ), + .csr_save_ex_i ( csr_save_ex ), + .csr_restore_mret_i ( csr_restore_mret_id ), + .csr_restore_uret_i ( csr_restore_uret_id ), + + .csr_restore_dret_i ( csr_restore_dret_id ), + + .csr_cause_i ( csr_cause ), + .csr_save_cause_i ( csr_save_cause ), + + // from hwloop registers + .hwlp_start_i ( hwlp_start ), + .hwlp_end_i ( hwlp_end ), + .hwlp_cnt_i ( hwlp_cnt ), + + .hwlp_regid_o ( csr_hwlp_regid ), + .hwlp_we_o ( csr_hwlp_we ), + .hwlp_data_o ( csr_hwlp_data ), + + .stack_base_o ( stack_base ), + .stack_limit_o ( stack_limit ), + + // performance counter related signals + .id_valid_i ( id_valid ), + .is_compressed_i ( is_compressed_id ), + .is_decoding_i ( is_decoding ), + + .imiss_i ( perf_imiss ), + .pc_set_i ( pc_set ), + .jump_i ( perf_jump ), + .branch_i ( branch_in_ex ), + .branch_taken_i ( branch_decision ), + .ld_stall_i ( perf_ld_stall ), + .jr_stall_i ( perf_jr_stall ), + .pipeline_stall_i ( perf_pipeline_stall ), + + .apu_typeconflict_i ( perf_apu_type ), + .apu_contention_i ( perf_apu_cont ), + .apu_dep_i ( perf_apu_dep ), + .apu_wb_i ( perf_apu_wb ), + + .mem_load_i ( data_req_o & data_gnt_i & (~data_we_o) ), + .mem_store_i ( data_req_o & data_gnt_i & data_we_o ) + + ); + + // CSR access + assign csr_access = csr_access_ex; + assign csr_addr = csr_addr_int; + assign csr_wdata = alu_operand_a_ex; + assign csr_op = csr_op_ex; + + assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0); + + + + /////////////////////////// + // ____ __ __ ____ // + // | _ \| \/ | _ \ // + // | |_) | |\/| | |_) | // + // | __/| | | | __/ // + // |_| |_| |_|_| // + // // + /////////////////////////// + + generate + if(PULP_SECURE && USE_PMP) begin : RISCY_PMP + riscv_pmp + #( + .N_PMP_ENTRIES(N_PMP_ENTRIES) + ) + pmp_unit_i + ( + .clk ( clk ), + .rst_n ( rst_ni ), + + .pmp_privil_mode_i ( current_priv_lvl ), + + .pmp_addr_i ( pmp_addr ), + .pmp_cfg_i ( pmp_cfg ), + + + .data_req_i ( data_req_pmp ), + .data_addr_i ( data_addr_pmp ), + .data_we_i ( data_we_o ), + .data_gnt_o ( data_gnt_pmp ), + + .data_req_o ( data_req_o ), + .data_gnt_i ( data_gnt_i ), + .data_addr_o ( data_addr_o ), + .data_err_o ( data_err_pmp ), + .data_err_ack_i ( data_err_ack ), + + .instr_req_i ( instr_req_pmp ), + .instr_addr_i ( instr_addr_pmp ), + .instr_gnt_o ( instr_gnt_pmp ), + + .instr_req_o ( instr_req_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_addr_o ( instr_addr_o ), + .instr_err_o ( instr_err_pmp ) + ); + end else begin + assign instr_req_o = instr_req_pmp; + assign instr_addr_o = instr_addr_pmp; + assign instr_gnt_pmp = instr_gnt_i; + assign instr_err_pmp = 1'b0; + + assign data_req_o = data_req_pmp; + assign data_addr_o = data_addr_pmp; + assign data_gnt_pmp = data_gnt_i; + assign data_err_pmp = 1'b0; + end + + + always_comb begin + pmp_addr = pmp_addr_cs; + pmp_cfg = pmp_cfg_cs; + + //external configuration has priority over CS + if (pmp_conf_override_i) begin + pmp_addr = pmp_addr_i; + pmp_cfg = pmp_cfg_i; + end + end + endgenerate + + +`ifdef TRACE_EXECUTION + + riscv_tracer riscv_tracer_i + ( + .clk ( clk_i ), // always-running clock for tracing + .rst_n ( rst_ni ), + + .fetch_enable ( fetch_enable_i ), + .hart_id_i ( hart_id_i ), + + .pc ( id_stage_i.pc_id_i ), + .instr ( id_stage_i.instr ), + .controller_state_i ( id_stage_i.controller_i.ctrl_fsm_cs ), + .compressed ( id_stage_i.is_compressed_i ), + .id_valid ( id_stage_i.id_valid_o ), + .is_decoding ( id_stage_i.is_decoding_o ), + .pipe_flush ( id_stage_i.controller_i.pipe_flush_i ), + .mret ( id_stage_i.controller_i.mret_insn_i ), + .uret ( id_stage_i.controller_i.uret_insn_i ), + .dret ( id_stage_i.controller_i.dret_insn_i ), + .ecall ( id_stage_i.controller_i.ecall_insn_i ), + .ebreak ( id_stage_i.controller_i.ebrk_insn_i ), + .fence ( id_stage_i.controller_i.fencei_insn_i), + .rs1_value ( id_stage_i.operand_a_fw_id ), + .rs2_value ( id_stage_i.operand_b_fw_id ), + .rs3_value ( id_stage_i.alu_operand_c ), + .rs2_value_vec ( id_stage_i.alu_operand_b ), + + .rs1_is_fp ( id_stage_i.regfile_fp_a ), + .rs2_is_fp ( id_stage_i.regfile_fp_b ), + .rs3_is_fp ( id_stage_i.regfile_fp_c ), + .rd_is_fp ( id_stage_i.regfile_fp_d ), + + .ex_valid ( ex_valid ), + .ex_reg_addr ( regfile_alu_waddr_fw ), + .ex_reg_we ( regfile_alu_we_fw ), + .ex_reg_wdata ( regfile_alu_wdata_fw ), + + .ex_data_addr ( data_addr_o ), + .ex_data_req ( data_req_o ), + .ex_data_gnt ( data_gnt_i ), + .ex_data_we ( data_we_o ), + .ex_data_wdata ( data_wdata_o ), + .data_misaligned ( data_misaligned ), + + .wb_bypass ( ex_stage_i.branch_in_ex_i ), + + .wb_valid ( wb_valid ), + .wb_reg_addr ( regfile_waddr_fw_wb_o ), + .wb_reg_we ( regfile_we_wb ), + .wb_reg_wdata ( regfile_wdata ), + + .imm_u_type ( id_stage_i.imm_u_type ), + .imm_uj_type ( id_stage_i.imm_uj_type ), + .imm_i_type ( id_stage_i.imm_i_type ), + .imm_iz_type ( id_stage_i.imm_iz_type[11:0] ), + .imm_z_type ( id_stage_i.imm_z_type ), + .imm_s_type ( id_stage_i.imm_s_type ), + .imm_sb_type ( id_stage_i.imm_sb_type ), + .imm_s2_type ( id_stage_i.imm_s2_type ), + .imm_s3_type ( id_stage_i.imm_s3_type ), + .imm_vs_type ( id_stage_i.imm_vs_type ), + .imm_vu_type ( id_stage_i.imm_vu_type ), + .imm_shuffle_type ( id_stage_i.imm_shuffle_type ), + .imm_clip_type ( id_stage_i.instr_rdata_i[11:7] ) + ); +`endif + +`ifdef PRINT_CORE_MEM_ACCESSES + always_comb begin + if (data_req_o && data_gnt_i) begin + if (data_we_o) begin + $display("Core %0d,%0d writes 0x%08x.", cluster_id_i, core_id_i, data_addr_o); + end else begin + $display("Core %0d,%0d reads 0x%08x.", cluster_id_i, core_id_i, data_addr_o); + end + end + end + `endif + +endmodule \ No newline at end of file diff --git a/hw/deps/riscv/riscv_cs_registers.sv b/hw/deps/riscv/riscv_cs_registers.sv new file mode 100644 index 0000000..57588a5 --- /dev/null +++ b/hw/deps/riscv/riscv_cs_registers.sv @@ -0,0 +1,1646 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Sven Stucki - svstucki@student.ethz.ch // +// // +// Additional contributions by: // +// Andreas Traber - atraber@iis.ee.ethz.ch // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// Andrea Bettati - andrea.bettati@studenti.unipr.it // +// // +// Design Name: Control and Status Registers // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Control and Status Registers (CSRs) loosely following the // +// RiscV draft priviledged instruction set spec (v1.9) // +// Added Floating point support // +// // +//////////////////////////////////////////////////////////////////////////////// + +import riscv_defines::*; + +`ifndef PULP_FPGA_EMUL + `ifdef SYNTHESIS + `define ASIC_SYNTHESIS + `endif +`endif + +module riscv_cs_registers +#( + parameter N_HWLP = 2, + parameter N_HWLP_BITS = $clog2(N_HWLP), + parameter APU = 0, + parameter A_EXTENSION = 0, + parameter FPU = 0, + parameter PULP_SECURE = 0, + parameter USE_PMP = 0, + parameter N_PMP_ENTRIES = 16, + parameter NUM_MHPMCOUNTERS = 1, + parameter PULP_HWLP = 0, + parameter DEBUG_TRIGGER_EN = 1 +) +( + // Clock and Reset + input logic clk, + input logic rst_n, + + // Hart ID + input logic [31:0] hart_id_i, + output logic [23:0] mtvec_o, + output logic [23:0] utvec_o, + output logic [1:0] mtvec_mode_o, + output logic [1:0] utvec_mode_o, + + // Used for boot address + input logic [30:0] boot_addr_i, + + // Interface to registers (SRAM like) + input logic csr_access_i, + input riscv_defines::csr_num_e csr_addr_i, + input logic [31:0] csr_wdata_i, + input logic [1:0] csr_op_i, + output logic [31:0] csr_rdata_o, + + output logic [2:0] frm_o, + output logic [C_PC-1:0] fprec_o, + input logic [C_FFLAG-1:0] fflags_i, + input logic fflags_we_i, + + // Interrupts + // IRQ lines from int_controller + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [47:0] irq_fast_i, + + output logic m_irq_enable_o, + output logic u_irq_enable_o, + // IRQ req to ID/controller + output logic irq_pending_o, //used to wake up the WFI and to signal interrupts to controller + output logic [5:0] irq_id_o, + + //csr_irq_sec_i is always 0 if PULP_SECURE is zero + input logic csr_irq_sec_i, + output logic sec_lvl_o, + output logic [31:0] mepc_o, + output logic [31:0] uepc_o, + + // debug + input logic debug_mode_i, + input logic [2:0] debug_cause_i, + input logic debug_csr_save_i, + output logic [31:0] depc_o, + output logic debug_single_step_o, + output logic debug_ebreakm_o, + output logic debug_ebreaku_o, + output logic trigger_match_o, + + + output logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_o, + output logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_o, + + output PrivLvl_t priv_lvl_o, + + input logic [31:0] pc_if_i, + input logic [31:0] pc_id_i, + input logic [31:0] pc_ex_i, + + input logic csr_save_if_i, + input logic csr_save_id_i, + input logic csr_save_ex_i, + + input logic csr_restore_mret_i, + input logic csr_restore_uret_i, + + input logic csr_restore_dret_i, + //coming from controller + input logic [6:0] csr_cause_i, + //coming from controller + input logic csr_save_cause_i, + // Hardware loops + input logic [N_HWLP-1:0] [31:0] hwlp_start_i, + input logic [N_HWLP-1:0] [31:0] hwlp_end_i, + input logic [N_HWLP-1:0] [31:0] hwlp_cnt_i, + + output logic [31:0] hwlp_data_o, + output logic [N_HWLP_BITS-1:0] hwlp_regid_o, + output logic [2:0] hwlp_we_o, + + // Stack Protection + output logic [31:0] stack_base_o, + output logic [31:0] stack_limit_o, + + // Performance Counters + input logic id_valid_i, // ID stage is done + input logic is_compressed_i, // compressed instruction in ID + input logic is_decoding_i, // controller is in DECODE state + + input logic imiss_i, // instruction fetch + input logic pc_set_i, // pc was set to a new value + input logic jump_i, // jump instruction seen (j, jr, jal, jalr) + input logic branch_i, // branch instruction seen (bf, bnf) + input logic branch_taken_i, // branch was taken + input logic ld_stall_i, // load use hazard + input logic jr_stall_i, // jump register use hazard + input logic pipeline_stall_i, // extra cycles from elw + + input logic apu_typeconflict_i, + input logic apu_contention_i, + input logic apu_dep_i, + input logic apu_wb_i, + + input logic mem_load_i, // load from memory in this cycle + input logic mem_store_i // store to memory in this cycle + +); + + localparam NUM_HPM_EVENTS = 16; + + localparam MTVEC_MODE = 2'b01; + + localparam MAX_N_PMP_ENTRIES = 16; + localparam MAX_N_PMP_CFG = 4; + localparam N_PMP_CFG = N_PMP_ENTRIES % 4 == 0 ? N_PMP_ENTRIES/4 : N_PMP_ENTRIES/4 + 1; + + + `define MSTATUS_UIE_BITS 0 + `define MSTATUS_SIE_BITS 1 + `define MSTATUS_MIE_BITS 3 + `define MSTATUS_UPIE_BITS 4 + `define MSTATUS_SPIE_BITS 5 + `define MSTATUS_MPIE_BITS 7 + `define MSTATUS_SPP_BITS 8 + `define MSTATUS_MPP_BITS 12:11 + `define MSTATUS_MPRV_BITS 17 + + // misa + localparam logic [1:0] MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32 + localparam logic [31:0] MISA_VALUE = + (32'(A_EXTENSION) << 0) // A - Atomic Instructions extension + | (1 << 2) // C - Compressed extension + | (0 << 3) // D - Double precision floating-point extension + | (0 << 4) // E - RV32E base ISA + | (32'(FPU) << 5) // F - Single precision floating-point extension + | (1 << 8) // I - RV32I/64I/128I base ISA + | (1 << 12) // M - Integer Multiply/Divide extension + | (0 << 13) // N - User level interrupts supported + | (0 << 18) // S - Supervisor mode implemented + | (32'(PULP_SECURE) << 20) // U - User mode implemented + | (1 << 23) // X - Non-standard extensions present + | (32'(MXL) << 30); // M-XLEN + + typedef struct packed { + logic uie; + // logic sie; - unimplemented, hardwired to '0 + // logic hie; - unimplemented, hardwired to '0 + logic mie; + logic upie; + // logic spie; - unimplemented, hardwired to '0 + // logic hpie; - unimplemented, hardwired to '0 + logic mpie; + // logic spp; - unimplemented, hardwired to '0 + // logic[1:0] hpp; - unimplemented, hardwired to '0 + PrivLvl_t mpp; + logic mprv; + } Status_t; + + typedef struct packed{ + logic [31:28] xdebugver; + logic [27:16] zero2; + logic ebreakm; + logic zero1; + logic ebreaks; + logic ebreaku; + logic stepie; + logic stopcount; + logic stoptime; + logic [8:6] cause; + logic zero0; + logic mprven; + logic nmip; + logic step; + PrivLvl_t prv; + } Dcsr_t; + +`ifndef SYNTHESIS + initial + begin + $display("[CORE] Core settings: PULP_SECURE = %d, N_PMP_ENTRIES = %d, N_PMP_CFG %d",PULP_SECURE, N_PMP_ENTRIES, N_PMP_CFG); + end +`endif + + typedef struct packed { + logic [MAX_N_PMP_ENTRIES-1:0] [31:0] pmpaddr; + //logic [MAX_N_PMP_CFG-1:0] [31:0] pmpcfg_packed; + logic [MAX_N_PMP_ENTRIES-1:0] [ 7:0] pmpcfg; + } Pmp_t; + + typedef logic [MAX_N_PMP_CFG-1:0][31:0] pmpcfg_packed_t; + + // CSR update logic + logic [31:0] csr_wdata_int; + logic [31:0] csr_rdata_int; + logic csr_we_int; + logic [C_RM-1:0] frm_q, frm_n; + logic [C_FFLAG-1:0] fflags_q, fflags_n; + logic [C_PC-1:0] fprec_q, fprec_n; + + // Interrupt control signals + logic [31:0] mepc_q, mepc_n; + logic [31:0] uepc_q, uepc_n; + // Trigger + logic [31:0] tmatch_control_rdata; + logic [31:0] tmatch_value_rdata; + // Debug + Dcsr_t dcsr_q, dcsr_n; + logic [31:0] depc_q, depc_n; + logic [31:0] dscratch0_q, dscratch0_n; + logic [31:0] dscratch1_q, dscratch1_n; + logic [31:0] mscratch_q, mscratch_n; + + logic [31:0] exception_pc; + Status_t mstatus_q, mstatus_n; + logic [ 6:0] mcause_q, mcause_n; + logic [ 6:0] ucause_q, ucause_n; + logic [31:0] stack_base_q, stack_base_n, + stack_size_q, stack_size_n; + //not implemented yet + logic [23:0] mtvec_n, mtvec_q; + logic [23:0] utvec_n, utvec_q; + logic [ 1:0] mtvec_mode_n, mtvec_mode_q; + logic [ 1:0] utvec_mode_n, utvec_mode_q; + + Interrupts_t mip; + logic [31:0] mip1; + Interrupts_t mie_q, mie_n; + logic [31:0] mie1_q, mie1_n; + //machine enabled interrupt pending + Interrupts_t menip; + logic [31:0] menip1; + + logic is_irq; + PrivLvl_t priv_lvl_n, priv_lvl_q; + + Pmp_t pmp_reg_q; + Pmp_t pmp_reg_n; + pmpcfg_packed_t pmpcfg_packed_q; + pmpcfg_packed_t pmpcfg_packed_n; + + //clock gating for pmp regs + logic [MAX_N_PMP_ENTRIES-1:0] pmpaddr_we; + logic [MAX_N_PMP_ENTRIES-1:0] pmpcfg_we; + + // Performance Counter Signals + logic id_valid_q; + + + // performance counters + logic [31:0] [63:0] mhpmcounter_q; + logic [31:0] [63:0] mhpmcounter_n; + + // event enable + logic [31:0] [31:0] mhpmevent_q; + logic [31:0] [31:0] mhpmevent_n; + + // performance counter enable + logic [31:0] mcountinhibit_q; + logic [31:0] mcountinhibit_n; + + logic [NUM_HPM_EVENTS-1:0] hpm_events; // events for performance counters + + Interrupts_t irq_req; + logic [31:0] irq_req1; + + assign is_irq = csr_cause_i[6]; + + assign irq_req.irq_software = irq_software_i; + assign irq_req.irq_timer = irq_timer_i; + assign irq_req.irq_external = irq_external_i; + assign irq_req.irq_fast = irq_fast_i[15:0]; + assign irq_req1 = irq_fast_i[47:16]; + + // mip CSR is purely combintational + // must be able to re-enable the clock upon WFI + assign mip.irq_software = irq_req.irq_software; + assign mip.irq_timer = irq_req.irq_timer; + assign mip.irq_external = irq_req.irq_external; + assign mip.irq_fast = irq_req.irq_fast; + assign mip1 = irq_req1; + + // menip signal the controller + assign menip.irq_software = irq_req.irq_software & mie_q.irq_software; + assign menip.irq_timer = irq_req.irq_timer & mie_q.irq_timer; + assign menip.irq_external = irq_req.irq_external & mie_q.irq_external; + assign menip.irq_fast = irq_req.irq_fast & mie_q.irq_fast; + assign menip1 = irq_req1 & mie1_q; + + + + //////////////////////////////////////////// + // ____ ____ ____ ____ // + // / ___/ ___|| _ \ | _ \ ___ __ _ // + // | | \___ \| |_) | | |_) / _ \/ _` | // + // | |___ ___) | _ < | _ < __/ (_| | // + // \____|____/|_| \_\ |_| \_\___|\__, | // + // |___/ // + //////////////////////////////////////////// + + // NOTE!!!: Any new CSR register added in this file must also be + // added to the valid CSR register list riscv_decoder.v + + genvar j; + + +if(PULP_SECURE==1) begin + // read logic + always_comb + begin + casex (csr_addr_i) + // fcsr: Floating-Point Control and Status Register (frm + fflags). + CSR_FFLAGS : csr_rdata_int = (FPU == 1) ? {27'b0, fflags_q} : '0; + CSR_FRM : csr_rdata_int = (FPU == 1) ? {29'b0, frm_q} : '0; + CSR_FCSR : csr_rdata_int = (FPU == 1) ? {24'b0, frm_q, fflags_q} : '0; + FPREC : csr_rdata_int = (FPU == 1) ? {27'b0, fprec_q} : '0; // Optional precision control for FP DIV/SQRT Unit + + // mstatus + CSR_MSTATUS: csr_rdata_int = { + 14'b0, + mstatus_q.mprv, + 4'b0, + mstatus_q.mpp, + 3'b0, + mstatus_q.mpie, + 2'h0, + mstatus_q.upie, + mstatus_q.mie, + 2'h0, + mstatus_q.uie + }; + + // misa: machine isa register + CSR_MISA: csr_rdata_int = MISA_VALUE; + + // mie: machine interrupt enable + CSR_MIE: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mie_q.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mie_q.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mie_q.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mie_q.irq_fast; + end + + // mie1: machine interrupt enable for fast interrupt extension (irq_fast_i[47:16]) + CSR_MIE1: csr_rdata_int = mie1_q; + + // mtvec: machine trap-handler base address + CSR_MTVEC: csr_rdata_int = {mtvec_q, 6'h0, mtvec_mode_q}; + // mscratch: machine scratch + CSR_MSCRATCH: csr_rdata_int = mscratch_q; + // mepc: exception program counter + CSR_MEPC: csr_rdata_int = mepc_q; + // mcause: exception cause + CSR_MCAUSE: csr_rdata_int = {mcause_q[6], 25'b0, mcause_q[5:0]}; + // mip: interrupt pending + CSR_MIP: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mip.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mip.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mip.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast; + end + + // mip1: machine interrupt pending for fast interrupt extension (irq_fast_i[47:16]) + CSR_MIP1: csr_rdata_int = mip1; + + // mhartid: unique hardware thread id + CSR_MHARTID: csr_rdata_int = hart_id_i; + + // unimplemented, read 0 CSRs + CSR_MVENDORID, + CSR_MARCHID, + CSR_MIMPID, + CSR_MTVAL, + CSR_MCOUNTEREN : + csr_rdata_int = 'b0; + + CSR_TSELECT, + CSR_TDATA3, + CSR_MCONTEXT, + CSR_SCONTEXT: + csr_rdata_int = 'b0; // Always read 0 + CSR_TDATA1: + csr_rdata_int = tmatch_control_rdata; + CSR_TDATA2: + csr_rdata_int = tmatch_value_rdata; + + CSR_DCSR: + csr_rdata_int = dcsr_q;// + CSR_DPC: + csr_rdata_int = depc_q; + CSR_DSCRATCH0: + csr_rdata_int = dscratch0_q;// + CSR_DSCRATCH1: + csr_rdata_int = dscratch1_q;// + + // Hardware Performance Monitor + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: + csr_rdata_int = mhpmcounter_q[csr_addr_i[4:0]][31:0]; + + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: + csr_rdata_int = mhpmcounter_q[csr_addr_i[4:0]][63:32]; + + CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit_q; + + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, + CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11, + CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, + CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, + CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, + CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, + CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: + csr_rdata_int = mhpmevent_q[csr_addr_i[4:0]]; + + // hardware loops (not official) + HWLoop0_START : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_start_i[0]; + HWLoop0_END : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_end_i[0] ; + HWLoop0_COUNTER: csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_cnt_i[0] ; + HWLoop1_START : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_start_i[1]; + HWLoop1_END : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_end_i[1] ; + HWLoop1_COUNTER: csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_cnt_i[1] ; + + // PMP config registers + CSR_PMPCFG0: csr_rdata_int = USE_PMP ? pmpcfg_packed_q[0] : '0; + CSR_PMPCFG1: csr_rdata_int = USE_PMP ? pmpcfg_packed_q[1] : '0; + CSR_PMPCFG2: csr_rdata_int = USE_PMP ? pmpcfg_packed_q[2] : '0; + CSR_PMPCFG3: csr_rdata_int = USE_PMP ? pmpcfg_packed_q[3] : '0; + + CSR_PMPADDR_RANGE_X : + csr_rdata_int = USE_PMP ? pmp_reg_q.pmpaddr[csr_addr_i[3:0]] : '0; + + /* USER CSR */ + // ustatus + CSR_USTATUS: csr_rdata_int = { + 27'b0, + mstatus_q.upie, + 3'h0, + mstatus_q.uie + }; + // utvec: user trap-handler base address + CSR_UTVEC: csr_rdata_int = {utvec_q, 6'h0, utvec_mode_q}; + // duplicated mhartid: unique hardware thread id (not official) + UHARTID: csr_rdata_int = hart_id_i; + // uepc: exception program counter + CSR_UEPC: csr_rdata_int = uepc_q; + // ucause: exception cause + CSR_UCAUSE: csr_rdata_int = {ucause_q[6], 25'h0, ucause_q[5:0]}; + + // current priv level (not official) + PRIVLV: csr_rdata_int = {30'h0, priv_lvl_q}; + + default: + csr_rdata_int = '0; + endcase + end +end else begin //PULP_SECURE == 0 + // read logic + always_comb + begin + + case (csr_addr_i) + // fcsr: Floating-Point Control and Status Register (frm + fflags). + CSR_FFLAGS : csr_rdata_int = (FPU == 1) ? {27'b0, fflags_q} : '0; + CSR_FRM : csr_rdata_int = (FPU == 1) ? {29'b0, frm_q} : '0; + CSR_FCSR : csr_rdata_int = (FPU == 1) ? {24'b0, frm_q, fflags_q} : '0; + FPREC : csr_rdata_int = (FPU == 1) ? {27'b0, fprec_q} : '0; // Optional precision control for FP DIV/SQRT Unit + // mstatus: always M-mode, contains IE bit + CSR_MSTATUS: csr_rdata_int = { + 14'b0, + mstatus_q.mprv, + 4'b0, + mstatus_q.mpp, + 3'b0, + mstatus_q.mpie, + 2'h0, + mstatus_q.upie, + mstatus_q.mie, + 2'h0, + mstatus_q.uie + }; + // misa: machine isa register + CSR_MISA: csr_rdata_int = MISA_VALUE; + // mie: machine interrupt enable + CSR_MIE: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mie_q.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mie_q.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mie_q.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mie_q.irq_fast; + end + + // mie1: machine interrupt enable for fast interrupt extension (irq_fast_i[47:16]) + CSR_MIE1: csr_rdata_int = mie1_q; + // mtvec: machine trap-handler base address + CSR_MTVEC: csr_rdata_int = {mtvec_q, 6'h0, mtvec_mode_q}; + // mscratch: machine scratch + CSR_MSCRATCH: csr_rdata_int = mscratch_q; + // mepc: exception program counter + CSR_MEPC: csr_rdata_int = mepc_q; + // mcause: exception cause + CSR_MCAUSE: csr_rdata_int = {mcause_q[6], 25'b0, mcause_q[5:0]}; + // mip: interrupt pending + CSR_MIP: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mip.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mip.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mip.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast; + end + // mip1: machine interrupt pending for fast interrupt extension (irq_fast_i[47:16]) + CSR_MIP1: csr_rdata_int = mip1; + // mhartid: unique hardware thread id + CSR_MHARTID: csr_rdata_int = hart_id_i; + + // unimplemented, read 0 CSRs + CSR_MVENDORID, + CSR_MARCHID, + CSR_MIMPID, + CSR_MTVAL, + CSR_MCOUNTEREN : + csr_rdata_int = 'b0; + + CSR_TSELECT, + CSR_TDATA3, + CSR_MCONTEXT, + CSR_SCONTEXT: + csr_rdata_int = 'b0; // Always read 0 + CSR_TDATA1: + csr_rdata_int = tmatch_control_rdata; + CSR_TDATA2: + csr_rdata_int = tmatch_value_rdata; + + CSR_DCSR: + csr_rdata_int = dcsr_q;// + CSR_DPC: + csr_rdata_int = depc_q; + CSR_DSCRATCH0: + csr_rdata_int = dscratch0_q;// + CSR_DSCRATCH1: + csr_rdata_int = dscratch1_q;// + + // Hardware Performance Monitor + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: + csr_rdata_int = mhpmcounter_q[csr_addr_i[4:0]][31:0]; + + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: + csr_rdata_int = mhpmcounter_q[csr_addr_i[4:0]][63:32]; + + CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit_q; + + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, + CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11, + CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, + CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, + CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, + CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, + CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: + csr_rdata_int = mhpmevent_q[csr_addr_i[4:0]]; + + // hardware loops (not official) + HWLoop0_START : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_start_i[0] ; + HWLoop0_END : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_end_i[0] ; + HWLoop0_COUNTER : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_cnt_i[0] ; + HWLoop1_START : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_start_i[1] ; + HWLoop1_END : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_end_i[1] ; + HWLoop1_COUNTER : csr_rdata_int = !PULP_HWLP ? 'b0 : hwlp_cnt_i[1] ; + + /* USER CSR */ + // dublicated mhartid: unique hardware thread id (not official) + UHARTID: csr_rdata_int = hart_id_i; + // current priv level (not official) + PRIVLV: csr_rdata_int = {30'h0, priv_lvl_q}; + default: + csr_rdata_int = '0; + endcase + end +end //PULP_SECURE + +if(PULP_SECURE==1) begin + // write logic + always_comb + begin + fflags_n = fflags_q; + frm_n = frm_q; + fprec_n = fprec_q; + mscratch_n = mscratch_q; + mepc_n = mepc_q; + uepc_n = uepc_q; + depc_n = depc_q; + dcsr_n = dcsr_q; + dscratch0_n = dscratch0_q; + dscratch1_n = dscratch1_q; + + mstatus_n = mstatus_q; + mcause_n = mcause_q; + ucause_n = ucause_q; + hwlp_we_o = '0; + hwlp_regid_o = '0; + exception_pc = pc_id_i; + priv_lvl_n = priv_lvl_q; + mtvec_n = mtvec_q; + utvec_n = utvec_q; + mtvec_mode_n = mtvec_mode_q; + utvec_mode_n = utvec_mode_q; + pmp_reg_n.pmpaddr = pmp_reg_q.pmpaddr; + pmpcfg_packed_n = pmpcfg_packed_q; + pmpaddr_we = '0; + pmpcfg_we = '0; + + mie_n = mie_q; + mie1_n = mie1_q; + + if (FPU == 1) if (fflags_we_i) fflags_n = fflags_i | fflags_q; + + casex (csr_addr_i) + // fcsr: Floating-Point Control and Status Register (frm, fflags, fprec). + CSR_FFLAGS : if (csr_we_int) fflags_n = (FPU == 1) ? csr_wdata_int[C_FFLAG-1:0] : '0; + CSR_FRM : if (csr_we_int) frm_n = (FPU == 1) ? csr_wdata_int[C_RM-1:0] : '0; + CSR_FCSR : if (csr_we_int) begin + fflags_n = (FPU == 1) ? csr_wdata_int[C_FFLAG-1:0] : '0; + frm_n = (FPU == 1) ? csr_wdata_int[C_RM+C_FFLAG-1:C_FFLAG] : '0; + end + FPREC : if (csr_we_int) fprec_n = (FPU == 1) ? csr_wdata_int[C_PC-1:0] : '0; + + // mstatus: IE bit + CSR_MSTATUS: if (csr_we_int) begin + mstatus_n = '{ + uie: csr_wdata_int[`MSTATUS_UIE_BITS], + mie: csr_wdata_int[`MSTATUS_MIE_BITS], + upie: csr_wdata_int[`MSTATUS_UPIE_BITS], + mpie: csr_wdata_int[`MSTATUS_MPIE_BITS], + mpp: PrivLvl_t'(csr_wdata_int[`MSTATUS_MPP_BITS]), + mprv: csr_wdata_int[`MSTATUS_MPRV_BITS] + }; + end + // mie: machine interrupt enable + CSR_MIE: if (csr_we_int) begin + mie_n.irq_software = csr_wdata_int[CSR_MSIX_BIT]; + mie_n.irq_timer = csr_wdata_int[CSR_MTIX_BIT]; + mie_n.irq_external = csr_wdata_int[CSR_MEIX_BIT]; + mie_n.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW]; + end + // mie1: machine interrupt enable for fast interrupt extension (irq_fast_i[47:16]) + CSR_MIE1: if (csr_we_int) begin + mie1_n = csr_wdata_int; + end + // mtvec: machine trap-handler base address + CSR_MTVEC: if (csr_we_int) begin + mtvec_n = csr_wdata_int[31:8]; + mtvec_mode_n = {1'b0, csr_wdata_int[0]}; // Only direct and vectored mode are supported + end + // mscratch: machine scratch + CSR_MSCRATCH: if (csr_we_int) begin + mscratch_n = csr_wdata_int; + end + // mepc: exception program counter + CSR_MEPC: if (csr_we_int) begin + mepc_n = csr_wdata_int & ~32'b1; // force 16-bit alignment + end + // mcause + CSR_MCAUSE: if (csr_we_int) mcause_n = {csr_wdata_int[31], csr_wdata_int[5:0]}; + + // Debug + CSR_DCSR: + if (csr_we_int) + begin + dcsr_n = csr_wdata_int; + //31:28 xdebuger = 4 -> debug is implemented + dcsr_n.xdebugver=4'h4; + //privilege level: 0-> U;1-> S; 3->M. + dcsr_n.prv=priv_lvl_q; + //currently not supported: + dcsr_n.nmip=1'b0; //nmip + dcsr_n.mprven=1'b0; //mprven + dcsr_n.stopcount=1'b0; //stopcount + dcsr_n.stoptime=1'b0; //stoptime + end + CSR_DPC: + if (csr_we_int) + begin + depc_n = csr_wdata_int & ~32'b1; // force 16-bit alignment + end + + CSR_DSCRATCH0: + if (csr_we_int) + begin + dscratch0_n = csr_wdata_int; + end + + CSR_DSCRATCH1: + if (csr_we_int) + begin + dscratch1_n = csr_wdata_int; + end + + // hardware loops + HWLoop0_START: if (csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b0; end + HWLoop0_END: if (csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b0; end + HWLoop0_COUNTER: if (csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b0; end + HWLoop1_START: if (csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end + HWLoop1_END: if (csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end + HWLoop1_COUNTER: if (csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end + + + // PMP config registers + CSR_PMPCFG0: if (csr_we_int) begin pmpcfg_packed_n[0] = csr_wdata_int; pmpcfg_we[3:0] = 4'b1111; end + CSR_PMPCFG1: if (csr_we_int) begin pmpcfg_packed_n[1] = csr_wdata_int; pmpcfg_we[7:4] = 4'b1111; end + CSR_PMPCFG2: if (csr_we_int) begin pmpcfg_packed_n[2] = csr_wdata_int; pmpcfg_we[11:8] = 4'b1111; end + CSR_PMPCFG3: if (csr_we_int) begin pmpcfg_packed_n[3] = csr_wdata_int; pmpcfg_we[15:12] = 4'b1111; end + + CSR_PMPADDR_RANGE_X : + if (csr_we_int) begin pmp_reg_n.pmpaddr[csr_addr_i[3:0]] = csr_wdata_int; pmpaddr_we[csr_addr_i[3:0]] = 1'b1; end + + + /* USER CSR */ + // ucause: exception cause + CSR_USTATUS: if (csr_we_int) begin + mstatus_n = '{ + uie: csr_wdata_int[`MSTATUS_UIE_BITS], + mie: mstatus_q.mie, + upie: csr_wdata_int[`MSTATUS_UPIE_BITS], + mpie: mstatus_q.mpie, + mpp: mstatus_q.mpp, + mprv: mstatus_q.mprv + }; + end + // utvec: user trap-handler base address + CSR_UTVEC: if (csr_we_int) begin + utvec_n = csr_wdata_int[31:8]; + utvec_mode_n = {1'b0, csr_wdata_int[0]}; // Only direct and vectored mode are supported + end + // uepc: exception program counter + CSR_UEPC: if (csr_we_int) begin + uepc_n = csr_wdata_int; + end + // ucause: exception cause + CSR_UCAUSE: if (csr_we_int) ucause_n = {csr_wdata_int[31], csr_wdata_int[5:0]}; + endcase + + // exception controller gets priority over other writes + unique case (1'b1) + + csr_save_cause_i: begin + + unique case (1'b1) + csr_save_if_i: + exception_pc = pc_if_i; + csr_save_id_i: + exception_pc = pc_id_i; + csr_save_ex_i: + exception_pc = pc_ex_i; + default:; + endcase + + unique case (priv_lvl_q) + + PRIV_LVL_U: begin + if(~is_irq) begin + //Exceptions, Ecall U --> M + priv_lvl_n = PRIV_LVL_M; + mstatus_n.mpie = mstatus_q.uie; + mstatus_n.mie = 1'b0; + mstatus_n.mpp = PRIV_LVL_U; + // TODO: correctly handled? + if (debug_csr_save_i) + depc_n = exception_pc; + else + mepc_n = exception_pc; + mcause_n = csr_cause_i; + + end + else begin + if(~csr_irq_sec_i) begin + //U --> U + priv_lvl_n = PRIV_LVL_U; + mstatus_n.upie = mstatus_q.uie; + mstatus_n.uie = 1'b0; + // TODO: correctly handled? + if (debug_csr_save_i) + depc_n = exception_pc; + else + uepc_n = exception_pc; + ucause_n = csr_cause_i; + + end else begin + //U --> M + priv_lvl_n = PRIV_LVL_M; + mstatus_n.mpie = mstatus_q.uie; + mstatus_n.mie = 1'b0; + mstatus_n.mpp = PRIV_LVL_U; + // TODO: correctly handled? + if (debug_csr_save_i) + depc_n = exception_pc; + else + mepc_n = exception_pc; + mcause_n = csr_cause_i; + end + end + end //PRIV_LVL_U + + PRIV_LVL_M: begin + if (debug_csr_save_i) begin + // all interrupts are masked, don't update cause, epc, tval dpc + // and mpstatus + dcsr_n.prv = PRIV_LVL_M; + dcsr_n.cause = debug_cause_i; + depc_n = exception_pc; + end else begin + //Exceptions or Interrupts from PRIV_LVL_M always do M --> M + priv_lvl_n = PRIV_LVL_M; + mstatus_n.mpie = mstatus_q.mie; + mstatus_n.mie = 1'b0; + mstatus_n.mpp = PRIV_LVL_M; + mepc_n = exception_pc; + mcause_n = csr_cause_i; + end + end //PRIV_LVL_M + default:; + + endcase + + end //csr_save_cause_i + + csr_restore_uret_i: begin //URET + //mstatus_q.upp is implicitly 0, i.e PRIV_LVL_U + mstatus_n.uie = mstatus_q.upie; + priv_lvl_n = PRIV_LVL_U; + mstatus_n.upie = 1'b1; + end //csr_restore_uret_i + + csr_restore_mret_i: begin //MRET + unique case (mstatus_q.mpp) + PRIV_LVL_U: begin + mstatus_n.uie = mstatus_q.mpie; + priv_lvl_n = PRIV_LVL_U; + mstatus_n.mpie = 1'b1; + mstatus_n.mpp = PRIV_LVL_U; + end + PRIV_LVL_M: begin + mstatus_n.mie = mstatus_q.mpie; + priv_lvl_n = PRIV_LVL_M; + mstatus_n.mpie = 1'b1; + mstatus_n.mpp = PRIV_LVL_U; + end + default:; + endcase + end //csr_restore_mret_i + + + csr_restore_dret_i: begin //DRET + // restore to the recorded privilege level + // TODO: prevent illegal values, see riscv-debug p.44 + priv_lvl_n = dcsr_q.prv; + + end //csr_restore_dret_i + + default:; + endcase + end +end else begin //PULP_SECURE == 0 + // write logic + always_comb + begin + fflags_n = fflags_q; + frm_n = frm_q; + fprec_n = fprec_q; + mscratch_n = mscratch_q; + mepc_n = mepc_q; + uepc_n = 'b0; // Not used if PULP_SECURE == 0 + depc_n = depc_q; + dcsr_n = dcsr_q; + dscratch0_n = dscratch0_q; + dscratch1_n = dscratch1_q; + + mstatus_n = mstatus_q; + mcause_n = mcause_q; + ucause_n = '0; // Not used if PULP_SECURE == 0 + hwlp_we_o = '0; + hwlp_regid_o = '0; + exception_pc = pc_id_i; + priv_lvl_n = priv_lvl_q; + mtvec_n = mtvec_q; + utvec_n = '0; // Not used if PULP_SECURE == 0 + pmp_reg_n.pmpaddr = '0; // Not used if PULP_SECURE == 0 + pmpcfg_packed_n = '0; // Not used if PULP_SECURE == 0 + pmp_reg_n.pmpcfg = '0; // Not used if PULP_SECURE == 0 + pmpaddr_we = '0; + pmpcfg_we = '0; + + mie_n = mie_q; + mie1_n = mie1_q; + mtvec_mode_n = mtvec_mode_q; + utvec_mode_n = '0; // Not used if PULP_SECURE == 0 + + if (FPU == 1) if (fflags_we_i) fflags_n = fflags_i | fflags_q; + + case (csr_addr_i) + // fcsr: Floating-Point Control and Status Register (frm, fflags, fprec). + CSR_FFLAGS : if (csr_we_int) fflags_n = (FPU == 1) ? csr_wdata_int[C_FFLAG-1:0] : '0; + CSR_FRM : if (csr_we_int) frm_n = (FPU == 1) ? csr_wdata_int[C_RM-1:0] : '0; + CSR_FCSR : if (csr_we_int) begin + fflags_n = (FPU == 1) ? csr_wdata_int[C_FFLAG-1:0] : '0; + frm_n = (FPU == 1) ? csr_wdata_int[C_RM+C_FFLAG-1:C_FFLAG] : '0; + end + FPREC : if (csr_we_int) fprec_n = (FPU == 1) ? csr_wdata_int[C_PC-1:0] : '0; + + // mstatus: IE bit + CSR_MSTATUS: if (csr_we_int) begin + mstatus_n = '{ + uie: csr_wdata_int[`MSTATUS_UIE_BITS], + mie: csr_wdata_int[`MSTATUS_MIE_BITS], + upie: csr_wdata_int[`MSTATUS_UPIE_BITS], + mpie: csr_wdata_int[`MSTATUS_MPIE_BITS], + mpp: PrivLvl_t'(csr_wdata_int[`MSTATUS_MPP_BITS]), + mprv: csr_wdata_int[`MSTATUS_MPRV_BITS] + }; + end + // mie: machine interrupt enable + CSR_MIE: if(csr_we_int) begin + mie_n.irq_software = csr_wdata_int[CSR_MSIX_BIT]; + mie_n.irq_timer = csr_wdata_int[CSR_MTIX_BIT]; + mie_n.irq_external = csr_wdata_int[CSR_MEIX_BIT]; + mie_n.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW]; + end + // mie1: machine interrupt enable for fast interrupt extension (irq_fast_i[47:16]) + CSR_MIE1: if (csr_we_int) begin + mie1_n = csr_wdata_int; + end + // mtvec: machine trap-handler base address + CSR_MTVEC: if (csr_we_int) begin + mtvec_n = csr_wdata_int[31:8]; + end + // mscratch: machine scratch + CSR_MSCRATCH: if (csr_we_int) begin + mscratch_n = csr_wdata_int; + end + // mepc: exception program counter + CSR_MEPC: if (csr_we_int) begin + mepc_n = csr_wdata_int & ~32'b1; // force 16-bit alignment + end + // mcause + CSR_MCAUSE: if (csr_we_int) mcause_n = {csr_wdata_int[31], csr_wdata_int[5:0]}; + + CSR_DCSR: + if (csr_we_int) + begin + dcsr_n = csr_wdata_int; + //31:28 xdebuger = 4 -> debug is implemented + dcsr_n.xdebugver=4'h4; + //privilege level: 0-> U;1-> S; 3->M. + dcsr_n.prv=priv_lvl_q; + //currently not supported: + dcsr_n.nmip=1'b0; //nmip + dcsr_n.mprven=1'b0; //mprven + dcsr_n.stopcount=1'b0; //stopcount + dcsr_n.stoptime=1'b0; //stoptime + end + CSR_DPC: + if (csr_we_int) + begin + depc_n = csr_wdata_int & ~32'b1; // force 16-bit alignment + end + + CSR_DSCRATCH0: + if (csr_we_int) + begin + dscratch0_n = csr_wdata_int; + end + + CSR_DSCRATCH1: + if (csr_we_int) + begin + dscratch1_n = csr_wdata_int; + end + + // hardware loops + HWLoop0_START: if (csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b0; end + HWLoop0_END: if (csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b0; end + HWLoop0_COUNTER: if (csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b0; end + HWLoop1_START: if (csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end + HWLoop1_END: if (csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end + HWLoop1_COUNTER: if (csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end + endcase + + // exception controller gets priority over other writes + unique case (1'b1) + + csr_save_cause_i: begin + unique case (1'b1) + csr_save_if_i: + exception_pc = pc_if_i; + csr_save_id_i: + exception_pc = pc_id_i; + default:; + endcase + + if (debug_csr_save_i) begin + // all interrupts are masked, don't update cause, epc, tval dpc and + // mpstatus + dcsr_n.prv = PRIV_LVL_M; + dcsr_n.cause = debug_cause_i; + depc_n = exception_pc; + end else begin + priv_lvl_n = PRIV_LVL_M; + mstatus_n.mpie = mstatus_q.mie; + mstatus_n.mie = 1'b0; + mstatus_n.mpp = PRIV_LVL_M; + mepc_n = exception_pc; + mcause_n = csr_cause_i; + end + end //csr_save_cause_i + + csr_restore_mret_i: begin //MRET + mstatus_n.mie = mstatus_q.mpie; + priv_lvl_n = PRIV_LVL_M; + mstatus_n.mpie = 1'b1; + mstatus_n.mpp = PRIV_LVL_M; + end //csr_restore_mret_i + + csr_restore_dret_i: begin //DRET + // restore to the recorded privilege level + // TODO: prevent illegal values, see riscv-debug p.44 + priv_lvl_n = dcsr_q.prv; + end //csr_restore_dret_i + + default:; + endcase + end +end //PULP_SECURE + + assign hwlp_data_o = csr_wdata_int; + + // CSR operation logic + always_comb + begin + csr_wdata_int = csr_wdata_i; + csr_we_int = 1'b1; + + unique case (csr_op_i) + CSR_OP_WRITE: csr_wdata_int = csr_wdata_i; + CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o; + CSR_OP_CLEAR: csr_wdata_int = (~csr_wdata_i) & csr_rdata_o; + + CSR_OP_READ: begin + csr_wdata_int = csr_wdata_i; + csr_we_int = 1'b0; + end + + default:; + endcase + end + + assign csr_rdata_o = csr_rdata_int; + + // Interrupt Encoder: + // - sets correct id to request to ID + // - encodes priority order + always_comb + begin + + if (menip1[31]) irq_id_o = 6'd63; + else if (menip1[30]) irq_id_o = 6'd62; + else if (menip1[29]) irq_id_o = 6'd61; + else if (menip1[28]) irq_id_o = 6'd60; + else if (menip1[27]) irq_id_o = 6'd59; + else if (menip1[26]) irq_id_o = 6'd58; + else if (menip1[25]) irq_id_o = 6'd57; + else if (menip1[24]) irq_id_o = 6'd56; + else if (menip1[23]) irq_id_o = 6'd55; + else if (menip1[22]) irq_id_o = 6'd54; + else if (menip1[21]) irq_id_o = 6'd53; + else if (menip1[20]) irq_id_o = 6'd52; + else if (menip1[19]) irq_id_o = 6'd51; + else if (menip1[18]) irq_id_o = 6'd50; + else if (menip1[17]) irq_id_o = 6'd49; + else if (menip1[16]) irq_id_o = 6'd48; + else if (menip1[15]) irq_id_o = 6'd47; + else if (menip1[14]) irq_id_o = 6'd46; + else if (menip1[13]) irq_id_o = 6'd45; + else if (menip1[12]) irq_id_o = 6'd44; + else if (menip1[11]) irq_id_o = 6'd43; + else if (menip1[10]) irq_id_o = 6'd42; + else if (menip1[ 9]) irq_id_o = 6'd41; + else if (menip1[ 8]) irq_id_o = 6'd40; + else if (menip1[ 7]) irq_id_o = 6'd39; + else if (menip1[ 6]) irq_id_o = 6'd38; + else if (menip1[ 5]) irq_id_o = 6'd37; + else if (menip1[ 4]) irq_id_o = 6'd36; + else if (menip1[ 3]) irq_id_o = 6'd35; + else if (menip1[ 2]) irq_id_o = 6'd34; + else if (menip1[ 1]) irq_id_o = 6'd33; + else if (menip1[ 0]) irq_id_o = 6'd32; + else if (menip.irq_fast[15]) irq_id_o = 6'd31; + else if (menip.irq_fast[14]) irq_id_o = 6'd30; + else if (menip.irq_fast[13]) irq_id_o = 6'd29; + else if (menip.irq_fast[12]) irq_id_o = 6'd28; + else if (menip.irq_fast[11]) irq_id_o = 6'd27; + else if (menip.irq_fast[10]) irq_id_o = 6'd26; + else if (menip.irq_fast[ 9]) irq_id_o = 6'd25; + else if (menip.irq_fast[ 8]) irq_id_o = 6'd24; + else if (menip.irq_fast[ 7]) irq_id_o = 6'd23; + else if (menip.irq_fast[ 6]) irq_id_o = 6'd22; + else if (menip.irq_fast[ 5]) irq_id_o = 6'd21; + else if (menip.irq_fast[ 4]) irq_id_o = 6'd20; + else if (menip.irq_fast[ 3]) irq_id_o = 6'd19; + else if (menip.irq_fast[ 2]) irq_id_o = 6'd18; + else if (menip.irq_fast[ 1]) irq_id_o = 6'd17; + else if (menip.irq_fast[ 0]) irq_id_o = 6'd16; + else if (menip.irq_external) irq_id_o = CSR_MEIX_BIT; + else if (menip.irq_software) irq_id_o = CSR_MSIX_BIT; + else if (menip.irq_timer) irq_id_o = CSR_MTIX_BIT; + else irq_id_o = CSR_MTIX_BIT; + end + + + // directly output some registers + assign m_irq_enable_o = mstatus_q.mie & priv_lvl_q == PRIV_LVL_M; + assign u_irq_enable_o = mstatus_q.uie & priv_lvl_q == PRIV_LVL_U; + assign priv_lvl_o = priv_lvl_q; + assign sec_lvl_o = priv_lvl_q[0]; + assign frm_o = (FPU == 1) ? frm_q : '0; + assign fprec_o = (FPU == 1) ? fprec_q : '0; + + assign mtvec_o = mtvec_q; + assign utvec_o = utvec_q; + assign mtvec_mode_o = mtvec_mode_q; + assign utvec_mode_o = utvec_mode_q; + + assign mepc_o = mepc_q; + assign uepc_o = uepc_q; + + assign depc_o = depc_q; + + assign pmp_addr_o = pmp_reg_q.pmpaddr; + assign pmp_cfg_o = pmp_reg_q.pmpcfg; + + assign debug_single_step_o = dcsr_q.step; + assign debug_ebreakm_o = dcsr_q.ebreakm; + assign debug_ebreaku_o = dcsr_q.ebreaku; + + // Output interrupt pending to ID/Controller and to clock gating (WFI) + assign irq_pending_o = menip.irq_software | menip.irq_timer | menip.irq_external | (|menip.irq_fast) | (|menip1); + + generate + if (PULP_SECURE == 1) + begin + + for(j=0;j2) && (cnt_idx<(NUM_MHPMCOUNTERS+3))) + // add +1 if any event is enabled and active + mhpmcounter_n[cnt_idx] = mhpmcounter_q[cnt_idx] + + |(hpm_events & mhpmevent_q[cnt_idx][NUM_HPM_EVENTS-1:0]) ; + end + + // ------------------------ + // HPM Registers + // Counter Registers: mhpcounter_q[] + genvar cnt_gidx; + generate + for(cnt_gidx = 0; cnt_gidx < 32; cnt_gidx++) begin : g_mhpmcounter + // mcyclce is located at index 0 + // there is no counter at index 1 + // minstret is located at index 2 + // Programable HPM counters start at index 3 + + if( (cnt_gidx == 1) || (cnt_gidx >= (NUM_MHPMCOUNTERS+3) ) ) begin : g_non_implemented + always_ff @(posedge clk, negedge rst_n) begin + mhpmcounter_q[cnt_gidx] <= 'b0; + end + end else begin : g_implemented + always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + mhpmcounter_q[cnt_gidx] <= 'b0; + end else begin + mhpmcounter_q[cnt_gidx] <= mhpmcounter_n[cnt_gidx]; + end + end + end + end + endgenerate + + // Event Register: mhpevent_q[] + genvar evt_gidx; + generate + for(evt_gidx = 0; evt_gidx < 32; evt_gidx++) begin : g_mhpmevent + // programable HPM events start at index3 + if( (evt_gidx < 3) || (evt_gidx >= (NUM_MHPMCOUNTERS+3) ) ) begin : g_non_implemented + always_ff @(posedge clk, negedge rst_n) begin + mhpmevent_q[evt_gidx] <= 'b0; + end + end else begin : g_implemented + if(NUM_HPM_EVENTS < 32) begin + always_ff @(posedge clk, negedge rst_n) begin + mhpmevent_q[evt_gidx][31:NUM_HPM_EVENTS] <= 'b0; + end + end else begin + always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + mhpmevent_q[evt_gidx][NUM_HPM_EVENTS-1:0] <= 'b0; + end else begin + mhpmevent_q[evt_gidx][NUM_HPM_EVENTS-1:0] <= mhpmevent_n[evt_gidx][NUM_HPM_EVENTS-1:0]; + end + end + end + end + end + endgenerate + + // Inhibit Regsiter: mcountinhibit_q + // Note: implemented counters are disabled out of reset to save power + genvar inh_gidx; + generate + for(inh_gidx = 0; inh_gidx < 32; inh_gidx++) begin : g_mcountinhibit + if( (inh_gidx == 1) || (inh_gidx >= (NUM_MHPMCOUNTERS+3) ) ) begin : g_non_implemented + always_ff @(posedge clk, negedge rst_n) begin + mcountinhibit_q[inh_gidx] <= 'b1; // default disable + end + end else begin : g_implemented + always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + mcountinhibit_q[inh_gidx] <= 'b1; // default disable + end else begin + mcountinhibit_q[inh_gidx] <= mcountinhibit_n[inh_gidx]; + end + end + end + end + endgenerate + + // capture valid for event match + always_ff @(posedge clk, negedge rst_n) + if (!rst_n) + id_valid_q <= 'b0; + else + id_valid_q <= id_valid_i; + + +endmodule + diff --git a/hw/deps/riscv/riscv_decoder.sv b/hw/deps/riscv/riscv_decoder.sv new file mode 100644 index 0000000..3a2bfff --- /dev/null +++ b/hw/deps/riscv/riscv_decoder.sv @@ -0,0 +1,2675 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer Andreas Traber - atraber@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// Matthias Baer - baermatt@student.ethz.ch // +// Igor Loi - igor.loi@unibo.it // +// Sven Stucki - svstucki@student.ethz.ch // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: Decoder // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Decoder // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "apu_macros.sv" + +import riscv_defines::*; + +module riscv_decoder +#( + parameter PULP_HWLP = 0, + parameter A_EXTENSION = 0, + parameter FPU = 0, + parameter FP_DIVSQRT = 0, + parameter PULP_SECURE = 0, + parameter USE_PMP = 0, + parameter SHARED_FP = 0, + parameter SHARED_DSP_MULT = 0, + parameter SHARED_INT_MULT = 0, + parameter SHARED_INT_DIV = 0, + parameter SHARED_FP_DIVSQRT = 0, + parameter WAPUTYPE = 0, + parameter APU_WOP_CPU = 6, + parameter DEBUG_TRIGGER_EN = 1 +) +( + // singals running to/from controller + input logic deassert_we_i, // deassert we, we are stalled or not active + input logic data_misaligned_i, // misaligned data load/store in progress + input logic mult_multicycle_i, // multiplier taking multiple cycles, using op c as storage + output logic instr_multicycle_o, // true when multiple cycles are decoded + + output logic illegal_insn_o, // illegal instruction encountered + output logic ebrk_insn_o, // trap instruction encountered + + output logic mret_insn_o, // return from exception instruction encountered (M) + output logic uret_insn_o, // return from exception instruction encountered (S) + output logic dret_insn_o, // return from debug (M) + + output logic mret_dec_o, // return from exception instruction encountered (M) without deassert + output logic uret_dec_o, // return from exception instruction encountered (S) without deassert + output logic dret_dec_o, // return from debug (M) without deassert + + output logic ecall_insn_o, // environment call (syscall) instruction encountered + output logic pipe_flush_o, // pipeline flush is requested + + output logic fencei_insn_o, // fence.i instruction + + output logic rega_used_o, // rs1 is used by current instruction + output logic regb_used_o, // rs2 is used by current instruction + output logic regc_used_o, // rs3 is used by current instruction + + output logic reg_fp_a_o, // fp reg a is used + output logic reg_fp_b_o, // fp reg b is used + output logic reg_fp_c_o, // fp reg c is used + output logic reg_fp_d_o, // fp reg d is used + + output logic [ 0:0] bmask_a_mux_o, // bit manipulation mask a mux + output logic [ 1:0] bmask_b_mux_o, // bit manipulation mask b mux + output logic alu_bmask_a_mux_sel_o, // bit manipulation mask a mux (reg or imm) + output logic alu_bmask_b_mux_sel_o, // bit manipulation mask b mux (reg or imm) + + // from IF/ID pipeline + input logic [31:0] instr_rdata_i, // instruction read from instr memory/cache + input logic illegal_c_insn_i, // compressed instruction decode failed + + // ALU signals + output logic alu_en_o, // ALU enable + output logic [ALU_OP_WIDTH-1:0] alu_operator_o, // ALU operation selection + output logic [2:0] alu_op_a_mux_sel_o, // operand a selection: reg value, PC, immediate or zero + output logic [2:0] alu_op_b_mux_sel_o, // operand b selection: reg value or immediate + output logic [1:0] alu_op_c_mux_sel_o, // operand c selection: reg value or jump target + output logic [1:0] alu_vec_mode_o, // selects between 32 bit, 16 bit and 8 bit vectorial modes + output logic scalar_replication_o, // scalar replication enable + output logic scalar_replication_c_o, // scalar replication enable for operand C + output logic [0:0] imm_a_mux_sel_o, // immediate selection for operand a + output logic [3:0] imm_b_mux_sel_o, // immediate selection for operand b + output logic [1:0] regc_mux_o, // register c selection: S3, RD or 0 + output logic is_clpx_o, // whether the instruction is complex (pulpv3) or not + output logic is_subrot_o, + + // MUL related control signals + output logic [2:0] mult_operator_o, // Multiplication operation selection + output logic mult_int_en_o, // perform integer multiplication + output logic mult_dot_en_o, // perform dot multiplication + output logic [0:0] mult_imm_mux_o, // Multiplication immediate mux selector + output logic mult_sel_subword_o, // Select subwords for 16x16 bit of multiplier + output logic [1:0] mult_signed_mode_o, // Multiplication in signed mode + output logic [1:0] mult_dot_signed_o, // Dot product in signed mode + + // FPU + input logic [C_RM-1:0] frm_i, // Rounding mode from float CSR + + output logic [C_FPNEW_FMTBITS-1:0] fpu_dst_fmt_o, // fpu destination format + output logic [C_FPNEW_FMTBITS-1:0] fpu_src_fmt_o, // fpu source format + output logic [C_FPNEW_IFMTBITS-1:0] fpu_int_fmt_o, // fpu integer format (for casts) + + // APU + output logic apu_en_o, + output logic [WAPUTYPE-1:0] apu_type_o, + output logic [APU_WOP_CPU-1:0] apu_op_o, + output logic [1:0] apu_lat_o, + output logic [WAPUTYPE-1:0] apu_flags_src_o, + output logic [2:0] fp_rnd_mode_o, + + // register file related signals + output logic regfile_mem_we_o, // write enable for regfile + output logic regfile_alu_we_o, // write enable for 2nd regfile port + output logic regfile_alu_we_dec_o, // write enable for 2nd regfile port without deassert + output logic regfile_alu_waddr_sel_o, // Select register write address for ALU/MUL operations + + // CSR manipulation + output logic csr_access_o, // access to CSR + output logic csr_status_o, // access to xstatus CSR + output logic [1:0] csr_op_o, // operation to perform on CSR + input PrivLvl_t current_priv_lvl_i, // The current privilege level + + // Stack protection + output logic stack_access_o, // memory access through the stack pointer + + // LD/ST unit signals + output logic data_req_o, // start transaction to data memory + output logic data_we_o, // data memory write enable + output logic prepost_useincr_o, // when not active bypass the alu result for address calculation + output logic [1:0] data_type_o, // data type on data memory: byte, half word or word + output logic [1:0] data_sign_extension_o, // sign extension on read data from data memory / NaN boxing + output logic [1:0] data_reg_offset_o, // offset in byte inside register for stores + output logic data_load_event_o, // data request is in the special event range + + // Atomic memory access + output logic [5:0] atop_o, // define atomic memory operation + output logic buffer_o, // define bufferable store + + // hwloop signals + output logic [2:0] hwloop_we_o, // write enable for hwloop regs + output logic hwloop_target_mux_sel_o, // selects immediate for hwloop target + output logic hwloop_start_mux_sel_o, // selects hwloop start address input + output logic hwloop_cnt_mux_sel_o, // selects hwloop counter input + + input logic debug_mode_i, // processor is in debug mode + + // jump/branches + output logic [1:0] jump_in_dec_o, // jump_in_id without deassert + output logic [1:0] jump_in_id_o, // jump is being calculated in ALU + output logic [1:0] jump_target_mux_sel_o // jump target selection +); + + // careful when modifying the following parameters! these types have to match the ones in the APU! + localparam APUTYPE_DSP_MULT = (SHARED_DSP_MULT) ? 0 : 0; + localparam APUTYPE_INT_MULT = (SHARED_INT_MULT) ? SHARED_DSP_MULT : 0; + localparam APUTYPE_INT_DIV = (SHARED_INT_DIV) ? SHARED_DSP_MULT + SHARED_INT_MULT : 0; + localparam APUTYPE_FP = (SHARED_FP) ? SHARED_DSP_MULT + SHARED_INT_MULT + SHARED_INT_DIV : 0; + localparam APUTYPE_ADDSUB = (SHARED_FP) ? ((SHARED_FP==1) ? APUTYPE_FP : APUTYPE_FP) : 0; + localparam APUTYPE_MULT = (SHARED_FP) ? ((SHARED_FP==1) ? APUTYPE_FP+1 : APUTYPE_FP) : 0; + localparam APUTYPE_CAST = (SHARED_FP) ? ((SHARED_FP==1) ? APUTYPE_FP+2 : APUTYPE_FP) : 0; + localparam APUTYPE_MAC = (SHARED_FP) ? ((SHARED_FP==1) ? APUTYPE_FP+3 : APUTYPE_FP) : 0; + // SHARED_FP_DIVSQRT is without effect unless FP_DIVSQRT is set. + // SHARED_FP_DIVSQRT==1, SHARED_FP==1 (old config): separate div and sqrt units + // SHARED_FP_DIVSQRT==1, SHARED_FP==2 (new config): divsqrt enabled within shared FPnew blocks + // SHARED_FP_DIVSQRT==2, SHARED_FP==1 (old config): merged div/sqrt unit + // SHARED_FP_DIVSQRT==2, SHARED_FP==2 (new config): separate shared divsqrt blocks (allows different share ratio) + localparam APUTYPE_DIV = (SHARED_FP_DIVSQRT==1) ? ((SHARED_FP==1) ? APUTYPE_FP+4 : APUTYPE_FP) : + ((SHARED_FP_DIVSQRT==2) ? ((SHARED_FP==1) ? APUTYPE_FP+4 : APUTYPE_FP+1) : 0); + localparam APUTYPE_SQRT = (SHARED_FP_DIVSQRT==1) ? ((SHARED_FP==1) ? APUTYPE_FP+5 : APUTYPE_FP) : + ((SHARED_FP_DIVSQRT==2) ? ((SHARED_FP==1) ? APUTYPE_FP+4 : APUTYPE_FP+1) : 0); + + // write enable/request control + logic regfile_mem_we; + logic regfile_alu_we; + logic data_req; + logic [2:0] hwloop_we; + logic csr_illegal; + logic [1:0] jump_in_id; + + logic [1:0] csr_op; + + logic mult_int_en; + logic mult_dot_en; + logic apu_en; + + // this instruction needs floating-point rounding-mode verification + logic check_fprm; + + logic [C_FPNEW_OPBITS-1:0] fpu_op; // fpu operation + logic fpu_op_mod; // fpu operation modifier + logic fpu_vec_op; // fpu vectorial operation + // unittypes for latencies to help us decode for APU + enum logic[1:0] {ADDMUL, DIVSQRT, NONCOMP, CONV} fp_op_group; + + + ///////////////////////////////////////////// + // ____ _ // + // | _ \ ___ ___ ___ __| | ___ _ __ // + // | | | |/ _ \/ __/ _ \ / _` |/ _ \ '__| // + // | |_| | __/ (_| (_) | (_| | __/ | // + // |____/ \___|\___\___/ \__,_|\___|_| // + // // + ///////////////////////////////////////////// + + always_comb + begin + jump_in_id = BRANCH_NONE; + jump_target_mux_sel_o = JT_JAL; + + alu_en_o = 1'b1; + alu_operator_o = ALU_SLTU; + alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD; + alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD; + alu_op_c_mux_sel_o = OP_C_REGC_OR_FWD; + alu_vec_mode_o = VEC_MODE32; + scalar_replication_o = 1'b0; + scalar_replication_c_o = 1'b0; + regc_mux_o = REGC_ZERO; + imm_a_mux_sel_o = IMMA_ZERO; + imm_b_mux_sel_o = IMMB_I; + + mult_operator_o = MUL_I; + mult_int_en = 1'b0; + mult_dot_en = 1'b0; + mult_imm_mux_o = MIMM_ZERO; + mult_signed_mode_o = 2'b00; + mult_sel_subword_o = 1'b0; + mult_dot_signed_o = 2'b00; + + apu_en = 1'b0; + apu_type_o = '0; + apu_op_o = '0; + apu_lat_o = '0; + apu_flags_src_o = '0; + fp_rnd_mode_o = '0; + fpu_op = fpnew_pkg::SGNJ; + fpu_op_mod = 1'b0; + fpu_vec_op = 1'b0; + fpu_dst_fmt_o = fpnew_pkg::FP32; + fpu_src_fmt_o = fpnew_pkg::FP32; + fpu_int_fmt_o = fpnew_pkg::INT32; + check_fprm = 1'b0; + fp_op_group = ADDMUL; + + regfile_mem_we = 1'b0; + regfile_alu_we = 1'b0; + regfile_alu_waddr_sel_o = 1'b1; + + prepost_useincr_o = 1'b1; + + hwloop_we = 3'b0; + hwloop_target_mux_sel_o = 1'b0; + hwloop_start_mux_sel_o = 1'b0; + hwloop_cnt_mux_sel_o = 1'b0; + + csr_access_o = 1'b0; + csr_status_o = 1'b0; + csr_illegal = 1'b0; + csr_op = CSR_OP_READ; + mret_insn_o = 1'b0; + uret_insn_o = 1'b0; + + dret_insn_o = 1'b0; + + data_we_o = 1'b0; + data_type_o = 2'b00; + data_sign_extension_o = 2'b00; + data_reg_offset_o = 2'b00; + data_req = 1'b0; + data_load_event_o = 1'b0; + + atop_o = 6'b000000; + buffer_o = 1'b0; + + illegal_insn_o = 1'b0; + ebrk_insn_o = 1'b0; + ecall_insn_o = 1'b0; + pipe_flush_o = 1'b0; + + fencei_insn_o = 1'b0; + + rega_used_o = 1'b0; + regb_used_o = 1'b0; + regc_used_o = 1'b0; + reg_fp_a_o = 1'b0; + reg_fp_b_o = 1'b0; + reg_fp_c_o = 1'b0; + reg_fp_d_o = 1'b0; + + bmask_a_mux_o = BMASK_A_ZERO; + bmask_b_mux_o = BMASK_B_ZERO; + alu_bmask_a_mux_sel_o = BMASK_A_IMM; + alu_bmask_b_mux_sel_o = BMASK_B_IMM; + + instr_multicycle_o = 1'b0; + is_clpx_o = 1'b0; + is_subrot_o = 1'b0; + + mret_dec_o = 1'b0; + uret_dec_o = 1'b0; + dret_dec_o = 1'b0; + + unique case (instr_rdata_i[6:0]) + + ////////////////////////////////////// + // _ _ _ __ __ ____ ____ // + // | | | | | \/ | _ \/ ___| // + // _ | | | | | |\/| | |_) \___ \ // + // | |_| | |_| | | | | __/ ___) | // + // \___/ \___/|_| |_|_| |____/ // + // // + ////////////////////////////////////// + + OPCODE_JAL: begin // Jump and Link + jump_target_mux_sel_o = JT_JAL; + jump_in_id = BRANCH_JAL; + // Calculate and store PC+4 + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_PCINCR; + alu_operator_o = ALU_ADD; + regfile_alu_we = 1'b1; + // Calculate jump target (= PC + UJ imm) + end + + OPCODE_JALR: begin // Jump and Link Register + jump_target_mux_sel_o = JT_JALR; + jump_in_id = BRANCH_JALR; + // Calculate and store PC+4 + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_PCINCR; + alu_operator_o = ALU_ADD; + regfile_alu_we = 1'b1; + // Calculate jump target (= RS1 + I imm) + rega_used_o = 1'b1; + + if (instr_rdata_i[14:12] != 3'b0) begin + jump_in_id = BRANCH_NONE; + regfile_alu_we = 1'b0; + illegal_insn_o = 1'b1; + end + end + + OPCODE_BRANCH: begin // Branch + jump_target_mux_sel_o = JT_COND; + jump_in_id = BRANCH_COND; + alu_op_c_mux_sel_o = OP_C_JT; + rega_used_o = 1'b1; + regb_used_o = 1'b1; + + unique case (instr_rdata_i[14:12]) + 3'b000: alu_operator_o = ALU_EQ; + 3'b001: alu_operator_o = ALU_NE; + 3'b100: alu_operator_o = ALU_LTS; + 3'b101: alu_operator_o = ALU_GES; + 3'b110: alu_operator_o = ALU_LTU; + 3'b111: alu_operator_o = ALU_GEU; + 3'b010: begin + alu_operator_o = ALU_EQ; + regb_used_o = 1'b0; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_BI; + end + 3'b011: begin + alu_operator_o = ALU_NE; + regb_used_o = 1'b0; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_BI; + end + endcase + end + + + ////////////////////////////////// + // _ ____ ______ _____ // + // | | | _ \ / / ___|_ _| // + // | | | | | |/ /\___ \ | | // + // | |___| |_| / / ___) || | // + // |_____|____/_/ |____/ |_| // + // // + ////////////////////////////////// + + OPCODE_STORE, + OPCODE_STORE_BUF, + OPCODE_STORE_POST, + OPCODE_STORE_POST_BUF: begin + data_req = 1'b1; + data_we_o = 1'b1; + rega_used_o = 1'b1; + regb_used_o = 1'b1; + alu_operator_o = ALU_ADD; + instr_multicycle_o = 1'b1; + // pass write data through ALU operand c + alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; + + // post-increment setup + if (instr_rdata_i[6:0] == OPCODE_STORE_POST) begin + prepost_useincr_o = 1'b0; + regfile_alu_waddr_sel_o = 1'b0; + regfile_alu_we = 1'b1; + end + + if (instr_rdata_i[14] == 1'b0) begin + // offset from immediate + imm_b_mux_sel_o = IMMB_S; + alu_op_b_mux_sel_o = OP_B_IMM; + end else begin + // offset from register + regc_used_o = 1'b1; + alu_op_b_mux_sel_o = OP_B_REGC_OR_FWD; + regc_mux_o = REGC_RD; + end + + // store size + unique case (instr_rdata_i[13:12]) + 2'b00: data_type_o = 2'b10; // SB + 2'b01: data_type_o = 2'b01; // SH + 2'b10: data_type_o = 2'b00; // SW + default: begin + data_req = 1'b0; + data_we_o = 1'b0; + illegal_insn_o = 1'b1; + end + endcase + + if (instr_rdata_i[6:0] == OPCODE_STORE_BUF + || instr_rdata_i[6:0] == OPCODE_STORE_POST_BUF) begin + buffer_o = 1'b1; + end + + stack_access_o = (instr_rdata_i[19:15] == 5'd2); + end + + OPCODE_LOAD, + OPCODE_LOAD_POST: begin + data_req = 1'b1; + regfile_mem_we = 1'b1; + rega_used_o = 1'b1; + data_type_o = 2'b00; + instr_multicycle_o = 1'b1; + // offset from immediate + alu_operator_o = ALU_ADD; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_I; + + // post-increment setup + if (instr_rdata_i[6:0] == OPCODE_LOAD_POST) begin + prepost_useincr_o = 1'b0; + regfile_alu_waddr_sel_o = 1'b0; + regfile_alu_we = 1'b1; + end + + // sign/zero extension + data_sign_extension_o = {1'b0,~instr_rdata_i[14]}; + + // load size + unique case (instr_rdata_i[13:12]) + 2'b00: data_type_o = 2'b10; // LB + 2'b01: data_type_o = 2'b01; // LH + 2'b10: data_type_o = 2'b00; // LW + default: data_type_o = 2'b00; // illegal or reg-reg + endcase + + // reg-reg load (different encoding) + if (instr_rdata_i[14:12] == 3'b111) begin + // offset from RS2 + regb_used_o = 1'b1; + alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD; + + // sign/zero extension + data_sign_extension_o = {1'b0, ~instr_rdata_i[30]}; + + // load size + unique case (instr_rdata_i[31:25]) + 7'b0000_000, + 7'b0100_000: data_type_o = 2'b10; // LB, LBU + 7'b0001_000, + 7'b0101_000: data_type_o = 2'b01; // LH, LHU + 7'b0010_000: data_type_o = 2'b00; // LW + default: begin + illegal_insn_o = 1'b1; + end + endcase + end + + // special p.elw (event load) + if (instr_rdata_i[14:12] == 3'b110) + data_load_event_o = 1'b1; + + if (instr_rdata_i[14:12] == 3'b011) begin + // LD -> RV64 only + illegal_insn_o = 1'b1; + end + + stack_access_o = (instr_rdata_i[19:15] == 5'd2); + end + + OPCODE_AMO: begin + if (A_EXTENSION) begin : decode_amo + if (instr_rdata_i[14:12] == 3'b010) begin // RV32A Extension (word) + data_req = 1'b1; + data_type_o = 2'b00; + rega_used_o = 1'b1; + regb_used_o = 1'b1; + regfile_mem_we = 1'b1; + prepost_useincr_o = 1'b0; // only use alu_operand_a as address (not a+b) + alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD; + + data_sign_extension_o = 1'b1; + + // Apply AMO instruction at `atop_o`. + atop_o = {1'b1, instr_rdata_i[31:27]}; + + unique case (instr_rdata_i[31:27]) + AMO_LR: begin + data_we_o = 1'b0; + end + AMO_SC, + AMO_SWAP, + AMO_ADD, + AMO_XOR, + AMO_AND, + AMO_OR, + AMO_MIN, + AMO_MAX, + AMO_MINU, + AMO_MAXU: begin + data_we_o = 1'b1; + alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; // pass write data through ALU operand c + end + default : illegal_insn_o = 1'b1; + endcase + end + else begin + illegal_insn_o = 1'b1; + end + end else begin : no_decode_amo + illegal_insn_o = 1'b1; + end + end + + + ////////////////////////// + // _ _ _ _ // + // / \ | | | | | | // + // / _ \ | | | | | | // + // / ___ \| |__| |_| | // + // /_/ \_\_____\___/ // + // // + ////////////////////////// + + OPCODE_LUI: begin // Load Upper Immediate + alu_op_a_mux_sel_o = OP_A_IMM; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMMA_ZERO; + imm_b_mux_sel_o = IMMB_U; + alu_operator_o = ALU_ADD; + regfile_alu_we = 1'b1; + end + + OPCODE_AUIPC: begin // Add Upper Immediate to PC + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_U; + alu_operator_o = ALU_ADD; + regfile_alu_we = 1'b1; + end + + OPCODE_OPIMM: begin // Register-Immediate ALU Operations + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_I; + regfile_alu_we = 1'b1; + rega_used_o = 1'b1; + + unique case (instr_rdata_i[14:12]) + 3'b000: alu_operator_o = ALU_ADD; // Add Immediate + 3'b010: alu_operator_o = ALU_SLTS; // Set to one if Lower Than Immediate + 3'b011: alu_operator_o = ALU_SLTU; // Set to one if Lower Than Immediate Unsigned + 3'b100: alu_operator_o = ALU_XOR; // Exclusive Or with Immediate + 3'b110: alu_operator_o = ALU_OR; // Or with Immediate + 3'b111: alu_operator_o = ALU_AND; // And with Immediate + + 3'b001: begin + alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate + if (instr_rdata_i[31:25] != 7'b0) + illegal_insn_o = 1'b1; + end + + 3'b101: begin + if (instr_rdata_i[31:25] == 7'b0) + alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate + else if (instr_rdata_i[31:25] == 7'b010_0000) + alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate + else + illegal_insn_o = 1'b1; + end + + + endcase + end + + OPCODE_OP: begin // Register-Register ALU operation + + // PREFIX 11 + if (instr_rdata_i[31:30] == 2'b11) begin + + ////////////////////////////// + // IMMEDIATE BIT-MANIPULATION + ////////////////////////////// + + regfile_alu_we = 1'b1; + rega_used_o = 1'b1; + + // bit-manipulation instructions + bmask_a_mux_o = BMASK_A_S3; + bmask_b_mux_o = BMASK_B_S2; + alu_op_b_mux_sel_o = OP_B_IMM; + + unique case (instr_rdata_i[14:12]) + 3'b000: begin + alu_operator_o = ALU_BEXT; + imm_b_mux_sel_o = IMMB_S2; + bmask_b_mux_o = BMASK_B_ZERO; + end + 3'b001: begin + alu_operator_o = ALU_BEXTU; + imm_b_mux_sel_o = IMMB_S2; + bmask_b_mux_o = BMASK_B_ZERO; + end + 3'b010: begin + alu_operator_o = ALU_BINS; + imm_b_mux_sel_o = IMMB_S2; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + end + 3'b011: begin + alu_operator_o = ALU_BCLR; + end + 3'b100: begin + alu_operator_o = ALU_BSET; + end + 3'b101: begin + alu_operator_o = ALU_BREV; + // Enable write back to RD + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + // Extract the source register on operand a + imm_b_mux_sel_o = IMMB_S2; + // Map the radix to bmask_a immediate + alu_bmask_a_mux_sel_o = BMASK_A_IMM; + end + default: illegal_insn_o = 1'b1; + endcase + end + + // PREFIX 10 + else if (instr_rdata_i[31:30] == 2'b10) begin + + ////////////////////////////// + // REGISTER BIT-MANIPULATION + ////////////////////////////// + if (instr_rdata_i[29:25]==5'b00000) begin + + regfile_alu_we = 1'b1; + rega_used_o = 1'b1; + + bmask_a_mux_o = BMASK_A_S3; + bmask_b_mux_o = BMASK_B_S2; + alu_op_b_mux_sel_o = OP_B_IMM; + + unique case (instr_rdata_i[14:12]) + 3'b000: begin + alu_operator_o = ALU_BEXT; + imm_b_mux_sel_o = IMMB_S2; + bmask_b_mux_o = BMASK_B_ZERO; + //register variant + alu_op_b_mux_sel_o = OP_B_BMASK; + alu_bmask_a_mux_sel_o = BMASK_A_REG; + regb_used_o = 1'b1; + end + 3'b001: begin + alu_operator_o = ALU_BEXTU; + imm_b_mux_sel_o = IMMB_S2; + bmask_b_mux_o = BMASK_B_ZERO; + //register variant + alu_op_b_mux_sel_o = OP_B_BMASK; + alu_bmask_a_mux_sel_o = BMASK_A_REG; + regb_used_o = 1'b1; + end + 3'b010: begin + alu_operator_o = ALU_BINS; + imm_b_mux_sel_o = IMMB_S2; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + //register variant + alu_op_b_mux_sel_o = OP_B_BMASK; + alu_bmask_a_mux_sel_o = BMASK_A_REG; + alu_bmask_b_mux_sel_o = BMASK_B_REG; + regb_used_o = 1'b1; + end + 3'b011: begin + alu_operator_o = ALU_BCLR; + //register variant + regb_used_o = 1'b1; + alu_bmask_a_mux_sel_o = BMASK_A_REG; + alu_bmask_b_mux_sel_o = BMASK_B_REG; + end + 3'b100: begin + alu_operator_o = ALU_BSET; + //register variant + regb_used_o = 1'b1; + alu_bmask_a_mux_sel_o = BMASK_A_REG; + alu_bmask_b_mux_sel_o = BMASK_B_REG; + end + default: illegal_insn_o = 1'b1; + endcase + + /////////////////////// + // VECTORIAL FLOAT OPS + /////////////////////// + end else begin + // Vectorial FP not available in 'old' shared FPU + if (FPU==1 && C_XFVEC && SHARED_FP!=1) begin + + // using APU instead of ALU + apu_en = 1'b1; + alu_en_o = 1'b0; + apu_flags_src_o = APU_FLAGS_FPNEW; + // by default, set all registers to FP registers and use 2 + rega_used_o = 1'b1; + regb_used_o = 1'b1; + reg_fp_a_o = 1'b1; + reg_fp_b_o = 1'b1; + reg_fp_d_o = 1'b1; + fpu_vec_op = 1'b1; + // replication bit comes from instruction (can change for some ops) + scalar_replication_o = instr_rdata_i[14]; + // by default we need to verify rm is legal but assume it is for now + check_fprm = 1'b1; + fp_rnd_mode_o = frm_i; // all vectorial ops have rm from fcsr + + // Decode Formats + unique case (instr_rdata_i[13:12]) + // FP32 + 2'b00: begin + fpu_dst_fmt_o = fpnew_pkg::FP32; + alu_vec_mode_o = VEC_MODE32; + end + // FP16ALT + 2'b01: begin + fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + alu_vec_mode_o = VEC_MODE16; + end + // FP16 + 2'b10: begin + fpu_dst_fmt_o = fpnew_pkg::FP16; + alu_vec_mode_o = VEC_MODE16; + end + // FP8 + 2'b11: begin + fpu_dst_fmt_o = fpnew_pkg::FP8; + alu_vec_mode_o = VEC_MODE8; + end + endcase + + // By default, src=dst + fpu_src_fmt_o = fpu_dst_fmt_o; + + // decode vectorial FP instruction + unique case (instr_rdata_i[29:25]) inside + // vfadd.vfmt - Vectorial FP Addition + 5'b00001: begin + fpu_op = fpnew_pkg::ADD; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_ADDSUB; + // FPnew needs addition operands as operand B and C + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; + alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; + scalar_replication_o = 1'b0; + scalar_replication_c_o = instr_rdata_i[14]; + end + // vfsub.vfmt - Vectorial FP Subtraction + 5'b00010: begin + fpu_op = fpnew_pkg::ADD; + fpu_op_mod = 1'b1; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_ADDSUB; + // FPnew needs addition operands as operand B and C + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; + alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; + scalar_replication_o = 1'b0; + scalar_replication_c_o = instr_rdata_i[14]; + end + // vfmul.vfmt - Vectorial FP Multiplication + 5'b00011: begin + fpu_op = fpnew_pkg::MUL; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_MULT; + end + // vfdiv.vfmt - Vectorial FP Division + 5'b00100: begin + if (FP_DIVSQRT) begin + fpu_op = fpnew_pkg::DIV; + fp_op_group = DIVSQRT; + apu_type_o = APUTYPE_DIV; + end else + illegal_insn_o = 1'b1; + end + // vfmin.vfmt - Vectorial FP Minimum + 5'b00101: begin + fpu_op = fpnew_pkg::MINMAX; + fp_rnd_mode_o = 3'b000; // min + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; // instruction encoded in rm + end + // vfmax.vfmt - Vectorial FP Maximum + 5'b00110: begin + fpu_op = fpnew_pkg::MINMAX; + fp_rnd_mode_o = 3'b001; // max + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; // instruction encoded in rm + end + // vfsqrt.vfmt - Vectorial FP Square Root + 5'b00111: begin + if (FP_DIVSQRT) begin + regb_used_o = 1'b0; + fpu_op = fpnew_pkg::SQRT; + fp_op_group = DIVSQRT; + apu_type_o = APUTYPE_SQRT; + // rs2 and R must be zero + if ((instr_rdata_i[24:20] != 5'b00000) || instr_rdata_i[14]) begin + illegal_insn_o = 1'b1; + end + end else + illegal_insn_o = 1'b1; + end + // vfmac.vfmt - Vectorial FP Multiply-Accumulate + 5'b01000: begin + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; // third operand is rd + reg_fp_c_o = 1'b1; + fpu_op = fpnew_pkg::FMADD; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_MAC; + end + // vfmre.vfmt - Vectorial FP Multiply-Reduce + 5'b01001: begin + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; // third operand is rd + reg_fp_c_o = 1'b1; + fpu_op = fpnew_pkg::FMADD; + fpu_op_mod = 1'b1; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_MAC; + end + // Moves, Conversions, Classifications + 5'b01100: begin + regb_used_o = 1'b0; + scalar_replication_o = 1'b0; + // Decode Operation in rs2 + unique case (instr_rdata_i[24:20]) inside + // vfmv.{x.vfmt/vfmt.x} - Vectorial FP Reg <-> GP Reg Moves + 5'b00000: begin + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + fpu_op = fpnew_pkg::SGNJ; + fp_rnd_mode_o = 3'b011; // passthrough without checking nan-box + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + // GP reg to FP reg + if (instr_rdata_i[14]) begin + reg_fp_a_o = 1'b0; // go from integer regfile + fpu_op_mod = 1'b0; // nan-box result + end + // FP reg to GP reg + else begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op_mod = 1'b1; // sign-extend result + end + end + // vfclass.vfmt - Vectorial FP Classifications + 5'b00001: begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::CLASSIFY; + fp_rnd_mode_o = 3'b000; + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + // R must not be set + if (instr_rdata_i[14]) illegal_insn_o = 1'b1; + end + // vfcvt.{x.vfmt/vfmt.x} - Vectorial FP <-> Int Conversions + 5'b0001?: begin + fp_op_group = CONV; + fpu_op_mod = instr_rdata_i[14]; // signed/unsigned switch + apu_type_o = APUTYPE_CAST; + // Integer width matches FP width + unique case (instr_rdata_i[13:12]) + // FP32 + 2'b00 : fpu_int_fmt_o = fpnew_pkg::INT32; + // FP16[ALT] + 2'b01, + 2'b10: fpu_int_fmt_o = fpnew_pkg::INT16; + // FP8 + 2'b11: fpu_int_fmt_o = fpnew_pkg::INT8; + endcase + // Int to FP conversion + if (instr_rdata_i[20]) begin + reg_fp_a_o = 1'b0; // go from integer regfile + fpu_op = fpnew_pkg::I2F; + end + // FP to Int conversion + else begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::F2I; + end + end + // vfcvt.vfmt.vfmt - Vectorial FP <-> FP Conversions + 5'b001??: begin + fpu_op = fpnew_pkg::F2F; + fp_op_group = CONV; + apu_type_o = APUTYPE_CAST; + // check source format + unique case (instr_rdata_i[21:20]) + // Only process instruction if corresponding extension is active (static) + 2'b00: begin + fpu_src_fmt_o = fpnew_pkg::FP32; + if (~C_RVF) illegal_insn_o = 1'b1; + end + 2'b01: begin + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + if (~C_XF16ALT) illegal_insn_o = 1'b1; + end + 2'b10: begin + fpu_src_fmt_o = fpnew_pkg::FP16; + if (~C_XF16) illegal_insn_o = 1'b1; + end + 2'b11: begin + fpu_src_fmt_o = fpnew_pkg::FP8; + if (~C_XF8) illegal_insn_o = 1'b1; + end + endcase + // R must not be set + if (instr_rdata_i[14]) illegal_insn_o = 1'b1; + end + // others + default : illegal_insn_o = 1'b1; + endcase + end + // vfsgnj.vfmt - Vectorial FP Sign Injection + 5'b01101: begin + fpu_op = fpnew_pkg::SGNJ; + fp_rnd_mode_o = 3'b000; // sgnj + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfsgnjn.vfmt - Vectorial FP Negated Sign Injection + 5'b01110: begin + fpu_op = fpnew_pkg::SGNJ; + fp_rnd_mode_o = 3'b001; // sgnjn + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfsgnjx.vfmt - Vectorial FP Xored Sign Injection + 5'b01111: begin + fpu_op = fpnew_pkg::SGNJ; + fp_rnd_mode_o = 3'b010; // sgnjx + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfeq.vfmt - Vectorial FP Equals + 5'b10000: begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::CMP; + fp_rnd_mode_o = 3'b010; // eq + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfne.vfmt - Vectorial FP Not Equals + 5'b10001: begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::CMP; + fpu_op_mod = 1'b1; // invert output + fp_rnd_mode_o = 3'b010; // eq + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vflt.vfmt - Vectorial FP Less Than + 5'b10010: begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::CMP; + fp_rnd_mode_o = 3'b001; // lt + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfge.vfmt - Vectorial FP Greater Than or Equals + 5'b10011: begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::CMP; + fpu_op_mod = 1'b1; // invert output + fp_rnd_mode_o = 3'b001; // lt + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfle.vfmt - Vectorial FP Less Than or Equals + 5'b10100: begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::CMP; + fp_rnd_mode_o = 3'b000; // le + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfgt.vfmt - Vectorial FP Greater Than + 5'b10101: begin + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::CMP; + fpu_op_mod = 1'b1; // invert output + fp_rnd_mode_o = 3'b000; // le + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; + end + // vfcpk{a-d}.vfmt.s/d + 5'b110??: begin + // vfcpk{{a/c}/{b/d}} selection in R bit + fpu_op_mod = instr_rdata_i[14]; + fp_op_group = CONV; + apu_type_o = APUTYPE_CAST; + scalar_replication_o = 1'b0; + + if (instr_rdata_i[25]) fpu_op = fpnew_pkg::CPKCD; // vfcpk{c/d} + else fpu_op = fpnew_pkg::CPKAB; // vfcpk{a/b} + + // vfcpk{a-d}.vfmt.d - from double + if (instr_rdata_i[26]) begin + fpu_src_fmt_o = fpnew_pkg::FP64; + if (~C_RVD) illegal_insn_o = 1'b1; + end + // vfcpk{a-d}.vfmt.s + else begin + fpu_src_fmt_o = fpnew_pkg::FP32; + if (~C_RVF) illegal_insn_o = 1'b1; + end + // Resolve legal vfcpk / format combinations (mostly static) + if (fpu_op == fpnew_pkg::CPKCD) begin // vfcpk{c/d} not possible unless FP8 and FLEN>=64 + if (~C_XF8 || ~C_RVD) illegal_insn_o = 1'b1; + end else begin + if (instr_rdata_i[14]) begin // vfcpkb + // vfcpkb not possible for FP32 + if (fpu_dst_fmt_o == fpnew_pkg::FP32) illegal_insn_o = 1'b1; + // vfcpkb not possible for FP16[ALT] if not RVD + if (~C_RVD && (fpu_dst_fmt_o != fpnew_pkg::FP8)) illegal_insn_o = 1'b1; + end + end + end + // Rest are illegal instructions + default: begin + illegal_insn_o = 1'b1; + end + endcase + + // check enabled formats (static) + // need RVD for F vectors + if ((~C_RVF || ~C_RVD) && fpu_dst_fmt_o == fpnew_pkg::FP32) illegal_insn_o = 1'b1; + // need RVF for F16 vectors + if ((~C_XF16 || ~C_RVF) && fpu_dst_fmt_o == fpnew_pkg::FP16) illegal_insn_o = 1'b1; + // need RVF for F16 vectors + if ((~C_XF16ALT || ~C_RVF) && fpu_dst_fmt_o == fpnew_pkg::FP16ALT) begin + illegal_insn_o = 1'b1; + end + // need F16 for F8 vectors + if ((~C_XF8 || (~C_XF16 && ~C_XF16ALT)) && fpu_dst_fmt_o == fpnew_pkg::FP8) begin + illegal_insn_o = 1'b1; + end + + // check rounding mode + if (check_fprm) begin + unique case (frm_i) inside + [3'b000:3'b100] : ; //legal rounding modes + default : illegal_insn_o = 1'b1; + endcase + end + + // Set latencies for FPnew from config. The C_LAT constants contain the number + // of pipeline registers. the APU takes the following values: + // 1 = single cycle (no latency), 2 = one pipestage, 3 = two or more pipestages + case (fp_op_group) + // ADDMUL has format dependent latency + ADDMUL : begin + unique case (fpu_dst_fmt_o) + fpnew_pkg::FP32 : apu_lat_o = (C_LAT_FP32<2) ? C_LAT_FP32+1 : 2'h3; + fpnew_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; + fpnew_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; + fpnew_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; + default : ; + endcase + end + // DIVSQRT is iterative and takes more than 2 cycles + DIVSQRT : apu_lat_o = 2'h3; + // NONCOMP uses the same latency for all formats + NONCOMP : apu_lat_o = (C_LAT_NONCOMP<2) ? C_LAT_NONCOMP+1 : 2'h3; + // CONV uses the same latency for all formats + CONV : apu_lat_o = (C_LAT_CONV<2) ? C_LAT_CONV+1 : 2'h3; + endcase + + // Set FPnew OP and OPMOD as the APU op + apu_op_o = {fpu_vec_op, fpu_op_mod, fpu_op}; + end + // FPU!=1 or no Vectors or old shared unit + else begin + illegal_insn_o = 1'b1; + end + end // Vectorial Float Ops + + end // prefix 10 + + // PREFIX 00/01 + else begin + // non bit-manipulation instructions + regfile_alu_we = 1'b1; + rega_used_o = 1'b1; + + if (~instr_rdata_i[28]) regb_used_o = 1'b1; + + unique case ({instr_rdata_i[30:25], instr_rdata_i[14:12]}) + // RV32I ALU operations + {6'b00_0000, 3'b000}: alu_operator_o = ALU_ADD; // Add + {6'b10_0000, 3'b000}: alu_operator_o = ALU_SUB; // Sub + {6'b00_0000, 3'b010}: alu_operator_o = ALU_SLTS; // Set Lower Than + {6'b00_0000, 3'b011}: alu_operator_o = ALU_SLTU; // Set Lower Than Unsigned + {6'b00_0000, 3'b100}: alu_operator_o = ALU_XOR; // Xor + {6'b00_0000, 3'b110}: alu_operator_o = ALU_OR; // Or + {6'b00_0000, 3'b111}: alu_operator_o = ALU_AND; // And + {6'b00_0000, 3'b001}: alu_operator_o = ALU_SLL; // Shift Left Logical + {6'b00_0000, 3'b101}: alu_operator_o = ALU_SRL; // Shift Right Logical + {6'b10_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic + + // supported RV32M instructions + {6'b00_0001, 3'b000}: begin // mul + alu_en_o = 1'b0; + mult_int_en = 1'b1; + mult_operator_o = MUL_MAC32; + regc_mux_o = REGC_ZERO; + end + {6'b00_0001, 3'b001}: begin // mulh + alu_en_o = 1'b0; + regc_used_o = 1'b1; + regc_mux_o = REGC_ZERO; + mult_signed_mode_o = 2'b11; + mult_int_en = 1'b1; + mult_operator_o = MUL_H; + instr_multicycle_o = 1'b1; + end + {6'b00_0001, 3'b010}: begin // mulhsu + alu_en_o = 1'b0; + regc_used_o = 1'b1; + regc_mux_o = REGC_ZERO; + mult_signed_mode_o = 2'b01; + mult_int_en = 1'b1; + mult_operator_o = MUL_H; + instr_multicycle_o = 1'b1; + end + {6'b00_0001, 3'b011}: begin // mulhu + alu_en_o = 1'b0; + regc_used_o = 1'b1; + regc_mux_o = REGC_ZERO; + mult_signed_mode_o = 2'b00; + mult_int_en = 1'b1; + mult_operator_o = MUL_H; + instr_multicycle_o = 1'b1; + end + {6'b00_0001, 3'b100}: begin // div + alu_op_a_mux_sel_o = OP_A_REGB_OR_FWD; + alu_op_b_mux_sel_o = OP_B_REGC_OR_FWD; + regc_mux_o = REGC_S1; + regc_used_o = 1'b1; + regb_used_o = 1'b1; + rega_used_o = 1'b0; + alu_operator_o = ALU_DIV; + instr_multicycle_o = 1'b1; + `USE_APU_INT_DIV + end + {6'b00_0001, 3'b101}: begin // divu + alu_op_a_mux_sel_o = OP_A_REGB_OR_FWD; + alu_op_b_mux_sel_o = OP_B_REGC_OR_FWD; + regc_mux_o = REGC_S1; + regc_used_o = 1'b1; + regb_used_o = 1'b1; + rega_used_o = 1'b0; + alu_operator_o = ALU_DIVU; + instr_multicycle_o = 1'b1; + `USE_APU_INT_DIV + end + {6'b00_0001, 3'b110}: begin // rem + alu_op_a_mux_sel_o = OP_A_REGB_OR_FWD; + alu_op_b_mux_sel_o = OP_B_REGC_OR_FWD; + regc_mux_o = REGC_S1; + regc_used_o = 1'b1; + regb_used_o = 1'b1; + rega_used_o = 1'b0; + alu_operator_o = ALU_REM; + instr_multicycle_o = 1'b1; + `USE_APU_INT_DIV + end + {6'b00_0001, 3'b111}: begin // remu + alu_op_a_mux_sel_o = OP_A_REGB_OR_FWD; + alu_op_b_mux_sel_o = OP_B_REGC_OR_FWD; + regc_mux_o = REGC_S1; + regc_used_o = 1'b1; + regb_used_o = 1'b1; + rega_used_o = 1'b0; + alu_operator_o = ALU_REMU; + instr_multicycle_o = 1'b1; + `USE_APU_INT_DIV + end + + // PULP specific instructions + {6'b10_0001, 3'b000}: begin // p.mac + alu_en_o = 1'b0; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + mult_int_en = 1'b1; + mult_operator_o = MUL_MAC32; + `USE_APU_INT_MULT + end + {6'b10_0001, 3'b001}: begin // p.msu + alu_en_o = 1'b0; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + mult_int_en = 1'b1; + mult_operator_o = MUL_MSU32; + `USE_APU_INT_MULT + end + {6'b00_0010, 3'b010}: alu_operator_o = ALU_SLETS; // Set Lower Equal Than p.slet + {6'b00_0010, 3'b011}: alu_operator_o = ALU_SLETU; // Set Lower Equal Than Unsigned p.sletu + {6'b00_0010, 3'b100}: begin alu_operator_o = ALU_MIN; end // Min p.min + {6'b00_0010, 3'b101}: begin alu_operator_o = ALU_MINU; end // Min Unsigned + {6'b00_0010, 3'b110}: begin alu_operator_o = ALU_MAX; end // Max + {6'b00_0010, 3'b111}: begin alu_operator_o = ALU_MAXU; end // Max Unsigned + {6'b00_0100, 3'b101}: begin alu_operator_o = ALU_ROR; end // Rotate Right + + // PULP specific instructions using only one source register + {6'b00_1000, 3'b000}: begin alu_operator_o = ALU_FF1; end // Find First 1 + {6'b00_1000, 3'b001}: begin alu_operator_o = ALU_FL1; end // Find Last 1 + {6'b00_1000, 3'b010}: begin alu_operator_o = ALU_CLB; end // Count Leading Bits + {6'b00_1000, 3'b011}: begin alu_operator_o = ALU_CNT; end // Count set bits (popcount) + {6'b00_1000, 3'b100}: begin alu_operator_o = ALU_EXTS; alu_vec_mode_o = VEC_MODE16; end // Sign-extend Half-word + {6'b00_1000, 3'b101}: begin alu_operator_o = ALU_EXT; alu_vec_mode_o = VEC_MODE16; end // Zero-extend Half-word + {6'b00_1000, 3'b110}: begin alu_operator_o = ALU_EXTS; alu_vec_mode_o = VEC_MODE8; end // Sign-extend Byte + {6'b00_1000, 3'b111}: begin alu_operator_o = ALU_EXT; alu_vec_mode_o = VEC_MODE8; end // Zero-extend Byte + + {6'b00_0010, 3'b000}: begin alu_operator_o = ALU_ABS; end // p.abs + + {6'b00_1010, 3'b001}: begin // p.clip + alu_operator_o = ALU_CLIP; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_CLIP; + end + + {6'b00_1010, 3'b010}: begin // p.clipu + alu_operator_o = ALU_CLIPU; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_CLIP; + end + + {6'b00_1010, 3'b101}: begin // p.clipr + alu_operator_o = ALU_CLIP; + regb_used_o = 1'b1; + end + + {6'b00_1010, 3'b110}: begin // p.clipur + alu_operator_o = ALU_CLIPU; + regb_used_o = 1'b1; + end + + default: begin + illegal_insn_o = 1'b1; + end + endcase + end + end + + //////////////////////////// + // ______ _____ _ _ // + // | ____| __ \| | | | // + // | |__ | |__) | | | | // + // | __| | ___/| | | | // + // | | | | | |__| | // + // |_| |_| \____/ // + // // + //////////////////////////// + + // floating point arithmetic + OPCODE_OP_FP: begin + if (FPU==1) begin + + // using APU instead of ALU + apu_en = 1'b1; + alu_en_o = 1'b0; + // Private and new shared FP use FPnew + apu_flags_src_o = (SHARED_FP==1) ? APU_FLAGS_FP : APU_FLAGS_FPNEW; + // by default, set all registers to FP registers and use 2 + rega_used_o = 1'b1; + regb_used_o = 1'b1; + reg_fp_a_o = 1'b1; + reg_fp_b_o = 1'b1; + reg_fp_d_o = 1'b1; + // by default we need to verify rm is legal but assume it is for now + check_fprm = 1'b1; + fp_rnd_mode_o = instr_rdata_i[14:12]; + + // Decode Formats (preliminary, can change for some ops) + unique case (instr_rdata_i[26:25]) + // FP32 + 2'b00: fpu_dst_fmt_o = fpnew_pkg::FP32; + // FP64 + 2'b01: fpu_dst_fmt_o = fpnew_pkg::FP64; + // FP16 or FP16ALT + 2'b10: begin + // FP16alt encoded in rm field + if (instr_rdata_i[14:12]==3'b101) fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + // this can still change to FP16ALT + else fpu_dst_fmt_o = fpnew_pkg::FP16; + end + // FP8 + 2'b11: fpu_dst_fmt_o = fpnew_pkg::FP8; + endcase + + // By default, src=dst + fpu_src_fmt_o = fpu_dst_fmt_o; + + // decode FP instruction + unique case (instr_rdata_i[31:27]) + // fadd.fmt - FP Addition + 5'b00000: begin + fpu_op = fpnew_pkg::ADD; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_ADDSUB; + apu_op_o = 2'b0; + apu_lat_o = (PIPE_REG_ADDSUB==1) ? 2'h2 : 2'h1; + // FPnew needs addition operands as operand B and C + if (SHARED_FP!=1) begin + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; + alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; + end + end + // fsub.fmt - FP Subtraction + 5'b00001: begin + fpu_op = fpnew_pkg::ADD; + fpu_op_mod = 1'b1; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_ADDSUB; + apu_op_o = 2'b1; + apu_lat_o = (PIPE_REG_ADDSUB==1) ? 2'h2 : 2'h1; + if (SHARED_FP!=1) begin + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; + alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; + end + end + // fmul.fmt - FP Multiplication + 5'b00010: begin + fpu_op = fpnew_pkg::MUL; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_MULT; + apu_lat_o = (PIPE_REG_MULT==1) ? 2'h2 : 2'h1; + end + // fdiv.fmt - FP Division + 5'b00011: begin + if (FP_DIVSQRT) begin + fpu_op = fpnew_pkg::DIV; + fp_op_group = DIVSQRT; + apu_type_o = APUTYPE_DIV; + apu_lat_o = 2'h3; + end else + illegal_insn_o = 1'b1; + end + // fsqrt.fmt - FP Square Root + 5'b01011: begin + if (FP_DIVSQRT) begin + regb_used_o = 1'b0; + fpu_op = fpnew_pkg::SQRT; + fp_op_group = DIVSQRT; + apu_type_o = APUTYPE_SQRT; + apu_op_o = 1'b1; + apu_lat_o = 2'h3; + // rs2 must be zero + if (instr_rdata_i[24:20] != 5'b00000) illegal_insn_o = 1'b1; + end else + illegal_insn_o = 1'b1; + end + // fsgn{j[n]/jx}.fmt - FP Sign Injection + 5'b00100: begin + // old FPU needs ALU + if (SHARED_FP==1) begin + apu_en = 1'b0; + alu_en_o = 1'b1; + regfile_alu_we = 1'b1; + case (instr_rdata_i[14:12]) + //fsgnj.s + 3'h0: alu_operator_o = ALU_FSGNJ; + //fsgnjn.s + 3'h1: alu_operator_o = ALU_FSGNJN; + //fsgnjx.s + 3'h2: alu_operator_o = ALU_FSGNJX; + // illegal instruction + default: illegal_insn_o = 1'b1; + endcase + // FPnew supports SGNJ + end else begin + fpu_op = fpnew_pkg::SGNJ; + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (C_XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (!(instr_rdata_i[14:12] inside {[3'b000:3'b010], [3'b100:3'b110]})) begin + illegal_insn_o = 1'b1; + end + // FP16ALT uses special encoding here + if (instr_rdata_i[14]) begin + fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end else begin + fp_rnd_mode_o = {1'b0, instr_rdata_i[13:12]}; + end + end else begin + if (!(instr_rdata_i[14:12] inside {[3'b000:3'b010]})) illegal_insn_o = 1'b1; + end + end + end + // fmin/fmax.fmt - FP Minimum / Maximum + 5'b00101: begin + // old FPU needs ALU + if (SHARED_FP==1) begin + apu_en = 1'b0; + alu_en_o = 1'b1; + regfile_alu_we = 1'b1; + case (instr_rdata_i[14:12]) + //fmin.s + 3'h0: alu_operator_o = ALU_FMIN; + //fmax.s + 3'h1: alu_operator_o = ALU_FMAX; + default: illegal_insn_o = 1'b1; + endcase + // FPnew supports MIN-MAX + end else begin + fpu_op = fpnew_pkg::MINMAX; + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (C_XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (!(instr_rdata_i[14:12] inside {[3'b000:3'b001], [3'b100:3'b101]})) begin + illegal_insn_o = 1'b1; + end + // FP16ALT uses special encoding here + if (instr_rdata_i[14]) begin + fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end else begin + fp_rnd_mode_o = {1'b0, instr_rdata_i[13:12]}; + end + end else begin + if (!(instr_rdata_i[14:12] inside {[3'b000:3'b001]})) illegal_insn_o = 1'b1; + end + end + end + // fcvt.fmt.fmt - FP to FP Conversion + 5'b01000: begin + // old FPU has hacky fcvt.s.d + if (SHARED_FP==1) begin + apu_en = 1'b0; + alu_en_o = 1'b1; + regfile_alu_we = 1'b1; + regb_used_o = 1'b0; + alu_operator_o = ALU_FKEEP; + // FPnew does proper casts + end else begin + regb_used_o = 1'b0; + fpu_op = fpnew_pkg::F2F; + fp_op_group = CONV; + apu_type_o = APUTYPE_CAST; + // bits [22:20] used, other bits must be 0 + if (instr_rdata_i[24:23]) illegal_insn_o = 1'b1; + // check source format + unique case (instr_rdata_i[22:20]) + // Only process instruction if corresponding extension is active (static) + 3'b000: begin + if (~C_RVF) illegal_insn_o = 1'b1; + fpu_src_fmt_o = fpnew_pkg::FP32; + end + 3'b001: begin + if (~C_RVD) illegal_insn_o = 1'b1; + fpu_src_fmt_o = fpnew_pkg::FP64; + end + 3'b010: begin + if (~C_XF16) illegal_insn_o = 1'b1; + fpu_src_fmt_o = fpnew_pkg::FP16; + end + 3'b110: begin + if (~C_XF16ALT) illegal_insn_o = 1'b1; + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end + 3'b011: begin + if (~C_XF8) illegal_insn_o = 1'b1; + fpu_src_fmt_o = fpnew_pkg::FP8; + end + default: illegal_insn_o = 1'b1; + endcase + end + end + // fmulex.s.fmt - FP Expanding Multiplication to FP32 + 5'b01001: begin + fpu_op = fpnew_pkg::MUL; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_MULT; + apu_lat_o = (PIPE_REG_MULT==1) ? 2'h2 : 2'h1; + // set dst format to FP32 + fpu_dst_fmt_o = fpnew_pkg::FP32; + end + // fmacex.s.fmt - FP Expanding Multipy-Accumulate to FP32 + 5'b01010: begin + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; // third operand is rd + reg_fp_c_o = 1'b1; + fpu_op = fpnew_pkg::FMADD; + fp_op_group = ADDMUL; + apu_type_o = APUTYPE_MAC; + apu_lat_o = (PIPE_REG_MULT==1) ? 2'h2 : 2'h1; + // set dst format to FP32 + fpu_dst_fmt_o = fpnew_pkg::FP32; + end + // feq/flt/fle.fmt - FP Comparisons + 5'b10100: begin + // old FPU needs ALU + if (SHARED_FP==1) begin + apu_en = 1'b0; + alu_en_o = 1'b1; + regfile_alu_we = 1'b1; + reg_fp_d_o = 1'b0; + case (instr_rdata_i[14:12]) + //fle.s + 3'h0: alu_operator_o = ALU_FLE; + //flt.s + 3'h1: alu_operator_o = ALU_FLT; + //feq.s + 3'h2: alu_operator_o = ALU_FEQ; + default: illegal_insn_o = 1'b1; + endcase + // FPnew supports comparisons + end else begin + fpu_op = fpnew_pkg::CMP; + fp_op_group = NONCOMP; + reg_fp_d_o = 1'b0; // go to integer regfile + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (C_XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (!(instr_rdata_i[14:12] inside {[3'b000:3'b010], [3'b100:3'b110]})) begin + illegal_insn_o = 1'b1; + end + // FP16ALT uses special encoding here + if (instr_rdata_i[14]) begin + fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end else begin + fp_rnd_mode_o = {1'b0, instr_rdata_i[13:12]}; + end + end else begin + if (!(instr_rdata_i[14:12] inside {[3'b000:3'b010]})) illegal_insn_o = 1'b1; + end + end + end + // fcvt.ifmt.fmt - FP to Int Conversion + 5'b11000: begin + regb_used_o = 1'b0; + reg_fp_d_o = 1'b0; // go to integer regfile + fpu_op = fpnew_pkg::F2I; + fp_op_group = CONV; + fpu_op_mod = instr_rdata_i[20]; // signed/unsigned switch + apu_type_o = APUTYPE_CAST; + apu_op_o = 2'b1; + apu_lat_o = (PIPE_REG_CAST==1) ? 2'h2 : 2'h1; + + unique case (instr_rdata_i[26:25]) //fix for casting to different formats other than FP32 + 2'b00: begin + if (~C_RVF) illegal_insn_o = 1; + else fpu_src_fmt_o = fpnew_pkg::FP32; + end + 2'b01: begin + if (~C_RVD) illegal_insn_o = 1; + else fpu_src_fmt_o = fpnew_pkg::FP64; + end + 2'b10: begin + if (instr_rdata_i[14:12] == 3'b101) begin + if (~C_XF16ALT) illegal_insn_o = 1; + else fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end else if (~C_XF16) begin + illegal_insn_o = 1; + end else begin + fpu_src_fmt_o = fpnew_pkg::FP16; + end + end + 2'b11: begin + if (~C_XF8) illegal_insn_o = 1; + else fpu_src_fmt_o = fpnew_pkg::FP8; + end + endcase // unique case (instr_rdata_i[26:25]) + // bits [21:20] used, other bits must be 0 + if (instr_rdata_i[24:21]) illegal_insn_o = 1'b1; // in RV32, no casts to L allowed. + end + // fcvt.fmt.ifmt - Int to FP Conversion + 5'b11010: begin + regb_used_o = 1'b0; + reg_fp_a_o = 1'b0; // go from integer regfile + fpu_op = fpnew_pkg::I2F; + fp_op_group = CONV; + fpu_op_mod = instr_rdata_i[20]; // signed/unsigned switch + apu_type_o = APUTYPE_CAST; + apu_op_o = 2'b0; + apu_lat_o = (PIPE_REG_CAST==1) ? 2'h2 : 2'h1; + // bits [21:20] used, other bits must be 0 + if (instr_rdata_i[24:21]) illegal_insn_o = 1'b1; // in RV32, no casts to L allowed. + end + // move and class + 5'b11100: begin + // old fpu maps this to ALU ops + if (SHARED_FP==1) begin + apu_en = 1'b0; + alu_en_o = 1'b1; + regfile_alu_we = 1'b1; + case (instr_rdata_i[14:12]) + // fmv.x.s - move from floating point to gp register + 3'b000: begin + reg_fp_d_o = 1'b0; // go to integer regfile + alu_operator_o = ALU_ADD; + end + // fclass - classify float + 3'b001: begin + regb_used_o = 1'b0; + reg_fp_d_o = 1'b0; // go to integer regfile + alu_operator_o = ALU_FCLASS; + end + default: illegal_insn_o = 1'b1; + endcase + // FPnew does proper NaN-Boxing + end else begin + regb_used_o = 1'b0; + reg_fp_d_o = 1'b0; // go to integer regfile + fp_op_group = NONCOMP; + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; // instruction encoded in rm, do the check here + // fmv.x.fmt - FPR to GPR Move + if (instr_rdata_i[14:12] == 3'b000 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100)) begin + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + fpu_op = fpnew_pkg::SGNJ; // mapped to SGNJ-passthrough since no recoding + fpu_op_mod = 1'b1; // sign-extend result + fp_rnd_mode_o = 3'b011; // passthrough without checking nan-box + // FP16ALT uses special encoding here + if (instr_rdata_i[14]) begin + fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end + // fclass.fmt - FP Classify + end else if (instr_rdata_i[14:12] == 3'b001 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b101)) begin + fpu_op = fpnew_pkg::CLASSIFY; + fp_rnd_mode_o = 3'b000; + // FP16ALT uses special encoding here + if (instr_rdata_i[14]) begin + fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end + end else begin + illegal_insn_o = 1'b1; + end + // rs2 must be zero + if (instr_rdata_i[24:20]) illegal_insn_o = 1'b1; + end + end + // fmv.fmt.x - GPR to FPR Move + 5'b11110: begin + // old fpu maps this to ALU ops + if (SHARED_FP==1) begin + apu_en = 1'b0; + alu_en_o = 1'b1; + regfile_alu_we = 1'b1; + reg_fp_a_o = 1'b0; // go from integer regfile + alu_operator_o = ALU_ADD; + // FPnew does proper NaN-Boxing + end else begin + regb_used_o = 1'b0; + reg_fp_a_o = 1'b0; // go from integer regfile + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + fpu_op = fpnew_pkg::SGNJ; // mapped to SGNJ-passthrough since no recoding + fpu_op_mod = 1'b0; // nan-box result + fp_op_group = NONCOMP; + fp_rnd_mode_o = 3'b011; // passthrough without checking nan-box + apu_type_o = APUTYPE_FP; // doesn't matter much as long as it's not div + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (instr_rdata_i[14:12] == 3'b000 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100)) begin + // FP16ALT uses special encoding here + if (instr_rdata_i[14]) begin + fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + fpu_src_fmt_o = fpnew_pkg::FP16ALT; + end + end else begin + illegal_insn_o = 1'b1; + end + // rs2 must be zero + if (instr_rdata_i[24:20] != 5'b00000) illegal_insn_o = 1'b1; + end + end + // Rest are illegal instructions + default: begin + illegal_insn_o = 1'b1; + end + endcase + + // check enabled formats (static) + if (~C_RVF && fpu_dst_fmt_o == fpnew_pkg::FP32) illegal_insn_o = 1'b1; + if ((~C_RVD || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP64) illegal_insn_o = 1'b1; + if ((~C_XF16 || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP16) illegal_insn_o = 1'b1; + if ((~C_XF16ALT || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP16ALT) begin + illegal_insn_o = 1'b1; + end + if ((~C_XF8 || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP8) illegal_insn_o = 1'b1; + + // check rounding mode + if (check_fprm) begin + unique case (instr_rdata_i[14:12]) inside + [3'b000:3'b100]: ; //legal rounding modes + 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 + if (~C_XF16ALT || fpu_dst_fmt_o != fpnew_pkg::FP16ALT) illegal_insn_o = 1'b1; + // actual rounding mode from frm csr + unique case (frm_i) inside + [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes + default : illegal_insn_o = 1'b1; + endcase + end + 3'b111: begin + // rounding mode from frm csr + unique case (frm_i) inside + [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes + default : illegal_insn_o = 1'b1; + endcase + end + default : illegal_insn_o = 1'b1; + endcase + end + + // Set latencies for FPnew from config. The C_LAT constants contain the number + // of pipeline registers. the APU takes the following values: + // 1 = single cycle (no latency), 2 = one pipestage, 3 = two or more pipestages + if (SHARED_FP!=1) begin + case (fp_op_group) + // ADDMUL has format dependent latency + ADDMUL : begin + unique case (fpu_dst_fmt_o) + fpnew_pkg::FP32 : apu_lat_o = (C_LAT_FP32<2) ? C_LAT_FP32+1 : 2'h3; + fpnew_pkg::FP64 : apu_lat_o = (C_LAT_FP64<2) ? C_LAT_FP64+1 : 2'h3; + fpnew_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; + fpnew_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; + fpnew_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; + default : ; + endcase + end + // DIVSQRT is iterative and takes more than 2 cycles + DIVSQRT : apu_lat_o = 2'h3; + // NONCOMP uses the same latency for all formats + NONCOMP : apu_lat_o = (C_LAT_NONCOMP<2) ? C_LAT_NONCOMP+1 : 2'h3; + // CONV uses the same latency for all formats + CONV : apu_lat_o = (C_LAT_CONV<2) ? C_LAT_CONV+1 : 2'h3; + endcase + end + + // Set FPnew OP and OPMOD as the APU op + if (SHARED_FP!=1) apu_op_o = {fpu_vec_op, fpu_op_mod, fpu_op}; + + end + // FPU!=1 + else + illegal_insn_o = 1'b1; + end + + // floating point fused arithmetic + OPCODE_OP_FMADD, + OPCODE_OP_FMSUB, + OPCODE_OP_FNMSUB, + OPCODE_OP_FNMADD : begin + if (FPU==1) begin + // using APU instead of ALU + apu_en = 1'b1; + alu_en_o = 1'b0; + // Private and new shared FP use FPnew + apu_flags_src_o = (SHARED_FP==1) ? APU_FLAGS_FP : APU_FLAGS_FPNEW; + apu_type_o = APUTYPE_MAC; + apu_lat_o = (PIPE_REG_MAC>1) ? 2'h3 : 2'h2; + // all registers are FP registers and use three + rega_used_o = 1'b1; + regb_used_o = 1'b1; + regc_used_o = 1'b1; + regc_mux_o = REGC_S4; + reg_fp_a_o = 1'b1; + reg_fp_b_o = 1'b1; + reg_fp_c_o = 1'b1; + reg_fp_d_o = 1'b1; + fp_rnd_mode_o = instr_rdata_i[14:12]; + + // Decode Formats + unique case (instr_rdata_i[26:25]) + // FP32 + 2'b00 : fpu_dst_fmt_o = fpnew_pkg::FP32; + // FP64 + 2'b01 : fpu_dst_fmt_o = fpnew_pkg::FP64; + // FP16 or FP16ALT + 2'b10 : begin + // FP16alt encoded in rm field + if (instr_rdata_i[14:12]==3'b101) fpu_dst_fmt_o = fpnew_pkg::FP16ALT; + else fpu_dst_fmt_o = fpnew_pkg::FP16; + end + // FP8 + 2'b11 : fpu_dst_fmt_o = fpnew_pkg::FP8; + endcase + + // By default, src=dst + fpu_src_fmt_o = fpu_dst_fmt_o; + + // decode FP intstruction + unique case (instr_rdata_i[6:0]) + // fmadd.fmt - FP Fused multiply-add + OPCODE_OP_FMADD : begin + fpu_op = fpnew_pkg::FMADD; + apu_op_o = 2'b00; + end + // fmsub.fmt - FP Fused multiply-subtract + OPCODE_OP_FMSUB : begin + fpu_op = fpnew_pkg::FMADD; + fpu_op_mod = 1'b1; + apu_op_o = 2'b01; + end + // fnmsub.fmt - FP Negated fused multiply-subtract + OPCODE_OP_FNMSUB : begin + fpu_op = fpnew_pkg::FNMSUB; + apu_op_o = 2'b10; + end + // fnmadd.fmt - FP Negated fused multiply-add + OPCODE_OP_FNMADD : begin + fpu_op = fpnew_pkg::FNMSUB; + fpu_op_mod = 1'b1; + apu_op_o = 2'b11; + end + endcase + + // check enabled formats (static) + if (~C_RVF && fpu_dst_fmt_o == fpnew_pkg::FP32) illegal_insn_o = 1'b1; + if ((~C_RVD || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP64) illegal_insn_o = 1'b1; + if ((~C_XF16 || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP16) illegal_insn_o = 1'b1; + if ((~C_XF16ALT || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP16ALT) begin + illegal_insn_o = 1'b1; + end + if ((~C_XF8 || SHARED_FP==1) && fpu_dst_fmt_o == fpnew_pkg::FP8) illegal_insn_o = 1'b1; + + // check rounding mode + unique case (instr_rdata_i[14:12]) inside + [3'b000:3'b100]: ; //legal rounding modes + 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 + if (~C_XF16ALT || fpu_dst_fmt_o != fpnew_pkg::FP16ALT) illegal_insn_o = 1'b1; + // actual rounding mode from frm csr + unique case (frm_i) inside + [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes + default : illegal_insn_o = 1'b1; + endcase + end + 3'b111: begin + // rounding mode from frm csr + unique case (frm_i) inside + [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes + default : illegal_insn_o = 1'b1; + endcase + end + default : illegal_insn_o = 1'b1; + endcase + + // Set latencies for FPnew from config. The C_LAT constants contain the number + // of pipeline registers. the APU takes the following values: + // 1 = single cycle (no latency), 2 = one pipestage, 3 = two or more pipestages + if (SHARED_FP!=1) begin + // format dependent latency + unique case (fpu_dst_fmt_o) + fpnew_pkg::FP32 : apu_lat_o = (C_LAT_FP32<2) ? C_LAT_FP32+1 : 2'h3; + fpnew_pkg::FP64 : apu_lat_o = (C_LAT_FP64<2) ? C_LAT_FP64+1 : 2'h3; + fpnew_pkg::FP16 : apu_lat_o = (C_LAT_FP16<2) ? C_LAT_FP16+1 : 2'h3; + fpnew_pkg::FP16ALT : apu_lat_o = (C_LAT_FP16ALT<2) ? C_LAT_FP16ALT+1 : 2'h3; + fpnew_pkg::FP8 : apu_lat_o = (C_LAT_FP8<2) ? C_LAT_FP8+1 : 2'h3; + default : ; + endcase + end + + // Set FPnew OP and OPMOD as the APU op + if (SHARED_FP!=1) apu_op_o = {fpu_vec_op, fpu_op_mod, fpu_op}; + end + // FPU!=1 + else begin + illegal_insn_o = 1'b1; + end + end + + OPCODE_STORE_FP: begin + if (FPU==1) begin + data_req = 1'b1; + data_we_o = 1'b1; + rega_used_o = 1'b1; + regb_used_o = 1'b1; + alu_operator_o = ALU_ADD; + reg_fp_b_o = 1'b1; + instr_multicycle_o = 1'b1; + + // offset from immediate + imm_b_mux_sel_o = IMMB_S; + alu_op_b_mux_sel_o = OP_B_IMM; + + // pass write data through ALU operand c + alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD; + + // Decode data type + unique case (instr_rdata_i[14:12]) + // fsb - FP8 store + 3'b000 : if (C_XF8) data_type_o = 2'b10; + else illegal_insn_o = 1'b1; + // fsh - FP16 store + 3'b001 : if (C_XF16 | C_XF16ALT) data_type_o = 2'b01; + else illegal_insn_o = 1'b1; + // fsw - FP32 store + 3'b010 : if (C_RVF) data_type_o = 2'b00; + else illegal_insn_o = 1'b1; + // fsd - FP64 store + 3'b011 : if (C_RVD) data_type_o = 2'b00; // 64bit stores unsupported! + else illegal_insn_o = 1'b1; + default: illegal_insn_o = 1'b1; + endcase + + // sanitize memory bus signals for illegal instr (not sure if needed??) + if (illegal_insn_o) begin + data_req = 1'b0; + data_we_o = 1'b0; + end + end + // FPU!=1 + else + illegal_insn_o = 1'b1; + end + + OPCODE_LOAD_FP: begin + if (FPU==1) begin + data_req = 1'b1; + regfile_mem_we = 1'b1; + reg_fp_d_o = 1'b1; + rega_used_o = 1'b1; + alu_operator_o = ALU_ADD; + instr_multicycle_o = 1'b1; + + // offset from immediate + imm_b_mux_sel_o = IMMB_I; + alu_op_b_mux_sel_o = OP_B_IMM; + + // NaN boxing + data_sign_extension_o = 2'b10; + + // Decode data type + unique case (instr_rdata_i[14:12]) + // flb - FP8 load + 3'b000 : if (C_XF8) data_type_o = 2'b10; + else illegal_insn_o = 1'b1; + // flh - FP16 load + 3'b001 : if (C_XF16 | C_XF16ALT) data_type_o = 2'b01; + else illegal_insn_o = 1'b1; + // flw - FP32 load + 3'b010 : if (C_RVF) data_type_o = 2'b00; + else illegal_insn_o = 1'b1; + // fld - FP64 load + 3'b011 : if (C_RVD) data_type_o = 2'b00; // 64bit loads unsupported! + else illegal_insn_o = 1'b1; + default: illegal_insn_o = 1'b1; + endcase + end + // FPU!=1 + else + illegal_insn_o = 1'b1; + end + + OPCODE_PULP_OP: begin // PULP specific ALU instructions with three source operands + regfile_alu_we = 1'b1; + rega_used_o = 1'b1; + regb_used_o = 1'b1; + + case (instr_rdata_i[13:12]) + 2'b00: begin // multiply with subword selection + alu_en_o = 1'b0; + + mult_sel_subword_o = instr_rdata_i[30]; + mult_signed_mode_o = {2{instr_rdata_i[31]}}; + + mult_imm_mux_o = MIMM_S3; + regc_mux_o = REGC_ZERO; + mult_int_en = 1'b1; + + if (instr_rdata_i[14]) + mult_operator_o = MUL_IR; + else + mult_operator_o = MUL_I; + + `USE_APU_INT_MULT + end + + 2'b01: begin // MAC with subword selection + alu_en_o = 1'b0; + + mult_sel_subword_o = instr_rdata_i[30]; + mult_signed_mode_o = {2{instr_rdata_i[31]}}; + + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + mult_imm_mux_o = MIMM_S3; + mult_int_en = 1'b1; + + if (instr_rdata_i[14]) + mult_operator_o = MUL_IR; + else + mult_operator_o = MUL_I; + + `USE_APU_INT_MULT + end + + 2'b10: begin // add with normalization and rounding + // decide between using unsigned and rounding, and combinations + // thereof + case ({instr_rdata_i[31],instr_rdata_i[14]}) + 2'b00: alu_operator_o = ALU_ADD; + 2'b01: alu_operator_o = ALU_ADDR; + 2'b10: alu_operator_o = ALU_ADDU; + 2'b11: alu_operator_o = ALU_ADDUR; + endcase + + bmask_a_mux_o = BMASK_A_ZERO; + bmask_b_mux_o = BMASK_B_S3; + + if (instr_rdata_i[30]) begin + //register variant + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + alu_bmask_b_mux_sel_o = BMASK_B_REG; + alu_op_a_mux_sel_o = OP_A_REGC_OR_FWD; + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; + end + + end + + 2'b11: begin // sub with normalization and rounding + // decide between using unsigned and rounding, and combinations + // thereof + case ({instr_rdata_i[31],instr_rdata_i[14]}) + 2'b00: alu_operator_o = ALU_SUB; + 2'b01: alu_operator_o = ALU_SUBR; + 2'b10: alu_operator_o = ALU_SUBU; + 2'b11: alu_operator_o = ALU_SUBUR; + endcase + + bmask_a_mux_o = BMASK_A_ZERO; + bmask_b_mux_o = BMASK_B_S3; + + if (instr_rdata_i[30]) begin + //register variant + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + alu_bmask_b_mux_sel_o = BMASK_B_REG; + alu_op_a_mux_sel_o = OP_A_REGC_OR_FWD; + alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD; + end + + end + endcase + end + + OPCODE_VECOP: begin + regfile_alu_we = 1'b1; + rega_used_o = 1'b1; + imm_b_mux_sel_o = IMMB_VS; + + // vector size + if (instr_rdata_i[12]) begin + alu_vec_mode_o = VEC_MODE8; + mult_operator_o = MUL_DOT8; + end else begin + alu_vec_mode_o = VEC_MODE16; + mult_operator_o = MUL_DOT16; + end + + // distinguish normal vector, sc and sci modes + if (instr_rdata_i[14]) begin + scalar_replication_o = 1'b1; + + if (instr_rdata_i[13]) begin + // immediate scalar replication, .sci + alu_op_b_mux_sel_o = OP_B_IMM; + end else begin + // register scalar replication, .sc + regb_used_o = 1'b1; + end + end else begin + // normal register use + regb_used_o = 1'b1; + end + + // now decode the instruction + unique case (instr_rdata_i[31:26]) + 6'b00000_0: begin alu_operator_o = ALU_ADD; imm_b_mux_sel_o = IMMB_VS; end // pv.add + 6'b00001_0: begin alu_operator_o = ALU_SUB; imm_b_mux_sel_o = IMMB_VS; end // pv.sub + 6'b00010_0: begin alu_operator_o = ALU_ADD; imm_b_mux_sel_o = IMMB_VS; bmask_b_mux_o = BMASK_B_ONE; end // pv.avg + 6'b00011_0: begin alu_operator_o = ALU_ADDU; imm_b_mux_sel_o = IMMB_VU; bmask_b_mux_o = BMASK_B_ONE; end // pv.avgu + 6'b00100_0: begin alu_operator_o = ALU_MIN; imm_b_mux_sel_o = IMMB_VS; end // pv.min + 6'b00101_0: begin alu_operator_o = ALU_MINU; imm_b_mux_sel_o = IMMB_VU; end // pv.minu + 6'b00110_0: begin alu_operator_o = ALU_MAX; imm_b_mux_sel_o = IMMB_VS; end // pv.max + 6'b00111_0: begin alu_operator_o = ALU_MAXU; imm_b_mux_sel_o = IMMB_VU; end // pv.maxu + 6'b01000_0: begin alu_operator_o = ALU_SRL; imm_b_mux_sel_o = IMMB_VS; end // pv.srl + 6'b01001_0: begin alu_operator_o = ALU_SRA; imm_b_mux_sel_o = IMMB_VS; end // pv.sra + 6'b01010_0: begin alu_operator_o = ALU_SLL; imm_b_mux_sel_o = IMMB_VS; end // pv.sll + 6'b01011_0: begin alu_operator_o = ALU_OR; imm_b_mux_sel_o = IMMB_VS; end // pv.or + 6'b01100_0: begin alu_operator_o = ALU_XOR; imm_b_mux_sel_o = IMMB_VS; end // pv.xor + 6'b01101_0: begin alu_operator_o = ALU_AND; imm_b_mux_sel_o = IMMB_VS; end // pv.and + 6'b01110_0: begin alu_operator_o = ALU_ABS; imm_b_mux_sel_o = IMMB_VS; end // pv.abs + + // shuffle/pack + 6'b11101_0, // pv.shuffleI1 + 6'b11110_0, // pv.shuffleI2 + 6'b11111_0, // pv.shuffleI3 + 6'b11000_0: begin // pv.shuffle, pv.shuffleI0 + alu_operator_o = ALU_SHUF; + imm_b_mux_sel_o = IMMB_SHUF; + regb_used_o = 1'b1; + scalar_replication_o = 1'b0; + end + 6'b11001_0: begin // pv.shuffle2 + alu_operator_o = ALU_SHUF2; + regb_used_o = 1'b1; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + scalar_replication_o = 1'b0; + end + 6'b11010_0: begin // pv.pack + alu_operator_o = instr_rdata_i[25] ? ALU_PCKHI : ALU_PCKLO; + regb_used_o = 1'b1; + end + 6'b11011_0: begin // pv.packhi + alu_operator_o = ALU_PCKHI; + regb_used_o = 1'b1; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + end + 6'b11100_0: begin // pv.packlo + alu_operator_o = ALU_PCKLO; + regb_used_o = 1'b1; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + end + + 6'b01111_0: begin // pv.extract + alu_operator_o = ALU_EXTS; + end + + 6'b10010_0: begin // pv.extractu + alu_operator_o = ALU_EXT; + end + + 6'b10110_0: begin // pv.insert + alu_operator_o = ALU_INS; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + alu_op_b_mux_sel_o = OP_B_REGC_OR_FWD; + end + + 6'b10000_0: begin // pv.dotup + alu_en_o = 1'b0; + mult_dot_en = 1'b1; + mult_dot_signed_o = 2'b00; + imm_b_mux_sel_o = IMMB_VU; + `USE_APU_DSP_MULT + end + 6'b10001_0: begin // pv.dotusp + alu_en_o = 1'b0; + mult_dot_en = 1'b1; + mult_dot_signed_o = 2'b01; + `USE_APU_DSP_MULT + end + 6'b10011_0: begin // pv.dotsp + alu_en_o = 1'b0; + mult_dot_en = 1'b1; + mult_dot_signed_o = 2'b11; + `USE_APU_DSP_MULT + end + 6'b10100_0: begin // pv.sdotup + alu_en_o = 1'b0; + mult_dot_en = 1'b1; + mult_dot_signed_o = 2'b00; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + imm_b_mux_sel_o = IMMB_VU; + `USE_APU_DSP_MULT + end + 6'b10101_0: begin // pv.sdotusp + alu_en_o = 1'b0; + mult_dot_en = 1'b1; + mult_dot_signed_o = 2'b01; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + `USE_APU_DSP_MULT + end + 6'b10111_0: begin // pv.sdotsp + alu_en_o = 1'b0; + mult_dot_en = 1'b1; + mult_dot_signed_o = 2'b11; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + `USE_APU_DSP_MULT + end + + /* COMPLEX INSTRUCTIONS */ + + 6'b01010_1: begin // pc.clpxmul.h.{r,i}.{/,div2,div4,div8} + alu_en_o = 1'b0; + mult_dot_en = 1'b1; + mult_dot_signed_o = 2'b11; + is_clpx_o = 1'b1; + regc_used_o = 1'b1; + regc_mux_o = REGC_RD; + scalar_replication_o = 1'b0; + alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD; + regb_used_o = 1'b1; + `USE_APU_DSP_MULT + end + + 6'b01101_1: begin // pv.subrotmj.h.{/,div2,div4,div8} + alu_operator_o = ALU_SUB; + is_clpx_o = 1'b1; + scalar_replication_o = 1'b0; + alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD; + regb_used_o = 1'b1; + is_subrot_o = 1'b1; + end + + 6'b01011_1: begin // pv.cplxconj.h + alu_operator_o = ALU_ABS; + is_clpx_o = 1'b1; + scalar_replication_o = 1'b0; + regb_used_o = 1'b0; + end + + 6'b01110_1: begin // pv.add.h.{div2,div4,div8} + alu_operator_o = ALU_ADD; + is_clpx_o = 1'b1; + scalar_replication_o = 1'b0; + alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD; + regb_used_o = 1'b1; + end + + 6'b01100_1: begin // pv.sub.h.{div2,div4,div8} + alu_operator_o = ALU_SUB; + is_clpx_o = 1'b1; + scalar_replication_o = 1'b0; + alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD; + regb_used_o = 1'b1; + end + + // comparisons, always have bit 26 set + 6'b00000_1: begin alu_operator_o = ALU_EQ; imm_b_mux_sel_o = IMMB_VS; end // pv.cmpeq + 6'b00001_1: begin alu_operator_o = ALU_NE; imm_b_mux_sel_o = IMMB_VS; end // pv.cmpne + 6'b00010_1: begin alu_operator_o = ALU_GTS; imm_b_mux_sel_o = IMMB_VS; end // pv.cmpgt + 6'b00011_1: begin alu_operator_o = ALU_GES; imm_b_mux_sel_o = IMMB_VS; end // pv.cmpge + 6'b00100_1: begin alu_operator_o = ALU_LTS; imm_b_mux_sel_o = IMMB_VS; end // pv.cmplt + 6'b00101_1: begin alu_operator_o = ALU_LES; imm_b_mux_sel_o = IMMB_VS; end // pv.cmple + 6'b00110_1: begin alu_operator_o = ALU_GTU; imm_b_mux_sel_o = IMMB_VU; end // pv.cmpgtu + 6'b00111_1: begin alu_operator_o = ALU_GEU; imm_b_mux_sel_o = IMMB_VU; end // pv.cmpgeu + 6'b01000_1: begin alu_operator_o = ALU_LTU; imm_b_mux_sel_o = IMMB_VU; end // pv.cmpltu + 6'b01001_1: begin alu_operator_o = ALU_LEU; imm_b_mux_sel_o = IMMB_VU; end // pv.cmpleu + + default: illegal_insn_o = 1'b1; + endcase + end + + + //////////////////////////////////////////////// + // ____ ____ _____ ____ ___ _ _ // + // / ___|| _ \| ____/ ___|_ _| / \ | | // + // \___ \| |_) | _|| | | | / _ \ | | // + // ___) | __/| |__| |___ | | / ___ \| |___ // + // |____/|_| |_____\____|___/_/ \_\_____| // + // // + //////////////////////////////////////////////// + + OPCODE_FENCE: begin + unique case (instr_rdata_i[14:12]) + 3'b000: begin // FENCE (FENCE.I instead, a bit more conservative) + // flush pipeline + fencei_insn_o = 1'b1; + end + + 3'b001: begin // FENCE.I + // flush prefetch buffer, flush pipeline + fencei_insn_o = 1'b1; + end + + default: begin + illegal_insn_o = 1'b1; + end + endcase + end + + OPCODE_SYSTEM: begin + if (instr_rdata_i[14:12] == 3'b000) + begin + // non CSR related SYSTEM instructions + if ( {instr_rdata_i[19:15], instr_rdata_i[11:7]} == '0) + begin + unique case (instr_rdata_i[31:20]) + 12'h000: // ECALL + begin + // environment (system) call + ecall_insn_o = 1'b1; + end + + 12'h001: // ebreak + begin + // debugger trap + ebrk_insn_o = 1'b1; + end + + 12'h302: // mret + begin + illegal_insn_o = (PULP_SECURE) ? current_priv_lvl_i != PRIV_LVL_M : 1'b0; + mret_insn_o = ~illegal_insn_o; + mret_dec_o = 1'b1; + end + + 12'h002: // uret + begin + uret_insn_o = (PULP_SECURE) ? 1'b1 : 1'b0; + uret_dec_o = 1'b1; + end + + 12'h7b2: // dret + begin + illegal_insn_o = !debug_mode_i; + dret_insn_o = debug_mode_i; + dret_dec_o = 1'b1; + end + + 12'h105: // wfi + begin + // flush pipeline + pipe_flush_o = 1'b1; + end + + default: + begin + illegal_insn_o = 1'b1; + end + endcase + end else illegal_insn_o = 1'b1; + end + else + begin + // instruction to read/modify CSR + csr_access_o = 1'b1; + regfile_alu_we = 1'b1; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMMA_Z; + imm_b_mux_sel_o = IMMB_I; // CSR address is encoded in I imm + instr_multicycle_o = 1'b1; + + if (instr_rdata_i[14] == 1'b1) begin + // rs1 field is used as immediate + alu_op_a_mux_sel_o = OP_A_IMM; + end else begin + rega_used_o = 1'b1; + alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD; + end + + // instr_rdata_i[19:14] = rs or immediate value + // if set or clear with rs==x0 or imm==0, + // then do not perform a write action + unique case (instr_rdata_i[13:12]) + 2'b01: csr_op = CSR_OP_WRITE; + 2'b10: csr_op = instr_rdata_i[19:15] == 5'b0 ? CSR_OP_READ : CSR_OP_SET; + 2'b11: csr_op = instr_rdata_i[19:15] == 5'b0 ? CSR_OP_READ : CSR_OP_CLEAR; + default: csr_illegal = 1'b1; + endcase + + if (instr_rdata_i[29:28] > current_priv_lvl_i) begin + // No access to higher privilege CSR + csr_illegal = 1'b1; + end + + // Determine if CSR access is illegal + casex(instr_rdata_i[31:20]) + // Floating point + CSR_FFLAGS, + CSR_FRM, + CSR_FCSR, + FPREC : + if(!FPU) csr_illegal = 1'b1; + + // Writes to read only CSRs results in illegal instruction + CSR_MVENDORID, + CSR_MARCHID, + CSR_MIMPID, + CSR_MHARTID : + if(csr_op != CSR_OP_READ) csr_illegal = 1'b1; + + // These are valid CSR registers + CSR_MSTATUS, + CSR_MISA, + CSR_MIE, + CSR_MIE1, + CSR_MTVEC, + CSR_MSCRATCH, + CSR_MEPC, + CSR_MCAUSE, + CSR_MTVAL, + CSR_MIP, + CSR_MIP1, + CSR_MVENDORID, + CSR_MARCHID, + CSR_MIMPID, + CSR_MHARTID, + CSR_MCOUNTEREN, + + UHARTID, + PRIVLV, + + // Hardware Performance Monitor + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31, + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H, + CSR_MCOUNTINHIBIT, + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, + CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11, + CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, + CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, + CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, + CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, + CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: + ; // do nothing, not illegal + + // Debug register access + CSR_DCSR, + CSR_DPC, + CSR_DSCRATCH0, + CSR_DSCRATCH1 : + if(!debug_mode_i) csr_illegal = 1'b1; + + // Debug Trigger register access + CSR_TSELECT , + CSR_TDATA1 , + CSR_TDATA2 , + CSR_TDATA3 , + CSR_MCONTEXT , + CSR_SCONTEXT : + if(!debug_mode_i || DEBUG_TRIGGER_EN != 1) + csr_illegal = 1'b1; + + // Hardware Loop register access + HWLoop0_START, + HWLoop0_END, + HWLoop0_COUNTER, + HWLoop1_START, + HWLoop1_END, + HWLoop1_COUNTER : + if(!PULP_HWLP) csr_illegal = 1'b1; + + // PMP register access + CSR_PMPCFG_RANGE_X, + CSR_PMPADDR_RANGE_X : + if(!USE_PMP) csr_illegal = 1'b1; + + // User register access + CSR_USTATUS, + CSR_UTVEC, + CSR_UEPC, + CSR_UCAUSE : + if(!PULP_SECURE) csr_illegal = 1'b1; + + default : csr_illegal = 1'b1; + + endcase // casex (instr_rdata_i[31:20]) + + // set csr_status for specific CSR register access: + // Causes controller to enter FLUSH + if(~csr_illegal) + if (instr_rdata_i[31:20] == CSR_MSTATUS || + instr_rdata_i[31:20] == CSR_USTATUS || + instr_rdata_i[31:20] == CSR_UEPC || + // Debug registers + instr_rdata_i[31:20] == CSR_DCSR || + instr_rdata_i[31:20] == CSR_DPC || + instr_rdata_i[31:20] == CSR_DSCRATCH0 || + instr_rdata_i[31:20] == CSR_DSCRATCH1 ) + //access to xstatus + csr_status_o = 1'b1; + + illegal_insn_o = csr_illegal; + + end + + end + + + /////////////////////////////////////////////// + // _ ___ ___ ___ ___ ____ // + // | | | \ \ / / | / _ \ / _ \| _ \ // + // | |_| |\ \ /\ / /| | | | | | | | | |_) | // + // | _ | \ V V / | |__| |_| | |_| | __/ // + // |_| |_| \_/\_/ |_____\___/ \___/|_| // + // // + /////////////////////////////////////////////// + + OPCODE_HWLOOP: begin + if(PULP_HWLP) begin : HWLOOP_FEATURE_ENABLED + hwloop_target_mux_sel_o = 1'b0; + + unique case (instr_rdata_i[14:12]) + 3'b000: begin + // lp.starti: set start address to PC + I-type immediate + hwloop_we[0] = 1'b1; + hwloop_start_mux_sel_o = 1'b0; + end + + 3'b001: begin + // lp.endi: set end address to PC + I-type immediate + hwloop_we[1] = 1'b1; + end + + 3'b010: begin + // lp.count: initialize counter from rs1 + hwloop_we[2] = 1'b1; + hwloop_cnt_mux_sel_o = 1'b1; + rega_used_o = 1'b1; + end + + 3'b011: begin + // lp.counti: initialize counter from I-type immediate + hwloop_we[2] = 1'b1; + hwloop_cnt_mux_sel_o = 1'b0; + end + + 3'b100: begin + // lp.setup: initialize counter from rs1, set start address to + // next instruction and end address to PC + I-type immediate + hwloop_we = 3'b111; + hwloop_start_mux_sel_o = 1'b1; + hwloop_cnt_mux_sel_o = 1'b1; + rega_used_o = 1'b1; + end + + 3'b101: begin + // lp.setupi: initialize counter from immediate, set start address to + // next instruction and end address to PC + I-type immediate + hwloop_we = 3'b111; + hwloop_target_mux_sel_o = 1'b1; + hwloop_start_mux_sel_o = 1'b1; + hwloop_cnt_mux_sel_o = 1'b0; + end + + default: begin + illegal_insn_o = 1'b1; + end + endcase // case (instr_rdata_i[14:12]) + + end else begin // block: HWLOOP_FEATURE_ENABLED + illegal_insn_o = 1'b1; + end + end // case: OPCODE_HWLOOP + + default: begin + illegal_insn_o = 1'b1; + end + endcase + + // make sure invalid compressed instruction causes an exception + if (illegal_c_insn_i) begin + illegal_insn_o = 1'b1; + end + + // misaligned access was detected by the LSU + // TODO: this section should eventually be moved out of the decoder + if (data_misaligned_i == 1'b1) + begin + // only part of the pipeline is unstalled, make sure that the + // correct operands are sent to the AGU + alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMMB_PCINCR; + + // if prepost increments are used, we do not write back the + // second address since the first calculated address was + // the correct one + regfile_alu_we = 1'b0; + + // if post increments are used, we must make sure that for + // the second memory access we do use the adder + prepost_useincr_o = 1'b1; + // we do not want to replicate operand_b + scalar_replication_o = 1'b0; + end else if (mult_multicycle_i) begin + alu_op_c_mux_sel_o = OP_C_REGC_OR_FWD; + end + end + + // deassert we signals (in case of stalls) + assign apu_en_o = (deassert_we_i) ? 1'b0 : apu_en; + assign mult_int_en_o = (deassert_we_i) ? 1'b0 : mult_int_en; + assign mult_dot_en_o = (deassert_we_i) ? 1'b0 : mult_dot_en; + assign regfile_mem_we_o = (deassert_we_i) ? 1'b0 : regfile_mem_we; + assign regfile_alu_we_o = (deassert_we_i) ? 1'b0 : regfile_alu_we; + assign data_req_o = (deassert_we_i) ? 1'b0 : data_req; + assign hwloop_we_o = (deassert_we_i) ? 3'b0 : hwloop_we; + assign csr_op_o = (deassert_we_i) ? CSR_OP_READ : csr_op; + assign jump_in_id_o = (deassert_we_i) ? BRANCH_NONE : jump_in_id; + + assign jump_in_dec_o = jump_in_id; + assign regfile_alu_we_dec_o = regfile_alu_we; + +endmodule // controller diff --git a/hw/deps/riscv/riscv_ex_stage.sv b/hw/deps/riscv/riscv_ex_stage.sv new file mode 100644 index 0000000..8afd4c8 --- /dev/null +++ b/hw/deps/riscv/riscv_ex_stage.sv @@ -0,0 +1,564 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Renzo Andri - andrire@student.ethz.ch // +// // +// Additional contributions by: // +// Igor Loi - igor.loi@unibo.it // +// Sven Stucki - svstucki@student.ethz.ch // +// Andreas Traber - atraber@iis.ee.ethz.ch // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: Execute stage // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Execution stage: Hosts ALU and MAC unit // +// ALU: computes additions/subtractions/comparisons // +// MULT: computes normal multiplications // +// APU_DISP: offloads instructions to the shared unit. // +// SHARED_DSP_MULT, SHARED_INT_DIV allow // +// to offload also dot-product, int-div, int-mult to the // +// shared unit. // +// // +//////////////////////////////////////////////////////////////////////////////// + +`include "apu_macros.sv" + +import apu_core_package::*; +import riscv_defines::*; + +module riscv_ex_stage +#( + parameter FPU = 0, + parameter FP_DIVSQRT = 0, + parameter SHARED_FP = 0, + parameter SHARED_DSP_MULT = 0, + parameter SHARED_INT_DIV = 0, + parameter APU_NARGS_CPU = 3, + parameter APU_WOP_CPU = 6, + parameter APU_NDSFLAGS_CPU = 15, + parameter APU_NUSFLAGS_CPU = 5 +) +( + input logic clk, + input logic rst_n, + + // ALU signals from ID stage + input logic [ALU_OP_WIDTH-1:0] alu_operator_i, + input logic [31:0] alu_operand_a_i, + input logic [31:0] alu_operand_b_i, + input logic [31:0] alu_operand_c_i, + input logic alu_en_i, + input logic [ 4:0] bmask_a_i, + input logic [ 4:0] bmask_b_i, + input logic [ 1:0] imm_vec_ext_i, + input logic [ 1:0] alu_vec_mode_i, + input logic alu_is_clpx_i, + input logic alu_is_subrot_i, + input logic [ 1:0] alu_clpx_shift_i, + + // Multiplier signals + input logic [ 2:0] mult_operator_i, + input logic [31:0] mult_operand_a_i, + input logic [31:0] mult_operand_b_i, + input logic [31:0] mult_operand_c_i, + input logic mult_en_i, + input logic mult_sel_subword_i, + input logic [ 1:0] mult_signed_mode_i, + input logic [ 4:0] mult_imm_i, + + input logic [31:0] mult_dot_op_a_i, + input logic [31:0] mult_dot_op_b_i, + input logic [31:0] mult_dot_op_c_i, + input logic [ 1:0] mult_dot_signed_i, + input logic mult_is_clpx_i, + input logic [ 1:0] mult_clpx_shift_i, + input logic mult_clpx_img_i, + + output logic mult_multicycle_o, + + // FPU signals + input logic [C_PC-1:0] fpu_prec_i, + output logic [C_FFLAG-1:0] fpu_fflags_o, + output logic fpu_fflags_we_o, + + // APU signals + input logic apu_en_i, + input logic [APU_WOP_CPU-1:0] apu_op_i, + input logic [1:0] apu_lat_i, + input logic [APU_NARGS_CPU-1:0][31:0] apu_operands_i, + input logic [5:0] apu_waddr_i, + input logic [APU_NDSFLAGS_CPU-1:0] apu_flags_i, + + input logic [2:0][5:0] apu_read_regs_i, + input logic [2:0] apu_read_regs_valid_i, + output logic apu_read_dep_o, + input logic [1:0][5:0] apu_write_regs_i, + input logic [1:0] apu_write_regs_valid_i, + output logic apu_write_dep_o, + + output logic apu_perf_type_o, + output logic apu_perf_cont_o, + output logic apu_perf_wb_o, + + output logic apu_busy_o, + output logic apu_ready_wb_o, + + // apu-interconnect + // handshake signals + output logic apu_master_req_o, + output logic apu_master_ready_o, + input logic apu_master_gnt_i, + // request channel + output logic [APU_NARGS_CPU-1:0][31:0] apu_master_operands_o, + output logic [APU_WOP_CPU-1:0] apu_master_op_o, + // response channel + input logic apu_master_valid_i, + input logic [31:0] apu_master_result_i, + + input logic lsu_en_i, + input logic [31:0] lsu_rdata_i, + + // input from ID stage + input logic branch_in_ex_i, + input logic [5:0] regfile_alu_waddr_i, + input logic regfile_alu_we_i, + + // directly passed through to WB stage, not used in EX + input logic regfile_we_i, + input logic [5:0] regfile_waddr_i, + + // CSR access + input logic csr_access_i, + input logic [31:0] csr_rdata_i, + + // Output of EX stage pipeline + output logic [5:0] regfile_waddr_wb_o, + output logic regfile_we_wb_o, + output logic [31:0] regfile_wdata_wb_o, + + // Forwarding ports : to ID stage + output logic [5:0] regfile_alu_waddr_fw_o, + output logic regfile_alu_we_fw_o, + output logic [31:0] regfile_alu_wdata_fw_o, // forward to RF and ID/EX pipe, ALU & MUL + + // To IF: Jump and branch target and decision + output logic [31:0] jump_target_o, + output logic branch_decision_o, + + // Stall Control + input logic is_decoding_i, // Used to mask data Dependency inside the APU dispatcher in case of an istruction non valid + input logic lsu_ready_ex_i, // EX part of LSU is done + input logic lsu_err_i, + + output logic ex_ready_o, // EX stage ready for new data + output logic ex_valid_o, // EX stage gets new data + input logic wb_ready_i // WB stage ready for new data +); + + logic [31:0] alu_result; + logic [31:0] mult_result; + logic alu_cmp_result; + + logic regfile_we_lsu; + logic [5:0] regfile_waddr_lsu; + + logic wb_contention; + logic wb_contention_lsu; + + logic alu_ready; + logic mult_ready; + logic fpu_ready; + + // APU signals + logic apu_valid; + logic [5:0] apu_waddr; + logic [31:0] apu_result; + logic apu_stall; + logic apu_active; + logic apu_singlecycle; + logic apu_multicycle; + logic apu_req; + logic apu_ready; + logic apu_gnt; + + // ALU write port mux + always_comb + begin + regfile_alu_wdata_fw_o = '0; + regfile_alu_waddr_fw_o = '0; + regfile_alu_we_fw_o = '0; + wb_contention = 1'b0; + + // APU single cycle operations, and multicycle operations (>2cycles) are written back on ALU port + if (apu_valid & (apu_singlecycle | apu_multicycle)) begin + regfile_alu_we_fw_o = 1'b1; + regfile_alu_waddr_fw_o = apu_waddr; + regfile_alu_wdata_fw_o = apu_result; + + if(regfile_alu_we_i & ~apu_en_i) begin + wb_contention = 1'b1; + end + end else begin + regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i; // private fpu incomplete? + regfile_alu_waddr_fw_o = regfile_alu_waddr_i; + if (alu_en_i) + regfile_alu_wdata_fw_o = alu_result; + if (mult_en_i) + regfile_alu_wdata_fw_o = mult_result; + if (csr_access_i) + regfile_alu_wdata_fw_o = csr_rdata_i; + end + end + + // LSU write port mux + always_comb + begin + regfile_we_wb_o = 1'b0; + regfile_waddr_wb_o = regfile_waddr_lsu; + regfile_wdata_wb_o = lsu_rdata_i; + wb_contention_lsu = 1'b0; + + if (regfile_we_lsu) begin + regfile_we_wb_o = 1'b1; + if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin + wb_contention_lsu = 1'b1; +// $error("%t, wb-contention", $time); + end + // APU two-cycle operations are written back on LSU port + end else if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin + regfile_we_wb_o = 1'b1; + regfile_waddr_wb_o = apu_waddr; + regfile_wdata_wb_o = apu_result; + end + end + + // branch handling + assign branch_decision_o = alu_cmp_result; + assign jump_target_o = alu_operand_c_i; + + + //////////////////////////// + // _ _ _ _ // + // / \ | | | | | | // + // / _ \ | | | | | | // + // / ___ \| |__| |_| | // + // /_/ \_\_____\___/ // + // // + //////////////////////////// + + riscv_alu + #( + .SHARED_INT_DIV( SHARED_INT_DIV ), + .FPU ( FPU ) + ) + alu_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + .enable_i ( alu_en_i ), + .operator_i ( alu_operator_i ), + .operand_a_i ( alu_operand_a_i ), + .operand_b_i ( alu_operand_b_i ), + .operand_c_i ( alu_operand_c_i ), + + .vector_mode_i ( alu_vec_mode_i ), + .bmask_a_i ( bmask_a_i ), + .bmask_b_i ( bmask_b_i ), + .imm_vec_ext_i ( imm_vec_ext_i ), + + .is_clpx_i ( alu_is_clpx_i ), + .clpx_shift_i ( alu_clpx_shift_i), + .is_subrot_i ( alu_is_subrot_i ), + + .result_o ( alu_result ), + .comparison_result_o ( alu_cmp_result ), + + .ready_o ( alu_ready ), + .ex_ready_i ( ex_ready_o ) + ); + + + //////////////////////////////////////////////////////////////// + // __ __ _ _ _ _____ ___ ____ _ ___ _____ ____ // + // | \/ | | | | | |_ _|_ _| _ \| | |_ _| ____| _ \ // + // | |\/| | | | | | | | | || |_) | | | || _| | |_) | // + // | | | | |_| | |___| | | || __/| |___ | || |___| _ < // + // |_| |_|\___/|_____|_| |___|_| |_____|___|_____|_| \_\ // + // // + //////////////////////////////////////////////////////////////// + + riscv_mult + #( + .SHARED_DSP_MULT(SHARED_DSP_MULT) + ) + mult_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .enable_i ( mult_en_i ), + .operator_i ( mult_operator_i ), + + .short_subword_i ( mult_sel_subword_i ), + .short_signed_i ( mult_signed_mode_i ), + + .op_a_i ( mult_operand_a_i ), + .op_b_i ( mult_operand_b_i ), + .op_c_i ( mult_operand_c_i ), + .imm_i ( mult_imm_i ), + + .dot_op_a_i ( mult_dot_op_a_i ), + .dot_op_b_i ( mult_dot_op_b_i ), + .dot_op_c_i ( mult_dot_op_c_i ), + .dot_signed_i ( mult_dot_signed_i ), + .is_clpx_i ( mult_is_clpx_i ), + .clpx_shift_i ( mult_clpx_shift_i ), + .clpx_img_i ( mult_clpx_img_i ), + + .result_o ( mult_result ), + + .multicycle_o ( mult_multicycle_o ), + .ready_o ( mult_ready ), + .ex_ready_i ( ex_ready_o ) + ); + + generate + if (FPU == 1) begin + //////////////////////////////////////////////////// + // _ ____ _ _ ____ ___ ____ ____ // + // / \ | _ \| | | | | _ \_ _/ ___|| _ \ // + // / _ \ | |_) | | | | | | | | |\___ \| |_) | // + // / ___ \| __/| |_| | | |_| | | ___) | __/ // + // /_/ \_\_| \___/ |____/___|____/|_| // + // // + //////////////////////////////////////////////////// + + riscv_apu_disp apu_disp_i + ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + + .enable_i ( apu_en_i ), + .apu_lat_i ( apu_lat_i ), + .apu_waddr_i ( apu_waddr_i ), + + .apu_waddr_o ( apu_waddr ), + .apu_multicycle_o ( apu_multicycle ), + .apu_singlecycle_o ( apu_singlecycle ), + + .active_o ( apu_active ), + .stall_o ( apu_stall ), + + .read_regs_i ( apu_read_regs_i ), + .read_regs_valid_i ( apu_read_regs_valid_i ), + .read_dep_o ( apu_read_dep_o ), + .write_regs_i ( apu_write_regs_i ), + .write_regs_valid_i ( apu_write_regs_valid_i ), + .write_dep_o ( apu_write_dep_o ), + + .perf_type_o ( apu_perf_type_o ), + .perf_cont_o ( apu_perf_cont_o ), + + // apu-interconnect + // handshake signals + .apu_master_req_o ( apu_req ), + .apu_master_ready_o ( apu_ready ), + .apu_master_gnt_i ( apu_gnt ), + // response channel + .apu_master_valid_i ( apu_valid ) + ); + + assign apu_perf_wb_o = wb_contention | wb_contention_lsu; + assign apu_ready_wb_o = ~(apu_active | apu_en_i | apu_stall) | apu_valid; + + if ( SHARED_FP ) begin + assign apu_master_req_o = apu_req; + assign apu_master_ready_o = apu_ready; + assign apu_gnt = apu_master_gnt_i; + assign apu_valid = apu_master_valid_i; + assign apu_master_operands_o = apu_operands_i; + assign apu_master_op_o = apu_op_i; + assign apu_result = apu_master_result_i; + assign fpu_fflags_we_o = apu_valid; + assign fpu_ready = 1'b1; + end + else begin + + ////////////////////////////// + // ______ _____ _ _ // + // | ____| __ \| | | | // + // | |__ | |__) | | | | // + // | __| | ___/| | | | // + // | | | | | |__| | // + // |_| |_| \____/ // + ////////////////////////////// + + + logic [C_FPNEW_OPBITS-1:0] fpu_op; + logic fpu_op_mod; + logic fpu_vec_op; + + logic [C_FPNEW_FMTBITS-1:0] fpu_dst_fmt; + logic [C_FPNEW_FMTBITS-1:0] fpu_src_fmt; + logic [C_FPNEW_IFMTBITS-1:0] fpu_int_fmt; + logic [C_RM-1:0] fp_rnd_mode; + + assign {fpu_vec_op, fpu_op_mod, fpu_op} = apu_op_i; + assign {fpu_int_fmt, fpu_src_fmt, fpu_dst_fmt, fp_rnd_mode} = apu_flags_i; + + localparam C_DIV = FP_DIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED; + + logic FPU_ready_int; + + // ----------- + // FPU Config + // ----------- + // Features (enabled formats, vectors etc.) + localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ + Width: C_FLEN, + EnableVectors: C_XFVEC, + EnableNanBox: 1'b0, + FpFmtMask: {C_RVF, C_RVD, C_XF16, C_XF8, C_XF16ALT}, + IntFmtMask: {C_XFVEC && C_XF8, C_XFVEC && (C_XF16 || C_XF16ALT), 1'b1, 1'b0} + }; + + // Implementation (number of registers etc) + localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ + PipeRegs: '{// FP32, FP64, FP16, FP8, FP16alt + '{C_LAT_FP32, C_LAT_FP64, C_LAT_FP16, C_LAT_FP8, C_LAT_FP16ALT}, // ADDMUL + '{default: C_LAT_DIVSQRT}, // DIVSQRT + '{default: C_LAT_NONCOMP}, // NONCOMP + '{default: C_LAT_CONV}}, // CONV + UnitTypes: '{'{default: fpnew_pkg::MERGED}, // ADDMUL + '{default: C_DIV}, // DIVSQRT + '{default: fpnew_pkg::PARALLEL}, // NONCOMP + '{default: fpnew_pkg::MERGED}}, // CONV + PipeConfig: fpnew_pkg::AFTER + }; + + //--------------- + // FPU instance + //--------------- + + fpnew_top #( + .Features ( FPU_FEATURES ), + .Implementation ( FPU_IMPLEMENTATION ), + .TagType ( logic ) + ) i_fpnew_bulk ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .operands_i ( apu_operands_i ), + .rnd_mode_i ( fpnew_pkg::roundmode_e'(fp_rnd_mode) ), + .op_i ( fpnew_pkg::operation_e'(fpu_op) ), + .op_mod_i ( fpu_op_mod ), + .src_fmt_i ( fpnew_pkg::fp_format_e'(fpu_src_fmt) ), + .dst_fmt_i ( fpnew_pkg::fp_format_e'(fpu_dst_fmt) ), + .int_fmt_i ( fpnew_pkg::int_format_e'(fpu_int_fmt) ), + .vectorial_op_i ( fpu_vec_op ), + .tag_i ( 1'b0 ), + .in_valid_i ( apu_req ), + .in_ready_o ( FPU_ready_int ), + .flush_i ( 1'b0 ), + .result_o ( apu_result ), + .status_o ( fpu_fflags_o ), + .tag_o ( /* unused */ ), + .out_valid_o ( apu_valid ), + .out_ready_i ( 1'b1 ), + .busy_o ( /* unused */ ) + ); + + assign fpu_fflags_we_o = apu_valid; + assign apu_master_req_o = '0; + assign apu_master_ready_o = 1'b1; + assign apu_master_operands_o[0] = '0; + assign apu_master_operands_o[1] = '0; + assign apu_master_operands_o[2] = '0; + assign apu_master_op_o = '0; + assign apu_gnt = 1'b1; + + assign fpu_ready = (FPU_ready_int & apu_req) | (~apu_req); + + end + + end + else begin + // default assignements for the case when no FPU/APU is attached. + assign apu_master_req_o = '0; + assign apu_master_ready_o = 1'b1; + assign apu_master_operands_o[0] = '0; + assign apu_master_operands_o[1] = '0; + assign apu_master_operands_o[2] = '0; + assign apu_master_op_o = '0; + assign apu_req = 1'b0; + assign apu_gnt = 1'b0; + assign apu_ready = 1'b0; + assign apu_result = 32'b0; + assign apu_valid = 1'b0; + assign apu_waddr = 6'b0; + assign apu_stall = 1'b0; + assign apu_active = 1'b0; + assign apu_ready_wb_o = 1'b1; + assign apu_perf_wb_o = 1'b0; + assign apu_perf_cont_o = 1'b0; + assign apu_perf_type_o = 1'b0; + assign apu_singlecycle = 1'b0; + assign apu_multicycle = 1'b0; + assign apu_read_dep_o = 1'b0; + assign apu_write_dep_o = 1'b0; + assign fpu_fflags_we_o = 1'b0; + assign fpu_fflags_o = '0; + // we need this because we want ex_ready_o to go high otherwise the + // pipeline can't progress + assign fpu_ready = 1'b1; + + end + endgenerate + + assign apu_busy_o = apu_active; + + /////////////////////////////////////// + // EX/WB Pipeline Register // + /////////////////////////////////////// + always_ff @(posedge clk, negedge rst_n) + begin : EX_WB_Pipeline_Register + if (~rst_n) + begin + regfile_waddr_lsu <= '0; + regfile_we_lsu <= 1'b0; + end + else + begin + if (ex_valid_o) // wb_ready_i is implied + begin + regfile_we_lsu <= regfile_we_i & ~lsu_err_i; + if (regfile_we_i & ~lsu_err_i ) begin + regfile_waddr_lsu <= regfile_waddr_i; + end + end else if (wb_ready_i) begin + // we are ready for a new instruction, but there is none available, + // so we just flush the current one out of the pipe + regfile_we_lsu <= 1'b0; + end + end + end + + // As valid always goes to the right and ready to the left, and we are able + // to finish branches without going to the WB stage, ex_valid does not + // depend on ex_ready. + assign ex_ready_o = (~apu_stall & alu_ready & mult_ready & lsu_ready_ex_i + & wb_ready_i & ~wb_contention & fpu_ready) | (branch_in_ex_i); + assign ex_valid_o = (apu_valid | alu_en_i | mult_en_i | csr_access_i | lsu_en_i) + & (alu_ready & mult_ready & lsu_ready_ex_i & wb_ready_i); + +endmodule diff --git a/hw/deps/riscv/riscv_ff_one.sv b/hw/deps/riscv/riscv_ff_one.sv new file mode 100644 index 0000000..8524e76 --- /dev/null +++ b/hw/deps/riscv/riscv_ff_one.sv @@ -0,0 +1,98 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Andreas Traber - atraber@student.ethz.ch // +// // +// Additional contributions by: // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: riscv_ff_one // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Find First One // +// // +//////////////////////////////////////////////////////////////////////////////// + +module riscv_ff_one +#( + parameter LEN = 32 +) +( + input logic [LEN-1:0] in_i, + + output logic [$clog2(LEN)-1:0] first_one_o, + output logic no_ones_o +); + + localparam NUM_LEVELS = $clog2(LEN); + + logic [LEN-1:0] [NUM_LEVELS-1:0] index_lut; + logic [2**NUM_LEVELS-1:0] sel_nodes; + logic [2**NUM_LEVELS-1:0] [NUM_LEVELS-1:0] index_nodes; + + + ////////////////////////////////////////////////////////////////////////////// + // generate tree structure + ////////////////////////////////////////////////////////////////////////////// + + generate + genvar j; + for (j = 0; j < LEN; j++) begin + assign index_lut[j] = $unsigned(j); + end + endgenerate + + generate + genvar k; + genvar l; + genvar level; + for (level = 0; level < NUM_LEVELS; level++) begin + //------------------------------------------------------------ + if (level < NUM_LEVELS-1) begin + for (l = 0; l < 2**level; l++) begin + assign sel_nodes[2**level-1+l] = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1]; + assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ? + index_nodes[2**(level+1)-1+l*2] : index_nodes[2**(level+1)-1+l*2+1]; + end + end + //------------------------------------------------------------ + if (level == NUM_LEVELS-1) begin + for (k = 0; k < 2**level; k++) begin + // if two successive indices are still in the vector... + if (k * 2 < LEN-1) begin + assign sel_nodes[2**level-1+k] = in_i[k*2] | in_i[k*2+1]; + assign index_nodes[2**level-1+k] = (in_i[k*2] == 1'b1) ? index_lut[k*2] : index_lut[k*2+1]; + end + // if only the first index is still in the vector... + if (k * 2 == LEN-1) begin + assign sel_nodes[2**level-1+k] = in_i[k*2]; + assign index_nodes[2**level-1+k] = index_lut[k*2]; + end + // if index is out of range + if (k * 2 > LEN-1) begin + assign sel_nodes[2**level-1+k] = 1'b0; + assign index_nodes[2**level-1+k] = '0; + end + end + end + //------------------------------------------------------------ + end + endgenerate + + ////////////////////////////////////////////////////////////////////////////// + // connect output + ////////////////////////////////////////////////////////////////////////////// + + assign first_one_o = index_nodes[0]; + assign no_ones_o = ~sel_nodes[0]; + +endmodule diff --git a/hw/deps/riscv/riscv_hwloop_controller.sv b/hw/deps/riscv/riscv_hwloop_controller.sv new file mode 100644 index 0000000..bab8f0a --- /dev/null +++ b/hw/deps/riscv/riscv_hwloop_controller.sv @@ -0,0 +1,98 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch // +// // +// Design Name: hwloop controller // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Hardware loop controller unit. This unit is responsible to // +// handle hardware loops. Tasks are: // +// a) compare PC to all stored end addresses // +// b) jump to the right start address if counter =/ 0 // +// // +//////////////////////////////////////////////////////////////////////////////// + +module riscv_hwloop_controller +#( + parameter N_REGS = 2 +) +( + // from id stage + input logic [31:0] current_pc_i, + + // from hwloop_regs + input logic [N_REGS-1:0] [31:0] hwlp_start_addr_i, + input logic [N_REGS-1:0] [31:0] hwlp_end_addr_i, + input logic [N_REGS-1:0] [31:0] hwlp_counter_i, + + // to hwloop_regs + output logic [N_REGS-1:0] hwlp_dec_cnt_o, + + // from pipeline stages + input logic [N_REGS-1:0] hwlp_dec_cnt_id_i, + + // to id stage + output logic hwlp_jump_o, + output logic [31:0] hwlp_targ_addr_o +); + + + logic [N_REGS-1:0] pc_is_end_addr; + + // end address detection + integer j; + + + // generate comparators. check for end address and the loop counter + genvar i; + generate + for (i = 0; i < N_REGS; i++) begin + always @(*) + begin + pc_is_end_addr[i] = 1'b0; + + if (current_pc_i == hwlp_end_addr_i[i]) begin + if (hwlp_counter_i[i][31:2] != 30'h0) begin + pc_is_end_addr[i] = 1'b1; + end else begin + // hwlp_counter_i[i][31:2] == 32'h0 + case (hwlp_counter_i[i][1:0]) + 2'b11: pc_is_end_addr[i] = 1'b1; + 2'b10: pc_is_end_addr[i] = ~hwlp_dec_cnt_id_i[i]; // only when there is nothing in flight + 2'b01, 2'b00: pc_is_end_addr[i] = 1'b0; + endcase + end + end + end + end + endgenerate + + // select corresponding start address and decrement counter + always_comb + begin + hwlp_targ_addr_o = '0; + hwlp_dec_cnt_o = '0; + + for (j = 0; j < N_REGS; j++) begin + if (pc_is_end_addr[j]) begin + hwlp_targ_addr_o = hwlp_start_addr_i[j]; + hwlp_dec_cnt_o[j] = 1'b1; + break; + end + end + end + + // output signal for ID stage + assign hwlp_jump_o = (|pc_is_end_addr); + +endmodule diff --git a/hw/deps/riscv/riscv_hwloop_regs.sv b/hw/deps/riscv/riscv_hwloop_regs.sv new file mode 100644 index 0000000..4f5b58b --- /dev/null +++ b/hw/deps/riscv/riscv_hwloop_regs.sv @@ -0,0 +1,134 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch // +// // +// Design Name: hwloop regs // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Hardware loop registers // +// a) store start/end address of N=4 hardware loops // +// b) store init value of counter for each hardware loop // +// c) decrement counter if hwloop taken // +// // +//////////////////////////////////////////////////////////////////////////////// + +module riscv_hwloop_regs +#( + parameter N_REGS = 2, + parameter N_REG_BITS = $clog2(N_REGS) +) +( + input logic clk, + input logic rst_n, + + // from ex stage + input logic [31:0] hwlp_start_data_i, + input logic [31:0] hwlp_end_data_i, + input logic [31:0] hwlp_cnt_data_i, + input logic [2:0] hwlp_we_i, + input logic [N_REG_BITS-1:0] hwlp_regid_i, // selects the register set + + // from controller + input logic valid_i, + + // from hwloop controller + input logic [N_REGS-1:0] hwlp_dec_cnt_i, + + // to hwloop controller + output logic [N_REGS-1:0] [31:0] hwlp_start_addr_o, + output logic [N_REGS-1:0] [31:0] hwlp_end_addr_o, + output logic [N_REGS-1:0] [31:0] hwlp_counter_o +); + + + logic [N_REGS-1:0] [31:0] hwlp_start_q; + logic [N_REGS-1:0] [31:0] hwlp_end_q; + logic [N_REGS-1:0] [31:0] hwlp_counter_q, hwlp_counter_n; + + int unsigned i; + + + assign hwlp_start_addr_o = hwlp_start_q; + assign hwlp_end_addr_o = hwlp_end_q; + assign hwlp_counter_o = hwlp_counter_q; + + + ///////////////////////////////////////////////////////////////////////////////// + // HWLOOP start-address register // + ///////////////////////////////////////////////////////////////////////////////// + always_ff @(posedge clk, negedge rst_n) + begin : HWLOOP_REGS_START + if (rst_n == 1'b0) + begin + hwlp_start_q <= '{default: 32'b0}; + end + else if (hwlp_we_i[0] == 1'b1) + begin + hwlp_start_q[hwlp_regid_i] <= hwlp_start_data_i; + end + end + + + ///////////////////////////////////////////////////////////////////////////////// + // HWLOOP end-address register // + ///////////////////////////////////////////////////////////////////////////////// + always_ff @(posedge clk, negedge rst_n) + begin : HWLOOP_REGS_END + if (rst_n == 1'b0) + begin + hwlp_end_q <= '{default: 32'b0}; + end + else if (hwlp_we_i[1] == 1'b1) + begin + hwlp_end_q[hwlp_regid_i] <= hwlp_end_data_i; + end + end + + + ///////////////////////////////////////////////////////////////////////////////// + // HWLOOP counter register with decrement logic // + ///////////////////////////////////////////////////////////////////////////////// + genvar k; + for (k = 0; k < N_REGS; k++) begin + assign hwlp_counter_n[k] = hwlp_counter_q[k] - 1; + end + + always_ff @(posedge clk, negedge rst_n) + begin : HWLOOP_REGS_COUNTER + if (rst_n == 1'b0) + begin + hwlp_counter_q <= '{default: 32'b0}; + end + else + begin + for (i = 0; i < N_REGS; i++) + begin + if ((hwlp_we_i[2] == 1'b1) && (i == hwlp_regid_i)) begin + hwlp_counter_q[i] <= hwlp_cnt_data_i; + end else begin + if (hwlp_dec_cnt_i[i] && valid_i) + hwlp_counter_q[i] <= hwlp_counter_n[i]; + end + end + end + end + + //---------------------------------------------------------------------------- + // Assertions + //---------------------------------------------------------------------------- + `ifndef VERILATOR + // do not decrement more than one counter at once + assert property ( + @(posedge clk) (valid_i) |-> ($countones(hwlp_dec_cnt_i) <= 1) ); + `endif +endmodule diff --git a/hw/deps/riscv/riscv_id_stage.sv b/hw/deps/riscv/riscv_id_stage.sv new file mode 100644 index 0000000..0c0df3b --- /dev/null +++ b/hw/deps/riscv/riscv_id_stage.sv @@ -0,0 +1,1676 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Renzo Andri - andrire@student.ethz.ch // +// // +// Additional contributions by: // +// Igor Loi - igor.loi@unibo.it // +// Andreas Traber - atraber@student.ethz.ch // +// Sven Stucki - svstucki@student.ethz.ch // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: Instruction Decode Stage // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Decode stage of the core. It decodes the instructions // +// and hosts the register file. // +// // +//////////////////////////////////////////////////////////////////////////////// + +import riscv_defines::*; +import apu_core_package::*; + + +// Source/Destination register instruction index +`define REG_S1 19:15 +`define REG_S2 24:20 +`define REG_S4 31:27 +`define REG_D 11:07 + +module riscv_id_stage +#( + parameter PULP_HWLP = 0, + parameter N_HWLP = 2, + parameter N_HWLP_BITS = $clog2(N_HWLP), + parameter PULP_SECURE = 0, + parameter USE_PMP = 0, + parameter A_EXTENSION = 0, + parameter APU = 0, + parameter FPU = 0, + parameter PULP_ZFINX = 0, + parameter FP_DIVSQRT = 0, + parameter SHARED_FP = 0, + parameter SHARED_DSP_MULT = 0, + parameter SHARED_INT_MULT = 0, + parameter SHARED_INT_DIV = 0, + parameter SHARED_FP_DIVSQRT = 0, + parameter WAPUTYPE = 0, + parameter APU_NARGS_CPU = 3, + parameter APU_WOP_CPU = 6, + parameter APU_NDSFLAGS_CPU = 15, + parameter APU_NUSFLAGS_CPU = 5, + parameter DEBUG_TRIGGER_EN = 1 +) +( + input logic clk, + input logic rst_n, + + input logic scan_cg_en_i, + + input logic fetch_enable_i, + output logic ctrl_busy_o, + output logic core_ctrl_firstfetch_o, + output logic is_decoding_o, + + // Interface to IF stage + input logic [N_HWLP-1:0] hwlp_dec_cnt_i, + input logic is_hwlp_i, + input logic instr_valid_i, + input logic [31:0] instr_rdata_i, // comes from pipeline of IF stage + output logic instr_req_o, + + + // Jumps and branches + output logic branch_in_ex_o, + input logic branch_decision_i, + output logic [31:0] jump_target_o, + + // IF and ID stage signals + output logic clear_instr_valid_o, + output logic pc_set_o, + output logic [2:0] pc_mux_o, + output logic [2:0] exc_pc_mux_o, + output logic [1:0] trap_addr_mux_o, + + input logic illegal_c_insn_i, + input logic is_compressed_i, + input logic is_fetch_failed_i, + + input logic [31:0] pc_if_i, + input logic [31:0] pc_id_i, + + // Stalls + output logic halt_if_o, // controller requests a halt of the IF stage + + output logic id_ready_o, // ID stage is ready for the next instruction + input logic ex_ready_i, // EX stage is ready for the next instruction + input logic wb_ready_i, // WB stage is ready for the next instruction + + output logic id_valid_o, // ID stage is done + input logic ex_valid_i, // EX stage is done + + // Pipeline ID/EX + output logic [31:0] pc_ex_o, + + output logic [31:0] alu_operand_a_ex_o, + output logic [31:0] alu_operand_b_ex_o, + output logic [31:0] alu_operand_c_ex_o, + output logic [ 4:0] bmask_a_ex_o, + output logic [ 4:0] bmask_b_ex_o, + output logic [ 1:0] imm_vec_ext_ex_o, + output logic [ 1:0] alu_vec_mode_ex_o, + + output logic [5:0] regfile_waddr_ex_o, + output logic regfile_we_ex_o, + + output logic [5:0] regfile_alu_waddr_ex_o, + output logic regfile_alu_we_ex_o, + + // ALU + output logic alu_en_ex_o, + output logic [ALU_OP_WIDTH-1:0] alu_operator_ex_o, + output logic alu_is_clpx_ex_o, + output logic alu_is_subrot_ex_o, + output logic [ 1:0] alu_clpx_shift_ex_o, + + + // MUL + output logic [ 2:0] mult_operator_ex_o, + output logic [31:0] mult_operand_a_ex_o, + output logic [31:0] mult_operand_b_ex_o, + output logic [31:0] mult_operand_c_ex_o, + output logic mult_en_ex_o, + output logic mult_sel_subword_ex_o, + output logic [ 1:0] mult_signed_mode_ex_o, + output logic [ 4:0] mult_imm_ex_o, + + output logic [31:0] mult_dot_op_a_ex_o, + output logic [31:0] mult_dot_op_b_ex_o, + output logic [31:0] mult_dot_op_c_ex_o, + output logic [ 1:0] mult_dot_signed_ex_o, + output logic mult_is_clpx_ex_o, + output logic [ 1:0] mult_clpx_shift_ex_o, + output logic mult_clpx_img_ex_o, + + // APU + output logic apu_en_ex_o, + output logic [WAPUTYPE-1:0] apu_type_ex_o, + output logic [APU_WOP_CPU-1:0] apu_op_ex_o, + output logic [1:0] apu_lat_ex_o, + output logic [APU_NARGS_CPU-1:0][31:0] apu_operands_ex_o, + output logic [APU_NDSFLAGS_CPU-1:0] apu_flags_ex_o, + output logic [5:0] apu_waddr_ex_o, + + output logic [2:0][5:0] apu_read_regs_o, + output logic [2:0] apu_read_regs_valid_o, + input logic apu_read_dep_i, + output logic [1:0][5:0] apu_write_regs_o, + output logic [1:0] apu_write_regs_valid_o, + input logic apu_write_dep_i, + output logic apu_perf_dep_o, + input logic apu_busy_i, + input logic [C_RM-1:0] frm_i, + + // CSR ID/EX + output logic csr_access_ex_o, + output logic [1:0] csr_op_ex_o, + input PrivLvl_t current_priv_lvl_i, + output logic csr_irq_sec_o, + output logic [6:0] csr_cause_o, + output logic csr_save_if_o, + output logic csr_save_id_o, + output logic csr_save_ex_o, + output logic csr_restore_mret_id_o, + output logic csr_restore_uret_id_o, + + output logic csr_restore_dret_id_o, + + // Stack protection + output logic stack_access_o, + + output logic csr_save_cause_o, + + // hwloop signals + output logic [N_HWLP-1:0] [31:0] hwlp_start_o, + output logic [N_HWLP-1:0] [31:0] hwlp_end_o, + output logic [N_HWLP-1:0] [31:0] hwlp_cnt_o, + + // hwloop signals from CS register + input logic [N_HWLP_BITS-1:0] csr_hwlp_regid_i, + input logic [2:0] csr_hwlp_we_i, + input logic [31:0] csr_hwlp_data_i, + + // Interface to load store unit + output logic data_req_ex_o, + output logic data_we_ex_o, + output logic [1:0] data_type_ex_o, + output logic [1:0] data_sign_ext_ex_o, + output logic [1:0] data_reg_offset_ex_o, + output logic data_load_event_ex_o, + + output logic data_misaligned_ex_o, + + output logic prepost_useincr_ex_o, + input logic data_misaligned_i, + input logic data_err_i, + output logic data_err_ack_o, + + output logic [5:0] atop_ex_o, + output logic buffer_ex_o, + + // Interrupt signals + input logic irq_pending_i, + input logic irq_sec_i, + input logic [5:0] irq_id_i, + input logic m_irq_enable_i, + input logic u_irq_enable_i, + output logic irq_ack_o, + output logic [5:0] irq_id_o, + output logic [5:0] exc_cause_o, + + // Debug Signal + output logic debug_mode_o, + output logic [2:0] debug_cause_o, + output logic debug_csr_save_o, + input logic debug_req_i, + input logic debug_single_step_i, + input logic debug_ebreakm_i, + input logic debug_ebreaku_i, + input logic trigger_match_i, + + // Forward Signals + input logic [5:0] regfile_waddr_wb_i, + input logic regfile_we_wb_i, + input logic [31:0] regfile_wdata_wb_i, // From wb_stage: selects data from data memory, ex_stage result and sp rdata + + input logic [5:0] regfile_alu_waddr_fw_i, + input logic regfile_alu_we_fw_i, + input logic [31:0] regfile_alu_wdata_fw_i, + + // from ALU + input logic mult_multicycle_i, // when we need multiple cycles in the multiplier and use op c as storage + + // Performance Counters + output logic perf_jump_o, // we are executing a jump instruction + output logic perf_jr_stall_o, // jump-register-hazard + output logic perf_ld_stall_o, // load-use-hazard + output logic perf_pipeline_stall_o //extra cycles from elw +); + + logic [31:0] instr; + + // Decoder/Controller ID stage internal signals + logic deassert_we; + + logic illegal_insn_dec; + logic ebrk_insn; + logic mret_insn_dec; + logic uret_insn_dec; + + logic dret_insn_dec; + + logic ecall_insn_dec; + logic pipe_flush_dec; + + logic fencei_insn_dec; + + logic rega_used_dec; + logic regb_used_dec; + logic regc_used_dec; + + logic branch_taken_ex; + logic [1:0] jump_in_id; + logic [1:0] jump_in_dec; + + logic misaligned_stall; + logic jr_stall; + logic load_stall; + logic csr_apu_stall; + logic instr_multicycle; + logic hwloop_mask; + logic halt_id; + + + // Immediate decoding and sign extension + logic [31:0] imm_i_type; + logic [31:0] imm_iz_type; + logic [31:0] imm_s_type; + logic [31:0] imm_sb_type; + logic [31:0] imm_u_type; + logic [31:0] imm_uj_type; + logic [31:0] imm_z_type; + logic [31:0] imm_s2_type; + logic [31:0] imm_bi_type; + logic [31:0] imm_s3_type; + logic [31:0] imm_vs_type; + logic [31:0] imm_vu_type; + logic [31:0] imm_shuffleb_type; + logic [31:0] imm_shuffleh_type; + logic [31:0] imm_shuffle_type; + logic [31:0] imm_clip_type; + + logic [31:0] imm_a; // contains the immediate for operand b + logic [31:0] imm_b; // contains the immediate for operand b + + logic [31:0] jump_target; // calculated jump target (-> EX -> IF) + + + + // Signals running between controller and exception controller + logic irq_req_ctrl, irq_sec_ctrl; + logic [5:0] irq_id_ctrl; + logic exc_ack, exc_kill;// handshake + + // Register file interface + logic [5:0] regfile_addr_ra_id; + logic [5:0] regfile_addr_rb_id; + logic [5:0] regfile_addr_rc_id; + + logic regfile_fp_a; + logic regfile_fp_b; + logic regfile_fp_c; + logic regfile_fp_d; + + logic fregfile_ena; // whether the fp register file is enabled/present + + logic [5:0] regfile_waddr_id; + logic [5:0] regfile_alu_waddr_id; + logic regfile_alu_we_id, regfile_alu_we_dec_id; + + logic [31:0] regfile_data_ra_id; + logic [31:0] regfile_data_rb_id; + logic [31:0] regfile_data_rc_id; + + // ALU Control + logic alu_en; + logic [ALU_OP_WIDTH-1:0] alu_operator; + logic [2:0] alu_op_a_mux_sel; + logic [2:0] alu_op_b_mux_sel; + logic [1:0] alu_op_c_mux_sel; + logic [1:0] regc_mux; + + logic [0:0] imm_a_mux_sel; + logic [3:0] imm_b_mux_sel; + logic [1:0] jump_target_mux_sel; + + // Multiplier Control + logic [2:0] mult_operator; // multiplication operation selection + logic mult_en; // multiplication is used instead of ALU + logic mult_int_en; // use integer multiplier + logic mult_sel_subword; // Select a subword when doing multiplications + logic [1:0] mult_signed_mode; // Signed mode multiplication at the output of the controller, and before the pipe registers + logic mult_dot_en; // use dot product + logic [1:0] mult_dot_signed; // Signed mode dot products (can be mixed types) + + // FPU signals + logic [C_FPNEW_FMTBITS-1:0] fpu_src_fmt; + logic [C_FPNEW_FMTBITS-1:0] fpu_dst_fmt; + logic [C_FPNEW_IFMTBITS-1:0] fpu_int_fmt; + + // APU signals + logic apu_en; + logic [WAPUTYPE-1:0] apu_type; + logic [APU_WOP_CPU-1:0] apu_op; + logic [1:0] apu_lat; + logic [APU_NARGS_CPU-1:0][31:0] apu_operands; + logic [APU_NDSFLAGS_CPU-1:0] apu_flags; + logic [5:0] apu_waddr; + + logic [2:0][5:0] apu_read_regs; + logic [2:0] apu_read_regs_valid; + logic [1:0][5:0] apu_write_regs; + logic [1:0] apu_write_regs_valid; + + logic [WAPUTYPE-1:0] apu_flags_src; + logic apu_stall; + logic [2:0] fp_rnd_mode; + + // Register Write Control + logic regfile_we_id; + logic regfile_alu_waddr_mux_sel; + + // Data Memory Control + logic data_we_id; + logic [1:0] data_type_id; + logic [1:0] data_sign_ext_id; + logic [1:0] data_reg_offset_id; + logic data_req_id; + logic data_load_event_id; + + // Atomic memory instruction + logic [5:0] atop_id; + logic buffer_id; + + // hwloop signals + logic [N_HWLP_BITS-1:0] hwloop_regid, hwloop_regid_int; + logic [2:0] hwloop_we, hwloop_we_int, hwloop_we_masked; + logic hwloop_target_mux_sel; + logic hwloop_start_mux_sel; + logic hwloop_cnt_mux_sel; + + logic [31:0] hwloop_target; + logic [31:0] hwloop_start, hwloop_start_int; + logic [31:0] hwloop_end; + logic [31:0] hwloop_cnt, hwloop_cnt_int; + + logic hwloop_valid; + + // CSR control + logic csr_access; + logic [1:0] csr_op; + logic csr_status; + + logic prepost_useincr; + + // Forwarding + logic [1:0] operand_a_fw_mux_sel; + logic [1:0] operand_b_fw_mux_sel; + logic [1:0] operand_c_fw_mux_sel; + logic [31:0] operand_a_fw_id; + logic [31:0] operand_b_fw_id; + logic [31:0] operand_c_fw_id; + + logic [31:0] operand_b, operand_b_vec; + logic [31:0] operand_c, operand_c_vec; + + logic [31:0] alu_operand_a; + logic [31:0] alu_operand_b; + logic [31:0] alu_operand_c; + + // Immediates for ID + logic [0:0] bmask_a_mux; + logic [1:0] bmask_b_mux; + logic alu_bmask_a_mux_sel; + logic alu_bmask_b_mux_sel; + logic [0:0] mult_imm_mux; + + logic [ 4:0] bmask_a_id_imm; + logic [ 4:0] bmask_b_id_imm; + logic [ 4:0] bmask_a_id; + logic [ 4:0] bmask_b_id; + logic [ 1:0] imm_vec_ext_id; + logic [ 4:0] mult_imm_id; + + logic [ 1:0] alu_vec_mode; + logic scalar_replication; + logic scalar_replication_c; + + // Forwarding detection signals + logic reg_d_ex_is_reg_a_id; + logic reg_d_ex_is_reg_b_id; + logic reg_d_ex_is_reg_c_id; + logic reg_d_wb_is_reg_a_id; + logic reg_d_wb_is_reg_b_id; + logic reg_d_wb_is_reg_c_id; + logic reg_d_alu_is_reg_a_id; + logic reg_d_alu_is_reg_b_id; + logic reg_d_alu_is_reg_c_id; + + logic stack_access; + + logic is_clpx, is_subrot; + + logic mret_dec; + logic uret_dec; + logic dret_dec; + + assign instr = instr_rdata_i; + + // immediate extraction and sign extension + assign imm_i_type = { {20 {instr[31]}}, instr[31:20] }; + assign imm_iz_type = { 20'b0, instr[31:20] }; + assign imm_s_type = { {20 {instr[31]}}, instr[31:25], instr[11:7] }; + assign imm_sb_type = { {19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 }; + assign imm_u_type = { instr[31:12], 12'b0 }; + assign imm_uj_type = { {12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }; + + // immediate for CSR manipulatin (zero extended) + assign imm_z_type = { 27'b0, instr[`REG_S1] }; + + assign imm_s2_type = { 27'b0, instr[24:20] }; + assign imm_bi_type = { {27{instr[24]}}, instr[24:20] }; + assign imm_s3_type = { 27'b0, instr[29:25] }; + assign imm_vs_type = { {26 {instr[24]}}, instr[24:20], instr[25] }; + assign imm_vu_type = { 26'b0, instr[24:20], instr[25] }; + + // same format as rS2 for shuffle needs, expands immediate + assign imm_shuffleb_type = {6'b0, instr[28:27], 6'b0, instr[24:23], 6'b0, instr[22:21], 6'b0, instr[20], instr[25]}; + assign imm_shuffleh_type = {15'h0, instr[20], 15'h0, instr[25]}; + + // clipping immediate, uses a small barrel shifter to pre-process the + // immediate and an adder to subtract 1 + // The end result is a mask that has 1's set in the lower part + // TODO: check if this can be shared with the bit-manipulation unit + assign imm_clip_type = (32'h1 << instr[24:20]) - 1; + + //----------------------------------------------------------------------------- + //-- FPU Register file enable: + //-- Taken from Cluster Config Reg if FPU reg file exists, or always disabled + //----------------------------------------------------------------------------- + assign fregfile_ena = FPU && !PULP_ZFINX ? 1'b1 : 1'b0; + + //--------------------------------------------------------------------------- + // source register selection regfile_fp_x=1 <=> REG_x is a FP-register + //--------------------------------------------------------------------------- + assign regfile_addr_ra_id = {fregfile_ena & regfile_fp_a, instr[`REG_S1]}; + assign regfile_addr_rb_id = {fregfile_ena & regfile_fp_b, instr[`REG_S2]}; + + // register C mux + always_comb begin + unique case (regc_mux) + REGC_ZERO: regfile_addr_rc_id = '0; + REGC_RD: regfile_addr_rc_id = {fregfile_ena & regfile_fp_c, instr[`REG_D]}; + REGC_S1: regfile_addr_rc_id = {fregfile_ena & regfile_fp_c, instr[`REG_S1]}; + REGC_S4: regfile_addr_rc_id = {fregfile_ena & regfile_fp_c, instr[`REG_S4]}; + default: regfile_addr_rc_id = '0; + endcase + end + + //--------------------------------------------------------------------------- + // destination registers regfile_fp_d=1 <=> REG_D is a FP-register + //--------------------------------------------------------------------------- + assign regfile_waddr_id = {fregfile_ena & regfile_fp_d, instr[`REG_D]}; + + // Second Register Write Address Selection + // Used for prepost load/store and multiplier + assign regfile_alu_waddr_id = regfile_alu_waddr_mux_sel ? + regfile_waddr_id : regfile_addr_ra_id; + + // Forwarding control signals + assign reg_d_ex_is_reg_a_id = (regfile_waddr_ex_o == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0); + assign reg_d_ex_is_reg_b_id = (regfile_waddr_ex_o == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0); + assign reg_d_ex_is_reg_c_id = (regfile_waddr_ex_o == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0); + assign reg_d_wb_is_reg_a_id = (regfile_waddr_wb_i == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0); + assign reg_d_wb_is_reg_b_id = (regfile_waddr_wb_i == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0); + assign reg_d_wb_is_reg_c_id = (regfile_waddr_wb_i == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0); + assign reg_d_alu_is_reg_a_id = (regfile_alu_waddr_fw_i == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0); + assign reg_d_alu_is_reg_b_id = (regfile_alu_waddr_fw_i == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0); + assign reg_d_alu_is_reg_c_id = (regfile_alu_waddr_fw_i == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0); + + + // kill instruction in the IF/ID stage by setting the instr_valid_id control + // signal to 0 for instructions that are done + assign clear_instr_valid_o = id_ready_o | halt_id | branch_taken_ex; + + assign branch_taken_ex = branch_in_ex_o & branch_decision_i; + + + assign mult_en = mult_int_en | mult_dot_en; + + /////////////////////////////////////////////// + // _ ___ ___ ___ ___ ____ // + // | | | \ \ / / | / _ \ / _ \| _ \ // + // | |_| |\ \ /\ / /| | | | | | | | | |_) | // + // | _ | \ V V / | |__| |_| | |_| | __/ // + // |_| |_| \_/\_/ |_____\___/ \___/|_| // + // // + /////////////////////////////////////////////// + + // hwloop register id + assign hwloop_regid_int = instr[7]; // rd contains hwloop register id + + // hwloop target mux + always_comb begin + case (hwloop_target_mux_sel) + 1'b0: hwloop_target = pc_id_i + {imm_iz_type[30:0], 1'b0}; + 1'b1: hwloop_target = pc_id_i + {imm_z_type[30:0], 1'b0}; + endcase + end + + // hwloop start mux + always_comb begin + case (hwloop_start_mux_sel) + 1'b0: hwloop_start_int = hwloop_target; // for PC + I imm + 1'b1: hwloop_start_int = pc_if_i; // for next PC + endcase + end + + + // hwloop cnt mux + always_comb begin : hwloop_cnt_mux + case (hwloop_cnt_mux_sel) + 1'b0: hwloop_cnt_int = imm_iz_type; + 1'b1: hwloop_cnt_int = operand_a_fw_id; + endcase; + end + + /* + when hwloop_mask is 1, the controller is about to take an interrupt + the xEPC is going to have the hwloop instruction PC, therefore, do not update the + hwloop registers to make clear that the instruction hasn't been executed. + Although it may not be a HW bugs causing uninteded behaviours, + it helps verifications processes when checking the hwloop regs + */ + assign hwloop_we_masked = hwloop_we_int & ~{3{hwloop_mask}} & {3{id_ready_o}}; + + // multiplex between access from instructions and access via CSR registers + assign hwloop_start = hwloop_we_masked[0] ? hwloop_start_int : csr_hwlp_data_i; + assign hwloop_end = hwloop_we_masked[1] ? hwloop_target : csr_hwlp_data_i; + assign hwloop_cnt = hwloop_we_masked[2] ? hwloop_cnt_int : csr_hwlp_data_i; + assign hwloop_regid = (|hwloop_we_masked) ? hwloop_regid_int : csr_hwlp_regid_i; + assign hwloop_we = (|hwloop_we_masked) ? hwloop_we_masked : csr_hwlp_we_i; + + + ////////////////////////////////////////////////////////////////// + // _ _____ _ // + // | |_ _ _ __ ___ _ __ |_ _|_ _ _ __ __ _ ___| |_ // + // _ | | | | | '_ ` _ \| '_ \ | |/ _` | '__/ _` |/ _ \ __| // + // | |_| | |_| | | | | | | |_) | | | (_| | | | (_| | __/ |_ // + // \___/ \__,_|_| |_| |_| .__/ |_|\__,_|_| \__, |\___|\__| // + // |_| |___/ // + ////////////////////////////////////////////////////////////////// + + always_comb begin : jump_target_mux + unique case (jump_target_mux_sel) + JT_JAL: jump_target = pc_id_i + imm_uj_type; + JT_COND: jump_target = pc_id_i + imm_sb_type; + + // JALR: Cannot forward RS1, since the path is too long + JT_JALR: jump_target = regfile_data_ra_id + imm_i_type; + default: jump_target = regfile_data_ra_id + imm_i_type; + endcase + end + + assign jump_target_o = jump_target; + + + //////////////////////////////////////////////////////// + // ___ _ _ // + // / _ \ _ __ ___ _ __ __ _ _ __ __| | / \ // + // | | | | '_ \ / _ \ '__/ _` | '_ \ / _` | / _ \ // + // | |_| | |_) | __/ | | (_| | | | | (_| | / ___ \ // + // \___/| .__/ \___|_| \__,_|_| |_|\__,_| /_/ \_\ // + // |_| // + //////////////////////////////////////////////////////// + + // ALU_Op_a Mux + always_comb begin : alu_operand_a_mux + case (alu_op_a_mux_sel) + OP_A_REGA_OR_FWD: alu_operand_a = operand_a_fw_id; + OP_A_REGB_OR_FWD: alu_operand_a = operand_b_fw_id; + OP_A_REGC_OR_FWD: alu_operand_a = operand_c_fw_id; + OP_A_CURRPC: alu_operand_a = pc_id_i; + OP_A_IMM: alu_operand_a = imm_a; + default: alu_operand_a = operand_a_fw_id; + endcase; // case (alu_op_a_mux_sel) + end + + always_comb begin : immediate_a_mux + unique case (imm_a_mux_sel) + IMMA_Z: imm_a = imm_z_type; + IMMA_ZERO: imm_a = '0; + default: imm_a = '0; + endcase + end + + // Operand a forwarding mux + always_comb begin : operand_a_fw_mux + case (operand_a_fw_mux_sel) + SEL_FW_EX: operand_a_fw_id = regfile_alu_wdata_fw_i; + SEL_FW_WB: operand_a_fw_id = regfile_wdata_wb_i; + SEL_REGFILE: operand_a_fw_id = regfile_data_ra_id; + default: operand_a_fw_id = regfile_data_ra_id; + endcase; // case (operand_a_fw_mux_sel) + end + + ////////////////////////////////////////////////////// + // ___ _ ____ // + // / _ \ _ __ ___ _ __ __ _ _ __ __| | | __ ) // + // | | | | '_ \ / _ \ '__/ _` | '_ \ / _` | | _ \ // + // | |_| | |_) | __/ | | (_| | | | | (_| | | |_) | // + // \___/| .__/ \___|_| \__,_|_| |_|\__,_| |____/ // + // |_| // + ////////////////////////////////////////////////////// + + // Immediate Mux for operand B + // TODO: check if sign-extension stuff works well here, maybe able to save + // some area here + always_comb begin : immediate_b_mux + unique case (imm_b_mux_sel) + IMMB_I: imm_b = imm_i_type; + IMMB_S: imm_b = imm_s_type; + IMMB_U: imm_b = imm_u_type; + IMMB_PCINCR: imm_b = (is_compressed_i && (~data_misaligned_i)) ? 32'h2 : 32'h4; + IMMB_S2: imm_b = imm_s2_type; + IMMB_BI: imm_b = imm_bi_type; + IMMB_S3: imm_b = imm_s3_type; + IMMB_VS: imm_b = imm_vs_type; + IMMB_VU: imm_b = imm_vu_type; + IMMB_SHUF: imm_b = imm_shuffle_type; + IMMB_CLIP: imm_b = {1'b0, imm_clip_type[31:1]}; + default: imm_b = imm_i_type; + endcase + end + + // ALU_Op_b Mux + always_comb begin : alu_operand_b_mux + case (alu_op_b_mux_sel) + OP_B_REGA_OR_FWD: operand_b = operand_a_fw_id; + OP_B_REGB_OR_FWD: operand_b = operand_b_fw_id; + OP_B_REGC_OR_FWD: operand_b = operand_c_fw_id; + OP_B_IMM: operand_b = imm_b; + OP_B_BMASK: operand_b = $unsigned(operand_b_fw_id[4:0]); + default: operand_b = operand_b_fw_id; + endcase // case (alu_op_b_mux_sel) + end + + + // scalar replication for operand B and shuffle type + always_comb begin + if (alu_vec_mode == VEC_MODE8) begin + operand_b_vec = {4{operand_b[7:0]}}; + imm_shuffle_type = imm_shuffleb_type; + end else begin + operand_b_vec = {2{operand_b[15:0]}}; + imm_shuffle_type = imm_shuffleh_type; + end + end + + // choose normal or scalar replicated version of operand b + assign alu_operand_b = (scalar_replication == 1'b1) ? operand_b_vec : operand_b; + + + // Operand b forwarding mux + always_comb begin : operand_b_fw_mux + case (operand_b_fw_mux_sel) + SEL_FW_EX: operand_b_fw_id = regfile_alu_wdata_fw_i; + SEL_FW_WB: operand_b_fw_id = regfile_wdata_wb_i; + SEL_REGFILE: operand_b_fw_id = regfile_data_rb_id; + default: operand_b_fw_id = regfile_data_rb_id; + endcase; // case (operand_b_fw_mux_sel) + end + + + ////////////////////////////////////////////////////// + // ___ _ ____ // + // / _ \ _ __ ___ _ __ __ _ _ __ __| | / ___| // + // | | | | '_ \ / _ \ '__/ _` | '_ \ / _` | | | // + // | |_| | |_) | __/ | | (_| | | | | (_| | | |___ // + // \___/| .__/ \___|_| \__,_|_| |_|\__,_| \____| // + // |_| // + ////////////////////////////////////////////////////// + + // ALU OP C Mux + always_comb begin : alu_operand_c_mux + case (alu_op_c_mux_sel) + OP_C_REGC_OR_FWD: operand_c = operand_c_fw_id; + OP_C_REGB_OR_FWD: operand_c = operand_b_fw_id; + OP_C_JT: operand_c = jump_target; + default: operand_c = operand_c_fw_id; + endcase // case (alu_op_c_mux_sel) + end + + + // scalar replication for operand C and shuffle type + always_comb begin + if (alu_vec_mode == VEC_MODE8) begin + operand_c_vec = {4{operand_c[7:0]}}; + end else begin + operand_c_vec = {2{operand_c[15:0]}}; + end + end + + // choose normal or scalar replicated version of operand b + assign alu_operand_c = (scalar_replication_c == 1'b1) ? operand_c_vec : operand_c; + + + // Operand c forwarding mux + always_comb begin : operand_c_fw_mux + case (operand_c_fw_mux_sel) + SEL_FW_EX: operand_c_fw_id = regfile_alu_wdata_fw_i; + SEL_FW_WB: operand_c_fw_id = regfile_wdata_wb_i; + SEL_REGFILE: operand_c_fw_id = regfile_data_rc_id; + default: operand_c_fw_id = regfile_data_rc_id; + endcase; // case (operand_c_fw_mux_sel) + end + + + /////////////////////////////////////////////////////////////////////////// + // ___ _ _ _ ___ ____ // + // |_ _|_ __ ___ _ __ ___ ___ __| (_) __ _| |_ ___ ___ |_ _| _ \ // + // | || '_ ` _ \| '_ ` _ \ / _ \/ _` | |/ _` | __/ _ \/ __| | || | | | // + // | || | | | | | | | | | | __/ (_| | | (_| | || __/\__ \ | || |_| | // + // |___|_| |_| |_|_| |_| |_|\___|\__,_|_|\__,_|\__\___||___/ |___|____/ // + // // + /////////////////////////////////////////////////////////////////////////// + + always_comb begin + unique case (bmask_a_mux) + BMASK_A_ZERO: bmask_a_id_imm = '0; + BMASK_A_S3: bmask_a_id_imm = imm_s3_type[4:0]; + default: bmask_a_id_imm = '0; + endcase + end + always_comb begin + unique case (bmask_b_mux) + BMASK_B_ZERO: bmask_b_id_imm = '0; + BMASK_B_ONE: bmask_b_id_imm = 5'd1; + BMASK_B_S2: bmask_b_id_imm = imm_s2_type[4:0]; + BMASK_B_S3: bmask_b_id_imm = imm_s3_type[4:0]; + default: bmask_b_id_imm = '0; + endcase + end + + always_comb begin + unique case (alu_bmask_a_mux_sel) + BMASK_A_IMM: bmask_a_id = bmask_a_id_imm; + BMASK_A_REG: bmask_a_id = operand_b_fw_id[9:5]; + default: bmask_a_id = bmask_a_id_imm; + endcase + end + always_comb begin + unique case (alu_bmask_b_mux_sel) + BMASK_B_IMM: bmask_b_id = bmask_b_id_imm; + BMASK_B_REG: bmask_b_id = operand_b_fw_id[4:0]; + default: bmask_b_id = bmask_b_id_imm; + endcase + end + + assign imm_vec_ext_id = imm_vu_type[1:0]; + + + always_comb begin + unique case (mult_imm_mux) + MIMM_ZERO: mult_imm_id = '0; + MIMM_S3: mult_imm_id = imm_s3_type[4:0]; + default: mult_imm_id = '0; + endcase + end + + ///////////////////////////// + // APU operand assignment // + ///////////////////////////// + // read regs + generate + if (APU == 1) begin : apu_op_preparation + + if (APU_NARGS_CPU >= 1) + assign apu_operands[0] = alu_operand_a; + if (APU_NARGS_CPU >= 2) + assign apu_operands[1] = alu_operand_b; + if (APU_NARGS_CPU >= 3) + assign apu_operands[2] = alu_operand_c; + + // write reg + assign apu_waddr = regfile_alu_waddr_id; + + // flags + always_comb begin + unique case (apu_flags_src) + APU_FLAGS_INT_MULT: + apu_flags = {7'h0 , mult_imm_id, mult_signed_mode, mult_sel_subword}; + APU_FLAGS_DSP_MULT: + apu_flags = {13'h0, mult_dot_signed}; + APU_FLAGS_FP: + if (FPU == 1) + apu_flags = fp_rnd_mode; + else + apu_flags = '0; + APU_FLAGS_FPNEW: + if (FPU == 1) + apu_flags = {fpu_int_fmt, fpu_src_fmt, fpu_dst_fmt, fp_rnd_mode}; + else + apu_flags = '0; + default: + apu_flags = '0; + endcase + end + + // dependency checks + always_comb begin + unique case (alu_op_a_mux_sel) + OP_A_REGA_OR_FWD: begin + apu_read_regs[0] = regfile_addr_ra_id; + apu_read_regs_valid [0] = 1'b1; + end // OP_A_REGA_OR_FWD: + OP_A_REGB_OR_FWD: begin + apu_read_regs[0] = regfile_addr_rb_id; + apu_read_regs_valid[0] = 1'b1; + end + default: begin + apu_read_regs[0] = regfile_addr_ra_id; + apu_read_regs_valid [0] = 1'b0; + end + endcase + end + + always_comb begin + unique case (alu_op_b_mux_sel) + OP_B_REGA_OR_FWD: begin + apu_read_regs[1] = regfile_addr_ra_id; + apu_read_regs_valid[1] = 1'b1; + end + OP_B_REGB_OR_FWD: begin + apu_read_regs[1] = regfile_addr_rb_id; + apu_read_regs_valid[1] = 1'b1; + end + OP_B_REGC_OR_FWD: begin + apu_read_regs[1] = regfile_addr_rc_id; + apu_read_regs_valid[1] = 1'b1; + end + default: begin + apu_read_regs[1] = regfile_addr_rb_id; + apu_read_regs_valid [1] = 1'b0; + end + endcase + end + + always_comb begin + unique case (alu_op_c_mux_sel) + OP_C_REGB_OR_FWD: begin + apu_read_regs[2] = regfile_addr_rb_id; + apu_read_regs_valid[2] = 1'b1; + end + OP_C_REGC_OR_FWD: begin + apu_read_regs[2] = regfile_addr_rc_id; + apu_read_regs_valid[2] = 1'b1; + end + default: begin + apu_read_regs[2] = regfile_addr_rc_id; + apu_read_regs_valid [2] = 1'b0; + end + endcase + end + + assign apu_write_regs[0] = regfile_alu_waddr_id; + assign apu_write_regs_valid [0] = regfile_alu_we_id; + + assign apu_write_regs[1] = regfile_waddr_id; + assign apu_write_regs_valid[1] = regfile_we_id; + + assign apu_read_regs_o = apu_read_regs; + assign apu_read_regs_valid_o = apu_read_regs_valid; + + assign apu_write_regs_o = apu_write_regs; + assign apu_write_regs_valid_o = apu_write_regs_valid; + end else begin + for (genvar i=0; i= C_RM+2*C_FPNEW_FMTBITS+C_FPNEW_IFMTBITS) + else $error("[apu] APU_NDSFLAGS_CPU APU flagbits is smaller than %0d", C_RM+2*C_FPNEW_FMTBITS+C_FPNEW_IFMTBITS); + end + end +`endif + + + ///////////////////////////////////////////////////////// + // ____ _____ ____ ___ ____ _____ _____ ____ ____ // + // | _ \| ____/ ___|_ _/ ___|_ _| ____| _ \/ ___| // + // | |_) | _|| | _ | |\___ \ | | | _| | |_) \___ \ // + // | _ <| |__| |_| || | ___) || | | |___| _ < ___) | // + // |_| \_\_____\____|___|____/ |_| |_____|_| \_\____/ // + // // + ///////////////////////////////////////////////////////// + riscv_register_file + #( + .ADDR_WIDTH(6), + .FPU(FPU) + ) + registers_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .test_en_i ( scan_cg_en_i ), + + .fregfile_disable_i ( 1'b0 ), + + // Read port a + .raddr_a_i ( regfile_addr_ra_id ), + .rdata_a_o ( regfile_data_ra_id ), + + // Read port b + .raddr_b_i ( regfile_addr_rb_id ), + .rdata_b_o ( regfile_data_rb_id ), + + // Read port c + .raddr_c_i ( regfile_addr_rc_id ), + .rdata_c_o ( regfile_data_rc_id ), + + // Write port a + .waddr_a_i ( regfile_waddr_wb_i ), + .wdata_a_i ( regfile_wdata_wb_i ), + .we_a_i ( regfile_we_wb_i ), + + // Write port b + .waddr_b_i ( regfile_alu_waddr_fw_i ), + .wdata_b_i ( regfile_alu_wdata_fw_i ), + .we_b_i ( regfile_alu_we_fw_i ) + ); + + + + + /////////////////////////////////////////////// + // ____ _____ ____ ___ ____ _____ ____ // + // | _ \| ____/ ___/ _ \| _ \| ____| _ \ // + // | | | | _|| | | | | | | | | _| | |_) | // + // | |_| | |__| |__| |_| | |_| | |___| _ < // + // |____/|_____\____\___/|____/|_____|_| \_\ // + // // + /////////////////////////////////////////////// + + riscv_decoder + #( + .PULP_HWLP ( PULP_HWLP ), + .A_EXTENSION ( A_EXTENSION ), + .FPU ( FPU ), + .FP_DIVSQRT ( FP_DIVSQRT ), + .PULP_SECURE ( PULP_SECURE ), + .USE_PMP ( USE_PMP ), + .SHARED_FP ( SHARED_FP ), + .SHARED_DSP_MULT ( SHARED_DSP_MULT ), + .SHARED_INT_MULT ( SHARED_INT_MULT ), + .SHARED_INT_DIV ( SHARED_INT_DIV ), + .SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ), + .WAPUTYPE ( WAPUTYPE ), + .APU_WOP_CPU ( APU_WOP_CPU ), + .DEBUG_TRIGGER_EN ( DEBUG_TRIGGER_EN ) + ) + decoder_i + ( + // controller related signals + .deassert_we_i ( deassert_we ), + .data_misaligned_i ( data_misaligned_i ), + .mult_multicycle_i ( mult_multicycle_i ), + .instr_multicycle_o ( instr_multicycle ), + + .illegal_insn_o ( illegal_insn_dec ), + .ebrk_insn_o ( ebrk_insn ), + + .mret_insn_o ( mret_insn_dec ), + .uret_insn_o ( uret_insn_dec ), + .dret_insn_o ( dret_insn_dec ), + + .mret_dec_o ( mret_dec ), + .uret_dec_o ( uret_dec ), + .dret_dec_o ( dret_dec ), + + .ecall_insn_o ( ecall_insn_dec ), + .pipe_flush_o ( pipe_flush_dec ), + + .fencei_insn_o ( fencei_insn_dec ), + + .rega_used_o ( rega_used_dec ), + .regb_used_o ( regb_used_dec ), + .regc_used_o ( regc_used_dec ), + + .reg_fp_a_o ( regfile_fp_a ), + .reg_fp_b_o ( regfile_fp_b ), + .reg_fp_c_o ( regfile_fp_c ), + .reg_fp_d_o ( regfile_fp_d ), + + .bmask_a_mux_o ( bmask_a_mux ), + .bmask_b_mux_o ( bmask_b_mux ), + .alu_bmask_a_mux_sel_o ( alu_bmask_a_mux_sel ), + .alu_bmask_b_mux_sel_o ( alu_bmask_b_mux_sel ), + + // from IF/ID pipeline + .instr_rdata_i ( instr ), + .illegal_c_insn_i ( illegal_c_insn_i ), + + // ALU signals + .alu_en_o ( alu_en ), + .alu_operator_o ( alu_operator ), + .alu_op_a_mux_sel_o ( alu_op_a_mux_sel ), + .alu_op_b_mux_sel_o ( alu_op_b_mux_sel ), + .alu_op_c_mux_sel_o ( alu_op_c_mux_sel ), + .alu_vec_mode_o ( alu_vec_mode ), + .scalar_replication_o ( scalar_replication ), + .scalar_replication_c_o ( scalar_replication_c ), + .imm_a_mux_sel_o ( imm_a_mux_sel ), + .imm_b_mux_sel_o ( imm_b_mux_sel ), + .regc_mux_o ( regc_mux ), + .is_clpx_o ( is_clpx ), + .is_subrot_o ( is_subrot ), + + // MUL signals + .mult_operator_o ( mult_operator ), + .mult_int_en_o ( mult_int_en ), + .mult_sel_subword_o ( mult_sel_subword ), + .mult_signed_mode_o ( mult_signed_mode ), + .mult_imm_mux_o ( mult_imm_mux ), + .mult_dot_en_o ( mult_dot_en ), + .mult_dot_signed_o ( mult_dot_signed ), + + // FPU / APU signals + .frm_i ( frm_i ), + .fpu_src_fmt_o ( fpu_src_fmt ), + .fpu_dst_fmt_o ( fpu_dst_fmt ), + .fpu_int_fmt_o ( fpu_int_fmt ), + .apu_en_o ( apu_en ), + .apu_type_o ( apu_type ), + .apu_op_o ( apu_op ), + .apu_lat_o ( apu_lat ), + .apu_flags_src_o ( apu_flags_src ), + .fp_rnd_mode_o ( fp_rnd_mode ), + + // Register file control signals + .regfile_mem_we_o ( regfile_we_id ), + .regfile_alu_we_o ( regfile_alu_we_id ), + .regfile_alu_we_dec_o ( regfile_alu_we_dec_id ), + .regfile_alu_waddr_sel_o ( regfile_alu_waddr_mux_sel ), + + // CSR control signals + .csr_access_o ( csr_access ), + .csr_status_o ( csr_status ), + .csr_op_o ( csr_op ), + .current_priv_lvl_i ( current_priv_lvl_i ), + + // Stack protection + .stack_access_o ( stack_access ), + + // Data bus interface + .data_req_o ( data_req_id ), + .data_we_o ( data_we_id ), + .prepost_useincr_o ( prepost_useincr ), + .data_type_o ( data_type_id ), + .data_sign_extension_o ( data_sign_ext_id ), + .data_reg_offset_o ( data_reg_offset_id ), + .data_load_event_o ( data_load_event_id ), + + // Atomic memory access + .atop_o ( atop_id ), + .buffer_o ( buffer_id ), + + // hwloop signals + .hwloop_we_o ( hwloop_we_int ), + .hwloop_target_mux_sel_o ( hwloop_target_mux_sel ), + .hwloop_start_mux_sel_o ( hwloop_start_mux_sel ), + .hwloop_cnt_mux_sel_o ( hwloop_cnt_mux_sel ), + + // debug mode + .debug_mode_i ( debug_mode_o ), + + // jump/branches + .jump_in_dec_o ( jump_in_dec ), + .jump_in_id_o ( jump_in_id ), + .jump_target_mux_sel_o ( jump_target_mux_sel ) + + ); + + //////////////////////////////////////////////////////////////////// + // ____ ___ _ _ _____ ____ ___ _ _ _____ ____ // + // / ___/ _ \| \ | |_ _| _ \ / _ \| | | | | ____| _ \ // + // | | | | | | \| | | | | |_) | | | | | | | | _| | |_) | // + // | |__| |_| | |\ | | | | _ <| |_| | |___| |___| |___| _ < // + // \____\___/|_| \_| |_| |_| \_\\___/|_____|_____|_____|_| \_\ // + // // + //////////////////////////////////////////////////////////////////// + + riscv_controller + #( + .FPU ( FPU ) + ) + controller_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .fetch_enable_i ( fetch_enable_i ), + .ctrl_busy_o ( ctrl_busy_o ), + .first_fetch_o ( core_ctrl_firstfetch_o ), + .is_decoding_o ( is_decoding_o ), + .is_fetch_failed_i ( is_fetch_failed_i ), + + // decoder related signals + .deassert_we_o ( deassert_we ), + + .illegal_insn_i ( illegal_insn_dec ), + .ecall_insn_i ( ecall_insn_dec ), + .mret_insn_i ( mret_insn_dec ), + .uret_insn_i ( uret_insn_dec ), + + .dret_insn_i ( dret_insn_dec ), + + .mret_dec_i ( mret_dec ), + .uret_dec_i ( uret_dec ), + .dret_dec_i ( dret_dec ), + + + .pipe_flush_i ( pipe_flush_dec ), + .ebrk_insn_i ( ebrk_insn ), + .fencei_insn_i ( fencei_insn_dec ), + .csr_status_i ( csr_status ), + .instr_multicycle_i ( instr_multicycle ), + + .hwloop_mask_o ( hwloop_mask ), + + // from IF/ID pipeline + .instr_valid_i ( instr_valid_i ), + + // from prefetcher + .instr_req_o ( instr_req_o ), + + // to prefetcher + .pc_set_o ( pc_set_o ), + .pc_mux_o ( pc_mux_o ), + .exc_pc_mux_o ( exc_pc_mux_o ), + .exc_cause_o ( exc_cause_o ), + .trap_addr_mux_o ( trap_addr_mux_o ), + + // LSU + .data_req_ex_i ( data_req_ex_o ), + .data_we_ex_i ( data_we_ex_o ), + .data_misaligned_i ( data_misaligned_i ), + .data_load_event_i ( data_load_event_id ), + .data_err_i ( data_err_i ), + .data_err_ack_o ( data_err_ack_o ), + + // ALU + .mult_multicycle_i ( mult_multicycle_i ), + + // APU + .apu_en_i ( apu_en ), + .apu_read_dep_i ( apu_read_dep_i ), + .apu_write_dep_i ( apu_write_dep_i ), + + .apu_stall_o ( apu_stall ), + + // jump/branch control + .branch_taken_ex_i ( branch_taken_ex ), + .jump_in_id_i ( jump_in_id ), + .jump_in_dec_i ( jump_in_dec ), + + // Interrupt Controller Signals + .irq_pending_i ( irq_pending_i ), + .irq_req_ctrl_i ( irq_req_ctrl ), + .irq_sec_ctrl_i ( irq_sec_ctrl ), + .irq_id_ctrl_i ( irq_id_ctrl ), + .m_IE_i ( m_irq_enable_i ), + .u_IE_i ( u_irq_enable_i ), + .current_priv_lvl_i ( current_priv_lvl_i ), + + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_id_o ), + + .exc_ack_o ( exc_ack ), + .exc_kill_o ( exc_kill ), + + // Debug Signal + .debug_mode_o ( debug_mode_o ), + .debug_cause_o ( debug_cause_o ), + .debug_csr_save_o ( debug_csr_save_o ), + .debug_req_i ( debug_req_i ), + .debug_single_step_i ( debug_single_step_i ), + .debug_ebreakm_i ( debug_ebreakm_i ), + .debug_ebreaku_i ( debug_ebreaku_i ), + .trigger_match_i ( trigger_match_i ), + + // CSR Controller Signals + .csr_save_cause_o ( csr_save_cause_o ), + .csr_cause_o ( csr_cause_o ), + .csr_save_if_o ( csr_save_if_o ), + .csr_save_id_o ( csr_save_id_o ), + .csr_save_ex_o ( csr_save_ex_o ), + .csr_restore_mret_id_o ( csr_restore_mret_id_o ), + .csr_restore_uret_id_o ( csr_restore_uret_id_o ), + + .csr_restore_dret_id_o ( csr_restore_dret_id_o ), + + .csr_irq_sec_o ( csr_irq_sec_o ), + + // Write targets from ID + .regfile_we_id_i ( regfile_alu_we_dec_id ), + .regfile_alu_waddr_id_i ( regfile_alu_waddr_id ), + + // Forwarding signals from regfile + .regfile_we_ex_i ( regfile_we_ex_o ), + .regfile_waddr_ex_i ( regfile_waddr_ex_o ), + .regfile_we_wb_i ( regfile_we_wb_i ), + + // regfile port 2 + .regfile_alu_we_fw_i ( regfile_alu_we_fw_i ), + + // Forwarding detection signals + .reg_d_ex_is_reg_a_i ( reg_d_ex_is_reg_a_id ), + .reg_d_ex_is_reg_b_i ( reg_d_ex_is_reg_b_id ), + .reg_d_ex_is_reg_c_i ( reg_d_ex_is_reg_c_id ), + .reg_d_wb_is_reg_a_i ( reg_d_wb_is_reg_a_id ), + .reg_d_wb_is_reg_b_i ( reg_d_wb_is_reg_b_id ), + .reg_d_wb_is_reg_c_i ( reg_d_wb_is_reg_c_id ), + .reg_d_alu_is_reg_a_i ( reg_d_alu_is_reg_a_id ), + .reg_d_alu_is_reg_b_i ( reg_d_alu_is_reg_b_id ), + .reg_d_alu_is_reg_c_i ( reg_d_alu_is_reg_c_id ), + + // Forwarding signals + .operand_a_fw_mux_sel_o ( operand_a_fw_mux_sel ), + .operand_b_fw_mux_sel_o ( operand_b_fw_mux_sel ), + .operand_c_fw_mux_sel_o ( operand_c_fw_mux_sel ), + + // Stall signals + .halt_if_o ( halt_if_o ), + .halt_id_o ( halt_id ), + + .misaligned_stall_o ( misaligned_stall ), + .jr_stall_o ( jr_stall ), + .load_stall_o ( load_stall ), + + .id_ready_i ( id_ready_o ), + + .ex_valid_i ( ex_valid_i ), + + .wb_ready_i ( wb_ready_i ), + + // Performance Counters + .perf_jump_o ( perf_jump_o ), + .perf_jr_stall_o ( perf_jr_stall_o ), + .perf_ld_stall_o ( perf_ld_stall_o ), + .perf_pipeline_stall_o ( perf_pipeline_stall_o ) + ); + + +//////////////////////////////////////////////////////////////////////// +// _____ _ _____ _ _ _ // +// |_ _| | | / __ \ | | | | | // +// | | _ __ | |_ | / \/ ___ _ __ | |_ _ __ ___ | | | ___ _ __ // +// | || '_ \| __| | | / _ \| '_ \| __| '__/ _ \| | |/ _ \ '__| // +// _| || | | | |_ _ | \__/\ (_) | | | | |_| | | (_) | | | __/ | // +// \___/_| |_|\__(_) \____/\___/|_| |_|\__|_| \___/|_|_|\___|_| // +// // +//////////////////////////////////////////////////////////////////////// + + riscv_int_controller + #( + .PULP_SECURE(PULP_SECURE) + ) + int_controller_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + // to controller + .irq_req_ctrl_o ( irq_req_ctrl ), + .irq_sec_ctrl_o ( irq_sec_ctrl ), + .irq_id_ctrl_o ( irq_id_ctrl ), + + .ctrl_ack_i ( exc_ack ), + .ctrl_kill_i ( exc_kill ), + + // Interrupt signals + .irq_pending_i ( irq_pending_i ), + .irq_sec_i ( irq_sec_i ), + .irq_id_i ( irq_id_i ), + + .m_IE_i ( m_irq_enable_i ), + .u_IE_i ( u_irq_enable_i ), + .current_priv_lvl_i ( current_priv_lvl_i ) + + ); + + + ////////////////////////////////////////////////////////////////////////// + // ____ ___ _ _ _____ ____ ___ _ _ _____ ____ // + // / ___/ _ \| \ | |_ _| _ \ / _ \| | | | | ____| _ \ // + // HWLOOP-| | | | | | \| | | | | |_) | | | | | | | | _| | |_) | // + // | |__| |_| | |\ | | | | _ <| |_| | |___| |___| |___| _ < // + // \____\___/|_| \_| |_| |_| \_\\___/|_____|_____|_____|_| \_\ // + // // + ////////////////////////////////////////////////////////////////////////// + + riscv_hwloop_regs + #( + .N_REGS ( N_HWLP ) + ) + hwloop_regs_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + // from ID + .hwlp_start_data_i ( hwloop_start ), + .hwlp_end_data_i ( hwloop_end ), + .hwlp_cnt_data_i ( hwloop_cnt ), + .hwlp_we_i ( hwloop_we ), + .hwlp_regid_i ( hwloop_regid ), + + // from controller + .valid_i ( hwloop_valid ), + + // to hwloop controller + .hwlp_start_addr_o ( hwlp_start_o ), + .hwlp_end_addr_o ( hwlp_end_o ), + .hwlp_counter_o ( hwlp_cnt_o ), + + // from hwloop controller + .hwlp_dec_cnt_i ( hwlp_dec_cnt_i ) + ); + + assign hwloop_valid = instr_valid_i & clear_instr_valid_o & is_hwlp_i; + + + ///////////////////////////////////////////////////////////////////////////////// + // ___ ____ _______ __ ____ ___ ____ _____ _ ___ _ _ _____ // + // |_ _| _ \ | ____\ \/ / | _ \_ _| _ \| ____| | |_ _| \ | | ____| // + // | || | | |_____| _| \ / | |_) | || |_) | _| | | | || \| | _| // + // | || |_| |_____| |___ / \ | __/| || __/| |___| |___ | || |\ | |___ // + // |___|____/ |_____/_/\_\ |_| |___|_| |_____|_____|___|_| \_|_____| // + // // + ///////////////////////////////////////////////////////////////////////////////// + + always_ff @(posedge clk, negedge rst_n) + begin : ID_EX_PIPE_REGISTERS + if (rst_n == 1'b0) + begin + alu_en_ex_o <= '0; + alu_operator_ex_o <= ALU_SLTU; + alu_operand_a_ex_o <= '0; + alu_operand_b_ex_o <= '0; + alu_operand_c_ex_o <= '0; + bmask_a_ex_o <= '0; + bmask_b_ex_o <= '0; + imm_vec_ext_ex_o <= '0; + alu_vec_mode_ex_o <= '0; + alu_clpx_shift_ex_o <= 2'b0; + alu_is_clpx_ex_o <= 1'b0; + alu_is_subrot_ex_o <= 1'b0; + + mult_operator_ex_o <= '0; + mult_operand_a_ex_o <= '0; + mult_operand_b_ex_o <= '0; + mult_operand_c_ex_o <= '0; + mult_en_ex_o <= 1'b0; + mult_sel_subword_ex_o <= 1'b0; + mult_signed_mode_ex_o <= 2'b00; + mult_imm_ex_o <= '0; + + mult_dot_op_a_ex_o <= '0; + mult_dot_op_b_ex_o <= '0; + mult_dot_op_c_ex_o <= '0; + mult_dot_signed_ex_o <= '0; + mult_is_clpx_ex_o <= 1'b0; + mult_clpx_shift_ex_o <= 2'b0; + mult_clpx_img_ex_o <= 1'b0; + + apu_en_ex_o <= '0; + apu_type_ex_o <= '0; + apu_op_ex_o <= '0; + apu_lat_ex_o <= '0; + apu_operands_ex_o[0] <= '0; + apu_operands_ex_o[1] <= '0; + apu_operands_ex_o[2] <= '0; + apu_flags_ex_o <= '0; + apu_waddr_ex_o <= '0; + + + regfile_waddr_ex_o <= 6'b0; + regfile_we_ex_o <= 1'b0; + + regfile_alu_waddr_ex_o <= 6'b0; + regfile_alu_we_ex_o <= 1'b0; + prepost_useincr_ex_o <= 1'b0; + + csr_access_ex_o <= 1'b0; + csr_op_ex_o <= CSR_OP_READ; + + data_we_ex_o <= 1'b0; + data_type_ex_o <= 2'b0; + data_sign_ext_ex_o <= 2'b0; + data_reg_offset_ex_o <= 2'b0; + data_req_ex_o <= 1'b0; + data_load_event_ex_o <= 1'b0; + atop_ex_o <= 5'b0; + buffer_ex_o <= 1'b0; + + data_misaligned_ex_o <= 1'b0; + stack_access_o <= 1'b0; + + pc_ex_o <= '0; + + branch_in_ex_o <= 1'b0; + + end + else if (data_misaligned_i) begin + // misaligned data access case + if (ex_ready_i) + begin // misaligned access case, only unstall alu operands + + // if we are using post increments, then we have to use the + // original value of the register for the second memory access + // => keep it stalled + if (prepost_useincr_ex_o == 1'b1) + begin + alu_operand_a_ex_o <= alu_operand_a; + end + + alu_operand_b_ex_o <= alu_operand_b; + regfile_alu_we_ex_o <= regfile_alu_we_id; + prepost_useincr_ex_o <= prepost_useincr; + + data_misaligned_ex_o <= 1'b1; + stack_access_o <= stack_access; + end + end else if (mult_multicycle_i) begin + mult_operand_c_ex_o <= alu_operand_c; + end + else begin + // normal pipeline unstall case + + if (id_valid_o) + begin // unstall the whole pipeline + + alu_en_ex_o <= alu_en | branch_taken_ex; + if (alu_en | branch_taken_ex) + begin + //this prevents divisions or multicycle instructions to keep the EX stage busy + alu_operator_ex_o <= branch_taken_ex ? ALU_SLTU : alu_operator; + if(~branch_taken_ex) begin + alu_operand_a_ex_o <= alu_operand_a; + alu_operand_b_ex_o <= alu_operand_b; + alu_operand_c_ex_o <= alu_operand_c; + bmask_a_ex_o <= bmask_a_id; + bmask_b_ex_o <= bmask_b_id; + imm_vec_ext_ex_o <= imm_vec_ext_id; + alu_vec_mode_ex_o <= alu_vec_mode; + alu_is_clpx_ex_o <= is_clpx; + alu_clpx_shift_ex_o <= instr[14:13]; + alu_is_subrot_ex_o <= is_subrot; + end + end + + mult_en_ex_o <= mult_en; + if (mult_int_en) begin + mult_operator_ex_o <= mult_operator; + mult_sel_subword_ex_o <= mult_sel_subword; + mult_signed_mode_ex_o <= mult_signed_mode; + mult_operand_a_ex_o <= alu_operand_a; + mult_operand_b_ex_o <= alu_operand_b; + mult_operand_c_ex_o <= alu_operand_c; + mult_imm_ex_o <= mult_imm_id; + end + if (mult_dot_en) begin + mult_operator_ex_o <= mult_operator; + mult_dot_signed_ex_o <= mult_dot_signed; + mult_dot_op_a_ex_o <= alu_operand_a; + mult_dot_op_b_ex_o <= alu_operand_b; + mult_dot_op_c_ex_o <= alu_operand_c; + mult_is_clpx_ex_o <= is_clpx; + mult_clpx_shift_ex_o <= instr[14:13]; + mult_clpx_img_ex_o <= instr[25]; + end + + // APU pipeline + apu_en_ex_o <= apu_en; + if (apu_en) begin + apu_type_ex_o <= apu_type; + apu_op_ex_o <= apu_op; + apu_lat_ex_o <= apu_lat; + apu_operands_ex_o <= apu_operands; + apu_flags_ex_o <= apu_flags; + apu_waddr_ex_o <= apu_waddr; + end + + regfile_we_ex_o <= regfile_we_id; + if (regfile_we_id) begin + regfile_waddr_ex_o <= regfile_waddr_id; + end + + regfile_alu_we_ex_o <= regfile_alu_we_id; + if (regfile_alu_we_id) begin + regfile_alu_waddr_ex_o <= regfile_alu_waddr_id; + end + + prepost_useincr_ex_o <= prepost_useincr; + + csr_access_ex_o <= csr_access; + csr_op_ex_o <= csr_op; + + data_req_ex_o <= data_req_id; + if (data_req_id) + begin // only needed for LSU when there is an active request + data_we_ex_o <= data_we_id; + data_type_ex_o <= data_type_id; + data_sign_ext_ex_o <= data_sign_ext_id; + data_reg_offset_ex_o <= data_reg_offset_id; + data_load_event_ex_o <= data_load_event_id; + atop_ex_o <= atop_id; + buffer_ex_o <= buffer_id; + end else begin + data_load_event_ex_o <= 1'b0; + end + + data_misaligned_ex_o <= 1'b0; + stack_access_o <= stack_access; + + if ((jump_in_id == BRANCH_COND) || data_req_id) begin + pc_ex_o <= pc_id_i; + end + + branch_in_ex_o <= jump_in_id == BRANCH_COND; + end else if(ex_ready_i) begin + // EX stage is ready but we don't have a new instruction for it, + // so we set all write enables to 0, but unstall the pipe + + regfile_we_ex_o <= 1'b0; + + regfile_alu_we_ex_o <= 1'b0; + + csr_op_ex_o <= CSR_OP_READ; + + data_req_ex_o <= 1'b0; + + data_load_event_ex_o <= 1'b0; + + data_misaligned_ex_o <= 1'b0; + stack_access_o <= stack_access; + + branch_in_ex_o <= 1'b0; + + apu_en_ex_o <= 1'b0; + + alu_operator_ex_o <= ALU_SLTU; + + mult_en_ex_o <= 1'b0; + + alu_en_ex_o <= 1'b1; + + end else if (csr_access_ex_o) begin + //In the EX stage there was a CSR access, to avoid multiple + //writes to the RF, disable regfile_alu_we_ex_o. + //Not doing it can overwrite the RF file with the currennt CSR value rather than the old one + regfile_alu_we_ex_o <= 1'b0; + end + end + end + + + // stall control + assign id_ready_o = ((~misaligned_stall) & (~jr_stall) & (~load_stall) & (~apu_stall) & (~csr_apu_stall) & ex_ready_i); + assign id_valid_o = (~halt_id) & id_ready_o; + + + //---------------------------------------------------------------------------- + // Assertions + //---------------------------------------------------------------------------- + `ifndef VERILATOR + // make sure that branch decision is valid when jumping + assert property ( + @(posedge clk) (branch_in_ex_o) |-> (branch_decision_i !== 1'bx) ) else begin $display("%t, Branch decision is X in module %m", $time); $stop; end + + // the instruction delivered to the ID stage should always be valid + assert property ( + @(posedge clk) (instr_valid_i & (~illegal_c_insn_i)) |-> (!$isunknown(instr_rdata_i)) ) else $display("Instruction is valid, but has at least one X"); + `endif +endmodule diff --git a/hw/deps/riscv/riscv_if_stage.sv b/hw/deps/riscv/riscv_if_stage.sv new file mode 100644 index 0000000..cef7739 --- /dev/null +++ b/hw/deps/riscv/riscv_if_stage.sv @@ -0,0 +1,428 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Renzo Andri - andrire@student.ethz.ch // +// // +// Additional contributions by: // +// Igor Loi - igor.loi@unibo.it // +// Andreas Traber - atraber@student.ethz.ch // +// Sven Stucki - svstucki@student.ethz.ch // +// // +// Design Name: Instruction Fetch Stage // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Instruction fetch unit: Selection of the next PC, and // +// buffering (sampling) of the read instruction // +// // +//////////////////////////////////////////////////////////////////////////////// + + +import riscv_defines::*; + +module riscv_if_stage +#( + parameter N_HWLP = 2, + parameter RDATA_WIDTH = 32, + parameter FPU = 0 +) +( + input logic clk, + input logic rst_n, + + // Used to calculate the exception offsets + input logic [23:0] m_trap_base_addr_i, + input logic [23:0] u_trap_base_addr_i, + input logic [1:0] trap_addr_mux_i, + // Boot address + input logic [30:0] boot_addr_i, + + // Debug mode halt address + input logic [29:0] dm_halt_addr_i, + + // instruction request control + input logic req_i, + + // instruction cache interface + output logic instr_req_o, + output logic [31:0] instr_addr_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + input logic [RDATA_WIDTH-1:0] instr_rdata_i, + input logic instr_err_pmp_i, + + // Output of IF Pipeline stage + output logic [N_HWLP-1:0] hwlp_dec_cnt_id_o, // currently served instruction was the target of a hwlp + output logic is_hwlp_id_o, // currently served instruction was the target of a hwlp + output logic instr_valid_id_o, // instruction in IF/ID pipeline is valid + output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding + output logic is_compressed_id_o, // compressed decoder thinks this is a compressed instruction + output logic illegal_c_insn_id_o, // compressed decoder thinks this is an invalid instruction + output logic [31:0] pc_if_o, + output logic [31:0] pc_id_o, + output logic is_fetch_failed_o, + + // Forwarding ports - control signals + input logic clear_instr_valid_i, // clear instruction valid bit in IF/ID pipe + input logic pc_set_i, // set the program counter to a new value + input logic [31:0] mepc_i, // address used to restore PC when the interrupt/exception is served + input logic [31:0] uepc_i, // address used to restore PC when the interrupt/exception is served + + input logic [31:0] depc_i, // address used to restore PC when the debug is served + + input logic [2:0] pc_mux_i, // sel for pc multiplexer + input logic [2:0] exc_pc_mux_i, // selects ISR address + input logic [5:0] m_exc_vec_pc_mux_i, // selects ISR address for vectorized interrupt lines + input logic [5:0] u_exc_vec_pc_mux_i, // selects ISR address for vectorized interrupt lines + + // jump and branch target and decision + input logic [31:0] jump_target_id_i, // jump target address + input logic [31:0] jump_target_ex_i, // jump target address + + // from hwloop controller + input logic [N_HWLP-1:0] [31:0] hwlp_start_i, // hardware loop start addresses + input logic [N_HWLP-1:0] [31:0] hwlp_end_i, // hardware loop end addresses + input logic [N_HWLP-1:0] [31:0] hwlp_cnt_i, // hardware loop counters + + // pipeline stall + input logic halt_if_i, + input logic id_ready_i, + + // misc signals + output logic if_busy_o, // is the IF stage busy fetching instructions? + output logic perf_imiss_o // Instruction Fetch Miss +); + + localparam IGNORE_CAUSE_MSB = 0; // Ignore the MSB of the exception code (effectively mapping the top 32 and bottom 32 IRQs on top of each other) + + // offset FSM + enum logic[0:0] {WAIT, IDLE } offset_fsm_cs, offset_fsm_ns; + + logic if_valid, if_ready; + logic valid; + + // prefetch buffer related signals + logic prefetch_busy; + logic branch_req; + logic [31:0] fetch_addr_n; + + logic fetch_valid; + logic fetch_ready; + logic [31:0] fetch_rdata; + logic [31:0] fetch_addr; + logic is_hwlp_id_q, fetch_is_hwlp; + + logic [31:0] exc_pc; + + // hardware loop related signals + logic hwlp_jump, hwlp_branch; + logic [31:0] hwlp_target; + logic [N_HWLP-1:0] hwlp_dec_cnt, hwlp_dec_cnt_if; + + logic [23:0] trap_base_addr; + logic [5:0] exc_vec_pc_mux; + logic fetch_failed; + + + // exception PC selection mux + always_comb + begin : EXC_PC_MUX + unique case (trap_addr_mux_i) + TRAP_MACHINE: trap_base_addr = m_trap_base_addr_i; + TRAP_USER: trap_base_addr = u_trap_base_addr_i; + default: trap_base_addr = m_trap_base_addr_i; + endcase + + unique case (trap_addr_mux_i) + TRAP_MACHINE: exc_vec_pc_mux = m_exc_vec_pc_mux_i; + TRAP_USER: exc_vec_pc_mux = u_exc_vec_pc_mux_i; + default: exc_vec_pc_mux = m_exc_vec_pc_mux_i; + endcase + + unique case (exc_pc_mux_i) + EXC_PC_EXCEPTION: exc_pc = { trap_base_addr, 8'h0 }; //1.10 all the exceptions go to base address + EXC_PC_IRQ: exc_pc = { trap_base_addr, 1'b0,IGNORE_CAUSE_MSB ? {1'b0, exc_vec_pc_mux[4:0]} : exc_vec_pc_mux[5:0], 2'b0 }; // interrupts are vectored + EXC_PC_DBD: exc_pc = { dm_halt_addr_i, 2'b0 }; + default: exc_pc = { trap_base_addr, 8'h0 }; + endcase + end + + // fetch address selection + always_comb + begin + fetch_addr_n = '0; + + unique case (pc_mux_i) + PC_BOOT: fetch_addr_n = {boot_addr_i, 1'b0}; + PC_JUMP: fetch_addr_n = jump_target_id_i; + PC_BRANCH: fetch_addr_n = jump_target_ex_i; + PC_EXCEPTION: fetch_addr_n = exc_pc; // set PC to exception handler + PC_MRET: fetch_addr_n = mepc_i; // PC is restored when returning from IRQ/exception + PC_URET: fetch_addr_n = uepc_i; // PC is restored when returning from IRQ/exception + PC_DRET: fetch_addr_n = depc_i; // + PC_FENCEI: fetch_addr_n = pc_id_o + 4; // jump to next instr forces prefetch buffer reload + default:; + endcase + end + + generate + if (RDATA_WIDTH == 32) begin : prefetch_32 + // prefetch buffer, caches a fixed number of instructions + riscv_prefetch_buffer prefetch_buffer_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .req_i ( req_i ), + + .branch_i ( branch_req ), + .addr_i ( {fetch_addr_n[31:1], 1'b0} ), + + .hwloop_i ( hwlp_jump ), + .hwloop_target_i ( hwlp_target ), + .hwlp_branch_o ( hwlp_branch ), + + .ready_i ( fetch_ready ), + .valid_o ( fetch_valid ), + .rdata_o ( fetch_rdata ), + .addr_o ( fetch_addr ), + .is_hwlp_o ( fetch_is_hwlp ), + + // goes to instruction memory / instruction cache + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_err_pmp_i ( instr_err_pmp_i ), + .fetch_failed_o ( fetch_failed ), + .instr_rdata_i ( instr_rdata_i ), + + // Prefetch Buffer Status + .busy_o ( prefetch_busy ) + ); + end else if (RDATA_WIDTH == 128) begin : prefetch_128 + // prefetch buffer, caches a fixed number of instructions + riscv_prefetch_L0_buffer prefetch_buffer_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .req_i ( 1'b1 ), + + .branch_i ( branch_req ), + .addr_i ( {fetch_addr_n[31:1], 1'b0} ), + + .hwloop_i ( hwlp_jump ), + .hwloop_target_i ( hwlp_target ), + + .ready_i ( fetch_ready ), + .valid_o ( fetch_valid ), + .rdata_o ( fetch_rdata ), + .addr_o ( fetch_addr ), + .is_hwlp_o ( fetch_is_hwlp ), + + // goes to instruction memory / instruction cache + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + + // Prefetch Buffer Status + .busy_o ( prefetch_busy ) + ); + + assign hwlp_branch = 1'b0; + assign fetch_failed = 1'b0; + + end + endgenerate + + // offset FSM state + always_ff @(posedge clk, negedge rst_n) + begin + if (rst_n == 1'b0) begin + offset_fsm_cs <= IDLE; + end else begin + offset_fsm_cs <= offset_fsm_ns; + end + end + + // offset FSM state transition logic + always_comb + begin + offset_fsm_ns = offset_fsm_cs; + + fetch_ready = 1'b0; + branch_req = 1'b0; + valid = 1'b0; + + unique case (offset_fsm_cs) + // no valid instruction data for ID stage + // assume aligned + IDLE: begin + if (req_i) begin + branch_req = 1'b1; + offset_fsm_ns = WAIT; + end + end + + // serving aligned 32 bit or 16 bit instruction, we don't know yet + WAIT: begin + if (fetch_valid) begin + valid = 1'b1; // an instruction is ready for ID stage + + if (req_i && if_valid) begin + fetch_ready = 1'b1; + offset_fsm_ns = WAIT; + end + end + end + + default: begin + offset_fsm_ns = IDLE; + end + endcase + + + // take care of jumps and branches + if (pc_set_i) begin + valid = 1'b0; + + // switch to new PC from ID stage + branch_req = 1'b1; + offset_fsm_ns = WAIT; + end + else begin + if(hwlp_branch) + valid = 1'b0; + end + end + + // Hardware Loops + riscv_hwloop_controller + #( + .N_REGS ( N_HWLP ) + ) + hwloop_controller_i + ( + .current_pc_i ( fetch_addr ), + + .hwlp_jump_o ( hwlp_jump ), + .hwlp_targ_addr_o ( hwlp_target ), + + // from hwloop_regs + .hwlp_start_addr_i ( hwlp_start_i ), + .hwlp_end_addr_i ( hwlp_end_i ), + .hwlp_counter_i ( hwlp_cnt_i ), + + // to hwloop_regs + .hwlp_dec_cnt_o ( hwlp_dec_cnt ), + .hwlp_dec_cnt_id_i ( hwlp_dec_cnt_id_o & {N_HWLP{is_hwlp_id_o}} ) + ); + + + assign pc_if_o = fetch_addr; + + assign if_busy_o = prefetch_busy; + + assign perf_imiss_o = (~fetch_valid) | branch_req; + + + // compressed instruction decoding, or more precisely compressed instruction + // expander + // + // since it does not matter where we decompress instructions, we do it here + // to ease timing closure + logic [31:0] instr_decompressed; + logic illegal_c_insn; + logic instr_compressed_int; + + riscv_compressed_decoder + #( + .FPU(FPU) + ) + compressed_decoder_i + ( + .instr_i ( fetch_rdata ), + .instr_o ( instr_decompressed ), + .is_compressed_o ( instr_compressed_int ), + .illegal_instr_o ( illegal_c_insn ) + ); + + // prefetch -> IF registers + always_ff @(posedge clk, negedge rst_n) + begin + if (rst_n == 1'b0) + begin + hwlp_dec_cnt_if <= '0; + end + else + begin + if (hwlp_jump) + hwlp_dec_cnt_if <= hwlp_dec_cnt; + end + end + + // IF-ID pipeline registers, frozen when the ID stage is stalled + always_ff @(posedge clk, negedge rst_n) + begin : IF_ID_PIPE_REGISTERS + if (rst_n == 1'b0) + begin + instr_valid_id_o <= 1'b0; + instr_rdata_id_o <= '0; + illegal_c_insn_id_o <= 1'b0; + is_compressed_id_o <= 1'b0; + pc_id_o <= '0; + is_hwlp_id_q <= 1'b0; + hwlp_dec_cnt_id_o <= '0; + is_fetch_failed_o <= 1'b0; + + end + else + begin + + if (if_valid) + begin + instr_valid_id_o <= 1'b1; + instr_rdata_id_o <= instr_decompressed; + illegal_c_insn_id_o <= illegal_c_insn; + is_compressed_id_o <= instr_compressed_int; + pc_id_o <= pc_if_o; + is_hwlp_id_q <= fetch_is_hwlp; + is_fetch_failed_o <= 1'b0; + + if (fetch_is_hwlp) + hwlp_dec_cnt_id_o <= hwlp_dec_cnt_if; + + end else if (clear_instr_valid_i) begin + instr_valid_id_o <= 1'b0; + is_fetch_failed_o <= fetch_failed; + end + + end + end + + assign is_hwlp_id_o = is_hwlp_id_q & instr_valid_id_o; + + assign if_ready = valid & id_ready_i; + assign if_valid = (~halt_if_i) & if_ready; + + //---------------------------------------------------------------------------- + // Assertions + //---------------------------------------------------------------------------- + `ifndef VERILATOR + // there should never be a grant when there is no request + assert property ( + @(posedge clk) (instr_gnt_i) |-> (instr_req_o) ) + else $warning("There was a grant without a request"); + `endif +endmodule diff --git a/hw/deps/riscv/riscv_int_controller.sv b/hw/deps/riscv/riscv_int_controller.sv new file mode 100644 index 0000000..b7fea15 --- /dev/null +++ b/hw/deps/riscv/riscv_int_controller.sv @@ -0,0 +1,126 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// // +// Design Name: Interrupt Controller // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Interrupt Controller of the pipelined processor // +// // +//////////////////////////////////////////////////////////////////////////////// + +import riscv_defines::*; + +module riscv_int_controller +#( + parameter PULP_SECURE = 0 +) +( + input logic clk, + input logic rst_n, + + // irq_req for controller + output logic irq_req_ctrl_o, + output logic irq_sec_ctrl_o, + output logic [5:0] irq_id_ctrl_o, + + // handshake signals to controller + input logic ctrl_ack_i, + input logic ctrl_kill_i, + + // external interrupt lines + input logic irq_pending_i, // level-triggered interrupt inputs + input logic irq_sec_i, // interrupt secure bit from EU + input logic [5:0] irq_id_i, // interrupt id [0,1,....31] + + input logic m_IE_i, // interrupt enable bit from CSR (M mode) + input logic u_IE_i, // interrupt enable bit from CSR (U mode) + input PrivLvl_t current_priv_lvl_i + +); + + enum logic [1:0] { IDLE, IRQ_PENDING, IRQ_DONE} exc_ctrl_cs; + + logic irq_enable_ext; + logic [5:0] irq_id_q; + logic irq_sec_q; + +if(PULP_SECURE) + assign irq_enable_ext = ((u_IE_i | irq_sec_i) & current_priv_lvl_i == PRIV_LVL_U) | (m_IE_i & current_priv_lvl_i == PRIV_LVL_M); +else + assign irq_enable_ext = m_IE_i; + + assign irq_req_ctrl_o = exc_ctrl_cs == IRQ_PENDING; + assign irq_sec_ctrl_o = irq_sec_q; + assign irq_id_ctrl_o = irq_id_q; + + always_ff @(posedge clk, negedge rst_n) + begin + if (rst_n == 1'b0) begin + + irq_id_q <= '0; + irq_sec_q <= 1'b0; + exc_ctrl_cs <= IDLE; + + end else begin + + unique case (exc_ctrl_cs) + + IDLE: + begin + if(irq_enable_ext & irq_pending_i) begin + exc_ctrl_cs <= IRQ_PENDING; + irq_id_q <= irq_id_i; + irq_sec_q <= irq_sec_i; + end + end + + IRQ_PENDING: + begin + unique case(1'b1) + ctrl_ack_i: + exc_ctrl_cs <= IRQ_DONE; + ctrl_kill_i: + exc_ctrl_cs <= IDLE; + default: + exc_ctrl_cs <= IRQ_PENDING; + endcase + end + + IRQ_DONE: + begin + irq_sec_q <= 1'b0; + exc_ctrl_cs <= IDLE; + end + + endcase + + end + end + + +`ifndef SYNTHESIS + // synopsys translate_off + // evaluate at falling edge to avoid duplicates during glitches + // Removed this message as it pollutes too much the output and makes tests fail + //always_ff @(negedge clk) + //begin + // if (rst_n && exc_ctrl_cs == IRQ_DONE) + // $display("%t: Entering interrupt service routine. [%m]", $time); + //end + // synopsys translate_on +`endif + +endmodule diff --git a/hw/deps/riscv/riscv_load_store_unit.sv b/hw/deps/riscv/riscv_load_store_unit.sv new file mode 100644 index 0000000..0c387b7 --- /dev/null +++ b/hw/deps/riscv/riscv_load_store_unit.sv @@ -0,0 +1,337 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module riscv_load_store_unit ( + input logic clk_i, + input logic rst_ni, + + // output to data memory + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + input logic data_err_i, + + output logic [31:0] data_addr_o, + output logic data_we_o, + output logic [3:0] data_be_o, + output logic data_buffer_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + + // signals from ex stage + input logic data_we_ex_i, // write enable -> from ex stage + input logic [1:0] data_type_ex_i, // Data type word, halfword, byte -> from ex stage + input logic [31:0] data_wdata_ex_i, // data to write to memory -> from ex stage + input logic [1:0] data_reg_offset_ex_i, // offset inside register for stores -> from ex stage + input logic [1:0] data_sign_ext_ex_i, // sign extension -> from ex stage + + output logic [31:0] data_rdata_ex_o, // requested data -> to ex stage + input logic data_req_ex_i, // data request -> from ex stage + input logic [31:0] operand_a_ex_i, // operand a from RF for address -> from ex stage + input logic [31:0] operand_b_ex_i, // operand b from RF for address -> from ex stage + input logic addr_useincr_ex_i, // use a + b or just a for address -> from ex stage + + input logic data_misaligned_ex_i, // misaligned access in last ld/st -> from ID/EX pipeline + output logic data_misaligned_o, // misaligned access was detected -> to controller + + input logic [5:0] data_atop_ex_i, // atomic instructions signal -> from ex stage + input logic data_buffer_ex_i, + output logic [5:0] data_atop_o, // atomic instruction signal -> core output + + // exception signals + output logic load_err_o, + output logic store_err_o, + + // stall signal + output logic lsu_ready_ex_o, // LSU ready for new data in EX stage + output logic lsu_ready_wb_o, // LSU ready for new data in WB stage + + input logic ex_valid_i, + output logic busy_o +); + + // Calculate shift amount for strobe and data for unaligned accesses. + logic [1:0] shamt; + always_comb begin + shamt = operand_a_ex_i[1:0]; + if (addr_useincr_ex_i) begin + shamt += operand_b_ex_i[1:0]; + end + end + + // Compute byte enable. + always_comb begin + if (data_type_ex_i[1]) begin // writing a single byte + data_be_o = 1'b1; + end else if (data_type_ex_i[0]) begin // writing a half word + data_be_o = 2'b11; + end else begin // writing a full word + data_be_o = 4'b1111; + end + data_be_o <<= shamt; + // Write or read the other part of the word during the second access of an unaligned access. + // FIXME: will not work for 16 bit accesses + if (data_misaligned_ex_i) begin + data_be_o = ~data_be_o; + end + end + + // Latch properties of request to reconstruct response. + logic [3:0] mask_d, mask_q; + logic [1:0] shamt_d, shamt_q; + logic [1:0] type_d, type_q; + logic [1:0] sign_ext_d, sign_ext_q; + logic we_d, we_q; + always_comb begin + mask_d = mask_q; + shamt_d = shamt_q; + sign_ext_d = sign_ext_q; + type_d = type_q; + we_d = we_q; + if (data_req_o && data_gnt_i) begin + mask_d = data_be_o; + shamt_d = shamt; + sign_ext_d = data_sign_ext_ex_i; + type_d = data_type_ex_i; + we_d = data_we_ex_i; + end + end + + // Rotate write data to the left by the shift amount. + always_comb begin + case (shamt) + 2'd0: data_wdata_o = data_wdata_ex_i; + 2'd1: data_wdata_o = {data_wdata_ex_i[23:0], data_wdata_ex_i[31:24]}; + 2'd2: data_wdata_o = {data_wdata_ex_i[15:0], data_wdata_ex_i[31:16]}; + 2'd3: data_wdata_o = {data_wdata_ex_i[ 7:0], data_wdata_ex_i[31: 8]}; + endcase + end + + // Identify responses to misaligned accesses. + enum logic [1:0] { + RespRegular, // response to regular, non-misaligned request + RespMisaligned, // response to first request of a misaligned access -> misaligned response + RespAligned // response to second request of a misaligned access -> aligned response + } resp_state_d, resp_state_q; + always_comb begin + resp_state_d = resp_state_q; + if (data_req_o && data_gnt_i && data_misaligned_o) begin + // When we request misaligned data, the next response is misaligned. + resp_state_d = RespMisaligned; + end else if (data_rvalid_i) begin + // A response to the first request of a misaligned access means the next response is to the + // second request. + resp_state_d = (resp_state_q == RespMisaligned) ? RespAligned : RespRegular; + end + end + + // Reconstruct read data from read response. + logic [31:0] rdata_d, rdata_q; + always_comb begin + rdata_d = rdata_q; + if (data_rvalid_i) begin + // Mask response with byte enable from request. + rdata_d = data_rdata_i & {{8{mask_q[3]}}, {8{mask_q[2]}}, {8{mask_q[1]}}, {8{mask_q[0]}}}; + // Reconstruct misaligned response. + case (resp_state_q) + RespRegular, + RespMisaligned: begin + rdata_d = rdata_d >> 8*shamt_q; + end + RespAligned: begin + rdata_d = (rdata_d << 8*(4 - shamt_q)) | rdata_q; + end + endcase + if (sign_ext_q == 2'b00) begin + // Zero-extend. + if (type_q[1]) begin // single byte + rdata_d = {{24{1'b0}}, rdata_d[ 7:0]}; + end else if (type_q[0]) begin // half word + rdata_d = {{16{1'b0}}, rdata_d[15:0]}; + end + end else if (sign_ext_q == 2'b10) begin + // One-extend. + if (type_q[1]) begin // single byte + rdata_d = {{24{1'b1}}, rdata_d[ 7:0]}; + end else if (type_q[0]) begin // half word + rdata_d = {{16{1'b1}}, rdata_d[15:0]}; + end + end else begin + // Sign-extend. + if (type_q[1]) begin // single byte + rdata_d = {{24{rdata_d[ 7]}}, rdata_d[ 7:0]}; + end else if (type_q[0]) begin // half word + rdata_d = {{16{rdata_d[15]}}, rdata_d[15:0]}; + end + end + end + end + + enum logic [1:0] { + Idle, WaitRValid, WaitRValidExStall, IdleExStall + } state_d, state_q; + + // Main LSU FSM + always_comb begin + state_d = state_q; + data_req_o = 1'b0; + lsu_ready_ex_o = 1'b1; + lsu_ready_wb_o = 1'b1; + + case (state_q) + Idle: begin + // Start here and stay in Idle until request was granted. + data_req_o = data_req_ex_i; + if (data_req_ex_i) begin + lsu_ready_ex_o = 1'b0; + if (data_gnt_i) begin + lsu_ready_ex_o = 1'b1; + if (ex_valid_i) begin + state_d = WaitRValid; + end else begin + state_d = WaitRValidExStall; + end + end + end + end + + WaitRValid: begin + // Wait for rvalid in WB stage and send a new request if there is any. + lsu_ready_wb_o = 1'b0; + if (data_rvalid_i) begin + // We don't have to wait for anything here as we are the only stall source for the WB + // stage. + lsu_ready_wb_o = 1'b1; + data_req_o = data_req_ex_i; + if (data_req_ex_i) begin + lsu_ready_ex_o = 1'b0; + if (data_gnt_i) begin + lsu_ready_ex_o = 1'b1; + if (ex_valid_i) begin + state_d = WaitRValid; + end else begin + state_d = WaitRValidExStall; + end + end else begin + state_d = Idle; + end + end else begin + if (data_rvalid_i) begin + // No request, so go to Idle + state_d = Idle; + end + end + end + end + + WaitRValidExStall: begin + // Wait for rvalid while still in EX stage. We end up here when there was an EX stall, so + // in this cycle we just wait and don't send new requests. + data_req_o = 1'b0; + if (data_rvalid_i) begin + if (ex_valid_i) begin + // We are done and can go back to Idle. The data is safely stored already. + state_d = Idle; + end else begin + // We have to wait until ex_stall is deasserted. + state_d = IdleExStall; + end + end else begin + // We didn't yet receive the rvalid, so we check the ex_stall signal. If we are no longer + // stalled we can change to the "normal" WaitRValid state. + if (ex_valid_i) begin + state_d = WaitRValid; + end + end + end + + IdleExStall: begin + // Wait for us to be unstalled and then change back to Idle state. + if (ex_valid_i) begin + state_d = Idle; + end + end + + default: state_d = Idle; + endcase + end + + // Check for misaligned accesses that need a second memory access. If one is detected, this is + // signaled with data_misaligned_o to the controller, which selectively stalls the pipeline. + always_comb begin + data_misaligned_o = 1'b0; + if (data_req_ex_i && !data_misaligned_ex_i) begin + data_misaligned_o = + (data_type_ex_i == 2'b00 && data_addr_o[1:0] != 2'b00) // misaligned word + || (data_type_ex_i == 2'b01 && data_addr_o[1:0] == 2'b11); // misaligned half word + end + end + + // Generate address from operands. + always_comb begin + data_addr_o = operand_a_ex_i; + if (addr_useincr_ex_i) begin + data_addr_o += operand_b_ex_i; + if (data_misaligned_ex_i) begin + data_addr_o &= 32'hFFFF_FFFC; + end + end + end + + assign busy_o = (state_q == WaitRValid) || (state_q == WaitRValidExStall) + || (state_q == IdleExStall) || (data_req_o); + + // Output to register file + assign data_rdata_ex_o = data_rvalid_i ? rdata_d : rdata_q; + + // Output to data interface + assign data_we_o = data_we_ex_i; + assign data_atop_o = data_atop_ex_i; + assign data_buffer_o = data_buffer_ex_i; + + assign load_err_o = data_gnt_i && data_err_i && ~data_we_o; + assign store_err_o = data_gnt_i && data_err_i && data_we_o; + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + mask_q <= '0; + rdata_q <= '0; + resp_state_q <= RespRegular; + shamt_q <= '0; + sign_ext_q <= '0; + state_q <= Idle; + type_q <= '0; + we_q <= 1'b0; + end else begin + mask_q <= mask_d; + rdata_q <= rdata_d; + resp_state_q <= resp_state_d; + shamt_q <= shamt_d; + sign_ext_q <= sign_ext_d; + state_q <= state_d; + type_q <= type_d; + we_q <= we_d; + end + end + + // Assertions + `ifndef VERILATOR + // Make sure there is no new request when the old one is not yet completely done. + assert property (@(posedge clk_i) state_q == WaitRValid && data_gnt_i |-> data_rvalid_i) + else $warning("It should not be possible to get a grant without an rvalid for the last request!"); + + assert property (@(posedge clk_i) state_q == Idle |-> !data_rvalid_i) + else $warning("There should be no rvalid when the LSU is idle!"); + + // Assert that the address does not contain X when request is sent. + assert property (@(posedge clk_i) data_req_o |-> !$isunknown(data_addr_o)) + else $error("There has been a data request but the address is unknown!"); + `endif +endmodule diff --git a/hw/deps/riscv/riscv_mult.sv b/hw/deps/riscv/riscv_mult.sv new file mode 100644 index 0000000..653392c --- /dev/null +++ b/hw/deps/riscv/riscv_mult.sv @@ -0,0 +1,365 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Matthias Baer - baermatt@student.ethz.ch // +// // +// Additional contributions by: // +// Andreas Traber - atraber@student.ethz.ch // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// // +// Design Name: Subword multiplier and MAC // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Advanced MAC unit for PULP. // +// added parameter SHARED_DSP_MULT to offload dot-product // +// instructions to the shared unit // +// // +//////////////////////////////////////////////////////////////////////////////// + +import riscv_defines::*; + +module riscv_mult +#( + parameter SHARED_DSP_MULT = 1 + ) +( + input logic clk, + input logic rst_n, + + input logic enable_i, + input logic [ 2:0] operator_i, + + // integer and short multiplier + input logic short_subword_i, + input logic [ 1:0] short_signed_i, + + input logic [31:0] op_a_i, + input logic [31:0] op_b_i, + input logic [31:0] op_c_i, + + input logic [ 4:0] imm_i, + + + // dot multiplier + input logic [ 1:0] dot_signed_i, + input logic [31:0] dot_op_a_i, + input logic [31:0] dot_op_b_i, + input logic [31:0] dot_op_c_i, + input logic is_clpx_i, + input logic [ 1:0] clpx_shift_i, + input logic clpx_img_i, + + output logic [31:0] result_o, + + output logic multicycle_o, + output logic ready_o, + input logic ex_ready_i +); + + /////////////////////////////////////////////////////////////// + // ___ _ _ _____ ___ ___ ___ ___ __ __ _ _ _ _____ // + // |_ _| \| |_ _| __/ __| __| _ \ | \/ | | | | ||_ _| // + // | || . | | | | _| (_ | _|| / | |\/| | |_| | |__| | // + // |___|_|\_| |_| |___\___|___|_|_\ |_| |_|\___/|____|_| // + // // + /////////////////////////////////////////////////////////////// + + logic [16:0] short_op_a; + logic [16:0] short_op_b; + logic [32:0] short_op_c; + logic [33:0] short_mul; + logic [33:0] short_mac; + logic [31:0] short_round, short_round_tmp; + logic [33:0] short_result; + + logic short_mac_msb1; + logic short_mac_msb0; + + logic [ 4:0] short_imm; + logic [ 1:0] short_subword; + logic [ 1:0] short_signed; + logic short_shift_arith; + logic [ 4:0] mulh_imm; + logic [ 1:0] mulh_subword; + logic [ 1:0] mulh_signed; + logic mulh_shift_arith; + logic mulh_carry_q; + logic mulh_active; + logic mulh_save; + logic mulh_clearcarry; + logic mulh_ready; + + enum logic [2:0] {IDLE, STEP0, STEP1, STEP2, FINISH} mulh_CS, mulh_NS; + + // prepare the rounding value + assign short_round_tmp = (32'h00000001) << imm_i; + assign short_round = (operator_i == MUL_IR) ? {1'b0, short_round_tmp[31:1]} : '0; + + // perform subword selection and sign extensions + assign short_op_a[15:0] = short_subword[0] ? op_a_i[31:16] : op_a_i[15:0]; + assign short_op_b[15:0] = short_subword[1] ? op_b_i[31:16] : op_b_i[15:0]; + + assign short_op_a[16] = short_signed[0] & short_op_a[15]; + assign short_op_b[16] = short_signed[1] & short_op_b[15]; + + assign short_op_c = mulh_active ? $signed({mulh_carry_q, op_c_i}) : $signed(op_c_i); + + assign short_mul = $signed(short_op_a) * $signed(short_op_b); + assign short_mac = $signed(short_op_c) + $signed(short_mul) + $signed(short_round); + + //we use only short_signed_i[0] as it cannot be short_signed_i[1] 1 and short_signed_i[0] 0 + assign short_result = $signed({short_shift_arith & short_mac_msb1, short_shift_arith & short_mac_msb0, short_mac[31:0]}) >>> short_imm; + + // choose between normal short multiplication operation and mulh operation + assign short_imm = mulh_active ? mulh_imm : imm_i; + assign short_subword = mulh_active ? mulh_subword : {2{short_subword_i}}; + assign short_signed = mulh_active ? mulh_signed : short_signed_i; + assign short_shift_arith = mulh_active ? mulh_shift_arith : short_signed_i[0]; + + assign short_mac_msb1 = mulh_active ? short_mac[33] : short_mac[31]; + assign short_mac_msb0 = mulh_active ? short_mac[32] : short_mac[31]; + + + always_comb + begin + mulh_NS = mulh_CS; + mulh_imm = 5'd0; + mulh_subword = 2'b00; + mulh_signed = 2'b00; + mulh_shift_arith = 1'b0; + mulh_ready = 1'b0; + mulh_active = 1'b1; + mulh_save = 1'b0; + mulh_clearcarry = 1'b0; + multicycle_o = 1'b0; + + case (mulh_CS) + IDLE: begin + mulh_active = 1'b0; + mulh_ready = 1'b1; + mulh_save = 1'b0; + if ((operator_i == MUL_H) && enable_i) begin + mulh_ready = 1'b0; + mulh_NS = STEP0; + end + end + + STEP0: begin + multicycle_o = 1'b1; + mulh_imm = 5'd16; + mulh_active = 1'b1; + //AL*BL never overflows + mulh_save = 1'b0; + mulh_NS = STEP1; + //Here always a 32'b unsigned result (no carry) + end + + STEP1: begin + multicycle_o = 1'b1; + //AL*BH is signed iff B is signed + mulh_signed = {short_signed_i[1], 1'b0}; + mulh_subword = 2'b10; + mulh_save = 1'b1; + mulh_shift_arith = 1'b1; + mulh_NS = STEP2; + //Here signed 32'b + unsigned 32'b result. + //Result is a signed 33'b + //Store the carry as it will be used as sign extension, we do + //not shift + end + + STEP2: begin + multicycle_o = 1'b1; + //AH*BL is signed iff A is signed + mulh_signed = {1'b0, short_signed_i[0]}; + mulh_subword = 2'b01; + mulh_imm = 5'd16; + mulh_save = 1'b1; + mulh_clearcarry = 1'b1; + mulh_shift_arith = 1'b1; + mulh_NS = FINISH; + //Here signed 32'b + signed 33'b result. + //Result is a signed 34'b + //We do not store the carries as the bits 34:33 are shifted back, so we clear it + end + + FINISH: begin + mulh_signed = short_signed_i; + mulh_subword = 2'b11; + mulh_ready = 1'b1; + if (ex_ready_i) + mulh_NS = IDLE; + end + endcase + end + + always_ff @(posedge clk, negedge rst_n) + begin + if (~rst_n) + begin + mulh_CS <= IDLE; + mulh_carry_q <= 1'b0; + end else begin + mulh_CS <= mulh_NS; + + if (mulh_save) + mulh_carry_q <= ~mulh_clearcarry & short_mac[32]; + else if (ex_ready_i) // clear carry when we are going to the next instruction + mulh_carry_q <= 1'b0; + end + end + + // 32x32 = 32-bit multiplier + logic [31:0] int_op_a_msu; + logic [31:0] int_op_b_msu; + logic [31:0] int_result; + + logic int_is_msu; + + assign int_is_msu = (operator_i == MUL_MSU32); // TODO: think about using a separate signal here, could prevent some switching + + assign int_op_a_msu = op_a_i ^ {32{int_is_msu}}; + assign int_op_b_msu = op_b_i & {32{int_is_msu}}; + + assign int_result = $signed(op_c_i) + $signed(int_op_b_msu) + $signed(int_op_a_msu) * $signed(op_b_i); + + /////////////////////////////////////////////// + // ___ ___ _____ __ __ _ _ _ _____ // + // | \ / _ \_ _| | \/ | | | | ||_ _| // + // | |) | (_) || | | |\/| | |_| | |__| | // + // |___/ \___/ |_| |_| |_|\___/|____|_| // + // // + /////////////////////////////////////////////// + + logic [31:0] dot_char_result; + logic [32:0] dot_short_result; + logic [31:0] accumulator; + logic [15:0] clpx_shift_result; + + generate + if (SHARED_DSP_MULT == 0) begin + + logic [3:0][ 8:0] dot_char_op_a; + logic [3:0][ 8:0] dot_char_op_b; + logic [3:0][17:0] dot_char_mul; + + logic [1:0][16:0] dot_short_op_a; + logic [1:0][16:0] dot_short_op_b; + logic [1:0][33:0] dot_short_mul; + logic [16:0] dot_short_op_a_1_neg; //to compute -rA[31:16]*rB[31:16] -> (!rA[31:16] + 1)*rB[31:16] = !rA[31:16]*rB[31:16] + rB[31:16] + logic [31:0] dot_short_op_b_ext; + + assign dot_char_op_a[0] = {dot_signed_i[1] & dot_op_a_i[ 7], dot_op_a_i[ 7: 0]}; + assign dot_char_op_a[1] = {dot_signed_i[1] & dot_op_a_i[15], dot_op_a_i[15: 8]}; + assign dot_char_op_a[2] = {dot_signed_i[1] & dot_op_a_i[23], dot_op_a_i[23:16]}; + assign dot_char_op_a[3] = {dot_signed_i[1] & dot_op_a_i[31], dot_op_a_i[31:24]}; + + assign dot_char_op_b[0] = {dot_signed_i[0] & dot_op_b_i[ 7], dot_op_b_i[ 7: 0]}; + assign dot_char_op_b[1] = {dot_signed_i[0] & dot_op_b_i[15], dot_op_b_i[15: 8]}; + assign dot_char_op_b[2] = {dot_signed_i[0] & dot_op_b_i[23], dot_op_b_i[23:16]}; + assign dot_char_op_b[3] = {dot_signed_i[0] & dot_op_b_i[31], dot_op_b_i[31:24]}; + + assign dot_char_mul[0] = $signed(dot_char_op_a[0]) * $signed(dot_char_op_b[0]); + assign dot_char_mul[1] = $signed(dot_char_op_a[1]) * $signed(dot_char_op_b[1]); + assign dot_char_mul[2] = $signed(dot_char_op_a[2]) * $signed(dot_char_op_b[2]); + assign dot_char_mul[3] = $signed(dot_char_op_a[3]) * $signed(dot_char_op_b[3]); + + assign dot_char_result = $signed(dot_char_mul[0]) + $signed(dot_char_mul[1]) + + $signed(dot_char_mul[2]) + $signed(dot_char_mul[3]) + + $signed(dot_op_c_i); + + + assign dot_short_op_a[0] = {dot_signed_i[1] & dot_op_a_i[15], dot_op_a_i[15: 0]}; + assign dot_short_op_a[1] = {dot_signed_i[1] & dot_op_a_i[31], dot_op_a_i[31:16]}; + assign dot_short_op_a_1_neg = dot_short_op_a[1] ^ {17{(is_clpx_i & ~clpx_img_i)}}; //negates whether clpx_img_i is 0 or 1, only REAL PART needs to be negated + + assign dot_short_op_b[0] = (is_clpx_i & clpx_img_i) ? {dot_signed_i[0] & dot_op_b_i[31], dot_op_b_i[31:16]} : {dot_signed_i[0] & dot_op_b_i[15], dot_op_b_i[15: 0]}; + assign dot_short_op_b[1] = (is_clpx_i & clpx_img_i) ? {dot_signed_i[0] & dot_op_b_i[15], dot_op_b_i[15: 0]} : {dot_signed_i[0] & dot_op_b_i[31], dot_op_b_i[31:16]}; + + assign dot_short_mul[0] = $signed(dot_short_op_a[0]) * $signed(dot_short_op_b[0]); + assign dot_short_mul[1] = $signed(dot_short_op_a_1_neg) * $signed(dot_short_op_b[1]); + + assign dot_short_op_b_ext = $signed(dot_short_op_b[1]); + assign accumulator = is_clpx_i ? dot_short_op_b_ext & {32{~clpx_img_i}} : $signed(dot_op_c_i); + + assign dot_short_result = $signed(dot_short_mul[0][31:0]) + $signed(dot_short_mul[1][31:0]) + $signed(accumulator); + assign clpx_shift_result = $signed(dot_short_result[31:15])>>>clpx_shift_i; + + end else begin + assign dot_char_result = '0; + assign dot_short_result = '0; + end + endgenerate + + //////////////////////////////////////////////////////// + // ____ _ _ __ __ // + // | _ \ ___ ___ _ _| | |_ | \/ |_ ___ __ // + // | |_) / _ \/ __| | | | | __| | |\/| | | | \ \/ / // + // | _ < __/\__ \ |_| | | |_ | | | | |_| |> < // + // |_| \_\___||___/\__,_|_|\__| |_| |_|\__,_/_/\_\ // + // // + //////////////////////////////////////////////////////// + + always_comb + begin + result_o = '0; + + unique case (operator_i) + MUL_MAC32, MUL_MSU32: result_o = int_result[31:0]; + + MUL_I, MUL_IR, MUL_H: result_o = short_result[31:0]; + + MUL_DOT8: result_o = dot_char_result[31:0]; + MUL_DOT16: begin + if(is_clpx_i) begin + if(clpx_img_i) begin + result_o[31:16] = clpx_shift_result; + result_o[15:0] = dot_op_c_i[15:0]; + end else begin + result_o[15:0] = clpx_shift_result; + result_o[31:16] = dot_op_c_i[31:16]; + end + end else begin + result_o = dot_short_result[31:0]; + end + end + + default: ; // default case to suppress unique warning + endcase + end + + assign ready_o = mulh_ready; + + //---------------------------------------------------------------------------- + // Assertions + //---------------------------------------------------------------------------- + + // check multiplication result for mulh + `ifndef VERILATOR + assert property ( + @(posedge clk) ((mulh_CS == FINISH) && (operator_i == MUL_H) && (short_signed_i == 2'b11)) + |-> + (result_o == (($signed({{32{op_a_i[31]}}, op_a_i}) * $signed({{32{op_b_i[31]}}, op_b_i})) >>> 32) ) ); + + // check multiplication result for mulhsu + assert property ( + @(posedge clk) ((mulh_CS == FINISH) && (operator_i == MUL_H) && (short_signed_i == 2'b01)) + |-> + (result_o == (($signed({{32{op_a_i[31]}}, op_a_i}) * {32'b0, op_b_i}) >> 32) ) ); + + // check multiplication result for mulhu + assert property ( + @(posedge clk) ((mulh_CS == FINISH) && (operator_i == MUL_H) && (short_signed_i == 2'b00)) + |-> + (result_o == (({32'b0, op_a_i} * {32'b0, op_b_i}) >> 32) ) ); + `endif +endmodule diff --git a/hw/deps/riscv/riscv_pmp.sv b/hw/deps/riscv/riscv_pmp.sv new file mode 100644 index 0000000..c8622d5 --- /dev/null +++ b/hw/deps/riscv/riscv_pmp.sv @@ -0,0 +1,810 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: BASIC MPU // +// Project Name: RISCV // +// Language: SystemVerilog // +// // +// Description: BASIC MPU: it suppoerts NA4, DIS, NAPOT and TOR // +// NAPOT can be configured from 8B to 4GB // +// Number of RULES is parametric, and TOR and NAPOT can be // +// disabled. // +// // +//////////////////////////////////////////////////////////////////////////////// + + + +`define RULE_0 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxx0 +`define RULE_1 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxx01 +`define RULE_2 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxx011 +`define RULE_3 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_xxxx0111 +`define RULE_4 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_xxx01111 +`define RULE_5 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_xx011111 +`define RULE_6 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_x0111111 +`define RULE_7 32'bxxxxxxxx_xxxxxxxx_xxxxxxxx_01111111 +`define RULE_8 32'bxxxxxxxx_xxxxxxxx_xxxxxxx0_11111111 +`define RULE_9 32'bxxxxxxxx_xxxxxxxx_xxxxxx01_11111111 +`define RULE_10 32'bxxxxxxxx_xxxxxxxx_xxxxx011_11111111 +`define RULE_11 32'bxxxxxxxx_xxxxxxxx_xxxx0111_11111111 +`define RULE_12 32'bxxxxxxxx_xxxxxxxx_xxx01111_11111111 +`define RULE_13 32'bxxxxxxxx_xxxxxxxx_xx011111_11111111 +`define RULE_14 32'bxxxxxxxx_xxxxxxxx_x0111111_11111111 +`define RULE_15 32'bxxxxxxxx_xxxxxxxx_01111111_11111111 +`define RULE_16 32'bxxxxxxxx_xxxxxxx0_11111111_11111111 +`define RULE_17 32'bxxxxxxxx_xxxxxx01_11111111_11111111 +`define RULE_18 32'bxxxxxxxx_xxxxx011_11111111_11111111 +`define RULE_19 32'bxxxxxxxx_xxxx0111_11111111_11111111 +`define RULE_20 32'bxxxxxxxx_xxx01111_11111111_11111111 +`define RULE_21 32'bxxxxxxxx_xx011111_11111111_11111111 +`define RULE_22 32'bxxxxxxxx_x0111111_11111111_11111111 +`define RULE_23 32'bxxxxxxxx_01111111_11111111_11111111 +`define RULE_24 32'bxxxxxxx0_11111111_11111111_11111111 +`define RULE_25 32'bxxxxxx01_11111111_11111111_11111111 +`define RULE_26 32'bxxxxx011_11111111_11111111_11111111 +`define RULE_27 32'bxxxx0111_11111111_11111111_11111111 +`define RULE_28 32'bxxx01111_11111111_11111111_11111111 +`define RULE_29 32'bxx011111_11111111_11111111_11111111 +`define RULE_30 32'bx0111111_11111111_11111111_11111111 +`define RULE_31 32'b01111111_11111111_11111111_11111111 + + + +`define EN_NAPOT_RULE_8B /* 0 */ +`define EN_NAPOT_RULE_16B /* 1 */ +`define EN_NAPOT_RULE_32B /* 2 */ +`define EN_NAPOT_RULE_64B /* 3 */ +`define EN_NAPOT_RULE_128B /* 4 */ +`define EN_NAPOT_RULE_256B /* 5 */ +`define EN_NAPOT_RULE_512B /* 6 */ +`define EN_NAPOT_RULE_1KB /* 7 */ +`define EN_NAPOT_RULE_2KB /* 8 */ +`define EN_NAPOT_RULE_4KB /* 9 */ +`define EN_NAPOT_RULE_8KB /* 10 */ +`define EN_NAPOT_RULE_16KB /* 11 */ +`define EN_NAPOT_RULE_32KB /* 12 */ +`define EN_NAPOT_RULE_64KB /* 13 */ +`define EN_NAPOT_RULE_128KB /* 14 */ +`define EN_NAPOT_RULE_256KB /* 15 */ +`define EN_NAPOT_RULE_512KB /* 16 */ +`define EN_NAPOT_RULE_1MB /* 17 */ +`define EN_NAPOT_RULE_2MB /* 18 */ +`define EN_NAPOT_RULE_4MB /* 19 */ +`define EN_NAPOT_RULE_8MB /* 20 */ +`define EN_NAPOT_RULE_16MB /* 21 */ +`define EN_NAPOT_RULE_32MB /* 22 */ +`define EN_NAPOT_RULE_64MB /* 23 */ +`define EN_NAPOT_RULE_128MB /* 24 */ +`define EN_NAPOT_RULE_256MB /* 25 */ +`define EN_NAPOT_RULE_512MB /* 26 */ +`define EN_NAPOT_RULE_1GB /* 27 */ +`define EN_NAPOT_RULE_2GB /* 28 */ +`define EN_NAPOT_RULE_4GB /* 29 */ +`define EN_NAPOT_RULE_8GB /* 30 */ +`define EN_NAPOT_RULE_16GB /* 31 */ + + +`define ENABLE_NAPOT +`define ENABLE_TOR + +//`define DEBUG_RULE + +import riscv_defines::*; + +module riscv_pmp +#( + parameter N_PMP_ENTRIES = 16 +) +( + input logic clk, + input logic rst_n, + + input PrivLvl_t pmp_privil_mode_i, + + input logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_i, + input logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_i, + + + // data side : if TO pipeline + input logic data_req_i, + input logic [31:0] data_addr_i, + input logic data_we_i, + output logic data_gnt_o, + // if to Memory + output logic data_req_o, + input logic data_gnt_i, + output logic [31:0] data_addr_o, + output logic data_err_o, + input logic data_err_ack_i, + + + // fetch side : if TO pipeline + input logic instr_req_i, + input logic [31:0] instr_addr_i, + output logic instr_gnt_o, + // fetch to PF buffer + output logic instr_req_o, + input logic instr_gnt_i, + output logic [31:0] instr_addr_o, + output logic instr_err_o +); + + + logic [N_PMP_ENTRIES-1:0] EN_rule; + logic [N_PMP_ENTRIES-1:0] R_rule; + logic [N_PMP_ENTRIES-1:0] W_rule; + logic [N_PMP_ENTRIES-1:0] X_rule; + logic [N_PMP_ENTRIES-1:0][1:0] MODE_rule; + logic [N_PMP_ENTRIES-1:0][1:0] WIRI_rule; + logic [N_PMP_ENTRIES-1:0][1:0] LOCK_rule; + logic [N_PMP_ENTRIES-1:0][31:0] mask_addr; + + logic [N_PMP_ENTRIES-1:0][31:0] start_addr; + logic [N_PMP_ENTRIES-1:0][31:0] stop_addr; + logic [N_PMP_ENTRIES-1:0] data_match_region; + logic [N_PMP_ENTRIES-1:0] instr_match_region; + logic data_err_int; + genvar i; + int unsigned j,k; + + + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // ██████╗ ██╗ ██╗██╗ ███████╗ ███████╗██╗ ██╗██████╗ █████╗ ███╗ ██╗███████╗██╗ ██████╗ ███╗ ██╗ // + // ██╔══██╗██║ ██║██║ ██╔════╝ ██╔════╝╚██╗██╔╝██╔══██╗██╔══██╗████╗ ██║██╔════╝██║██╔═══██╗████╗ ██║ // + // ██████╔╝██║ ██║██║ █████╗ █████╗ ╚███╔╝ ██████╔╝███████║██╔██╗ ██║███████╗██║██║ ██║██╔██╗ ██║ // + // ██╔══██╗██║ ██║██║ ██╔══╝ ██╔══╝ ██╔██╗ ██╔═══╝ ██╔══██║██║╚██╗██║╚════██║██║██║ ██║██║╚██╗██║ // + // ██║ ██║╚██████╔╝███████╗███████╗ ███████╗██╔╝ ██╗██║ ██║ ██║██║ ╚████║███████║██║╚██████╔╝██║ ╚████║ // + // ╚═╝ ╚═╝ ╚═════╝ ╚══════╝╚══════╝ ╚══════╝╚═╝ ╚═╝╚═╝ ╚═╝ ╚═╝╚═╝ ╚═══╝╚══════╝╚═╝ ╚═════╝ ╚═╝ ╚═══╝ // + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + generate + for(i=0;i %8h", i , start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end +`endif + + + 2'b10: + begin : NA4_MODE + EN_rule[i] = 1'b1; + stop_addr[i] = pmp_addr_i[i]; + start_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NA4[%d] %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + +`ifdef ENABLE_NAPOT + 2'b11: + begin : NAPOT_MODE + EN_rule[i] = 1'b1; + mask_addr[i] = 32'hFFFF_FFFF; + stop_addr[i] = pmp_addr_i[i]; + start_addr[i] = pmp_addr_i[i]; + + + + casex(pmp_addr_i[i]) + + `ifdef EN_NAPOT_RULE_8B + `RULE_0: + begin: BYTE_ALIGN_8B + mask_addr[i] = 32'hFFFF_FFFE; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_8B: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_16B + `RULE_1: + begin: BYTE_ALIGN_16B + mask_addr[i] = 32'hFFFF_FFFC; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_16B: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_32B + `RULE_2: + begin: BYTE_ALIGN_32B + mask_addr[i] = 32'hFFFF_FFF8; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_32B: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_64B + `RULE_3: + begin: BYTE_ALIGN_64B + mask_addr[i] = 32'hFFFF_FFF0; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_64B: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + + + + `ifdef EN_NAPOT_RULE_128B + `RULE_4: + begin: BYTE_ALIGN_128B + mask_addr[i] = 32'hFFFF_FFE0; + start_addr[i] = pmp_addr_i[i] & 32'hFFFF_FFE0; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_128B: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_256B + `RULE_5: + begin: BYTE_ALIGN_256B + mask_addr[i] = 32'hFFFF_FFC0; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_256B: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_512B + `RULE_6: + begin: BYTE_ALIGN_512B + mask_addr[i] = 32'hFFFF_FF80; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_512B: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_1KB + `RULE_7: + begin: BYTE_ALIGN_1KB + mask_addr[i] = 32'hFFFF_FF00; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_1KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + + + + `ifdef EN_NAPOT_RULE_2KB + `RULE_8: + begin: BYTE_ALIGN_2KB + mask_addr[i] = 32'hFFFF_FE00; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_2K: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_4KB + `RULE_9: + begin: BYTE_ALIGN_4KB + mask_addr[i] = 32'hFFFF_FC00; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_4KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_8KB + `RULE_10: + begin: BYTE_ALIGN_8KB + mask_addr[i] = 32'hFFFF_F800; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_8KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_16KB + `RULE_11: + begin: BYTE_ALIGN_16KB + mask_addr[i] = 32'hFFFF_F000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_16KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + + + + `ifdef EN_NAPOT_RULE_32KB + `RULE_12: + begin: BYTE_ALIGN_32KB + mask_addr[i] = 32'hFFFF_E000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_32KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_64KB + `RULE_13: + begin: BYTE_ALIGN_64KB + mask_addr[i] = 32'hFFFF_C000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_64KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_128KB + `RULE_14: + begin: BYTE_ALIGN_128KB + mask_addr[i] = 32'hFFFF_8000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_128KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_256KB + `RULE_15: + begin: BYTE_ALIGN_256KB + mask_addr[i] = 32'hFFFF_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_256KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + + + + `ifdef EN_NAPOT_RULE_512KB + `RULE_16: + begin: BYTE_ALIGN_512KB + mask_addr[i] = 32'hFFFE_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_512KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_1MB + `RULE_17: + begin: BYTE_ALIGN_1MB + mask_addr[i] = 32'hFFFC_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_1MB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_2MB + `RULE_18: + begin: BYTE_ALIGN_2MB + mask_addr[i] = 32'hFFF8_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_2MB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_4MB + `RULE_19: + begin: BYTE_ALIGN_4MB + mask_addr[i] = 32'hFFF0_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_4MB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + + + `ifdef EN_NAPOT_RULE_8MB + `RULE_20: + begin: BYTE_ALIGN_8MB + mask_addr[i] = 32'hFFE0_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_8MB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_16MB + `RULE_21: + begin: BYTE_ALIGN_16MB + mask_addr[i] = 32'hFFC0_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_16MB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_32MB + `RULE_22: + begin: BYTE_ALIGN_32MB + mask_addr[i] = 32'hFF80_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_32MB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + `ifdef EN_NAPOT_RULE_64MB + `RULE_23: + begin: BYTE_ALIGN_64MB + mask_addr[i] = 32'hFF00_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + `ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_64MB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif + end + `endif + + + + `ifdef EN_NAPOT_RULE_128MB + `RULE_24: + begin: BYTE_ALIGN_128MB + mask_addr[i] = 32'hFE00_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + `ifdef EN_NAPOT_RULE_256MB + `RULE_25: + begin: BYTE_ALIGN_256MB + mask_addr[i] = 32'hFC00_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + `ifdef EN_NAPOT_RULE_512MB + `RULE_26: + begin: BYTE_ALIGN_512MB + mask_addr[i] = 32'hF800_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + `ifdef EN_NAPOT_RULE_1GB + `RULE_27: + begin: BYTE_ALIGN_1GB + mask_addr[i] = 32'hF000_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + + + + `ifdef EN_NAPOT_RULE_2GB + `RULE_28: + begin: BYTE_ALIGN_2GB + mask_addr[i] = 32'hE000_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + + `ifdef EN_NAPOT_RULE_4GB + `RULE_29: + begin: BYTE_ALIGN_4GB + mask_addr[i] = 32'hC000_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + + `ifdef EN_NAPOT_RULE_8GB + `RULE_30: + begin: BYTE_ALIGN_8GB + mask_addr[i] = 32'h8000_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + + `ifdef EN_NAPOT_RULE_16GB + `RULE_31: + begin: BYTE_ALIGN_16GB + mask_addr[i] = 32'h0000_0000; + start_addr[i] = pmp_addr_i[i] & mask_addr[i]; + stop_addr[i] = pmp_addr_i[i]; + end + `endif + default: + begin: INVALID_RULE + EN_rule[i] = 1'b0; + start_addr[i] = '0; + stop_addr[i] = '0; + end + + endcase + + + end +`endif + + default: + begin: DEFAULT_DISABLED + EN_rule[i] = 1'b0; + start_addr[i] = '0; + stop_addr[i] = '0; + end + + endcase + end + end + endgenerate + + + /////////////////////////////////////////////////////////////////////////////////////////////// + // ██████╗ ██╗ ██╗██╗ ███████╗ ██████╗██╗ ██╗███████╗ ██████╗██╗ ██╗███████╗ // + // ██╔══██╗██║ ██║██║ ██╔════╝ ██╔════╝██║ ██║██╔════╝██╔════╝██║ ██╔╝██╔════╝ // + // ██████╔╝██║ ██║██║ █████╗ ██║ ███████║█████╗ ██║ █████╔╝ ███████╗ // + // ██╔══██╗██║ ██║██║ ██╔══╝ ██║ ██╔══██║██╔══╝ ██║ ██╔═██╗ ╚════██║ // + // ██║ ██║╚██████╔╝███████╗███████╗███████╗╚██████╗██║ ██║███████╗╚██████╗██║ ██╗███████║ // + // ╚═╝ ╚═╝ ╚═════╝ ╚══════╝╚══════╝╚══════╝ ╚═════╝╚═╝ ╚═╝╚══════╝ ╚═════╝╚═╝ ╚═╝╚══════╝ // + /////////////////////////////////////////////////////////////////////////////////////////////// + + + + + always_comb + begin + for(j=0;j= start_addr[j]) && ( data_addr_i[31:2] < stop_addr[j]) ) + begin + data_match_region[j] = 1'b1; + `ifdef DEBUG_RULE $display("HIT on TOR RULE %d: [%8h] <= data_addr_i [%8h] <= [%8h], RULE=%2h, X=%b, W=%b, R=%d", j, (start_addr[j])>>2 , data_addr_i , (stop_addr[j])>>2, pmp_cfg_i[j][4:3], X_rule[j], W_rule[j], R_rule[j]); `endif + end + else + begin + data_match_region[j] = 1'b0; + end + end + `endif + + 2'b10: + begin : NA4_CHECK_DATA + if ( data_addr_i[31:2] == start_addr[j][29:0] ) + begin + data_match_region[j] = 1'b1; + `ifdef DEBUG_RULE $display("HIT on NA4 RULE %d: [%8h] == [%8h] , RULE=%2h, X=%b, W=%b, R=%d", j, (start_addr[j])>>2 , data_addr_i , pmp_cfg_i[j][4:3], X_rule[j], W_rule[j], R_rule[j]); `endif + end + else + begin + data_match_region[j] = 1'b0; + end + end + + `ifdef ENABLE_NAPOT + 2'b11: + begin : NAPOT_CHECK_DATA + //$display("Checking NAPOT RULE [%d]: %8h, == %8h", j, data_addr_i[31:2] & mask_addr[j][29:0], start_addr[j][29:0]); + if ( (data_addr_i[31:2] & mask_addr[j][31:2]) == start_addr[j][31:2] ) + begin + data_match_region[j] = 1'b1; + end + else + begin + data_match_region[j] = 1'b0; + //$display("NO MACHING NAPOT: %8h, == %8h", (data_addr_i[31:2] & mask_addr[j][29:0]), start_addr[j][29:0]); + end + end + `endif + + default: + begin + data_match_region[j] = 1'b0; + end + endcase // MODE_rule[j] + + end + else + begin + data_match_region[j] = 1'b0; + end + + end + end + + assign data_addr_o = data_addr_i; + + always_comb + begin + if(pmp_privil_mode_i == PRIV_LVL_M) + begin + data_req_o = data_req_i; + data_gnt_o = data_gnt_i; + data_err_int = 1'b0; + + end + else + begin + if(|data_match_region == 1'b0) + begin + data_req_o = 1'b0; + data_err_int = data_req_i; + data_gnt_o = 1'b0; + end + else + begin + data_req_o = data_req_i; + data_err_int = 1'b0; + data_gnt_o = data_gnt_i; + end + end + end + + + enum logic {IDLE, GIVE_ERROR} data_err_state_q, data_err_state_n; + + always_comb + begin + data_err_o = 1'b0; + data_err_state_n = data_err_state_q; + unique case(data_err_state_q) + + IDLE: + begin + if(data_err_int) + data_err_state_n = GIVE_ERROR; + end + + GIVE_ERROR: + begin + data_err_o = 1'b1; + if(data_err_ack_i) + data_err_state_n = IDLE; + end + + default: ; + endcase + end + + + always_ff @(posedge clk or negedge rst_n) begin + if(~rst_n) begin + data_err_state_q <= IDLE; + end else begin + data_err_state_q <= data_err_state_n; + end + end + + + always_comb + begin + for(k=0;k= start_addr[k]) && ( instr_addr_i[31:2] < stop_addr[k]) ) + begin + instr_match_region[k] = 1'b1; + `ifdef DEBUG_RULE $display("HIT on TOR RULE %d: [%8h] <= data_addr_i [%8h] <= [%8h], RULE=%2h, X=%b, W=%b, R=%d", k, (start_addr[k])>>2 , data_addr_i , (stop_addr[k])>>2, pmp_cfg_i[k][4:3], X_rule[k], W_rule[k], R_rule[k]); `endif + end + else + begin + instr_match_region[k] = 1'b0; + end + end + `endif + + 2'b10: + begin : NA4_CHECK + if ( instr_addr_i[31:2] == start_addr[k][29:0] ) + begin + instr_match_region[k] = 1'b1; + `ifdef DEBUG_RULE $display("HIT on NA4 RULE %d: [%8h] == [%8h] , RULE=%2h, X=%b, W=%b, R=%d", k, (start_addr[k])>>2 , data_addr_i , pmp_cfg_i[k][4:3], X_rule[k], W_rule[k], R_rule[k]); `endif + end + else + begin + instr_match_region[k] = 1'b0; + end + end + + `ifdef ENABLE_NAPOT + 2'b11: + begin + if ( (instr_addr_i[31:2] & mask_addr[k][31:2]) == start_addr[k][31:2] ) + begin + instr_match_region[k] = 1'b1; + end + else + begin + instr_match_region[k] = 1'b0; + end + end + `endif + + default: + begin + instr_match_region[k] = 1'b0; + end + endcase // MODE_rule[i] + +/* if ( ( instr_addr_i[31:2] >= start_addr[k]) && ( instr_addr_i[31:2] <= stop_addr[k]) ) + begin + instr_match_region[k] = 1'b1; + end + else + begin + instr_match_region[k] = 1'b0; + end*/ + end + else + begin + instr_match_region[k] = 1'b0; + end + + + end + end + + assign instr_addr_o = instr_addr_i; + + always_comb + begin + if(pmp_privil_mode_i == PRIV_LVL_M) + begin + instr_req_o = instr_req_i; + instr_gnt_o = instr_gnt_i; + instr_err_o = 1'b0; + + end + else + begin + if(|instr_match_region == 1'b0) + begin + instr_req_o = 1'b0; + instr_err_o = instr_req_i; + instr_gnt_o = 1'b0; + end + else + begin + instr_req_o = instr_req_i; + instr_err_o = 1'b0; + instr_gnt_o = instr_gnt_i; + end + end + end + + +endmodule diff --git a/hw/deps/riscv/riscv_popcnt.sv b/hw/deps/riscv/riscv_popcnt.sv new file mode 100644 index 0000000..69c7ee6 --- /dev/null +++ b/hw/deps/riscv/riscv_popcnt.sv @@ -0,0 +1,63 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Andreas Traber - atraber@student.ethz.ch // +// // +// Additional contributions by: // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// // +// Design Name: riscv_popcnt // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Count the number of '1's in a word // +// // +//////////////////////////////////////////////////////////////////////////////// + +module riscv_popcnt +( + input logic [31:0] in_i, + output logic [5: 0] result_o +); + + logic [15:0][1:0] cnt_l1; + logic [ 7:0][2:0] cnt_l2; + logic [ 3:0][3:0] cnt_l3; + logic [ 1:0][4:0] cnt_l4; + + genvar l, m, n, p; + generate for(l = 0; l < 16; l++) + begin + assign cnt_l1[l] = {1'b0, in_i[2*l]} + {1'b0, in_i[2*l + 1]}; + end + endgenerate + + generate for(m = 0; m < 8; m++) + begin + assign cnt_l2[m] = {1'b0, cnt_l1[2*m]} + {1'b0, cnt_l1[2*m + 1]}; + end + endgenerate + + generate for(n = 0; n < 4; n++) + begin + assign cnt_l3[n] = {1'b0, cnt_l2[2*n]} + {1'b0, cnt_l2[2*n + 1]}; + end + endgenerate + + generate for(p = 0; p < 2; p++) + begin + assign cnt_l4[p] = {1'b0, cnt_l3[2*p]} + {1'b0, cnt_l3[2*p + 1]}; + end + endgenerate + + assign result_o = {1'b0, cnt_l4[0]} + {1'b0, cnt_l4[1]}; + +endmodule diff --git a/hw/deps/riscv/riscv_prefetch_L0_buffer.sv b/hw/deps/riscv/riscv_prefetch_L0_buffer.sv new file mode 100644 index 0000000..b2f2f44 --- /dev/null +++ b/hw/deps/riscv/riscv_prefetch_L0_buffer.sv @@ -0,0 +1,579 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Igor Loi - igor.loi@unibo.it // +// // +// Additional contributions by: // +// Andreas Traber - atraber@iis.ee.ethz.ch // +// // +// Design Name: Prefetcher Buffer for 128 bit memory interface // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Prefetch Buffer that caches instructions. This cuts overly // +// long critical paths to the instruction cache // +// // +//////////////////////////////////////////////////////////////////////////////// + +module riscv_prefetch_L0_buffer +#( + parameter RDATA_IN_WIDTH = 128 +) +( + input logic clk, + input logic rst_n, + + input logic req_i, + + input logic branch_i, + input logic [31:0] addr_i, + + input logic hwloop_i, + input logic [31:0] hwloop_target_i, + + input logic ready_i, + output logic valid_o, + output logic [31:0] rdata_o, + output logic [31:0] addr_o, + output logic is_hwlp_o, // is set when the currently served data is from a hwloop + + // goes to instruction memory / instruction cache + output logic instr_req_o, + output logic [31:0] instr_addr_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + input logic [RDATA_IN_WIDTH/32-1:0][31:0] instr_rdata_i, + + // Prefetch Buffer Status + output logic busy_o +); + + logic busy_L0; + + enum logic [3:0] { IDLE, BRANCHED, + HWLP_WAIT_GNT, HWLP_GRANTED, HWLP_GRANTED_WAIT, HWLP_FETCH_DONE, + NOT_VALID, NOT_VALID_GRANTED, NOT_VALID_CROSS, NOT_VALID_CROSS_GRANTED, + VALID, VALID_CROSS, VALID_GRANTED, VALID_FETCH_DONE } CS, NS; + + logic do_fetch; + logic do_hwlp, do_hwlp_int; + logic use_last; + logic save_rdata_last; + logic use_hwlp; + logic save_rdata_hwlp; + logic valid; + + logic hwlp_is_crossword; + logic is_crossword; + logic next_is_crossword; + logic next_valid; + logic next_upper_compressed; + logic fetch_possible; + logic upper_is_compressed; + + logic [31:0] addr_q, addr_n, addr_int, addr_aligned_next, addr_real_next; + logic is_hwlp_q, is_hwlp_n; + + logic [31:0] rdata_last_q; + + logic valid_L0; + logic [RDATA_IN_WIDTH/32-1:0][31:0] rdata_L0; + logic [31:0] addr_L0; + + logic fetch_valid; + logic fetch_gnt; + + // prepared data for output + logic [31:0] rdata, rdata_unaligned; + + logic aligned_is_compressed, unaligned_is_compressed; + logic hwlp_aligned_is_compressed, hwlp_unaligned_is_compressed; + + + riscv_L0_buffer + #( + .RDATA_IN_WIDTH ( RDATA_IN_WIDTH ) + ) + L0_buffer_i + ( + .clk ( clk ), + .rst_n ( rst_n ), + + .prefetch_i ( do_fetch ), + .prefetch_addr_i ( addr_real_next ), //addr_aligned_next + + .branch_i ( branch_i ), + .branch_addr_i ( addr_i ), + + .hwlp_i ( do_hwlp | do_hwlp_int ), + .hwlp_addr_i ( hwloop_target_i ), + + .fetch_gnt_o ( fetch_gnt ), + .fetch_valid_o ( fetch_valid ), + + .valid_o ( valid_L0 ), + .rdata_o ( rdata_L0 ), + .addr_o ( addr_L0 ), + + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + + .busy_o ( busy_L0 ) + ); + + + assign rdata = (use_last || use_hwlp) ? rdata_last_q : rdata_L0[addr_o[3:2]]; + + // the lower part of rdata_unaligned is always the higher part of rdata + assign rdata_unaligned[15:0] = rdata[31:16]; + + always_comb + begin + // rdata_unaligned[31:16] = '0; Not Needed + + case(addr_o[3:2]) + 2'b00: begin rdata_unaligned[31:16] = rdata_L0[1][15:0]; end + 2'b01: begin rdata_unaligned[31:16] = rdata_L0[2][15:0]; end + 2'b10: begin rdata_unaligned[31:16] = rdata_L0[3][15:0]; end + 2'b11: begin rdata_unaligned[31:16] = rdata_L0[0][15:0]; end + endcase // addr_o + end + + + assign unaligned_is_compressed = rdata[17:16] != 2'b11; + assign aligned_is_compressed = rdata[1:0] != 2'b11; + assign upper_is_compressed = rdata_L0[3][17:16] != 2'b11; + assign is_crossword = (addr_o[3:1] == 3'b111) && (~upper_is_compressed); + assign next_is_crossword = ((addr_o[3:1] == 3'b110) && (aligned_is_compressed) && (~upper_is_compressed)) || ((addr_o[3:1] == 3'b101) && (~unaligned_is_compressed) && (~upper_is_compressed)); + assign next_upper_compressed = ((addr_o[3:1] == 3'b110) && (aligned_is_compressed) && upper_is_compressed) || ((addr_o[3:1] == 3'b101) && (~unaligned_is_compressed) && upper_is_compressed); + assign next_valid = ((addr_o[3:2] != 2'b11) || next_upper_compressed) && (~next_is_crossword) && valid; + + //addr_o[3:2] == 2'b11;// ((addr_o[3:1] == 3'b101) & (~upper_is_compressed)) | addr_o[3:2] == 2'b11; // + assign fetch_possible = (addr_o[3:2] == 2'b11 ); + + assign addr_aligned_next = { addr_o[31:2], 2'b00 } + 32'h4; + assign addr_real_next = (next_is_crossword) ? { addr_o[31:4], 4'b0000 } + 32'h16 : { addr_o[31:2], 2'b00 } + 32'h4; + + assign hwlp_unaligned_is_compressed = rdata_L0[2][17:16] != 2'b11; + assign hwlp_aligned_is_compressed = rdata_L0[3][1:0] != 2'b11; + assign hwlp_is_crossword = (hwloop_target_i[3:1] == 3'b111) && (~upper_is_compressed); + + always_comb + begin + addr_int = addr_o; + + // advance address when pipeline is unstalled + if (ready_i) begin + + if (addr_o[1]) begin + // unaligned case + // always move to next entry in the FIFO + + if (unaligned_is_compressed) begin + addr_int = { addr_aligned_next[31:2], 2'b00}; + end else begin + addr_int = { addr_aligned_next[31:2], 2'b10}; + end + + end else begin + // aligned case + + if (aligned_is_compressed) begin + // just increase address, do not move to next entry in the FIFO + addr_int = { addr_o[31:2], 2'b10 }; + end else begin + // move to next entry in the FIFO + addr_int = { addr_aligned_next[31:2], 2'b00 }; + end + end + + end + end + + always_comb + begin + NS = CS; + do_fetch = 1'b0; + do_hwlp = 1'b0; + do_hwlp_int = 1'b0; + use_last = 1'b0; + use_hwlp = 1'b0; + save_rdata_last = 1'b0; + save_rdata_hwlp = 1'b0; + valid = 1'b0; + addr_n = addr_int; + is_hwlp_n = is_hwlp_q; + + if (ready_i) + is_hwlp_n = 1'b0; + + case (CS) + IDLE: begin + // wait here for something to happen + end + + BRANCHED: begin + valid = 1'b0; + do_fetch = fetch_possible; + + if (fetch_valid && (~is_crossword)) + valid = 1'b1; + + if (ready_i) begin + if (hwloop_i) begin + addr_n = addr_o; // keep the old address for now + NS = HWLP_WAIT_GNT; + end else begin + if (next_valid) begin + if (fetch_gnt) begin + save_rdata_last = 1'b1; + NS = VALID_GRANTED; + end else + NS = VALID; + end else if (next_is_crossword) begin + if (fetch_gnt) begin + save_rdata_last = 1'b1; + NS = NOT_VALID_CROSS_GRANTED; + end else begin + NS = NOT_VALID_CROSS; + end + end else begin + if (fetch_gnt) + NS = NOT_VALID_GRANTED; + else + NS = NOT_VALID; + end + end + end else begin + if (fetch_valid) begin + if (is_crossword) begin + save_rdata_last = 1'b1; + if (fetch_gnt) + NS = NOT_VALID_CROSS_GRANTED; + else + NS = NOT_VALID_CROSS; + end else begin + if (fetch_gnt) begin + save_rdata_last = 1'b1; + NS = VALID_GRANTED; + end else + NS = VALID; + end + end + end + end + + NOT_VALID: begin + do_fetch = 1'b1; + + if (fetch_gnt) + NS = NOT_VALID_GRANTED; + end + + NOT_VALID_GRANTED: begin + valid = fetch_valid; + do_hwlp = hwloop_i; + + if (fetch_valid) + NS = VALID; + end + + NOT_VALID_CROSS: + begin + do_fetch = 1'b1; + + if (fetch_gnt) + begin + save_rdata_last = 1'b1; + NS = NOT_VALID_CROSS_GRANTED; + end + end + + NOT_VALID_CROSS_GRANTED: + begin + valid = fetch_valid; + use_last = 1'b1; + do_hwlp = hwloop_i; + + if (fetch_valid) + begin + if (ready_i) + NS = VALID; + else + NS = VALID_CROSS; + end + end + + VALID: begin + valid = 1'b1; + do_fetch = fetch_possible; // fetch_possible = addr_o[3:2] == 2'b11;// + do_hwlp = hwloop_i; + + if (ready_i) + begin + if (next_is_crossword) + begin + do_fetch = 1'b1; + + if (fetch_gnt) + begin + save_rdata_last = 1'b1; + NS = NOT_VALID_CROSS_GRANTED; + end + else // not fetching + begin + NS = NOT_VALID_CROSS; + end + end + else // Next is not crossword + if (~next_valid) + begin + if (fetch_gnt) + NS = NOT_VALID_GRANTED; + else + NS = NOT_VALID; + end + else // Next is valid + begin + if (fetch_gnt) + begin + if (next_upper_compressed) + begin + save_rdata_last = 1'b1; + NS = VALID_GRANTED; + end + end + end + end + else // NOT ready + begin + if (fetch_gnt) + begin + save_rdata_last = 1'b1; + NS = VALID_GRANTED; + end + end + end + + VALID_CROSS: begin + valid = 1'b1; + use_last = 1'b1; + do_hwlp = hwloop_i; + + if (ready_i) + NS = VALID; + end + + VALID_GRANTED: begin + valid = 1'b1; + use_last = 1'b1; + do_hwlp = hwloop_i; + + if (ready_i) begin + if (fetch_valid) begin + if (next_is_crossword) + NS = VALID_CROSS; + else if(next_upper_compressed) + NS = VALID_FETCH_DONE; + else + NS = VALID; + end else begin + if (next_is_crossword) + NS = NOT_VALID_CROSS_GRANTED; + else if (next_upper_compressed) + NS = VALID_GRANTED; + else + NS = NOT_VALID_GRANTED; + end + end else begin + if (fetch_valid) + NS = VALID_FETCH_DONE; + end + end + + VALID_FETCH_DONE: begin + valid = 1'b1; + use_last = 1'b1; + do_hwlp = hwloop_i; + + if (ready_i) begin + if (next_is_crossword) + NS = VALID_CROSS; + else if (next_upper_compressed) + NS = VALID_FETCH_DONE; + else + NS = VALID; + end + end + + HWLP_WAIT_GNT: begin + do_hwlp_int = 1'b1; + + if (fetch_gnt) begin + is_hwlp_n = 1'b1; + addr_n = hwloop_target_i; + NS = BRANCHED; + end + end + + HWLP_GRANTED: begin + valid = 1'b1; + use_hwlp = 1'b1; + + if (ready_i) begin + addr_n = hwloop_target_i; + + if (fetch_valid) begin + is_hwlp_n = 1'b1; + + if (hwlp_is_crossword) begin + NS = NOT_VALID_CROSS; + end else begin + NS = VALID; + end + end else begin + NS = HWLP_GRANTED_WAIT; + end + end else begin + if (fetch_valid) + NS = HWLP_FETCH_DONE; + end + end + + HWLP_GRANTED_WAIT: begin + use_hwlp = 1'b1; + + if (fetch_valid) begin + is_hwlp_n = 1'b1; + + if ( (addr_L0[3:1] == 3'b111) && (~upper_is_compressed)) begin + NS = NOT_VALID_CROSS; + end else begin + NS = VALID; + end + end + end + + HWLP_FETCH_DONE: begin + valid = 1'b1; + use_hwlp = 1'b1; + + if (ready_i) begin + is_hwlp_n = 1'b1; + addr_n = hwloop_target_i; + + if (hwlp_is_crossword) begin + NS = NOT_VALID_CROSS; + end else begin + NS = VALID; + end + end + end + endcase + + // branches always have priority + if (branch_i) begin + is_hwlp_n = 1'b0; + addr_n = addr_i; + NS = BRANCHED; + + end else if (hwloop_i) begin + if (do_hwlp) begin + if (ready_i) begin + if (fetch_gnt) begin + is_hwlp_n = 1'b1; + addr_n = hwloop_target_i; + NS = BRANCHED; + end else begin + addr_n = addr_o; // keep the old address for now + NS = HWLP_WAIT_GNT; + end + end else begin + if (fetch_gnt) begin + save_rdata_hwlp = 1'b1; + NS = HWLP_GRANTED; + end + end + end + end + end + + + ////////////////////////////////////////////////////////////////////////////// + // registers + ////////////////////////////////////////////////////////////////////////////// + + always_ff @(posedge clk, negedge rst_n) + begin + if (~rst_n) + begin + addr_q <= '0; + is_hwlp_q <= 1'b0; + CS <= IDLE; + rdata_last_q <= '0; + end + else + begin + addr_q <= addr_n; + is_hwlp_q <= is_hwlp_n; + + CS <= NS; + + if (save_rdata_hwlp) + rdata_last_q <= rdata_o; + else if(save_rdata_last) + begin + //rdata_last_q <= rdata_L0[3]; + if(ready_i) + begin + rdata_last_q <= rdata_L0[3];//rdata; + end + else + begin + rdata_last_q <= rdata;//rdata; + end + end + end + end + + ////////////////////////////////////////////////////////////////////////////// + // output ports + ////////////////////////////////////////////////////////////////////////////// + + assign rdata_o = ((~addr_o[1]) || use_hwlp) ? rdata : rdata_unaligned; + assign valid_o = valid & (~branch_i); + + assign addr_o = addr_q; + + assign is_hwlp_o = is_hwlp_q & (~branch_i); + + assign busy_o = busy_L0; + + + //---------------------------------------------------------------------------- + // Assertions + //---------------------------------------------------------------------------- + `ifndef VERILATOR + // there should never be a ready_i without valid_o + assert property ( + @(posedge clk) (ready_i) |-> (valid_o) ) else $warning("IF Stage is ready without prefetcher having valid data"); + + // never is_crossword while also next_is_crossword + assert property ( + @(posedge clk) (next_is_crossword) |-> (~is_crossword) ) else $warning("Cannot have two crossword accesses back-to-back"); + assert property ( + @(posedge clk) (is_crossword) |-> (~next_is_crossword) ) else $warning("Cannot have two crossword accesses back-to-back"); + `endif +endmodule // prefetch_L0_buffer + diff --git a/hw/deps/riscv/riscv_register_file.sv b/hw/deps/riscv/riscv_register_file.sv new file mode 100644 index 0000000..24881fc --- /dev/null +++ b/hw/deps/riscv/riscv_register_file.sv @@ -0,0 +1,189 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Francesco Conti - f.conti@unibo.it // +// // +// Additional contributions by: // +// Michael Gautschi - gautschi@iis.ee.ethz.ch // +// // +// Design Name: RISC-V register file // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Register file with 31x 32 bit wide registers. Register 0 // +// is fixed to 0. This register file is based on flip-flops. // +// Also supports the fp-register file now if FPU=1 // +// // +//////////////////////////////////////////////////////////////////////////////// + +module riscv_register_file +#( + parameter ADDR_WIDTH = 5, + parameter DATA_WIDTH = 32, + parameter FPU = 0 +) +( + // Clock and Reset + input logic clk, + input logic rst_n, + + input logic test_en_i, + + input logic fregfile_disable_i, + + //Read port R1 + input logic [ADDR_WIDTH-1:0] raddr_a_i, + output logic [DATA_WIDTH-1:0] rdata_a_o, + + //Read port R2 + input logic [ADDR_WIDTH-1:0] raddr_b_i, + output logic [DATA_WIDTH-1:0] rdata_b_o, + + //Read port R3 + input logic [ADDR_WIDTH-1:0] raddr_c_i, + output logic [DATA_WIDTH-1:0] rdata_c_o, + + // Write port W1 + input logic [ADDR_WIDTH-1:0] waddr_a_i, + input logic [DATA_WIDTH-1:0] wdata_a_i, + input logic we_a_i, + + // Write port W2 + input logic [ADDR_WIDTH-1:0] waddr_b_i, + input logic [DATA_WIDTH-1:0] wdata_b_i, + input logic we_b_i +); + + // number of integer registers + localparam NUM_WORDS = 2**(ADDR_WIDTH-1); + // number of floating point registers + localparam NUM_FP_WORDS = 2**(ADDR_WIDTH-1); + localparam NUM_TOT_WORDS = FPU ? NUM_WORDS + NUM_FP_WORDS : NUM_WORDS; + + // integer register file + logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] mem; + + // fp register file + logic [NUM_FP_WORDS-1:0][DATA_WIDTH-1:0] mem_fp; + + // mask bit for fpregfile selection (top bit of address) + logic fregfile_ena; + + // masked write addresses + logic [ADDR_WIDTH-1:0] waddr_a; + logic [ADDR_WIDTH-1:0] waddr_b; + + // write enable signals for all registers + logic [NUM_TOT_WORDS-1:0] we_a_dec; + logic [NUM_TOT_WORDS-1:0] we_b_dec; + + + //----------------------------------------------------------------------------- + //-- FPU Register file enable: + //-- Taken from Cluster Config Reg if FPU reg file exists, or always enabled (safe default) + //----------------------------------------------------------------------------- + assign fregfile_ena = FPU ? ~fregfile_disable_i : '1; + + + //----------------------------------------------------------------------------- + //-- READ : Read address decoder RAD + //----------------------------------------------------------------------------- + if (FPU == 1) begin + assign rdata_a_o = (fregfile_ena & raddr_a_i[5]) ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]]; + assign rdata_b_o = (fregfile_ena & raddr_b_i[5]) ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]]; + assign rdata_c_o = (fregfile_ena & raddr_c_i[5]) ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]]; + end else begin + assign rdata_a_o = mem[raddr_a_i[4:0]]; + assign rdata_b_o = mem[raddr_b_i[4:0]]; + assign rdata_c_o = mem[raddr_c_i[4:0]]; + end + + //----------------------------------------------------------------------------- + //-- WRITE : Write Address Decoder (WAD), combinatorial process + //----------------------------------------------------------------------------- + + // Mask top bit of write address to disable fp regfile + assign waddr_a = {(fregfile_ena & waddr_a_i[5]), waddr_a_i[4:0]}; + assign waddr_b = {(fregfile_ena & waddr_b_i[5]), waddr_b_i[4:0]}; + + always_comb + begin : we_a_decoder + for (int i = 0; i < NUM_TOT_WORDS; i++) begin + if (waddr_a == i) + we_a_dec[i] = we_a_i; + else + we_a_dec[i] = 1'b0; + end + end + + always_comb + begin : we_b_decoder + for (int i=0; i 0) else $fatal(1, "Address width must be non-zero!"); + assert (DataWidth > 0) else $fatal(1, "Data width must be non-zero!"); + assert (Depth > 0) else $fatal(1, "Depth must be non-zero!"); + end + `endif + // pragma translate_on + +endmodule diff --git a/hw/deps/riscv/riscv_tracer.sv b/hw/deps/riscv/riscv_tracer.sv new file mode 100644 index 0000000..087c452 --- /dev/null +++ b/hw/deps/riscv/riscv_tracer.sv @@ -0,0 +1,1192 @@ +// Copyright (c) 2019-2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// Davide Schiavone - pschiavo@iis.ee.ethz.ch // +// Salvatore Di Girolamo - digirols@inf.ethz.ch // +// // +// Design Name: RISC-V Tracer // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Traces the executed instructions // +// // +//////////////////////////////////////////////////////////////////////////////// + +import riscv_defines::*; +import riscv_tracer_defines::*; + +// Source/Destination register instruction index +`define REG_S1 19:15 +`define REG_S2 24:20 +`define REG_S3 29:25 +`define REG_S4 31:27 +`define REG_D 11:07 + +module riscv_tracer ( + // Clock and Reset + input logic clk, + input logic rst_n, + + input logic fetch_enable, + input logic [31:0] hart_id_i, + + input logic [31:0] pc, + input logic [31:0] instr, + input ctrl_state_e controller_state_i, + + input logic compressed, + input logic id_valid, + input logic is_decoding, + input logic pipe_flush, + input logic mret, + input logic uret, + input logic dret, + input logic ecall, + input logic ebreak, + input logic fence, + + input logic [31:0] rs1_value, + input logic [31:0] rs2_value, + input logic [31:0] rs3_value, + + input logic [31:0] rs2_value_vec, + + input logic rd_is_fp, + input logic rs1_is_fp, + input logic rs2_is_fp, + input logic rs3_is_fp, + + input logic ex_valid, + input logic [ 5:0] ex_reg_addr, + input logic ex_reg_we, + input logic [31:0] ex_reg_wdata, + + input logic ex_data_req, + input logic ex_data_gnt, + input logic ex_data_we, + input logic [31:0] ex_data_addr, + input logic [31:0] ex_data_wdata, + input logic data_misaligned, + + input logic wb_bypass, + + input logic wb_valid, + input logic [ 5:0] wb_reg_addr, + input logic wb_reg_we, + input logic [31:0] wb_reg_wdata, + + input logic [31:0] imm_u_type, + input logic [31:0] imm_uj_type, + input logic [31:0] imm_i_type, + input logic [11:0] imm_iz_type, + input logic [31:0] imm_z_type, + input logic [31:0] imm_s_type, + input logic [31:0] imm_sb_type, + input logic [31:0] imm_s2_type, + input logic [31:0] imm_s3_type, + input logic [31:0] imm_vs_type, + input logic [31:0] imm_vu_type, + input logic [31:0] imm_shuffle_type, + input logic [ 4:0] imm_clip_type +); + + `define ADDREG(REQ_QUEUE, R, ADDR, VAL) R.addr = ADDR; R.value = VAL; REQ_QUEUE.push_back(R); + + typedef enum logic [1:0] {Init, Running} state_t; + + typedef struct packed { + logic [ 5:0] addr; + logic [31:0] value; + } reg_t; + + typedef struct packed { + logic [31:0] addr; + logic we; + logic [ 3:0] be; + logic [31:0] wdata; + logic [31:0] rdata; + } mem_acc_t; + + class instr_trace_t; + time simtime; + integer cycles; + logic [31:0] pc; + logic [31:0] instr; + reg_t regs_read[$]; + reg_t regs_write[$]; + mem_acc_t mem_access[$]; + logic run_ex; + string str; + + function new(); + str = ""; + endfunction + + endclass + + integer f; + string fn; + integer cycles; + logic [5:0] rd, rs1, rs2, rs3, rs4; + + state_t state; + + // TODO: this is super ugly but verilator currently does not + // support complex data types as function argurments. :-( + instr_trace_t current_instr; + + instr_trace_t instr_ex[$]; + instr_trace_t instr_wb[$]; + instr_trace_t instr_ex_misaligned[$]; + instr_trace_t to_print[$]; + + assign rd = {rd_is_fp, instr[`REG_D]}; + assign rs1 = {rs1_is_fp, instr[`REG_S1]}; + assign rs2 = {rs2_is_fp, instr[`REG_S2]}; + assign rs3 = {rs3_is_fp, instr[`REG_S3]}; + assign rs4 = {rs3_is_fp, instr[`REG_S4]}; + + function void printMnemonic(input string mnemonic); + begin + current_instr.str = mnemonic; + end + endfunction // printMnemonic + + function void printRInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2); + end + endfunction // printRInstr + + function void printAddNInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, x%0d, 0x%0d", mnemonic, rd, rs1, rs2, $unsigned(imm_s3_type[4:0])); + end + endfunction // printAddNInstr + + function void printR1Instr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d", mnemonic, rd, rs1); + end + endfunction // printR1Instr + + function void printR3Instr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rd, rs3_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2); + end + endfunction // printR3Instr + + function void printF3Instr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs4, rs3_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s f%0d, f%0d, f%0d, f%0d", mnemonic, rd-32, rs1-32, rs2-32, rs4-32); + end + endfunction // printF3Instr + + function void printF2Instr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s f%0d, f%0d, f%0d", mnemonic, rd-32, rs1-32, rs2-32); + end + endfunction // printF2Instr + + function void printF2IInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, f%0d, f%0d", mnemonic, rd, rs1-32, rs2-32); + end + endfunction // printF2IInstr + + function void printFInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s f%0d, f%0d", mnemonic, rd-32, rs1-32); + end + endfunction // printFInstr + + function void printFIInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, f%0d", mnemonic, rd, rs1-32); + end + endfunction // printFIInstr + + function void printIFInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s f%0d, x%0d", mnemonic, rd-32, rs1); + end + endfunction // printIFInstr + + function void printClipInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $unsigned(imm_clip_type)); + end + endfunction // printClipInstr + + function void printIInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed(imm_i_type)); + end + endfunction // printIInstr + + function void printIuInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, imm_i_type); + end + endfunction // printIuInstr + + function void printUInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type[31:12], 12'h000}); + end + endfunction // printUInstr + + function void printUJInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed(imm_uj_type)); + end + endfunction // printUJInstr + + function void printSBInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + current_instr.str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed(imm_sb_type)); + end + endfunction // printSBInstr + + function void printSBallInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s x%0d, %0d", mnemonic, rs1, $signed(imm_sb_type)); + end + endfunction // printSBallInstr + + function void printCSRInstr(input string mnemonic); + logic [11:0] csr; + reg_t r; + begin + csr = instr[31:20]; + + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + + if (instr[14] == 1'b0) begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, rd, rs1, csr); + end else begin + current_instr.str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, imm_z_type, csr); + end + end + endfunction // printCSRInstr + + function void printBit1Instr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, %0d, %0d", mnemonic, rd, rs1, imm_s3_type, imm_s2_type); + end + endfunction // printBit1Instr + + function void printBitRevInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, %0d, %0d", mnemonic, rd, rs1, imm_s2_type, imm_s3_type); + end + endfunction // printBitRevInstr + + function void printBit2Instr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rd, rs3_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + current_instr.str = $sformatf("%-16s x%0d, x%0d, %0d, %0d", mnemonic, rd, rs1, imm_s3_type, imm_s2_type); + end + endfunction // printBit2Instr + + function void printAtomicInstr(input string mnemonic); + reg_t r; + begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + if (instr[31:27] == AMO_LR) begin + // Do not print rs2 for load-reserved + current_instr.str = $sformatf("%-16s x%0d, (x%0d)", mnemonic, rd, rs1); + end else begin + current_instr.str = $sformatf("%-16s x%0d, x%0d, (x%0d)", mnemonic, rd, rs2, rs1); + end + end + endfunction // printAtomicInstr + + function void printStoreBuffInstr(); + string mnemonic; + reg_t r; + begin + + case (instr[13:12]) + 2'b00: mnemonic = "bsb"; + 2'b01: mnemonic = "bsh"; + 2'b10: mnemonic = "bsw"; + 2'b11: begin + printMnemonic("INVALID"); + return; + end + endcase + + if (instr[14] == 1'b0) begin + // regular store + if (instr[6:0] != OPCODE_STORE_POST_BUF) begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type), rs1); + end else begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rs1, 32'hDEADBEEF); + current_instr.str = $sformatf("p.%-14s x%0d, %0d(x%0d!)", mnemonic, rs2, $signed(imm_s_type), rs1); + end + end else begin + // reg-reg store + if (instr[6:0] != OPCODE_STORE_POST_BUF) begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs3, rs3_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("p.%-14s x%0d, x%0d(x%0d)", mnemonic, rs2, rs3, rs1); + end else begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs3, rs3_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rs1, 32'hDEADBEEF); + current_instr.str = $sformatf("p.%-14s x%0d, x%0d(x%0d!)", mnemonic, rs2, rs3, rs1); + end + end + end + endfunction // printStoreBuffInstr + + function void printStoreInstr(); + string mnemonic; + reg_t r; + begin + + case (instr[13:12]) + 2'b00: mnemonic = "sb"; + 2'b01: mnemonic = "sh"; + 2'b10: mnemonic = "sw"; + 2'b11: begin + printMnemonic("INVALID"); + return; + end + endcase + + if (instr[14] == 1'b0) begin + // regular store + if (instr[6:0] != OPCODE_STORE_POST) begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type), rs1); + end else begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rs1, 32'hDEADBEEF); + current_instr.str = $sformatf("p.%-14s x%0d, %0d(x%0d!)", mnemonic, rs2, $signed(imm_s_type), rs1); + end + end else begin + // reg-reg store + if (instr[6:0] != OPCODE_STORE_POST) begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs3, rs3_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("p.%-14s x%0d, x%0d(x%0d)", mnemonic, rs2, rs3, rs1); + end else begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs3, rs3_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rs1, 32'hDEADBEEF); + current_instr.str = $sformatf("p.%-14s x%0d, x%0d(x%0d!)", mnemonic, rs2, rs3, rs1); + end + end + end + endfunction // printStoreInstr + + function void printHwloopInstr(); + string mnemonic; + reg_t r; + begin + // set mnemonic + case (instr[14:12]) + 3'b000: mnemonic = "lp.starti"; + 3'b001: mnemonic = "lp.endi"; + 3'b010: mnemonic = "lp.count"; + 3'b011: mnemonic = "lp.counti"; + 3'b100: mnemonic = "lp.setup"; + 3'b101: mnemonic = "lp.setupi"; + 3'b111: begin + printMnemonic("INVALID"); + return; + end + endcase + + // decode and print instruction + case (instr[14:12]) + // lp.starti and lp.endi + 3'b000, + 3'b001: current_instr.str = $sformatf("%-16s 0x%0d, 0x%0h", mnemonic, rd, imm_iz_type); + // lp.count + 3'b010: begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s 0x%0d, x%0d", mnemonic, rd, rs1); + end + // lp.counti + 3'b011: current_instr.str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, imm_iz_type); + // lp.setup + 3'b100: begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s 0x%0d, x%0d, 0x%0h", mnemonic, rd, rs1, imm_iz_type); + end + // lp.setupi + 3'b101: begin + current_instr.str = $sformatf("%-16s 0x%0d, 0x%0h, 0x%0h", mnemonic, rd, imm_iz_type, rs1); + end + endcase + end + endfunction // printHwloopInstr + + function void printLoadInstr(); + string mnemonic; + logic [2:0] size; + reg_t r; + begin + // detect reg-reg load and find size + size = instr[14:12]; + if (instr[14:12] == 3'b111) + size = instr[30:28]; + + case (size) + 3'b000: mnemonic = "lb"; + 3'b001: mnemonic = "lh"; + 3'b010: mnemonic = "lw"; + 3'b100: mnemonic = "lbu"; + 3'b101: mnemonic = "lhu"; + 3'b110: mnemonic = "p.elw"; + 3'b011, + 3'b111: begin + printMnemonic("INVALID"); + return; + end + endcase + + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + + if (instr[14:12] != 3'b111) begin + // regular load + if (instr[6:0] != OPCODE_LOAD_POST) begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type), rs1); + end else begin + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rs1, 32'hDEADBEEF); + current_instr.str = $sformatf("p.%-14s x%0d, %0d(x%0d!)", mnemonic, rd, $signed(imm_i_type), rs1); + end + end else begin + // reg-reg load + if (instr[6:0] != OPCODE_LOAD_POST) begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + current_instr.str = $sformatf("%-16s x%0d, x%0d(x%0d)", mnemonic, rd, rs2, rs1); + end else begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rs1, 32'hDEADBEEF); + current_instr.str = $sformatf("p.%-14s x%0d, x%0d(x%0d!)", mnemonic, rd, rs2, rs1); + end + end + end + endfunction //printLoadInstr + + function void printMulInstr(); + string mnemonic; + string str_suf; + string str_imm; + string str_asm; + reg_t r; + begin + + // always read rs1 and rs2 and write rd + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + + if (instr[12]) begin + `ADDREG(current_instr.regs_read, r, rd, rs3_value); + end + + case ({instr[31:30], instr[14]}) + 3'b000: str_suf = "u"; + 3'b001: str_suf = "uR"; + 3'b010: str_suf = "hhu"; + 3'b011: str_suf = "hhuR"; + 3'b100: str_suf = "s"; + 3'b101: str_suf = "sR"; + 3'b110: str_suf = "hhs"; + 3'b111: str_suf = "hhsR"; + endcase + + if (instr[12]) + mnemonic = "p.mac"; + else + mnemonic = "p.mul"; + + if (imm_s3_type[4:0] != 5'b00000) + str_asm = $sformatf("%s%sN", mnemonic, str_suf); + else + str_asm = $sformatf("%s%s", mnemonic, str_suf); + + if (instr[29:25] != 5'b00000) + current_instr.str = $sformatf("%-16s x%0d, x%0d, x%0d, %0d", str_asm, rd, rs1, rs2, $unsigned(imm_s3_type[4:0])); + else + current_instr.str = $sformatf("%-16s x%0d, x%0d, x%0d", str_asm, rd, rs1, rs2); + end + endfunction // printMulInstr + + function void printVecInstr(); + string mnemonic; + string str_asm; + string str_args; + string str_hb; + string str_sci; + string str_imm; + reg_t r; + begin + + // always read rs1 and write rd + `ADDREG(current_instr.regs_read, r, rs1, rs1_value); + `ADDREG(current_instr.regs_write, r, rd, 32'hDEADBEEF); + + case (instr[14:13]) + 2'b00: str_sci = ""; + 2'b10: str_sci = ".sc"; + 2'b11: str_sci = ".sci"; + endcase + + if (instr[12]) + str_hb = ".b"; + else + str_hb = ".h"; + + // set mnemonic + case (instr[31:26]) + 6'b000000: begin mnemonic = "pv.add"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b000010: begin mnemonic = "pv.sub"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b000100: begin mnemonic = "pv.avg"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b000110: begin mnemonic = "pv.avgu"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b001000: begin mnemonic = "pv.min"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b001010: begin mnemonic = "pv.minu"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b001100: begin mnemonic = "pv.max"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b001110: begin mnemonic = "pv.maxu"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b010000: begin mnemonic = "pv.srl"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b010010: begin mnemonic = "pv.sra"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b010100: begin mnemonic = "pv.sll"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b010110: begin mnemonic = "pv.or"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b011000: begin mnemonic = "pv.xor"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b011010: begin mnemonic = "pv.and"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b011100: begin mnemonic = "pv.abs"; str_imm = $sformatf("0x%0d", imm_vs_type); end + + 6'b011110: begin mnemonic = "pv.extract"; str_imm = $sformatf("0x%0d", imm_vs_type); str_sci = ""; end + 6'b100100: begin mnemonic = "pv.extractu"; str_imm = $sformatf("0x%0d", imm_vu_type); str_sci = ""; end + 6'b101100: begin mnemonic = "pv.insert"; str_imm = $sformatf("0x%0d", imm_vs_type); end + + // shuffle/pack + 6'b110000: begin + if (instr[14:12] == 3'b001) begin + mnemonic = "pv.shuffle"; + end else begin + mnemonic = "pv.shufflei0"; + str_imm = $sformatf("0x%0d", imm_shuffle_type); + end + end + 6'b111010: begin mnemonic = "pv.shufflei1"; str_imm = $sformatf("0x%0d", imm_shuffle_type); end + 6'b111100: begin mnemonic = "pv.shufflei2"; str_imm = $sformatf("0x%0d", imm_shuffle_type); end + 6'b111110: begin mnemonic = "pv.shufflei3"; str_imm = $sformatf("0x%0d", imm_shuffle_type); end + + 6'b110010: begin mnemonic = "pv.shuffle2"; end + + 6'b110100: begin mnemonic = instr[25] ? "pv.pack.h" : "pv.pack"; end + 6'b110110: begin mnemonic = "pv.packhi"; end + 6'b111000: begin mnemonic = "pv.packlo"; end + + // comparisons + 6'b000001: begin mnemonic = "pv.cmpeq"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b000011: begin mnemonic = "pv.cmpne"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b000101: begin mnemonic = "pv.cmpgt"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b000111: begin mnemonic = "pv.cmpge"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b001001: begin mnemonic = "pv.cmplt"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b001011: begin mnemonic = "pv.cmple"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b001101: begin mnemonic = "pv.cmpgtu"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b001111: begin mnemonic = "pv.cmpgeu"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b010001: begin mnemonic = "pv.cmpltu"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b010011: begin mnemonic = "pv.cmpleu"; str_imm = $sformatf("0x%0d", imm_vu_type); end + + // dotproducts + 6'b100000: begin mnemonic = "pv.dotup"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b100010: begin mnemonic = "pv.dotusp"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b100110: begin mnemonic = "pv.dotsp"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b101000: begin mnemonic = "pv.sdotup"; str_imm = $sformatf("0x%0d", imm_vu_type); end + 6'b101010: begin mnemonic = "pv.sdotusp"; str_imm = $sformatf("0x%0d", imm_vs_type); end + 6'b101110: begin mnemonic = "pv.sdotsp"; str_imm = $sformatf("0x%0d", imm_vs_type); end + + 6'b010101: begin + unique case (instr[14:13]) + 2'b00: mnemonic = instr[25] ? "pv.clpxmul.r" : "pv.clpxmul.i"; + 2'b01: mnemonic = instr[25] ? "pv.clpxmul.r.div2" : "pv.clpxmul.i.div2"; + 2'b10: mnemonic = instr[25] ? "pv.clpxmul.r.div4" : "pv.clpxmul.i.div4"; + 2'b11: mnemonic = instr[25] ? "pv.clpxmul.r.div8" : "pv.clpxmul.i.div8"; + endcase + str_sci = ""; + end + + 6'b011011: begin + unique case (instr[14:13]) + 2'b00: mnemonic = "pv.subrotmj"; + 2'b01: mnemonic = "pv.subrotmj.div2"; + 2'b10: mnemonic = "pv.subrotmj.div4"; + 2'b11: mnemonic = "pv.subrotmj.div8"; + endcase + str_sci = ""; + end + + 6'b010111: begin mnemonic = "pv.cplxconj"; end + + 6'b011101: begin + unique case (instr[14:13]) + 2'b01: mnemonic = "pv.add.div2"; + 2'b10: mnemonic = "pv.add.div4"; + 2'b11: mnemonic = "pv.add.div8"; + endcase + str_sci = ""; + end + + 6'b011001: begin + unique case (instr[14:13]) + 2'b01: mnemonic = "pv.sub.div2"; + 2'b10: mnemonic = "pv.sub.div4"; + 2'b11: mnemonic = "pv.sub.div8"; + endcase + str_sci = ""; + end + + default: begin + printMnemonic("INVALID"); + return; + end + endcase + + if (str_sci == "") begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value); + str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2); + end else if (str_sci == ".sc") begin + `ADDREG(current_instr.regs_read, r, rs2, rs2_value_vec); + str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2); + end else if (str_sci == ".sci") begin + str_args = $sformatf("x%0d, x%0d, %s", rd, rs1, str_imm); + end + + str_asm = $sformatf("%s%s%s", mnemonic, str_sci, str_hb); + + current_instr.str = $sformatf("%-16s %s", str_asm, str_args); + end + endfunction // printVecInstr + + + function string regAddrToStr(input logic [5:0] addr); + begin + // TODO: use this function to also format the arguments to the + // instructions + if (SymbolicRegs) begin // format according to RISC-V ABI + if (addr >= 42) + return $sformatf(" f%0d", addr-32); + else if (addr > 32) + return $sformatf(" f%0d", addr-32); + else begin + if (addr == 0) + return $sformatf("zero"); + else if (addr == 1) + return $sformatf(" ra"); + else if (addr == 2) + return $sformatf(" sp"); + else if (addr == 3) + return $sformatf(" gp"); + else if (addr == 4) + return $sformatf(" tp"); + else if (addr >= 5 && addr <= 7) + return $sformatf(" t%0d", addr-5); + else if (addr >= 8 && addr <= 9) + return $sformatf(" s%0d", addr-8); + else if (addr >= 10 && addr <= 17) + return $sformatf(" a%0d", addr-10); + else if (addr >= 18 && addr <= 25) + return $sformatf(" s%0d", addr-16); + else if (addr >= 26 && addr <= 27) + return $sformatf(" s%0d", addr-16); + else if (addr >= 28 && addr <= 31) + return $sformatf(" t%0d", addr-25); + else + return $sformatf("UNKNOWN %0d", addr); + end + end else begin + if (addr >= 42) + return $sformatf("f%0d", addr-32); + else if (addr > 32) + return $sformatf(" f%0d", addr-32); + else if (addr < 10) + return $sformatf(" x%0d", addr); + else + return $sformatf("x%0d", addr); + end + end + endfunction + + function void printInstrTrace(); + instr_trace_t trace; + mem_acc_t mem_acc; + if (to_print.size() > 0) begin + trace = to_print.pop_front(); + + $fwrite(f, "%21d %15d %h %h %-36s", trace.simtime, + trace.cycles, + trace.pc, + trace.instr, + trace.str); + + foreach(trace.regs_write[i]) begin + if (trace.regs_write[i].addr != 0) + $fwrite(f, " %s=%08x", regAddrToStr(trace.regs_write[i].addr), trace.regs_write[i].value); + end + + foreach(trace.regs_read[i]) begin + if (trace.regs_read[i].addr != 0) + $fwrite(f, " %s:%08x", regAddrToStr(trace.regs_read[i].addr), trace.regs_read[i].value); + end + + if (trace.mem_access.size() > 0) begin + mem_acc = trace.mem_access.pop_front(); + + $fwrite(f, " PA:%08x", mem_acc.addr); + end + + $fwrite(f, "\n"); + $fflush(); + + end + endfunction + + + function void progressID(); + + // special case for WFI because we don't wait for unstalling there + if ( (id_valid || pipe_flush || mret || uret || ecall || ebreak || dret || fence) && is_decoding) + begin + current_instr = new (); + + current_instr.simtime = $time; + current_instr.cycles = cycles; + current_instr.pc = pc; + current_instr.instr = instr; + current_instr.run_ex = 0; + //$display("LOG: %08x time: %0d \n", current_instr.pc, cycles); + + // use casex instead of case inside due to ModelSim bug + casex (instr) + // Aliases + 32'h00_00_00_13: printMnemonic("nop"); + // Regular opcodes + INSTR_LUI: printUInstr("lui"); + INSTR_AUIPC: printUInstr("auipc"); + INSTR_JAL: printUJInstr("jal"); + INSTR_JALR: printIInstr("jalr"); + // BRANCH + INSTR_BEQ: printSBInstr("beq"); + INSTR_BNE: printSBInstr("bne"); + INSTR_BLT: printSBInstr("blt"); + INSTR_BGE: printSBInstr("bge"); + INSTR_BLTU: printSBInstr("bltu"); + INSTR_BGEU: printSBInstr("bgeu"); + INSTR_BEQIMM: printSBallInstr("p.beqimm"); + INSTR_BNEIMM: printSBallInstr("p.bneimm"); + // OPIMM + INSTR_ADDI: printIInstr("addi"); + INSTR_SLTI: printIInstr("slti"); + INSTR_SLTIU: printIInstr("sltiu"); + INSTR_XORI: printIInstr("xori"); + INSTR_ORI: printIInstr("ori"); + INSTR_ANDI: printIInstr("andi"); + INSTR_SLLI: printIuInstr("slli"); + INSTR_SRLI: printIuInstr("srli"); + INSTR_SRAI: printIuInstr("srai"); + // OP + INSTR_ADD: printRInstr("add"); + INSTR_SUB: printRInstr("sub"); + INSTR_SLL: printRInstr("sll"); + INSTR_SLT: printRInstr("slt"); + INSTR_SLTU: printRInstr("sltu"); + INSTR_XOR: printRInstr("xor"); + INSTR_SRL: printRInstr("srl"); + INSTR_SRA: printRInstr("sra"); + INSTR_OR: printRInstr("or"); + INSTR_AND: printRInstr("and"); + INSTR_EXTHS: printRInstr("p.exths"); + INSTR_EXTHZ: printRInstr("p.exthz"); + INSTR_EXTBS: printRInstr("p.extbs"); + INSTR_EXTBZ: printRInstr("p.extbz"); + INSTR_PAVG: printRInstr("p.avg"); + INSTR_PAVGU: printRInstr("p.avgu"); + + INSTR_PADDN: printAddNInstr("p.addN"); + INSTR_PADDUN: printAddNInstr("p.adduN"); + INSTR_PADDRN: printAddNInstr("p.addRN"); + INSTR_PADDURN: printAddNInstr("p.adduRN"); + INSTR_PSUBN: printAddNInstr("p.subN"); + INSTR_PSUBUN: printAddNInstr("p.subuN"); + INSTR_PSUBRN: printAddNInstr("p.subRN"); + INSTR_PSUBURN: printAddNInstr("p.subuRN"); + + INSTR_PADDNR: printR3Instr("p.addNr"); + INSTR_PADDUNR: printR3Instr("p.adduNr"); + INSTR_PADDRNR: printR3Instr("p.addRNr"); + INSTR_PADDURNR: printR3Instr("p.adduRNr"); + INSTR_PSUBNR: printR3Instr("p.subNr"); + INSTR_PSUBUNR: printR3Instr("p.subuNr"); + INSTR_PSUBRNR: printR3Instr("p.subRNr"); + INSTR_PSUBURNR: printR3Instr("p.subuRNr"); + + INSTR_PSLET: printRInstr("p.slet"); + INSTR_PSLETU: printRInstr("p.sletu"); + INSTR_PMIN: printRInstr("p.min"); + INSTR_PMINU: printRInstr("p.minu"); + INSTR_PMAX: printRInstr("p.max"); + INSTR_PMAXU: printRInstr("p.maxu"); + INSTR_PABS: printR1Instr("p.abs"); + INSTR_PCLIP: printClipInstr("p.clip"); + INSTR_PCLIPU: printClipInstr("p.clipu"); + INSTR_PBEXT: printBit1Instr("p.extract"); + INSTR_PBEXTU: printBit1Instr("p.extractu"); + INSTR_PBINS: printBit2Instr("p.insert"); + INSTR_PBCLR: printBit1Instr("p.bclr"); + INSTR_PBSET: printBit1Instr("p.bset"); + INSTR_PBREV: printBitRevInstr("p.bitrev"); + + INSTR_PCLIPR: printRInstr("p.clipr"); + INSTR_PCLIPUR: printRInstr("p.clipur"); + INSTR_PBEXTR: printRInstr("p.extractr"); + INSTR_PBEXTUR: printRInstr("p.extractur"); + INSTR_PBINSR: printR3Instr("p.insertr"); + INSTR_PBCLRR: printRInstr("p.bclrr"); + INSTR_PBSETR: printRInstr("p.bsetr"); + + INSTR_FF1: printR1Instr("p.ff1"); + INSTR_FL1: printR1Instr("p.fl1"); + INSTR_CLB: printR1Instr("p.clb"); + INSTR_CNT: printR1Instr("p.cnt"); + INSTR_ROR: printRInstr("p.ror"); + + // FENCE + INSTR_FENCE: printMnemonic("fence"); + INSTR_FENCEI: printMnemonic("fencei"); + // SYSTEM (CSR manipulation) + INSTR_CSRRW: printCSRInstr("csrrw"); + INSTR_CSRRS: printCSRInstr("csrrs"); + INSTR_CSRRC: printCSRInstr("csrrc"); + INSTR_CSRRWI: printCSRInstr("csrrwi"); + INSTR_CSRRSI: printCSRInstr("csrrsi"); + INSTR_CSRRCI: printCSRInstr("csrrci"); + // SYSTEM (others) + INSTR_ECALL: printMnemonic("ecall"); + INSTR_EBREAK: printMnemonic("ebreak"); + INSTR_URET: printMnemonic("uret"); + INSTR_MRET: printMnemonic("mret"); + INSTR_WFI: printMnemonic("wfi"); + + INSTR_DRET: printMnemonic("dret"); + + // RV32M + INSTR_PMUL: printRInstr("mul"); + INSTR_PMUH: printRInstr("mulh"); + INSTR_PMULHSU: printRInstr("mulhsu"); + INSTR_PMULHU: printRInstr("mulhu"); + INSTR_DIV: printRInstr("div"); + INSTR_DIVU: printRInstr("divu"); + INSTR_REM: printRInstr("rem"); + INSTR_REMU: printRInstr("remu"); + // PULP MULTIPLIER + INSTR_PMAC: printR3Instr("p.mac"); + INSTR_PMSU: printR3Instr("p.msu"); + INSTR_PMULS : printMulInstr(); + INSTR_PMULHLSN : printMulInstr(); + INSTR_PMULRS : printMulInstr(); + INSTR_PMULRHLSN : printMulInstr(); + INSTR_PMULU : printMulInstr(); + INSTR_PMULUHLU : printMulInstr(); + INSTR_PMULRU : printMulInstr(); + INSTR_PMULRUHLU : printMulInstr(); + INSTR_PMACS : printMulInstr(); + INSTR_PMACHLSN : printMulInstr(); + INSTR_PMACRS : printMulInstr(); + INSTR_PMACRHLSN : printMulInstr(); + INSTR_PMACU : printMulInstr(); + INSTR_PMACUHLU : printMulInstr(); + INSTR_PMACRU : printMulInstr(); + INSTR_PMACRUHLU : printMulInstr(); + + // FP-OP + INSTR_FMADD: printF3Instr("fmadd.s"); + INSTR_FMSUB: printF3Instr("fmsub.s"); + INSTR_FNMADD: printF3Instr("fnmadd.s"); + INSTR_FNMSUB: printF3Instr("fnmsub.s"); + INSTR_FADD: printF2Instr("fadd.s"); + INSTR_FSUB: printF2Instr("fsub.s"); + INSTR_FMUL: printF2Instr("fmul.s"); + INSTR_FDIV: printF2Instr("fdiv.s"); + INSTR_FSQRT: printFInstr("fsqrt.s"); + INSTR_FSGNJS: printF2Instr("fsgnj.s"); + INSTR_FSGNJNS: printF2Instr("fsgnjn.s"); + INSTR_FSGNJXS: printF2Instr("fsgnjx.s"); + INSTR_FMIN: printF2Instr("fmin.s"); + INSTR_FMAX: printF2Instr("fmax.s"); + INSTR_FCVTWS: printFIInstr("fcvt.w.s"); + INSTR_FCVTWUS: printFIInstr("fcvt.wu.s"); + INSTR_FMVXS: printFIInstr("fmv.x.s"); + INSTR_FEQS: printF2IInstr("feq.s"); + INSTR_FLTS: printF2IInstr("flt.s"); + INSTR_FLES: printF2IInstr("fle.s"); + INSTR_FCLASS: printFIInstr("fclass.s"); + INSTR_FCVTSW: printIFInstr("fcvt.s.w"); + INSTR_FCVTSWU: printIFInstr("fcvt.s.wu"); + INSTR_FMVSX: printIFInstr("fmv.s.x"); + + // RV32A + INSTR_LR: printAtomicInstr("lr.w"); + INSTR_SC: printAtomicInstr("sc.w"); + INSTR_AMOSWAP: printAtomicInstr("amoswap.w"); + INSTR_AMOADD: printAtomicInstr("amoadd.w"); + INSTR_AMOXOR: printAtomicInstr("amoxor.w"); + INSTR_AMOAND: printAtomicInstr("amoand.w"); + INSTR_AMOOR: printAtomicInstr("amoor.w"); + INSTR_AMOMIN: printAtomicInstr("amomin.w"); + INSTR_AMOMAX: printAtomicInstr("amomax.w"); + INSTR_AMOMINU: printAtomicInstr("amominu.w"); + INSTR_AMOMAXU: printAtomicInstr("amomaxu.w"); + + // opcodes with custom decoding + {25'b?, OPCODE_LOAD}: printLoadInstr(); + {25'b?, OPCODE_LOAD_FP}: printLoadInstr(); + {25'b?, OPCODE_LOAD_POST}: printLoadInstr(); + {25'b?, OPCODE_STORE}: printStoreInstr(); + {25'b?, OPCODE_STORE_FP}: printStoreInstr(); + {25'b?, OPCODE_STORE_POST}: printStoreInstr(); + {25'b?, OPCODE_STORE_BUF}: printStoreBuffInstr(); + {25'b?, OPCODE_STORE_POST_BUF}: printStoreBuffInstr(); + {25'b?, OPCODE_HWLOOP}: printHwloopInstr(); + {25'b?, OPCODE_VECOP}: printVecInstr(); + default: printMnemonic("INVALID"); + endcase // unique case (instr) + + instr_ex.push_back(current_instr); + end + endfunction + + function void progressEX(); + instr_trace_t trace; + instr_trace_t trace_pop; + mem_acc_t mem_acc; + + if (instr_ex.size() > 0) begin + trace = instr_ex.pop_front(); + + //$display("EX: %08x time: %0d \n", trace.pc, cycles); + + foreach(trace.regs_write[i]) begin + if ((trace.regs_write[i].addr == ex_reg_addr) && ex_reg_we) begin + trace.regs_write[i].value = ex_reg_wdata; + end + end + + if (ex_data_req && ex_data_gnt) begin + mem_acc.addr = ex_data_addr; + mem_acc.we = ex_data_we; + + if (mem_acc.we) begin + mem_acc.wdata = ex_data_wdata; + end else begin + mem_acc.wdata = 32'hDEADBEEF; + end + + trace.mem_access.push_back(mem_acc); + end + + if (ex_valid || wb_bypass) begin + if(ex_data_req && data_misaligned) begin + instr_ex_misaligned.push_back(trace); + end else begin + instr_wb.push_back(trace); + end + + // NOTE: verilator seems to not like pop_front as standalone (i.e., without assignment) statement. + //trace_pop = instr_ex.pop_front(); + end else begin + // NOTE: we don't have a front() method (?) and instr_ex[0] has not queue semantic. Verilator + // maps queue operations to std::deque, so pushing/popping have O(1) complexity + instr_ex.push_front(trace); + end + end + endfunction + + function void progressEXMisaligned(); + instr_trace_t trace; + instr_trace_t trace_pop; + + if (instr_ex_misaligned.size() > 0) begin + trace = instr_ex_misaligned.pop_front(); + //$display("EXM: %08x time: %0d \n", trace.pc, cycles); + if (ex_valid || wb_bypass) begin + instr_wb.push_back(trace); + // NOTE: verilator seems to not like pop_front as standalone (i.e., without assignment) statement. + //trace_pop = instr_ex_misaligned.pop_front(); + end else begin + instr_ex_misaligned.push_front(trace); + end + end + endfunction + + function void progressWB(); + instr_trace_t trace; + instr_trace_t trace_pop; + if (instr_wb.size() > 0) begin + trace = instr_wb.pop_front(); + foreach(trace.regs_write[i]) begin + //$display("WB: %0d; wb_reg_addr: %08x; wb_reg_wdata: %08x\n", trace.instr, wb_reg_addr, wb_reg_wdata); + //$display("WB: %08x time: %0d \n", trace.pc, cycles); + + if ((trace.regs_write[i].addr == wb_reg_addr) && wb_reg_we) begin + trace.regs_write[i].value = wb_reg_wdata; + end + end + + if (wb_valid) begin + to_print.push_back(trace); + // NOTE: verilator seems to not like pop_front as standalone (i.e., without assignment) statement. + //trace_pop = instr_wb.pop_front(); + end else begin + instr_wb.push_front(trace); + end + end + endfunction + + // cycle counter + always_ff @(posedge clk, negedge rst_n) + begin + if (rst_n == 1'b0) + cycles <= 0; + else + cycles <= cycles + 1; + end + + always_ff @(posedge clk, negedge rst_n) begin + if (rst_n == 1'b0) begin + state <= Init; + f = 0; + end else begin + state <= Running; + if (f == 0) begin + $sformat(fn, "trace_core_%h_%h.log", hart_id_i[10:5], hart_id_i[3:0]); + // $display("[TRACER] Output filename is: %s", fn); + f = $fopen(fn, "w"); + $fwrite(f, " Time Cycles PC Instr Mnemonic\n"); + end + end + end + + final + begin + $fclose(f); + end + + // log execution + always @(negedge clk) + begin + + if (state == Running) begin + //we run the stages in reverse order because we don't want the same instr being + //processed by the multiple stages in the same cycle. + progressWB(); + progressEXMisaligned(); + progressEX(); + progressID(); + + printInstrTrace(); + end + end // always @ (posedge clk) + +endmodule diff --git a/hw/deps/riscv/verilator-model/cluster_clock_gating.sv b/hw/deps/riscv/verilator-model/cluster_clock_gating.sv new file mode 100644 index 0000000..d486555 --- /dev/null +++ b/hw/deps/riscv/verilator-model/cluster_clock_gating.sv @@ -0,0 +1,34 @@ +// Copyright 2017 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module cluster_clock_gating +( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o + ); + +`ifdef PULP_FPGA_EMUL + // no clock gates in FPGA flow + assign clk_o = clk_i; +`else + logic clk_en; + + always_latch + begin + if (clk_i == 1'b0) + clk_en <= en_i | test_en_i; + end + + assign clk_o = clk_i & clk_en; +`endif + +endmodule // cluster_clock_gating diff --git a/hw/deps/scm/latch_scm/register_file_1w_multi_port_read.sv b/hw/deps/scm/latch_scm/register_file_1w_multi_port_read.sv new file mode 100644 index 0000000..9d93525 --- /dev/null +++ b/hw/deps/scm/latch_scm/register_file_1w_multi_port_read.sv @@ -0,0 +1,173 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module register_file_1w_multi_port_read +#( + parameter ADDR_WIDTH = 5, + parameter DATA_WIDTH = 32, + + parameter N_READ = 2, + parameter N_WRITE = 1 +) +( + input logic clk, + input logic rst_n, + input logic test_en_i, + + // Read port + input logic [N_READ-1:0] ReadEnable, + input logic [N_READ-1:0][ADDR_WIDTH-1:0] ReadAddr, + output logic [N_READ-1:0][DATA_WIDTH-1:0] ReadData, + + // Write port + input logic WriteEnable, + input logic [ADDR_WIDTH-1:0] WriteAddr, + input logic [DATA_WIDTH-1:0] WriteData +); + + localparam NUM_WORDS = 2**ADDR_WIDTH; + + // Read address register, located at the input of the address decoder + logic [N_READ-1:0][ADDR_WIDTH-1:0] RAddrRegxDP; + logic [N_READ-1:0][NUM_WORDS-1:0] RAddrOneHotxD; + + logic [DATA_WIDTH-1:0] MemContentxDP[NUM_WORDS]; + + logic [NUM_WORDS-1:0] WAddrOneHotxD; + logic [NUM_WORDS-1:0] ClocksxC; + logic [DATA_WIDTH-1:0] WDataIntxD; + + logic clk_int; + + int unsigned i; + int unsigned k; + + genvar x; + genvar z; + + cluster_clock_gating CG_WE_GLOBAL + ( + .clk_o ( clk_int ), + .en_i ( WriteEnable ), + .test_en_i ( test_en_i ), + .clk_i ( clk ) + ); + + //----------------------------------------------------------------------------- + //-- READ : Read address register + //----------------------------------------------------------------------------- + + generate + for(z=0; z + +// Description: Functional module of a generic SRAM +// +// Parameters: +// - NumWords: Number of words in the macro. Address width can be calculated with: +// `AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1` +// The module issues a warning if there is a request on an address which is +// not in range. +// - DataWidth: Width of the ports `wdata_i` and `rdata_o`. +// - ByteWidth: Width of a byte, the byte enable signal `be_i` can be calculated with the +// ceiling division `ceil(DataWidth, ByteWidth)`. +// - NumPorts: Number of read and write ports. Each is a full port. Ports with a higher +// index read and write after the ones with lower indices. +// - Latency: Read latency, the read data is available this many cycles after a request. +// - SimInit: Macro simulation initialization. Values are: +// "zeros": Each bit gets initialized with 1'b0. +// "ones": Each bit gets initialized with 1'b1. +// "random": Each bit gets random initialized with 1'b0 or 1'b1. +// "none": Each bit gets initialized with 1'bx. (default) +// - PrintSimCfg: Prints at the beginning of the simulation a `Hello` message with +// the instantiated parameters and signal widths. +// +// Ports: +// - `clk_i`: Clock +// - `rst_ni`: Asynchronous reset, active low +// - `req_i`: Request, active high +// - `we_i`: Write request, active high +// - `addr_i`: Request address +// - `wdata_i`: Write data, has to be valid on request +// - `be_i`: Byte enable, active high +// - `rdata_o`: Read data, valid `Latency` cycles after a request with `we_i` low. +// +// Behaviour: +// - Address collision: When Ports are making a write access onto the same address, +// the write operation will start at the port with the lowest address +// index, each port will overwrite the changes made by the previous ports +// according how the respective `be_i` signal is set. +// - Read data on write: This implementation will not produce a read data output on the signal +// `rdata_o` when `req_i` and `we_i` are asserted. The output data is stable +// on write requests. + +module tc_sram #( + parameter int unsigned NumWords = 32'd1024, // Number of Words in data array + parameter int unsigned DataWidth = 32'd128, // Data signal width + parameter int unsigned ByteWidth = 32'd8, // Width of a data byte + parameter int unsigned NumPorts = 32'd2, // Number of read and write ports + parameter int unsigned Latency = 32'd1, // Latency when the read data is available + parameter SimInit = "none", // Simulation initialization + parameter bit PrintSimCfg = 1'b0, // Print configuration + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, + parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div + parameter type addr_t = logic [AddrWidth-1:0], + parameter type data_t = logic [DataWidth-1:0], + parameter type be_t = logic [BeWidth-1:0] +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // input ports + input logic [NumPorts-1:0] req_i, // request + input logic [NumPorts-1:0] we_i, // write enable + input addr_t [NumPorts-1:0] addr_i, // request address + input data_t [NumPorts-1:0] wdata_i, // write data + input be_t [NumPorts-1:0] be_i, // write byte enable + // output ports + output data_t [NumPorts-1:0] rdata_o // read data +); + + // memory array + data_t sram [NumWords-1:0]; + // hold the read address when no read access is made + addr_t [NumPorts-1:0] r_addr_q; + + // SRAM simulation initialization + data_t [NumWords-1:0] init_val; + initial begin : proc_sram_init + for (int unsigned i = 0; i < NumWords; i++) begin + for (int unsigned j = 0; j < DataWidth; j++) begin + case (SimInit) + "zeros": init_val[i][j] = 1'b0; + "ones": init_val[i][j] = 1'b1; + "random": init_val[i][j] = $urandom(); + default: init_val[i][j] = 1'bx; + endcase + end + end + end + + // set the read output if requested + // The read data at the highest array index is set combinational. + // It gets then delayed for a number of cycles until it gets available at the output at + // array index 0. + + // read data output assignment + data_t [NumPorts-1:0][Latency-1:0] rdata_q, rdata_d; + if (Latency == 32'd0) begin : gen_no_read_lat + for (genvar i = 0; i < NumPorts; i++) begin : gen_port + assign rdata_o[i] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]]; + end + end else begin : gen_read_lat + + always_comb begin + for (int unsigned i = 0; i < NumPorts; i++) begin + rdata_o[i] = rdata_q[i][0]; + for (int unsigned j = 0; j < (Latency-1); j++) begin + rdata_d[i][j] = rdata_q[i][j+1]; + end + rdata_d[i][Latency-1] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]]; + end + end + end + + /* verilator lint_on BLKLOOPINIT */ + // write memory array + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + for (int i = 0; i < NumPorts; i++) begin + r_addr_q[i] <= {AddrWidth{1'b0}}; + // initialize the read output register for each port + if (Latency != 32'd0) begin + for (int unsigned j = 0; j < Latency; j++) begin + rdata_q[i][j] <= init_val[{AddrWidth{1'b0}}]; + end + end + end + end else begin + // read value latch happens before new data is written to the sram + for (int unsigned i = 0; i < NumPorts; i++) begin + if (Latency != 0) begin + for (int unsigned j = 0; j < Latency; j++) begin + rdata_q[i][j] <= rdata_d[i][j]; + end + end + end + // there is a request for the SRAM, latch the required register + for (int unsigned i = 0; i < NumPorts; i++) begin + if (req_i[i]) begin + if (we_i[i]) begin + // update value when write is set at clock + for (int unsigned j = 0; j < DataWidth; j++) begin + if (be_i[i][j/ByteWidth]) begin + sram[addr_i[i]][j] = wdata_i[i][j]; + end + end + end else begin + // otherwise update read address for subsequent non request cycles + r_addr_q[i] <= addr_i[i]; + end + end // if req_i + end // for ports + end // if !rst_ni + end + /* verilator lint_on BLKLOOPINIT */ + +// Validate parameters. +// pragma translate_off +`ifndef VERILATOR +`ifndef TARGET_SYNTHESYS + initial begin: p_assertions + assert ($bits(addr_i) == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`"); + assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`"); + assert ($bits(be_i) == NumPorts * BeWidth) else $fatal(1, "BeWidth problem on `be_i`" ); + assert ($bits(rdata_o) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `rdata_o`"); + assert (NumWords >= 32'd1) else $fatal(1, "NumWords has to be > 0"); + assert (DataWidth >= 32'd1) else $fatal(1, "DataWidth has to be > 0"); + assert (ByteWidth >= 32'd1) else $fatal(1, "ByteWidth has to be > 0"); + assert (NumPorts >= 32'd1) else $fatal(1, "The number of ports must be at least 1!"); + end + initial begin: p_sim_hello + if (PrintSimCfg) begin + $display("#################################################################################"); + $display("tc_sram functional instantiated with the configuration:" ); + $display("Instance: %m" ); + $display("Number of ports (dec): %0d", NumPorts ); + $display("Number of words (dec): %0d", NumWords ); + $display("Address width (dec): %0d", AddrWidth ); + $display("Data width (dec): %0d", DataWidth ); + $display("Byte width (dec): %0d", ByteWidth ); + $display("Byte enable width (dec): %0d", BeWidth ); + $display("Latency Cycles (dec): %0d", Latency ); + $display("Simulation init (str): %0s", SimInit ); + $display("#################################################################################"); + end + end + for (genvar i = 0; i < NumPorts; i++) begin : gen_assertions + assert property ( @(posedge clk_i) disable iff (!rst_ni) + (req_i[i] |-> (addr_i[i] < NumWords))) else + $warning("Request address %0h not mapped, port %0d, expect random write or read behavior!", + addr_i[i], i); + end + +`endif +`endif +// pragma translate_on +endmodule diff --git a/hw/deps/timer_unit/rtl/timer_unit.sv b/hw/deps/timer_unit/rtl/timer_unit.sv new file mode 100644 index 0000000..07f19df --- /dev/null +++ b/hw/deps/timer_unit/rtl/timer_unit.sv @@ -0,0 +1,579 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +`define CFG_REG_LO 6'h0 +`define CFG_REG_HI 6'h4 +`define TIMER_VAL_LO 6'h8 +`define TIMER_VAL_HI 6'hC +`define TIMER_CMP_LO 6'h10 +`define TIMER_CMP_HI 6'h14 +`define TIMER_START_LO 6'h18 +`define TIMER_START_HI 6'h1C +`define TIMER_RESET_LO 6'h20 +`define TIMER_RESET_HI 6'h24 + + +`define ENABLE_BIT 'd0 +`define RESET_BIT 'd1 +`define IRQ_BIT 'd2 +`define IEM_BIT 'd3 +`define CMP_CLR_BIT 'd4 +`define ONE_SHOT_BIT 'd5 +`define PRESCALER_EN_BIT 'd6 +`define REF_CLK_EN_BIT 'd7 +`define PRESCALER_START_BIT 'd8 +`define PRESCALER_STOP_BIT 'd15 +`define MODE_64_BIT 'd31 + +module timer_unit + #( + parameter ID_WIDTH = 5 + ) + ( + input logic clk_i, + input logic rst_ni, + + input logic ref_clk_i, + + input logic req_i, + input logic [31:0] addr_i, + input logic wen_i, + input logic [31:0] wdata_i, + input logic [3:0] be_i, + input logic [ID_WIDTH-1:0] id_i, + output logic gnt_o, + + output logic r_valid_o, + output logic r_opc_o, + output logic [ID_WIDTH-1:0] r_id_o, + output logic [31:0] r_rdata_o, + + input logic event_lo_i, + input logic event_hi_i, + + output logic irq_lo_o, + output logic irq_hi_o, + + output logic busy_o + ); + + logic s_req,s_wen; + logic [31:0] s_addr; + + logic s_write_counter_lo, s_write_counter_hi; + logic s_start_timer_lo,s_start_timer_hi,s_reset_timer_lo,s_reset_timer_hi; + + logic s_ref_clk0, s_ref_clk1, s_ref_clk2, s_ref_clk3, s_ref_clk_edge, s_ref_clk_edge_del; + + logic [31:0] s_counter_val_lo, s_counter_val_hi; + + logic [31:0] s_cfg_lo, s_cfg_lo_reg; + logic [31:0] s_cfg_hi, s_cfg_hi_reg; + logic [31:0] s_timer_val_lo; + logic [31:0] s_timer_val_hi; + logic [31:0] s_timer_cmp_lo, s_timer_cmp_lo_reg; + logic [31:0] s_timer_cmp_hi, s_timer_cmp_hi_reg; + + logic s_enable_count_lo,s_enable_count_hi,s_enable_count_prescaler_lo,s_enable_count_prescaler_hi; + logic s_reset_count_lo,s_reset_count_hi,s_reset_count_prescaler_lo,s_reset_count_prescaler_hi; + logic s_target_reached_lo,s_target_reached_hi,s_target_reached_prescaler_lo, s_target_reached_prescaler_hi; + logic s_clear_reset_lo, s_clear_reset_hi; + + enum logic [1:0] { TRANS_IDLE, TRANS_RUN } CS, NS; + + //********************************************************** + //*************** FSM FOR GNT AND R_VALID ****************** + //********************************************************** + assign r_opc_o = 1'b0; + + always_ff @(posedge clk_i, negedge rst_ni) + begin + if(rst_ni == 1'b0) + CS <= TRANS_IDLE; + else + CS <= NS; + end + + always_comb + begin + + gnt_o = 1'b1; + r_valid_o = 1'b0; + + case(CS) + + TRANS_IDLE: + begin + if (req_i == 1'b1) + NS = TRANS_RUN; + else + NS = TRANS_IDLE; + end + + TRANS_RUN: + begin + r_valid_o = 1'b1; + if (req_i == 1'b1) + NS = TRANS_RUN; + else + NS = TRANS_IDLE; + end + + default: + NS = TRANS_IDLE; + + endcase + + end + + //********************************************************** + //*************** DELAYED ADDR, REQ, WEN ******************* + //********************************************************** + + always_ff @(posedge clk_i, negedge rst_ni) + begin + if(rst_ni == 1'b0) + begin + s_req <= 0; + s_wen <= 0; + s_addr <= 0; + r_id_o <= 0; + end + else + begin + s_req <= req_i; + s_wen <= wen_i; + s_addr <= addr_i; + r_id_o <= id_i; + end + end + + //********************************************************** + //*************** PERIPHS INTERFACE ************************ + //********************************************************** + + // register write logic + always_comb + begin + + s_cfg_lo = s_cfg_lo_reg; + s_cfg_hi = s_cfg_hi_reg; + s_timer_cmp_lo = s_timer_cmp_lo_reg; + s_timer_cmp_hi = s_timer_cmp_hi_reg; + s_write_counter_lo = 1'b0; + s_write_counter_hi = 1'b0; + s_start_timer_lo = 1'b0; + s_start_timer_hi = 1'b0; + s_reset_timer_lo = 1'b0; + s_reset_timer_hi = 1'b0; + + // APERIPH BUS: LOWER PRIORITY + if (req_i && ~wen_i) + begin + + case (addr_i[5:0]) + + `CFG_REG_LO: + s_cfg_lo = wdata_i; + + `CFG_REG_HI: + s_cfg_hi = wdata_i; + + `TIMER_VAL_LO: + s_write_counter_lo = 1'b1; + + `TIMER_VAL_HI: + s_write_counter_hi = 1'b1; + + `TIMER_CMP_LO: + s_timer_cmp_lo = wdata_i; + + `TIMER_CMP_HI: + s_timer_cmp_hi = wdata_i; + + `TIMER_START_LO: + s_start_timer_lo = 1'b1; + + `TIMER_START_HI: + s_start_timer_hi = 1'b1; + + `TIMER_RESET_LO: + s_reset_timer_lo = 1'b1; + + `TIMER_RESET_HI: + s_reset_timer_hi = 1'b1; + + endcase + end + + // INPUT EVENTS: HIGHER PRIORITY + if ( ((event_lo_i == 1) && (s_cfg_lo[`IEM_BIT] == 1'b1)) | s_start_timer_lo == 1 ) + s_cfg_lo[`ENABLE_BIT] = 1; + else + begin + if ( s_cfg_lo_reg[`MODE_64_BIT] == 1'b0 ) // 32 BIT MODE + begin + if ( ( s_cfg_lo[`ONE_SHOT_BIT] == 1'b1 ) && ( s_target_reached_lo == 1'b1 ) ) // ONE SHOT FEATURE: DISABLES TIMER ONCE THE TARGET IS REACHED + s_cfg_lo[`ENABLE_BIT] = 0; + end + else + begin + if ( ( s_cfg_lo[`ONE_SHOT_BIT] == 1'b1 ) && ( s_target_reached_lo == 1'b1 ) && ( s_target_reached_hi == 1'b1 ) ) // ONE SHOT FEATURE: DISABLES TIMER ONCE LOW COUNTER REACHES 0xFFFFFFFF and HI COUNTER TARGET IS REACHED + s_cfg_lo[`ENABLE_BIT] = 0; + end + end + + // INPUT EVENTS: HIGHER PRIORITY + if ( ((event_hi_i == 1) && (s_cfg_hi[`IEM_BIT] == 1'b1)) | s_start_timer_hi == 1 ) + s_cfg_hi[`ENABLE_BIT] = 1; + else + begin + if ( ( s_cfg_hi_reg[`MODE_64_BIT] == 1'b0 ) && ( s_cfg_hi[`ONE_SHOT_BIT] == 1'b1 ) && ( s_target_reached_hi == 1'b1 ) ) // ONE SHOT FEATURE: DISABLES TIMER ONCE THE TARGET IS REACHED IN 32 BIT MODE + s_cfg_hi[`ENABLE_BIT] = 0; + else begin + if ( ( s_cfg_lo[`ONE_SHOT_BIT] == 1'b1 ) && ( s_target_reached_lo == 1'b1 ) && ( s_target_reached_hi == 1'b1 ) ) + s_cfg_hi[`ENABLE_BIT] = 0; + end + end + + // RESET LO + if (s_reset_count_lo == 1'b1) + s_cfg_lo[`RESET_BIT] = 1'b0; + + // RESET HI + if (s_reset_count_hi == 1'b1) + s_cfg_hi[`RESET_BIT] = 1'b0; + + end + + // sequential part + always_ff @(posedge clk_i, negedge rst_ni) + begin + if(~rst_ni) + begin + s_cfg_lo_reg <= 0; + s_cfg_hi_reg <= 0; + s_timer_cmp_lo_reg <= 0; + s_timer_cmp_hi_reg <= 0; + end + else + begin + s_cfg_lo_reg <= s_cfg_lo; + s_cfg_hi_reg <= s_cfg_hi; + s_timer_cmp_lo_reg <= s_timer_cmp_lo; + s_timer_cmp_hi_reg <= s_timer_cmp_hi; + end + end + + // APB register read logic + always_comb + begin + r_rdata_o = 'b0; + + if (s_req && s_wen) + begin + + case (s_addr[5:0]) + + `CFG_REG_LO: + r_rdata_o = s_cfg_lo_reg; + + `CFG_REG_HI: + r_rdata_o = s_cfg_hi_reg; + + `TIMER_VAL_LO: + r_rdata_o = s_timer_val_lo; + + `TIMER_VAL_HI: + r_rdata_o = s_timer_val_hi; + + `TIMER_CMP_LO: + r_rdata_o = s_timer_cmp_lo_reg; + + `TIMER_CMP_HI: + r_rdata_o = s_timer_cmp_hi_reg; + + endcase + + end + + end + + //********************************************************** + //*************** CONTROL ********************************** + //********************************************************** + + // RESET COUNT SIGNAL GENERATION + always_comb + begin + s_reset_count_lo = 1'b0; + s_reset_count_hi = 1'b0; + s_reset_count_prescaler_lo = 1'b0; + s_reset_count_prescaler_hi = 1'b0; + + if ( s_cfg_lo_reg[`RESET_BIT] == 1'b1 | s_reset_timer_lo == 1'b1 ) + begin + s_reset_count_lo = 1'b1; + s_reset_count_prescaler_lo = 1'b1; + end + else + begin + if ( s_cfg_lo_reg[`MODE_64_BIT] == 1'b0 ) // 32-bit mode + begin + if ( ( s_cfg_lo_reg[`CMP_CLR_BIT] == 1'b1 ) && ( s_target_reached_lo == 1'b1 ) ) // if compare and clear feature is enabled the counter is resetted when the target is reached + begin + s_reset_count_lo = 1; + end + end + else // 64-bit mode + begin + if ( ( s_cfg_lo_reg[`CMP_CLR_BIT] == 1'b1 ) && ( s_target_reached_lo == 1'b1 ) && ( s_target_reached_hi == 1'b1 ) ) // if compare and clear feature is enabled the counter is resetted when the target is reached + begin + s_reset_count_lo = 1; + end + end + end + + if ( s_cfg_hi_reg[`RESET_BIT] == 1'b1 | s_reset_timer_hi == 1'b1 ) + begin + s_reset_count_hi = 1'b1; + s_reset_count_prescaler_hi = 1'b1; + end + else + begin + if ( s_cfg_lo_reg[`MODE_64_BIT] == 1'b0 ) // 32-bit mode + begin + if ( ( s_cfg_hi_reg[`CMP_CLR_BIT] == 1'b1 ) && ( s_target_reached_hi == 1'b1 ) ) // if compare and clear feature is enabled the counter is resetted when the target is reached + begin + s_reset_count_hi = 1; + end + end + else // 64-bit mode + begin + if ( ( s_cfg_lo_reg[`CMP_CLR_BIT] == 1'b1 ) && ( s_target_reached_lo == 1'b1 ) && ( s_target_reached_hi == 1'b1 ) ) // if compare and clear feature is enabled the counter is resetted when the target is reached + begin + s_reset_count_hi = 1; + end + end + end + + if ( ( s_cfg_lo_reg[`PRESCALER_EN_BIT] ) && ( s_target_reached_prescaler_lo == 1'b1 ) ) + begin + s_reset_count_prescaler_lo = 1'b1; + end + + if ( ( s_cfg_hi_reg[`PRESCALER_EN_BIT] ) && ( s_target_reached_prescaler_hi == 1'b1 ) ) + begin + s_reset_count_prescaler_hi = 1'b1; + end + + end + + // ENABLE SIGNALS GENERATION + always_comb + begin + s_enable_count_lo = 1'b0; + s_enable_count_hi = 1'b0; + s_enable_count_prescaler_lo = 1'b0; + s_enable_count_prescaler_hi = 1'b0; + + // 32 bit mode lo counter + if ( s_cfg_lo_reg[`ENABLE_BIT] == 1'b1 ) + begin + if ( s_cfg_lo_reg[`PRESCALER_EN_BIT] == 1'b0 && s_cfg_lo_reg[`REF_CLK_EN_BIT] == 1'b0 ) // prescaler disabled, ref clock disabled + begin + s_enable_count_lo = 1'b1; + end + else + if ( s_cfg_lo_reg[`PRESCALER_EN_BIT] == 1'b0 && s_cfg_lo_reg[`REF_CLK_EN_BIT] == 1'b1 ) // prescaler disabled, ref clock enabled + begin + s_enable_count_lo = s_ref_clk_edge; + end + else + if ( s_cfg_lo_reg[`PRESCALER_EN_BIT] == 1'b1 && s_cfg_lo_reg[`REF_CLK_EN_BIT] == 1'b1 ) // prescaler enabled, ref clock enabled + begin + s_enable_count_prescaler_lo = s_ref_clk_edge; + s_enable_count_lo = s_target_reached_prescaler_lo; + end + else // prescaler enabled, ref clock disabled + begin + s_enable_count_prescaler_lo = 1'b1; + s_enable_count_lo = s_target_reached_prescaler_lo; + end + end + + // 32 bit mode hi counter + if ( s_cfg_hi_reg[`ENABLE_BIT] == 1'b1 ) // counter hi enabled + begin + if ( s_cfg_hi_reg[`PRESCALER_EN_BIT] == 1'b0 && s_cfg_hi_reg[`REF_CLK_EN_BIT] == 1'b0 ) // prescaler disabled, ref clock disabled + begin + s_enable_count_hi = 1'b1; + end + else + if ( s_cfg_hi_reg[`PRESCALER_EN_BIT] == 1'b0 && s_cfg_hi_reg[`REF_CLK_EN_BIT] == 1'b1 ) // prescaler disabled, ref clock enabled + begin + s_enable_count_hi = s_ref_clk_edge; + end + else + if ( s_cfg_hi_reg[`PRESCALER_EN_BIT] == 1'b1 && s_cfg_hi_reg[`REF_CLK_EN_BIT] == 1'b1 ) // prescaler enabled, ref clock enabled + begin + s_enable_count_prescaler_hi = s_ref_clk_edge; + s_enable_count_hi = s_target_reached_prescaler_hi; + end + else // prescaler enabled, ref clock disabled + begin + s_enable_count_prescaler_hi = 1'b1; + s_enable_count_hi = s_target_reached_prescaler_hi; + end + end + + // 64-bit mode + if ( ( s_cfg_lo_reg[`ENABLE_BIT] == 1'b1 ) && ( s_cfg_lo_reg[`MODE_64_BIT] == 1'b1 ) ) // timer enabled, 64-bit mode + begin + if ( ( s_cfg_lo_reg[`PRESCALER_EN_BIT] == 1'b0 ) && s_cfg_lo_reg[`REF_CLK_EN_BIT] == 1'b0 ) // prescaler disabled, ref clock disabled + begin + s_enable_count_lo = 1'b1; + s_enable_count_hi = ( s_timer_val_lo == 32'hFFFFFFFF ); + end + else if ( s_cfg_lo_reg[`PRESCALER_EN_BIT] == 1'b0 && s_cfg_lo_reg[`REF_CLK_EN_BIT] == 1'b1 ) // prescaler disabled, ref clock enabled + begin + s_enable_count_lo = s_ref_clk_edge; + s_enable_count_hi = s_ref_clk_edge_del && ( s_timer_val_lo == 32'hFFFFFFFF ); + end + else if ( s_cfg_lo_reg[`PRESCALER_EN_BIT] == 1'b1 && s_cfg_lo_reg[`REF_CLK_EN_BIT] == 1'b1 ) // prescaler enabled, ref clock enabled + begin + s_enable_count_prescaler_lo = s_ref_clk_edge; + s_enable_count_lo = s_target_reached_prescaler_lo; + s_enable_count_hi = s_target_reached_prescaler_lo && s_ref_clk_edge_del && ( s_timer_val_lo == 32'hFFFFFFFF ); + end + else // prescaler enabled, ref clock disabled + begin + s_enable_count_prescaler_lo = 1'b1; + s_enable_count_lo = s_target_reached_prescaler_lo; + s_enable_count_hi = s_target_reached_prescaler_lo && ( s_timer_val_lo == 32'hFFFFFFFF ); + end + end + end + + // IRQ SIGNALS GENERATION + always_comb + begin + irq_lo_o = 1'b0; + irq_hi_o = 1'b0; + + if ( s_cfg_lo_reg[`MODE_64_BIT] == 1'b0 ) + begin + irq_lo_o = s_target_reached_lo & s_cfg_lo_reg[`IRQ_BIT]; + irq_hi_o = s_target_reached_hi & s_cfg_hi_reg[`IRQ_BIT]; + end + else + begin + irq_lo_o = s_target_reached_lo & s_target_reached_hi & s_cfg_lo_reg[`IRQ_BIT]; + end + end + + //********************************************************** + //*************** EDGE DETECTOR FOR REF CLOCK ************** + //********************************************************** + + always_ff @(posedge clk_i, negedge rst_ni) + begin + if(~rst_ni) + begin + s_ref_clk0 <= 1'b0; + s_ref_clk1 <= 1'b0; + s_ref_clk2 <= 1'b0; + s_ref_clk3 <= 1'b0; + end + else + begin + s_ref_clk0 <= ref_clk_i; + s_ref_clk1 <= s_ref_clk0; + s_ref_clk2 <= s_ref_clk1; + s_ref_clk3 <= s_ref_clk2; + end + end + + assign s_ref_clk_edge = ( ( s_ref_clk1 == 1'b1 ) & ( s_ref_clk2 == 1'b0 ) ) ? 1'b1 : 1'b0; + assign s_ref_clk_edge_del = ( ( s_ref_clk2 == 1'b1 ) & ( s_ref_clk3 == 1'b0 ) ) ? 1'b1 : 1'b0; + + //********************************************************** + //*************** COUNTERS ********************************* + //********************************************************** + + timer_unit_counter_presc prescaler_lo_i + ( + .clk_i(clk_i), + .rst_ni(rst_ni), + + .write_counter_i(1'b0), + .counter_value_i(32'h0000_0000), + + .enable_count_i(s_enable_count_prescaler_lo), + .reset_count_i(s_reset_count_prescaler_lo), + .compare_value_i({24'd0,s_cfg_lo_reg[`PRESCALER_STOP_BIT:`PRESCALER_START_BIT]}), + + .counter_value_o(), + .target_reached_o(s_target_reached_prescaler_lo) + ); + + timer_unit_counter_presc prescaler_hi_i + ( + .clk_i(clk_i), + .rst_ni(rst_ni), + + .write_counter_i(1'b0), + .counter_value_i(32'h0000_0000), + + .enable_count_i(s_enable_count_prescaler_hi), + .reset_count_i(s_reset_count_prescaler_hi), + .compare_value_i({24'd0,s_cfg_hi_reg[`PRESCALER_STOP_BIT:`PRESCALER_START_BIT]}), + + .counter_value_o(), + .target_reached_o(s_target_reached_prescaler_hi) + ); + + timer_unit_counter counter_lo_i + ( + .clk_i(clk_i), + .rst_ni(rst_ni), + + .write_counter_i(s_write_counter_lo), + .counter_value_i(wdata_i), + + .enable_count_i(s_enable_count_lo), + .reset_count_i(s_reset_count_lo), + .compare_value_i(s_timer_cmp_lo_reg), + + .counter_value_o(s_timer_val_lo), + .target_reached_o(s_target_reached_lo) + ); + + timer_unit_counter counter_hi_i + ( + .clk_i(clk_i), + .rst_ni(rst_ni), + + .write_counter_i(s_write_counter_hi), + .counter_value_i(wdata_i), + + .enable_count_i(s_enable_count_hi), + .reset_count_i(s_reset_count_hi), + .compare_value_i(s_timer_cmp_hi_reg), + + .counter_value_o(s_timer_val_hi), + .target_reached_o(s_target_reached_hi) + ); + + assign busy_o = s_cfg_hi_reg[`ENABLE_BIT] | s_cfg_lo_reg[`ENABLE_BIT]; + +endmodule diff --git a/hw/deps/timer_unit/rtl/timer_unit_counter.sv b/hw/deps/timer_unit/rtl/timer_unit_counter.sv new file mode 100644 index 0000000..6592d7f --- /dev/null +++ b/hw/deps/timer_unit/rtl/timer_unit_counter.sv @@ -0,0 +1,73 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module timer_unit_counter + ( + input logic clk_i, + input logic rst_ni, + + input logic write_counter_i, + input logic [31:0] counter_value_i, + + input logic reset_count_i, + input logic enable_count_i, + input logic [31:0] compare_value_i, + + output logic [31:0] counter_value_o, + output logic target_reached_o + ); + + logic [31:0] s_count, s_count_reg; + + // COUNTER + always_comb + begin + s_count = s_count_reg; + + // start counting + if ( reset_count_i == 1 ) + s_count = 0; + else + begin + if (write_counter_i == 1) // OVERWRITE COUNTER + s_count = counter_value_i; + else + begin + if ( enable_count_i == 1 ) // the counter is increased if counter is enabled and there is a tick + s_count = s_count_reg + 1; + end + end + end + + always_ff@(posedge clk_i, negedge rst_ni) + begin + if (rst_ni == 0) + s_count_reg <= 0; + else + s_count_reg <= s_count; + end + + // COMPARATOR + always_ff@(posedge clk_i, negedge rst_ni) + begin + if (rst_ni == 0) + target_reached_o <= 1'b0; + else + if ( s_count == compare_value_i ) + target_reached_o <= 1'b1; + else + target_reached_o <= 1'b0; + end + + assign counter_value_o = s_count_reg; + +endmodule diff --git a/hw/deps/timer_unit/rtl/timer_unit_counter_presc.sv b/hw/deps/timer_unit/rtl/timer_unit_counter_presc.sv new file mode 100644 index 0000000..099da6b --- /dev/null +++ b/hw/deps/timer_unit/rtl/timer_unit_counter_presc.sv @@ -0,0 +1,73 @@ +// Copyright 2014-2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Davide Rossi + +module timer_unit_counter_presc + ( + input logic clk_i, + input logic rst_ni, + + input logic write_counter_i, + input logic [31:0] counter_value_i, + + input logic reset_count_i, + input logic enable_count_i, + input logic [31:0] compare_value_i, + + output logic [31:0] counter_value_o, + output logic target_reached_o + ); + + logic [31:0] s_count, s_count_reg; + + // COUNTER + always_comb + begin + s_count = s_count_reg; + + // start counting + if ( reset_count_i == 1 || target_reached_o==1) + s_count = 0; + else + begin + if (write_counter_i == 1) // OVERWRITE COUNTER + s_count = counter_value_i; + else + begin + if ( enable_count_i == 1 ) + s_count = s_count_reg + 1; + end + end + end + + always_ff@(posedge clk_i, negedge rst_ni) + begin + if (rst_ni == 0) + s_count_reg <= 0; + else + s_count_reg <= s_count; + end + + // COMPARATOR + always_ff@(posedge clk_i, negedge rst_ni) + begin + if (rst_ni == 0) + target_reached_o <= 1'b0; + else + if ( s_count == compare_value_i ) + target_reached_o <= 1'b1; + else + target_reached_o <= 1'b0; + end + + assign counter_value_o = s_count_reg; + +endmodule diff --git a/hw/src/apb/apb_bus.sv b/hw/src/apb/apb_bus.sv new file mode 100644 index 0000000..d908873 --- /dev/null +++ b/hw/src/apb/apb_bus.sv @@ -0,0 +1,128 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Imported from WIP in axi repo; TODO: unify APB modules and depend on the updated apb repo + +// APB Bus with Single Master and Multiple Slave Interfaces +// Each slave is accessible at exactly one address segment, and the address ranges of no two slaves +// may overlap. If the input address of this bus is not in any slave address segment, the bus +// responds with slverr; otherwise, this bus feeds all signals through to the slave. The slaves see +// offset-compensated addresses, e.g., if this bus gets ADDR_BEGIN[i] as input address, slave i will +// get address 0. +module apb_bus #( + // Number of slaves. + parameter int unsigned ADDR_WIDTH = 0, + parameter int unsigned DATA_WIDTH = 0, + parameter int unsigned N_SLV = 0, + // Address ranges of the slaves. Slave i is mapped in the inclusive interval from ADDR_BEGIN[i] to + // ADDR_END[i]. + parameter logic [N_SLV-1:0][ADDR_WIDTH-1:0] ADDR_BEGIN = '0, + parameter logic [N_SLV-1:0][ADDR_WIDTH-1:0] ADDR_END = '0, + // Dependent parameters, do not change! + parameter int unsigned STRB_WIDTH = DATA_WIDTH/8 +) ( + // Input + input logic [ADDR_WIDTH-1:0] paddr_i, + input logic [2:0] pprot_i, + input logic psel_i, + input logic penable_i, + input logic pwrite_i, + input logic [DATA_WIDTH-1:0] pwdata_i, + input logic [STRB_WIDTH-1:0] pstrb_i, + output logic pready_o, + output logic [DATA_WIDTH-1:0] prdata_o, + output logic pslverr_o, + + // Outputs + output logic [N_SLV-1:0][ADDR_WIDTH-1:0] paddr_o, + output logic [N_SLV-1:0] [2:0] pprot_o, + output logic [N_SLV-1:0] psel_o, + output logic [N_SLV-1:0] penable_o, + output logic [N_SLV-1:0] pwrite_o, + output logic [N_SLV-1:0][DATA_WIDTH-1:0] pwdata_o, + output logic [N_SLV-1:0][STRB_WIDTH-1:0] pstrb_o, + input logic [N_SLV-1:0] pready_i, + input logic [N_SLV-1:0][DATA_WIDTH-1:0] prdata_i, + input logic [N_SLV-1:0] pslverr_i +); + + logic [$clog2(N_SLV)-1:0] sel_idx; + logic dec_err; + + for (genvar i = 0; i < N_SLV; i++) begin: gen_oup_demux + assign paddr_o[i] = paddr_i - ADDR_BEGIN[i]; + assign pprot_o[i] = pprot_i; + assign psel_o[i] = psel_i & (paddr_i >= ADDR_BEGIN[i] && paddr_i <= ADDR_END[i]); + assign penable_o[i] = penable_i; + assign pwrite_o[i] = pwrite_i; + assign pwdata_o[i] = pwdata_i; + assign pstrb_o[i] = pstrb_i; + end + + assign dec_err = psel_i & ~(|psel_o); + + if (N_SLV > 1) begin: gen_sel_idx_onehot + onehot_to_bin #(.ONEHOT_WIDTH(N_SLV)) i_sel_idx ( + .onehot (psel_o), + .bin (sel_idx) + ); + end else begin: gen_sel_idx_zero + assign sel_idx = 1'b0; + end + + always_comb begin + if (psel_i) begin + if (dec_err) begin + pready_o = 1'b1; + prdata_o = '0; + pslverr_o = 1'b1; + end else begin + pready_o = pready_i[sel_idx]; + prdata_o = prdata_i[sel_idx]; + pslverr_o = pslverr_i[sel_idx]; + end + end else begin // !psel_i + pready_o = 1'b0; + prdata_o = '0; + pslverr_o = 1'b0; + end + end + + // Validate parameters. + // pragma translate_off + `ifndef VERILATOR + initial begin: p_assertions + assert (N_SLV >= 1) else $fatal(1, "The number of slave ports must be at least 1!"); + assert (ADDR_WIDTH >= 1) else $fatal(1, "The addr width must be at least 1!"); + assert (DATA_WIDTH >= 1) else $fatal(1, "The data width must be at least 1!"); + end + for (genvar i = 0; i < N_SLV; i++) begin: gen_assert_addr_outer + initial begin + assert (ADDR_BEGIN[i] <= ADDR_END[i]) + else $fatal(1, "Invalid address range for slave %0d", i); + end + for (genvar j = 0; j < N_SLV; j++) begin: gen_assert_addr_inner + initial begin + if (i != j) begin + if (ADDR_BEGIN[j] >= ADDR_BEGIN[i]) begin + assert (ADDR_BEGIN[j] > ADDR_END[i]) + else $fatal("Address range of slaves %0d and %0d overlap!", i, j); + end else begin + assert (ADDR_END[j] < ADDR_BEGIN[i]) + else $fatal("Address range of slaves %0d and %0d overlap!", i, j); + end + end + end + end + end + `endif + // pragma translate_on + +endmodule diff --git a/hw/src/apb/apb_bus_wrap.sv b/hw/src/apb/apb_bus_wrap.sv new file mode 100644 index 0000000..47ada15 --- /dev/null +++ b/hw/src/apb/apb_bus_wrap.sv @@ -0,0 +1,82 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// TODO: put into updated apb repo + +module apb_bus_wrap #( + parameter int unsigned ADDR_WIDTH = 0, + parameter int unsigned DATA_WIDTH = 0, + parameter int unsigned N_SLV = 0, + // Address ranges of the slaves. Slave i is mapped in the inclusive interval from ADDR_BEGIN[i] to + // ADDR_END[i]. + parameter logic [N_SLV-1:0][ADDR_WIDTH-1:0] ADDR_BEGIN = '0, + parameter logic [N_SLV-1:0][ADDR_WIDTH-1:0] ADDR_END = '0, + // Dependent parameters, do not change! + parameter int unsigned STRB_WIDTH = DATA_WIDTH/8 +) ( + APB_BUS.Slave inp, + APB_BUS.Master oup[N_SLV-1:0] +); + + logic [N_SLV-1:0][ADDR_WIDTH-1:0] paddr; + logic [N_SLV-1:0] [2:0] pprot; + logic [N_SLV-1:0] psel; + logic [N_SLV-1:0] penable; + logic [N_SLV-1:0] pwrite; + logic [N_SLV-1:0][DATA_WIDTH-1:0] pwdata; + logic [N_SLV-1:0][STRB_WIDTH-1:0] pstrb; + logic [N_SLV-1:0] pready; + logic [N_SLV-1:0][DATA_WIDTH-1:0] prdata; + logic [N_SLV-1:0] pslverr; + + apb_bus #( + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .N_SLV (N_SLV), + .ADDR_BEGIN (ADDR_BEGIN), + .ADDR_END (ADDR_END) + ) i_apb_bus ( + .paddr_i (inp.paddr), + .pprot_i ('0), // TODO: connect after upgrade to APBv2 + .psel_i (inp.psel), + .penable_i (inp.penable), + .pwrite_i (inp.pwrite), + .pwdata_i (inp.pwdata), + .pstrb_i ('1), // TODO: connect after upgrade to APBv2 + .pready_o (inp.pready), + .prdata_o (inp.prdata), + .pslverr_o (inp.pslverr), + + .paddr_o (paddr), + .pprot_o (), // TODO: connect after upgrade to APBv2 + .psel_o (psel), + .penable_o (penable), + .pwrite_o (pwrite), + .pwdata_o (pwdata), + .pstrb_o (), // TODO: connect after upgrade to APBv2 + .pready_i (pready), + .prdata_i (prdata), + .pslverr_i (pslverr) + ); + + for (genvar i = 0; i < N_SLV; i++) begin: gen_bind_oup + assign oup[i].paddr = paddr[i]; + //assign oup[i].pprot = pprot[i]; // TODO: connect after upgrade to APBv2 + assign oup[i].psel = psel[i]; + assign oup[i].penable = penable[i]; + assign oup[i].pwrite = pwrite[i]; + assign oup[i].pwdata = pwdata[i]; + //assign oup[i].pstrb = pstrb[i]; // TODO: connect after upgrade to APBv2 + assign pready[i] = oup[i].pready; + assign prdata[i] = oup[i].prdata; + assign pslverr[i] = oup[i].pslverr; + end + +endmodule diff --git a/hw/src/apb/apb_ro_regs.sv b/hw/src/apb/apb_ro_regs.sv new file mode 100644 index 0000000..e454a0b --- /dev/null +++ b/hw/src/apb/apb_ro_regs.sv @@ -0,0 +1,56 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Imported from WIP in axi repo; TODO: unify APB modules and depend on the updated apb repo + +// APB Read-Only Registers +// TODO: Module specification + +module apb_ro_regs #( + parameter int unsigned ADDR_WIDTH = 0, + parameter int unsigned DATA_WIDTH = 0, + parameter int unsigned N_REGS = 0 +) ( + APB_BUS.Slave apb, + input logic [N_REGS-1:0][DATA_WIDTH-1:0] reg_i +); + + localparam WORD_OFF = $clog2(DATA_WIDTH/8); + + always_comb begin + apb.prdata = 'x; + apb.pslverr = 1'b0; + if (apb.psel) begin + if (apb.pwrite) begin + // Error response to writes + apb.pslverr = 1'b1; + end else begin + automatic logic [ADDR_WIDTH-WORD_OFF-1:0] word_addr = apb.paddr >> WORD_OFF; + if (word_addr >= N_REGS) begin + // Error response to reads out of range + apb.pslverr = 1'b1; + end else begin + apb.prdata = reg_i[word_addr]; + end + end + end + end + assign apb.pready = apb.psel & apb.penable; + + // Validate parameters. + // pragma translate_off + `ifndef VERILATOR + initial begin: p_assertions + assert (N_REGS >= 1) else $fatal(1, "The number of registers must be at least 1!"); + end + `endif + // pragma translate_on + +endmodule diff --git a/hw/src/apb/apb_rw_regs.sv b/hw/src/apb/apb_rw_regs.sv new file mode 100644 index 0000000..7d9d40e --- /dev/null +++ b/hw/src/apb/apb_rw_regs.sv @@ -0,0 +1,82 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Imported from WIP in axi repo; TODO: unify APB modules and depend on the updated apb repo + +// APB Read-Write Registers +// TODO: Module specification + +module apb_rw_regs #( + parameter int unsigned ADDR_WIDTH = 0, + parameter int unsigned DATA_WIDTH = 0, + parameter int unsigned N_REGS = 0 +) ( + input logic clk_i, + input logic rst_ni, + + // APB Interface + APB_BUS.Slave apb, + + // Register Interface + input logic [N_REGS-1:0][DATA_WIDTH-1:0] init_i, + output logic [N_REGS-1:0][DATA_WIDTH-1:0] q_o +); + + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8; + localparam int unsigned WORD_OFF = $clog2(STRB_WIDTH); + + logic [N_REGS-1:0][DATA_WIDTH-1:0] reg_d, reg_q; + + always_comb begin + reg_d = reg_q; + apb.prdata = 'x; + apb.pslverr = 1'b0; + if (apb.psel) begin + automatic logic [ADDR_WIDTH-WORD_OFF-1:0] word_addr = apb.paddr >> WORD_OFF; + if (word_addr >= N_REGS) begin + // Error response to accesses that are out of range + apb.pslverr = 1'b1; + end else begin + if (apb.pwrite) begin + reg_d[word_addr] = apb.pwdata; + // TODO: handle after upgrade to APBv2 + //for (int i = 0; i < STRB_WIDTH; i++) begin + // if (apb.pstrb[i]) begin + // reg_d[word_addr][i*8 +: 8] = apb.pwdata[i*8 +: 8]; + // end + //end + end else begin + apb.prdata = reg_q[word_addr]; + end + end + end + end + assign apb.pready = apb.psel & apb.penable; + + assign q_o = reg_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + reg_q <= init_i; + end else begin + reg_q <= reg_d; + end + end + + // Validate parameters. + // pragma translate_off + `ifndef VERILATOR + initial begin: p_assertions + assert (N_REGS >= 1) else $fatal(1, "The number of registers must be at least 1!"); + end + `endif + // pragma translate_on + +endmodule diff --git a/hw/src/apb/apb_stdout.sv b/hw/src/apb/apb_stdout.sv new file mode 100644 index 0000000..3e44ae7 --- /dev/null +++ b/hw/src/apb/apb_stdout.sv @@ -0,0 +1,70 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module apb_stdout #( + parameter int unsigned N_CORES = 0, + parameter int unsigned N_CLUSTERS = 0, + parameter int unsigned ADDR_WIDTH = 0, + parameter int unsigned DATA_WIDTH = 0 +) ( + input logic clk_i, + input logic rst_ni, + APB_BUS.Slave apb +); + `ifndef VERILATOR + byte buffer [N_CLUSTERS-1:0][N_CORES-1:0][$]; + + function void flush(int unsigned i_cl, int unsigned i_core); + automatic string s; + for (int i_char = 0; i_char < buffer[i_cl][i_core].size(); i_char++) begin + s = $sformatf("%s%c", s, buffer[i_cl][i_core][i_char]); + end + if (s.len() > 0) begin + $display("[%01d,%01d] %s", i_cl, i_core, s); + end + buffer[i_cl][i_core] = {}; + endfunction + + function void append(int unsigned i_cl, int unsigned i_core, byte ch); + if (ch == 8'hA) begin + flush(i_cl, i_core); + end else begin + buffer[i_cl][i_core].push_back(ch); + end + endfunction + + always_ff @(posedge clk_i or negedge rst_ni) begin + int unsigned cl_idx, core_idx; + byte data; + if (!rst_ni) begin + for (int i_cl = 0; i_cl < N_CLUSTERS; i_cl++) begin + for (int i_core = 0; i_core < N_CORES; i_core++) begin + flush(i_cl, i_core); + end + end + end else begin + if (apb.psel && apb.penable && apb.pwrite) begin + cl_idx = (apb.paddr >> 7) & 32'hF; + core_idx = (apb.paddr >> 3) & 32'hF; + if (cl_idx < N_CLUSTERS && core_idx < N_CORES) begin + data = apb.pwdata & 32'hFF; + append(cl_idx, core_idx, data); + end + end + end + end + `endif + + assign apb.prdata = '0; + assign apb.pslverr = 1'b0; + assign apb.pready = 1'b1; + + +endmodule diff --git a/hw/src/cmds/cluster_cmd.sv b/hw/src/cmds/cluster_cmd.sv new file mode 100644 index 0000000..08500e9 --- /dev/null +++ b/hw/src/cmds/cluster_cmd.sv @@ -0,0 +1,50 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import pspin_cfg_pkg::*; + +module cluster_cmd #( + parameter int unsigned NUM_CORES = 8 +) ( + input logic clk_i, + input logic rst_ni, + + //from hpu drivers (commands) + output logic [NUM_CORES-1:0] cmd_ready_o, + input logic [NUM_CORES-1:0] cmd_valid_i, + input pspin_cmd_t [NUM_CORES-1:0] cmd_i, + + //to uncluster + input logic cmd_ready_i, + output logic cmd_valid_o, + output pspin_cmd_t cmd_o +); + + rr_arb_tree #( + .NumIn (NUM_CORES), + .DataType (pspin_cmd_t), + .ExtPrio (0), + .AxiVldRdy (1), + .LockIn (1) + ) i_cluster_cmd_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .rr_i ('0), + .req_i (cmd_valid_i), + .gnt_o (cmd_ready_o), + .data_i (cmd_i), + .gnt_i (cmd_ready_i), + .req_o (cmd_valid_o), + .data_o (cmd_o), + .idx_o () + ); + +endmodule diff --git a/hw/src/cmds/cmd_unit.sv b/hw/src/cmds/cmd_unit.sv new file mode 100644 index 0000000..2e698c7 --- /dev/null +++ b/hw/src/cmds/cmd_unit.sv @@ -0,0 +1,212 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import pspin_cfg_pkg::*; + +module cmd_unit #( + parameter int unsigned NUM_CLUSTERS = 4, + parameter int unsigned NUM_CMD_INTERFACES = 2, + parameter int unsigned INTF_RESP_BUFF_SIZE = 8 +) ( + input logic clk_i, + input logic rst_ni, + + output logic [NUM_CLUSTERS-1:0] cmd_ready_o, + input logic [NUM_CLUSTERS-1:0] cmd_valid_i, + input pspin_cmd_t [NUM_CLUSTERS-1:0] cmd_i, + + output logic cmd_resp_valid_o, + output pspin_cmd_resp_t cmd_resp_o, + + input logic [NUM_CMD_INTERFACES-1:0] intf_ready_i, + output logic [NUM_CMD_INTERFACES-1:0] intf_valid_o, + output pspin_cmd_t [NUM_CMD_INTERFACES-1:0] intf_cmd_o, + + input logic [NUM_CMD_INTERFACES-1:0] intf_cmd_resp_valid_i, + input pspin_cmd_resp_t [NUM_CMD_INTERFACES-1:0] intf_cmd_resp_i +); + + /* spill registers from clusters */ + logic [NUM_CLUSTERS-1:0] cluster_cmd_ready; + logic [NUM_CLUSTERS-1:0] cluster_cmd_valid; + pspin_cmd_t [NUM_CLUSTERS-1:0] cluster_cmd; + + for (genvar i=0; i=8 + parameter int unsigned CUT_N_WORDS = 16384, // must be a power of 2 + parameter int unsigned N_PAR_CUTS_MUL = 4 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv_a, + AXI_BUS.Slave slv_b +); + + // Properties of one memory cut, keep synchronized with instantiated macro. + //localparam int unsigned CUT_DW = 64; // [bit], must be a power of 2 and >=8 + //localparam int unsigned CUT_N_WORDS = 16384; // must be a power of 2 + localparam int unsigned CUT_N_BITS = CUT_DW * CUT_N_WORDS; + + // Derived properties of memory array + localparam int unsigned N_PAR_CUTS = N_PAR_CUTS_MUL * AXI_DW / CUT_DW; + localparam int unsigned PAR_CUTS_N_BYTES = N_PAR_CUTS * CUT_N_BITS / 8; + localparam int unsigned N_SER_CUTS = N_BYTES / PAR_CUTS_N_BYTES; + + localparam int unsigned MEM_ADDR_WIDTH = $clog2(CUT_N_WORDS * N_SER_CUTS); + typedef logic [N_PAR_CUTS-1:0][MEM_ADDR_WIDTH-1:0] mem_addr_t; + typedef logic [N_PAR_CUTS-1:0][CUT_DW-1:0] mem_data_t; + typedef logic [N_PAR_CUTS-1:0][CUT_DW/8-1:0] mem_strb_t; + typedef logic [N_PAR_CUTS-1:0] mem_logic_t; + + mem_logic_t mem_req, + mem_wen; + mem_addr_t mem_addr; + mem_data_t mem_wdata, + mem_rdata; + mem_strb_t mem_be; + + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) internal_a (); + + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) internal_b (); + + axi_buf_intf #( + .AW_DEPTH (32'd2), + .W_DEPTH (32'd1), + .ADDR_WIDTH (AXI_AW), + .DATA_WIDTH (AXI_DW), + .ID_WIDTH (AXI_IW), + .USER_WIDTH (AXI_UW) + ) i_axi_a_buf ( + .clk_i, + .rst_ni, + .slv (slv_a), + .mst (internal_a) + ); + + axi_buf_intf #( + .AW_DEPTH (32'd2), + .W_DEPTH (32'd1), + .ADDR_WIDTH (AXI_AW), + .DATA_WIDTH (AXI_DW), + .ID_WIDTH (AXI_IW), + .USER_WIDTH (AXI_UW) + ) i_axi_b_buf ( + .clk_i, + .rst_ni, + .slv (slv_b), + .mst (internal_b) + ); + + axi_to_mem_banked_2p_intf #( + .AXI_ID_WIDTH (AXI_IW), + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_DW), + .AXI_USER_WIDTH (AXI_UW), + .MEM_NUM_BANKS (N_PAR_CUTS), + .MEM_ADDR_WIDTH (MEM_ADDR_WIDTH), + .MEM_DATA_WIDTH (CUT_DW), + .MEM_LATENCY (1), + .TOPOLOGY (tcdm_interconnect_pkg::LIC) + ) i_axi_to_mem_banked ( + .clk_i, + .rst_ni, + .test_i (1'b0), + .slv_a (internal_a), + .slv_b (internal_b), + .mem_req_o (mem_req), + .mem_gnt_i ({N_PAR_CUTS{1'b1}}), + .mem_add_o (mem_addr), + .mem_wen_o (mem_wen), + .mem_wdata_o (mem_wdata), + .mem_be_o (mem_be), + .mem_atop_o (/* unused */), + .mem_rdata_i (mem_rdata), + .axi_to_mem_busy_a_o (/* unused */), + .axi_to_mem_busy_b_o (/* unused */) + ); + + // Interface from memory array to memory cuts + localparam int unsigned WORD_IDX_OFF = 0; // output of `axi_to_mem_banked` is word-addressed + localparam int unsigned WORD_IDX_WIDTH = $clog2(CUT_N_WORDS); + localparam int unsigned ROW_IDX_OFF = WORD_IDX_OFF + WORD_IDX_WIDTH; + localparam int unsigned ROW_IDX_WIDTH = $clog2(N_SER_CUTS); + + // Types for memory cuts + typedef logic [$clog2(CUT_N_WORDS)-1:0] cut_addr_t; + typedef logic [CUT_DW-1:0] cut_data_t; + + logic [N_PAR_CUTS-1:0][N_SER_CUTS-1:0] cut_req; + cut_addr_t [N_PAR_CUTS-1:0] cut_addr_d, cut_addr_q; + cut_data_t [N_PAR_CUTS-1:0][N_SER_CUTS-1:0] cut_rdata; + logic [N_PAR_CUTS-1:0][ROW_IDX_WIDTH-1:0] row_idx_d, row_idx_q; + + for (genvar iCol = 0; iCol < N_PAR_CUTS; iCol++) begin : gen_cols + assign cut_addr_d[iCol] + = mem_req[iCol] ? mem_addr[iCol][WORD_IDX_OFF+:WORD_IDX_WIDTH] : cut_addr_q[iCol]; + + if (ROW_IDX_WIDTH > 0) begin : gen_row_idx + assign row_idx_d[iCol] + = mem_req[iCol] ? mem_addr[iCol][ROW_IDX_OFF+:ROW_IDX_WIDTH] : row_idx_q[iCol]; + always_comb begin + cut_req[iCol] = '0; + cut_req[iCol][row_idx_d[iCol]] = mem_req[iCol]; + end + assign mem_rdata[iCol] = cut_rdata[iCol][row_idx_q[iCol]]; + + end else begin : gen_no_row_idx + assign cut_req[iCol][0] = mem_req[iCol]; + assign mem_rdata[iCol] = cut_rdata[iCol][0]; + end + + for (genvar iRow = 0; iRow < N_SER_CUTS; iRow++) begin : gen_rows + sram #( + .DATA_WIDTH (CUT_DW), + .N_WORDS (CUT_N_WORDS) + ) i_mem_cut ( + .clk_i, + .rst_ni, + .req_i (cut_req[iCol][iRow]), + .we_i (mem_wen[iCol]), + .addr_i (cut_addr_d[iCol]), + .wdata_i (mem_wdata[iCol]), + .be_i (mem_be[iCol]), + .rdata_o (cut_rdata[iCol][iRow]) + ); + end + end + + `FFARN(cut_addr_q, cut_addr_d, '0, clk_i, rst_ni) + `FFARN(row_idx_q, row_idx_d, '0, clk_i, rst_ni) + + // Validate parameters and properties. + // pragma translate_off + initial begin + assert (AXI_AW > 0); + assert (AXI_AW % (2**$clog2(AXI_AW)) == 0); + assert (AXI_DW > 0); + assert (AXI_DW % (2**$clog2(AXI_DW)) == 0); + assert (N_BYTES > 0); + assert (N_BYTES % (2**$clog2(N_BYTES)) == 0); + assert (CUT_DW % (2**$clog2(CUT_DW)) == 0); + assert (CUT_DW >= 8); + assert (AXI_DW >= CUT_DW); + assert (CUT_N_WORDS % 2**$clog2(CUT_N_WORDS) == 0); + assert (N_BYTES % PAR_CUTS_N_BYTES == 0); + end + // pragma translate_on + +endmodule diff --git a/hw/src/memories/prog_mem.sv b/hw/src/memories/prog_mem.sv new file mode 100644 index 0000000..6397202 --- /dev/null +++ b/hw/src/memories/prog_mem.sv @@ -0,0 +1,163 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "axi/typedef.svh" +`include "common_cells/registers.svh" + +/// Program memory shared by all clusters, with an additional port for the host to deploy handler +/// code. +module prog_mem #( + parameter int unsigned NumClusters = 0, + parameter int unsigned NumBytes = 0, + parameter int unsigned AddrWidth = 0, + parameter int unsigned DataWidth = 0, + parameter int unsigned IdWidth = 0, + parameter int unsigned UserWidth = 0, + parameter type req_t = logic, + parameter type resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + + input req_t [NumClusters-1:0] cl_req_i, + output resp_t [NumClusters-1:0] cl_resp_o, + input req_t host_req_i, + output resp_t host_resp_o +); + + // Types of input and output channels. + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [IdWidth-1:0] id_t; + typedef logic [DataWidth/8-1:0] strb_t; + typedef logic [UserWidth-1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t) + + // Slave ports of multiplexer. + localparam int unsigned NumSlvPorts = NumClusters + 1; + req_t [NumSlvPorts-1:0] req; + resp_t [NumSlvPorts-1:0] resp; + for (genvar i = 0; i < NumSlvPorts; i++) begin : gen_bind_slv_ports + if (i < NumClusters) begin : gen_bind_cluster + assign req[i] = cl_req_i[i]; + assign cl_resp_o[i] = resp[i]; + end else begin : gen_bind_host + assign req[i] = host_req_i; + assign host_resp_o = resp[i]; + end + end + + // Types of master ports of multiplexer. + parameter int unsigned MuxIdWidth = IdWidth + cf_math_pkg::idx_width(NumSlvPorts); + typedef logic [MuxIdWidth-1:0] mux_id_t; + `AXI_TYPEDEF_AW_CHAN_T(mux_aw_t, addr_t, mux_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mux_b_t, mux_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mux_ar_t, addr_t, mux_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mux_r_t, data_t, mux_id_t, user_t) + `AXI_TYPEDEF_REQ_T(mux_req_t, mux_aw_t, w_t, mux_ar_t) + `AXI_TYPEDEF_RESP_T(mux_resp_t, mux_b_t, mux_r_t) + mux_req_t mux_req; + mux_resp_t mux_resp; + // Instantiation of multiplexer. + axi_mux #( + .SlvAxiIDWidth (IdWidth), + .slv_aw_chan_t (aw_t), + .mst_aw_chan_t (mux_aw_t), + .w_chan_t (w_t), + .slv_b_chan_t (b_t), + .mst_b_chan_t (mux_b_t), + .slv_ar_chan_t (ar_t), + .mst_ar_chan_t (mux_ar_t), + .slv_r_chan_t (r_t), + .mst_r_chan_t (mux_r_t), + .slv_req_t (req_t), + .slv_resp_t (resp_t), + .mst_req_t (mux_req_t), + .mst_resp_t (mux_resp_t), + .NoSlvPorts (NumSlvPorts), + .MaxWTrans (1), + .FallThrough (1'b0), + .SpillAw (1'b0), + .SpillW (1'b0), + .SpillB (1'b0), + .SpillAr (1'b0), + .SpillR (1'b0) + ) i_mux ( + .clk_i, + .rst_ni, + .test_i (1'b0), + .slv_reqs_i (req), + .slv_resps_o (resp), + .mst_req_o (mux_req), + .mst_resp_i (mux_resp) + ); + + // AXI-to-memory converter + logic mem_req, + mem_req_q, + mem_we; + addr_t axi_to_mem_addr; + data_t mem_rdata, + mem_wdata; + strb_t mem_strb; + axi_to_mem #( + .axi_req_t (mux_req_t), + .axi_resp_t (mux_resp_t), + .AddrWidth (AddrWidth), + .DataWidth (DataWidth), + .IdWidth (MuxIdWidth), + .NumBanks (1), + .BufDepth (1) + ) i_axi_to_mem ( + .clk_i, + .rst_ni, + .busy_o (/* unused */), + .axi_req_i (mux_req), + .axi_resp_o (mux_resp), + .mem_req_o (mem_req), + .mem_gnt_i (1'b1), + .mem_addr_o (axi_to_mem_addr), + .mem_wdata_o (mem_wdata), + .mem_strb_o (mem_strb), + .mem_atop_o (/* unsupported */), + .mem_we_o (mem_we), + .mem_rvalid_i (mem_req_q), + .mem_rdata_i (mem_rdata) + ); + `FFARN(mem_req_q, mem_req, 1'b0, clk_i, rst_ni) + + // Truncation of addresses into SRAM + localparam int unsigned NumWords = NumBytes / (DataWidth / 8); + localparam int unsigned ByteOffset = $clog2(DataWidth / 8); + localparam int unsigned MemAddrWidth = cf_math_pkg::idx_width(NumWords); + typedef logic [MemAddrWidth-1:0] mem_addr_t; + mem_addr_t mem_addr; + assign mem_addr = axi_to_mem_addr[ByteOffset+:MemAddrWidth]; + + // SRAM macro + sram #( + .DATA_WIDTH (DataWidth), + .N_WORDS (NumWords) + ) i_sram ( + .clk_i, + .rst_ni, + .req_i (mem_req), + .we_i (mem_we), + .addr_i (mem_addr), + .wdata_i (mem_wdata), + .be_i (mem_strb), + .rdata_o (mem_rdata) + ); + +endmodule diff --git a/hw/src/memories/sram.sv b/hw/src/memories/sram.sv new file mode 100644 index 0000000..a42154b --- /dev/null +++ b/hw/src/memories/sram.sv @@ -0,0 +1,52 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// TODO: Replace behavior with instantiation of cuts. + +module sram #( + parameter int unsigned DATA_WIDTH = 0, // [bit] + parameter int unsigned N_WORDS = 0, + parameter SimInit = "none", + // Dependent parameters, do not override! + parameter int unsigned N_BYTES = DATA_WIDTH/8, + parameter type addr_t = logic[$clog2(N_WORDS)-1:0], + parameter type data_t = logic[DATA_WIDTH-1:0], + parameter type strb_t = logic[N_BYTES-1:0] +) ( + input logic clk_i, + input logic rst_ni, + input logic req_i, + input logic we_i, + input addr_t addr_i, + input data_t wdata_i, + input strb_t be_i, + output data_t rdata_o +); + + tc_sram #( + .NumWords ( N_WORDS ), + .DataWidth ( DATA_WIDTH ), + .ByteWidth ( 8 ), + .NumPorts ( 1 ), + .Latency ( 1 ), + .SimInit ( SimInit ), + .PrintSimCfg ( 1'b0 ) + ) i_tc_sram ( + .clk_i, + .rst_ni, + .req_i, + .we_i, + .addr_i, + .wdata_i, + .be_i, + .rdata_o + ); + +endmodule diff --git a/hw/src/pkt_scheduler/cluster_rb.sv b/hw/src/pkt_scheduler/cluster_rb.sv new file mode 100644 index 0000000..2e7c719 --- /dev/null +++ b/hw/src/pkt_scheduler/cluster_rb.sv @@ -0,0 +1,190 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/* + An allocator which manages memory as a ring-buffer. All allocations requests + are always served from the tail_ptr. It allocates only contiguous memory regions, so + an allocation cannot wrap around: + - if head_ptr =< tail_ptr, the available space is max(mem_region_end - tail_ptr, head_ptr). + - if head_ptr > tail_ptr, the available space is head_ptr - tail_ptr. + + Free are not treated as FIFO pops, but they came with their own memory index, i.e., the index + at which the memory region to free starts, and size. A memory index to free is not necesserly + equal to the head_ptr but can be samewhere in between head_ptr and tail_ptr. The head_ptr is + moved forward only when there is a consecutive free memory region in front of it. +*/ + +module cluster_rb #( + parameter int unsigned BuffMemLength = 1, + parameter int unsigned MemSlotSize = 64, //[B] + + //derived parameters + parameter type elem_size_t = logic [$clog2(BuffMemLength):0], + parameter type elem_idx_t = logic [$clog2(BuffMemLength)-1:0], + parameter int unsigned NumSlots = BuffMemLength / MemSlotSize +) ( + + input logic clk_i, + input logic rst_ni, + + input logic alloc_valid_i, + output logic alloc_ready_o, + input elem_size_t alloc_size_i, //[B] + output elem_idx_t alloc_index_o, //[B] + + input logic free_valid_i, + input elem_idx_t free_index_i, //[B] + input elem_size_t free_size_i, //[B] + + output elem_size_t free_space_o //[B] +); + + /* we take the minimum allocatable unit as parameter, this is MemSlotSize. + Internally, we represent memory as a sequence of blocks of size MemSlotSize. + */ + typedef logic [$clog2(NumSlots)-1:0] slot_ptr_t; + typedef logic [$clog2(NumSlots):0] slot_size_t; + + logic [NumSlots-1:0] bitmap_d; + logic [NumSlots-1:0] bitmap_q; + + slot_ptr_t head_ptr_d, head_ptr_q; + slot_ptr_t tail_ptr_d, tail_ptr_q; + + slot_ptr_t push_idx, pop_idx; + slot_size_t push_size, pop_size; + + logic [NumSlots*2-1:0] bitmap_to_shift; + logic [NumSlots-1:0] bitmap_shifted; + + logic push_en, pop_en; + + slot_ptr_t head_ptr_incr_lzc; + slot_size_t head_ptr_incr; + slot_size_t head_ptr_incr_max; + slot_size_t head_ptr_incr_real; + logic no_head_ptr_incr; + + slot_size_t padding; + logic data_fits; + + logic equal_full, equal_empty; + + slot_size_t free_slots, free_slots_to_end, free_slots_to_head; + + //the idea is to store the status of the memory blocks in a bitmap. + for (genvar i=0; i= push_idx && i < push_idx + push_size) || (pop_en && i >= pop_idx && i < pop_idx + pop_size)); + end + + //the bitmap is shifted right by head_ptr_q, so to let lzc count the number of consecutive free blocks and use + //that information to update head_ptr_q. + + assign head_ptr_incr_max = (tail_ptr_q >= head_ptr_q) ? tail_ptr_q - head_ptr_q : tail_ptr_q + NumSlots - head_ptr_q; + assign head_ptr_incr = head_ptr_incr_lzc + no_head_ptr_incr; + assign head_ptr_incr_real = (head_ptr_incr_max > head_ptr_incr) ? head_ptr_incr : head_ptr_incr_max; + + assign bitmap_to_shift = { bitmap_q, bitmap_q } ; // input is the 512 bit bitmap + assign bitmap_shifted = bitmap_to_shift[head_ptr_q +: NumSlots]; + + //get increment of head_ptr; + lzc #( + .WIDTH (NumSlots) + ) i_lzc_head_ptr_incr ( + .in_i (bitmap_shifted), + .cnt_o (head_ptr_incr_lzc), + .empty_o (no_head_ptr_incr) + ); + + + assign push_en = data_fits && alloc_valid_i; + assign pop_en = free_valid_i; + + assign pop_idx = free_index_i / MemSlotSize; + assign push_idx = tail_ptr_q + padding; + + assign push_size = (alloc_size_i + MemSlotSize - 1) / MemSlotSize; + assign pop_size = (free_size_i + MemSlotSize - 1) / MemSlotSize; + + assign alloc_ready_o = push_en; + assign alloc_index_o = push_idx * MemSlotSize; + + assign equal_full = (head_ptr_q == tail_ptr_q && bitmap_q > 0); + assign equal_empty = (head_ptr_q == tail_ptr_q && bitmap_q == 0); + + //meaningful only if tail_ptr_q >= head_ptr_q + assign free_slots_to_end = NumSlots - tail_ptr_q; + assign free_slots_to_head = head_ptr_q; + + assign free_space_o = free_slots * MemSlotSize; + + //determine number of consecutive slots available + always_comb begin + free_slots = 0; + if (!equal_full) begin + if (head_ptr_q <= tail_ptr_q) begin + free_slots = (free_slots_to_end > free_slots_to_head) ? free_slots_to_end : free_slots_to_head; + end + else begin + free_slots = head_ptr_q - tail_ptr_q; + end + end + end + + always_comb begin + head_ptr_d = head_ptr_q + head_ptr_incr_real; + tail_ptr_d = (push_en) ? tail_ptr_q + padding + push_size : tail_ptr_q; + + //if everything is quiet and the buffer is empty, reset the pointers to zero + //so to regain the full space. + if (!push_en && !pop_en && equal_empty) begin + head_ptr_d = '0; + tail_ptr_d = '0; + end + end + + //check if data fits + always_comb begin + data_fits = 1'b0; + padding = '0; + + if (!equal_full) begin + if (head_ptr_q <= tail_ptr_q) begin + if (NumSlots - tail_ptr_q >= push_size) begin + // |<- start | <- pop | <-push [data fits here] | <- end + data_fits = 1'b1; + end + else if (push_size < head_ptr_q) begin //FIXME: this should be <= ? + // |<- start [data fits here] | <- pop | <-push | <- end + //push doesn't fit there, we start from 0 + data_fits = 1'b1; + padding = NumSlots - tail_ptr_q; + end + end + else if (tail_ptr_q - head_ptr_q >= push_size) begin + // |<- start | <- push [data fits here] | <-pop | <- end + data_fits = 1'b1; + end + end + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + bitmap_q <= '0; + head_ptr_q <= '0; + tail_ptr_q <= '0; + end else begin + bitmap_q <= bitmap_d; + head_ptr_q <= head_ptr_d; + tail_ptr_q <= tail_ptr_d; + end + end + +endmodule diff --git a/hw/src/pkt_scheduler/cluster_scheduler.sv b/hw/src/pkt_scheduler/cluster_scheduler.sv new file mode 100644 index 0000000..8a8c424 --- /dev/null +++ b/hw/src/pkt_scheduler/cluster_scheduler.sv @@ -0,0 +1,298 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import pspin_cfg_pkg::*; + +module cluster_scheduler #( + parameter int NUM_HERS_PER_CLUSTER = 64, + parameter int L1_PKT_BUFF_SIZE = 512, + parameter int L1_CLUSTER_BASE = 0, + parameter int L1_CLUSTER_MEM_SIZE = 0, + parameter int L1_RUNTIME_OFFSET = 0, + parameter int TASKS_FIFO_DEPTH = 1 +) ( + + input logic clk_i, + input logic rst_ni, + + input logic [5:0] cluster_id_i, + + //task from scheduler + input logic task_valid_i, + output logic task_ready_o, + input handler_task_t task_descr_i, + + //feedback to scheduler + output logic feedback_valid_o, + input logic feedback_ready_i, + output feedback_descr_t feedback_o, + + //dma request to DMA engine + output logic dma_xfer_valid_o, + input logic dma_xfer_ready_i, + output transf_descr_32_t dma_xfer_o, + + //dma response from DMA engine + input logic dma_resp_i, + + //task_descr_t to HPU + output logic [NUM_CORES-1:0] hpu_task_valid_o, + input logic [NUM_CORES-1:0] hpu_task_ready_i, + output hpu_handler_task_t hpu_task_o, + + //feedback from HPUs + input logic [NUM_CORES-1:0] hpu_feedback_valid_i, + output logic [NUM_CORES-1:0] hpu_feedback_ready_o, + input task_feedback_descr_t [NUM_CORES-1:0] hpu_feedback_i, + + //activation signal from HPUs + input logic [NUM_CORES-1:0] hpu_active_i, + + //activation signal out + output logic cluster_active_o +); + + localparam int unsigned PktBuffMemSlotSize = 64; + typedef logic [$clog2(L1_PKT_BUFF_SIZE):0] pkt_buf_size_t; + typedef logic [$clog2(L1_PKT_BUFF_SIZE)-1:0] pkt_buf_idx_t; + + logic [$clog2(NUM_HERS_PER_CLUSTER):0] to_pop_d; + logic [$clog2(NUM_HERS_PER_CLUSTER):0] to_pop_q; + + //tasks which DMA xfers are still in-flight + logic dma_req_empty; + logic dma_req_full; + //set if a request has been popped (i.e., dma resp recvd + assigned to core) + logic dma_req_pop, dma_req_pop_nz; + hpu_handler_task_t ready_task; + hpu_handler_task_t new_task; + + //true if we can issue a DMA transfer a + logic can_issue_dma; + + logic [31:0] l1_pkt_base_addr; + logic [31:0] l1_pkt_ptr; + + //free HPUs + logic [$clog2(NUM_CORES)-1:0] free_hpu_idx; + logic no_free_hpu; + + //L1 packet buffer + pkt_buf_idx_t free_pkt_idx; + pkt_buf_idx_t feedback_pkt_idx; + pkt_buf_size_t pkt_buff_free_space; + + //true if the HER allocator is ready + logic pkt_alloc_ready; //unused in synthesis + + //internal state + typedef enum logic {Ready, WaitDMA} state_t; + state_t state_d, state_q; + + transf_descr_32_t dma_xfer, dma_xfer_q, dma_xfer_d; + + // buffer the tasks in a fifo + fifo_v3 #( + .dtype (hpu_handler_task_t), + .DEPTH (NUM_HERS_PER_CLUSTER) + ) i_dma_request_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (dma_req_full), + .empty_o (dma_req_empty), + .usage_o (), + .data_i (new_task), + .push_i (task_valid_i && task_ready_o), + .data_o (ready_task), + .pop_i (dma_req_pop) + ); + + //idle HPUs + lzc #( + .WIDTH (NUM_CORES) + ) i_lzc_free_hpus ( + .in_i (hpu_task_ready_i), + .cnt_o (free_hpu_idx), + .empty_o (no_free_hpu) + ); + + // Packet buffer allocator + cluster_rb #( + .BuffMemLength (L1_PKT_BUFF_SIZE), + .MemSlotSize (PktBuffMemSlotSize) + ) i_her_alloc ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .alloc_valid_i (task_valid_i && task_ready_o), + .alloc_ready_o (pkt_alloc_ready), + .alloc_size_i (task_descr_i.pkt_size[$clog2(L1_PKT_BUFF_SIZE):0]), + .alloc_index_o (free_pkt_idx), + + .free_valid_i (feedback_valid_o && feedback_ready_i), + .free_index_i (feedback_pkt_idx), + .free_size_i (hpu_feedback_arb_i.feedback_descr.pkt_size[$clog2(L1_PKT_BUFF_SIZE):0]), + + .free_space_o (pkt_buff_free_space) + ); + + // HPU feedbacks to cluster feedback arbiter + task_feedback_descr_t hpu_feedback_arb_i; + rr_arb_tree #( + .NumIn (NUM_CORES), + .DataType (task_feedback_descr_t), + .ExtPrio (0), + .AxiVldRdy (1), + .LockIn (1) + ) i_hpu_feedback_rr_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .rr_i ('0), + .req_i (hpu_feedback_valid_i), + .gnt_o (hpu_feedback_ready_o), + .data_i (hpu_feedback_i), + .gnt_i (feedback_ready_i), + .req_o (feedback_valid_o), + .data_o (hpu_feedback_arb_i), + .idx_o () + ); + + assign cluster_active_o = (~hpu_active_i == '0); + + assign l1_pkt_base_addr = (L1_CLUSTER_BASE + cluster_id_i * L1_CLUSTER_MEM_SIZE) + L1_PKT_BUFF_OFFSET; + assign l1_pkt_ptr = l1_pkt_base_addr + free_pkt_idx; + assign feedback_pkt_idx = hpu_feedback_arb_i.pkt_ptr - l1_pkt_base_addr; + + /*** Accepting tasks and starting DMA xfers ***/ + + //define a new task + assign new_task.handler_task = task_descr_i; + assign new_task.pkt_ptr = l1_pkt_ptr; + + //define DMA xfer + assign can_issue_dma = task_valid_i && task_ready_o && task_descr_i.pkt_size != '0; + + assign dma_xfer.num_bytes = task_descr_i.pkt_size; + assign dma_xfer.src_addr = task_descr_i.pkt_addr; + assign dma_xfer.dst_addr = l1_pkt_ptr; + + assign dma_xfer.decouple = 1'b1; + assign dma_xfer.deburst = 1'b0; + assign dma_xfer.serialize = 1'b0; // TODO: connect me! + + assign dma_xfer_d = (state_q == Ready) ? dma_xfer : dma_xfer_q; + assign dma_xfer_o = (state_q == Ready) ? dma_xfer : dma_xfer_q; + assign dma_xfer_valid_o = (state_d == Ready && can_issue_dma) || (state_q == WaitDMA); + + //we are ready to accept new tasks if + // - we are in Ready state AND + // - we can buffer the new DMA xfer AND + // - we have an HER in L1 where we can copy the L2 HER + //This is a bit redundant because we expect the scheduler to not forward + //us tasks if we are at capacity. + assign task_ready_o = (state_q == Ready) && (!dma_req_full) && (pkt_buff_free_space >= task_descr_i.pkt_size); + + always_comb begin + state_d = state_q; + + case (state_q) + Ready: begin + //we don't issue a DMA transfer for zero-byte task (e.g., header, completion) + if (can_issue_dma) begin + state_d = (dma_xfer_ready_i) ? Ready : WaitDMA; + end + end + + WaitDMA: begin + if (dma_xfer_ready_i) begin + state_d = Ready; + end + end + endcase + end + + /*** Other side of the FIFO: popping and assigning to free HPUs ***/ + + //we pop if there is a free HPU and if there is a completed xfer + assign dma_req_pop = !dma_req_empty && !no_free_hpu && (to_pop_q > 0 || ready_task.handler_task.pkt_size == 0); + + //this gets asserted if we are popping an entry associated with an actual DMA transfer. + assign dma_req_pop_nz = !dma_req_empty && !no_free_hpu && to_pop_q > 0 && ready_task.handler_task.pkt_size > 0; + + //ready hput tasks goes to all HPUs' outputs but only one will be enabled + assign hpu_task_o = ready_task; + for (genvar i = 0; i < NUM_CORES; i++) begin : gen_hpu_task + assign hpu_task_valid_o[i] = dma_req_pop & (i == free_hpu_idx); + end + + /*** Feedback forwarding ***/ + assign feedback_o = hpu_feedback_arb_i.feedback_descr; + + + /*** Internal state ***/ + + //count how many DMA xfers can be popped. + //+1 if we get a DMA completion but do not pop at this cycle (e.g., no free HPU) + //-1 if we can pop at this cycle but did not get a DMA completion + //+0 if we get a DMA completion and also pop in this cycle + always_comb begin + case ({dma_resp_i, dma_req_pop_nz}) + 2'b10 : to_pop_d = to_pop_q + 1; + 2'b01 : to_pop_d = to_pop_q - 1; + default : to_pop_d = to_pop_q; + endcase + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + to_pop_q <= '0; + state_q <= Ready; + dma_xfer_q <= '0; + end else begin + to_pop_q <= to_pop_d; + state_q <= state_d; + dma_xfer_q <= dma_xfer_d; + end + end + + `ifndef VERILATOR + // pragma translate_off + initial begin + forever begin + @(posedge clk_i); + if (task_valid_i && task_ready_o) begin + $display("%0d CLUSTER %0d got task (msg_id: %0d; size: %0d; addr: %0d)!", $time, cluster_id_i, task_descr_i.msgid, task_descr_i.pkt_size, task_descr_i.pkt_addr); + + if (dma_xfer_valid_o && dma_xfer_ready_i && dma_xfer.src_addr[5:0] != '0) begin + $display("WARNING: source address of DMA transfer is not 512-bit aligned: this will negatively impact performance!"); + end + if (dma_xfer_valid_o && dma_xfer_ready_i && dma_xfer.dst_addr[5:0] != '0) begin + $display("WARNING: destination address of DMA transfer is not 512-bit aligned: this will negatively impact performance!"); + end + end + end + end + + initial begin : p_assertions + + assert property (@(posedge clk_i) (dma_req_pop) |-> (!dma_req_empty)) else + $fatal(1, "We cannot pop from an empty queue!"); + + assert property (@(posedge clk_i) (task_valid_i && task_ready_o) |-> (pkt_buff_free_space >= task_descr_i.pkt_size)) else + $fatal(1, "We received a packet that cannot store!"); + + end + // pragma translate_on + `endif + +endmodule \ No newline at end of file diff --git a/hw/src/pkt_scheduler/fifo_engine.sv b/hw/src/pkt_scheduler/fifo_engine.sv new file mode 100644 index 0000000..116bd7f --- /dev/null +++ b/hw/src/pkt_scheduler/fifo_engine.sv @@ -0,0 +1,221 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// this does not work if we are pushing and popping at the same time +// from a queue of size 0 +module fifo_engine #( + //dynamic cells + parameter int NUM_CELLS = 64, + parameter int NUM_FIFO = 16, + parameter int NUM_STATIC_CELLS_PER_FIFO = 4, + parameter type elem_t = logic, + + //do not touch! + parameter int TOT_STATIC_CELLS = NUM_STATIC_CELLS_PER_FIFO * NUM_FIFO, + parameter int TOT_CELLS = TOT_STATIC_CELLS + NUM_CELLS, + parameter type fifo_id_t = logic [$clog2(NUM_FIFO)-1:0], + parameter type cell_id_t = logic [$clog2(TOT_CELLS)-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + //push interface + input elem_t new_el_i, + input logic push_i, + input fifo_id_t fifo_push_id_i, + + //pop interface + input logic pop_i, + input fifo_id_t fifo_pop_id_i, + output elem_t data_o, + + //output interface + output logic empty_o, + output logic [NUM_FIFO-1:0] fifo_full_o +); + + typedef struct packed { + cell_id_t next; + logic is_last; + } cell_t; + + localparam int unsigned ELEM_SIZE = $bits(elem_t); + localparam int unsigned ELEM_SIZE_B = $bits(elem_t)/8; + + cell_t [TOT_CELLS-1:0] cells_q; + cell_t [TOT_CELLS-1:0] cells_d; + + logic [TOT_CELLS-1:0] free_cells_d; + logic [TOT_CELLS-1:0] free_cells_q; + + cell_id_t [NUM_FIFO-1:0] fifo_head_d; + cell_id_t [NUM_FIFO-1:0] fifo_head_q; + + cell_id_t [NUM_FIFO-1:0] fifo_last_d; + cell_id_t [NUM_FIFO-1:0] fifo_last_q; + + logic [NUM_FIFO-1:0] fifo_empty_q; + logic [NUM_FIFO-1:0] fifo_empty_d; + + logic [NUM_FIFO-1:0][$clog2(NUM_STATIC_CELLS_PER_FIFO):0] fifo_static_occup_q; + logic [NUM_FIFO-1:0][$clog2(NUM_STATIC_CELLS_PER_FIFO):0] fifo_static_occup_d; + + cell_id_t free_dynamic_cell_idx; + cell_id_t free_static_cell_idx, free_static_cell_idx_lzc; + cell_id_t push_cell_idx, pop_cell_idx; + logic no_free_dynamic_cells, no_free_static_cells; + logic pushing_to_static; + logic popping_from_static; + + // free dynamic slots + assign free_dynamic_cell_idx[$clog2(TOT_CELLS)-1:$clog2(NUM_CELLS)] = '0; + lzc #( + .WIDTH (NUM_CELLS) + ) i_lzc_dynamic_free_slots ( + .in_i (~(free_cells_q[NUM_CELLS-1:0])), + .cnt_o (free_dynamic_cell_idx[$clog2(NUM_CELLS)-1:0]), + .empty_o (no_free_dynamic_cells) + ); + + // free static slots + assign free_static_cell_idx = free_static_cell_idx_lzc + NUM_CELLS; + assign free_static_cell_idx_lzc[$clog2(TOT_CELLS)-1:$clog2(TOT_STATIC_CELLS)] = '0; + lzc #( + .WIDTH (TOT_STATIC_CELLS) + ) i_lzc_static_free_slots ( + .in_i (~(free_cells_q[TOT_CELLS-1:NUM_CELLS])), + .cnt_o (free_static_cell_idx_lzc[$clog2(TOT_STATIC_CELLS)-1:0]), + .empty_o (no_free_static_cells) + ); + + //memory for storing FIFO entries + elem_t fifo_data_ignored; + tc_sram #( + .NumWords (TOT_CELLS), + .DataWidth (ELEM_SIZE), + .NumPorts (2) + ) i_fifo_data ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i ({push_i, 1'b1}), + .we_i ({push_i, 1'b0}), + .addr_i ({push_cell_idx, pop_cell_idx}), + .wdata_i ({new_el_i, {ELEM_SIZE{1'b0}}}), + .be_i ({{ELEM_SIZE_B{1'b1}}, {ELEM_SIZE_B{1'b0}}}), + .rdata_o ({fifo_data_ignored, data_o}) + ); + + //output + assign empty_o = (free_cells_q == '0); + + for (genvar i=0; i= NUM_CELLS); + + assign pop_cell_idx = fifo_head_q[fifo_pop_id_i]; + + always_comb begin + free_cells_d = free_cells_q; + + if (push_i) begin + free_cells_d[push_cell_idx] = 1'b1; + end + + if (pop_i) begin + free_cells_d[fifo_head_q[fifo_pop_id_i]] = 1'b0; + end + end + + //static cells occupation + always_comb begin + fifo_static_occup_d = fifo_static_occup_q; + + if (push_i && pop_i && fifo_push_id_i == fifo_pop_id_i) begin + //special case: we are pushing and popping from the same MPQ + case ({pushing_to_static, popping_from_static}) + 2'b10: fifo_static_occup_d[fifo_push_id_i] = fifo_static_occup_q[fifo_push_id_i] + 1; + 2'b01: fifo_static_occup_d[fifo_push_id_i] = fifo_static_occup_q[fifo_push_id_i] - 1; + endcase + end else begin + //we are popping/pushing on different MPQs or we are either popping or pushing + //to the same MPQ. + if (push_i && pushing_to_static) begin + fifo_static_occup_d[fifo_push_id_i] = fifo_static_occup_q[fifo_push_id_i] + 1; + end + + if (pop_i && popping_from_static) begin + fifo_static_occup_d[fifo_pop_id_i] = fifo_static_occup_q[fifo_pop_id_i] - 1; + end + end + end + + //pointers + always_comb begin + fifo_last_d = fifo_last_q; + fifo_head_d = fifo_head_q; + cells_d = cells_q; + fifo_empty_d = fifo_empty_q; + + if (push_i && pop_i && fifo_push_id_i == fifo_pop_id_i && cells_q[fifo_head_q[fifo_push_id_i]].is_last) begin + fifo_head_d[fifo_pop_id_i] = push_cell_idx; + fifo_last_d[fifo_push_id_i] = push_cell_idx; + + cells_d[push_cell_idx].is_last = 1'b1; + + end else begin + if (push_i) begin + + fifo_last_d[fifo_push_id_i] = push_cell_idx; + cells_d[push_cell_idx].is_last = 1'b1; + + if (fifo_empty_q[fifo_push_id_i]) begin + fifo_head_d[fifo_push_id_i] = push_cell_idx; + fifo_empty_d[fifo_push_id_i] = 1'b0; + end else begin + cells_d[fifo_last_q[fifo_push_id_i]].next = push_cell_idx; + cells_d[fifo_last_q[fifo_push_id_i]].is_last = 1'b0; + end + end + + if (pop_i) begin + fifo_head_d[fifo_pop_id_i] = cells_q[fifo_head_q[fifo_pop_id_i]].next; + fifo_empty_d[fifo_pop_id_i] = cells_q[fifo_head_q[fifo_pop_id_i]].is_last; + end + end + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + cells_q <= '0; + free_cells_q <= '0; + fifo_head_q <= '0; + fifo_last_q <= '0; + fifo_empty_q <= '1; + fifo_static_occup_q <= '0; + end else begin + cells_q <= cells_d; + free_cells_q <= free_cells_d; + fifo_head_q <= fifo_head_d; + fifo_last_q <= fifo_last_d; + fifo_empty_q <= fifo_empty_d; + fifo_static_occup_q <= fifo_static_occup_d; + end + end +endmodule diff --git a/hw/src/pkt_scheduler/hpu_driver.sv b/hw/src/pkt_scheduler/hpu_driver.sv new file mode 100644 index 0000000..6c738b9 --- /dev/null +++ b/hw/src/pkt_scheduler/hpu_driver.sv @@ -0,0 +1,884 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import pspin_cfg_pkg::*; + +module hpu_driver #( + parameter int C_CORE_ID = 0, + parameter int L1_PKT_BUFF_SIZE = 512, + parameter int NUM_CLUSTERS = 4, + parameter int NUM_SCRATCHPADS = 1, + parameter int NUM_HERS_PER_CLUSTER = 1, + parameter int L1_CLUSTER_BASE = 0, + parameter int L1_CLUSTER_MEM_SIZE = 0, + parameter int L1_RUNTIME_OFFSET = 0, + parameter int L1_SCRATCHPAD_SIZE = 4096, + parameter int NUM_CMDS = 4, + parameter int N_PMP_ENTRIES = 16 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [5:0] cluster_id_i, + + //task in + input logic hpu_task_valid_i, + output logic hpu_task_ready_o, + input hpu_handler_task_t hpu_task_i, + + //feedback out + output logic hpu_feedback_valid_o, + input logic hpu_feedback_ready_i, + output task_feedback_descr_t hpu_feedback_o, + + //high if we are ready to accept tasks + output logic hpu_active_o, + + //core interface + XBAR_PERIPH_BUS.Slave hpu_driver_slave_i, + + //high if this core has no pending DMA requests + input logic no_dma_req_pending_i, + + //command out + input logic cmd_ready_i, + output logic cmd_valid_o, + output pspin_cmd_t cmd_o, + + //command completion notification in + input logic cmd_resp_valid_i, + input pspin_cmd_resp_t cmd_resp_i, + + //PMP configuration + output logic pmp_conf_override_o, + output logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_o, + output logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_o +); + + logic no_pending_cmd; + + //request destination: 0: task_frontend; 1: cmd_frontend; + logic [1:0] add_type_d; + logic [1:0] add_type_q; + assign add_type_d = hpu_driver_slave_i.add[8:7]; + + //word idx (max 32 words per add_type) + //logic [4:0] add_idx; + //assign add_idx = hpu_driver_slave_i.add[6:2]; + + //tf: task frontend; cf: cmd frontend + logic [3:0] frontend_req; + logic [3:0] frontend_gnt; + logic [3:0] frontend_r_valid; + logic [3:0][31:0] frontend_r_rdata; + + logic can_send_feedback; + logic cmd_resp_valid; + logic disable_commands; + + //NOTE: frontends 2 and 3 are unused (reserved for future extensions) + for (genvar i=0; i<4; i++) begin + assign frontend_req[i] = hpu_driver_slave_i.req && (add_type_d == i); + end + + for (genvar i=2; i<4; i++) begin + assign frontend_gnt[i] = 1'b0; + assign frontend_r_valid[i] = 1'b0; + assign frontend_r_rdata[i] = '0; + end + + assign hpu_driver_slave_i.gnt = frontend_gnt[add_type_d]; + + //we need to remember which output to pick because this will (eventually) + //be valid at the next cycle. + assign hpu_driver_slave_i.r_rdata = frontend_r_rdata[add_type_q]; + assign hpu_driver_slave_i.r_valid = frontend_r_valid[add_type_q]; + + assign can_send_feedback = no_dma_req_pending_i && no_pending_cmd; + + assign cmd_resp_valid = cmd_resp_valid_i && cmd_resp_i.cmd_id.cluster_id == cluster_id_i && cmd_resp_i.cmd_id.core_id == C_CORE_ID; + + task_frontend #( + .C_CORE_ID (C_CORE_ID), + .L1_PKT_BUFF_SIZE (L1_PKT_BUFF_SIZE), + .NUM_CLUSTERS (NUM_CLUSTERS), + .NUM_SCRATCHPADS (NUM_SCRATCHPADS), + .NUM_HERS_PER_CLUSTER (NUM_HERS_PER_CLUSTER), + .L1_CLUSTER_BASE (L1_CLUSTER_BASE), + .L1_CLUSTER_MEM_SIZE (L1_CLUSTER_MEM_SIZE), + .L1_RUNTIME_OFFSET (L1_RUNTIME_OFFSET), + .L1_SCRATCHPAD_SIZE (L1_SCRATCHPAD_SIZE), + .N_PMP_ENTRIES (N_PMP_ENTRIES) + ) i_task_frontend ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .cluster_id_i (cluster_id_i), + .hpu_task_valid_i (hpu_task_valid_i), + .hpu_task_ready_o (hpu_task_ready_o), + .hpu_task_i (hpu_task_i), + .hpu_feedback_valid_o (hpu_feedback_valid_o), + .hpu_feedback_ready_i (hpu_feedback_ready_i), + .hpu_feedback_o (hpu_feedback_o), + .hpu_active_o (hpu_active_o), + .req_i (frontend_req[0]), + .add_i (hpu_driver_slave_i.add), + .wen_ni (hpu_driver_slave_i.wen), + .wdata_i (hpu_driver_slave_i.wdata), + .be_i (hpu_driver_slave_i.be), + .gnt_o (frontend_gnt[0]), + .r_rdata_o (frontend_r_rdata[0]), + .r_valid_o (frontend_r_valid[0]), + .can_send_feedback_i (can_send_feedback), + .pmp_conf_override_o (pmp_conf_override_o), + .pmp_cfg_o (pmp_cfg_o), + .pmp_addr_o (pmp_addr_o), + .disable_commands_o (disable_commands) + ); + + cmd_frontend #( + .C_CORE_ID (C_CORE_ID), + .NUM_CMDS (NUM_CMDS), + .NUM_BUFFERED_CMD (NUM_CMDS) + ) i_cmd_frontend ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .cluster_id_i (cluster_id_i), + .req_i (frontend_req[1]), + .add_i (hpu_driver_slave_i.add), + .wen_ni (hpu_driver_slave_i.wen), + .wdata_i (hpu_driver_slave_i.wdata), + .be_i (hpu_driver_slave_i.be), + .gnt_o (frontend_gnt[1]), + .r_rdata_o (frontend_r_rdata[1]), + .r_valid_o (frontend_r_valid[1]), + + .cmd_resp_valid_i (cmd_resp_valid), + .cmd_resp_i (cmd_resp_i), + + .disabled_i (disable_commands), + .no_pending_cmd_o (no_pending_cmd), + + .cmd_ready_i (cmd_ready_i), + .cmd_valid_o (cmd_valid_o), + .cmd_o (cmd_o) + ); + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + add_type_q <= '0; + end else begin + add_type_q <= add_type_d; + end + end + +endmodule + + +module task_frontend #( + parameter int C_CORE_ID = 0, + parameter int L1_PKT_BUFF_SIZE = 512, + parameter int NUM_CLUSTERS = 4, + parameter int NUM_SCRATCHPADS = 1, + parameter int NUM_HERS_PER_CLUSTER = 1, + parameter int L1_CLUSTER_BASE = 0, + parameter int L1_CLUSTER_MEM_SIZE = 0, + parameter int L1_RUNTIME_OFFSET = 0, + parameter int L1_SCRATCHPAD_SIZE = 4096, + parameter int N_PMP_ENTRIES = 16 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [5:0] cluster_id_i, + + //task in + input logic hpu_task_valid_i, + output logic hpu_task_ready_o, + input hpu_handler_task_t hpu_task_i, + + //feedback out + output logic hpu_feedback_valid_o, + input logic hpu_feedback_ready_i, + output task_feedback_descr_t hpu_feedback_o, + + output logic hpu_active_o, + + input logic req_i, + input logic [31:0] add_i, + input logic wen_ni, + input logic [31:0] wdata_i, + input logic [3:0] be_i, + output logic gnt_o, + output logic [31:0] r_rdata_o, + output logic r_valid_o, + + output logic disable_commands_o, + input logic can_send_feedback_i, + + output logic pmp_conf_override_o, + output logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_o, + output logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_o +); + + typedef enum logic [1:0] {Init, Idle, Running, SendingFeedback} state_t; + state_t state_d, state_q; + + hpu_handler_task_t current_task_q, current_task_d; + + logic trigger_feedback; + + logic valid_d, valid_q; + logic [31:0] rdata_d, rdata_q; + + logic [$clog2(NUM_SCRATCHPADS)-1:0] scratchpad_id; + logic [$clog2(NUM_CLUSTERS)-1:0] home_cluster_id; + + logic [31:0] l1_pkt_base_addr; // in this cluster + logic [NUM_CLUSTERS-1:0][31:0] l1_scratchpad_addr; //in the home cluster + + logic [31:0] l1_base_addr; + logic [31:0] l1_home_base_addr; + logic [31:0] l1_pkt_addr; + + logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_q; + logic [N_PMP_ENTRIES-1:0] [31:0] pmp_addr_d; + logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_q; + logic [N_PMP_ENTRIES-1:0] [7:0] pmp_cfg_d; + + + logic [31:0] handler_error_code; + logic handler_error; + + //buffer feedback waiting for command to complete + //NOTE: only one feedback at time can be buffered with this implementation! + task_feedback_descr_t hpu_feedback; + logic feedback_buff_full, feedback_buff_empty; + logic feedback_buff_push; + fifo_v3 #( + .dtype (task_feedback_descr_t), + .DEPTH (1) + ) i_hpu_cmd_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (feedback_buff_full), + .empty_o (feedback_buff_empty), + .usage_o (), + .data_i (hpu_feedback), + .push_i (feedback_buff_push), + .data_o (hpu_feedback_o), + .pop_i (hpu_feedback_ready_i && hpu_feedback_valid_o) + ); + + assign feedback_buff_push = !feedback_buff_full && (trigger_feedback || state_q==SendingFeedback); + assign disable_commands_o = !feedback_buff_empty; + + assign r_rdata_o = rdata_q; + assign r_valid_o = valid_q; + + //this way of determining addresses is super ugly but don't know how to make it nicer + assign scratchpad_id = current_task_q.handler_task.msgid[$clog2(NUM_CLUSTERS)+$clog2(NUM_SCRATCHPADS)-1:$clog2(NUM_CLUSTERS)]; + assign home_cluster_id = current_task_q.handler_task.msgid[$clog2(NUM_CLUSTERS)-1:0]; + assign l1_base_addr = (L1_CLUSTER_BASE + cluster_id_i * L1_CLUSTER_MEM_SIZE); + assign l1_pkt_base_addr = l1_base_addr + L1_RUNTIME_OFFSET; + assign l1_pkt_addr = current_task_q.pkt_ptr; + + for (genvar i=0; i= 4 && add_idx <= 10 && ~wen_ni) begin //command definition (words) + cmd_d.descr.words[add_idx - 4] = wdata_i; + end + end + end + + //assigning ID to command when issued + always_comb begin + cmd_d.cmd_id.local_cmd_id = cmd_q.cmd_id.local_cmd_id; + + case (state_q) + WaitingID: begin + if (cmd_resp_valid_i) begin + cmd_d.cmd_id.local_cmd_id = cmd_resp_i.cmd_id.local_cmd_id; + end + end + default: begin + if (assign_id) begin + cmd_d.cmd_id.local_cmd_id = cmd_idx; + end + end + endcase + end + + //command issuing + always_comb begin + rdata_d = rdata_q; + + case (state_q) + Ready: begin + if (cmd_issued) begin + rdata_d = cmd_idx; + end + + if (test_issued) begin + rdata_d = (wt_cmd_finished) ? 32'h0000_0001 : '0; + end + end + + Waiting: begin + if (cmd_resp_valid_i) begin + rdata_d = cmd_resp_i.cmd_id.local_cmd_id; + end + end + endcase + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + state_q <= Ready; + free_cmd_ids_q <= '0; + wt_cmd_idx_q <= '0; + rvalid_q <= 1'b0; + rdata_q <= '0; + cmd_q <= '0; + end else begin + state_q <= state_d; + free_cmd_ids_q <= free_cmd_ids_d; + wt_cmd_idx_q <= wt_cmd_idx_d; + rvalid_q <= rvalid_d; + rdata_q <= rdata_d; + cmd_q <= cmd_d; + end + end +endmodule diff --git a/hw/src/pkt_scheduler/mpq_engine.sv b/hw/src/pkt_scheduler/mpq_engine.sv new file mode 100644 index 0000000..95c7af7 --- /dev/null +++ b/hw/src/pkt_scheduler/mpq_engine.sv @@ -0,0 +1,538 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import pspin_cfg_pkg::*; + +module mpq_engine #( + parameter int NUM_HER_SLOTS = 64, + parameter int NUM_MPQ = 8 +) +( + input logic clk_i, + input logic rst_ni, + + //from pkt gen + output logic her_ready_o, + input logic her_valid_i, + input her_descr_t her_i, + + //termination signal + input logic eos_i, + + //mpq ready signal + output logic [NUM_MPQ-1:0] mpq_full_o, + + //from feedback engine + output logic feedback_ready_o, + input logic feedback_valid_i, + input feedback_descr_t feedback_i, + + //to scheduler + input logic task_ready_i, + output logic task_valid_o, + output handler_task_t task_o, + + //to pktgen + input logic nic_feedback_ready_i, + output logic nic_feedback_valid_o, + output feedback_descr_t nic_feedback_o +); + typedef struct packed { + mem_addr_t pkt_addr; + mem_size_t pkt_size; + } mpq_pkt_t; + + localparam int unsigned MPQ_META_LEN = $bits(mpq_meta_t); + localparam int unsigned MPQ_META_LEN_B = MPQ_META_LEN/8; + + // MPQ engine state. This is mainly to handle the case in which + // task_ready_i is not asserted and enable pipelining between + // reading from MPQ meta memory and defining output task + typedef enum logic [2:0] {Idle, Ready, Stalled} mpqeng_state_t; + mpqeng_state_t state_q, state_d; + + // MPQ state. I don't think we can move this too to memory :( + mpq_t [NUM_MPQ-1:0] mpq_q; + mpq_t [NUM_MPQ-1:0] mpq_d; + + // Flag saying if an MPQ is ready or not + logic [NUM_MPQ-1:0] mpq_valid; + + // Flag saying if an MPQ is being used or not + logic [NUM_MPQ-1:0] mpq_busy; + + // ID of the MPQ for which we received a new HER + logic [$clog2(NUM_MPQ)-1:0] newher_mpq_idx; + + // ID of the MPQ which we are sending a task from + logic [$clog2(NUM_MPQ)-1:0] tasksent_mpq_idx; + + // ID of the MPQ for which we received a task + logic [$clog2(NUM_MPQ)-1:0] feedback_mpq_idx; + + // aribitrate ready MPQs + logic [$clog2(NUM_MPQ)-1:0] mpq_arb_idx; + + // Next packet to schedule for each MPQ + mpq_pkt_t mpq_head; + + // New packet to push in the fifo_engine + mpq_pkt_t new_pkt; + + // We store the handler_task in order to use it in case we get stalled + handler_task_t task_q, task_d, new_task; + + // We use these registers to rember info about the currently selected MPQ. + // We need to way one cycle to get the output from memory and use that, + // toghether with these info, to build the output. + mpq_state_t mpq_out_state_d, mpq_out_state_q; + logic [$clog2(NUM_MPQ)-1:0] selected_mpq_d; + logic [$clog2(NUM_MPQ)-1:0] selected_mpq_q; + + // push/pop drivers for FIFO engine + logic fifo_push, fifo_pop; + + // flag saying if the FIFO engine is empty of full + // NOTE: fifo_empty is only used in assertions + logic fifo_empty; + logic [NUM_MPQ-1:0] fifo_full; + + // Updated MPQs from the FSMs output + mpq_t newher_mpq_fsm_s, tasksent_mpq_fsm_s, feedback_mpq_fsm_s; + + // Flags saying if the FSMs' output is valid + logic newher_mpq_fsm_update, tasksent_mpq_fsm_update, feedback_mpq_fsm_update; + + // True if we are writing to the MPQ meta memory + logic mpqmeta_write; + + // True if we are reading from MPQ meta memory + logic mpqmeta_read; + + // Flag used in the defintion of the output task (ugly). + logic new_task_triggers_feedback_q, new_task_triggers_feedback_d; + + // Read output of the MPQ meta memory + mpq_meta_t mpqmeta_read_mpq; + mpq_meta_t mpqmeta_read_mpq_ignored; + + // ready/valid for arbiter + logic arb_ready, arb_valid; + + assign mpq_full_o = fifo_full; + + // define the MPQ indices for the different events + assign newher_mpq_idx = her_i.msgid[$clog2(NUM_MPQ)-1:0]; + assign tasksent_mpq_idx = mpq_arb_idx; //this one comes one cycle before task_o! + assign feedback_mpq_idx = feedback_i.msgid[$clog2(NUM_MPQ)-1:0]; + + // Here we store the packets that are queued for each MPQ + assign new_pkt.pkt_addr = her_i.her_addr; + assign new_pkt.pkt_size = her_i.xfer_size; + + assign fifo_push = her_ready_o && her_valid_i; + + // Note: this is quite ugly, should be fixed. + assign fifo_pop = (arb_ready && arb_valid && ( + (mpq_q[tasksent_mpq_idx].state == Payload && mpq_d[tasksent_mpq_idx].state == Payload) || /* pop payload packets but not the eom */ + (mpq_q[tasksent_mpq_idx].state == Payload && mpq_d[tasksent_mpq_idx].state == PayloadDraining && !mpq_d[tasksent_mpq_idx].has_completion) || /* pop eom already if there is no completion handler */ + (mpq_q[tasksent_mpq_idx].state == Completion) /* pop EOM when the completion is sent */ + )); + + fifo_engine #( + .NUM_CELLS(NUM_HER_SLOTS), + .NUM_STATIC_CELLS_PER_FIFO(NUM_MPQ_STATIC_CELLS), + .NUM_FIFO(NUM_MPQ), + .elem_t(mpq_pkt_t) + ) i_fifo_engine ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .new_el_i (new_pkt), + .push_i (fifo_push), + .fifo_push_id_i (newher_mpq_idx), + .pop_i (fifo_pop), + .fifo_pop_id_i (tasksent_mpq_idx), + .data_o (mpq_head), + .empty_o (fifo_empty), + .fifo_full_o (fifo_full) + ); + + // MPQ metadata memory + assign mpqmeta_write = her_valid_i && her_ready_o && !mpq_busy[newher_mpq_idx]; + assign mpqmeta_read = arb_ready && arb_valid; + + tc_sram #( + .NumWords (NUM_MPQ), + .DataWidth (MPQ_META_LEN), + .NumPorts (2) + ) i_mpq_meta_mem ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i ({mpqmeta_write, mpqmeta_read}), + .we_i ({mpqmeta_write, 1'b0}), + .addr_i ({newher_mpq_idx, tasksent_mpq_idx}), + .wdata_i ({her_i.mpq_meta, {MPQ_META_LEN{1'b0}}}), + .be_i ({{MPQ_META_LEN_B{1'b1}}, {MPQ_META_LEN_B{1'b0}}}), + .rdata_o ({mpqmeta_read_mpq_ignored, mpqmeta_read_mpq}) + ); + + // Select a ready MPQ + rr_arb_tree #( + .NumIn (NUM_MPQ), + .DataWidth (0), + .ExtPrio (0), + .AxiVldRdy (1), + .LockIn (1) + ) i_mpq_rr_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .rr_i ('0), + .req_i (mpq_valid), + .gnt_o (), + .data_i (), + .gnt_i (arb_ready), + .req_o (arb_valid), + .data_o (), + .idx_o (mpq_arb_idx) + ); + + // Define state + always_comb begin + state_d = state_q; + arb_ready = 1'b0; + + case (state_q) + Idle: begin + if (arb_valid == 1'b1) begin + state_d = Ready; + arb_ready = 1'b1; + end + end + Ready: begin + if (task_ready_i == 1'b0) begin + state_d = Stalled; + end else begin + state_d = (arb_valid == 1'b1) ? Ready : Idle; + arb_ready = (arb_valid == 1'b1); + end + end + Stalled: begin + if (task_ready_i == 1'b1) begin + state_d = (arb_valid == 1'b1) ? Ready : Idle; + arb_ready = (arb_valid == 1'b1); //to pipeline next memory read + end + end + endcase + end + + // Define output + // we delay mpq_arb_idx because the the memory read output will be + // ready at the next cycle + + assign task_valid_o = (state_q == Ready || state_q == Stalled); + + //this seems overworked.. + assign task_o = (state_q==Ready) ? new_task : task_q; + assign task_d = (state_q==Ready) ? new_task : task_q; + + assign mpq_out_state_d = (arb_ready && arb_valid) ? mpq_q[tasksent_mpq_idx].state : mpq_out_state_q; + assign selected_mpq_d = (arb_ready && arb_valid) ? tasksent_mpq_idx : selected_mpq_q; + assign new_task_triggers_feedback_d = (arb_ready && arb_valid) ? fifo_pop : new_task_triggers_feedback_q; + + always_comb begin + case (mpq_out_state_q) + Header: begin + new_task.handler_fun = mpqmeta_read_mpq.hh_addr; + new_task.handler_fun_size = mpqmeta_read_mpq.hh_size; + new_task.pkt_addr = mpq_head.pkt_addr; + new_task.pkt_size = mpq_head.pkt_size; + new_task.trigger_feedback = new_task_triggers_feedback_q; + end + + Payload: begin + new_task.handler_fun = mpqmeta_read_mpq.ph_addr; + new_task.handler_fun_size = mpqmeta_read_mpq.ph_size; + new_task.pkt_addr = mpq_head.pkt_addr; + new_task.pkt_size = mpq_head.pkt_size; + new_task.trigger_feedback = new_task_triggers_feedback_q; + end + + Completion: begin + new_task.handler_fun = mpqmeta_read_mpq.th_addr; + new_task.handler_fun_size = mpqmeta_read_mpq.th_size; + new_task.pkt_addr = mpq_head.pkt_addr; + new_task.pkt_size = mpq_head.pkt_size; + new_task.trigger_feedback = new_task_triggers_feedback_q; + end + + default: begin + new_task.handler_fun = '0; + new_task.handler_fun_size = '0; + new_task.pkt_addr = '0; + new_task.pkt_size = '0; + new_task.trigger_feedback = 1'b0; + end + endcase + end + + assign new_task.msgid = selected_mpq_q; + assign new_task.handler_mem_addr = mpqmeta_read_mpq.handler_mem_addr; + assign new_task.handler_mem_size = mpqmeta_read_mpq.handler_mem_size; + assign new_task.host_mem_addr = mpqmeta_read_mpq.host_mem_addr; + assign new_task.host_mem_size = mpqmeta_read_mpq.host_mem_size; + + for (genvar i = 0; i< pspin_cfg_pkg::NUM_CLUSTERS; i++) begin: gen_task_scratchpad + assign new_task.scratchpad_addr[i] = mpqmeta_read_mpq.scratchpad_addr[i]; + assign new_task.scratchpad_size[i] = mpqmeta_read_mpq.scratchpad_size[i]; + end + + // Update MPQ state + // This unit might have to process at most three MPQs at the same time: + // - the MPQ for which we get a new HER, + // - the MPQ for which we get a completion feedback, + // - the MPQ that gets selected to send a new task. + // For this reason, we keep three mpq_fsm. It can happen that two or all FSM + // will be fed with the same MPQ (e.g., getting a new HER and a completion feedback + // for the same MPQ in the same cycle). In that case, the FSM will produce the same + // output state, so it does not matter which output gets written. + mpq_fsm #( + ) i_newher_mpq_fsm ( + .her_new_i (her_valid_i && her_ready_o), + .task_sent_i (arb_valid && arb_ready && tasksent_mpq_idx == newher_mpq_idx), + .feedback_i (feedback_valid_i && feedback_ready_o && feedback_mpq_idx == newher_mpq_idx), + + .her_new_has_hh_i (her_i.mpq_meta.hh_addr != '0), + .her_new_has_th_i (her_i.mpq_meta.th_addr != '0), + .her_new_is_eom_i (her_i.eom), + + .mpq_q (mpq_q[newher_mpq_idx]), + .mpq_o (newher_mpq_fsm_s), + + .update_o (newher_mpq_fsm_update) + ); + + mpq_fsm #( + ) i_tasksent_mpq_fsm ( + .her_new_i (her_valid_i && her_ready_o && newher_mpq_idx == tasksent_mpq_idx), + .task_sent_i (arb_valid && arb_ready), + .feedback_i (feedback_valid_i && feedback_ready_o && feedback_mpq_idx == tasksent_mpq_idx), + + .her_new_has_hh_i (her_i.mpq_meta.hh_addr != '0), + .her_new_has_th_i (her_i.mpq_meta.th_addr != '0), + .her_new_is_eom_i (her_i.eom), + + .mpq_q (mpq_q[tasksent_mpq_idx]), + .mpq_o (tasksent_mpq_fsm_s), + + .update_o (tasksent_mpq_fsm_update) + ); + + mpq_fsm #( + ) i_feedback_mpq_fsm ( + .her_new_i (her_valid_i && her_ready_o && newher_mpq_idx == feedback_mpq_idx), + .task_sent_i (arb_valid && arb_ready && feedback_mpq_idx == tasksent_mpq_idx), + .feedback_i (feedback_valid_i && feedback_ready_o), + + .her_new_has_hh_i (her_i.mpq_meta.hh_addr != '0), + .her_new_has_th_i (her_i.mpq_meta.th_addr != '0), + .her_new_is_eom_i (her_i.eom), + + .mpq_q (mpq_q[feedback_mpq_idx]), + .mpq_o (feedback_mpq_fsm_s), + + .update_o (feedback_mpq_fsm_update) + ); + + always_comb begin + mpq_d = mpq_q; + + if (newher_mpq_fsm_update) begin + mpq_d[newher_mpq_idx] = newher_mpq_fsm_s; + end + + if (tasksent_mpq_fsm_update) begin + mpq_d[tasksent_mpq_idx] = tasksent_mpq_fsm_s; + end + + if (feedback_mpq_fsm_update) begin + mpq_d[feedback_mpq_idx] = feedback_mpq_fsm_s; + end + end + + // Define valid/busy MPQs + for (genvar i=0; i 0) || + (mpq_q[i].state == Completion)); + assign mpq_busy[i] = (mpq_q[i].state != Free); + end + + // Define ready signal on the HER input interface. We can + // get a new HER if the MPQ to which the HER will go has space. + assign her_ready_o = !fifo_full[newher_mpq_idx]; //((~fifo_full) != '0); + + // Forward the feedback to the NIC inbound engine + assign feedback_ready_o = nic_feedback_ready_i; + assign nic_feedback_valid_o = feedback_valid_i && feedback_i.trigger_feedback == 1'b1; + assign nic_feedback_o = feedback_i; + + // Sequential + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + mpq_q <= '0; + selected_mpq_q <= '0; + state_q <= Idle; + mpq_out_state_q <= Free; + task_q <= '0; + new_task_triggers_feedback_q <= 1'b0; + end else begin + mpq_q <= mpq_d; + selected_mpq_q <= selected_mpq_d; + state_q <= state_d; + mpq_out_state_q <= mpq_out_state_d; + task_q <= task_d; + new_task_triggers_feedback_q <= new_task_triggers_feedback_d; + end + end + + // Simulation only + // pragma translate_off + `ifndef VERILATOR + initial begin + forever begin + @(posedge clk_i); + if (feedback_ready_o && feedback_valid_i) begin + $display("%0d MPQ engine got feedback for msg id %0d", $time, feedback_i.msgid); + end + + if (her_ready_o && her_valid_i) begin + $display("%0d MPQ engine got new packet for msg id %0d", $time, her_i.msgid); + end + + end + end + + // Assertions + nonempty : assert property( + @(posedge clk_i) (mpq_busy=='0 && eos_i) |-> (fifo_empty)) + else $fatal (1, "Termination detected but there still are packets to process!"); + + for (genvar i=0; i (~(mpq_d[i].length) != '0)) + else $fatal (1, "MPQ length is negative!"); + + negativeinflight: assert property( + @(posedge clk_i) (mpq_q[i].in_flight == '0) |-> (~(mpq_d[i].in_flight) != '0)) + else $fatal (1, "MPQ in_flight is negative!"); + end + `endif + // pragma translate_on + + +endmodule + +module mpq_fsm #( +) ( + + // events + input logic her_new_i, // got a new HER + input logic task_sent_i, // got selected for sending a task + input logic feedback_i, // got a completion feedback + + //info on the new HER, if any (used only if her_new_i is asserted) + input logic her_new_has_hh_i, // Asserted if the new HER as a header handler + input logic her_new_has_th_i, // Asserted if the new HER as a completion handler + input logic her_new_is_eom_i, // Asserted if the new HER is flagged as EOM + + input mpq_t mpq_q, // current state + output mpq_t mpq_o, // new state + + output logic update_o // asserted if mpq_o is valid +); + + logic pushing_her, popping_her; + assign pushing_her = her_new_i; + assign popping_her = (task_sent_i && mpq_q.state == Payload); + + assign update_o = her_new_i || task_sent_i || feedback_i; + + //update MPQ length + always_comb begin + case ({pushing_her, popping_her}) + 2'b10 : mpq_o.length = mpq_q.length + 1; + 2'b01 : mpq_o.length = mpq_q.length - 1; + default : mpq_o.length = mpq_q.length; + endcase + end + + always_comb begin + case ({task_sent_i, feedback_i}) + 2'b10 : mpq_o.in_flight = mpq_q.in_flight + 1; + 2'b01 : mpq_o.in_flight = mpq_q.in_flight - 1; + default : mpq_o.in_flight = mpq_q.in_flight; + endcase + end + + assign mpq_o.eom_seen = mpq_q.eom_seen || (her_new_i && her_new_is_eom_i); + + //update state + always_comb begin //H-P-C case + + mpq_o.state = mpq_q.state; + mpq_o.has_completion = mpq_q.has_completion; + + case (mpq_q.state) + Free: begin + if (her_new_i) begin + mpq_o.state = (her_new_has_hh_i) ? Header : Payload; + mpq_o.has_completion = her_new_has_th_i; + end + end + + Header: begin + if (task_sent_i) begin + mpq_o.state = HeaderRunning; + end + end + + HeaderRunning: begin + if (feedback_i) begin + mpq_o.state = Payload; + end + end + + Payload: begin + if (task_sent_i && mpq_q.eom_seen && mpq_q.length == 1) begin + mpq_o.state = PayloadDraining; + end + end + + PayloadDraining: begin + if (feedback_i && mpq_q.in_flight == 1) begin + mpq_o.state = (mpq_q.has_completion) ? Completion : Free; + end + end + + Completion: begin + if (task_sent_i) begin + mpq_o.state = CompletionRunning; + end + end + + CompletionRunning: begin + if (feedback_i) begin + mpq_o.state = Free; + end + end + endcase + end +endmodule diff --git a/hw/src/pkt_scheduler/scheduler.sv b/hw/src/pkt_scheduler/scheduler.sv new file mode 100644 index 0000000..0dd522a --- /dev/null +++ b/hw/src/pkt_scheduler/scheduler.sv @@ -0,0 +1,293 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import pspin_cfg_pkg::*; + +/** + NOTE: this module needs to be revisioned because by introducing a packet buffer in L1 we don't have + the concept of "packet slots" anymore. The cluster_occup_i signal should be signal the available space + instead of the number of available packet slots. +**/ + +module scheduler #( + parameter int NUM_CLUSTERS = 4, + parameter int NUM_HERS_PER_CLUSTER = 64 +) ( + input logic clk_i, + input logic rst_ni, + + //input IF from MPQ engine + input logic task_valid_i, + output logic task_ready_o, + input handler_task_t task_descr_i, + + //output IF to cluster schedulers + output logic [NUM_CLUSTERS-1:0] cluster_task_valid_o, + input logic [NUM_CLUSTERS-1:0] cluster_task_ready_i, + output handler_task_t [NUM_CLUSTERS-1:0] cluster_task_descr_o, + + //input IF from clusters for the feedbacks + input logic [NUM_CLUSTERS-1:0] cluster_feedback_valid_i, + output logic [NUM_CLUSTERS-1:0] cluster_feedback_ready_o, + input feedback_descr_t [NUM_CLUSTERS-1:0] cluster_feedback_i, + + //output IF to pktgen for feedbacks + output logic pktgen_feedback_valid_o, + input logic pktgen_feedback_ready_i, + output feedback_descr_t pktgen_feedback_o + +); + + ///////////////////////// + /// Cluster interface /// + ///////////////////////// + + // We use these registers to cut the combinatorial network from + // the uncluster (outside a cluster) to inside a cluster. This helps + // defining domains and to close timings separately. It also reduces + // paths lengths. + logic [NUM_CLUSTERS-1:0] cluster_task_valid_od; + logic [NUM_CLUSTERS-1:0] cluster_task_ready_id; + handler_task_t [NUM_CLUSTERS-1:0] cluster_task_descr_od; + + logic [NUM_CLUSTERS-1:0] cluster_feedback_valid_iq; + logic [NUM_CLUSTERS-1:0] cluster_feedback_ready_oq; + feedback_descr_t [NUM_CLUSTERS-1:0] cluster_feedback_iq; + + for (genvar i=0; i= MAX_OCC) ? 1'b1 : 1'b0; + assign can_use_home_cluster = (no_cluster_avail || (cluster_occup_q[home_cluster_id] < MAX_OCC && cluster_task_ready_id[home_cluster_id])); + assign sel_cluster_id = (can_use_home_cluster) ? home_cluster_id : c_occup_min; + assign cluster_id_d = (state_q == ServePacket) ? sel_cluster_id : cluster_id_q; + + //task is put on all the output interfaces. Only the selected cluster ID will have + //cluster_valid_o[i] set. + for (genvar i = 0; i < NUM_CLUSTERS; i++) begin : gen_cluster_task + assign cluster_task_descr_od[i] = (state_q == ServePacket) ? task_descr_i : task_q; + assign cluster_task_valid_od[i] = (cluster_id_d == i) && serving_cluster; + end + + always_comb begin + int i; + state_d = state_q; + task_ready_o = 1'b0; + serving_cluster = 1'b0; + + case (state_q) + ServePacket: begin + serving_cluster = 1'b0; + + if (task_valid_i && !no_cluster_avail) begin + task_ready_o = 1'b1; //signal that we recvd the data + state_d = (cluster_task_ready_id[cluster_id_d]) ? ServePacket : WaitTransfer; + serving_cluster = 1'b1; + end + end + WaitTransfer: begin + serving_cluster = 1'b1; + if ((cluster_task_ready_id[cluster_id_q])) begin + state_d = ServePacket; + end + end + default: begin + state_d = ServePacket; + end + + endcase + end + + argmin4 #( + .VALUE_WIDTH ($clog2(NUM_HERS_PER_CLUSTER)+1) + ) i_argmin4 ( + .values_i(cluster_occup_q), + .enabled_i(cluster_task_ready_id), + .argmin_o(c_occup_min) + ); + + /** sequential part **/ + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + state_q <= ServePacket; + cluster_id_q <= '0; + task_q <= '0; + cluster_occup_q <= '0; + end else begin + state_q <= state_d; + cluster_id_q <= cluster_id_d; + task_q <= task_d; + cluster_occup_q <= cluster_occup_d; + end + end + + /** simulation **/ + /* + initial begin + forever begin + @(posedge clk_i); + if (task_valid_i && task_ready_o) begin + $display("[sched] msg_id: %0d; cluster_id: %0d; occupation: %0d; no_cluster_avail: %0d", task_descr_i.msgid, cluster_id_d, cluster_occup_iq[cluster_id_d], no_cluster_avail); + end + end + end + */ + + // pragma translate_off + `ifndef VERILATOR + initial begin + static int start_time = 0; + forever begin + @(posedge clk_i); + if (task_valid_i && task_ready_o && start_time == 0) begin + start_time = $stime; + end + + if (task_valid_i && task_ready_o) begin + $display("%0d INFO TASK %0d %0d", $stime, task_descr_i.msgid, ($stime - start_time)); + end + + if (pktgen_feedback_valid_o && pktgen_feedback_ready_i) begin + $display("%0d INFO FEEDBACK %0d %0d", $stime, pktgen_feedback_o.msgid, ($stime - start_time)); + end + end + end + `endif + // pragma translate_on + + ///////////////////////////////////////////////////// + /// Arbitrating feedbacks from cluster schedulers /// + ///////////////////////////////////////////////////// + + //logic [$clog2(NUM_CLUSTERS)-1:0] cluster_idx_arb; + rr_arb_tree #( + .NumIn (NUM_CLUSTERS), + .DataType (feedback_descr_t), + .ExtPrio (0), + .AxiVldRdy (1), + .LockIn (1) + ) i_rr_arb_tree ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .rr_i ('0), + .req_i (cluster_feedback_valid_iq), + .gnt_o (cluster_feedback_ready_oq), + .data_i (cluster_feedback_iq), + .gnt_i (pktgen_feedback_ready_i), + .req_o (pktgen_feedback_valid_o), + .data_o (pktgen_feedback_o), + .idx_o () + ); + +endmodule + +module argmin4 #( + VALUE_WIDTH = 64 +) +( + input logic [3:0][VALUE_WIDTH-1:0] values_i, + input logic [3:0] enabled_i, + output logic [1:0] argmin_o +); + logic [1:0] min_l0; + logic [1:0] min_l1; + + logic [3:0][VALUE_WIDTH-1:0] values; + + assign values[0] = (enabled_i[0]) ? values_i[0] : {VALUE_WIDTH{1'b1}}; + assign values[1] = (enabled_i[1]) ? values_i[1] : {VALUE_WIDTH{1'b1}}; + assign values[2] = (enabled_i[2]) ? values_i[2] : {VALUE_WIDTH{1'b1}}; + assign values[3] = (enabled_i[3]) ? values_i[3] : {VALUE_WIDTH{1'b1}}; + + assign min_l0[1:0] = (values[0] <= values[1]) ? 2'b00 : 2'b01; + assign min_l1[1:0] = (values[2] <= values[3]) ? 2'b10 : 2'b11; + assign argmin_o[1:0] = (values[min_l0] <= values[min_l1]) ? min_l0 : min_l1; +endmodule \ No newline at end of file diff --git a/hw/src/pspin.sv b/hw/src/pspin.sv new file mode 100644 index 0000000..308136b --- /dev/null +++ b/hw/src/pspin.sv @@ -0,0 +1,865 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module pspin #( + parameter int unsigned N_CLUSTERS = 0, + parameter int N_MPQ = 0 +) ( + // Clocks and Resets + input logic clk_i, + input logic rst_ni, + + // Cluster Control + input logic [N_CLUSTERS-1:0] cl_fetch_en_i, + output logic [N_CLUSTERS-1:0] cl_eoc_o, + output logic [N_CLUSTERS-1:0] cl_busy_o, + + AXI_BUS.Slave axi_ni_slv, //NIC inbound slave port: to inject packets + AXI_BUS.Slave axi_no_slv, //NIC outbound slave port: to read data to send out + AXI_BUS.Master axi_host_mst, // Host master port: to write to host memory + AXI_BUS.Slave axi_host_slv, // Host slave port: to let the host write to L2 prog mem and L2 handler mem + + //from pktgen + output logic her_ready_o, + input logic her_valid_i, + input pspin_cfg_pkg::her_descr_t her_i, + + //termination signal + input logic eos_i, + + //MPQ full signal + output logic [N_MPQ-1:0] mpq_full_o, + + //to pktgen + input logic nic_feedback_ready_i, + output logic nic_feedback_valid_o, + output pspin_cfg_pkg::feedback_descr_t nic_feedback_o, + + output logic pspin_active_o, + + input logic nic_cmd_ready_i, + output logic nic_cmd_valid_o, + output pspin_cfg_pkg::pspin_cmd_t nic_cmd_o, + + input logic nic_cmd_resp_valid_i, + input pspin_cfg_pkg::pspin_cmd_resp_t nic_cmd_resp_i +); + + import pspin_cfg_pkg::AXI_AW; + import pspin_cfg_pkg::HOST_AXI_AW; + import pspin_cfg_pkg::addr_t; + import pspin_cfg_pkg::AXI_WIDE_DW; + import pspin_cfg_pkg::data_t; + import pspin_cfg_pkg::strb_t; + import pspin_cfg_pkg::AXI_IW; + import pspin_cfg_pkg::id_t; + import pspin_cfg_pkg::AXI_UW; + import pspin_cfg_pkg::user_t; + import pspin_cfg_pkg::aw_t; + import pspin_cfg_pkg::w_t; + import pspin_cfg_pkg::b_t; + import pspin_cfg_pkg::ar_t; + import pspin_cfg_pkg::r_t; + import pspin_cfg_pkg::req_t; + import pspin_cfg_pkg::resp_t; + import pspin_cfg_pkg::host_req_t; + import pspin_cfg_pkg::host_resp_t; + import pspin_cfg_pkg::PKT_MEM_SIZE; + import pspin_cfg_pkg::HND_MEM_SIZE; + import pspin_cfg_pkg::L1_CLUSTER_BASE; + import pspin_cfg_pkg::L1_CLUSTER_MEM_SIZE; + localparam int unsigned L2_SIZE = pulp_cluster_cfg_pkg::L2_SIZE; + + // Interface from NIC inbound + req_t ni_req; + resp_t ni_resp; + `AXI_ASSIGN_TO_REQ(ni_req, axi_ni_slv) + `AXI_ASSIGN_FROM_RESP(axi_ni_slv, ni_resp) + + // Interface from NIC outbound + req_t no_req; + resp_t no_resp; + `AXI_ASSIGN_TO_REQ(no_req, axi_no_slv) + `AXI_ASSIGN_FROM_RESP(axi_no_slv, no_resp) + + // Interface to Host + host_req_t host_mst_req; + host_resp_t host_mst_resp; + `AXI_ASSIGN_FROM_REQ(axi_host_mst, host_mst_req) + `AXI_ASSIGN_TO_RESP(host_mst_resp, axi_host_mst) + + host_req_t host_mst_soc_dma_req, host_mst_hdir_req; + host_resp_t host_mst_soc_dma_resp, host_mst_hdir_resp; + + // Interface from Host + req_t host_slv_req; + resp_t host_slv_resp; + `AXI_ASSIGN_TO_REQ(host_slv_req, axi_host_slv) + `AXI_ASSIGN_FROM_RESP(axi_host_slv, host_slv_resp) + + // Interface from NHI interconnect to cluster noc + req_t nhi_req; + resp_t nhi_resp; + + // Interfaces to Clusters + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_SLV), + .AXI_USER_WIDTH (AXI_UW) + ) cl_inp[N_CLUSTERS-1:0](); + pulp_cluster_cfg_pkg::req_slv_t [N_CLUSTERS-1:0] cl_inp_req; + pulp_cluster_cfg_pkg::resp_slv_t [N_CLUSTERS-1:0] cl_inp_resp; + for (genvar i = 0; i < N_CLUSTERS; i++) begin : gen_assign_cl_inp + `AXI_ASSIGN_FROM_REQ(cl_inp[i], cl_inp_req[i]) + `AXI_ASSIGN_TO_RESP(cl_inp_resp[i], cl_inp[i]) + end + AXI_BUS_ASYNC #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_SLV), + .AXI_USER_WIDTH (AXI_UW), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) cl_inp_async[N_CLUSTERS-1:0](); + + // Interfaces from Clusters + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_MST), + .AXI_USER_WIDTH (AXI_UW) + ) cl_oup[N_CLUSTERS-1:0](); + pulp_cluster_cfg_pkg::req_mst_t [N_CLUSTERS-1:0] cl_oup_req; + pulp_cluster_cfg_pkg::resp_mst_t [N_CLUSTERS-1:0] cl_oup_resp; + for (genvar i = 0; i < N_CLUSTERS; i++) begin : gen_assign_cl_oup + `AXI_ASSIGN_TO_REQ(cl_oup_req[i], cl_oup[i]) + `AXI_ASSIGN_FROM_RESP(cl_oup[i], cl_oup_resp[i]) + end + AXI_BUS_ASYNC #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_MST), + .AXI_USER_WIDTH (AXI_UW), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) cl_oup_async[N_CLUSTERS-1:0](); + + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_IW), + .AXI_USER_WIDTH (AXI_UW) + ) cl_dma[N_CLUSTERS-1:0](); + pulp_cluster_cfg_pkg::req_dma_t [N_CLUSTERS-1:0] cl_dma_req; + pulp_cluster_cfg_pkg::resp_dma_t [N_CLUSTERS-1:0] cl_dma_resp; + for (genvar i = 0; i < N_CLUSTERS; i++) begin : gen_assign_cl_dma + `AXI_ASSIGN_TO_REQ(cl_dma_req[i], cl_dma[i]) + `AXI_ASSIGN_FROM_RESP(cl_dma[i], cl_dma_resp[i]) + end + AXI_BUS_ASYNC #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_IW), + .AXI_USER_WIDTH (AXI_UW), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) cl_dma_async[N_CLUSTERS-1:0](); + + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_IW), + .AXI_USER_WIDTH (AXI_UW) + ) cl_nhi[N_CLUSTERS-1:0](); + pulp_cluster_cfg_pkg::req_dma_t [N_CLUSTERS-1:0] cl_nhi_req; + pulp_cluster_cfg_pkg::resp_dma_t [N_CLUSTERS-1:0] cl_nhi_resp; + for (genvar i = 0; i < N_CLUSTERS; i++) begin : gen_assign_cl_nhi + `AXI_ASSIGN_FROM_REQ(cl_nhi[i], cl_nhi_req[i]) + `AXI_ASSIGN_TO_RESP(cl_nhi_resp[i], cl_nhi[i]) + end + /* We are not using async clusters, can we remove their definition? */ + /* + AXI_BUS_ASYNC #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_DW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_IW), + .AXI_USER_WIDTH (AXI_UW), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) cl_nhi_async[N_CLUSTERS-1:0](); + */ + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW_ICACHE), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_ICACHE), + .AXI_USER_WIDTH (AXI_UW) + ) cl_icache[N_CLUSTERS-1:0](); + + pulp_cluster_cfg_pkg::req_icache_t [N_CLUSTERS-1:0] cl_icache_req; + pulp_cluster_cfg_pkg::resp_icache_t [N_CLUSTERS-1:0] cl_icache_resp; + + pulp_cluster_cfg_pkg::req_icache_t host_slv_downsized_req; + pulp_cluster_cfg_pkg::resp_icache_t host_slv_downsized_resp; + + for (genvar i = 0; i < N_CLUSTERS; i++) begin : gen_assign_cl_icache + `AXI_ASSIGN_TO_REQ(cl_icache_req[i], cl_icache[i]) + `AXI_ASSIGN_FROM_RESP(cl_icache[i], cl_icache_resp[i]) + end + AXI_BUS_ASYNC #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW_ICACHE), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_ICACHE), + .AXI_USER_WIDTH (AXI_UW), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) cl_icache_async[N_CLUSTERS-1:0](); + + // Interfaces to L2 Memory + req_t pe_l2_req, dma_l2_req, l2_hnd_req_a, l2_hnd_req_b, l2_pkt_req_a, l2_pkt_req_b; + resp_t pe_l2_resp, dma_l2_resp, l2_hnd_resp_a, l2_hnd_resp_b, l2_pkt_resp_a, l2_pkt_resp_b; + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_WIDE_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) l2_hnd_mst_a(), l2_pkt_mst_a(), l2_hnd_mst_b(), l2_pkt_mst_b(); + + `AXI_ASSIGN_FROM_REQ(l2_hnd_mst_a, l2_hnd_req_a) + `AXI_ASSIGN_TO_RESP(l2_hnd_resp_a, l2_hnd_mst_a) + + `AXI_ASSIGN_FROM_REQ(l2_hnd_mst_b, l2_hnd_req_b) + `AXI_ASSIGN_TO_RESP(l2_hnd_resp_b, l2_hnd_mst_b) + + `AXI_ASSIGN_FROM_REQ(l2_pkt_mst_a, l2_pkt_req_a) + `AXI_ASSIGN_TO_RESP(l2_pkt_resp_a, l2_pkt_mst_a) + + `AXI_ASSIGN_FROM_REQ(l2_pkt_mst_b, l2_pkt_req_b) + `AXI_ASSIGN_TO_RESP(l2_pkt_resp_b, l2_pkt_mst_b) + + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_WIDE_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) l2_hnd_mst_wo_atomics(); + + req_t host_l2_prog_req; + resp_t host_l2_prog_resp; + + // Interface from eDMA to NHI + req_t nhi_mst_edma_req; + resp_t nhi_mst_edma_resp; + + // Interfaces to Peripherals + localparam int unsigned AXI_DW_PERIPHS = 64; + typedef logic [AXI_DW_PERIPHS-1:0] periph_data_t; + typedef logic [AXI_DW_PERIPHS/8-1:0] periph_strb_t; + `AXI_TYPEDEF_W_CHAN_T(periph_w_t, periph_data_t, periph_strb_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(periph_r_t, periph_data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(periph_req_t, aw_t, periph_w_t, ar_t) + `AXI_TYPEDEF_RESP_T(periph_resp_t, b_t, periph_r_t) + periph_req_t periph_req; + periph_resp_t periph_resp; + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_DW_PERIPHS), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) periph_mst(); + `AXI_ASSIGN_FROM_REQ(periph_mst, periph_req) + `AXI_ASSIGN_TO_RESP(periph_resp, periph_mst) + + // mpq_engine -> scheduler + logic mpqengine_scheduler_valid; + logic mpqengine_scheduler_ready; + pspin_cfg_pkg::handler_task_t mpqengine_scheduler_task; + + // scheduler -> mpq_engine + logic scheduler_mpqengine_valid; + logic scheduler_mpqengine_ready; + pspin_cfg_pkg::feedback_descr_t scheduler_mpqengine_feedback; + + // scheduler -> cluster_schedulers + logic [N_CLUSTERS-1:0] sched_loc_valid; + logic [N_CLUSTERS-1:0] sched_loc_ready; + pspin_cfg_pkg::handler_task_t [N_CLUSTERS-1:0] sched_loc_task; + + // cluster_schedulers -> scheduler + logic [N_CLUSTERS-1:0] loc_sched_valid; + logic [N_CLUSTERS-1:0] loc_sched_ready; + pspin_cfg_pkg::feedback_descr_t [N_CLUSTERS-1:0] loc_sched_feedback; + + logic [N_CLUSTERS-1:0] cluster_active_q; + logic [N_CLUSTERS-1:0] cluster_active_d; + + logic [N_CLUSTERS-1:0] cluster_cmd_ready; + logic [N_CLUSTERS-1:0] cluster_cmd_valid; + pspin_cfg_pkg::pspin_cmd_t [N_CLUSTERS-1:0] cluster_cmd; + + logic cluster_cmd_resp_valid; + pspin_cfg_pkg::pspin_cmd_resp_t cluster_cmd_resp; + + // CMD unit <-> soc-level DMA + logic edma_cmd_ready; + logic edma_cmd_valid; + pspin_cfg_pkg::pspin_cmd_t edma_cmd; + logic edma_resp_valid; + pspin_cfg_pkg::pspin_cmd_resp_t edma_resp; + + // CMD unit <-> HostDirect unit + logic hdir_cmd_valid; + logic hdir_cmd_ready; + pspin_cfg_pkg::pspin_cmd_t hdir_cmd; + logic hdir_resp_valid; + pspin_cfg_pkg::pspin_cmd_resp_t hdir_resp; + + assign pspin_active_o = (~cluster_active_q == '0); + + mpq_engine #( + .NUM_HER_SLOTS (pspin_cfg_pkg::NUM_MPQ_CELLS), + .NUM_MPQ (N_MPQ) + ) i_mpq_engine ( + .rst_ni (rst_ni), + .clk_i (clk_i), + + .her_ready_o (her_ready_o), + .her_valid_i (her_valid_i), + .her_i (her_i), + + .eos_i (eos_i), + + .mpq_full_o (mpq_full_o), + + .nic_feedback_ready_i (nic_feedback_ready_i), + .nic_feedback_valid_o (nic_feedback_valid_o), + .nic_feedback_o (nic_feedback_o), + + .feedback_ready_o (scheduler_mpqengine_ready), + .feedback_valid_i (scheduler_mpqengine_valid), + .feedback_i (scheduler_mpqengine_feedback), + + .task_ready_i (mpqengine_scheduler_ready), + .task_valid_o (mpqengine_scheduler_valid), + .task_o (mpqengine_scheduler_task) + + ); + + scheduler #( + .NUM_CLUSTERS (N_CLUSTERS), + .NUM_HERS_PER_CLUSTER (pspin_cfg_pkg::NUM_HERS_PER_CLUSTER) + ) i_scheduler ( + .rst_ni (rst_ni), + .clk_i (clk_i), + + //from MPQ engine + .task_valid_i (mpqengine_scheduler_valid), + .task_ready_o (mpqengine_scheduler_ready), + .task_descr_i (mpqengine_scheduler_task), + + // to MPQ engine (TODO: change names) + .pktgen_feedback_valid_o (scheduler_mpqengine_valid), + .pktgen_feedback_ready_i (scheduler_mpqengine_ready), + .pktgen_feedback_o (scheduler_mpqengine_feedback), + + // to cluster_schedulers + .cluster_task_valid_o (sched_loc_valid), + .cluster_task_ready_i (sched_loc_ready), + .cluster_task_descr_o (sched_loc_task), + + // from cluster schedulers + .cluster_feedback_valid_i (loc_sched_valid), + .cluster_feedback_ready_o (loc_sched_ready), + .cluster_feedback_i (loc_sched_feedback) + ); + + soc_dma_wrap #( + .DmaAxiIdWidth (AXI_IW), + .DmaDataWidth (AXI_WIDE_DW), + .DmaUserWidth (AXI_UW), + .AxiAxReqDepth (pspin_cfg_pkg::SOC_DMA_AXI_REQ_DEPTH), + .TfReqFifoDepth (pspin_cfg_pkg::SOC_DMA_REQ_FIFO_DEPT), + .axi_nhi_req_t (req_t), + .axi_nhi_res_t (resp_t), + .axi_host_req_t (host_req_t), + .axi_host_res_t (host_resp_t) + ) i_soc_dma_wrap ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .cmd_req_valid_i (edma_cmd_valid), + .cmd_req_ready_o (edma_cmd_ready), + .cmd_req_i (edma_cmd), + + .cmd_resp_valid_o (edma_resp_valid), + .cmd_resp_o (edma_resp), + + //AXI wide port 1 (to NHI) + .nhi_req_o (nhi_mst_edma_req), + .nhi_resp_i (nhi_mst_edma_resp), + //AXI wide port 2 (to HOST) + .host_req_o (host_mst_soc_dma_req), + .host_resp_i (host_mst_soc_dma_resp) + ); + + host_direct #( + .AXI_AW (HOST_AXI_AW), + .AXI_DW (AXI_WIDE_DW), + .CMD_IMM_DATA_SIZE (AXI_WIDE_DW), + .axi_host_aw_t (pspin_cfg_pkg::aw_host_t), + .axi_host_ar_t (pspin_cfg_pkg::ar_host_t), + .axi_host_w_t (pspin_cfg_pkg::w_t), + .axi_host_r_t (pspin_cfg_pkg::r_t), + .axi_host_b_t (pspin_cfg_pkg::b_t), + .axi_host_req_t (host_req_t), + .axi_host_res_t (host_resp_t), + .cmd_req_t (pspin_cfg_pkg::pspin_cmd_t), + .cmd_res_t (pspin_cfg_pkg::pspin_cmd_resp_t), + .cmd_id_t (pspin_cfg_pkg::pspin_cmd_id_t) + ) i_host_direct ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .cmd_req_valid_i (hdir_cmd_valid), + .cmd_req_ready_o (hdir_cmd_ready), + .cmd_req_i (hdir_cmd), + + .cmd_resp_valid_o (hdir_resp_valid), + .cmd_resp_o (hdir_resp), + + .host_req_o (host_mst_hdir_req), + .host_resp_i (host_mst_hdir_resp) + ); + + host_mst_mux #( + .AddrWidth (HOST_AXI_AW), + .DataWidth (AXI_WIDE_DW), + .IdWidth (AXI_IW), + .UserWidth (AXI_UW), + .req_t (host_req_t), + .resp_t (host_resp_t) + ) i_mux_host_mst ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .dma_req_i (host_mst_soc_dma_req), + .dma_resp_o (host_mst_soc_dma_resp), + + .hdir_req_i (host_mst_hdir_req), + .hdir_resp_o (host_mst_hdir_resp), + + .host_req_o (host_mst_req), + .host_resp_i (host_mst_resp) + ); + + cmd_unit #( + .NUM_CLUSTERS (N_CLUSTERS), + .NUM_CMD_INTERFACES (pspin_cfg_pkg::NUM_CMD_INTERFACES) + ) i_cmd_unit ( + .rst_ni (rst_ni), + .clk_i (clk_i), + + //commands from clusters + .cmd_ready_o (cluster_cmd_ready), + .cmd_valid_i (cluster_cmd_valid), + .cmd_i (cluster_cmd), + + //command responses to clusters + .cmd_resp_valid_o (cluster_cmd_resp_valid), + .cmd_resp_o (cluster_cmd_resp), + + //command interfaces requests + .intf_ready_i ({edma_cmd_ready, nic_cmd_ready_i, hdir_cmd_ready}), + .intf_valid_o ({edma_cmd_valid, nic_cmd_valid_o, hdir_cmd_valid}), + .intf_cmd_o ({edma_cmd, nic_cmd_o, hdir_cmd}), + + //command interfaces responses + .intf_cmd_resp_valid_i ({edma_resp_valid, nic_cmd_resp_valid_i, hdir_resp_valid}), + .intf_cmd_resp_i ({edma_resp, nic_cmd_resp_i, hdir_resp}) + ); + + for (genvar i = 0; i < N_CLUSTERS; i++) begin: gen_clusters + logic [5:0] cluster_id; + assign cluster_id = i; + + if (pulp_cluster_cfg_pkg::ASYNC) begin : gen_cluster_async + axi_slice_dc_slave_wrap #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW), + .AXI_USER_WIDTH (AXI_UW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_SLV), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) i_dc_slice_cl_inp ( + .clk_i, + .rst_ni, + .test_cgbypass_i (1'b0), + .isolate_i (1'b0), + .axi_slave (cl_inp[i]), + .axi_master_async (cl_inp_async[i]) + ); + pulp_cluster_async i_cluster ( + .clk_i, + .rst_ni, + .ref_clk_i (clk_i), + .cluster_id_i (cluster_id), + .fetch_en_i (cl_fetch_en_i[i]), + .eoc_o (cl_eoc_o[i]), + .busy_o (cl_busy_o[i]), + .slv (cl_inp_async[i]), + .mst (cl_oup_async[i]), + .dma (cl_dma_async[i]), + .icache (cl_icache_async[i]) + ); + axi_slice_dc_master_wrap #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DW), + .AXI_USER_WIDTH (AXI_UW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_IW_MST), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) i_dc_slice_cl_oup ( + .clk_i, + .rst_ni, + .test_cgbypass_i (1'b0), + .clock_down_i (1'b0), + .isolate_i (1'b0), + .incoming_req_o (), + .axi_slave_async (cl_oup_async[i]), + .axi_master (cl_oup[i]) + ); + axi_slice_dc_master_wrap #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_DW), + .AXI_USER_WIDTH (AXI_UW), + .AXI_ID_WIDTH (pulp_cluster_cfg_pkg::AXI_DMA_IW), + .BUFFER_WIDTH (pulp_cluster_cfg_pkg::DC_BUF_W) + ) i_dc_slice_cl_dma ( + .clk_i, + .rst_ni, + .test_cgbypass_i (1'b0), + .clock_down_i (1'b0), + .isolate_i (1'b0), + .incoming_req_o (), + .axi_slave_async (cl_dma_async[i]), + .axi_master (cl_dma[i]) + ); + + end else begin : gen_cluster_sync + pulp_cluster_sync i_cluster ( + .clk_i, + .rst_ni, + .ref_clk_i (clk_i), + .cluster_id_i (cluster_id), + .fetch_en_i (cl_fetch_en_i[i]), + .eoc_o (cl_eoc_o[i]), + .busy_o (cl_busy_o[i]), + .slv (cl_inp[i]), + .mst (cl_oup[i]), + .dma (cl_dma[i]), + .icache (cl_icache[i]), + .nhi (cl_nhi[i]), + + .task_valid_i (sched_loc_valid[i]), + .task_ready_o (sched_loc_ready[i]), + .task_descr_i (sched_loc_task[i]), + .feedback_valid_o (loc_sched_valid[i]), + .feedback_ready_i (loc_sched_ready[i]), + .feedback_o (loc_sched_feedback[i]), + .cluster_active_o (cluster_active_d[i]), + .cmd_ready_i (cluster_cmd_ready[i]), + .cmd_valid_o (cluster_cmd_valid[i]), + .cmd_o (cluster_cmd[i]), + .cmd_resp_valid_i (cluster_cmd_resp_valid), + .cmd_resp_i (cluster_cmd_resp) + ); + end + end + + /// Address map + // Clusters + addr_t [N_CLUSTERS-1:0] cl_start_addr, cl_end_addr; + for (genvar i = 0; i < N_CLUSTERS; i++) begin : gen_map_clusters + assign cl_start_addr[i] = L1_CLUSTER_BASE + i * L1_CLUSTER_MEM_SIZE; + assign cl_end_addr[i] = L1_CLUSTER_BASE + (i+1) * L1_CLUSTER_MEM_SIZE; + end + // L2 + addr_t l2_hnd_start_addr, l2_hnd_end_addr, + l2_pkt_start_addr, l2_pkt_end_addr, + l2_prog_start_addr, l2_prog_end_addr, + l2_start_addr, l2_end_addr; + assign l2_hnd_start_addr = 32'h1C00_0000; + assign l2_hnd_end_addr = l2_hnd_start_addr + addr_t'(HND_MEM_SIZE); + + assign l2_pkt_start_addr = l2_hnd_end_addr; + assign l2_pkt_end_addr = l2_pkt_start_addr + addr_t'(PKT_MEM_SIZE); + + assign l2_prog_start_addr = 32'h1D00_0000; + assign l2_prog_end_addr = l2_prog_start_addr + 32'h0000_8000; + + assign l2_start_addr = l2_hnd_start_addr; + assign l2_end_addr = l2_pkt_end_addr; + + // Peripherals + addr_t periph_start_addr, periph_end_addr; + assign periph_start_addr = 32'h1A10_0000; + assign periph_end_addr = periph_start_addr + addr_t'(32*1024); + + prog_mem #( + .NumClusters (N_CLUSTERS), + .NumBytes (32*1024), + .AddrWidth (AXI_AW), + .DataWidth (pulp_cluster_cfg_pkg::AXI_DW_ICACHE), + .IdWidth (pulp_cluster_cfg_pkg::AXI_IW_ICACHE), + .UserWidth (AXI_UW), + .req_t (pulp_cluster_cfg_pkg::req_icache_t), + .resp_t (pulp_cluster_cfg_pkg::resp_icache_t) + ) i_prog_mem ( + .clk_i, + .rst_ni, + .cl_req_i ( cl_icache_req ), + .cl_resp_o ( cl_icache_resp ), + .host_req_i ( host_slv_downsized_req ), + .host_resp_o ( host_slv_downsized_resp ) + ); + + pe_noc #( + .NumClusters (N_CLUSTERS), + .AddrWidth (AXI_AW), + .ClDataWidth (pulp_cluster_cfg_pkg::AXI_DW), + .ClOupIdWidth (pulp_cluster_cfg_pkg::AXI_IW_MST), + .ClInpIdWidth (pulp_cluster_cfg_pkg::AXI_IW_SLV), + .L2DataWidth (AXI_WIDE_DW), + .L2IdWidth (AXI_IW), + .PeriphDataWidth (AXI_DW_PERIPHS), + .PeriphIdWidth (AXI_IW), + .UserWidth (AXI_UW), + .cl_oup_req_t (pulp_cluster_cfg_pkg::req_mst_t), + .cl_oup_resp_t (pulp_cluster_cfg_pkg::resp_mst_t), + .cl_inp_req_t (pulp_cluster_cfg_pkg::req_slv_t), + .cl_inp_resp_t (pulp_cluster_cfg_pkg::resp_slv_t), + .l2_req_t (req_t), + .l2_resp_t (resp_t), + .periph_req_t (periph_req_t), + .periph_resp_t (periph_resp_t) + ) i_pe_noc ( + .clk_i, + .rst_ni, + .cl_start_addr_i (cl_start_addr), + .cl_end_addr_i (cl_end_addr), + .l2_start_addr_i (l2_start_addr), + .l2_end_addr_i (l2_end_addr), + .periph_start_addr_i (periph_start_addr), + .periph_end_addr_i (periph_end_addr), + .from_cl_req_i (cl_oup_req), + .from_cl_resp_o (cl_oup_resp), + .to_cl_req_o (cl_inp_req), + .to_cl_resp_i (cl_inp_resp), + .l2_req_o (pe_l2_req), + .l2_resp_i (pe_l2_resp), + .periph_req_o (periph_req), + .periph_resp_i (periph_resp) + ); + + dma_noc #( + .NumClusters (N_CLUSTERS), + .AddrWidth (AXI_AW), + .DataWidth (AXI_WIDE_DW), + .DMAIdWidth (pulp_cluster_cfg_pkg::AXI_DMA_IW), + .L2IdWidth (AXI_IW), + .UserWidth (AXI_UW), + .dma_req_t (pulp_cluster_cfg_pkg::req_dma_t), + .dma_resp_t (pulp_cluster_cfg_pkg::resp_dma_t), + .l2_req_t (req_t), + .l2_resp_t (resp_t) + ) i_dma_noc ( + .clk_i, + .rst_ni, + .l2_start_addr_i(l2_start_addr), + .l2_end_addr_i (l2_end_addr), + .dma_req_i (cl_dma_req), + .dma_resp_o (cl_dma_resp), + .l2_req_o (dma_l2_req), + .l2_resp_i (dma_l2_resp) + ); + + cluster_noc #( + .NumClusters (N_CLUSTERS), + .AddrWidth (AXI_AW), + .DataWidth (AXI_WIDE_DW), + .UserWidth (AXI_UW), + .NHIIdWidth (AXI_IW), + .ClIdWidth (pulp_cluster_cfg_pkg::AXI_DMA_IW), + .nhi_req_t (req_t), + .nhi_resp_t (resp_t), + .cl_req_t (pulp_cluster_cfg_pkg::req_dma_t), + .cl_resp_t (pulp_cluster_cfg_pkg::resp_dma_t) + ) i_cluster_noc ( + .clk_i, + .rst_ni, + .cl_start_addr_i (cl_start_addr), + .cl_end_addr_i (cl_end_addr), + .cl_req_o (cl_nhi_req), + .cl_resp_i (cl_nhi_resp), + .nhi_req_i (nhi_req), + .nhi_resp_o (nhi_resp) + ); + + l2_xbar #( + .AddrWidth (AXI_AW), + .DataWidth (AXI_WIDE_DW), + .IdWidth (AXI_IW), + .UserWidth (AXI_UW), + .req_t (req_t), + .resp_t (resp_t) + ) i_l2_xbar ( + .clk_i, + .rst_ni, + .l2_hnd_start_addr_i (l2_hnd_start_addr), + .l2_hnd_end_addr_i (l2_hnd_end_addr), + .l2_pkt_start_addr_i (l2_pkt_start_addr), + .l2_pkt_end_addr_i (l2_pkt_end_addr), + .pe_req_i (pe_l2_req), + .pe_resp_o (pe_l2_resp), + .dma_req_i (dma_l2_req), + .dma_resp_o (dma_l2_resp), + .l2_hnd_req_o (l2_hnd_req_a), + .l2_hnd_resp_i (l2_hnd_resp_a), + .l2_pkt_req_o (l2_pkt_req_a), + .l2_pkt_resp_i (l2_pkt_resp_a) + ); + + nhi_xbar #( + .AddrWidth (AXI_AW), + .DataWidth (AXI_WIDE_DW), + .IdWidth (AXI_IW), + .UserWidth (AXI_UW), + .req_t (req_t), + .resp_t (resp_t) + ) i_nhi_xbar ( + .clk_i, + .rst_ni, + .l2_hnd_start_addr_i ( l2_hnd_start_addr ), + .l2_hnd_end_addr_i ( l2_hnd_end_addr ), + .l2_pkt_start_addr_i ( l2_pkt_start_addr ), + .l2_pkt_end_addr_i ( l2_pkt_end_addr ), + .l2_prog_start_addr_i ( l2_prog_start_addr ), + .l2_prog_end_addr_i ( l2_prog_end_addr ), + .l1_start_addr_i ( cl_start_addr[0] ), + .l1_end_addr_i ( cl_end_addr[N_CLUSTERS-1] ), + .host_req_i ( host_slv_req ), + .host_resp_o ( host_slv_resp ), + .ni_req_i ( ni_req ), + .ni_resp_o ( ni_resp ), + .no_req_i ( no_req ), + .no_resp_o ( no_resp ), + .edma_req_i ( nhi_mst_edma_req ), + .edma_resp_o ( nhi_mst_edma_resp ), + .l2_hnd_req_o ( l2_hnd_req_b ), + .l2_hnd_resp_i ( l2_hnd_resp_b ), + .l2_pkt_req_o ( l2_pkt_req_b ), + .l2_pkt_resp_i ( l2_pkt_resp_b ), + .l2_prog_req_o ( host_l2_prog_req ), + .l2_prog_resp_i ( host_l2_prog_resp ), + .cluster_req_o ( nhi_req ), + .cluster_resp_i ( nhi_resp ) + ); + + axi_dw_downsizer #( + .AxiMaxReads ( 4 ), // Number of outstanding reads + .AxiSlvPortDataWidth ( pspin_cfg_pkg::AXI_WIDE_DW ), // Data width of the slv port + .AxiMstPortDataWidth ( pulp_cluster_cfg_pkg::AXI_DW_ICACHE ), // Data width of the mst port + .AxiAddrWidth ( pulp_cluster_cfg_pkg::AXI_AW ), // Address width + .AxiIdWidth ( pspin_cfg_pkg::AXI_IW ), // ID width + .aw_chan_t ( pspin_cfg_pkg::aw_t ), // AW Channel Type + .mst_w_chan_t ( pulp_cluster_cfg_pkg::w_icache_t ), // W Channel Type for the mst port + .slv_w_chan_t ( pspin_cfg_pkg::w_t ), // W Channel Type for the slv port + .b_chan_t ( pspin_cfg_pkg::b_t ), // B Channel Type + .ar_chan_t ( pspin_cfg_pkg::ar_t ), // AR Channel Type + .mst_r_chan_t ( pulp_cluster_cfg_pkg::r_icache_t ), // R Channel Type for the mst port + .slv_r_chan_t ( pspin_cfg_pkg::r_t ), // R Channel Type for the slv port + .axi_mst_req_t ( pulp_cluster_cfg_pkg::req_icache_t ), // AXI Request Type for mst ports + .axi_mst_resp_t ( pulp_cluster_cfg_pkg::resp_icache_t ), // AXI Response Type for mst ports + .axi_slv_req_t ( pspin_cfg_pkg::req_t ), // AXI Request Type for slv ports + .axi_slv_resp_t ( pspin_cfg_pkg::resp_t ) // AXI Response Type for slv ports + ) i_dw_downsizer_host_l2_prog ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( host_l2_prog_req ), + .slv_resp_o ( host_l2_prog_resp ), + .mst_req_o ( host_slv_downsized_req ), + .mst_resp_i ( host_slv_downsized_resp ) + ); + + axi_riscv_atomics_wrap #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_WIDE_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW), + .AXI_MAX_READ_TXNS (4), + .AXI_MAX_WRITE_TXNS (4), + .RISCV_WORD_WIDTH (32) + ) i_atomics ( + .clk_i, + .rst_ni, + .slv (l2_hnd_mst_a), + .mst (l2_hnd_mst_wo_atomics) + ); + + l2_mem #( + .AXI_AW (AXI_AW), + .AXI_DW (AXI_WIDE_DW), + .AXI_UW (AXI_UW), + .AXI_IW (AXI_IW), + .N_BYTES (HND_MEM_SIZE), + .CUT_DW (64), + .CUT_N_WORDS (16384), + .N_PAR_CUTS_MUL (4) + ) i_l2_hnd_mem ( + .clk_i, + .rst_ni, + .slv_a (l2_hnd_mst_wo_atomics), + .slv_b (l2_hnd_mst_b) + ); + + l2_mem #( + .AXI_AW (AXI_AW), + .AXI_DW (AXI_WIDE_DW), + .AXI_UW (AXI_UW), + .AXI_IW (AXI_IW), + .N_BYTES (PKT_MEM_SIZE), + .CUT_DW (512), + .CUT_N_WORDS (2048), + .N_PAR_CUTS_MUL (32) + ) i_l2_pkt_mem ( + .clk_i, + .rst_ni, + .slv_a (l2_pkt_mst_a), + .slv_b (l2_pkt_mst_b) + ); + + soc_peripherals #( + .AXI_AW (AXI_AW), + .AXI_IW (AXI_IW), + .AXI_UW (AXI_UW), + .N_CORES (pulp_cluster_cfg_pkg::N_CORES), + .N_CLUSTERS (N_CLUSTERS) + ) i_periphs ( + .clk_i, + .rst_ni, + .test_en_i ('0), + .axi (periph_mst) + ); + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + cluster_active_q <= '0; + end else begin + cluster_active_q <= cluster_active_d; + end + end + +endmodule diff --git a/hw/src/pspin_cfg_pkg.sv b/hw/src/pspin_cfg_pkg.sv new file mode 100644 index 0000000..2816854 --- /dev/null +++ b/hw/src/pspin_cfg_pkg.sv @@ -0,0 +1,322 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +package automatic pspin_cfg_pkg; + + localparam int unsigned HOST_AXI_AW = 64; + + // Interface parameters + localparam int unsigned AXI_AW = pulp_cluster_cfg_pkg::AXI_AW; + localparam int unsigned AXI_WIDE_DW = 512; // [bit], must be a power of 2 + localparam int unsigned AXI_IW = 6; + localparam int unsigned AXI_UW = pulp_cluster_cfg_pkg::AXI_UW; + + localparam int unsigned PKT_MEM_SIZE = pulp_cluster_cfg_pkg::L2_SIZE / 2; + localparam int unsigned HND_MEM_SIZE = pulp_cluster_cfg_pkg::L2_SIZE / 2; + + localparam int unsigned SOC_DMA_AXI_REQ_DEPTH = 12; + localparam int unsigned SOC_DMA_REQ_FIFO_DEPT = 64; //tune me! + + /* + localparam longint unsigned PCIE_START_ADDR = 64'h1000_0000_0000_0000; + localparam longint unsigned PCIE_END_ADDR = 64'h1FFF_FFFF_FFFF_FFFF; + localparam int unsigned NHI_START_ADDR = 32'h1000_0000; + localparam int unsigned NHI_END_ADDR = 32'hFF00_0000; + */ + + localparam int unsigned C_SIZE_WIDTH = AXI_AW; + localparam int unsigned C_MSGID_WIDTH = 10; + localparam int unsigned C_ADDR_WIDTH = AXI_AW; + localparam int unsigned C_HOST_ADDR_WIDTH = HOST_AXI_AW; + localparam int unsigned NUM_CLUSTERS = 4; + localparam int unsigned NUM_CORES = 8; + + //MPQ engine + localparam int unsigned NUM_MPQ = 1024; + localparam int unsigned NUM_MPQ_CELLS = 128; + localparam int unsigned NUM_MPQ_STATIC_CELLS = 1; //per MPQ + + localparam int unsigned HER_FLAGS_IS_HDR_IDX = 4; + localparam int unsigned HER_FLAGS_IS_CMPL_IDX = 5; + + localparam int unsigned L1_CLUSTER_BASE = 32'h1000_0000; + localparam int unsigned L1_CLUSTER_MEM_SIZE = 32'h0040_0000; //address space reserved to a cluster is 4 MiB + + //this is the actual L1 memory size + localparam int unsigned L1_CLUSTER_ACTUAL_MEM_SIZE = 32'h0010_0000; // 1 MiB + + //L1_RUNTIME_OFFSET + L1_RUNTIME_SIZE < L1_SIZE + + localparam int unsigned L1_RUNTIME_OFFSET = 32'h0000_0400; // 1 KiB reserved at the beginning. + localparam int unsigned L1_RUNTIME_SIZE = 32'h0000_4000; // 16 KiB + + localparam int unsigned L1_PKT_BUFF_OFFSET = L1_RUNTIME_OFFSET + L1_RUNTIME_SIZE; + localparam int unsigned L1_PKT_BUFF_SIZE = 32'h0001_0000; // 64 KiB + + localparam int unsigned L1_SCRATCHPAD_OFFSET = L1_PKT_BUFF_OFFSET + L1_PKT_BUFF_SIZE; + localparam int unsigned L1_SCRATCHPAD_SIZE = L1_CLUSTER_ACTUAL_MEM_SIZE - L1_PKT_BUFF_OFFSET; + + //number of HERs that can be buffered (allows to overlap DMA transfer to running handlers) + localparam int unsigned BUFFERED_HERS_PER_CLUSTER = 12; + + // the number of HERs in a cluster is the number of buffer ones + the ones running + localparam int unsigned NUM_HERS_PER_CLUSTER = BUFFERED_HERS_PER_CLUSTER + NUM_CORES; + + //number of messages per cluster + localparam int unsigned NUM_MSG_PER_CLUSTER = NUM_MPQ / NUM_CLUSTERS; + + //max number of commands that an HPU can keep in flight + localparam int unsigned NUM_HPU_CMDS = 4; + + //Number of command interfaces (NIC outbound, soc-level DMA) and IDs + //NOTE: the IDs need to be consistent with the inputs of the cmd unit. + localparam int unsigned NUM_CMD_INTERFACES = 3; + localparam int unsigned CMD_HOSTDIRECT_ID = 0; + localparam int unsigned CMD_NIC_OUTBOUND_ID = 1; + localparam int unsigned CMD_EDMA_ID = 2; + + + // Interface types + typedef logic [AXI_AW-1:0] addr_t; + typedef logic [AXI_WIDE_DW-1:0] data_t; + typedef logic [AXI_WIDE_DW/8-1:0] strb_t; + typedef logic [AXI_IW-1:0] id_t; + typedef logic [AXI_UW-1:0] user_t; + typedef logic [HOST_AXI_AW-1:0] host_addr_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_t, w_t, ar_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_t, r_t) + + `AXI_TYPEDEF_AW_CHAN_T(aw_host_t, host_addr_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_host_t, host_addr_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(host_req_t, aw_host_t, w_t, ar_host_t) + `AXI_TYPEDEF_RESP_T(host_resp_t, b_t, r_t) + + typedef logic [$clog2(NUM_HERS_PER_CLUSTER):0] cluster_occup_t; + typedef logic [31:0] pkt_ptr_t; + + typedef logic [C_ADDR_WIDTH-1:0] mem_addr_t; + typedef logic [C_SIZE_WIDTH-1:0] mem_size_t; + + + // feedback descriptor + typedef struct packed { + logic [C_ADDR_WIDTH-1:0] pkt_addr; + mem_size_t pkt_size; + logic [C_MSGID_WIDTH-1:0] msgid; + logic trigger_feedback; + } feedback_descr_t; + + typedef struct packed { + + //handler memory + mem_addr_t handler_mem_addr; + mem_size_t handler_mem_size; + + //host memory + host_addr_t host_mem_addr; + mem_size_t host_mem_size; + + //header handler + mem_addr_t hh_addr; + mem_size_t hh_size; + + //payload handler + mem_addr_t ph_addr; + mem_size_t ph_size; + + //completion (aka tail) handler + mem_addr_t th_addr; + mem_size_t th_size; + + //L1 scratchpads + mem_addr_t [NUM_CLUSTERS-1:0] scratchpad_addr; + mem_size_t [NUM_CLUSTERS-1:0] scratchpad_size; + + } mpq_meta_t; + + typedef struct packed { + + logic [C_MSGID_WIDTH-1:0] msgid; + + logic eom; + + //full her descriptor + mem_addr_t her_addr; + mem_size_t her_size; + mem_size_t xfer_size; + + mpq_meta_t mpq_meta; + } her_descr_t; + + //typedef enum logic [1:0] {HeaderHandler, PayloadHandler, CompletionHandler} her_task_type_t; + // job descriptor + typedef struct packed { + + logic [C_MSGID_WIDTH-1:0] msgid; + + mem_addr_t handler_fun; + mem_size_t handler_fun_size; + + mem_addr_t handler_mem_addr; + mem_size_t handler_mem_size; + + host_addr_t host_mem_addr; + mem_size_t host_mem_size; + + mem_addr_t pkt_addr; + mem_size_t pkt_size; + + logic trigger_feedback; + + mem_addr_t [NUM_CLUSTERS-1:0] scratchpad_addr; + mem_size_t [NUM_CLUSTERS-1:0] scratchpad_size; + + } handler_task_t; + + // DMA transfer descriptor + typedef struct packed { + logic [31:0] num_bytes; + logic [31:0] dst_addr_high; + logic [31:0] dst_addr_low; + logic [31:0] src_addr_high; + logic [31:0] src_addr_low; + logic deburst; + logic decouple; + logic serialize; + } transf_descr_t; + + // DMA transfer descriptor + typedef struct packed { + logic [31:0] num_bytes; + logic [31:0] dst_addr; + logic [31:0] src_addr; + logic deburst; + logic decouple; + logic serialize; + } transf_descr_32_t; + + // DMA transfer descriptor + typedef struct packed { + logic [31:0] num_bytes; + logic [65:0] dst_addr; + logic [65:0] src_addr; + logic deburst; + logic decouple; + logic serialize; + } transf_descr_soc_t; + + // Task descriptor (sent by the local scheduler to the HPU driver) + typedef struct packed { + handler_task_t handler_task; + pkt_ptr_t pkt_ptr; + } hpu_handler_task_t; + + // Task feedback descriptor (sent by the HPU driver to the local scheduler) + typedef struct packed { + feedback_descr_t feedback_descr; + pkt_ptr_t pkt_ptr; + } task_feedback_descr_t; + + + // a bit ugly but they are shared between the mpq_engine and the mpq_fsm, so not sure + // how to share these two types differertly (except for passing both of them as parameters, which + // would be ugly as well) + typedef enum logic [2:0] {Free, Header, HeaderRunning, Payload, PayloadDraining, Completion, CompletionRunning} mpq_state_t; + typedef struct packed { + mpq_state_t state; + logic [$clog2(NUM_MPQ_CELLS):0] length; + logic [$clog2(NUM_MPQ_CELLS):0] in_flight; + logic has_completion; + logic eom_seen; + } mpq_t; + + /* commands */ + + // network ID (e.g., IP address) + typedef logic [31:0] nid_t; + + // flow ID (e.g., (srcport, dstport) or matching bits) + typedef logic [31:0] fid_t; + + // memory type + typedef enum logic [1:0] {HostMem, NicMem} mem_type_t; + + // userptr + typedef logic [63:0] user_ptr_t; + + //NIC put/send command (224 b, padded to 76 B) + typedef struct packed { + logic [383:0] unused; // 384b + user_ptr_t user_ptr; // 64b + mem_size_t length; // 32b + host_addr_t src_addr; // 64b + fid_t fid; // 32b unused + nid_t nid; // 32b + } nic_cmd_t; + + // Host <-> PsPIN DMA command (193 b, padded to 76 B) + typedef struct packed { + logic [414:0] unused; // 415b + user_ptr_t user_ptr; // 64b + logic nic_to_host;// 1 + mem_size_t length; // 32b + mem_addr_t nic_addr; // 32b + host_addr_t host_addr; // 64b + } host_dma_cmd_t; + + // PsPIN <-> Host with immediate data (586 b, padded to 76 B) + typedef struct packed { + logic [AXI_WIDE_DW-1:0] imm_data; // 512b + logic [21:0] unused; // 22b + logic [$clog2(AXI_WIDE_DW)-1:0] imm_data_size; // 9b + logic nic_to_host; // 1b + host_addr_t host_addr; // 64b + } host_direct_cmd_t; + + typedef union packed { + logic [18:0][31:0] words; //TODO: determine this size programatically (max(sizeof(nic_cmd_t), sizeof(host_dma_cmd_t)))/32 + nic_cmd_t nic_cmd; + host_dma_cmd_t host_dma_cmd; + host_direct_cmd_t host_direct_cmd; + } pspin_cmd_descr_t; + + typedef enum logic [1:0] {HostMemCpy, NICSend, HostDirect} pspin_cmd_type_t; + typedef logic [$clog2(NUM_CMD_INTERFACES)-1:0] pspin_cmd_intf_id_t; + + typedef struct packed { + logic [$clog2(NUM_CLUSTERS)-1:0] cluster_id; + logic [$clog2(NUM_CORES)-1:0] core_id; + logic [$clog2(NUM_HPU_CMDS)-1:0] local_cmd_id; + } pspin_cmd_id_t; + + typedef struct packed { + pspin_cmd_intf_id_t intf_id; + pspin_cmd_id_t cmd_id; + pspin_cmd_type_t cmd_type; + pspin_cmd_descr_t descr; + + logic generate_event; + } pspin_cmd_t; + + typedef struct packed { + pspin_cmd_id_t cmd_id; + logic [AXI_WIDE_DW-1:0] imm_data; + } pspin_cmd_resp_t; + + +endpackage diff --git a/hw/src/pspin_verilator.sv b/hw/src/pspin_verilator.sv new file mode 100644 index 0000000..93880ae --- /dev/null +++ b/hw/src/pspin_verilator.sv @@ -0,0 +1,696 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import pspin_cfg_pkg::*; + +package automatic pspin_io; + + typedef logic [pspin_cfg_pkg::HOST_AXI_AW-1:0] wide_addr_t; + typedef logic [pspin_cfg_pkg::AXI_AW-1:0] addr_t; + typedef logic [pspin_cfg_pkg::AXI_WIDE_DW-1:0] data_t; + typedef logic [pspin_cfg_pkg::AXI_WIDE_DW/8-1:0] strb_t; + typedef logic [pspin_cfg_pkg::AXI_IW-1:0] id_t; + typedef logic [pspin_cfg_pkg::AXI_UW-1:0] user_t; + +endpackage + +module pspin_verilator #( +) ( + /** Clocks and Resets **/ + input logic clk_i, + input logic rst_ni, + + // asserted when HPUs are ready + output logic pspin_active_o, + + // termination signal + input logic eos_i, + + // MPQ full signal + output logic [NUM_MPQ-1:0] mpq_full_o, + + + /** NIC inbound engine AXI slave port **/ + // WRITE ADDRESS CHANNEL + input pspin_io::addr_t ni_slave_aw_addr_i, + input axi_pkg::prot_t ni_slave_aw_prot_i, + input axi_pkg::region_t ni_slave_aw_region_i, + input axi_pkg::len_t ni_slave_aw_len_i, + input axi_pkg::size_t ni_slave_aw_size_i, + input axi_pkg::burst_t ni_slave_aw_burst_i, + input logic ni_slave_aw_lock_i, + input axi_pkg::atop_t ni_slave_aw_atop_i, + input axi_pkg::cache_t ni_slave_aw_cache_i, + input axi_pkg::qos_t ni_slave_aw_qos_i, + input pspin_io::id_t ni_slave_aw_id_i, + input pspin_io::user_t ni_slave_aw_user_i, + input logic ni_slave_aw_valid_i, + output logic ni_slave_aw_ready_o, + + // READ ADDRESS CHANNEL + input pspin_io::addr_t ni_slave_ar_addr_i, + input axi_pkg::prot_t ni_slave_ar_prot_i, + input axi_pkg::region_t ni_slave_ar_region_i, + input axi_pkg::len_t ni_slave_ar_len_i, + input axi_pkg::size_t ni_slave_ar_size_i, + input axi_pkg::burst_t ni_slave_ar_burst_i, + input logic ni_slave_ar_lock_i, + input axi_pkg::cache_t ni_slave_ar_cache_i, + input axi_pkg::qos_t ni_slave_ar_qos_i, + input pspin_io::id_t ni_slave_ar_id_i, + input pspin_io::user_t ni_slave_ar_user_i, + input logic ni_slave_ar_valid_i, + output logic ni_slave_ar_ready_o, + + // WRITE DATA CHANNEL + input pspin_io::data_t ni_slave_w_data_i, + input pspin_io::strb_t ni_slave_w_strb_i, + input pspin_io::user_t ni_slave_w_user_i, + input logic ni_slave_w_last_i, + input logic ni_slave_w_valid_i, + output logic ni_slave_w_ready_o, + + // READ DATA CHANNEL + output pspin_io::data_t ni_slave_r_data_o, + output axi_pkg::resp_t ni_slave_r_resp_o, + output logic ni_slave_r_last_o, + output pspin_io::id_t ni_slave_r_id_o, + output pspin_io::user_t ni_slave_r_user_o, + output logic ni_slave_r_valid_o, + input logic ni_slave_r_ready_i, + + // WRITE RESPONSE CHANNEL + output axi_pkg::resp_t ni_slave_b_resp_o, + output pspin_io::id_t ni_slave_b_id_o, + output pspin_io::user_t ni_slave_b_user_o, + output logic ni_slave_b_valid_o, + input logic ni_slave_b_ready_i, + + + /** NIC outbound engine AXI slave port **/ + // WRITE ADDRESS CHANNEL + input pspin_io::addr_t no_slave_aw_addr_i, + input axi_pkg::prot_t no_slave_aw_prot_i, + input axi_pkg::region_t no_slave_aw_region_i, + input axi_pkg::len_t no_slave_aw_len_i, + input axi_pkg::size_t no_slave_aw_size_i, + input axi_pkg::burst_t no_slave_aw_burst_i, + input logic no_slave_aw_lock_i, + input axi_pkg::atop_t no_slave_aw_atop_i, + input axi_pkg::cache_t no_slave_aw_cache_i, + input axi_pkg::qos_t no_slave_aw_qos_i, + input pspin_io::id_t no_slave_aw_id_i, + input pspin_io::user_t no_slave_aw_user_i, + input logic no_slave_aw_valid_i, + output logic no_slave_aw_ready_o, + + // READ ADDRESS CHANNEL + input pspin_io::addr_t no_slave_ar_addr_i, + input axi_pkg::prot_t no_slave_ar_prot_i, + input axi_pkg::region_t no_slave_ar_region_i, + input axi_pkg::len_t no_slave_ar_len_i, + input axi_pkg::size_t no_slave_ar_size_i, + input axi_pkg::burst_t no_slave_ar_burst_i, + input logic no_slave_ar_lock_i, + input axi_pkg::cache_t no_slave_ar_cache_i, + input axi_pkg::qos_t no_slave_ar_qos_i, + input pspin_io::id_t no_slave_ar_id_i, + input pspin_io::user_t no_slave_ar_user_i, + input logic no_slave_ar_valid_i, + output logic no_slave_ar_ready_o, + + // WRITE DATA CHANNEL + input pspin_io::data_t no_slave_w_data_i, + input pspin_io::strb_t no_slave_w_strb_i, + input pspin_io::user_t no_slave_w_user_i, + input logic no_slave_w_last_i, + input logic no_slave_w_valid_i, + output logic no_slave_w_ready_o, + + // READ DATA CHANNEL + output pspin_io::data_t no_slave_r_data_o, + output axi_pkg::resp_t no_slave_r_resp_o, + output logic no_slave_r_last_o, + output pspin_io::id_t no_slave_r_id_o, + output pspin_io::user_t no_slave_r_user_o, + output logic no_slave_r_valid_o, + input logic no_slave_r_ready_i, + + // WRITE RESPONSE CHANNEL + output axi_pkg::resp_t no_slave_b_resp_o, + output pspin_io::id_t no_slave_b_id_o, + output pspin_io::user_t no_slave_b_user_o, + output logic no_slave_b_valid_o, + input logic no_slave_b_ready_i, + + + /** host AXI slave port **/ + // WRITE ADDRESS CHANNEL + input pspin_io::addr_t host_slave_aw_addr_i, + input axi_pkg::prot_t host_slave_aw_prot_i, + input axi_pkg::region_t host_slave_aw_region_i, + input axi_pkg::len_t host_slave_aw_len_i, + input axi_pkg::size_t host_slave_aw_size_i, + input axi_pkg::burst_t host_slave_aw_burst_i, + input logic host_slave_aw_lock_i, + input axi_pkg::atop_t host_slave_aw_atop_i, + input axi_pkg::cache_t host_slave_aw_cache_i, + input axi_pkg::qos_t host_slave_aw_qos_i, + input pspin_io::id_t host_slave_aw_id_i, + input pspin_io::user_t host_slave_aw_user_i, + input logic host_slave_aw_valid_i, + output logic host_slave_aw_ready_o, + + // READ ADDRESS CHANNEL + input pspin_io::addr_t host_slave_ar_addr_i, + input axi_pkg::prot_t host_slave_ar_prot_i, + input axi_pkg::region_t host_slave_ar_region_i, + input axi_pkg::len_t host_slave_ar_len_i, + input axi_pkg::size_t host_slave_ar_size_i, + input axi_pkg::burst_t host_slave_ar_burst_i, + input logic host_slave_ar_lock_i, + input axi_pkg::cache_t host_slave_ar_cache_i, + input axi_pkg::qos_t host_slave_ar_qos_i, + input pspin_io::id_t host_slave_ar_id_i, + input pspin_io::user_t host_slave_ar_user_i, + input logic host_slave_ar_valid_i, + output logic host_slave_ar_ready_o, + + // WRITE DATA CHANNEL + input pspin_io::data_t host_slave_w_data_i, + input pspin_io::strb_t host_slave_w_strb_i, + input pspin_io::user_t host_slave_w_user_i, + input logic host_slave_w_last_i, + input logic host_slave_w_valid_i, + output logic host_slave_w_ready_o, + + // READ DATA CHANNEL + output pspin_io::data_t host_slave_r_data_o, + output axi_pkg::resp_t host_slave_r_resp_o, + output logic host_slave_r_last_o, + output pspin_io::id_t host_slave_r_id_o, + output pspin_io::user_t host_slave_r_user_o, + output logic host_slave_r_valid_o, + input logic host_slave_r_ready_i, + + // WRITE RESPONSE CHANNEL + output axi_pkg::resp_t host_slave_b_resp_o, + output pspin_io::id_t host_slave_b_id_o, + output pspin_io::user_t host_slave_b_user_o, + output logic host_slave_b_valid_o, + input logic host_slave_b_ready_i, + + + /** host AXI master port **/ + // WRITE ADDRESS CHANNEL + output pspin_io::wide_addr_t host_master_aw_addr_o, + output axi_pkg::prot_t host_master_aw_prot_o, + output axi_pkg::region_t host_master_aw_region_o, + output axi_pkg::len_t host_master_aw_len_o, + output axi_pkg::size_t host_master_aw_size_o, + output axi_pkg::burst_t host_master_aw_burst_o, + output logic host_master_aw_lock_o, + output axi_pkg::atop_t host_master_aw_atop_o, + output axi_pkg::cache_t host_master_aw_cache_o, + output axi_pkg::qos_t host_master_aw_qos_o, + output pspin_io::id_t host_master_aw_id_o, + output pspin_io::user_t host_master_aw_user_o, + output logic host_master_aw_valid_o, + input logic host_master_aw_ready_i, + + // READ ADDRESS CHANNEL + output pspin_io::wide_addr_t host_master_ar_addr_o, + output axi_pkg::prot_t host_master_ar_prot_o, + output axi_pkg::region_t host_master_ar_region_o, + output axi_pkg::len_t host_master_ar_len_o, + output axi_pkg::size_t host_master_ar_size_o, + output axi_pkg::burst_t host_master_ar_burst_o, + output logic host_master_ar_lock_o, + output axi_pkg::cache_t host_master_ar_cache_o, + output axi_pkg::qos_t host_master_ar_qos_o, + output pspin_io::id_t host_master_ar_id_o, + output pspin_io::user_t host_master_ar_user_o, + output logic host_master_ar_valid_o, + input logic host_master_ar_ready_i, + + // WRITE DATA CHANNEL + output pspin_io::data_t host_master_w_data_o, + output pspin_io::strb_t host_master_w_strb_o, + output pspin_io::user_t host_master_w_user_o, + output logic host_master_w_last_o, + output logic host_master_w_valid_o, + input logic host_master_w_ready_i, + + // READ DATA CHANNEL + input pspin_io::data_t host_master_r_data_i, + input axi_pkg::resp_t host_master_r_resp_i, + input logic host_master_r_last_i, + input pspin_io::id_t host_master_r_id_i, + input pspin_io::user_t host_master_r_user_i, + input logic host_master_r_valid_i, + output logic host_master_r_ready_o, + + // WRITE RESPONSE CHANNEL + input axi_pkg::resp_t host_master_b_resp_i, + input pspin_io::id_t host_master_b_id_i, + input pspin_io::user_t host_master_b_user_i, + input logic host_master_b_valid_i, + output logic host_master_b_ready_o, + + + /** NIC inbound engine/packet generator control **/ + //from pktgen + output logic her_ready_o, + input logic her_valid_i, + input logic [C_MSGID_WIDTH-1:0] her_msgid_i, + input logic her_is_eom_i, + input mem_addr_t her_addr_i, + input mem_size_t her_size_i, + input mem_size_t her_xfer_size_i, + input mem_addr_t her_meta_handler_mem_addr_i, + input mem_size_t her_meta_handler_mem_size_i, + input host_addr_t her_meta_host_mem_addr_i, + input mem_size_t her_meta_host_mem_size_i, + input mem_addr_t her_meta_hh_addr_i, + input mem_size_t her_meta_hh_size_i, + input mem_addr_t her_meta_ph_addr_i, + input mem_size_t her_meta_ph_size_i, + input mem_addr_t her_meta_th_addr_i, + input mem_size_t her_meta_th_size_i, + input mem_addr_t her_meta_scratchpad_0_addr_i, + input mem_size_t her_meta_scratchpad_0_size_i, + input mem_addr_t her_meta_scratchpad_1_addr_i, + input mem_size_t her_meta_scratchpad_1_size_i, + input mem_addr_t her_meta_scratchpad_2_addr_i, + input mem_size_t her_meta_scratchpad_2_size_i, + input mem_addr_t her_meta_scratchpad_3_addr_i, + input mem_size_t her_meta_scratchpad_3_size_i, + + // to pktgen + input logic feedback_ready_i, + output logic feedback_valid_o, + output mem_addr_t feedback_her_addr_o, + output mem_size_t feedback_her_size_o, + output logic [C_MSGID_WIDTH-1:0] feedback_msgid_o, + + + /** NIC outbound engine or NIC command unit **/ + input logic nic_cmd_req_ready_i, + output logic nic_cmd_req_valid_o, + output pspin_cmd_id_t nic_cmd_req_id_o, + output nid_t nic_cmd_req_nid_o, + output fid_t nic_cmd_req_fid_o, + output host_addr_t nic_cmd_req_src_addr_o, + output mem_size_t nic_cmd_req_length_o, + output user_ptr_t nic_cmd_req_user_ptr_o, + + input logic nic_cmd_resp_valid_i, + input pspin_cmd_id_t nic_cmd_resp_id_i +); + + import pulp_cluster_cfg_pkg::N_TCDM_BANKS; + import pulp_cluster_cfg_pkg::TCDM_WORDS_PER_BANK; + import pspin_cfg_pkg::NUM_CLUSTERS; + + import "DPI-C" function string get_slm_path(); + +/* + export "DPI-C" function fill_l2_prog_mem; + export "DPI-C" function fill_l2_handler_mem; +*/ + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_WIDE_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) axi_ni (); + + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_WIDE_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) axi_no (); + + AXI_BUS #( + .AXI_ADDR_WIDTH (HOST_AXI_AW), + .AXI_DATA_WIDTH (AXI_WIDE_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) axi_host_mst (); + + AXI_BUS #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_WIDE_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW) + ) axi_host_slv (); + + logic [pspin_cfg_pkg::NUM_CLUSTERS-1:0] cl_fetch_en; + logic [pspin_cfg_pkg::NUM_CLUSTERS-1:0] cl_eoc; + logic [pspin_cfg_pkg::NUM_CLUSTERS-1:0] cl_busy; + + + her_descr_t her_descr; + feedback_descr_t feedback; + pspin_cmd_t nic_cmd_req; + pspin_cmd_resp_t nic_cmd_resp; + + pspin #( + .N_CLUSTERS (pspin_cfg_pkg::NUM_CLUSTERS), + .N_MPQ (pspin_cfg_pkg::NUM_MPQ) + ) i_pspin ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .cl_fetch_en_i (cl_fetch_en), + .cl_eoc_o (cl_eoc), + .cl_busy_o (cl_busy), + + .mpq_full_o (mpq_full_o), + + .axi_ni_slv (axi_ni), + .axi_no_slv (axi_no), + .axi_host_mst (axi_host_mst), + .axi_host_slv (axi_host_slv), + + .her_ready_o (her_ready_o), + .her_valid_i (her_valid_i), + .her_i (her_descr), + .eos_i (eos_i), + .nic_feedback_ready_i (feedback_ready_i), + .nic_feedback_valid_o (feedback_valid_o), + .nic_feedback_o (feedback), + .pspin_active_o (pspin_active_o), + .nic_cmd_ready_i (nic_cmd_req_ready_i), + .nic_cmd_valid_o (nic_cmd_req_valid_o), + .nic_cmd_o (nic_cmd_req), + .nic_cmd_resp_valid_i (nic_cmd_resp_valid_i), + .nic_cmd_resp_i (nic_cmd_resp) + ); + + + //TODO: move number of rows and number of cols in configuration file! + for (genvar iRow = 0; iRow < 1; iRow++) begin: gen_fill_l2_hnd_rows + for (genvar iCol = 0; iCol < 32; iCol++) begin: gen_fill_l2_hnd_cols + initial begin + //$readmemh($sformatf("../sim_files/slm_files/l2_hnd_%01d_%01d.slm", iRow, iCol), + //$display($sformatf(get_l2_handler_slm_path(), iRow, iCol)); + $readmemh({get_slm_path(), $sformatf("l2_hnd_%01d_%01d.slm", iRow, iCol)}, + i_pspin.i_l2_hnd_mem.gen_cols[iCol].gen_rows[iRow].i_mem_cut.i_tc_sram.sram); + end + end + end + + for (genvar iCluster = 0; iCluster < NUM_CLUSTERS; iCluster++) begin: gen_fill_tcdm_cluster + for (genvar iBank = 0; iBank < N_TCDM_BANKS; iBank++) begin: gen_fill_tcdm_bank + initial begin + for (int iWord = 0; iWord < TCDM_WORDS_PER_BANK; iWord++) begin + i_pspin.gen_clusters[iCluster].gen_cluster_sync.i_cluster.i_ooc.i_bound.gen_tcdm_banks[iBank].i_mem.i_tc_sram.sram[iWord] = '0; + end + end + end + end + + initial begin + //$readmemh("../sim_files/slm_files/prog_mem_stim.slm", i_pspin.i_prog_mem.i_sram.i_tc_sram.sram); + $readmemh({get_slm_path(), "prog_mem_stim.slm"}, i_pspin.i_prog_mem.i_sram.i_tc_sram.sram); + end + + // Wait for termination + always_ff @(posedge clk_i, negedge rst_ni) begin + if (i_pspin.i_mpq_engine.mpq_busy == '0 && i_pspin.i_mpq_engine.eos_i && i_pspin.i_mpq_engine.fifo_empty) begin + $finish; + end + end + + /* enable instruction fetch signal */ + assign cl_fetch_en = (rst_ni) ? 4'b1111 : '0; + + // Connecting axi_ni + assign axi_ni.aw_addr = ni_slave_aw_addr_i; + assign axi_ni.aw_prot = ni_slave_aw_prot_i; + assign axi_ni.aw_region = ni_slave_aw_region_i; + assign axi_ni.aw_len = ni_slave_aw_len_i; + assign axi_ni.aw_size = ni_slave_aw_size_i; + assign axi_ni.aw_burst = ni_slave_aw_burst_i; + assign axi_ni.aw_lock = ni_slave_aw_lock_i; + assign axi_ni.aw_atop = ni_slave_aw_atop_i; + assign axi_ni.aw_cache = ni_slave_aw_cache_i; + assign axi_ni.aw_qos = ni_slave_aw_qos_i; + assign axi_ni.aw_id = ni_slave_aw_id_i; + assign axi_ni.aw_user = ni_slave_aw_user_i; + assign axi_ni.aw_valid = ni_slave_aw_valid_i; + assign ni_slave_aw_ready_o = axi_ni.aw_ready; + + assign axi_ni.ar_addr = ni_slave_ar_addr_i; + assign axi_ni.ar_prot = ni_slave_ar_prot_i; + assign axi_ni.ar_region = ni_slave_ar_region_i; + assign axi_ni.ar_len = ni_slave_ar_len_i; + assign axi_ni.ar_size = ni_slave_ar_size_i; + assign axi_ni.ar_burst = ni_slave_ar_burst_i; + assign axi_ni.ar_lock = ni_slave_ar_lock_i; + assign axi_ni.ar_cache = ni_slave_ar_cache_i; + assign axi_ni.ar_qos = ni_slave_ar_qos_i; + assign axi_ni.ar_id = ni_slave_ar_id_i; + assign axi_ni.ar_user = ni_slave_ar_user_i; + assign axi_ni.ar_valid = ni_slave_ar_valid_i; + assign ni_slave_ar_ready_o = axi_ni.ar_ready; + + assign axi_ni.w_data = ni_slave_w_data_i; + assign axi_ni.w_strb = ni_slave_w_strb_i; + assign axi_ni.w_user = ni_slave_w_user_i; + assign axi_ni.w_last = ni_slave_w_last_i; + assign axi_ni.w_valid = ni_slave_w_valid_i; + assign ni_slave_w_ready_o = axi_ni.w_ready; + + assign ni_slave_r_data_o = axi_ni.r_data; + assign ni_slave_r_resp_o = axi_ni.r_resp; + assign ni_slave_r_last_o = axi_ni.r_last; + assign ni_slave_r_id_o = axi_ni.r_id; + assign ni_slave_r_user_o = axi_ni.r_user; + assign ni_slave_r_valid_o = axi_ni.r_valid; + assign axi_ni.r_ready = ni_slave_r_ready_i; + + assign ni_slave_b_resp_o = axi_ni.b_resp; + assign ni_slave_b_id_o = axi_ni.b_id; + assign ni_slave_b_user_o = axi_ni.b_user; + assign ni_slave_b_valid_o = axi_ni.b_valid; + assign axi_ni.b_ready = ni_slave_b_ready_i; + + + // Connecting axi_no + assign axi_no.aw_addr = no_slave_aw_addr_i; + assign axi_no.aw_prot = no_slave_aw_prot_i; + assign axi_no.aw_region = no_slave_aw_region_i; + assign axi_no.aw_len = no_slave_aw_len_i; + assign axi_no.aw_size = no_slave_aw_size_i; + assign axi_no.aw_burst = no_slave_aw_burst_i; + assign axi_no.aw_lock = no_slave_aw_lock_i; + assign axi_no.aw_atop = no_slave_aw_atop_i; + assign axi_no.aw_cache = no_slave_aw_cache_i; + assign axi_no.aw_qos = no_slave_aw_qos_i; + assign axi_no.aw_id = no_slave_aw_id_i; + assign axi_no.aw_user = no_slave_aw_user_i; + assign axi_no.aw_valid = no_slave_aw_valid_i; + assign no_slave_aw_ready_o = axi_no.aw_ready; + + assign axi_no.ar_addr = no_slave_ar_addr_i; + assign axi_no.ar_prot = no_slave_ar_prot_i; + assign axi_no.ar_region = no_slave_ar_region_i; + assign axi_no.ar_len = no_slave_ar_len_i; + assign axi_no.ar_size = no_slave_ar_size_i; + assign axi_no.ar_burst = no_slave_ar_burst_i; + assign axi_no.ar_lock = no_slave_ar_lock_i; + assign axi_no.ar_cache = no_slave_ar_cache_i; + assign axi_no.ar_qos = no_slave_ar_qos_i; + assign axi_no.ar_id = no_slave_ar_id_i; + assign axi_no.ar_user = no_slave_ar_user_i; + assign axi_no.ar_valid = no_slave_ar_valid_i; + assign no_slave_ar_ready_o = axi_no.ar_ready; + + assign axi_no.w_data = no_slave_w_data_i; + assign axi_no.w_strb = no_slave_w_strb_i; + assign axi_no.w_user = no_slave_w_user_i; + assign axi_no.w_last = no_slave_w_last_i; + assign axi_no.w_valid = no_slave_w_valid_i; + assign no_slave_w_ready_o = axi_no.w_ready; + + assign no_slave_r_data_o = axi_no.r_data; + assign no_slave_r_resp_o = axi_no.r_resp; + assign no_slave_r_last_o = axi_no.r_last; + assign no_slave_r_id_o = axi_no.r_id; + assign no_slave_r_user_o = axi_no.r_user; + assign no_slave_r_valid_o = axi_no.r_valid; + assign axi_no.r_ready = no_slave_r_ready_i; + + assign no_slave_b_resp_o = axi_no.b_resp; + assign no_slave_b_id_o = axi_no.b_id; + assign no_slave_b_user_o = axi_no.b_user; + assign no_slave_b_valid_o = axi_no.b_valid; + assign axi_no.b_ready = no_slave_b_ready_i; + + + // Connecting axi_host_slv + assign axi_host_slv.aw_addr = host_slave_aw_addr_i; + assign axi_host_slv.aw_prot = host_slave_aw_prot_i; + assign axi_host_slv.aw_region = host_slave_aw_region_i; + assign axi_host_slv.aw_len = host_slave_aw_len_i; + assign axi_host_slv.aw_size = host_slave_aw_size_i; + assign axi_host_slv.aw_burst = host_slave_aw_burst_i; + assign axi_host_slv.aw_lock = host_slave_aw_lock_i; + assign axi_host_slv.aw_atop = host_slave_aw_atop_i; + assign axi_host_slv.aw_cache = host_slave_aw_cache_i; + assign axi_host_slv.aw_qos = host_slave_aw_qos_i; + assign axi_host_slv.aw_id = host_slave_aw_id_i; + assign axi_host_slv.aw_user = host_slave_aw_user_i; + assign axi_host_slv.aw_valid = host_slave_aw_valid_i; + assign host_slave_aw_ready_o = axi_host_slv.aw_ready; + + assign axi_host_slv.ar_addr = host_slave_ar_addr_i; + assign axi_host_slv.ar_prot = host_slave_ar_prot_i; + assign axi_host_slv.ar_region = host_slave_ar_region_i; + assign axi_host_slv.ar_len = host_slave_ar_len_i; + assign axi_host_slv.ar_size = host_slave_ar_size_i; + assign axi_host_slv.ar_burst = host_slave_ar_burst_i; + assign axi_host_slv.ar_lock = host_slave_ar_lock_i; + assign axi_host_slv.ar_cache = host_slave_ar_cache_i; + assign axi_host_slv.ar_qos = host_slave_ar_qos_i; + assign axi_host_slv.ar_id = host_slave_ar_id_i; + assign axi_host_slv.ar_user = host_slave_ar_user_i; + assign axi_host_slv.ar_valid = host_slave_ar_valid_i; + assign host_slave_ar_ready_o = axi_host_slv.ar_ready; + + assign axi_host_slv.w_data = host_slave_w_data_i; + assign axi_host_slv.w_strb = host_slave_w_strb_i; + assign axi_host_slv.w_user = host_slave_w_user_i; + assign axi_host_slv.w_last = host_slave_w_last_i; + assign axi_host_slv.w_valid = host_slave_w_valid_i; + assign host_slave_w_ready_o = axi_host_slv.w_ready; + + assign host_slave_r_data_o = axi_host_slv.r_data; + assign host_slave_r_resp_o = axi_host_slv.r_resp; + assign host_slave_r_last_o = axi_host_slv.r_last; + assign host_slave_r_id_o = axi_host_slv.r_id; + assign host_slave_r_user_o = axi_host_slv.r_user; + assign host_slave_r_valid_o = axi_host_slv.r_valid; + assign axi_host_slv.r_ready = host_slave_r_ready_i; + + assign host_slave_b_resp_o = axi_host_slv.b_resp; + assign host_slave_b_id_o = axi_host_slv.b_id; + assign host_slave_b_user_o = axi_host_slv.b_user; + assign host_slave_b_valid_o = axi_host_slv.b_valid; + assign axi_host_slv.b_ready = host_slave_b_ready_i; + + // Connecting axi_host_mst + assign host_master_aw_addr_o = axi_host_mst.aw_addr; + assign host_master_aw_prot_o = axi_host_mst.aw_prot; + assign host_master_aw_region_o = axi_host_mst.aw_region; + assign host_master_aw_len_o = axi_host_mst.aw_len; + assign host_master_aw_size_o = axi_host_mst.aw_size; + assign host_master_aw_burst_o = axi_host_mst.aw_burst; + assign host_master_aw_lock_o = axi_host_mst.aw_lock; + assign host_master_aw_atop_o = axi_host_mst.aw_atop; + assign host_master_aw_cache_o = axi_host_mst.aw_cache; + assign host_master_aw_qos_o = axi_host_mst.aw_qos; + assign host_master_aw_id_o = axi_host_mst.aw_id; + assign host_master_aw_user_o = axi_host_mst.aw_user; + assign host_master_aw_valid_o = axi_host_mst.aw_valid; + assign axi_host_mst.aw_ready = host_master_aw_ready_i; + + assign host_master_ar_addr_o = axi_host_mst.ar_addr; + assign host_master_ar_prot_o = axi_host_mst.ar_prot; + assign host_master_ar_region_o = axi_host_mst.ar_region; + assign host_master_ar_len_o = axi_host_mst.ar_len; + assign host_master_ar_size_o = axi_host_mst.ar_size; + assign host_master_ar_burst_o = axi_host_mst.ar_burst; + assign host_master_ar_lock_o = axi_host_mst.ar_lock; + assign host_master_ar_cache_o = axi_host_mst.ar_cache; + assign host_master_ar_qos_o = axi_host_mst.ar_qos; + assign host_master_ar_id_o = axi_host_mst.ar_id; + assign host_master_ar_user_o = axi_host_mst.ar_user; + assign host_master_ar_valid_o = axi_host_mst.ar_valid; + assign axi_host_mst.ar_ready = host_master_ar_ready_i; + + assign host_master_w_data_o = axi_host_mst.w_data; + assign host_master_w_strb_o = axi_host_mst.w_strb; + assign host_master_w_user_o = axi_host_mst.w_user; + assign host_master_w_last_o = axi_host_mst.w_last; + assign host_master_w_valid_o = axi_host_mst.w_valid; + assign axi_host_mst.w_ready = host_master_w_ready_i; + + assign axi_host_mst.r_data = host_master_r_data_i; + assign axi_host_mst.r_resp = host_master_r_resp_i; + assign axi_host_mst.r_last = host_master_r_last_i; + assign axi_host_mst.r_id = host_master_r_id_i; + assign axi_host_mst.r_user = host_master_r_user_i; + assign axi_host_mst.r_valid = host_master_r_valid_i; + assign host_master_r_ready_o = axi_host_mst.r_ready; + + assign axi_host_mst.b_resp = host_master_b_resp_i; + assign axi_host_mst.b_id = host_master_b_id_i; + assign axi_host_mst.b_user = host_master_b_user_i; + assign axi_host_mst.b_valid = host_master_b_valid_i; + assign host_master_b_ready_o = axi_host_mst.b_ready; + + // Connecting her_descr + assign her_descr.msgid = her_msgid_i; + assign her_descr.eom = her_is_eom_i; + assign her_descr.her_addr = her_addr_i; + assign her_descr.her_size = her_size_i; + assign her_descr.xfer_size = her_xfer_size_i; + assign her_descr.mpq_meta.handler_mem_addr = her_meta_handler_mem_addr_i; + assign her_descr.mpq_meta.handler_mem_size = her_meta_handler_mem_size_i; + assign her_descr.mpq_meta.host_mem_addr = her_meta_host_mem_addr_i; + assign her_descr.mpq_meta.host_mem_size = her_meta_host_mem_size_i; + assign her_descr.mpq_meta.hh_addr = her_meta_hh_addr_i; + assign her_descr.mpq_meta.hh_size = her_meta_hh_size_i; + assign her_descr.mpq_meta.ph_addr = her_meta_ph_addr_i; + assign her_descr.mpq_meta.ph_size = her_meta_ph_size_i; + assign her_descr.mpq_meta.th_addr = her_meta_th_addr_i; + assign her_descr.mpq_meta.th_size = her_meta_th_size_i; + assign her_descr.mpq_meta.scratchpad_addr[0] = her_meta_scratchpad_0_addr_i; + assign her_descr.mpq_meta.scratchpad_addr[1] = her_meta_scratchpad_1_addr_i; + assign her_descr.mpq_meta.scratchpad_addr[2] = her_meta_scratchpad_2_addr_i; + assign her_descr.mpq_meta.scratchpad_addr[3] = her_meta_scratchpad_3_addr_i; + assign her_descr.mpq_meta.scratchpad_size[0] = her_meta_scratchpad_0_size_i; + assign her_descr.mpq_meta.scratchpad_size[1] = her_meta_scratchpad_1_size_i; + assign her_descr.mpq_meta.scratchpad_size[2] = her_meta_scratchpad_2_size_i; + assign her_descr.mpq_meta.scratchpad_size[3] = her_meta_scratchpad_3_size_i; + + // Connecting feedback + assign feedback_her_addr_o = feedback.pkt_addr; + assign feedback_her_size_o = feedback.pkt_size; + assign feedback_msgid_o = feedback.msgid; + + // Connecting NIC command request + assign nic_cmd_req_id_o = nic_cmd_req.cmd_id; + assign nic_cmd_req_nid_o = nic_cmd_req.descr.nic_cmd.nid; + assign nic_cmd_req_fid_o = nic_cmd_req.descr.nic_cmd.fid; + assign nic_cmd_req_src_addr_o = nic_cmd_req.descr.nic_cmd.src_addr; + assign nic_cmd_req_length_o = nic_cmd_req.descr.nic_cmd.length; + assign nic_cmd_req_user_ptr_o = nic_cmd_req.descr.nic_cmd.user_ptr; + + // Connecting NIC command response + assign nic_cmd_resp.cmd_id = nic_cmd_resp_id_i; + + + // Observe SoC bus for errors. + for (genvar iCluster = 0; iCluster < NUM_CLUSTERS; iCluster++) begin: gen_assert_cluster + assert property (@(posedge i_pspin.clk_i) i_pspin.rst_ni && i_pspin.cl_oup[iCluster].r_valid + |-> !i_pspin.cl_oup[iCluster].r_resp[1]) + else $warning("R resp error at cl_oup[%01d]", iCluster); + + assert property (@(posedge i_pspin.clk_i) i_pspin.rst_ni && i_pspin.cl_oup[iCluster].b_valid + |-> !i_pspin.cl_oup[iCluster].b_resp[1]) + else $warning("B resp error at cl_oup[%01d]", iCluster); + end + +endmodule diff --git a/hw/src/pulp_cluster_cfg_pkg.sv b/hw/src/pulp_cluster_cfg_pkg.sv new file mode 100644 index 0000000..c1bf424 --- /dev/null +++ b/hw/src/pulp_cluster_cfg_pkg.sv @@ -0,0 +1,88 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "axi/typedef.svh" + +// Configuration package for PULP cluster OOC stub +package automatic pulp_cluster_cfg_pkg; + // -- Decoupling of cluster clock domain + localparam bit ASYNC = 1'b0; + localparam int unsigned DC_BUF_W = 8; + // -- Cores + localparam int unsigned N_CORES = 8; // must be a power of 2 and <= 8 + // -- AXI + localparam int unsigned AXI_AW = 32; // [bit] + localparam int unsigned AXI_DW = 64; // [bit] + localparam int unsigned AXI_IW_MST = 6; // [bit] + localparam int unsigned AXI_IW_SLV = 4; // [bit] + localparam int unsigned AXI_UW = 4; // [bit] + // -- DMA + localparam int unsigned AXI_DMA_DW = 512; // [bit]; do not change + localparam int unsigned AXI_DMA_IW = 4; // [bit]; do not change + localparam int unsigned DMA_MAX_BURST_SIZE = 2048; // [B], must be a power of 2 + // Maximum number of beats in a DMA burst on the SoC bus + localparam int unsigned DMA_MAX_BURST_LEN = DMA_MAX_BURST_SIZE / (AXI_DW/8); + // Maximum number of transactions the DMA can have in flight + localparam int unsigned DMA_MAX_N_TXNS = N_CORES; + localparam int unsigned N_DMAS = 4; // larger values seem to break the cluster + // -- Instruction Cache + localparam int unsigned ICACHE_SIZE = 4096; // [B], must be a power of 2 + localparam int unsigned AXI_DW_ICACHE = 64; // [bit]; do not change, seems to break instruction cache + localparam int unsigned AXI_IW_ICACHE = 6; // [bit]; do not change, seems to break instruction cache + // -- TCDM + localparam int unsigned N_TCDM_BANKS = 8*N_CORES; // must be a power of 2 + localparam int unsigned TCDM_SIZE = 1024*1024; // [B], must be a power of 2 + localparam int unsigned TCDM_WORDS_PER_BANK = (TCDM_SIZE / 4) / N_TCDM_BANKS; + // -- L2 Memory (not inside cluster) + localparam int unsigned L2_SIZE = 8192*1024; // [B], must be a power of 2 + + typedef logic [AXI_AW-1:0] addr_t; + typedef logic [5:0] cluster_id_t; + typedef logic [AXI_DW-1:0] data_t; + typedef logic [AXI_DMA_DW-1:0] data_dma_t; + typedef logic [AXI_DW_ICACHE-1:0] data_icache_t; + typedef logic [DC_BUF_W-1:0] dc_buf_t; + typedef logic [AXI_IW_MST-1:0] id_mst_t; + typedef logic [AXI_IW_SLV-1:0] id_slv_t; + typedef logic [AXI_DMA_IW-1:0] id_dma_t; + typedef logic [AXI_IW_ICACHE-1:0] id_icache_t; + typedef logic [AXI_DW/8-1:0] strb_t; + typedef logic [AXI_DMA_DW/8-1:0] strb_dma_t; + typedef logic [AXI_DW_ICACHE/8-1:0] strb_icache_t; + typedef logic [AXI_UW-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_mst_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_dma_t, addr_t, id_dma_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_icache_t, addr_t, id_icache_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_dma_t, data_dma_t, strb_dma_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_icache_t, data_icache_t, strb_icache_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_mst_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_slv_t, id_slv_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_dma_t, id_dma_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_icache_t, id_icache_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_mst_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_dma_t, addr_t, id_dma_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_icache_t, addr_t, id_icache_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_mst_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_slv_t, data_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_dma_t, data_dma_t, id_dma_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_icache_t, data_icache_t, id_icache_t, user_t) + `AXI_TYPEDEF_REQ_T(req_mst_t, aw_mst_t, w_t, ar_mst_t) + `AXI_TYPEDEF_REQ_T(req_slv_t, aw_slv_t, w_t, ar_slv_t) + `AXI_TYPEDEF_REQ_T(req_dma_t, aw_dma_t, w_dma_t, ar_dma_t) + `AXI_TYPEDEF_REQ_T(req_icache_t, aw_icache_t, w_icache_t, ar_icache_t) + `AXI_TYPEDEF_RESP_T(resp_mst_t, b_mst_t, r_mst_t) + `AXI_TYPEDEF_RESP_T(resp_slv_t, b_slv_t, r_slv_t) + `AXI_TYPEDEF_RESP_T(resp_dma_t, b_dma_t, r_dma_t) + `AXI_TYPEDEF_RESP_T(resp_icache_t, b_icache_t, r_icache_t) +endpackage diff --git a/hw/src/pulp_cluster_ooc.sv b/hw/src/pulp_cluster_ooc.sv new file mode 100644 index 0000000..8a7c6f4 --- /dev/null +++ b/hw/src/pulp_cluster_ooc.sv @@ -0,0 +1,1213 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +import axi_pkg::*; +import pulp_cluster_cfg_pkg::*; + +// Stub of PULP Cluster for out-of-context synthesis +module pulp_cluster_ooc ( + input logic clk_i, + input logic rst_ni, + input logic ref_clk_i, + input cluster_id_t cluster_id_i, + input logic fetch_en_i, + output logic eoc_o, + output logic busy_o, + + // Slave Port + // AW + input addr_t slv_aw_addr_i, + input prot_t slv_aw_prot_i, + input region_t slv_aw_region_i, + input len_t slv_aw_len_i, + input size_t slv_aw_size_i, + input burst_t slv_aw_burst_i, + input logic slv_aw_lock_i, + input atop_t slv_aw_atop_i, + input cache_t slv_aw_cache_i, + input qos_t slv_aw_qos_i, + input id_slv_t slv_aw_id_i, + input user_t slv_aw_user_i, + // used if ASYNC_INTF + input dc_buf_t slv_aw_writetoken_i, + output dc_buf_t slv_aw_readpointer_o, + // used if !ASYNC_INTF + input logic slv_aw_valid_i, + output logic slv_aw_ready_o, + // AR + input addr_t slv_ar_addr_i, + input prot_t slv_ar_prot_i, + input region_t slv_ar_region_i, + input len_t slv_ar_len_i, + input size_t slv_ar_size_i, + input burst_t slv_ar_burst_i, + input logic slv_ar_lock_i, + input cache_t slv_ar_cache_i, + input qos_t slv_ar_qos_i, + input id_slv_t slv_ar_id_i, + input user_t slv_ar_user_i, + // used if ASYNC_INTF + input dc_buf_t slv_ar_writetoken_i, + output dc_buf_t slv_ar_readpointer_o, + // used if !ASYNC_INTF + input logic slv_ar_valid_i, + output logic slv_ar_ready_o, + // W + input data_t slv_w_data_i, + input strb_t slv_w_strb_i, + input user_t slv_w_user_i, + input logic slv_w_last_i, + // used if ASYNC_INTF + input dc_buf_t slv_w_writetoken_i, + output dc_buf_t slv_w_readpointer_o, + // used if !ASYNC_INTF + input logic slv_w_valid_i, + output logic slv_w_ready_o, + // R + output data_t slv_r_data_o, + output resp_t slv_r_resp_o, + output logic slv_r_last_o, + output id_slv_t slv_r_id_o, + output user_t slv_r_user_o, + // used if ASYNC_INTF + output dc_buf_t slv_r_writetoken_o, + input dc_buf_t slv_r_readpointer_i, + // used if !ASYNC_INTF + output logic slv_r_valid_o, + input logic slv_r_ready_i, + // B + output resp_t slv_b_resp_o, + output id_slv_t slv_b_id_o, + output user_t slv_b_user_o, + // used if ASYNC_INTF + output dc_buf_t slv_b_writetoken_o, + input dc_buf_t slv_b_readpointer_i, + // used if !ASYNC_INTF + output logic slv_b_valid_o, + input logic slv_b_ready_i, + + // Master Port + // AW + output addr_t mst_aw_addr_o, + output prot_t mst_aw_prot_o, + output region_t mst_aw_region_o, + output len_t mst_aw_len_o, + output size_t mst_aw_size_o, + output burst_t mst_aw_burst_o, + output logic mst_aw_lock_o, + output atop_t mst_aw_atop_o, + output cache_t mst_aw_cache_o, + output qos_t mst_aw_qos_o, + output id_mst_t mst_aw_id_o, + output user_t mst_aw_user_o, + // used if ASYNC_INTF + output dc_buf_t mst_aw_writetoken_o, + input dc_buf_t mst_aw_readpointer_i, + // used if !ASYNC_INTF + output logic mst_aw_valid_o, + input logic mst_aw_ready_i, + // AR + output addr_t mst_ar_addr_o, + output prot_t mst_ar_prot_o, + output region_t mst_ar_region_o, + output len_t mst_ar_len_o, + output size_t mst_ar_size_o, + output burst_t mst_ar_burst_o, + output logic mst_ar_lock_o, + output cache_t mst_ar_cache_o, + output qos_t mst_ar_qos_o, + output id_mst_t mst_ar_id_o, + output user_t mst_ar_user_o, + // used if ASYNC_INTF + output dc_buf_t mst_ar_writetoken_o, + input dc_buf_t mst_ar_readpointer_i, + // used if !ASYNC_INTF + output logic mst_ar_valid_o, + input logic mst_ar_ready_i, + // W + output data_t mst_w_data_o, + output strb_t mst_w_strb_o, + output user_t mst_w_user_o, + output logic mst_w_last_o, + // used if ASYNC_INTF + output dc_buf_t mst_w_writetoken_o, + input dc_buf_t mst_w_readpointer_i, + // used if !ASYNC_INTF + output logic mst_w_valid_o, + input logic mst_w_ready_i, + // R + input data_t mst_r_data_i, + input resp_t mst_r_resp_i, + input logic mst_r_last_i, + input id_mst_t mst_r_id_i, + input user_t mst_r_user_i, + // used if ASYNC_INTF + input dc_buf_t mst_r_writetoken_i, + output dc_buf_t mst_r_readpointer_o, + // used if !ASYNC_INTF + input logic mst_r_valid_i, + output logic mst_r_ready_o, + // B + input resp_t mst_b_resp_i, + input id_mst_t mst_b_id_i, + input user_t mst_b_user_i, + // used if ASYNC_INTF + input dc_buf_t mst_b_writetoken_i, + output dc_buf_t mst_b_readpointer_o, + // used if !ASYNC_INTF + input logic mst_b_valid_i, + output logic mst_b_ready_o, + + // AXI4 DMA MASTER + // WRITE ADDRESS CHANNEL + output addr_t dma_aw_addr_o, + output prot_t dma_aw_prot_o, + output region_t dma_aw_region_o, + output len_t dma_aw_len_o, + output size_t dma_aw_size_o, + output burst_t dma_aw_burst_o, + output logic dma_aw_lock_o, + output atop_t dma_aw_atop_o, + output cache_t dma_aw_cache_o, + output qos_t dma_aw_qos_o, + output id_dma_t dma_aw_id_o, + output user_t dma_aw_user_o, + output logic dma_aw_valid_o, + input logic dma_aw_ready_i, + + // READ ADDRESS CHANNEL + output addr_t dma_ar_addr_o, + output prot_t dma_ar_prot_o, + output region_t dma_ar_region_o, + output len_t dma_ar_len_o, + output size_t dma_ar_size_o, + output burst_t dma_ar_burst_o, + output logic dma_ar_lock_o, + output cache_t dma_ar_cache_o, + output qos_t dma_ar_qos_o, + output id_dma_t dma_ar_id_o, + output user_t dma_ar_user_o, + output logic dma_ar_valid_o, + input logic dma_ar_ready_i, + + // WRITE DATA CHANNEL + output data_dma_t dma_w_data_o, + output strb_dma_t dma_w_strb_o, + output user_t dma_w_user_o, + output logic dma_w_last_o, + output logic dma_w_valid_o, + input logic dma_w_ready_i, + + // READ DATA CHANNEL + input data_dma_t dma_r_data_i, + input resp_t dma_r_resp_i, + input logic dma_r_last_i, + input id_dma_t dma_r_id_i, + input user_t dma_r_user_i, + input logic dma_r_valid_i, + output logic dma_r_ready_o, + + // WRITE RESPONSE CHANNEL + input resp_t dma_b_resp_i, + input id_dma_t dma_b_id_i, + input user_t dma_b_user_i, + input logic dma_b_valid_i, + output logic dma_b_ready_o, + + //AXI4 NHI SLAVE + // WRITE ADDRESS CHANNEL + input addr_t nhi_aw_addr_i, + input prot_t nhi_aw_prot_i, + input region_t nhi_aw_region_i, + input len_t nhi_aw_len_i, + input size_t nhi_aw_size_i, + input burst_t nhi_aw_burst_i, + input logic nhi_aw_lock_i, + input atop_t nhi_aw_atop_i, + input cache_t nhi_aw_cache_i, + input qos_t nhi_aw_qos_i, + input id_dma_t nhi_aw_id_i, + input user_t nhi_aw_user_i, + input logic nhi_aw_valid_i, + output logic nhi_aw_ready_o, + + // READ ADDRESS CHANNEL + input addr_t nhi_ar_addr_i, + input prot_t nhi_ar_prot_i, + input region_t nhi_ar_region_i, + input len_t nhi_ar_len_i, + input size_t nhi_ar_size_i, + input burst_t nhi_ar_burst_i, + input logic nhi_ar_lock_i, + input cache_t nhi_ar_cache_i, + input qos_t nhi_ar_qos_i, + input id_dma_t nhi_ar_id_i, + input user_t nhi_ar_user_i, + input logic nhi_ar_valid_i, + output logic nhi_ar_ready_o, + + // WRITE DATA CHANNEL + input data_dma_t nhi_w_data_i, + input strb_dma_t nhi_w_strb_i, + input user_t nhi_w_user_i, + input logic nhi_w_last_i, + input logic nhi_w_valid_i, + output logic nhi_w_ready_o, + + // READ DATA CHANNEL + output data_dma_t nhi_r_data_o, + output resp_t nhi_r_resp_o, + output logic nhi_r_last_o, + output id_dma_t nhi_r_id_o, + output user_t nhi_r_user_o, + output logic nhi_r_valid_o, + input logic nhi_r_ready_i, + + // WRITE RESPONSE CHANNEL + output resp_t nhi_b_resp_o, + output id_dma_t nhi_b_id_o, + output user_t nhi_b_user_o, + output logic nhi_b_valid_o, + input logic nhi_b_ready_i, + + // Instruction Cache Master Port + output addr_t icache_aw_addr_o, + output prot_t icache_aw_prot_o, + output region_t icache_aw_region_o, + output len_t icache_aw_len_o, + output size_t icache_aw_size_o, + output burst_t icache_aw_burst_o, + output logic icache_aw_lock_o, + output atop_t icache_aw_atop_o, + output cache_t icache_aw_cache_o, + output qos_t icache_aw_qos_o, + output id_icache_t icache_aw_id_o, + output user_t icache_aw_user_o, + output logic icache_aw_valid_o, + input logic icache_aw_ready_i, + + output addr_t icache_ar_addr_o, + output prot_t icache_ar_prot_o, + output region_t icache_ar_region_o, + output len_t icache_ar_len_o, + output size_t icache_ar_size_o, + output burst_t icache_ar_burst_o, + output logic icache_ar_lock_o, + output cache_t icache_ar_cache_o, + output qos_t icache_ar_qos_o, + output id_icache_t icache_ar_id_o, + output user_t icache_ar_user_o, + output logic icache_ar_valid_o, + input logic icache_ar_ready_i, + + output data_icache_t icache_w_data_o, + output strb_icache_t icache_w_strb_o, + output user_t icache_w_user_o, + output logic icache_w_last_o, + output logic icache_w_valid_o, + input logic icache_w_ready_i, + + input data_icache_t icache_r_data_i, + input resp_t icache_r_resp_i, + input logic icache_r_last_i, + input id_icache_t icache_r_id_i, + input user_t icache_r_user_i, + input logic icache_r_valid_i, + output logic icache_r_ready_o, + + input resp_t icache_b_resp_i, + input id_icache_t icache_b_id_i, + input user_t icache_b_user_i, + input logic icache_b_valid_i, + output logic icache_b_ready_o, + + input logic task_valid_i, + output logic task_ready_o, + input pspin_cfg_pkg::handler_task_t task_descr_i, + + output logic feedback_valid_o, + input logic feedback_ready_i, + output pspin_cfg_pkg::feedback_descr_t feedback_o, + + output logic cluster_active_o, + + input logic cmd_ready_i, + output logic cmd_valid_o, + output pspin_cfg_pkg::pspin_cmd_t cmd_o, + + input logic cmd_resp_valid_i, + input pspin_cfg_pkg::pspin_cmd_resp_t cmd_resp_i +); + + pulp_cluster #( + .ASYNC_INTF (ASYNC), + .NB_CORES (N_CORES), + .NB_HWACC_PORTS (0), + .NB_DMAS (N_DMAS), + .CLUSTER_ALIAS (1'b1), + .CLUSTER_ALIAS_BASE (12'h1B0), + .TCDM_SIZE (TCDM_SIZE), + .NB_TCDM_BANKS (N_TCDM_BANKS), + .XNE_PRESENT (1'b0), + // I$ Parameters + .NB_CACHE_BANKS (4), + .CACHE_SIZE (ICACHE_SIZE), + .L2_SIZE (L2_SIZE), + // Core Parameters + .DEM_PER_BEFORE_TCDM_TS (1'b0), + .ROM_BOOT_ADDR (32'h1A00_0000), + .BOOT_ADDR (32'h1D00_0080), + // AXI Parameters + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_C2S_WIDTH (AXI_DW), + .AXI_DATA_S2C_WIDTH (AXI_DW), + .AXI_USER_WIDTH (AXI_UW), + .AXI_ID_IN_WIDTH (AXI_IW_SLV), + .AXI_ID_OUT_WIDTH (AXI_IW_MST), + .DC_SLICE_BUFFER_WIDTH (DC_BUF_W), + // TCDM and Interconnect Parameters + .DATA_WIDTH (32), + .ADDR_WIDTH (32), + .TEST_SET_BIT (20), + // DMA Parameters + .NB_OUTSND_BURSTS (DMA_MAX_N_TXNS), + .MCHAN_BURST_LENGTH (DMA_MAX_BURST_SIZE) + ) i_bound ( + .clk_i, + .rst_ni, + .ref_clk_i, + + .pmu_mem_pwdn_i (1'b0), + .base_addr_i ('0), + .test_mode_i ('0), + .en_sa_boot_i ('0), + + .cluster_id_i, + + .fetch_en_i, + .eoc_o, + .busy_o, + + .ext_events_writetoken_i ('0), + .ext_events_readpointer_o (), + .ext_events_dataasync_i ('0), + .dma_pe_evt_ack_i ('0), + .dma_pe_evt_valid_o (), + .dma_pe_irq_ack_i ('0), + .dma_pe_irq_valid_o (), + .pf_evt_ack_i ('0), + .pf_evt_valid_o (), + + .data_slave_aw_addr_i (slv_aw_addr_i), + .data_slave_aw_prot_i (slv_aw_prot_i), + .data_slave_aw_region_i (slv_aw_region_i), + .data_slave_aw_len_i (slv_aw_len_i), + .data_slave_aw_size_i (slv_aw_size_i), + .data_slave_aw_burst_i (slv_aw_burst_i), + .data_slave_aw_lock_i (slv_aw_lock_i), + .data_slave_aw_atop_i (slv_aw_atop_i), + .data_slave_aw_cache_i (slv_aw_cache_i), + .data_slave_aw_qos_i (slv_aw_qos_i), + .data_slave_aw_id_i (slv_aw_id_i), + .data_slave_aw_user_i (slv_aw_user_i), + .data_slave_aw_writetoken_i (slv_aw_writetoken_i), + .data_slave_aw_readpointer_o (slv_aw_readpointer_o), + .data_slave_aw_valid_i (slv_aw_valid_i), + .data_slave_aw_ready_o (slv_aw_ready_o), + .data_slave_ar_addr_i (slv_ar_addr_i), + .data_slave_ar_prot_i (slv_ar_prot_i), + .data_slave_ar_region_i (slv_ar_region_i), + .data_slave_ar_len_i (slv_ar_len_i), + .data_slave_ar_size_i (slv_ar_size_i), + .data_slave_ar_burst_i (slv_ar_burst_i), + .data_slave_ar_lock_i (slv_ar_lock_i), + .data_slave_ar_cache_i (slv_ar_cache_i), + .data_slave_ar_qos_i (slv_ar_qos_i), + .data_slave_ar_id_i (slv_ar_id_i), + .data_slave_ar_user_i (slv_ar_user_i), + .data_slave_ar_writetoken_i (slv_ar_writetoken_i), + .data_slave_ar_readpointer_o (slv_ar_readpointer_o), + .data_slave_ar_valid_i (slv_ar_valid_i), + .data_slave_ar_ready_o (slv_ar_ready_o), + .data_slave_w_data_i (slv_w_data_i), + .data_slave_w_strb_i (slv_w_strb_i), + .data_slave_w_user_i (slv_w_user_i), + .data_slave_w_last_i (slv_w_last_i), + .data_slave_w_writetoken_i (slv_w_writetoken_i), + .data_slave_w_readpointer_o (slv_w_readpointer_o), + .data_slave_w_valid_i (slv_w_valid_i), + .data_slave_w_ready_o (slv_w_ready_o), + .data_slave_r_data_o (slv_r_data_o), + .data_slave_r_resp_o (slv_r_resp_o), + .data_slave_r_last_o (slv_r_last_o), + .data_slave_r_id_o (slv_r_id_o), + .data_slave_r_user_o (slv_r_user_o), + .data_slave_r_writetoken_o (slv_r_writetoken_o), + .data_slave_r_readpointer_i (slv_r_readpointer_i), + .data_slave_r_valid_o (slv_r_valid_o), + .data_slave_r_ready_i (slv_r_ready_i), + .data_slave_b_resp_o (slv_b_resp_o), + .data_slave_b_id_o (slv_b_id_o), + .data_slave_b_user_o (slv_b_user_o), + .data_slave_b_writetoken_o (slv_b_writetoken_o), + .data_slave_b_readpointer_i (slv_b_readpointer_i), + .data_slave_b_valid_o (slv_b_valid_o), + .data_slave_b_ready_i (slv_b_ready_i), + + .data_master_aw_addr_o (mst_aw_addr_o), + .data_master_aw_prot_o (mst_aw_prot_o), + .data_master_aw_region_o (mst_aw_region_o), + .data_master_aw_len_o (mst_aw_len_o), + .data_master_aw_size_o (mst_aw_size_o), + .data_master_aw_burst_o (mst_aw_burst_o), + .data_master_aw_lock_o (mst_aw_lock_o), + .data_master_aw_atop_o (mst_aw_atop_o), + .data_master_aw_cache_o (), + .data_master_aw_qos_o (mst_aw_qos_o), + .data_master_aw_id_o (mst_aw_id_o), + .data_master_aw_user_o (mst_aw_user_o), + .data_master_aw_writetoken_o (mst_aw_writetoken_o), + .data_master_aw_readpointer_i (mst_aw_readpointer_i), + .data_master_aw_valid_o (mst_aw_valid_o), + .data_master_aw_ready_i (mst_aw_ready_i), + .data_master_ar_addr_o (mst_ar_addr_o), + .data_master_ar_prot_o (mst_ar_prot_o), + .data_master_ar_region_o (mst_ar_region_o), + .data_master_ar_len_o (mst_ar_len_o), + .data_master_ar_size_o (mst_ar_size_o), + .data_master_ar_burst_o (mst_ar_burst_o), + .data_master_ar_lock_o (mst_ar_lock_o), + .data_master_ar_cache_o (), + .data_master_ar_qos_o (mst_ar_qos_o), + .data_master_ar_id_o (mst_ar_id_o), + .data_master_ar_user_o (mst_ar_user_o), + .data_master_ar_writetoken_o (mst_ar_writetoken_o), + .data_master_ar_readpointer_i (mst_ar_readpointer_i), + .data_master_ar_valid_o (mst_ar_valid_o), + .data_master_ar_ready_i (mst_ar_ready_i), + .data_master_w_data_o (mst_w_data_o), + .data_master_w_strb_o (mst_w_strb_o), + .data_master_w_user_o (mst_w_user_o), + .data_master_w_last_o (mst_w_last_o), + .data_master_w_writetoken_o (mst_w_writetoken_o), + .data_master_w_readpointer_i (mst_w_readpointer_i), + .data_master_w_valid_o (mst_w_valid_o), + .data_master_w_ready_i (mst_w_ready_i), + .data_master_r_data_i (mst_r_data_i), + .data_master_r_resp_i (mst_r_resp_i), + .data_master_r_last_i (mst_r_last_i), + .data_master_r_id_i (mst_r_id_i), + .data_master_r_user_i (mst_r_user_i), + .data_master_r_writetoken_i (mst_r_writetoken_i), + .data_master_r_readpointer_o (mst_r_readpointer_o), + .data_master_r_valid_i (mst_r_valid_i), + .data_master_r_ready_o (mst_r_ready_o), + .data_master_b_resp_i (mst_b_resp_i), + .data_master_b_id_i (mst_b_id_i), + .data_master_b_user_i (mst_b_user_i), + .data_master_b_writetoken_i (mst_b_writetoken_i), + .data_master_b_readpointer_o (mst_b_readpointer_o), + .data_master_b_valid_i (mst_b_valid_i), + .data_master_b_ready_o (mst_b_ready_o), + + .dma_aw_addr_o, + .dma_aw_prot_o, + .dma_aw_region_o, + .dma_aw_len_o, + .dma_aw_size_o, + .dma_aw_burst_o, + .dma_aw_lock_o, + .dma_aw_atop_o, + .dma_aw_cache_o (), + .dma_aw_qos_o, + .dma_aw_id_o, + .dma_aw_user_o, + .dma_aw_valid_o, + .dma_aw_ready_i, + .dma_ar_addr_o, + .dma_ar_prot_o, + .dma_ar_region_o, + .dma_ar_len_o, + .dma_ar_size_o, + .dma_ar_burst_o, + .dma_ar_lock_o, + .dma_ar_cache_o (), + .dma_ar_qos_o, + .dma_ar_id_o, + .dma_ar_user_o, + .dma_ar_valid_o, + .dma_ar_ready_i, + .dma_w_data_o, + .dma_w_strb_o, + .dma_w_user_o, + .dma_w_last_o, + .dma_w_valid_o, + .dma_w_ready_i, + .dma_r_data_i, + .dma_r_resp_i, + .dma_r_last_i, + .dma_r_id_i, + .dma_r_user_i, + .dma_r_valid_i, + .dma_r_ready_o, + .dma_b_resp_i, + .dma_b_id_i, + .dma_b_user_i, + .dma_b_valid_i, + .dma_b_ready_o, + + .nhi_aw_addr_i, + .nhi_aw_prot_i, + .nhi_aw_region_i, + .nhi_aw_len_i, + .nhi_aw_size_i, + .nhi_aw_burst_i, + .nhi_aw_lock_i, + .nhi_aw_atop_i, + .nhi_aw_cache_i, + .nhi_aw_qos_i, + .nhi_aw_id_i, + .nhi_aw_user_i, + .nhi_aw_valid_i, + .nhi_aw_ready_o, + .nhi_ar_addr_i, + .nhi_ar_prot_i, + .nhi_ar_region_i, + .nhi_ar_len_i, + .nhi_ar_size_i, + .nhi_ar_burst_i, + .nhi_ar_lock_i, + .nhi_ar_cache_i, + .nhi_ar_qos_i, + .nhi_ar_id_i, + .nhi_ar_user_i, + .nhi_ar_valid_i, + .nhi_ar_ready_o, + .nhi_w_data_i, + .nhi_w_strb_i, + .nhi_w_user_i, + .nhi_w_last_i, + .nhi_w_valid_i, + .nhi_w_ready_o, + .nhi_r_data_o, + .nhi_r_resp_o, + .nhi_r_last_o, + .nhi_r_id_o, + .nhi_r_user_o, + .nhi_r_valid_o, + .nhi_r_ready_i, + .nhi_b_resp_o, + .nhi_b_id_o, + .nhi_b_user_o, + .nhi_b_valid_o, + .nhi_b_ready_i, + + .icache_aw_addr_o, + .icache_aw_prot_o, + .icache_aw_region_o, + .icache_aw_len_o, + .icache_aw_size_o, + .icache_aw_burst_o, + .icache_aw_lock_o, + .icache_aw_atop_o, + .icache_aw_cache_o, + .icache_aw_qos_o, + .icache_aw_id_o, + .icache_aw_user_o, + .icache_aw_valid_o, + .icache_aw_ready_i, + .icache_ar_addr_o, + .icache_ar_prot_o, + .icache_ar_region_o, + .icache_ar_len_o, + .icache_ar_size_o, + .icache_ar_burst_o, + .icache_ar_lock_o, + .icache_ar_cache_o, + .icache_ar_qos_o, + .icache_ar_id_o, + .icache_ar_user_o, + .icache_ar_valid_o, + .icache_ar_ready_i, + .icache_w_data_o, + .icache_w_strb_o, + .icache_w_user_o, + .icache_w_last_o, + .icache_w_valid_o, + .icache_w_ready_i, + .icache_r_data_i, + .icache_r_resp_i, + .icache_r_last_i, + .icache_r_id_i, + .icache_r_user_i, + .icache_r_valid_i, + .icache_r_ready_o, + .icache_b_resp_i, + .icache_b_id_i, + .icache_b_user_i, + .icache_b_valid_i, + .icache_b_ready_o, + + .task_valid_i (task_valid_i), + .task_ready_o (task_ready_o), + .task_descr_i (task_descr_i), + .feedback_valid_o (feedback_valid_o), + .feedback_ready_i (feedback_ready_i), + .feedback_o (feedback_o), + .cluster_active_o (cluster_active_o), + .cmd_ready_i (cmd_ready_i), + .cmd_valid_o (cmd_valid_o), + .cmd_o (cmd_o), + .cmd_resp_valid_i (cmd_resp_valid_i), + .cmd_resp_i (cmd_resp_i) + ); + // Make all reads and writes from cluster modifiable. + // TODO: This might be undesired for transactions from cores to peripherals, better modify the + // DMA and I$ to issue modifiable transactions. + assign mst_ar_cache_o = 4'b0010; + assign mst_aw_cache_o = 4'b0010; + assign dma_ar_cache_o = 4'b0010; + assign dma_aw_cache_o = 4'b0010; + +endmodule + + +// Interface wrapper for OOC-synthesized synchronous PULP cluster +module pulp_cluster_sync ( + input logic clk_i, + input logic rst_ni, + input logic ref_clk_i, + input cluster_id_t cluster_id_i, + input logic fetch_en_i, + output logic eoc_o, + output logic busy_o, + AXI_BUS.Slave slv, + AXI_BUS.Master mst, + AXI_BUS.Master dma, + AXI_BUS.Master icache, + AXI_BUS.Slave nhi, + + input logic task_valid_i, + output logic task_ready_o, + input pspin_cfg_pkg::handler_task_t task_descr_i, + output logic feedback_valid_o, + input logic feedback_ready_i, + output pspin_cfg_pkg::feedback_descr_t feedback_o, + output logic cluster_active_o, + input logic cmd_ready_i, + output logic cmd_valid_o, + output pspin_cfg_pkg::pspin_cmd_t cmd_o, + input logic cmd_resp_valid_i, + input pspin_cfg_pkg::pspin_cmd_resp_t cmd_resp_i +); + + pulp_cluster_ooc i_ooc ( + .clk_i, + .rst_ni, + .ref_clk_i, + .cluster_id_i, + .fetch_en_i, + .eoc_o, + .busy_o, + + .slv_aw_addr_i (slv.aw_addr), + .slv_aw_prot_i (slv.aw_prot), + .slv_aw_region_i (slv.aw_region), + .slv_aw_len_i (slv.aw_len), + .slv_aw_size_i (slv.aw_size), + .slv_aw_burst_i (slv.aw_burst), + .slv_aw_lock_i (slv.aw_lock), + .slv_aw_atop_i (slv.aw_atop), + .slv_aw_cache_i (slv.aw_cache), + .slv_aw_qos_i (slv.aw_qos), + .slv_aw_id_i (slv.aw_id), + .slv_aw_user_i (slv.aw_user), + .slv_aw_valid_i (slv.aw_valid), + .slv_aw_ready_o (slv.aw_ready), + .slv_aw_writetoken_i (), + .slv_aw_readpointer_o (), + .slv_ar_addr_i (slv.ar_addr), + .slv_ar_prot_i (slv.ar_prot), + .slv_ar_region_i (slv.ar_region), + .slv_ar_len_i (slv.ar_len), + .slv_ar_size_i (slv.ar_size), + .slv_ar_burst_i (slv.ar_burst), + .slv_ar_lock_i (slv.ar_lock), + .slv_ar_cache_i (slv.ar_cache), + .slv_ar_qos_i (slv.ar_qos), + .slv_ar_id_i (slv.ar_id), + .slv_ar_user_i (slv.ar_user), + .slv_ar_valid_i (slv.ar_valid), + .slv_ar_ready_o (slv.ar_ready), + .slv_ar_writetoken_i (), + .slv_ar_readpointer_o (), + .slv_w_data_i (slv.w_data), + .slv_w_strb_i (slv.w_strb), + .slv_w_user_i (slv.w_user), + .slv_w_last_i (slv.w_last), + .slv_w_valid_i (slv.w_valid), + .slv_w_ready_o (slv.w_ready), + .slv_w_writetoken_i (), + .slv_w_readpointer_o (), + .slv_r_data_o (slv.r_data), + .slv_r_resp_o (slv.r_resp), + .slv_r_last_o (slv.r_last), + .slv_r_id_o (slv.r_id), + .slv_r_user_o (slv.r_user), + .slv_r_valid_o (slv.r_valid), + .slv_r_ready_i (slv.r_ready), + .slv_r_writetoken_o (), + .slv_r_readpointer_i (), + .slv_b_resp_o (slv.b_resp), + .slv_b_id_o (slv.b_id), + .slv_b_user_o (slv.b_user), + .slv_b_valid_o (slv.b_valid), + .slv_b_ready_i (slv.b_ready), + .slv_b_writetoken_o (), + .slv_b_readpointer_i (), + + .mst_aw_addr_o (mst.aw_addr), + .mst_aw_prot_o (mst.aw_prot), + .mst_aw_region_o (mst.aw_region), + .mst_aw_len_o (mst.aw_len), + .mst_aw_size_o (mst.aw_size), + .mst_aw_burst_o (mst.aw_burst), + .mst_aw_lock_o (mst.aw_lock), + .mst_aw_atop_o (mst.aw_atop), + .mst_aw_cache_o (mst.aw_cache), + .mst_aw_qos_o (mst.aw_qos), + .mst_aw_id_o (mst.aw_id), + .mst_aw_user_o (mst.aw_user), + .mst_aw_valid_o (mst.aw_valid), + .mst_aw_ready_i (mst.aw_ready), + .mst_aw_writetoken_o (), + .mst_aw_readpointer_i (), + .mst_ar_addr_o (mst.ar_addr), + .mst_ar_prot_o (mst.ar_prot), + .mst_ar_region_o (mst.ar_region), + .mst_ar_len_o (mst.ar_len), + .mst_ar_size_o (mst.ar_size), + .mst_ar_burst_o (mst.ar_burst), + .mst_ar_lock_o (mst.ar_lock), + .mst_ar_cache_o (mst.ar_cache), + .mst_ar_qos_o (mst.ar_qos), + .mst_ar_id_o (mst.ar_id), + .mst_ar_user_o (mst.ar_user), + .mst_ar_valid_o (mst.ar_valid), + .mst_ar_ready_i (mst.ar_ready), + .mst_ar_writetoken_o (), + .mst_ar_readpointer_i (), + .mst_w_data_o (mst.w_data), + .mst_w_strb_o (mst.w_strb), + .mst_w_user_o (mst.w_user), + .mst_w_last_o (mst.w_last), + .mst_w_valid_o (mst.w_valid), + .mst_w_ready_i (mst.w_ready), + .mst_w_writetoken_o (), + .mst_w_readpointer_i (), + .mst_r_data_i (mst.r_data), + .mst_r_resp_i (mst.r_resp), + .mst_r_last_i (mst.r_last), + .mst_r_id_i (mst.r_id), + .mst_r_user_i (mst.r_user), + .mst_r_valid_i (mst.r_valid), + .mst_r_ready_o (mst.r_ready), + .mst_r_writetoken_i (), + .mst_r_readpointer_o (), + .mst_b_resp_i (mst.b_resp), + .mst_b_id_i (mst.b_id), + .mst_b_user_i (mst.b_user), + .mst_b_valid_i (mst.b_valid), + .mst_b_ready_o (mst.b_ready), + .mst_b_writetoken_i (), + .mst_b_readpointer_o (), + + .dma_aw_addr_o (dma.aw_addr), + .dma_aw_prot_o (dma.aw_prot), + .dma_aw_region_o (dma.aw_region), + .dma_aw_len_o (dma.aw_len), + .dma_aw_size_o (dma.aw_size), + .dma_aw_burst_o (dma.aw_burst), + .dma_aw_lock_o (dma.aw_lock), + .dma_aw_atop_o (dma.aw_atop), + .dma_aw_cache_o (dma.aw_cache), + .dma_aw_qos_o (dma.aw_qos), + .dma_aw_id_o (dma.aw_id), + .dma_aw_user_o (dma.aw_user), + .dma_aw_valid_o (dma.aw_valid), + .dma_aw_ready_i (dma.aw_ready), + .dma_ar_addr_o (dma.ar_addr), + .dma_ar_prot_o (dma.ar_prot), + .dma_ar_region_o (dma.ar_region), + .dma_ar_len_o (dma.ar_len), + .dma_ar_size_o (dma.ar_size), + .dma_ar_burst_o (dma.ar_burst), + .dma_ar_lock_o (dma.ar_lock), + .dma_ar_cache_o (dma.ar_cache), + .dma_ar_qos_o (dma.ar_qos), + .dma_ar_id_o (dma.ar_id), + .dma_ar_user_o (dma.ar_user), + .dma_ar_valid_o (dma.ar_valid), + .dma_ar_ready_i (dma.ar_ready), + .dma_w_data_o (dma.w_data), + .dma_w_strb_o (dma.w_strb), + .dma_w_user_o (dma.w_user), + .dma_w_last_o (dma.w_last), + .dma_w_valid_o (dma.w_valid), + .dma_w_ready_i (dma.w_ready), + .dma_r_data_i (dma.r_data), + .dma_r_resp_i (dma.r_resp), + .dma_r_last_i (dma.r_last), + .dma_r_id_i (dma.r_id), + .dma_r_user_i (dma.r_user), + .dma_r_valid_i (dma.r_valid), + .dma_r_ready_o (dma.r_ready), + .dma_b_resp_i (dma.b_resp), + .dma_b_id_i (dma.b_id), + .dma_b_user_i (dma.b_user), + .dma_b_valid_i (dma.b_valid), + .dma_b_ready_o (dma.b_ready), + + .nhi_aw_addr_i (nhi.aw_addr), + .nhi_aw_prot_i (nhi.aw_prot), + .nhi_aw_region_i (nhi.aw_region), + .nhi_aw_len_i (nhi.aw_len), + .nhi_aw_size_i (nhi.aw_size), + .nhi_aw_burst_i (nhi.aw_burst), + .nhi_aw_lock_i (nhi.aw_lock), + .nhi_aw_atop_i (nhi.aw_atop), + .nhi_aw_cache_i (nhi.aw_cache), + .nhi_aw_qos_i (nhi.aw_qos), + .nhi_aw_id_i (nhi.aw_id), + .nhi_aw_user_i (nhi.aw_user), + .nhi_aw_valid_i (nhi.aw_valid), + .nhi_aw_ready_o (nhi.aw_ready), + .nhi_ar_addr_i (nhi.ar_addr), + .nhi_ar_prot_i (nhi.ar_prot), + .nhi_ar_region_i (nhi.ar_region), + .nhi_ar_len_i (nhi.ar_len), + .nhi_ar_size_i (nhi.ar_size), + .nhi_ar_burst_i (nhi.ar_burst), + .nhi_ar_lock_i (nhi.ar_lock), + .nhi_ar_cache_i (nhi.ar_cache), + .nhi_ar_qos_i (nhi.ar_qos), + .nhi_ar_id_i (nhi.ar_id), + .nhi_ar_user_i (nhi.ar_user), + .nhi_ar_valid_i (nhi.ar_valid), + .nhi_ar_ready_o (nhi.ar_ready), + .nhi_w_data_i (nhi.w_data), + .nhi_w_strb_i (nhi.w_strb), + .nhi_w_user_i (nhi.w_user), + .nhi_w_last_i (nhi.w_last), + .nhi_w_valid_i (nhi.w_valid), + .nhi_w_ready_o (nhi.w_ready), + .nhi_r_data_o (nhi.r_data), + .nhi_r_resp_o (nhi.r_resp), + .nhi_r_last_o (nhi.r_last), + .nhi_r_id_o (nhi.r_id), + .nhi_r_user_o (nhi.r_user), + .nhi_r_valid_o (nhi.r_valid), + .nhi_r_ready_i (nhi.r_ready), + .nhi_b_resp_o (nhi.b_resp), + .nhi_b_id_o (nhi.b_id), + .nhi_b_user_o (nhi.b_user), + .nhi_b_valid_o (nhi.b_valid), + .nhi_b_ready_i (nhi.b_ready), + + .icache_aw_addr_o (icache.aw_addr), + .icache_aw_prot_o (icache.aw_prot), + .icache_aw_region_o (icache.aw_region), + .icache_aw_len_o (icache.aw_len), + .icache_aw_size_o (icache.aw_size), + .icache_aw_burst_o (icache.aw_burst), + .icache_aw_lock_o (icache.aw_lock), + .icache_aw_atop_o (icache.aw_atop), + .icache_aw_cache_o (icache.aw_cache), + .icache_aw_qos_o (icache.aw_qos), + .icache_aw_id_o (icache.aw_id), + .icache_aw_user_o (icache.aw_user), + .icache_aw_valid_o (icache.aw_valid), + .icache_aw_ready_i (icache.aw_ready), + .icache_ar_addr_o (icache.ar_addr), + .icache_ar_prot_o (icache.ar_prot), + .icache_ar_region_o (icache.ar_region), + .icache_ar_len_o (icache.ar_len), + .icache_ar_size_o (icache.ar_size), + .icache_ar_burst_o (icache.ar_burst), + .icache_ar_lock_o (icache.ar_lock), + .icache_ar_cache_o (icache.ar_cache), + .icache_ar_qos_o (icache.ar_qos), + .icache_ar_id_o (icache.ar_id), + .icache_ar_user_o (icache.ar_user), + .icache_ar_valid_o (icache.ar_valid), + .icache_ar_ready_i (icache.ar_ready), + .icache_w_data_o (icache.w_data), + .icache_w_strb_o (icache.w_strb), + .icache_w_user_o (icache.w_user), + .icache_w_last_o (icache.w_last), + .icache_w_valid_o (icache.w_valid), + .icache_w_ready_i (icache.w_ready), + .icache_r_data_i (icache.r_data), + .icache_r_resp_i (icache.r_resp), + .icache_r_last_i (icache.r_last), + .icache_r_id_i (icache.r_id), + .icache_r_user_i (icache.r_user), + .icache_r_valid_i (icache.r_valid), + .icache_r_ready_o (icache.r_ready), + .icache_b_resp_i (icache.b_resp), + .icache_b_id_i (icache.b_id), + .icache_b_user_i (icache.b_user), + .icache_b_valid_i (icache.b_valid), + .icache_b_ready_o (icache.b_ready), + + .task_valid_i (task_valid_i), + .task_ready_o (task_ready_o), + .task_descr_i (task_descr_i), + .feedback_valid_o (feedback_valid_o), + .feedback_ready_i (feedback_ready_i), + .feedback_o (feedback_o), + .cluster_active_o (cluster_active_o), + .cmd_ready_i (cmd_ready_i), + .cmd_valid_o (cmd_valid_o), + .cmd_o (cmd_o), + .cmd_resp_valid_i (cmd_resp_valid_i), + .cmd_resp_i (cmd_resp_i) + ); +endmodule + +// Interface wrapper for OOC-synthesized asynchronous PULP cluster +module pulp_cluster_async ( + input logic clk_i, + input logic rst_ni, + input logic ref_clk_i, + input cluster_id_t cluster_id_i, + input logic fetch_en_i, + output logic eoc_o, + output logic busy_o, + AXI_BUS_ASYNC.Slave slv, + AXI_BUS_ASYNC.Master mst, + AXI_BUS_ASYNC.Master dma, + AXI_BUS_ASYNC.Master icache +); + + pulp_cluster_ooc i_ooc ( + .clk_i, + .rst_ni, + .ref_clk_i, + .cluster_id_i, + .fetch_en_i, + .eoc_o, + .busy_o, + + .slv_aw_addr_i (slv.aw_addr), + .slv_aw_prot_i (slv.aw_prot), + .slv_aw_region_i (slv.aw_region), + .slv_aw_len_i (slv.aw_len), + .slv_aw_size_i (slv.aw_size), + .slv_aw_burst_i (slv.aw_burst), + .slv_aw_lock_i (slv.aw_lock), + .slv_aw_atop_i (slv.aw_atop), + .slv_aw_cache_i (slv.aw_cache), + .slv_aw_qos_i (slv.aw_qos), + .slv_aw_id_i (slv.aw_id), + .slv_aw_user_i (slv.aw_user), + .slv_aw_valid_i (), + .slv_aw_ready_o (), + .slv_aw_writetoken_i (slv.aw_writetoken), + .slv_aw_readpointer_o (slv.aw_readpointer), + .slv_ar_addr_i (slv.ar_addr), + .slv_ar_prot_i (slv.ar_prot), + .slv_ar_region_i (slv.ar_region), + .slv_ar_len_i (slv.ar_len), + .slv_ar_size_i (slv.ar_size), + .slv_ar_burst_i (slv.ar_burst), + .slv_ar_lock_i (slv.ar_lock), + .slv_ar_cache_i (slv.ar_cache), + .slv_ar_qos_i (slv.ar_qos), + .slv_ar_id_i (slv.ar_id), + .slv_ar_user_i (slv.ar_user), + .slv_ar_valid_i (), + .slv_ar_ready_o (), + .slv_ar_writetoken_i (slv.ar_writetoken), + .slv_ar_readpointer_o (slv.ar_readpointer), + .slv_w_data_i (slv.w_data), + .slv_w_strb_i (slv.w_strb), + .slv_w_user_i (slv.w_user), + .slv_w_last_i (slv.w_last), + .slv_w_valid_i (), + .slv_w_ready_o (), + .slv_w_writetoken_i (slv.w_writetoken), + .slv_w_readpointer_o (slv.w_readpointer), + .slv_r_data_o (slv.r_data), + .slv_r_resp_o (slv.r_resp), + .slv_r_last_o (slv.r_last), + .slv_r_id_o (slv.r_id), + .slv_r_user_o (slv.r_user), + .slv_r_valid_o (), + .slv_r_ready_i (), + .slv_r_writetoken_o (slv.r_writetoken), + .slv_r_readpointer_i (slv.r_readpointer), + .slv_b_resp_o (slv.b_resp), + .slv_b_id_o (slv.b_id), + .slv_b_user_o (slv.b_user), + .slv_b_valid_o (), + .slv_b_ready_i (), + .slv_b_writetoken_o (slv.b_writetoken), + .slv_b_readpointer_i (slv.b_readpointer), + + .mst_aw_addr_o (mst.aw_addr), + .mst_aw_prot_o (mst.aw_prot), + .mst_aw_region_o (mst.aw_region), + .mst_aw_len_o (mst.aw_len), + .mst_aw_size_o (mst.aw_size), + .mst_aw_burst_o (mst.aw_burst), + .mst_aw_lock_o (mst.aw_lock), + .mst_aw_atop_o (mst.aw_atop), + .mst_aw_cache_o (mst.aw_cache), + .mst_aw_qos_o (mst.aw_qos), + .mst_aw_id_o (mst.aw_id), + .mst_aw_user_o (mst.aw_user), + .mst_aw_valid_o (), + .mst_aw_ready_i (), + .mst_aw_writetoken_o (mst.aw_writetoken), + .mst_aw_readpointer_i (mst.aw_readpointer), + .mst_ar_addr_o (mst.ar_addr), + .mst_ar_prot_o (mst.ar_prot), + .mst_ar_region_o (mst.ar_region), + .mst_ar_len_o (mst.ar_len), + .mst_ar_size_o (mst.ar_size), + .mst_ar_burst_o (mst.ar_burst), + .mst_ar_lock_o (mst.ar_lock), + .mst_ar_cache_o (mst.ar_cache), + .mst_ar_qos_o (mst.ar_qos), + .mst_ar_id_o (mst.ar_id), + .mst_ar_user_o (mst.ar_user), + .mst_ar_valid_o (), + .mst_ar_ready_i (), + .mst_ar_writetoken_o (mst.ar_writetoken), + .mst_ar_readpointer_i (mst.ar_readpointer), + .mst_w_data_o (mst.w_data), + .mst_w_strb_o (mst.w_strb), + .mst_w_user_o (mst.w_user), + .mst_w_last_o (mst.w_last), + .mst_w_valid_o (), + .mst_w_ready_i (), + .mst_w_writetoken_o (mst.w_writetoken), + .mst_w_readpointer_i (mst.w_readpointer), + .mst_r_data_i (mst.r_data), + .mst_r_resp_i (mst.r_resp), + .mst_r_last_i (mst.r_last), + .mst_r_id_i (mst.r_id), + .mst_r_user_i (mst.r_user), + .mst_r_valid_i (), + .mst_r_ready_o (), + .mst_r_writetoken_i (mst.r_writetoken), + .mst_r_readpointer_o (mst.r_readpointer), + .mst_b_resp_i (mst.b_resp), + .mst_b_id_i (mst.b_id), + .mst_b_user_i (mst.b_user), + .mst_b_valid_i (), + .mst_b_ready_o (), + .mst_b_writetoken_i (mst.b_writetoken), + .mst_b_readpointer_o (mst.b_readpointer), + + .dma_aw_addr_o (dma.aw_addr), + .dma_aw_prot_o (dma.aw_prot), + .dma_aw_region_o (dma.aw_region), + .dma_aw_len_o (dma.aw_len), + .dma_aw_size_o (dma.aw_size), + .dma_aw_burst_o (dma.aw_burst), + .dma_aw_lock_o (dma.aw_lock), + .dma_aw_atop_o (dma.aw_atop), + .dma_aw_cache_o (dma.aw_cache), + .dma_aw_qos_o (dma.aw_qos), + .dma_aw_id_o (dma.aw_id), + .dma_aw_user_o (dma.aw_user), + .dma_aw_valid_o (), + .dma_aw_ready_i (), + .dma_ar_addr_o (dma.ar_addr), + .dma_ar_prot_o (dma.ar_prot), + .dma_ar_region_o (dma.ar_region), + .dma_ar_len_o (dma.ar_len), + .dma_ar_size_o (dma.ar_size), + .dma_ar_burst_o (dma.ar_burst), + .dma_ar_lock_o (dma.ar_lock), + .dma_ar_cache_o (dma.ar_cache), + .dma_ar_qos_o (dma.ar_qos), + .dma_ar_id_o (dma.ar_id), + .dma_ar_user_o (dma.ar_user), + .dma_ar_valid_o (), + .dma_ar_ready_i (), + .dma_w_data_o (dma.w_data), + .dma_w_strb_o (dma.w_strb), + .dma_w_user_o (dma.w_user), + .dma_w_last_o (dma.w_last), + .dma_w_valid_o (), + .dma_w_ready_i (), + .dma_r_data_i (dma.r_data), + .dma_r_resp_i (dma.r_resp), + .dma_r_last_i (dma.r_last), + .dma_r_id_i (dma.r_id), + .dma_r_user_i (dma.r_user), + .dma_r_valid_i (), + .dma_r_ready_o (), + .dma_b_resp_i (dma.b_resp), + .dma_b_id_i (dma.b_id), + .dma_b_user_i (dma.b_user), + .dma_b_valid_i (), + .dma_b_ready_o (), + + .icache_aw_addr_o (icache.aw_addr), + .icache_aw_prot_o (icache.aw_prot), + .icache_aw_region_o (icache.aw_region), + .icache_aw_len_o (icache.aw_len), + .icache_aw_size_o (icache.aw_size), + .icache_aw_burst_o (icache.aw_burst), + .icache_aw_lock_o (icache.aw_lock), + .icache_aw_atop_o (icache.aw_atop), + .icache_aw_cache_o (icache.aw_cache), + .icache_aw_qos_o (icache.aw_qos), + .icache_aw_id_o (icache.aw_id), + .icache_aw_user_o (icache.aw_user), + .icache_aw_valid_o (), + .icache_aw_ready_i (), + .icache_ar_addr_o (icache.ar_addr), + .icache_ar_prot_o (icache.ar_prot), + .icache_ar_region_o (icache.ar_region), + .icache_ar_len_o (icache.ar_len), + .icache_ar_size_o (icache.ar_size), + .icache_ar_burst_o (icache.ar_burst), + .icache_ar_lock_o (icache.ar_lock), + .icache_ar_cache_o (icache.ar_cache), + .icache_ar_qos_o (icache.ar_qos), + .icache_ar_id_o (icache.ar_id), + .icache_ar_user_o (icache.ar_user), + .icache_ar_valid_o (), + .icache_ar_ready_i (), + .icache_w_data_o (icache.w_data), + .icache_w_strb_o (icache.w_strb), + .icache_w_user_o (icache.w_user), + .icache_w_last_o (icache.w_last), + .icache_w_valid_o (), + .icache_w_ready_i (), + .icache_r_data_i (icache.r_data), + .icache_r_resp_i (icache.r_resp), + .icache_r_last_i (icache.r_last), + .icache_r_id_i (icache.r_id), + .icache_r_user_i (icache.r_user), + .icache_r_valid_i (), + .icache_r_ready_o (), + .icache_b_resp_i (icache.b_resp), + .icache_b_id_i (icache.b_id), + .icache_b_user_i (icache.b_user), + .icache_b_valid_i (), + .icache_b_ready_o () + ); +endmodule diff --git a/hw/src/soc_ctrl_regs.sv b/hw/src/soc_ctrl_regs.sv new file mode 100644 index 0000000..508cfa0 --- /dev/null +++ b/hw/src/soc_ctrl_regs.sv @@ -0,0 +1,92 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module soc_ctrl_regs #( + parameter int unsigned N_CORES = 0, + parameter int unsigned N_CLUSTERS = 0, + parameter int unsigned ADDR_WIDTH = 0, + parameter int unsigned DATA_WIDTH = 0 +) ( + input logic clk_i, + input logic rst_ni, + APB_BUS.Slave apb +); + + localparam int unsigned N_SLV = 5; + + APB_BUS #( + .APB_ADDR_WIDTH (ADDR_WIDTH), + .APB_DATA_WIDTH (DATA_WIDTH) + ) apb_bus[N_SLV-1:0] (); + + apb_bus_wrap #( + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .N_SLV (N_SLV), + .ADDR_BEGIN ({32'h0000_0090, 32'h0000_0080, 32'h0000_0014, 32'h0000_0010, 32'h0000_0000}), + .ADDR_END ({32'h0000_0FFF, 32'h0000_008F, 32'h0000_007F, 32'h0000_0013, 32'h0000_000F}) + ) i_apb_bus ( + .inp (apb), + .oup (apb_bus) + ); + + apb_ro_regs #( + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .N_REGS (4) + ) i_zero_0 ( + .apb (apb_bus[0]), + .reg_i ('0) + ); + + logic [DATA_WIDTH-1:0] info_reg; + assign info_reg = {N_CORES, N_CLUSTERS}; + apb_ro_regs #( + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .N_REGS (1) + ) i_info ( + .apb (apb_bus[1]), + .reg_i (info_reg) + ); + + apb_ro_regs #( + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .N_REGS (27) + ) i_zero_1 ( + .apb (apb_bus[2]), + .reg_i ('0) + ); + + apb_rw_regs #( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .N_REGS (4) // TODO: Why 4 and not the actual number of cores? Are these regs even needed? + ) i_core_res ( + .clk_i, + .rst_ni, + .apb (apb_bus[3]), + .init_i ('0), + .q_o () + ); + + apb_ro_regs #( + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .N_REGS (988) + ) i_zero_2 ( + .apb (apb_bus[4]), + /* verilator lint_off WIDTHCONCAT */ + .reg_i ('0) + /* verilator lint_on WIDTHCONCAT */ + ); + +endmodule diff --git a/hw/src/soc_dma_wrap.sv b/hw/src/soc_dma_wrap.sv new file mode 100644 index 0000000..a6d03a7 --- /dev/null +++ b/hw/src/soc_dma_wrap.sv @@ -0,0 +1,336 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +import pspin_cfg_pkg::*; + +module soc_dma_wrap #( + /// id width of the DMA AXI Master port + parameter int unsigned DmaAxiIdWidth = -1, + /// data width of the DMA AXI Master port + parameter int unsigned DmaDataWidth = -1, + /// user width + parameter int unsigned DmaUserWidth = -1, + /// number of AX requests in-flight + parameter int unsigned AxiAxReqDepth = -1, + /// number of 1D transfers buffered in backend + parameter int unsigned TfReqFifoDepth = -1, + /// NHI data request type + parameter type axi_nhi_req_t = logic, + /// NHI data response type + parameter type axi_nhi_res_t = logic, + /// host data request type (64 bit) + parameter type axi_host_req_t = logic, + /// host data response type (64 bit) + parameter type axi_host_res_t = logic +) ( + input logic clk_i, + input logic rst_ni, + + //command + input logic cmd_req_valid_i, + output logic cmd_req_ready_o, + input pspin_cmd_t cmd_req_i, + + //response + output logic cmd_resp_valid_o, + output pspin_cmd_resp_t cmd_resp_o, + + /// to NHI (32 bit address) + output axi_nhi_req_t nhi_req_o, + input axi_nhi_res_t nhi_resp_i, + + /// to host (64 bit address) + output axi_host_req_t host_req_o, + input axi_host_res_t host_resp_i +); + + localparam logic[64:0] PCIeStartAddr = 65'h1_0000_0000_0000_0000; + localparam logic[64:0] PCIeEndAddr = 65'h1_FFFF_FFFF_FFFF_FFFF; + localparam logic[64:0] NHIStartAddr = 65'h0_0000_0000_0000_0000; + localparam logic[64:0] NHIEndAddr = 65'h0_0000_0000_FFFF_FFFF; + + localparam int unsigned IDX_PCIE = 0; + localparam int unsigned IDX_NHI = 1; + localparam int unsigned RespFIFODepth = TfReqFifoDepth + AxiAxReqDepth; + + localparam int unsigned DmaAddrWidth = 65; //64th bit used to distinguish host/NIC addresses + + logic [$clog2(RespFIFODepth):0] to_pop_rx_d; + logic [$clog2(RespFIFODepth):0] to_pop_rx_q; + + logic [$clog2(RespFIFODepth):0] to_pop_tx_d; + logic [$clog2(RespFIFODepth):0] to_pop_tx_q; + + logic tx_req_valid, rx_req_valid; + logic tx_req_ready, rx_req_ready; + logic tx_resp_valid, rx_resp_valid; + + transf_descr_soc_t xfer_descr; + pspin_cmd_resp_t cmd_resp; + + pspin_cmd_resp_t cmd_rx_resp, cmd_tx_resp; + + logic fifo_rx_full, fifo_tx_full; + logic fifo_rx_sel, fifo_tx_sel; + + logic fifo_rx_pop, fifo_tx_pop; + + logic fifo_rx_resp_avail, fifo_tx_resp_avail; + + assign xfer_descr.num_bytes = cmd_req_i.descr.host_dma_cmd.length; + + assign xfer_descr.dst_addr[64] = (cmd_req_i.descr.host_dma_cmd.nic_to_host) ? 1'b1 : 1'b0; + assign xfer_descr.dst_addr[63:32] = (cmd_req_i.descr.host_dma_cmd.nic_to_host) ? cmd_req_i.descr.host_dma_cmd.host_addr[63:32] : '0; + assign xfer_descr.dst_addr[31:0] = (cmd_req_i.descr.host_dma_cmd.nic_to_host) ? cmd_req_i.descr.host_dma_cmd.host_addr[31:0] : cmd_req_i.descr.host_dma_cmd.nic_addr; + + assign xfer_descr.src_addr[64] = (cmd_req_i.descr.host_dma_cmd.nic_to_host) ? 1'b0 : 1'b1; + assign xfer_descr.src_addr[63:32] = (cmd_req_i.descr.host_dma_cmd.nic_to_host) ? '0 : cmd_req_i.descr.host_dma_cmd.host_addr[63:32]; + assign xfer_descr.src_addr[31:0] = (cmd_req_i.descr.host_dma_cmd.nic_to_host) ? cmd_req_i.descr.host_dma_cmd.nic_addr : cmd_req_i.descr.host_dma_cmd.host_addr[31:0]; + assign xfer_descr.deburst = 1'b0; + assign xfer_descr.decouple = 1'b1; + assign xfer_descr.serialize = 1'b0; // TODO: connect me! + + assign cmd_resp.cmd_id = cmd_req_i.cmd_id; + + always_comb begin + cmd_req_ready_o = 1'b0; + rx_req_valid = 1'b0; + tx_req_valid = 1'b0; + + if (cmd_req_valid_i) begin + cmd_req_ready_o = (cmd_req_i.descr.host_dma_cmd.nic_to_host) ? (!fifo_rx_full && rx_req_ready) : (!fifo_tx_full && tx_req_ready); + rx_req_valid = cmd_req_i.descr.host_dma_cmd.nic_to_host == 1'b1; + tx_req_valid = cmd_req_i.descr.host_dma_cmd.nic_to_host == 1'b0; + end + end + + //FIFO with RX responses + assign fifo_rx_resp_avail = to_pop_rx_q > 0; + assign fifo_rx_pop = fifo_rx_resp_avail && fifo_rx_sel; + + fifo_v3 #( + .dtype (pspin_cmd_resp_t), + .DEPTH (RespFIFODepth) + ) i_rx_resp_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (fifo_rx_full), + .empty_o (), + .usage_o (), + .data_i (cmd_resp), + .push_i (cmd_req_ready_o && rx_req_valid), + .data_o (cmd_rx_resp), + .pop_i (fifo_rx_pop) + ); + + always_comb begin + case ({rx_resp_valid, fifo_rx_pop}) + 2'b10 : to_pop_rx_d = to_pop_rx_q + 1; + 2'b01 : to_pop_rx_d = to_pop_rx_q - 1; + default : to_pop_rx_d = to_pop_rx_q; + endcase + end + + //FIFO with TX responses + assign fifo_tx_resp_avail = to_pop_tx_q > 0; + assign fifo_tx_pop = fifo_tx_resp_avail && fifo_tx_sel; + + fifo_v3 #( + .dtype (pspin_cmd_resp_t), + .DEPTH (RespFIFODepth) + ) i_tx_resp_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (fifo_tx_full), + .empty_o (), + .usage_o (), + .data_i (cmd_resp), + .push_i (cmd_req_ready_o && tx_req_valid), + .data_o (cmd_tx_resp), + .pop_i (fifo_tx_pop) + ); + + always_comb begin + case ({tx_resp_valid, fifo_tx_pop}) + 2'b10 : to_pop_tx_d = to_pop_tx_q + 1; + 2'b01 : to_pop_tx_d = to_pop_tx_q - 1; + default : to_pop_tx_d = to_pop_tx_q; + endcase + end + + // arbitrate response from the two ports + rr_arb_tree #( + .NumIn (2), + .DataType (pspin_cmd_resp_t), + .ExtPrio (0), + .AxiVldRdy (1), + .LockIn (1) + ) i_resp_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .rr_i ('0), + .req_i ({fifo_tx_resp_avail, fifo_rx_resp_avail}), + .gnt_o ({fifo_tx_sel, fifo_rx_sel}), + .data_i ({cmd_tx_resp, cmd_rx_resp}), + .gnt_i (1'b1), + .req_o (cmd_resp_valid_o), + .data_o (cmd_resp_o), + .idx_o () + ); + + typedef logic [DmaDataWidth-1 :0] data_t; + typedef logic [DmaAxiIdWidth-1 :0] id_t; + typedef logic [DmaDataWidth/8-1 :0] strb_t; + typedef logic [DmaUserWidth-1 :0] user_t; + typedef logic [DmaAddrWidth-1 :0] wide_addr_t; + + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, wide_addr_t, id_t, user_t); + `AXI_TYPEDEF_W_CHAN_T (w_chan_t, data_t, strb_t, user_t); + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, wide_addr_t, id_t, user_t); + `AXI_TYPEDEF_B_CHAN_T (b_chan_t, id_t, user_t); + `AXI_TYPEDEF_R_CHAN_T (r_chan_t, data_t, id_t, user_t); + `AXI_TYPEDEF_REQ_T (axi_dma_wide_req_t, aw_chan_t, w_chan_t, ar_chan_t); + `AXI_TYPEDEF_RESP_T (axi_dma_wide_resp_t, b_chan_t, r_chan_t); + + axi_dma_wide_req_t nhi_wide_req; + axi_dma_wide_req_t host_wide_req; + + //cut NHI address to 32 bit (lower) + assign nhi_req_o.aw.id = nhi_wide_req.aw.id; + assign nhi_req_o.aw.addr = nhi_wide_req.aw.addr[31:0]; + assign nhi_req_o.aw.len = nhi_wide_req.aw.len; + assign nhi_req_o.aw.size = nhi_wide_req.aw.size; + assign nhi_req_o.aw.burst = nhi_wide_req.aw.burst; + assign nhi_req_o.aw.lock = nhi_wide_req.aw.lock; + assign nhi_req_o.aw.cache = nhi_wide_req.aw.cache; + assign nhi_req_o.aw.prot = nhi_wide_req.aw.prot; + assign nhi_req_o.aw.qos = nhi_wide_req.aw.qos; + assign nhi_req_o.aw.region = nhi_wide_req.aw.region; + assign nhi_req_o.aw.atop = nhi_wide_req.aw.atop; + assign nhi_req_o.aw.user = nhi_wide_req.aw.user; + assign nhi_req_o.aw_valid = nhi_wide_req.aw_valid; + + assign nhi_req_o.w.data = nhi_wide_req.w.data; + assign nhi_req_o.w.strb = nhi_wide_req.w.strb; + assign nhi_req_o.w.last = nhi_wide_req.w.last; + assign nhi_req_o.w.user = nhi_wide_req.w.user; + assign nhi_req_o.w_valid = nhi_wide_req.w_valid; + + assign nhi_req_o.ar.id = nhi_wide_req.ar.id; + assign nhi_req_o.ar.addr = nhi_wide_req.ar.addr[31:0]; + assign nhi_req_o.ar.len = nhi_wide_req.ar.len; + assign nhi_req_o.ar.size = nhi_wide_req.ar.size; + assign nhi_req_o.ar.burst = nhi_wide_req.ar.burst; + assign nhi_req_o.ar.lock = nhi_wide_req.ar.lock; + assign nhi_req_o.ar.cache = nhi_wide_req.ar.cache; + assign nhi_req_o.ar.prot = nhi_wide_req.ar.prot; + assign nhi_req_o.ar.qos = nhi_wide_req.ar.qos; + assign nhi_req_o.ar.region = nhi_wide_req.ar.region; + assign nhi_req_o.ar.user = nhi_wide_req.ar.user; + assign nhi_req_o.ar_valid = nhi_wide_req.ar_valid; + + assign nhi_req_o.r_ready = nhi_wide_req.r_ready; + assign nhi_req_o.b_ready = nhi_wide_req.b_ready; + + //cut host address to 64 bit (lower) + assign host_req_o.aw.id = host_wide_req.aw.id; + assign host_req_o.aw.addr = host_wide_req.aw.addr[63:0]; + assign host_req_o.aw.len = host_wide_req.aw.len; + assign host_req_o.aw.size = host_wide_req.aw.size; + assign host_req_o.aw.burst = host_wide_req.aw.burst; + assign host_req_o.aw.lock = host_wide_req.aw.lock; + assign host_req_o.aw.cache = host_wide_req.aw.cache; + assign host_req_o.aw.prot = host_wide_req.aw.prot; + assign host_req_o.aw.qos = host_wide_req.aw.qos; + assign host_req_o.aw.region = host_wide_req.aw.region; + assign host_req_o.aw.atop = host_wide_req.aw.atop; + assign host_req_o.aw.user = host_wide_req.aw.user; + assign host_req_o.aw_valid = host_wide_req.aw_valid; + + assign host_req_o.w.data = host_wide_req.w.data; + assign host_req_o.w.strb = host_wide_req.w.strb; + assign host_req_o.w.last = host_wide_req.w.last; + assign host_req_o.w.user = host_wide_req.w.user; + assign host_req_o.w_valid = host_wide_req.w_valid; + + assign host_req_o.ar.id = host_wide_req.ar.id; + assign host_req_o.ar.addr = host_wide_req.ar.addr[63:0]; + assign host_req_o.ar.len = host_wide_req.ar.len; + assign host_req_o.ar.size = host_wide_req.ar.size; + assign host_req_o.ar.burst = host_wide_req.ar.burst; + assign host_req_o.ar.lock = host_wide_req.ar.lock; + assign host_req_o.ar.cache = host_wide_req.ar.cache; + assign host_req_o.ar.prot = host_wide_req.ar.prot; + assign host_req_o.ar.qos = host_wide_req.ar.qos; + assign host_req_o.ar.region = host_wide_req.ar.region; + assign host_req_o.ar.user = host_wide_req.ar.user; + assign host_req_o.ar_valid = host_wide_req.ar_valid; + + assign host_req_o.r_ready = host_wide_req.r_ready; + assign host_req_o.b_ready = host_wide_req.b_ready; + + //DMA engine + pspin_soc_dma #( + .DmaAxiIdWidth (DmaAxiIdWidth), + .DmaDataWidth (DmaDataWidth), + .DmaAddrWidth (DmaAddrWidth), + .DmaUserWidth (DmaUserWidth), + .AxiAxReqDepth (AxiAxReqDepth), + .TfReqFifoDepth (TfReqFifoDepth), + .axi_req_t (axi_dma_wide_req_t), + .axi_res_t (axi_dma_wide_resp_t), + .transf_descr_t (pspin_cfg_pkg::transf_descr_soc_t), + .PCIeStartAddr (PCIeStartAddr), + .PCIeEndAddr (PCIeEndAddr), + .NHIStartAddr (NHIStartAddr), + .NHIEndAddr (NHIEndAddr) + ) i_soc_dma ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + //direct hw port 1 + .rx_req_valid_i (rx_req_valid ), + .rx_req_ready_o (rx_req_ready ), + .rx_req_i (xfer_descr ), + .rx_rsp_valid_o (rx_resp_valid ), + //direct hw port 2 + .tx_req_valid_i (tx_req_valid ), + .tx_req_ready_o (tx_req_ready ), + .tx_req_i (xfer_descr ), + .tx_rsp_valid_o (tx_resp_valid ), + //AXI wide port 1 (to NHI) + .nhi_dma_req_o (nhi_wide_req ), + .nhi_dma_res_i (nhi_resp_i ), + //AXI wide port 2 (to HOST) + .pcie_dma_req_o (host_wide_req ), + .pcie_dma_res_i (host_resp_i ), + //status + .idle_o ( ) + ); + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + to_pop_tx_q <= '0; + to_pop_rx_q <= '0; + end else begin + to_pop_tx_q <= to_pop_tx_d; + to_pop_rx_q <= to_pop_rx_d; + end + end + +endmodule \ No newline at end of file diff --git a/hw/src/soc_peripherals.sv b/hw/src/soc_peripherals.sv new file mode 100644 index 0000000..2ac46a8 --- /dev/null +++ b/hw/src/soc_peripherals.sv @@ -0,0 +1,94 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module soc_peripherals #( + parameter int unsigned AXI_AW = 0, + parameter int unsigned AXI_IW = 0, + parameter int unsigned AXI_UW = 0, + parameter int unsigned N_CORES = 0, + parameter int unsigned N_CLUSTERS = 0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic test_en_i, + + AXI_BUS.Slave axi +); + + localparam int unsigned APB_AW = 32; + localparam int unsigned APB_DW = 32; + localparam int unsigned AXI_DW = 64; + + APB_BUS #( + .APB_ADDR_WIDTH (APB_AW), + .APB_DATA_WIDTH (APB_DW) + ) apb (); + + axi2apb_wrap #( + .AXI_ADDR_WIDTH (AXI_AW), + .AXI_DATA_WIDTH (AXI_DW), + .AXI_ID_WIDTH (AXI_IW), + .AXI_USER_WIDTH (AXI_UW), + .APB_ADDR_WIDTH (APB_AW), + .APB_DATA_WIDTH (APB_DW) + ) i_axi2apb ( + .clk_i, + .rst_ni, + .test_en_i, + .axi_slave (axi), + .apb_master (apb) + ); + + APB_BUS #( + .APB_ADDR_WIDTH (APB_AW), + .APB_DATA_WIDTH (APB_DW) + ) apb_periphs[1:0] (); + + apb_bus_wrap #( + .ADDR_WIDTH (APB_AW), + .DATA_WIDTH (APB_DW), + .N_SLV (2), + .ADDR_BEGIN ({32'h1A10_4000, 32'h1A10_3000}), + .ADDR_END ({32'h1A10_4FFF, 32'h1A10_3FFF}) + ) i_bus ( + .inp (apb), + .oup (apb_periphs) + ); + + `ifndef TARGET_SYNTHESIS + apb_stdout #( + .N_CORES (N_CORES), + .N_CLUSTERS (N_CLUSTERS), + .ADDR_WIDTH (APB_AW), + .DATA_WIDTH (APB_DW) + ) i_stdout ( + .clk_i, + .rst_ni, + .apb (apb_periphs[1]) + ); + `else + assign apb_periphs[1].pready = 1'b1; + assign apb_periphs[1].pslverr = 1'b1; + assign apb_periphs[1].prdata = '0; + `endif + + soc_ctrl_regs #( + .N_CORES (N_CORES), + .N_CLUSTERS (N_CLUSTERS), + .ADDR_WIDTH (APB_AW), + .DATA_WIDTH (APB_DW) + ) i_soc_ctrl_regs ( + .clk_i, + .rst_ni, + .apb (apb_periphs[0]) + ); + +endmodule diff --git a/hw/verilator_model/Makefile b/hw/verilator_model/Makefile new file mode 100644 index 0000000..d3aafa4 --- /dev/null +++ b/hw/verilator_model/Makefile @@ -0,0 +1,285 @@ +PSPIN_VERSION ?= undef +VERILATOR_CMD ?= verilator +VERILATOR_CC=$(VERILATOR_BIN)$(VERILATOR_CMD) +TOP_MODULE=pspin_verilator +SIM_EXE_SRCS=src/main.cpp +SIM_LIB_SRCS=src/pspinsim.cpp + +TRACE_DEPTH?=6 +VFLAGS_RELEASE=--Mdir obj_dir_release --sv -Wno-UNOPTFLAT -Wno-NOLATCH -Wno-WIDTHCONCAT -j 8 +systemverilogext+sv -Wno-lint -CFLAGS "-fPIC" +VFLAGS_DEBUG=--Mdir obj_dir_debug --sv --assert --trace --trace-structs --trace-depth $(TRACE_DEPTH) -CFLAGS "-DVERILATOR_HAS_TRACE -fPIC" -Wno-UNOPTFLAT -Wno-NOLATCH -Wno-WIDTHCONCAT -j 8 +systemverilogext+sv -Wno-lint + +CC ?= gcc +CXX ?= g++ + +LIB_RELEASE_FLAGS=-fPIC --std=c++11 -Os -shared -Iobj_dir_release -I$(VERILATOR_HOME)/include -I$(VERILATOR_HOME)/include/vltstd/ -Iinclude/ +LIB_DEBUG_FLAGS=-fPIC -g --std=c++11 -Os -shared -Iobj_dir_debug -I$(VERILATOR_HOME)/include -I$(VERILATOR_HOME)/include/vltstd/ -Iinclude/ -DVERILATOR_HAS_TRACE + +EXE_RELEASE_FLAGS=-Iinclude/ +EXE_DEBUG_FLAGS=-Iinclude/ -DVERILATOR_HAS_TRACE + +SV_INC=-I../deps/axi/include/ -I../deps/common_cells/include -I../deps/cluster_interconnect/rtl/low_latency_interco/ -I../deps/riscv/include/ +SV_SRCS=../deps/axi/src/axi_pkg.sv \ + ../deps/axi/src/axi_intf.sv \ + ../src/pulp_cluster_cfg_pkg.sv \ + ../src/pspin_cfg_pkg.sv \ + ../deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \ + ../deps/common_cells/src/fifo_v3.sv \ + ../deps/common_cells/src/stream_fifo.sv \ + ../deps/axi/src/axi_buf.sv \ + ../deps/common_cells/src/delta_counter.sv \ + ../deps/common_cells/src/cf_math_pkg.sv \ + ../deps/common_cells/src/lzc.sv \ + ../deps/common_cells/src/rr_arb_tree.sv \ + ../deps/common_cells/src/spill_register.sv \ + ../deps/axi/src/axi_demux.sv \ + ../deps/riscv/include/fpnew_pkg.sv \ + ../deps/riscv/include/riscv_defines.sv \ + ../deps/common_cells/src/deprecated/fifo_v2.sv \ + ../deps/common_cells/src/fall_through_register.sv \ + ../deps/common_cells/src/stream_demux.sv \ + ../deps/common_cells/src/stream_mux.sv \ + ../deps/common_cells/src/stream_fork.sv \ + ../deps/common_cells/src/stream_fork_dynamic.sv \ + ../deps/common_cells/src/stream_to_mem.sv \ + ../deps/common_cells/src/stream_join.sv \ + ../deps/axi2mem/src/axi_to_mem.sv \ + ../deps/cluster_interconnect/rtl/tcdm_interconnect/addr_dec_resp_mux.sv \ + ../deps/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv \ + ../deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv \ + ../deps/axi2mem/src/axi_to_mem_banked_mp.sv \ + ../deps/tech_cells_generic/src/rtl/tc_sram.sv \ + ../src/memories/sram.sv \ + ../src/memories/l2_mem.sv \ + ../src/pkt_scheduler/fifo_engine.sv \ + ../src/pkt_scheduler/mpq_engine.sv \ + ../src/pkt_scheduler/scheduler.sv \ + ../deps/axi/src/dma/axi_dma_burst_reshaper.sv \ + ../deps/axi/src/dma/axi_dma_data_path \ + ../deps/axi/src/dma/axi_dma_data_mover.sv \ + ../deps/axi/src/dma/axi_dma_backend.sv \ + ../deps/common_cells/src/addr_decode.sv \ + ../deps/common_cells/src/stream_register.sv \ + ../deps/common_cells/src/counter.sv \ + ../deps/axi/src/axi_atop_filter.sv \ + ../deps/axi/src/axi_err_slv.sv \ + ../deps/axi/src/axi_id_prepend.sv \ + ../deps/axi/src/axi_mux.sv \ + ../deps/axi/src/axi_xbar.sv \ + ../deps/axi/src/dma/frontends/pspin_soc_frontend/src/pspin_soc_dma.sv \ + ../src/soc_dma_wrap.sv \ + ../src/cmds/cmd_unit.sv \ + ../deps/pulp_cluster/packages/pulp_cluster_package.sv \ + ../deps/riscv/include/apu_core_package.sv \ + ../deps/pulp_cluster/packages/apu_package.sv \ + ../deps/cluster_interconnect/rtl/interfaces/xbar_tcdm_bus.sv \ + ../deps/cluster_interconnect/rtl/interfaces/xbar_periph_bus.sv \ + ../deps/pulp_cluster/rtl/cpu_marx_if.sv \ + ../deps/cluster_interconnect/rtl/interfaces/tcdm_bank_mem_bus.sv \ + ../deps/cluster_interconnect/rtl/interfaces/wide_dma_tcdm.sv \ + ../deps/cluster_peripherals/icache_ctrl_unit/interfaces/mp_pf_icache_ctrl_unit_bus.sv \ + ../deps/common_cells/src/rstgen_bypass.sv \ + ../deps/common_cells/src/rstgen.sv \ + ../deps/pulp_cluster/rtl/cluster_bus_wrap.sv \ + ../deps/axi_slice/src/axi_w_buffer.sv \ + ../deps/axi_slice/src/axi_r_buffer.sv \ + ../deps/axi_slice/src/axi_ar_buffer.sv \ + ../deps/axi_slice/src/axi_b_buffer.sv \ + ../deps/common_cells/src/deprecated/fifo_v1.sv \ + ../deps/axi_slice/src/axi_single_slice.sv \ + ../deps/axi_slice/src/axi_aw_buffer.sv \ + ../deps/axi2per/axi2per_req_channel.sv \ + ../deps/axi2per/axi2per_res_channel.sv \ + ../deps/axi2per/axi2per.sv \ + ../deps/pulp_cluster/rtl/axi2per_wrap.sv \ + ../deps/pulp_cluster/rtl/per_demux_wrap.sv \ + ../deps/per2axi/src/per2axi_req_channel.sv \ + ../deps/per2axi/src/per2axi_res_channel.sv \ + ../deps/per2axi/src/per2axi_busy_unit.sv \ + ../deps/per2axi/src/per2axi.sv \ + ../deps/pulp_cluster/rtl/per2axi_wrap.sv \ + ../deps/pulp_cluster/rtl/tryx_ctrl.sv \ + ../deps/cluster_interconnect/rtl/tcdm_interconnect/superbank_addr_decoder.sv \ + ../deps/cluster_interconnect/rtl/tcdm_interconnect/tcdm_superbank_mux.sv \ + ../deps/cluster_interconnect/rtl/tcdm_interconnect/amo_shim.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/RR_Flag_Req_PE \ + ../deps/cluster_interconnect/rtl/peripheral_interco/ArbitrationTree_PE.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/MUX2_REQ_PE.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/RequestBlock2CH_PE.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_PE_Resp \ + ../deps/cluster_interconnect/rtl/peripheral_interco/ResponseTree_PE.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_PE_Req.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/ResponseBlock_PE.sv \ + ../deps/cluster_interconnect/rtl/peripheral_interco/XBAR_PE.sv \ + ../deps/pulp_cluster/rtl/cluster_interconnect_wrap.sv \ + ../deps/axi/src/axi_serializer.sv \ + ../deps/axi/src/dma/frontends/pulp_cluster_frontend/src/transfer_id_gen.sv \ + ../deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend_regs.sv \ + ../deps/axi/src/dma/frontends/pulp_cluster_frontend/src/pulp_cluster_frontend.sv \ + ../deps/pulp_cluster/rtl/dmac_wrap.sv \ + ../deps/axi2mem/src/axi_to_mem_interleaved.sv \ + ../deps/pulp_cluster/rtl/nhi_port_wrap.sv \ + ../deps/event_unit_flex/message_bus.sv \ + ../deps/cluster_peripherals/cluster_control_unit/cluster_control_unit.sv \ + ../deps/pulp_cluster/rtl/cluster_timer_wrap.sv \ + ../deps/timer_unit/rtl/timer_unit_counter_presc.sv \ + ../deps/timer_unit/rtl/timer_unit_counter.sv \ + ../deps/timer_unit/rtl/timer_unit.sv \ + ../deps/event_unit_flex/event_unit_interface_mux.sv \ + ../deps/pulp_cluster/rtl/cluster_event_map.sv \ + ../deps/event_unit_flex/interc_sw_evt_trig.sv \ + ../deps/event_unit_flex/event_unit_core.sv \ + ../deps/event_unit_flex/hw_barrier_unit.sv \ + ../deps/event_unit_flex/hw_mutex_unit.sv \ + ../deps/event_unit_flex/hw_dispatch.sv \ + ../deps/event_unit_flex/event_unit_top.sv \ + ../deps/cluster_peripherals/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv \ + ../deps/pulp_cluster/rtl/cluster_peripherals.sv \ + ../src/pkt_scheduler/cluster_rb.sv \ + ../src/pkt_scheduler/cluster_scheduler.sv \ + ../src/cmds/cluster_cmd.sv \ + ../deps/cluster_interconnect/rtl/interfaces/xbar_demux_bus.sv \ + ../deps/riscv/verilator-model/cluster_clock_gating.sv \ + ../deps/riscv/riscv_L0_buffer.sv \ + ../deps/riscv/riscv_prefetch_L0_buffer.sv \ + ../deps/riscv/riscv_hwloop_controller.sv \ + ../deps/riscv/riscv_compressed_decoder.sv \ + ../deps/riscv/riscv_if_stage.sv \ + ../deps/riscv/riscv_register_file.sv \ + ../deps/riscv/riscv_decoder.sv \ + ../deps/riscv/riscv_controller.sv \ + ../deps/riscv/riscv_int_controller.sv \ + ../deps/riscv/riscv_hwloop_regs.sv \ + ../deps/riscv/riscv_id_stage.sv \ + ../deps/riscv/riscv_popcnt.sv \ + ../deps/riscv/riscv_ff_one.sv \ + ../deps/riscv/riscv_alu_div.sv \ + ../deps/riscv/riscv_alu.sv \ + ../deps/riscv/riscv_mult.sv \ + ../deps/riscv/riscv_apu_disp.sv \ + ../deps/riscv/riscv_ex_stage.sv \ + ../deps/riscv/riscv_load_store_unit.sv \ + ../deps/riscv/riscv_cs_registers.sv \ + ../deps/riscv/riscv_pmp.sv \ + ../deps/riscv/include/riscv_tracer_defines.sv \ + ../deps/riscv/riscv_tracer.sv \ + ../deps/riscv/riscv_core.sv \ + ../deps/common_cells/src/deprecated/generic_fifo.sv \ + ../deps/pulp_cluster/rtl/periph_FIFO.sv \ + ../deps/pulp_cluster/rtl/core_demux.sv \ + ../deps/riscv/riscv_store_buffer.sv \ + ../deps/pulp_cluster/rtl/periph_demux.sv \ + ../deps/pulp_cluster/rtl/inter_core_fifo.sv \ + ../deps/pulp_cluster/rtl/virtual_stdout_demux.sv \ + ../deps/pulp_cluster/rtl/core_region.sv \ + ../src/pkt_scheduler/hpu_driver.sv \ + ../deps/common_cells/src/deprecated/generic_LFSR_8bit.sv \ + ../deps/common_cells/src/onehot_to_bin.sv \ + ../deps/icache_mp_128_pf/RTL/icache_bank_mp_128.sv \ + ../deps/scm/latch_scm/register_file_1w_multi_port_read.sv \ + ../deps/icache-intc/Req_Arb_Node_icache_intc.sv \ + ../deps/icache-intc/DistributedArbitrationNetwork_Req_icache_intc.sv \ + ../deps/icache-intc/RoutingBlock_Req_icache_intc.sv \ + ../deps/icache-intc/DistributedArbitrationNetwork_Resp_icache_intc.sv \ + ../deps/icache-intc/RoutingBlock_Resp_icache_intc.sv \ + ../deps/icache-intc/icache_intc.sv \ + ../deps/icache_mp_128_pf/RTL/pf_miss_mux.sv \ + ../deps/icache_mp_128_pf/RTL/merge_refill_cam_128_16.sv \ + ../deps/icache_mp_128_pf/RTL/central_controller_128.sv \ + ../deps/icache_mp_128_pf/RTL/cache_controller_to_axi_128_PF.sv \ + ../deps/icache_mp_128_pf/RTL/icache_bank_mp_PF.sv \ + ../deps/icache_mp_128_pf/RTL/prefetcher_if.sv \ + ../deps/icache_mp_128_pf/RTL/icache_top_mp_128_PF.sv \ + ../deps/axi/src/axi_cut.sv \ + ../deps/axi_slice_dc/src/dc_token_ring.v \ + ../deps/axi_slice_dc/src/dc_synchronizer.v \ + ../deps/axi_slice_dc/src/dc_token_ring_fifo_dout.v \ + ../deps/common_cells/src/edge_propagator_tx.sv \ + ../deps/pulp_cluster/rtl/pulp_cluster.sv \ + ../src/pulp_cluster_ooc.sv \ + ../src/memories/prog_mem.sv \ + ../deps/axi/src/axi_dw_upsizer.sv \ + ../deps/axi/src/axi_dw_converter.sv \ + ../src/interconnects/pe_noc.sv \ + ../src/interconnects/dma_noc.sv \ + ../src/interconnects/cluster_noc.sv \ + ../src/interconnects/l2_xbar.sv \ + ../deps/axi/src/axi_id_remap.sv \ + ../src/interconnects/nhi_xbar.sv \ + ../deps/axi_riscv_atomics/src/axi_riscv_amos_alu.sv \ + ../deps/axi_riscv_atomics/src/axi_riscv_amos.sv \ + ../deps/common_cells/src/id_queue.sv \ + ../deps/common_cells/src/stream_filter.sv \ + ../deps/common_cells/src/stream_arbiter_flushable.sv \ + ../deps/common_cells/src/stream_arbiter.sv \ + ../deps/axi_riscv_atomics/src/axi_res_tbl.sv \ + ../deps/axi_riscv_atomics/src/axi_riscv_lrsc.sv \ + ../deps/axi_riscv_atomics/src/axi_riscv_atomics.sv \ + ../deps/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv \ + ../deps/apb/src/apb_intf.sv \ + ../deps/axi2apb/src/axi2apb_64_32.sv \ + ../deps/axi2apb/src/axi2apb_wrap.sv \ + ../src/apb/apb_bus.sv \ + ../src/apb/apb_bus_wrap.sv \ + ../src/apb/apb_stdout.sv \ + ../src/apb/apb_ro_regs.sv \ + ../src/apb/apb_rw_regs.sv \ + ../src/soc_ctrl_regs.sv \ + ../src/soc_peripherals.sv \ + ../deps/axi/src/axi_dw_downsizer.sv \ + ../src/host_direct.sv \ + ../src/host_mst_mux.sv \ + ../src/pspin.sv \ + ../src/pspin_verilator.sv \ + +.PHONY: archive + +lib/libpspin_debug.so: + $(VERILATOR_CC) $(VFLAGS_DEBUG) $(SV_INC) -cc $(SV_SRCS) --top-module $(TOP_MODULE) --build $(SIM_LIB_SRCS) -o pspin + @mkdir -p lib/ + $(CXX) $(LIB_DEBUG_FLAGS) -o lib/libpspin_debug.so $(SIM_LIB_SRCS) obj_dir_debug/Vpspin_verilator__ALL.a $(VERILATOR_HOME)/include/verilated.cpp $(VERILATOR_HOME)/include/verilated_vcd_c.cpp + +lib/libpspin.so: + $(VERILATOR_CC) $(VFLAGS_RELEASE) $(SV_INC) -cc $(SV_SRCS) --top-module $(TOP_MODULE) --build $(SIM_LIB_SRCS) -o pspin + @mkdir -p lib/ + $(CXX) $(LIB_RELEASE_FLAGS) -o lib/libpspin.so $(SIM_LIB_SRCS) obj_dir_release/Vpspin_verilator__ALL.a $(VERILATOR_HOME)/include/verilated.cpp + +release: lib/libpspin.so + @mkdir -p bin/ + $(CC) $(EXE_RELEASE_FLAGS) $(SIM_EXE_SRCS) -Llib/ -lpspin -o bin/pspin_release + +debug: lib/libpspin_debug.so + @mkdir -p bin/ + $(CC) $(EXE_DEBUG_FLAGS) $(SIM_EXE_SRCS) -Llib/ -lpspin_debug -o bin/pspin_debug + +build-debug: debug + @mkdir -p verilator/ + @mkdir -p verilator/bin/ + cp start_sim.sh verilator/ + cp bin/pspin_debug verilator/bin/ + cp -r lib/ verilator/ + +build-release: release + @mkdir -p verilator/ + @mkdir -p verilator/bin/ + cp start_sim.sh verilator/ + cp bin/pspin_release verilator/bin/ + cp -r lib/ verilator/ + + +clean: + @rm -rf obj_dir_debug/ obj_dir_release/ bin/pspin bin/pspin_debug lib/libpspin.so lib/libpspin_debug.so > /dev/null 2> /dev/null + +pack: + mkdir -p pspin-v${PSPIN_VERSION}/sim_files/slm_files/ + mkdir -p pspin-v${PSPIN_VERSION}/verilator_model/bin/ + mkdir -p pspin-v${PSPIN_VERSION}/verilator_model/lib/ + cp bin/pspin* pspin-v${PSPIN_VERSION}/verilator_model/bin/ + cp lib/lib* pspin-v${PSPIN_VERSION}/verilator_model/lib/ + cp -r include pspin-v${PSPIN_VERSION}/verilator_model/ + cp start_sim.sh pspin-v${PSPIN_VERSION}/verilator_model/ + tar -czvf pspin-v${PSPIN_VERSION}.tar.gz pspin-v${PSPIN_VERSION}/ + +.PHONY: lib/libpspin.so lib/libpspin_debug.so clean pack diff --git a/hw/verilator_model/include/pspinsim.h b/hw/verilator_model/include/pspinsim.h new file mode 100644 index 0000000..472d86d --- /dev/null +++ b/hw/verilator_model/include/pspinsim.h @@ -0,0 +1,87 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __PSPINSIM_H__ +#define __PSPINSIM_H__ + +#include "spin.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct ni_conf +{ + uint32_t axi_aw_buffer; + uint32_t axi_w_buffer; + uint32_t axi_b_buffer; +} ni_conf_t; + +typedef struct no_conf +{ + uint32_t axi_ar_buffer; + uint32_t axi_r_buffer; + double network_G; + uint32_t max_pkt_size; + uint32_t max_network_queue_len; +} no_conf_t; + +typedef struct pcie_slv_conf +{ + uint32_t axi_aw_buffer; + uint32_t axi_w_buffer; + uint32_t axi_ar_buffer; + uint32_t axi_b_buffer; + uint32_t axi_r_buffer; + uint32_t pcie_L; + double pcie_G; +} pcie_slv_conf_t; + +typedef struct pspin_conf { + char *slm_files_path; + ni_conf_t ni_conf; + no_conf_t no_conf; + pcie_slv_conf_t pcie_slv_conf; +} pspin_conf_t; + +typedef void (*pkt_out_cb_t)(uint8_t*, size_t); +typedef void (*pkt_feedback_cb_t)(uint64_t, uint64_t, uint64_t, uint64_t); +typedef void (*pcie_slv_write_cb_t)(uint64_t, uint8_t*, size_t); +typedef void (*pcie_slv_read_cb_t)(uint64_t, uint8_t*, size_t); +typedef void (*pcie_mst_write_cb_t)(void*); +typedef void (*pcie_mst_read_cb_t)(void*); + +int pspinsim_default_conf(pspin_conf_t *conf); + +int pspinsim_init(int argc, char **argv, pspin_conf_t *conf); +int pspinsim_run(); +int pspinsim_run_tick(uint8_t *done_flag); +int pspinsim_fini(); + +int pspinsim_packet_trace_read(const char* pkt_file_path, const char* data_file_path); +int pspinsim_packet_add(spin_ec_t* ec, uint32_t msgid, uint8_t* pkt_data, size_t pkt_len, size_t pkt_l1_len, uint8_t eom, uint32_t wait_cycles, uint64_t user_ptr); +int pspinsim_packet_eos(); + +int pspinsim_cb_set_pkt_out(pkt_out_cb_t cb); +int pspinsim_cb_set_pcie_slv_write(pcie_slv_write_cb_t cb); +int pspinsim_cb_set_pcie_slv_read(pcie_slv_read_cb_t cb); +int pspinsim_cb_set_pcie_mst_write_completion(pcie_mst_write_cb_t cb); +int pspinsim_cb_set_pcie_mst_read_completion(pcie_mst_read_cb_t cb); +int pspinsim_cb_set_pkt_feedback(pkt_feedback_cb_t cb); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* __PSPINSIM_H__ */ diff --git a/hw/verilator_model/include/spin.h b/hw/verilator_model/include/spin.h new file mode 100644 index 0000000..6704992 --- /dev/null +++ b/hw/verilator_model/include/spin.h @@ -0,0 +1,72 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __SPIN_H__ +#define __SPIN_H__ + +#include +#include + +#include "spin_hw_conf.h" + +#define SPIN_SUCCESS 0 +#define SPIN_ERR 1 + +#ifdef __cplusplus +extern "C" { +#endif + +typedef uint32_t mem_addr_t; +typedef uint32_t mem_size_t; +typedef uint64_t host_addr_t; + +typedef struct spin_ec +{ + //handler memory + mem_addr_t handler_mem_addr; + mem_size_t handler_mem_size; + + //host memory + host_addr_t host_mem_addr; + mem_size_t host_mem_size; + + //header handler + mem_addr_t hh_addr; + mem_size_t hh_size; + + //payload handler + mem_addr_t ph_addr; + mem_size_t ph_size; + + //completion (aka tail) handler + mem_addr_t th_addr; + mem_size_t th_size; + + //L1 scratchpads + mem_addr_t scratchpad_addr[NUM_CLUSTERS]; + mem_size_t scratchpad_size[NUM_CLUSTERS]; + +} __attribute__((__packed__)) spin_ec_t; + +typedef uint32_t spin_nic_addr_t; + +int spin_nicmem_write(spin_nic_addr_t addr, void *data, size_t size, void* user_ptr); +int spin_nicmem_read(spin_nic_addr_t addr, void *data, size_t size, void* user_ptr); +int spin_find_handler_by_name(char *binfile, char* handler_name, spin_nic_addr_t *handler_addr, size_t *handler_size); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* __SPIN_H__ */ \ No newline at end of file diff --git a/hw/verilator_model/include/spin_hw_conf.h b/hw/verilator_model/include/spin_hw_conf.h new file mode 100644 index 0000000..597a907 --- /dev/null +++ b/hw/verilator_model/include/spin_hw_conf.h @@ -0,0 +1,41 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +// WARNING: this has to match pspin_cfg_pkg.sv !!! +#define NUM_CLUSTERS 4 +#define NUM_CORES 8 +#define C_MSGID_WIDTH 10 +#define PCIE_START_ADDR 0x1000000000000000 + +// 1 MiB +#define L1_CLUSTER_ACTUAL_MEM_SIZE 0x00100000 + +// 1 KiB reserved at the beginning. +#define L1_RUNTIME_OFFSET 0x00000400 + +// 16 KiB +#define L1_RUNTIME_SIZE 0x00004000 + +#define L1_PKT_BUFF_OFFSET (L1_RUNTIME_OFFSET + L1_RUNTIME_SIZE) + +// 32 KiB +#define L1_PKT_BUFF_SIZE 0x00008000 + +#define L2_PKT_BUFF_START 0x1c400000 +#define L2_PKT_BUFF_SIZE 4 * 1024 * 1024 + +#define L1_SCRATCHPAD_OFFSET (L1_PKT_BUFF_OFFSET + L1_PKT_BUFF_SIZE) +#define L1_SCRATCHPAD_SIZE (L1_CLUSTER_ACTUAL_MEM_SIZE - L1_PKT_BUFF_OFFSET) diff --git a/hw/verilator_model/src/AXIDriver.hpp b/hw/verilator_model/src/AXIDriver.hpp new file mode 100644 index 0000000..bf4b373 --- /dev/null +++ b/hw/verilator_model/src/AXIDriver.hpp @@ -0,0 +1,247 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#include "AXIPort.hpp" + +namespace PsPIN +{ + template + class AXIDriver + { + typedef typename AXIPortType::axi_addr_t axi_addr_t; + typedef typename AXIPortType::axi_strb_t axi_strb_t; + typedef typename AXIPortType::axi_prot_t axi_prot_t; + typedef typename AXIPortType::axi_region_t axi_region_t; + typedef typename AXIPortType::axi_len_t axi_len_t; + typedef typename AXIPortType::axi_size_t axi_size_t; + typedef typename AXIPortType::axi_burst_t axi_burst_t; + typedef typename AXIPortType::axi_lock_t axi_lock_t; + typedef typename AXIPortType::axi_atop_t axi_atop_t; + typedef typename AXIPortType::axi_cache_t axi_cache_t; + typedef typename AXIPortType::axi_qos_t axi_qos_t; + typedef typename AXIPortType::axi_id_t axi_id_t; + typedef typename AXIPortType::axi_user_t axi_user_t; + + protected: + typedef struct axi_ax_beat + { + axi_id_t ax_id; + axi_addr_t ax_addr; + axi_len_t ax_len; + axi_size_t ax_size; + axi_burst_t ax_burst; + axi_lock_t ax_lock; + axi_cache_t ax_cache; + axi_prot_t ax_prot; + axi_qos_t ax_qos; + axi_region_t ax_region; + axi_atop_t ax_atop; // Only defined on the AW channel. + axi_user_t ax_user; + + uint32_t offset; //bytes already received + } axi_ax_beat_t; + + typedef struct axi_w_beat + { + uint8_t w_data[AXI_SW]; + axi_strb_t w_strb; + axi_user_t w_user; + uint8_t w_last; + } axi_w_beat_t; + + typedef struct axi_b_beat + { + uint8_t b_resp; + axi_id_t b_id; + axi_user_t b_user; + } axi_b_beat_t; + + typedef struct axi_r_beat + { + uint8_t r_resp; + uint8_t r_last; + axi_id_t r_id; + axi_user_t r_user; + uint8_t r_data[AXI_SW]; + } axi_r_beat_t; + + typedef struct axi_b_queue_entry + { + uint32_t n_bursts; + void *b_callback_arg; + } axi_b_queue_entry_t; + + typedef struct axi_r_queue_entry + { + uint32_t data_left; + uint32_t n_bursts; + void *r_callback_arg; + } axi_r_queue_entry_t; + + typedef struct beat_and_size + { + axi_ax_beat_t beat; + uint32_t n_bytes; + } beat_and_size_t; + + public: + AXIDriver(AXIPortType &port) : port(port) + { + *port.aw_valid = 0; + *port.w_valid = 0; + *port.b_ready = 0; + *port.ar_valid = 0; + *port.r_ready = 0; + } + + virtual void posedge() = 0; + virtual void negedge() = 0; + + protected: + AXIPortType &port; + + protected: + uint32_t axi_num_bytes(axi_size_t size) + { + return 1 << size; + } + + axi_addr_t axi_aligned_address(axi_addr_t addr, axi_size_t size) + { + return (addr / axi_num_bytes(size)) * axi_num_bytes(size); + } + + axi_addr_t beat_addr(axi_ax_beat_t ax, uint32_t i_beat) + { + if (i_beat == 0) + return ax.ax_addr; + else + return axi_aligned_address(ax.ax_addr, ax.ax_size) + i_beat * (1 << ax.ax_size); + } + + uint32_t beat_lower_byte(axi_ax_beat_t ax, uint32_t i_beat) + { + axi_addr_t addr = beat_addr(ax, i_beat); + return addr - (addr / AXI_SW) * AXI_SW; + } + + uint32_t beat_upper_byte(axi_ax_beat_t ax, uint32_t i_beat, uint32_t n_bytes) + { + if (i_beat == 0) + { + return axi_aligned_address(ax.ax_addr, ax.ax_size) + (1 << ax.ax_size) - (ax.ax_addr / AXI_SW) * AXI_SW; + } + else if (i_beat == ax.ax_len) + { + return n_bytes - (AXI_SW - beat_lower_byte(ax, 0)) - (ax.ax_len - 1) * AXI_SW; + } + else + { + return beat_lower_byte(ax, i_beat) + (1 << ax.ax_size); + } + } + + uint64_t page_num(axi_addr_t addr) + { + return addr >> 12; + } + + void create_ax_beats(axi_addr_t addr, uint32_t n_bytes, std::queue &ax_beats) + { + uint64_t n_beats; + uint32_t bytes_in_first_beat, bytes_in_last_beat; + size_t ax_size; + + // Iteratively create Ax beats until all bytes have been transferred. + while (n_bytes > 0) + { + axi_ax_beat_t ax_beat; + uint32_t bytes_in_burst; + + memset(&ax_beat, 0, sizeof(axi_ax_beat_t)); + + ax_beat.ax_addr = addr; + ax_beat.ax_burst = AXI_BURST_INCR; + + // Determine size of each beat. + if (n_bytes > AXI_SW || (addr >> ((uint32_t)log2(AXI_SW))) != (addr + n_bytes - 1) >> ((uint32_t)log2(AXI_SW))) + { + // If the number of bytes exceeds the data bus width or the first byte is not on the same + // AXI line as the last byte, we have to write multiple beats. In this case, the burst must + // use the full data bus. + ax_beat.ax_size = log2(AXI_SW); + } + else + { + // If the number of bytes is less or equal to the data bus width, a single beat is + // sufficient. The size of the beat depends on the address, which determines the lower byte + // lane; all bytes must fit into the beat. + // The smallest possible value is the number of bytes to be transferred. + ax_beat.ax_size = log2(n_bytes); + // If the resulting upper byte lane is not high enough to accommodate all bytes, increment + // the size. + while (beat_upper_byte(ax_beat, 0, n_bytes) - beat_lower_byte(ax_beat, 0) < n_bytes) + { + assert(ax_beat.ax_size < log2(AXI_SW)); + ax_beat.ax_size++; + } + } + + // Calculate bytes per beat and total number of beats. + bytes_in_first_beat = AXI_SW - (addr % AXI_SW); + if (n_bytes <= bytes_in_first_beat) + { + bytes_in_first_beat = n_bytes; + n_beats = 1; + } + else + { + n_beats = 1 + ceil(((double)(n_bytes - bytes_in_first_beat)) / AXI_SW); + bytes_in_last_beat = n_bytes - bytes_in_first_beat - AXI_SW * (n_beats - 2); + } + + if (page_num(addr) != page_num(addr + n_bytes - 1)) + { + bytes_in_burst = 4096 - (addr & 0xFFF); + create_ax_beats(addr, bytes_in_burst, ax_beats); + } + else + { + beat_and_size_t bs; + bytes_in_burst = bytes_in_first_beat; + if (n_beats > 256) + { + n_beats = 256; + bytes_in_last_beat = AXI_SW; + } + if (n_beats > 1) + { + bytes_in_burst += (n_beats - 2) * AXI_SW + bytes_in_last_beat; + } + ax_beat.ax_len = n_beats - 1; + bs.beat = ax_beat; + bs.n_bytes = bytes_in_burst; + ax_beats.push(bs); + } + addr += bytes_in_burst; + n_bytes -= bytes_in_burst; + } + } + }; + +} // namespace PsPIN diff --git a/hw/verilator_model/src/AXIMaster.hpp b/hw/verilator_model/src/AXIMaster.hpp new file mode 100644 index 0000000..5a01554 --- /dev/null +++ b/hw/verilator_model/src/AXIMaster.hpp @@ -0,0 +1,492 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "AXIDriver.hpp" + +namespace PsPIN +{ + + template + class AXIMaster : public AXIDriver + { + using typename AXIDriver::axi_ax_beat_t; + using typename AXIDriver::axi_w_beat_t; + using typename AXIDriver::axi_b_queue_entry_t; + using typename AXIDriver::axi_r_queue_entry_t; + using typename AXIDriver::beat_and_size_t; + + typedef typename AXIPortType::axi_addr_t axi_addr_t; + + using AXIDriver::port; + using AXIDriver::create_ax_beats; + using AXIDriver::beat_lower_byte; + using AXIDriver::beat_upper_byte; + + private: + typedef struct axi_r_buffered + { + uint32_t data_length; + uint8_t data[AXI_SW]; + bool is_last; + } axi_r_buffered_t; + + private: + std::queue aw_queue; + std::queue w_queue; + std::queue r_queue; + + // a bit more high level. Takes into account that a write can be composed + // by multiple AW beats. Same for reads. + std::queue write_queue; + std::queue read_queue; + + + std::queue ar_queue; + std::queue b_queue; + + std::queue aw_pending_queue; + std::queue ar_pending_queue; + std::queue w_pending_queue; + + bool aw_wait; + bool ar_wait; + bool w_wait; + + uint32_t aw_beats_buffer_size; + uint32_t w_beats_buffer_size; + uint32_t b_beats_buffer_size; + uint32_t ar_beats_buffer_size; + uint32_t r_beats_buffer_size; + + public: + + bool has_aw_beat() + { + return !aw_pending_queue.empty(); + } + + bool can_send_aw_beat() + { + return aw_beats_buffer_size == 0 || aw_queue.size() < aw_beats_buffer_size; + } + + void send_aw_beat() + { + assert(!aw_pending_queue.empty() && can_send_aw_beat()); + axi_ax_beat_t &aw = aw_pending_queue.front(); + aw_queue.push(aw); + aw_pending_queue.pop(); + } + + bool has_ar_beat() + { + return !ar_pending_queue.empty(); + } + + bool can_send_ar_beat() + { + return ar_beats_buffer_size == 0 || ar_queue.size() < ar_beats_buffer_size; + } + + void send_ar_beat() + { + assert(!ar_pending_queue.empty() && can_send_ar_beat()); + axi_ax_beat_t &ar = ar_pending_queue.front(); + ar_queue.push(ar); + ar_pending_queue.pop(); + } + + bool has_w_beat() + { + return !w_pending_queue.empty(); + } + + bool can_send_w_beat() + { + return w_beats_buffer_size == 0 || w_queue.size() < w_beats_buffer_size; + } + + void send_w_beat() + { + assert(!w_pending_queue.empty() && can_send_w_beat()); + axi_w_beat_t &w = w_pending_queue.front(); + w_queue.push(w); + w_pending_queue.pop(); + } + + bool has_r_beat() + { + return !r_queue.empty(); + } + + bool consume_r_beat(uint8_t *data, uint32_t &data_length) + { + assert(has_r_beat()); + axi_r_buffered_t r = r_queue.front(); + data_length = std::min(data_length, r.data_length); + if (data!=NULL) { + memcpy(data, &(r.data[0]), data_length); + } + bool read_complete = r.is_last; + r_queue.pop(); + return read_complete; + } + + bool has_b_beat() + { + return !b_queue.empty(); + } + + bool consume_b_beat() + { + bool res = b_queue.front(); + b_queue.pop(); + return res; + } + + void set_aw_buffer(uint32_t aw_buffer_size) + { + aw_beats_buffer_size = aw_buffer_size; + } + + void set_ar_buffer(uint32_t ar_buffer_size) + { + ar_beats_buffer_size = ar_buffer_size; + } + + void set_w_buffer(uint32_t w_buffer_size) + { + w_beats_buffer_size = w_buffer_size; + } + + void set_r_buffer(uint32_t r_buffer_size) + { + r_beats_buffer_size = r_buffer_size; + } + + void set_b_buffer(uint32_t b_buffer_size) + { + b_beats_buffer_size = b_buffer_size; + } + + public: + AXIMaster(AXIPortType &port) : AXIDriver(port) + { + *port.aw_valid = 0; + *port.aw_valid = 0; + *port.w_valid = 0; + + *port.b_ready = 0; + *port.r_ready = 0; + + aw_wait = false; + ar_wait = false; + w_wait = false; + + aw_beats_buffer_size = 0; + ar_beats_buffer_size = 0; + w_beats_buffer_size = 0; + r_beats_buffer_size = 0; + b_beats_buffer_size = 0; + } + + void posedge() + { + aw_posedge(); + ar_posedge(); + w_posedge(); + b_posedge(); + r_posedge(); + } + + void negedge() + { + aw_negedge(); + ar_negedge(); + w_negedge(); + b_negedge(); + r_negedge(); + } + + public: /* interface */ + void write(axi_addr_t addr, uint8_t *data, uint32_t n_bytes, uint32_t offset) + { + // Create and send AW. + uint32_t bytes_written = 0; + axi_b_queue_entry_t write_queue_entry; + + std::queue aw_beats; + create_ax_beats(addr, n_bytes, aw_beats); + + write_queue_entry.n_bursts = aw_beats.size(); + write_queue.push(write_queue_entry); + + //printf("Write: #aw: %u\n", aw_beats.size()); + uint32_t aw_cnt = 0; + while (aw_beats.size() != 0) + { + uint32_t burst_bytes_written = 0; + beat_and_size_t bs = aw_beats.front(); + aw_beats.pop(); + axi_ax_beat_t aw_beat = bs.beat; + aw_pending_queue.push(aw_beat); + + aw_cnt++; + //printf("Write: #w (aw_cnt: %u): %u; bytes_written: %u\n", aw_cnt, aw_beat.ax_len, bytes_written); + + // Send W beats filled with data from the `data` array. + for (uint32_t i_beat = 0; i_beat <= aw_beat.ax_len; i_beat++) + { + uint32_t lower_byte = beat_lower_byte(aw_beat, i_beat); + uint32_t upper_byte = beat_upper_byte(aw_beat, i_beat, bs.n_bytes); + + axi_w_beat_t w_beat; + memset(&w_beat, 0, sizeof(axi_w_beat_t)); + + uint32_t beat_size = std::min(upper_byte - lower_byte, bs.n_bytes); + + //printf("lb: %u; ub: %u; ub-lb: %u; bs.n_bytes: %u\n", lower_byte, upper_byte, upper_byte - lower_byte, bs.n_bytes); + + memcpy(w_beat.w_data + lower_byte, data + offset + bytes_written + burst_bytes_written, beat_size); + + for (uint32_t i_byte = lower_byte; i_byte < upper_byte && burst_bytes_written < bs.n_bytes; i_byte++) + { + w_beat.w_strb = w_beat.w_strb | ((1ul << (AXI_SW-1)) >> (AXI_SW - i_byte - 1)); + //printf("%% i_byte: %u; w_strb: 0x%lx\n", i_byte, w_beat.w_strb); + } + if (i_beat == aw_beat.ax_len) + { + w_beat.w_last = 1; + } + + w_pending_queue.push(w_beat); + burst_bytes_written += beat_size; + } + bytes_written += burst_bytes_written; + } + if (bytes_written != n_bytes) + { + printf("ERROR: bytes_written: %u; n_bytes: %u\n", bytes_written, n_bytes); + assert(bytes_written == n_bytes); + } + } + + void read(axi_addr_t addr, uint32_t n_bytes) + { + axi_r_queue_entry_t read_queue_entry; + std::queue ar_beats; + + create_ax_beats(addr, n_bytes, ar_beats); + read_queue_entry.n_bursts = ar_beats.size(); + read_queue_entry.data_left = n_bytes; + read_queue.push(read_queue_entry); + + while (ar_beats.size() != 0) + { + beat_and_size_t &bs = ar_beats.front(); + ar_beats.pop(); + axi_ax_beat_t ar_beat = bs.beat; + ar_pending_queue.push(ar_beat); + } + } + + private: + void aw_posedge() + { + if (aw_wait) + { + return; + } + + *port.aw_valid = 0; + + if (aw_queue.empty()) + { + return; + } + + // send next AW beat + axi_ax_beat_t &aw_beat = aw_queue.front(); + + *port.aw_addr = aw_beat.ax_addr; + *port.aw_prot = aw_beat.ax_prot; + *port.aw_region = aw_beat.ax_region; + *port.aw_len = aw_beat.ax_len; + *port.aw_size = aw_beat.ax_size; + *port.aw_burst = aw_beat.ax_burst; + *port.aw_lock = aw_beat.ax_lock; + *port.aw_atop = aw_beat.ax_atop; + *port.aw_cache = aw_beat.ax_cache; + *port.aw_qos = aw_beat.ax_qos; + *port.aw_id = aw_beat.ax_id; + *port.aw_user = aw_beat.ax_user; + + *port.aw_valid = 1; + aw_queue.pop(); + } + + void aw_negedge() + { + //AW_READY can be function of AW_VALID, so let's see if we have it set already + aw_wait = false; + if (*port.aw_valid && !(*port.aw_ready)) + { + aw_wait = true; + } + } + + void ar_posedge() + { + if (ar_wait) + { + return; + } + + *port.ar_valid = 0; + + if (ar_queue.empty()) + { + return; + } + + // send next AR beat + axi_ax_beat_t &ar_beat = ar_queue.front(); + + *port.ar_addr = ar_beat.ax_addr; + *port.ar_prot = ar_beat.ax_prot; + *port.ar_region = ar_beat.ax_region; + *port.ar_len = ar_beat.ax_len; + *port.ar_size = ar_beat.ax_size; + *port.ar_burst = ar_beat.ax_burst; + *port.ar_lock = ar_beat.ax_lock; + *port.ar_cache = ar_beat.ax_cache; + *port.ar_qos = ar_beat.ax_qos; + *port.ar_id = ar_beat.ax_id; + *port.ar_user = ar_beat.ax_user; + + *port.ar_valid = 1; + ar_queue.pop(); + } + + void ar_negedge() + { + //AR_READY can be function of AR_VALID, so let's see if we have it set already + ar_wait = false; + if (*port.ar_valid && !(*port.ar_ready)) + { + ar_wait = true; + } + } + + void w_posedge() + { + if (w_wait) + { + return; + } + + *port.w_valid = 0; + *port.w_last = 0; + + if (w_queue.empty()) + { + return; + } + + // send next W beat + axi_w_beat_t &w_beat = w_queue.front(); + + //copy data + memcpy(port.w_data, w_beat.w_data, AXI_SW); + + *port.w_strb = w_beat.w_strb; + *port.w_user = w_beat.w_user; + *port.w_last = w_beat.w_last; + + *port.w_valid = 1; + w_queue.pop(); + } + + void w_negedge() + { + //AW_READY can be function of AW_VALID, so let's see if we have it set already + w_wait = false; + if (*port.w_valid && !(*port.w_ready)) + { + w_wait = true; + } + } + + void b_posedge() + { + bool can_accept_b = b_beats_buffer_size == 0 || b_queue.size() < b_beats_buffer_size; + + if (*port.b_valid && can_accept_b) + { + assert(!write_queue.empty()); + axi_b_queue_entry_t &entry = write_queue.front(); + + entry.n_bursts--; + bool is_complete = entry.n_bursts == 0; + + *port.b_ready = 1; + if (is_complete) { + write_queue.pop(); + } + + b_queue.push(is_complete); + } + } + + void b_negedge() + { + //nothing to do here + } + + void r_posedge() + { + bool can_accept_r = r_beats_buffer_size == 0 || r_queue.size() < r_beats_buffer_size; + + if (*port.r_valid && can_accept_r) + { + assert(!read_queue.empty()); + axi_r_queue_entry_t &entry = read_queue.front(); + + uint32_t data_size = std::min((uint32_t)AXI_SW, entry.data_left); + uint32_t completed_burst = (*port.r_last == 1) ? 1 : 0; + + *port.r_ready = 1; + + entry.n_bursts -= completed_burst; + entry.data_left -= data_size; + bool is_complete = entry.n_bursts == 0; + if (is_complete) read_queue.pop(); + + axi_r_buffered_t r_buff; + r_buff.data_length = data_size; + memcpy(r_buff.data, port.r_data, data_size); + r_buff.is_last = is_complete; + r_queue.push(r_buff); + } + } + + void r_negedge() + { + //nothing to do here + } + }; + +} // namespace PsPIN \ No newline at end of file diff --git a/hw/verilator_model/src/AXIPort.hpp b/hw/verilator_model/src/AXIPort.hpp new file mode 100644 index 0000000..7042997 --- /dev/null +++ b/hw/verilator_model/src/AXIPort.hpp @@ -0,0 +1,218 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include + +#define PASTER(x, y) x##_##y +#define EVALUATOR(x, y) PASTER(x, y) +#define NAME(fun) EVALUATOR(fun, VARIABLE) + +#define AXI_MASTER_PORT_ASSIGN(SRC, SRC_PREFIX, DST) \ + { \ + (DST)->aw_addr = &((SRC)->EVALUATOR(SRC_PREFIX, aw_addr_i)); \ + (DST)->aw_prot = &((SRC)->EVALUATOR(SRC_PREFIX, aw_prot_i)); \ + (DST)->aw_region = &((SRC)->EVALUATOR(SRC_PREFIX, aw_region_i)); \ + (DST)->aw_len = &((SRC)->EVALUATOR(SRC_PREFIX, aw_len_i)); \ + (DST)->aw_size = &((SRC)->EVALUATOR(SRC_PREFIX, aw_size_i)); \ + (DST)->aw_burst = &((SRC)->EVALUATOR(SRC_PREFIX, aw_burst_i)); \ + (DST)->aw_lock = &((SRC)->EVALUATOR(SRC_PREFIX, aw_lock_i)); \ + (DST)->aw_atop = &((SRC)->EVALUATOR(SRC_PREFIX, aw_atop_i)); \ + (DST)->aw_cache = &((SRC)->EVALUATOR(SRC_PREFIX, aw_cache_i)); \ + (DST)->aw_qos = &((SRC)->EVALUATOR(SRC_PREFIX, aw_qos_i)); \ + (DST)->aw_id = &((SRC)->EVALUATOR(SRC_PREFIX, aw_id_i)); \ + (DST)->aw_user = &((SRC)->EVALUATOR(SRC_PREFIX, aw_user_i)); \ + (DST)->aw_valid = &((SRC)->EVALUATOR(SRC_PREFIX, aw_valid_i)); \ + (DST)->aw_ready = &((SRC)->EVALUATOR(SRC_PREFIX, aw_ready_o)); \ + \ + (DST)->ar_addr = &((SRC)->EVALUATOR(SRC_PREFIX, ar_addr_i)); \ + (DST)->ar_prot = &((SRC)->EVALUATOR(SRC_PREFIX, ar_prot_i)); \ + (DST)->ar_region = &((SRC)->EVALUATOR(SRC_PREFIX, ar_region_i)); \ + (DST)->ar_len = &((SRC)->EVALUATOR(SRC_PREFIX, ar_len_i)); \ + (DST)->ar_size = &((SRC)->EVALUATOR(SRC_PREFIX, ar_size_i)); \ + (DST)->ar_burst = &((SRC)->EVALUATOR(SRC_PREFIX, ar_burst_i)); \ + (DST)->ar_lock = &((SRC)->EVALUATOR(SRC_PREFIX, ar_lock_i)); \ + (DST)->ar_cache = &((SRC)->EVALUATOR(SRC_PREFIX, ar_cache_i)); \ + (DST)->ar_qos = &((SRC)->EVALUATOR(SRC_PREFIX, ar_qos_i)); \ + (DST)->ar_id = &((SRC)->EVALUATOR(SRC_PREFIX, ar_id_i)); \ + (DST)->ar_user = &((SRC)->EVALUATOR(SRC_PREFIX, ar_user_i)); \ + (DST)->ar_valid = &((SRC)->EVALUATOR(SRC_PREFIX, ar_valid_i)); \ + (DST)->ar_ready = &((SRC)->EVALUATOR(SRC_PREFIX, ar_ready_o)); \ + \ + (DST)->w_data = (uint8_t *)&((SRC)->EVALUATOR(SRC_PREFIX, w_data_i)); \ + (DST)->w_strb = &((SRC)->EVALUATOR(SRC_PREFIX, w_strb_i)); \ + (DST)->w_user = &((SRC)->EVALUATOR(SRC_PREFIX, w_user_i)); \ + (DST)->w_last = &((SRC)->EVALUATOR(SRC_PREFIX, w_last_i)); \ + (DST)->w_valid = &((SRC)->EVALUATOR(SRC_PREFIX, w_valid_i)); \ + (DST)->w_ready = &((SRC)->EVALUATOR(SRC_PREFIX, w_ready_o)); \ + \ + (DST)->r_data = (uint8_t *)&((SRC)->EVALUATOR(SRC_PREFIX, r_data_o)); \ + (DST)->r_resp = &((SRC)->EVALUATOR(SRC_PREFIX, r_resp_o)); \ + (DST)->r_last = &((SRC)->EVALUATOR(SRC_PREFIX, r_last_o)); \ + (DST)->r_id = &((SRC)->EVALUATOR(SRC_PREFIX, r_id_o)); \ + (DST)->r_user = &((SRC)->EVALUATOR(SRC_PREFIX, r_user_o)); \ + (DST)->r_valid = &((SRC)->EVALUATOR(SRC_PREFIX, r_valid_o)); \ + (DST)->r_ready = &((SRC)->EVALUATOR(SRC_PREFIX, r_ready_i)); \ + \ + (DST)->b_resp = &((SRC)->EVALUATOR(SRC_PREFIX, b_resp_o)); \ + (DST)->b_id = &((SRC)->EVALUATOR(SRC_PREFIX, b_id_o)); \ + (DST)->b_user = &((SRC)->EVALUATOR(SRC_PREFIX, b_user_o)); \ + (DST)->b_valid = &((SRC)->EVALUATOR(SRC_PREFIX, b_valid_o)); \ + (DST)->b_ready = &((SRC)->EVALUATOR(SRC_PREFIX, b_ready_i)); \ + } + + +#define AXI_SLAVE_PORT_ASSIGN(SRC, SRC_PREFIX, DST) \ + { \ + (DST)->aw_addr = &((SRC)->EVALUATOR(SRC_PREFIX, aw_addr_o)); \ + (DST)->aw_prot = &((SRC)->EVALUATOR(SRC_PREFIX, aw_prot_o)); \ + (DST)->aw_region = &((SRC)->EVALUATOR(SRC_PREFIX, aw_region_o)); \ + (DST)->aw_len = &((SRC)->EVALUATOR(SRC_PREFIX, aw_len_o)); \ + (DST)->aw_size = &((SRC)->EVALUATOR(SRC_PREFIX, aw_size_o)); \ + (DST)->aw_burst = &((SRC)->EVALUATOR(SRC_PREFIX, aw_burst_o)); \ + (DST)->aw_lock = &((SRC)->EVALUATOR(SRC_PREFIX, aw_lock_o)); \ + (DST)->aw_atop = &((SRC)->EVALUATOR(SRC_PREFIX, aw_atop_o)); \ + (DST)->aw_cache = &((SRC)->EVALUATOR(SRC_PREFIX, aw_cache_o)); \ + (DST)->aw_qos = &((SRC)->EVALUATOR(SRC_PREFIX, aw_qos_o)); \ + (DST)->aw_id = &((SRC)->EVALUATOR(SRC_PREFIX, aw_id_o)); \ + (DST)->aw_user = &((SRC)->EVALUATOR(SRC_PREFIX, aw_user_o)); \ + (DST)->aw_valid = &((SRC)->EVALUATOR(SRC_PREFIX, aw_valid_o)); \ + (DST)->aw_ready = &((SRC)->EVALUATOR(SRC_PREFIX, aw_ready_i)); \ + \ + (DST)->ar_addr = &((SRC)->EVALUATOR(SRC_PREFIX, ar_addr_o)); \ + (DST)->ar_prot = &((SRC)->EVALUATOR(SRC_PREFIX, ar_prot_o)); \ + (DST)->ar_region = &((SRC)->EVALUATOR(SRC_PREFIX, ar_region_o)); \ + (DST)->ar_len = &((SRC)->EVALUATOR(SRC_PREFIX, ar_len_o)); \ + (DST)->ar_size = &((SRC)->EVALUATOR(SRC_PREFIX, ar_size_o)); \ + (DST)->ar_burst = &((SRC)->EVALUATOR(SRC_PREFIX, ar_burst_o)); \ + (DST)->ar_lock = &((SRC)->EVALUATOR(SRC_PREFIX, ar_lock_o)); \ + (DST)->ar_cache = &((SRC)->EVALUATOR(SRC_PREFIX, ar_cache_o)); \ + (DST)->ar_qos = &((SRC)->EVALUATOR(SRC_PREFIX, ar_qos_o)); \ + (DST)->ar_id = &((SRC)->EVALUATOR(SRC_PREFIX, ar_id_o)); \ + (DST)->ar_user = &((SRC)->EVALUATOR(SRC_PREFIX, ar_user_o)); \ + (DST)->ar_valid = &((SRC)->EVALUATOR(SRC_PREFIX, ar_valid_o)); \ + (DST)->ar_ready = &((SRC)->EVALUATOR(SRC_PREFIX, ar_ready_i)); \ + \ + (DST)->w_data = (uint8_t *)&((SRC)->EVALUATOR(SRC_PREFIX, w_data_o)); \ + (DST)->w_strb = &((SRC)->EVALUATOR(SRC_PREFIX, w_strb_o)); \ + (DST)->w_user = &((SRC)->EVALUATOR(SRC_PREFIX, w_user_o)); \ + (DST)->w_last = &((SRC)->EVALUATOR(SRC_PREFIX, w_last_o)); \ + (DST)->w_valid = &((SRC)->EVALUATOR(SRC_PREFIX, w_valid_o)); \ + (DST)->w_ready = &((SRC)->EVALUATOR(SRC_PREFIX, w_ready_i)); \ + \ + (DST)->r_data = (uint8_t *)&((SRC)->EVALUATOR(SRC_PREFIX, r_data_i)); \ + (DST)->r_resp = &((SRC)->EVALUATOR(SRC_PREFIX, r_resp_i)); \ + (DST)->r_last = &((SRC)->EVALUATOR(SRC_PREFIX, r_last_i)); \ + (DST)->r_id = &((SRC)->EVALUATOR(SRC_PREFIX, r_id_i)); \ + (DST)->r_user = &((SRC)->EVALUATOR(SRC_PREFIX, r_user_i)); \ + (DST)->r_valid = &((SRC)->EVALUATOR(SRC_PREFIX, r_valid_i)); \ + (DST)->r_ready = &((SRC)->EVALUATOR(SRC_PREFIX, r_ready_o)); \ + \ + (DST)->b_resp = &((SRC)->EVALUATOR(SRC_PREFIX, b_resp_i)); \ + (DST)->b_id = &((SRC)->EVALUATOR(SRC_PREFIX, b_id_i)); \ + (DST)->b_user = &((SRC)->EVALUATOR(SRC_PREFIX, b_user_i)); \ + (DST)->b_valid = &((SRC)->EVALUATOR(SRC_PREFIX, b_valid_i)); \ + (DST)->b_ready = &((SRC)->EVALUATOR(SRC_PREFIX, b_ready_o)); \ + } + +#define AXI_BURST_FIXED 0 +#define AXI_BURST_INCR 1 +#define AXI_BURST_WRAP 2 + +#define AXI_RESP_OKAY 0 +#define AXI_RESP_EXOKAY 1 +#define AXI_RESP_SLVERR 2 +#define AXI_RESP_DECERR 3 + +// data width +#define AXI_DW 512 + +// strobe width = number of bytes in beat +#define AXI_SW (AXI_DW / 8) + + +namespace PsPIN { + +template +class AXIPort +{ +public: + typedef AW_T axi_addr_t; + typedef STRB_T axi_strb_t; + typedef uint8_t axi_prot_t; + typedef uint8_t axi_region_t; + typedef uint8_t axi_len_t; + typedef uint8_t axi_size_t; + typedef uint8_t axi_burst_t; + typedef uint8_t axi_lock_t; + typedef uint8_t axi_atop_t; + typedef uint8_t axi_cache_t; + typedef uint8_t axi_qos_t; + typedef uint8_t axi_id_t; + typedef uint8_t axi_user_t; + +public: + axi_addr_t *aw_addr; + axi_prot_t *aw_prot; + axi_region_t *aw_region; + axi_len_t *aw_len; + axi_size_t *aw_size; + axi_burst_t *aw_burst; + axi_lock_t *aw_lock; + axi_atop_t *aw_atop; + axi_cache_t *aw_cache; + axi_qos_t *aw_qos; + axi_id_t *aw_id; + axi_user_t *aw_user; + uint8_t *aw_valid; + uint8_t *aw_ready; + + axi_addr_t *ar_addr; + axi_prot_t *ar_prot; + axi_region_t *ar_region; + axi_len_t *ar_len; + axi_size_t *ar_size; + axi_burst_t *ar_burst; + axi_lock_t *ar_lock; + axi_cache_t *ar_cache; + axi_qos_t *ar_qos; + axi_id_t *ar_id; + axi_user_t *ar_user; + uint8_t *ar_valid; + uint8_t *ar_ready; + + uint8_t *w_data; + axi_strb_t *w_strb; + axi_user_t *w_user; + uint8_t *w_last; + uint8_t *w_valid; + uint8_t *w_ready; + + uint8_t *r_data; + uint8_t *r_resp; + uint8_t *r_last; + axi_id_t *r_id; + axi_user_t *r_user; + uint8_t *r_valid; + uint8_t *r_ready; + + uint8_t *b_resp; + axi_id_t *b_id; + axi_user_t *b_user; + uint8_t *b_valid; + uint8_t *b_ready; +}; + +} \ No newline at end of file diff --git a/hw/verilator_model/src/AXISlave.hpp b/hw/verilator_model/src/AXISlave.hpp new file mode 100644 index 0000000..1d08dd8 --- /dev/null +++ b/hw/verilator_model/src/AXISlave.hpp @@ -0,0 +1,404 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "AXIDriver.hpp" + +namespace PsPIN +{ + + template + class AXISlave : public AXIDriver + { + using typename AXIDriver::axi_ax_beat_t; + using typename AXIDriver::axi_b_beat_t; + using typename AXIDriver::axi_r_beat_t; + using typename AXIDriver::axi_w_beat_t; + + using AXIDriver::port; + using AXIDriver::create_ax_beats; + using AXIDriver::beat_lower_byte; + using AXIDriver::beat_upper_byte; + + typedef typename AXIPortType::axi_addr_t axi_addr_t; + + public: + typedef struct r_beat_request + { + axi_addr_t addr; + uint32_t data_size; + axi_r_beat_t r_beat; + } r_beat_request_t; + + typedef struct w_beat_request + { + axi_addr_t addr; + uint32_t data_size; + axi_w_beat_t w_beat; + } w_beat_request_t; + + private: + uint32_t aw_beats_buffer_size; + uint32_t ar_beats_buffer_size; + uint32_t w_beats_buffer_size; + uint32_t r_beats_buffer_size; + uint32_t b_beats_buffer_size; + + std::queue aw_beats; + std::queue ar_beats; + std::queue b_beats; + std::queue r_beats; + + std::queue aw_pending_resp; + std::queue w_beat_requests; + + private: + bool r_wait; + bool b_wait; + + public: + AXISlave(AXIPortType &port) + : AXIDriver(port) + { + r_wait = 0; + b_wait = 0; + + *port.ar_ready = 0; + *port.aw_ready = 0; + *port.w_ready = 0; + *port.r_valid = 0; + *port.b_valid = 0; + + aw_beats_buffer_size = 0; + ar_beats_buffer_size = 0; + w_beats_buffer_size = 0; + r_beats_buffer_size = 0; + b_beats_buffer_size = 0; + } + + void set_aw_buffer(uint32_t aw_buffer_size) + { + aw_beats_buffer_size = aw_buffer_size; + } + + void set_ar_buffer(uint32_t ar_buffer_size) + { + ar_beats_buffer_size = ar_buffer_size; + } + + void set_w_buffer(uint32_t w_buffer_size) + { + w_beats_buffer_size = w_buffer_size; + } + + void set_r_buffer(uint32_t r_buffer_size) + { + r_beats_buffer_size = r_buffer_size; + } + + void set_b_buffer(uint32_t b_buffer_size) + { + b_beats_buffer_size = b_buffer_size; + } + + void posedge() + { + aw_posedge(); + ar_posedge(); + w_posedge(); + r_posedge(); + b_posedge(); + } + + void negedge() + { + aw_negedge(); + ar_negedge(); + w_negedge(); + r_negedge(); + b_negedge(); + } + + bool can_send_r_beat() + { + return r_beats_buffer_size == 0 || r_beats.size() < r_beats_buffer_size; + } + + void send_r_beat(axi_r_beat_t beat) + { + assert(can_send_r_beat()); + r_beats.push(beat); + } + + bool can_send_b_beat() + { + return b_beats_buffer_size == 0 || b_beats.size() < b_beats_buffer_size; + } + + void send_b_beat() + { + assert(!aw_pending_resp.empty()); + assert(can_send_b_beat()); + axi_ax_beat_t &aw = aw_pending_resp.front(); + + // prepare B beat + axi_b_beat_t b; + b.b_resp = AXI_RESP_OKAY; + b.b_id = aw.ax_id; + b.b_user = aw.ax_user; + b_beats.push(b); + + aw_pending_resp.pop(); + } + + bool has_w_beat() + { + return !w_beat_requests.empty(); + } + + w_beat_request_t get_next_w_beat() + { + assert(has_w_beat()); + w_beat_request_t w = w_beat_requests.front(); + w_beat_requests.pop(); + return w; + } + + bool has_r_beat() + { + return !ar_beats.empty(); + } + + r_beat_request_t get_next_r_beat() + { + assert(has_r_beat()); + + axi_ax_beat_t &ar = ar_beats.front(); + uint32_t data_size = pow(2, ar.ax_size); + + bool is_last = ar.ax_len == 0; + //printf("AXISlave AR beat ax_len: %u; is_last: %u\n", (uint32_t) ar.ax_len, (uint32_t) is_last); + r_beat_request_t req; + req.addr = ar.ax_addr; + req.data_size = data_size; + + req.r_beat.r_resp = AXI_RESP_OKAY; + req.r_beat.r_last = is_last; + req.r_beat.r_id = ar.ax_id; + req.r_beat.r_user = ar.ax_user; + + // AXI_BURST_WRAP is not implemented + assert(ar.ax_burst == AXI_BURST_FIXED || ar.ax_burst == AXI_BURST_INCR); + if (ar.ax_burst == AXI_BURST_INCR) + { + ar.ax_addr += data_size; + } + + //ax_len = n_beats + 1; + if (is_last) + { + ar_beats.pop(); + } + else + { + ar.ax_len--; + } + + return req; + } + + private: + void aw_posedge() + { + *port.aw_ready = 0; + + bool can_accept_aw = aw_beats_buffer_size == 0 || aw_beats.size() < aw_beats_buffer_size; + if (*port.aw_valid && can_accept_aw) + { + axi_ax_beat_t aw_beat; + + aw_beat.ax_addr = *port.aw_addr; + aw_beat.ax_atop = *port.aw_atop; + aw_beat.ax_burst = *port.aw_burst; + aw_beat.ax_cache = *port.aw_cache; + aw_beat.ax_id = *port.aw_id; + aw_beat.ax_len = *port.aw_len; + aw_beat.ax_lock = *port.aw_lock; + aw_beat.ax_prot = *port.aw_prot; + aw_beat.ax_qos = *port.aw_qos; + aw_beat.ax_region = *port.aw_region; + aw_beat.ax_size = *port.aw_size; + aw_beat.ax_user = *port.aw_user; + aw_beat.offset = 0; + + aw_beats.push(aw_beat); + + *port.aw_ready = 1; + } + } + + void aw_negedge() + { + // Nothing to do here + } + + void ar_posedge() + { + *port.ar_ready = 0; + + bool can_accept_ar = ar_beats_buffer_size == 0 || ar_beats.size() < ar_beats_buffer_size; + if (*port.ar_valid && can_accept_ar) + { + axi_ax_beat_t ar_beat; + + ar_beat.ax_addr = *port.ar_addr; + ar_beat.ax_burst = *port.ar_burst; + ar_beat.ax_cache = *port.ar_cache; + ar_beat.ax_id = *port.ar_id; + ar_beat.ax_len = *port.ar_len; + ar_beat.ax_lock = *port.ar_lock; + ar_beat.ax_prot = *port.ar_prot; + ar_beat.ax_qos = *port.ar_qos; + ar_beat.ax_region = *port.ar_region; + ar_beat.ax_size = *port.ar_size; + ar_beat.ax_user = *port.ar_user; + + ar_beat.offset = 0; + + ar_beats.push(ar_beat); + + *port.ar_ready = 1; + } + } + + void ar_negedge() + { + // Nothing to do here + } + + void w_posedge() + { + *port.w_ready = 0; + + bool can_accept_w = w_beats_buffer_size == 0 || w_beat_requests.size() < w_beats_buffer_size; + if (*port.w_valid && can_accept_w) + { + assert(!aw_beats.empty()); + axi_ax_beat_t &aw = aw_beats.front(); + unsigned int strb_low = (unsigned int) ((*port.w_strb)); + unsigned int strb_high = (unsigned int) ((*port.w_strb) >> 32); + uint32_t data_size = __builtin_popcount(strb_low) + __builtin_popcount(strb_high); + + w_beat_request_t req; + req.addr = aw.ax_addr + aw.offset; + req.data_size = data_size; + req.w_beat.w_strb = *port.w_strb; + req.w_beat.w_user = *port.w_user; + req.w_beat.w_last = *port.w_last; + + aw.offset += data_size; + + memcpy(req.w_beat.w_data, port.w_data, AXI_SW); + + w_beat_requests.push(req); + + if (*port.w_last == 1) + { + aw_pending_resp.push(aw); + aw_beats.pop(); + } + + *port.w_ready = 1; + } + } + + void w_negedge() + { + // Nothing to do here + } + + void r_posedge() + { + if (r_wait) + { + return; + } + + *port.r_valid = 0; + + if (r_beats.empty()) + { + return; + } + + axi_r_beat_t &r = r_beats.front(); + + + *port.r_resp = r.r_resp; + *port.r_last = r.r_last; + *port.r_id = r.r_id; + *port.r_user = r.r_user; + memcpy(port.r_data, r.r_data, AXI_SW); + + *port.r_valid = 1; + r_beats.pop(); + } + + void r_negedge() + { + //R_READY can be function of R_VALID, so let's see if we have it set already + r_wait = false; + if (*port.r_valid && !(*port.r_ready)) + { + r_wait = true; + } + } + + void b_posedge() + { + if (b_wait) + { + return; + } + + *port.b_valid = 0; + + if (b_beats.empty()) + { + return; + } + + axi_b_beat_t &b = b_beats.front(); + + *port.b_resp = b.b_resp; + *port.b_id = b.b_id; + *port.b_user = b.b_user; + b_beats.pop(); + + *port.b_valid = 1; + } + + void b_negedge() + { + //B_READY can be function of B_VALID, so let's see if we have it set already + b_wait = false; + if (*port.b_valid && !(*port.b_ready)) + { + b_wait = true; + } + } + }; + +} // namespace PsPIN \ No newline at end of file diff --git a/hw/verilator_model/src/NICInbound.hpp b/hw/verilator_model/src/NICInbound.hpp new file mode 100644 index 0000000..c88aa06 --- /dev/null +++ b/hw/verilator_model/src/NICInbound.hpp @@ -0,0 +1,549 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "AXIPort.hpp" +#include "Vpspin_verilator.h" +#include "verilated.h" +#include "SimModule.hpp" +#include "AXIMaster.hpp" +#include "pspin.hpp" +#include "spin.h" +#include "pspinsim.h" + +#include +#include +#include +#include + +#define NI_PKT_ADDR_ALIGNMENT 64 + +namespace PsPIN +{ + + template + class NICInbound : public SimModule + { + typedef typename AXIPortType::axi_addr_t axi_addr_t; + + typedef struct incoming_her + { + her_descr_t her; + std::vector pkt_data; + size_t pkt_len; + uint32_t wait_cycles; + } incoming_her_t; + + public: + ni_control_port_t &ni_ctrl; + + public: + typedef std::function pkt_feedback_cb_t; + + private: + AXIMaster axi_driver; + axi_addr_t l2_pkt_buff_start; + uint32_t l2_pkt_buff_size; + uint32_t hers_to_send; + + //HERs that are coming from the network (virtual delay applied) + std::queue incoming_hers; + + //HERs that have been read and for which a DMA write is in flight + std::queue queued_hers; + + //HERs that are ready to be sent to PsPIN (DMA completed) + std::queue ready_hers; + + uint32_t packet_wait_cycles; + + FILE *pkt_file; + FILE *data_file; + uint64_t head_ptr, tail_ptr, cut_ptr; + bool cut; + uint32_t in_flight_packets; + std::unordered_map free_req_queue; + + bool her_cmd_wait; + + bool app_sent_eos; + + pkt_feedback_cb_t feedback_cb; + + //Statistics + private: + typedef struct pktentry + { + uint64_t nic_arrival_time; + uint64_t pspin_arrival_time; + uint32_t size; + uint64_t user_ptr; + } pktentry_t; + + uint32_t total_bytes_sent; + uint32_t total_pkts; + + uint64_t time_last_feedback; + uint64_t time_first_feedback; + uint32_t total_feedbacks; + uint32_t ni_ctrl_stalls; + + uint32_t sum_pkt_latency; + uint32_t min_pkt_latency; + uint32_t max_pkt_latency; + + std::unordered_map pktmap; + + public: + NICInbound(AXIPortType &ni_mst, ni_control_port_t &ni_ctrl, axi_addr_t l2_pkt_buff_start, uint32_t l2_pkt_buff_size) + : axi_driver(ni_mst), ni_ctrl(ni_ctrl), l2_pkt_buff_start(l2_pkt_buff_start), l2_pkt_buff_size(l2_pkt_buff_size) + { + *ni_ctrl.her_valid_o = 0; + *ni_ctrl.eos_o = 0; + + // Accept feedbacks + *ni_ctrl.feedback_ready_o = 1; + + packet_wait_cycles = 0; + + pkt_file = NULL; + data_file = NULL; + + app_sent_eos = false; + + head_ptr = 0; + tail_ptr = 0; + cut_ptr = 0; + cut = false; + in_flight_packets = 0; + + //printf("sizeof(her_descr_t): %lu\n", sizeof(her_descr_t)); + + total_bytes_sent = 0; + total_pkts = 0; + time_last_feedback = 0; + time_first_feedback = 0; + total_feedbacks = 0; + sum_pkt_latency = 0; + min_pkt_latency = 0; + max_pkt_latency = 0; + ni_ctrl_stalls = 0; + + hers_to_send = 0; + + her_cmd_wait = false; + } + + ~NICInbound() + { + if (data_file != NULL) + fclose(data_file); + if (pkt_file != NULL) + fclose(pkt_file); + } + + void set_feedback_cb(pkt_feedback_cb_t cb) + { + this->feedback_cb = cb; + } + + void set_eos() + { + app_sent_eos = true; + } + + int add_packet(her_descr_t &her, uint8_t *pkt_data, size_t pkt_len, uint32_t wait_cycles) + { + incoming_her_t ih; + ih.her = her; + ih.pkt_data.resize(pkt_len); + memcpy(&(ih.pkt_data[0]), pkt_data, pkt_len); + ih.pkt_len = pkt_len; + ih.wait_cycles = wait_cycles; + + incoming_hers.push(ih); + hers_to_send++; + + return SPIN_SUCCESS; + } + + int read_trace(const char *pkt_filename, const char *data_filename) + { + // Note: this can be optimized if the packet trace becomes too big + FILE *pkt_file = fopen(pkt_filename, "r"); + if (pkt_file == NULL) + { + printf("Task file not found!\n"); + return SPIN_ERR; + } + + FILE *data_file = fopen(data_filename, "rb"); + if (data_file == NULL) + { + printf("Data file not found!\n"); + return SPIN_ERR; + } + + while (!feof(pkt_file)) + { + uint32_t msgid, hh_addr, hh_size, ph_addr, ph_size, th_addr, th_size, hmem_addr, hmem_size, pkt_size, pkt_xfer_size, eom, wait_cycles; + int code = fscanf(pkt_file, "%u,%u,%u,%u,%u,%u,%u,%u,%u,%u,%u,%u,%u\n", &msgid, &hh_addr, &hh_size, &ph_addr, &ph_size, &th_addr, &th_size, &hmem_addr, &hmem_size, &pkt_size, &pkt_xfer_size, &eom, &wait_cycles); + assert(code == 13); + + uint8_t *pkt_data = new uint8_t[pkt_size]; + code = fread(&(pkt_data[0]), sizeof(uint8_t), pkt_size, data_file); + assert(code == pkt_size); + + her_descr_t her_descr; + + // prepare handler execution request (HER) + her_descr.mpq_meta.hh_addr = hh_addr; + her_descr.mpq_meta.hh_size = hh_size; + + her_descr.mpq_meta.ph_addr = ph_addr; + her_descr.mpq_meta.ph_size = ph_size; + + her_descr.mpq_meta.th_addr = th_addr; + her_descr.mpq_meta.th_size = th_size; + + her_descr.mpq_meta.handler_mem_addr = hmem_addr; + her_descr.mpq_meta.handler_mem_size = hmem_size; + + her_descr.mpq_meta.host_mem_addr = PCIE_START_ADDR; + her_descr.mpq_meta.host_mem_size = 0x40000000; + + for (int i = 0; i < NUM_CLUSTERS; i++) + { + her_descr.mpq_meta.scratchpad_addr[i] = 0; + her_descr.mpq_meta.scratchpad_size[i] = L1_SCRATCHPAD_SIZE; + } + + her_descr.msgid = msgid; + her_descr.her_addr = 0x0; //will be set later + her_descr.her_size = pkt_size; + her_descr.xfer_size = pkt_xfer_size; + her_descr.eom = (eom == 1); + + add_packet(her_descr, pkt_data, pkt_size, wait_cycles); + } + fclose(data_file); + fclose(pkt_file); + + return SPIN_SUCCESS; + } + + bool allocate_pkt_space(uint32_t pkt_size, axi_addr_t *addr) + { + bool can_allocate = false; + + uint32_t segments = (pkt_size + NI_PKT_ADDR_ALIGNMENT - 1) / NI_PKT_ADDR_ALIGNMENT; + pkt_size = segments * NI_PKT_ADDR_ALIGNMENT; + + if (tail_ptr > head_ptr || (tail_ptr == head_ptr && in_flight_packets == 0)) + { + if (l2_pkt_buff_size - tail_ptr >= pkt_size) + { + can_allocate = true; + } + else if (head_ptr >= pkt_size) + { + cut_ptr = tail_ptr; + cut = true; + tail_ptr = 0; + can_allocate = true; + } + } + else if (head_ptr > tail_ptr) + { + if (head_ptr - tail_ptr >= pkt_size) + { + can_allocate = true; + } + } + + if (can_allocate) + { + *addr = l2_pkt_buff_start + tail_ptr; + tail_ptr += pkt_size; + in_flight_packets++; + SIM_PRINT("NIC inbound engine: allocated %u bytes; head_ptr: %lu; tail_ptr: %lu; in_flight_packets: %lu\n", pkt_size, head_ptr, tail_ptr, in_flight_packets); + } + else{ + SIM_PRINT("NIC inbound engine: allocation failed! bytes: %u; head_ptr: %lu; tail_ptr: %lu; in_flight_packets: %lu\n", pkt_size, head_ptr, tail_ptr, in_flight_packets); + } + + return can_allocate; + } + + void free_pkt_space(axi_addr_t addr, uint32_t size) + { + uint32_t offset = addr - l2_pkt_buff_start; + assert(addr >= l2_pkt_buff_start); + + uint32_t segments = (size + NI_PKT_ADDR_ALIGNMENT - 1) / NI_PKT_ADDR_ALIGNMENT; + size = segments * NI_PKT_ADDR_ALIGNMENT; + + assert(free_req_queue.find(offset) == free_req_queue.end()); + free_req_queue[offset] = size; + + while (!free_req_queue.empty() && free_req_queue.find(head_ptr) != free_req_queue.end()) + { + uint32_t head_ptr_increase = free_req_queue[head_ptr]; + free_req_queue.erase(head_ptr); + + head_ptr += head_ptr_increase; + in_flight_packets--; + SIM_PRINT("NIC inbound engine: freeing %u bytes; head_ptr: %lu; tail_ptr: %lu; in_flight_packets: %lu; cut: %u; cut_ptr: %lu\n", head_ptr_increase, head_ptr, tail_ptr, in_flight_packets, (uint32_t) cut, cut_ptr); + + if (cut && head_ptr == cut_ptr) + { + head_ptr = 0; + cut = false; + SIM_PRINT("NIC inbound engine: resetting head_ptr! cut_ptr: %lu;\n", cut_ptr); + } + } + } + + bool process_packet(her_descr_t &her_descr, uint8_t *pkt_data, uint32_t pkt_size) + { + axi_addr_t pkt_addr; + if (!allocate_pkt_space(pkt_size, &pkt_addr)) + { + return false; + } + + axi_driver.write(pkt_addr, pkt_data, pkt_size, 0); + + her_descr.her_addr = pkt_addr; + her_descr.nic_arrival_time = sim_time(); + + queued_hers.push(her_descr); + + return true; + } + + void progress_incoming_packets() + { + if (incoming_hers.empty()) + return; + + if (packet_wait_cycles > 0) + { + packet_wait_cycles--; + if (packet_wait_cycles > 0) + return; + } + + incoming_her_t &ih = incoming_hers.front(); + + if (process_packet(ih.her, &(ih.pkt_data[0]), ih.pkt_len)) + { + // we won't serve the next packet before wait_cycles; + packet_wait_cycles = ih.wait_cycles; + + incoming_hers.pop(); + } + else + { + //the packet is here and we cannot push it to PsPIN because of no space in L2; + //still spending "wait" cycles. + ih.wait_cycles = (ih.wait_cycles > 0) ? ih.wait_cycles-- : 0; + } + } + + void posedge() + { + if (*ni_ctrl.pspin_active_i) + { + progress_axi_writes(); + axi_driver.posedge(); + progress_axi_write_responses(); + progress_incoming_packets(); + her_progress_posedge(); + feedback_progress(); + } + } + + void negedge() + { + axi_driver.negedge(); + her_progress_negedge(); + } + + private: + // Progress HERs + void her_progress_posedge() + { + if (her_cmd_wait) + { + ni_ctrl_stalls++; + return; + } + + *ni_ctrl.her_valid_o = 0; + + if (ready_hers.empty()) + { + return; + } + + her_descr_t her = ready_hers.front(); + + *ni_ctrl.her_o.msgid = her.msgid; + *ni_ctrl.her_o.eom = her.eom; + *ni_ctrl.her_o.her_addr = her.her_addr; + *ni_ctrl.her_o.her_size = her.her_size; + *ni_ctrl.her_o.xfer_size = her.xfer_size; + *ni_ctrl.her_o.mpq_meta.handler_mem_addr = her.mpq_meta.handler_mem_addr; + *ni_ctrl.her_o.mpq_meta.handler_mem_size = her.mpq_meta.handler_mem_size; + *ni_ctrl.her_o.mpq_meta.host_mem_addr = her.mpq_meta.host_mem_addr; + *ni_ctrl.her_o.mpq_meta.host_mem_size = her.mpq_meta.host_mem_size; + *ni_ctrl.her_o.mpq_meta.hh_addr = her.mpq_meta.hh_addr; + *ni_ctrl.her_o.mpq_meta.hh_size = her.mpq_meta.hh_size; + *ni_ctrl.her_o.mpq_meta.ph_addr = her.mpq_meta.ph_addr; + *ni_ctrl.her_o.mpq_meta.ph_size = her.mpq_meta.ph_size; + *ni_ctrl.her_o.mpq_meta.th_addr = her.mpq_meta.th_addr; + *ni_ctrl.her_o.mpq_meta.th_size = her.mpq_meta.th_size; + *ni_ctrl.her_o.mpq_meta.scratchpad_addr[0] = her.mpq_meta.scratchpad_addr[0]; + *ni_ctrl.her_o.mpq_meta.scratchpad_addr[1] = her.mpq_meta.scratchpad_addr[1]; + *ni_ctrl.her_o.mpq_meta.scratchpad_addr[2] = her.mpq_meta.scratchpad_addr[2]; + *ni_ctrl.her_o.mpq_meta.scratchpad_addr[3] = her.mpq_meta.scratchpad_addr[3]; + *ni_ctrl.her_o.mpq_meta.scratchpad_size[0] = her.mpq_meta.scratchpad_size[0]; + *ni_ctrl.her_o.mpq_meta.scratchpad_size[1] = her.mpq_meta.scratchpad_size[1]; + *ni_ctrl.her_o.mpq_meta.scratchpad_size[2] = her.mpq_meta.scratchpad_size[2]; + *ni_ctrl.her_o.mpq_meta.scratchpad_size[3] = her.mpq_meta.scratchpad_size[3]; + + *ni_ctrl.her_valid_o = 1; + + hers_to_send--; + + ready_hers.pop(); + + SIM_PRINT("HER sent (0x%x)\n", *ni_ctrl.her_o.her_addr); + + pktentry_t pktentry; + pktentry.pspin_arrival_time = sim_time(); + pktentry.nic_arrival_time = her.nic_arrival_time; + pktentry.size = her.her_size; + pktentry.user_ptr = her.user_ptr; + + assert(pktmap.find(*ni_ctrl.her_o.her_addr) == pktmap.end()); + pktmap[*ni_ctrl.her_o.her_addr] = pktentry; + + //stats + total_bytes_sent += her.her_size; + total_pkts++; + + if (hers_to_send == 0 && app_sent_eos) + { + *ni_ctrl.eos_o = 1; + } + } + + void her_progress_negedge() + { + her_cmd_wait = false; + if (*ni_ctrl.her_valid_o && !(*ni_ctrl.her_ready_i)) + { + her_cmd_wait = true; + } + } + + // Get feedback + void feedback_progress() + { + if (*ni_ctrl.feedback_ready_o && *ni_ctrl.feedback_valid_i) + { + assert(pktmap.find(*ni_ctrl.feedback_her_addr_i) != pktmap.end()); + pktentry_t pktentry = pktmap[*ni_ctrl.feedback_her_addr_i]; + uint32_t latency = sim_time() - pktentry.nic_arrival_time; + + SIM_PRINT("INFO FEEDBACK 0x%x %u %u\n", *ni_ctrl.feedback_her_addr_i, latency, pktentry.size); + + assert(*ni_ctrl.feedback_her_size_i == pktentry.size); + free_pkt_space(*ni_ctrl.feedback_her_addr_i, *ni_ctrl.feedback_her_size_i); + + sum_pkt_latency += latency; + + if (feedback_cb) + feedback_cb(pktentry.user_ptr, pktentry.nic_arrival_time, pktentry.pspin_arrival_time, sim_time()); + + pktmap.erase(*ni_ctrl.feedback_her_addr_i); + + if (total_feedbacks == 0) + { + time_first_feedback = sim_time(); + min_pkt_latency = latency; + max_pkt_latency = latency; + } + else + { + min_pkt_latency = std::min(min_pkt_latency, latency); + max_pkt_latency = std::max(max_pkt_latency, latency); + } + + time_last_feedback = sim_time(); + + total_feedbacks++; + } + } + + void progress_axi_writes() + { + if (axi_driver.has_aw_beat() && axi_driver.can_send_aw_beat()) + { + axi_driver.send_aw_beat(); + } + + if (axi_driver.has_w_beat() && axi_driver.can_send_w_beat()) + { + axi_driver.send_w_beat(); + } + } + + void progress_axi_write_responses() + { + if (!axi_driver.has_b_beat()) + return; + + bool write_completed = axi_driver.consume_b_beat(); + + if (write_completed) + { + assert(!queued_hers.empty()); + her_descr_t her = queued_hers.front(); + queued_hers.pop(); + ready_hers.push(her); + } + } + + public: + void print_stats() + { + double avg_pkt_length = ((double)total_bytes_sent) / total_pkts; + double avg_intra_feedback = ((double)(time_last_feedback - time_first_feedback)) / (1000 * (total_feedbacks - 1)); + double avg_feedback_throughput = THROUGHPUT_1GHZ(avg_intra_feedback, avg_pkt_length); + double avg_pkt_latency = ((double)sum_pkt_latency) / (1000 * total_pkts); + + printf("NIC inbound engine:\n"); + printf("\tPackets: %d; Bytes: %d\n", total_pkts, total_bytes_sent); + printf("\tAvg packet length: %.3lf B\n", avg_pkt_length); + printf("\tFeedback throughput: %.3lf Gbit/s (feedback arrival time: %.3lf ns)\n", avg_feedback_throughput, avg_intra_feedback); + printf("\tPacket latency: avg: %.3lf ns; min: %d ns; max: %d ns\n", avg_pkt_latency, min_pkt_latency / 1000, max_pkt_latency / 1000); + printf("\tHER stalls: %d\n", ni_ctrl_stalls); + } + }; + +} // namespace PsPIN diff --git a/hw/verilator_model/src/NICOutbound.hpp b/hw/verilator_model/src/NICOutbound.hpp new file mode 100644 index 0000000..af31d30 --- /dev/null +++ b/hw/verilator_model/src/NICOutbound.hpp @@ -0,0 +1,325 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "AXIPort.hpp" +#include "Vpspin_verilator.h" +#include "verilated.h" +#include "SimModule.hpp" +#include "AXIMaster.hpp" +#include "pspin.hpp" + +#include +#include + +#define RDMA_HEADER_LENGTH 32 +#define NUM_PARALLEL_CMD 16 + +// The network delay is computed by slicing the packet in words +// and applying G to the number of segments. This is to +#define WORD_SIZE 64 + +namespace PsPIN +{ + template + class NICOutbound : public SimModule + { + + private: + class NetworkPacket + { + public: + uint64_t source_addr; + uint32_t current_offset; + uint32_t length; + uint32_t payload_length; + uint8_t cmd_id; + bool is_last; + std::vector data; + + NetworkPacket(uint32_t length) : length(length) + { + current_offset = 0; + data.resize(length); + } + }; + + class NICCommand + { + public: + uint64_t source_addr; + uint32_t length; + uint32_t nid; + uint32_t fid; + uint8_t cmd_id; + }; + + class Packetizer + { + private: + uint32_t num_parallel_cmds; + uint32_t max_packet_len; + std::queue commands; + + public: + Packetizer(uint32_t num_parallel_cmds, uint32_t max_packet_len) : num_parallel_cmds(num_parallel_cmds), max_packet_len(max_packet_len) + { + ; + } + + bool has_free_cmd_slot() + { + return commands.size() < num_parallel_cmds; + } + + bool has_packets() + { + return commands.size() > 0; + } + + void new_cmd(NICCommand cmd) + { + assert(commands.size() < num_parallel_cmds); + commands.push(cmd); + } + + NetworkPacket get_next_packet() + { + assert(!commands.empty()); + NICCommand cmd = commands.front(); + commands.pop(); + + uint32_t header_length = 0; + if (cmd.fid>0) { /* RDMA (can be multi packet) */ + header_length = RDMA_HEADER_LENGTH; + } else { /* single packet */ + assert(cmd.length <= max_packet_len); + } + + uint32_t payloadlen = std::min(max_packet_len - header_length, cmd.length); + uint32_t pktlen = header_length + payloadlen; + + NetworkPacket pkt(pktlen); + + pkt.cmd_id = cmd.cmd_id; + pkt.is_last = cmd.length - payloadlen == 0; + pkt.length = pktlen; + pkt.payload_length = payloadlen; + pkt.source_addr = cmd.source_addr; + + cmd.length -= payloadlen; + cmd.source_addr += payloadlen; + + //printf("generating packet: length: %d; payload: %d; new cmd length: %d; next pkt addr: 0x%lx\n", pktlen, payloadlen, cmd.length, cmd.source_addr); + + if (cmd.length>0){ + commands.push(cmd); + } + + return pkt; + } + }; + + public: + typedef std::function out_packet_cb_t; + + private: + AXIMaster axi_driver; + no_cmd_port &no_cmd; + double network_G; //ns + uint32_t max_pkt_length; + uint32_t network_buffer_size; + + uint32_t wait_cycles; + + std::queue network_queue; + + std::queue dma_pkt_in_flight; + + Packetizer packetizer; + + public: + out_packet_cb_t pktout_cb; + + //statistics + private: + uint32_t total_cmds; + uint32_t total_pkts; + uint32_t total_bytes; + uint64_t time_first_pkt; + uint64_t time_last_pkt; + + public: + NICOutbound(AXIPortType &no_mst, no_cmd_port_t &no_cmd, double network_G, uint32_t max_pkt_length, uint32_t network_buffer_size) + : axi_driver(no_mst), no_cmd(no_cmd), network_G(network_G), max_pkt_length(max_pkt_length), network_buffer_size(network_buffer_size), packetizer(NUM_PARALLEL_CMD, max_pkt_length) + { + *no_cmd.no_cmd_resp_valid_o = 0; + *no_cmd.no_cmd_req_ready_o = 0; + + wait_cycles = 0; + + total_cmds = 0; + total_pkts = 0; + total_bytes = 0; + time_first_pkt = 0; + time_last_pkt = 0; + } + + void posedge() + { + progress_axi_reads(); + axi_driver.posedge(); + progress_axi_read_responses(); + progress_netqueue(); + handle_cmd_posedge(); + progress_packets(); + } + + void negedge() + { + axi_driver.negedge(); + } + + void set_packet_out_cb(out_packet_cb_t cb) + { + this->pktout_cb = cb; + } + + private: + void handle_cmd_posedge() + { + *no_cmd.no_cmd_req_ready_o = 0; + + bool can_accept_cmd = packetizer.has_free_cmd_slot(); + + if (*no_cmd.no_cmd_req_valid_i && can_accept_cmd) + { + + NICCommand cmd; + cmd.source_addr = *no_cmd.no_cmd_req_src_addr_i; + cmd.length = *no_cmd.no_cmd_req_length_i; + cmd.nid = *no_cmd.no_cmd_req_nid_i; + cmd.fid = *no_cmd.no_cmd_req_fid_i; + cmd.cmd_id = *no_cmd.no_cmd_req_id_i; + + assert(cmd.fid>0 || cmd.length <= max_pkt_length); + + SIM_PRINT("NIC outbound got new command: source_addr: 0x%lx; length: %d; FID: %d (>0 is RDMA)\n", cmd.source_addr, cmd.length, cmd.fid); + total_cmds++; + + packetizer.new_cmd(cmd); + + *no_cmd.no_cmd_req_ready_o = 1; + } + } + + void progress_packets() + { + bool can_send_pkt = network_queue.size() + dma_pkt_in_flight.size() < network_buffer_size; + if (packetizer.has_packets() && can_send_pkt) + { + NetworkPacket pkt = packetizer.get_next_packet(); + axi_driver.read(pkt.source_addr, pkt.payload_length); + dma_pkt_in_flight.push(pkt); + } + } + + void progress_netqueue() + { + *no_cmd.no_cmd_resp_valid_o = 0; + + if (wait_cycles > 0) + { + wait_cycles--; + if (wait_cycles > 0) return; + } + + if (!network_queue.empty()) + { + NetworkPacket &pkt = network_queue.front(); + + wait_cycles = ((uint32_t)(network_G * WORD_SIZE)) * std::floor((double) pkt.length / WORD_SIZE); + + if (pkt.is_last) + { + *no_cmd.no_cmd_resp_valid_o = 1; + *no_cmd.no_cmd_resp_id_o = pkt.cmd_id; + } + + // TODO: packet is ready. This is the point where we can do something with it. + + if (pktout_cb) pktout_cb((uint8_t*) &(pkt.data[0]), pkt.length); + + SIM_PRINT("packet sent; size: %d; wait_cycles: %d (G: %lf); is_last: %d\n", pkt.length, wait_cycles, network_G, (uint32_t) pkt.is_last); + + if (total_pkts==0) time_first_pkt = sim_time(); + time_last_pkt = sim_time(); + total_pkts++; + total_bytes += pkt.length; + + network_queue.pop(); + + } + } + + void progress_axi_reads() + { + if (axi_driver.has_ar_beat() && axi_driver.can_send_ar_beat()) + { + axi_driver.send_ar_beat(); + } + } + + void progress_axi_read_responses() + { + + if (axi_driver.has_r_beat()) + { + bool read_complete; + uint32_t length = AXI_SW; + + assert(!dma_pkt_in_flight.empty()); + NetworkPacket &pkt = dma_pkt_in_flight.front(); + + uint8_t *dest_ptr = ((uint8_t *)&(pkt.data[0])) + pkt.current_offset; + read_complete = axi_driver.consume_r_beat(dest_ptr, length); + + pkt.current_offset += length; + + if (read_complete) + { + //printf("pkt.current_offset: %d; pkt.length: %d\n", pkt.current_offset, pkt.length); + assert(pkt.current_offset == pkt.payload_length); + network_queue.push(pkt); + dma_pkt_in_flight.pop(); + } + } + } + + public: + void print_stats() + { + double avg_pkt_length = ((double) total_bytes) / total_pkts; + double avg_intra_pkt = ((double) (time_last_pkt - time_first_pkt)) / (1000*(total_pkts-1)); + double avg_pkt_throughput = THROUGHPUT_1GHZ(avg_intra_pkt, avg_pkt_length); + + printf("NIC outbound engine:\n"); + printf("\tCommands: %d; Packets: %d; Bytes: %d\n", total_cmds, total_pkts, total_bytes); + printf("\tAvg packet length: %.3lf B\n", avg_pkt_length); + printf("\tPacket throughput: %.3lf Gbit/s (pkt departure time: %.3lf ns)\n", avg_pkt_throughput, avg_intra_pkt); + } + }; + +} // namespace PsPIN \ No newline at end of file diff --git a/hw/verilator_model/src/PCIe.hpp b/hw/verilator_model/src/PCIe.hpp new file mode 100644 index 0000000..d940e24 --- /dev/null +++ b/hw/verilator_model/src/PCIe.hpp @@ -0,0 +1,251 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "AXIPort.hpp" +#include "Vpspin_verilator.h" +#include "verilated.h" +#include "SimModule.hpp" +#include "AXIMaster.hpp" +#include "AXISlave.hpp" +#include "pspin.hpp" + +#include +#include + +namespace PsPIN +{ + using std::placeholders::_1; + + template + class PCIe : public SimModule + { + + typedef typename AXISlave::w_beat_request_t w_beat_request_t; + typedef typename AXISlave::r_beat_request_t r_beat_request_t; + + private: + typedef struct pcie_write + { + w_beat_request_t req; + uint64_t time; + } pcie_write_t; + + typedef struct pcie_read + { + r_beat_request_t req; + uint64_t time; + } pcie_read_t; + + private: + AXIMaster axi_driver_mst; + AXISlave axi_driver_slv; + + uint32_t pcie_L; + double pcie_G; + + uint32_t write_wait_cycles; + uint32_t read_wait_cycles; + + std::queue in_flight_write_requests; + std::queue in_flight_read_requests; + + public: + typedef std::function slv_write_cb_t; + typedef std::function slv_read_cb_t; + + // Statistics + private: + uint32_t bytes_written; + uint32_t bytes_read; + uint64_t time_first_read; + uint64_t time_last_write; + uint64_t time_first_write; + uint64_t time_last_read; + uint32_t num_reads; + uint32_t num_writes; + + slv_write_cb_t slv_write_cb; + slv_read_cb_t slv_read_cb; + + public: + PCIe(AXIMstPortType &axi_mst, AXISlvPortType &axi_slv, uint32_t aw_buffer_size, uint32_t w_buffer_size, uint32_t ar_buffer_size, uint32_t r_buffer_size, uint32_t b_buffer_size, uint32_t pcie_L, uint32_t pcie_G) + : axi_driver_mst(axi_mst), axi_driver_slv(axi_slv), pcie_L(pcie_L), pcie_G(pcie_G) + { + write_wait_cycles = 0; + read_wait_cycles = 0; + + axi_driver_slv.set_ar_buffer(ar_buffer_size); + axi_driver_slv.set_aw_buffer(aw_buffer_size); + axi_driver_slv.set_w_buffer(w_buffer_size); + axi_driver_slv.set_r_buffer(r_buffer_size); + axi_driver_slv.set_b_buffer(b_buffer_size); + + bytes_written = 0; + bytes_read = 0; + time_first_read = 0; + time_last_write = 0; + time_first_write = 0; + time_last_read = 0; + num_reads = 0; + num_writes = 0; + } + + void set_slv_write_cb(slv_write_cb_t cb) + { + this->slv_write_cb = cb; + } + + void set_slv_read_cb(slv_read_cb_t cb) + { + this->slv_read_cb = cb; + } + + private: + + void progress_new_writes() + { + if (write_wait_cycles > 0) { + write_wait_cycles--; + return; + } + + if (axi_driver_slv.has_w_beat()) + { + w_beat_request_t w_beat_req = axi_driver_slv.get_next_w_beat(); + + pcie_write_t write; + write.req = w_beat_req; + write.time = sim_time() + pcie_L; + + in_flight_write_requests.push(write); + + + write_wait_cycles = (uint32_t) (pcie_G * w_beat_req.data_size); + } + } + + + void progress_in_flight_writes() + { + if (in_flight_write_requests.empty()) return; + + pcie_write_t &write = in_flight_write_requests.front(); + + + if (sim_time() >= write.time && axi_driver_slv.can_send_b_beat()) + { + // TODO: consume data here! + SIM_PRINT("PCIe got data (data size: %d)!\n", write.req.data_size); + if (slv_write_cb) slv_write_cb(write.req.addr, write.req.w_beat.w_data, write.req.data_size); + + bytes_written += write.req.data_size; + if (num_writes==0) time_first_write = sim_time(); + num_writes++; + time_last_write = sim_time(); + + if (write.req.w_beat.w_last) + { + axi_driver_slv.send_b_beat(); + } + + in_flight_write_requests.pop(); + } + } + + + void progress_new_reads() + { + if (read_wait_cycles > 0) { + read_wait_cycles--; + return; + } + + if (axi_driver_slv.has_r_beat()) + { + r_beat_request_t r_beat_req = axi_driver_slv.get_next_r_beat(); + + pcie_read_t read; + read.req = r_beat_req; + read.time = sim_time() + pcie_L; + + in_flight_read_requests.push(read); + + read_wait_cycles = (uint32_t) (pcie_G * r_beat_req.data_size); + } + } + + + void progress_in_flight_reads() + { + if (in_flight_read_requests.empty()) return; + + pcie_read_t &read = in_flight_read_requests.front(); + + if (sim_time() >= read.time && axi_driver_slv.can_send_r_beat()) + { + // TODO: copy data here (memcpy in read.req.r_beat.r_data)! + SIM_PRINT("PCIe: got read request (data size: %d)!\n", read.req.data_size); + if (slv_read_cb) slv_read_cb(read.req.addr, read.req.r_beat.r_data, read.req.data_size); + + bytes_read += read.req.data_size; + if (num_reads==0) time_first_read = sim_time(); + num_reads++; + time_last_read = sim_time(); + + axi_driver_slv.send_r_beat(read.req.r_beat); + in_flight_read_requests.pop(); + } + } + + + private: + + void posedge() + { + //push staff on the AXI interface + progress_in_flight_reads(); + progress_in_flight_writes(); + + //progress AXI interface + axi_driver_mst.posedge(); + axi_driver_slv.posedge(); + + //sample signals from AXI interface + progress_new_reads(); + progress_new_writes(); + } + + void negedge() + { + axi_driver_mst.negedge(); + axi_driver_slv.negedge(); + } + + public: + void print_stats() + { + double write_time = ((double) (time_last_write - time_first_write)) / 1000; + double read_time = ((double) (time_last_read - time_first_read)) / 1000; + double write_throghput = THROUGHPUT_1GHZ(write_time, bytes_written); + double read_throghput = THROUGHPUT_1GHZ(read_time, bytes_read); + + printf("PCIe:\n"); + printf("\tWrites: beats: %d; bytes: %d; avg throughput: %.03lf Gbit/s\n", num_writes, bytes_written, write_throghput); + printf("\tReads: beats: %d; bytes: %d; avg throughput: %.03lf Gbit/s\n", num_reads, bytes_read, read_throghput); + } + }; + +} // namespace PsPIN \ No newline at end of file diff --git a/hw/verilator_model/src/PCIeMaster.hpp b/hw/verilator_model/src/PCIeMaster.hpp new file mode 100644 index 0000000..0ddf01b --- /dev/null +++ b/hw/verilator_model/src/PCIeMaster.hpp @@ -0,0 +1,193 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "AXIPort.hpp" +#include "Vpspin_verilator.h" +#include "verilated.h" +#include "SimModule.hpp" +#include "AXIMaster.hpp" +#include "pspin.hpp" + +#include +#include + +namespace PsPIN +{ + using std::placeholders::_1; + + template + class PCIeMaster : public SimModule + { + + public: + typedef std::function mst_write_cb_t; + typedef std::function mst_read_cb_t; + + private: + typedef struct write_descr + { + void *user_ptr; + } write_descr_t; + + typedef struct read_descr + { + uint8_t *data; + uint32_t offset; + size_t len; + void *user_ptr; + } read_descr_t; + + private: + AXIMaster axi_driver; + std::queue in_flight_reads; + std::queue in_flight_writes; + + mst_write_cb_t write_cb; + mst_read_cb_t read_cb; + + uint32_t bytes_written, bytes_read; + + public: + PCIeMaster(AXIPortType &axi_mst) + : axi_driver(axi_mst) + { + bytes_written = 0; + bytes_read = 0; + } + + void nic_mem_write(uint32_t nic_mem_addr, uint8_t *data, size_t len, void *user_ptr) + { + write_descr_t write; + write.user_ptr = user_ptr; + axi_driver.write(nic_mem_addr, data, len, 0); + in_flight_writes.push(write); + + bytes_written += len; + } + + void nic_mem_read(uint32_t nic_mem_addr, uint8_t *data, size_t len, void *user_ptr) + { + read_descr_t read; + read.data = data; + read.offset = 0; + read.len = len; + read.user_ptr = user_ptr; + axi_driver.read(nic_mem_addr, len); + in_flight_reads.push(read); + + bytes_read += len; + } + + void set_mst_write_cb(mst_write_cb_t wb) + { + this->write_cb = wb; + } + + void set_mst_read_cb(mst_read_cb_t rb) + { + this->read_cb = rb; + } + + private: + void posedge() + { + progress_axi_writes(); + progress_axi_reads(); + axi_driver.posedge(); + progress_axi_write_responses(); + progress_axi_read_responses(); + } + + void negedge() + { + axi_driver.negedge(); + } + + void print_stats() + { + printf("PCIe Master:\n"); + printf("\tBytes written: %d; Bytes read: %d\n", bytes_written, bytes_read); + + } + + private: + void progress_axi_writes() + { + if (axi_driver.has_aw_beat() && axi_driver.can_send_aw_beat()) + { + axi_driver.send_aw_beat(); + } + + if (axi_driver.has_w_beat() && axi_driver.can_send_w_beat()) + { + axi_driver.send_w_beat(); + } + } + + void progress_axi_write_responses() + { + if (!axi_driver.has_b_beat()) + return; + + bool write_completed = axi_driver.consume_b_beat(); + + if (write_completed) + { + assert(!in_flight_writes.empty()); + write_descr_t &write_descr = in_flight_writes.front(); + if (write_cb) write_cb(write_descr.user_ptr); + in_flight_writes.pop(); + } + } + + void progress_axi_reads() + { + if (axi_driver.has_ar_beat() && axi_driver.can_send_ar_beat()) + { + axi_driver.send_ar_beat(); + } + } + + void progress_axi_read_responses() + { + + if (axi_driver.has_r_beat()) + { + bool read_complete; + uint32_t length = AXI_SW; + + assert(!in_flight_reads.empty()); + read_descr_t &read_descr = in_flight_reads.front(); + + assert(read_descr.offset + length < read_descr.len); + uint8_t *dest_ptr = read_descr.data + read_descr.offset; + read_descr.offset += length; + + //do something with this data + read_complete = axi_driver.consume_r_beat(dest_ptr, length); + + if (read_complete) + { + // read complete + assert(read_descr.offset == read_descr.len); + if (read_cb) read_cb(read_descr.user_ptr); + in_flight_reads.pop(); + } + } + } + }; + +} // namespace PsPIN \ No newline at end of file diff --git a/hw/verilator_model/src/PCIeSlave.hpp b/hw/verilator_model/src/PCIeSlave.hpp new file mode 100644 index 0000000..3036a3d --- /dev/null +++ b/hw/verilator_model/src/PCIeSlave.hpp @@ -0,0 +1,257 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "AXIPort.hpp" +#include "Vpspin_verilator.h" +#include "verilated.h" +#include "SimModule.hpp" +#include "AXIMaster.hpp" +#include "AXISlave.hpp" +#include "pspin.hpp" + +#include +#include + +namespace PsPIN +{ + using std::placeholders::_1; + + template + class PCIeSlave : public SimModule + { + + typedef typename AXISlave::w_beat_request_t w_beat_request_t; + typedef typename AXISlave::r_beat_request_t r_beat_request_t; + + private: + typedef struct pcie_write + { + w_beat_request_t req; + uint64_t time; + } pcie_write_t; + + typedef struct pcie_read + { + r_beat_request_t req; + uint64_t time; + } pcie_read_t; + + private: + AXISlave axi_driver_slv; + + uint32_t pcie_L; + double pcie_G; + + uint32_t write_wait_cycles; + uint32_t read_wait_cycles; + + std::queue in_flight_write_requests; + std::queue in_flight_read_requests; + + public: + typedef std::function slv_write_cb_t; + typedef std::function slv_read_cb_t; + + // Statistics + private: + uint32_t bytes_written; + uint32_t bytes_read; + uint64_t time_first_read; + uint64_t time_last_write; + uint64_t time_first_write; + uint64_t time_last_read; + uint32_t num_reads; + uint32_t num_writes; + + slv_write_cb_t slv_write_cb; + slv_read_cb_t slv_read_cb; + + public: + PCIeSlave(AXISlvPortType &axi_slv, uint32_t aw_buffer_size, uint32_t w_buffer_size, uint32_t ar_buffer_size, uint32_t r_buffer_size, uint32_t b_buffer_size, uint32_t pcie_L, double pcie_G) + : axi_driver_slv(axi_slv), pcie_L(pcie_L), pcie_G(pcie_G) + { + write_wait_cycles = 0; + read_wait_cycles = 0; + + axi_driver_slv.set_ar_buffer(ar_buffer_size); + axi_driver_slv.set_aw_buffer(aw_buffer_size); + axi_driver_slv.set_w_buffer(w_buffer_size); + axi_driver_slv.set_r_buffer(r_buffer_size); + axi_driver_slv.set_b_buffer(b_buffer_size); + + bytes_written = 0; + bytes_read = 0; + time_first_read = 0; + time_last_write = 0; + time_first_write = 0; + time_last_read = 0; + num_reads = 0; + num_writes = 0; + } + + void set_slv_write_cb(slv_write_cb_t cb) + { + this->slv_write_cb = cb; + } + + void set_slv_read_cb(slv_read_cb_t cb) + { + this->slv_read_cb = cb; + } + + private: + + void progress_new_writes() + { + if (write_wait_cycles > 0) { + write_wait_cycles--; + if (write_wait_cycles > 0) return; + } + + if (axi_driver_slv.has_w_beat()) + { + w_beat_request_t w_beat_req = axi_driver_slv.get_next_w_beat(); + + pcie_write_t write; + write.req = w_beat_req; + write.time = sim_time() + pcie_L; + + in_flight_write_requests.push(write); + + write_wait_cycles = (uint32_t) (pcie_G * w_beat_req.data_size); + //SIM_PRINT("PCIe write wait cycles: %u\n", write_wait_cycles); + } + } + + + void progress_in_flight_writes() + { + if (in_flight_write_requests.empty()) return; + + pcie_write_t &write = in_flight_write_requests.front(); + + if (sim_time() >= write.time && axi_driver_slv.can_send_b_beat()) + { + // TODO: consume data here! + assert(write.req.w_beat.w_strb>0); + //int fs = __builtin_clzl(write.req.w_beat.w_strb); + int fs = __builtin_ffsl(write.req.w_beat.w_strb) - 1; + + //SIM_PRINT("PCIe got data: addr: %lx; offset: %d; actual address: %lx; size: %d (last: %u)!\n", write.req.addr, fs, write.req.addr + fs, write.req.data_size, (uint32_t) write.req.w_beat.w_last); + //for (int i=0; i<16; i++){ printf("%x ", ((uint32_t *) (write.req.w_beat.w_data))[i]); } + //uint64_t data = ((uint64_t *) write.req.w_beat.w_data)[0]; + //printf("\n U64: %lx\n", data); + + if (slv_write_cb) slv_write_cb(write.req.addr + fs, write.req.w_beat.w_data + fs, write.req.data_size); + + bytes_written += write.req.data_size; + if (num_writes==0) time_first_write = sim_time(); + num_writes++; + time_last_write = sim_time(); + + if (write.req.w_beat.w_last) + { + axi_driver_slv.send_b_beat(); + } + + in_flight_write_requests.pop(); + } + } + + + void progress_new_reads() + { + if (read_wait_cycles > 0) { + read_wait_cycles--; + return; + } + + if (axi_driver_slv.has_r_beat()) + { + r_beat_request_t r_beat_req = axi_driver_slv.get_next_r_beat(); + + pcie_read_t read; + read.req = r_beat_req; + read.time = sim_time() + pcie_L; + + in_flight_read_requests.push(read); + + read_wait_cycles = (uint32_t) (pcie_G * r_beat_req.data_size); + } + } + + + void progress_in_flight_reads() + { + if (in_flight_read_requests.empty()) return; + + pcie_read_t &read = in_flight_read_requests.front(); + + if (sim_time() >= read.time && axi_driver_slv.can_send_r_beat()) + { + // TODO: copy data here (memcpy in read.req.r_beat.r_data)! + SIM_PRINT("PCIe: got read request (data size: %d)!\n", read.req.data_size); + if (slv_read_cb) slv_read_cb(read.req.addr, read.req.r_beat.r_data, read.req.data_size); + + bytes_read += read.req.data_size; + if (num_reads==0) time_first_read = sim_time(); + num_reads++; + time_last_read = sim_time(); + + axi_driver_slv.send_r_beat(read.req.r_beat); + in_flight_read_requests.pop(); + } + } + + + private: + + void posedge() + { + //push staff on the AXI interface + progress_in_flight_reads(); + progress_in_flight_writes(); + + //progress AXI interface + //axi_driver_mst.posedge(); + axi_driver_slv.posedge(); + + //sample signals from AXI interface + progress_new_reads(); + progress_new_writes(); + } + + void negedge() + { + //axi_driver_mst.negedge(); + axi_driver_slv.negedge(); + } + + public: + void print_stats() + { + double write_time = ((double) (time_last_write - time_first_write)) / 1000; + double read_time = ((double) (time_last_read - time_first_read)) / 1000; + double write_throghput = THROUGHPUT_1GHZ(write_time, bytes_written); + double read_throghput = THROUGHPUT_1GHZ(read_time, bytes_read); + + printf("PCIe Slave:\n"); + printf("\tWrites: beats: %d; bytes: %d; avg throughput: %.03lf Gbit/s\n", num_writes, bytes_written, write_throghput); + printf("\tReads: beats: %d; bytes: %d; avg throughput: %.03lf Gbit/s\n", num_reads, bytes_read, read_throghput); + } + }; + +} // namespace PsPIN diff --git a/hw/verilator_model/src/SimControl.hpp b/hw/verilator_model/src/SimControl.hpp new file mode 100644 index 0000000..58c1d52 --- /dev/null +++ b/hw/verilator_model/src/SimControl.hpp @@ -0,0 +1,183 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "verilated.h" +#include "verilated_vcd_c.h" + +#include "SimModule.hpp" + +#include +#include + +template +class SimControl +{ +private: + T *tb; + VerilatedVcdC *m_trace; + uint64_t m_tickcount; + bool trace; + std::vector> sim_modules; + +public: + SimControl(T *tb, const char *trace_filename) : tb(tb) + { + m_tickcount = 0; + +#ifdef VERILATOR_HAS_TRACE + trace = trace_filename != NULL; + + if (trace) + { + Verilated::traceEverOn(true); + + m_trace = new VerilatedVcdC; + + // Initialize trace + tb->trace(m_trace, 99); + m_trace->open(trace_filename); + printf("trace on!\n"); + } +#else + printf("trace off!\n"); + trace = false; +#endif + } + + ~SimControl() + { +#ifdef VERILATOR_HAS_TRACE + m_trace->flush(); + m_trace->close(); +#endif + } + + std::vector>& get_modules() + { + return sim_modules; + } + + void add_module(SimModule &module) + { + sim_modules.push_back(std::ref(module)); + } + + // simulated time (ps) + uint64_t time() + { + return m_tickcount*1000; + } + + void reset() + { + tb->rst_ni = 0; + for (int i = 0; i < 4; i++) + { + tb->clk_i = 1; + tb->eval(); + tb->clk_i = 0; + tb->eval(); + } + tb->rst_ni = 1; + } + + void run_single() + { + m_tickcount++; + + tb->clk_i = 1; + tb->eval(); + +#ifdef VERILATOR_HAS_TRACE + if (trace) + { + m_trace->dump(1000 * m_tickcount); + } +#endif + run_sim_modules_posedge(); + + // Allow any combinatorial logic to settle before we tick + // the clock. This becomes necessary in the case where + // we may have modified or adjusted the inputs prior to + // coming into here, since we need all combinatorial logic + // to be settled before we call for a clock tick. + tb->clk_i = 1; + tb->eval(); + +#ifdef VERILATOR_HAS_TRACE + if (trace) + { + m_trace->dump(1000 * m_tickcount + 250); + m_trace->flush(); + } +#endif + + tb->clk_i = 0; + tb->eval(); + +#ifdef VERILATOR_HAS_TRACE + if (trace) + { + m_trace->dump(1000 * m_tickcount + 500); + } +#endif + + run_sim_modules_negedge(); + + tb->clk_i = 0; + tb->eval(); + +#ifdef VERILATOR_HAS_TRACE + if (trace) + { + m_trace->dump(1000 * m_tickcount + 750); + } +#endif + + } + + void run_all() + { + while (!done()) + { + run_single(); + } + } + + bool done() + { + return Verilated::gotFinish(); + } + +private: + void run_sim_modules_posedge() + { + for (auto it=sim_modules.begin(); it!=sim_modules.end(); ++it) + { + it->get().posedge(); + } + } + + void run_sim_modules_negedge() + { + for (auto it=sim_modules.begin(); it!=sim_modules.end(); ++it) + { + it->get().negedge(); + } + } + + +}; diff --git a/hw/verilator_model/src/SimModule.hpp b/hw/verilator_model/src/SimModule.hpp new file mode 100644 index 0000000..6014cb7 --- /dev/null +++ b/hw/verilator_model/src/SimModule.hpp @@ -0,0 +1,31 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include + +#define SIM_PRINT(FORMAT, ...) printf ("[%lu][%s:%u]: " FORMAT, sim_time(), __FILE__, __LINE__, ## __VA_ARGS__) + +class SimModule { +public: + virtual void posedge() = 0; + virtual void negedge() = 0; + + virtual void print_stats() = 0; + +public: + uint64_t sim_time() { + return sc_time_stamp(); + } +}; diff --git a/hw/verilator_model/src/main.cpp b/hw/verilator_model/src/main.cpp new file mode 100644 index 0000000..0e94385 --- /dev/null +++ b/hw/verilator_model/src/main.cpp @@ -0,0 +1,79 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "pspinsim.h" +#include "spin.h" + +#include +#include +#include + +//this is where the runtime SLM files are (they are flashed to L2) +#define SLM_FILES_PATH "../sim_files/slm_files" +#define PKT_TASK_FILE "../sim_files/tasks.csv" +#define PKT_DATA_FILE "../sim_files/data.bin" + +void pkt_out(uint8_t* data, size_t len) +{ + printf("Got packet! (len: %lu)\n", len); +} + +void pcie_slv_write(uint64_t addr, uint8_t* data, size_t len) +{ + printf("NIC wants to write %lu bytes to addr %lx\n", len, addr); +} + +void pcie_slv_read(uint64_t addr, uint8_t* data, size_t len) +{ + printf("NIC wants to read %lu bytes from addr %lx\n", len, addr); +} + +void pcie_mst_write_complete(void *user_ptr) +{ + printf("Write to NIC memory completed (user_ptr: %p)\n", user_ptr); +} + +void pcie_mst_read_complete(void *user_ptr) +{ + printf("Read from NIC memory completed (user_ptr: %p)\n", user_ptr); +} + +int main(int argc, char**argv) +{ + pspin_conf_t conf; + pspinsim_default_conf(&conf); + conf.slm_files_path = (char*) SLM_FILES_PATH; + + pspinsim_init(argc, argv, &conf); + + pspinsim_cb_set_pkt_out(pkt_out); + pspinsim_cb_set_pcie_slv_write(pcie_slv_write); + pspinsim_cb_set_pcie_slv_read(pcie_slv_read); + pspinsim_cb_set_pcie_mst_write_completion(pcie_mst_write_complete); + pspinsim_cb_set_pcie_mst_read_completion(pcie_mst_read_complete); + + int ret = pspinsim_packet_trace_read(PKT_TASK_FILE, PKT_DATA_FILE); + if (ret!=SPIN_SUCCESS) { + printf("Error while reading packet trace!\n"); + exit(1); + } + + pspinsim_packet_eos(); + + pspinsim_run(); + + pspinsim_fini(); + + return 0; +} diff --git a/hw/verilator_model/src/pspin.hpp b/hw/verilator_model/src/pspin.hpp new file mode 100644 index 0000000..369efb8 --- /dev/null +++ b/hw/verilator_model/src/pspin.hpp @@ -0,0 +1,170 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#include "spin.h" +#include "spin_hw_conf.h" + +#define THROUGHPUT_1GHZ(T, S) (((double)8 * S) / T) + +#define NI_CTRL_PORT_ASSIGN(SRC, SRC_PREFIX, DST) \ + { \ + (DST)->her_ready_i = &((SRC)->EVALUATOR(SRC_PREFIX, ready_o)); \ + (DST)->her_valid_o = &((SRC)->EVALUATOR(SRC_PREFIX, valid_i)); \ + (DST)->her_o.msgid = &((SRC)->EVALUATOR(SRC_PREFIX, msgid_i)); \ + (DST)->her_o.eom = &((SRC)->EVALUATOR(SRC_PREFIX, is_eom_i)); \ + (DST)->her_o.her_addr = &((SRC)->EVALUATOR(SRC_PREFIX, addr_i)); \ + (DST)->her_o.her_size = &((SRC)->EVALUATOR(SRC_PREFIX, size_i)); \ + (DST)->her_o.her_size = &((SRC)->EVALUATOR(SRC_PREFIX, size_i)); \ + (DST)->her_o.xfer_size = &((SRC)->EVALUATOR(SRC_PREFIX, xfer_size_i)); \ + (DST)->her_o.mpq_meta.handler_mem_addr = &((SRC)->EVALUATOR(SRC_PREFIX, meta_handler_mem_addr_i)); \ + (DST)->her_o.mpq_meta.handler_mem_size = &((SRC)->EVALUATOR(SRC_PREFIX, meta_handler_mem_size_i)); \ + (DST)->her_o.mpq_meta.host_mem_addr = &((SRC)->EVALUATOR(SRC_PREFIX, meta_host_mem_addr_i)); \ + (DST)->her_o.mpq_meta.host_mem_size = &((SRC)->EVALUATOR(SRC_PREFIX, meta_host_mem_size_i)); \ + (DST)->her_o.mpq_meta.hh_addr = &((SRC)->EVALUATOR(SRC_PREFIX, meta_hh_addr_i)); \ + (DST)->her_o.mpq_meta.hh_size = &((SRC)->EVALUATOR(SRC_PREFIX, meta_hh_size_i)); \ + (DST)->her_o.mpq_meta.ph_addr = &((SRC)->EVALUATOR(SRC_PREFIX, meta_ph_addr_i)); \ + (DST)->her_o.mpq_meta.ph_size = &((SRC)->EVALUATOR(SRC_PREFIX, meta_ph_size_i)); \ + (DST)->her_o.mpq_meta.th_addr = &((SRC)->EVALUATOR(SRC_PREFIX, meta_th_addr_i)); \ + (DST)->her_o.mpq_meta.th_size = &((SRC)->EVALUATOR(SRC_PREFIX, meta_th_size_i)); \ + (DST)->her_o.mpq_meta.scratchpad_addr[0] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_0_addr_i)); \ + (DST)->her_o.mpq_meta.scratchpad_size[0] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_0_size_i)); \ + (DST)->her_o.mpq_meta.scratchpad_addr[1] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_1_addr_i)); \ + (DST)->her_o.mpq_meta.scratchpad_size[1] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_1_size_i)); \ + (DST)->her_o.mpq_meta.scratchpad_addr[2] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_2_addr_i)); \ + (DST)->her_o.mpq_meta.scratchpad_size[2] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_2_size_i)); \ + (DST)->her_o.mpq_meta.scratchpad_addr[3] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_3_addr_i)); \ + (DST)->her_o.mpq_meta.scratchpad_size[3] = &((SRC)->EVALUATOR(SRC_PREFIX, meta_scratchpad_3_size_i)); \ + (DST)->pspin_active_i = &tb->pspin_active_o; \ + (DST)->feedback_valid_i = &tb->feedback_valid_o; \ + (DST)->feedback_ready_o = &tb->feedback_ready_i; \ + (DST)->feedback_msgid_i = &tb->feedback_msgid_o; \ + (DST)->feedback_her_addr_i = &tb->feedback_her_addr_o; \ + (DST)->feedback_her_size_i = &tb->feedback_her_size_o; \ + (DST)->eos_o = &tb->eos_i; \ + } + +#define NO_CMD_PORT_ASSIGN(SRC, SRC_PREFIX, DST) \ + { \ + (DST)->no_cmd_req_ready_o = &((SRC)->EVALUATOR(SRC_PREFIX, req_ready_i)); \ + (DST)->no_cmd_req_valid_i = &((SRC)->EVALUATOR(SRC_PREFIX, req_valid_o)); \ + (DST)->no_cmd_req_src_addr_i = &((SRC)->EVALUATOR(SRC_PREFIX, req_src_addr_o)); \ + (DST)->no_cmd_req_length_i = &((SRC)->EVALUATOR(SRC_PREFIX, req_length_o)); \ + (DST)->no_cmd_req_user_ptr_i = &((SRC)->EVALUATOR(SRC_PREFIX, req_user_ptr_o)); \ + (DST)->no_cmd_req_id_i = &((SRC)->EVALUATOR(SRC_PREFIX, req_id_o)); \ + (DST)->no_cmd_req_nid_i = &((SRC)->EVALUATOR(SRC_PREFIX, req_nid_o)); \ + (DST)->no_cmd_req_fid_i = &((SRC)->EVALUATOR(SRC_PREFIX, req_fid_o)); \ + (DST)->no_cmd_resp_valid_o = &((SRC)->EVALUATOR(SRC_PREFIX, resp_valid_i)); \ + (DST)->no_cmd_resp_id_o = &((SRC)->EVALUATOR(SRC_PREFIX, resp_id_i)); \ + } + +namespace PsPIN +{ + + typedef spin_ec_t mpq_meta_t; + + typedef struct her_descr + { + uint32_t msgid; + uint8_t eom; + + //full her descriptor + mem_addr_t her_addr; + mem_size_t her_size; + mem_size_t xfer_size; + + mpq_meta_t mpq_meta; + + //Note: this is used only between the driver and the NIC inbound engine. It + //is not sent to PsPIN. + uint64_t user_ptr; + uint64_t nic_arrival_time; + } __attribute__((__packed__)) her_descr_t; + + typedef struct mpq_meta_p + { + //handler memory + mem_addr_t *handler_mem_addr; + mem_size_t *handler_mem_size; + + //host memory + host_addr_t *host_mem_addr; + mem_size_t *host_mem_size; + + //header handler + mem_addr_t *hh_addr; + mem_size_t *hh_size; + + //payload handler + mem_addr_t *ph_addr; + mem_size_t *ph_size; + + //completion (aka tail) handler + mem_addr_t *th_addr; + mem_size_t *th_size; + + //L1 scratchpads + mem_addr_t *scratchpad_addr[NUM_CLUSTERS]; + mem_size_t *scratchpad_size[NUM_CLUSTERS]; + + } __attribute__((__packed__)) mpq_meta_p_t; + + typedef struct her_descr_p + { + uint16_t *msgid; + uint8_t *eom; + + //full her descriptor + mem_addr_t *her_addr; + mem_size_t *her_size; + mem_size_t *xfer_size; + + mpq_meta_p_t mpq_meta; + } __attribute__((__packed__)) her_descr_p_t; + + typedef struct ni_control_port + { + uint8_t *her_valid_o; + uint8_t *her_ready_i; + her_descr_p_t her_o; + uint8_t *pspin_active_i; + uint8_t *feedback_valid_i; + uint8_t *feedback_ready_o; + uint16_t *feedback_msgid_i; + uint32_t *feedback_her_addr_i; + uint32_t *feedback_her_size_i; + uint8_t *eos_o; + } ni_control_port_t; + + typedef struct no_cmd_port + { + // Request + uint8_t *no_cmd_req_ready_o; + uint8_t *no_cmd_req_valid_i; + uint64_t *no_cmd_req_src_addr_i; + uint32_t *no_cmd_req_length_i; + uint64_t *no_cmd_req_user_ptr_i; + uint8_t *no_cmd_req_id_i; + uint32_t *no_cmd_req_nid_i; + uint32_t *no_cmd_req_fid_i; + + // Response + uint8_t *no_cmd_resp_valid_o; + uint8_t *no_cmd_resp_id_o; + } no_cmd_port_t; + +} // namespace PsPIN diff --git a/hw/verilator_model/src/pspinsim.cpp b/hw/verilator_model/src/pspinsim.cpp new file mode 100644 index 0000000..771bb21 --- /dev/null +++ b/hw/verilator_model/src/pspinsim.cpp @@ -0,0 +1,335 @@ +// Copyright 2020 ETH Zurich +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include +#include +#include + +#include "Vpspin_verilator.h" +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "AXIPort.hpp" +#include "NICInbound.hpp" +#include "NICOutbound.hpp" +#include "PCIeSlave.hpp" +#include "PCIeMaster.hpp" +#include "SimControl.hpp" + +#include "pspinsim.h" +#include "spin.h" +#include "pspin.hpp" + +#define VCD_FILE "waves.vcd" + + +#define DEFAULT_NI_AXI_AW_BUFFER 32 +#define DEFAULT_NI_AXI_W_BUFFER 32 +#define DEFAULT_NI_AXI_B_BUFFER 32 + +#define NETWORK_G_200G 0.037252 +#define NETWORK_G_400G 0.018626 +#define PCIE_G_5_16 0.014782 + +#define DEFAULT_NO_AXI_AR_BUFFER 32 +#define DEFAULT_NO_AXI_R_BUFFER 32 +//#define DEFAULT_NO_NETWORK_G NETWORK_G_200G +#define DEFAULT_NO_NETWORK_G 0 +#define DEFAULT_NO_MAX_PKT_SIZE 2048 +#define DEFAULT_NO_NET_PKT_QUEUE_LEN 32 + +#define DEFAULT_PCIE_SLV_AW_BUFFER_SIZE 32 +#define DEFAULT_PCIE_SLV_W_BUFFER_SIZE 32 +#define DEFAULT_PCIE_SLV_AR_BUFFER_SIZE 32 +#define DEFAULT_PCIE_SLV_B_BUFFER_SIZE 32 +#define DEFAULT_PCIE_SLV_R_BUFFER_SIZE 32 +#define DEFAULT_PCIE_SLV_L 2 +#define DEFAULT_PCIE_SLV_G PCIE_G_5_16 + +#define PATH_MAX 1024 + +using namespace PsPIN; + +AXIPort ni_mst; +ni_control_port_t ni_control; +AXIPort no_mst; +no_cmd_port_t no_cmd; +AXIPort pcie_slv_port; +AXIPort pcie_mst_port; + +SimControl *sim; +NICInbound> *ni; +NICOutbound> *no; +PCIeSlave> *pcie_slv; +PCIeMaster> *pcie_mst; + +char slm_path[PATH_MAX]; + +double sc_time_stamp() +{ // Called by $time in Verilog + return sim->time(); +} + +const char* get_slm_path() +{ + return slm_path; +} + +int pspinsim_default_conf(pspin_conf_t *conf) +{ + conf->slm_files_path = NULL; + conf->ni_conf.axi_aw_buffer = DEFAULT_NI_AXI_AW_BUFFER; + conf->ni_conf.axi_w_buffer = DEFAULT_NI_AXI_W_BUFFER; + conf->ni_conf.axi_b_buffer = DEFAULT_NI_AXI_B_BUFFER; + + conf->no_conf.axi_ar_buffer = DEFAULT_NO_AXI_AR_BUFFER; + conf->no_conf.axi_r_buffer = DEFAULT_NO_AXI_R_BUFFER; + conf->no_conf.network_G = DEFAULT_NO_NETWORK_G; + conf->no_conf.max_pkt_size = DEFAULT_NO_MAX_PKT_SIZE; + conf->no_conf.max_network_queue_len = DEFAULT_NO_NET_PKT_QUEUE_LEN; + + conf->pcie_slv_conf.axi_aw_buffer = DEFAULT_PCIE_SLV_AW_BUFFER_SIZE; + conf->pcie_slv_conf.axi_w_buffer = DEFAULT_PCIE_SLV_W_BUFFER_SIZE; + conf->pcie_slv_conf.axi_ar_buffer = DEFAULT_PCIE_SLV_AR_BUFFER_SIZE; + conf->pcie_slv_conf.axi_b_buffer = DEFAULT_PCIE_SLV_B_BUFFER_SIZE; + conf->pcie_slv_conf.axi_r_buffer = DEFAULT_PCIE_SLV_R_BUFFER_SIZE; + conf->pcie_slv_conf.pcie_L = DEFAULT_PCIE_SLV_L; + conf->pcie_slv_conf.pcie_G = DEFAULT_PCIE_SLV_G; + + return SPIN_SUCCESS; +} + +int pspinsim_init(int argc, char **argv, pspin_conf_t *conf) +{ + Verilated::commandArgs(argc, argv); + Vpspin_verilator *tb = new Vpspin_verilator(); + sim = new SimControl(tb, VCD_FILE); + + pspin_conf_t default_conf; + if (conf==NULL) { + pspinsim_default_conf(&default_conf); + conf = &default_conf; + } + + // Define ports + AXI_MASTER_PORT_ASSIGN(tb, ni_slave, &ni_mst); + NI_CTRL_PORT_ASSIGN(tb, her, &ni_control) + AXI_MASTER_PORT_ASSIGN(tb, no_slave, &no_mst); + NO_CMD_PORT_ASSIGN(tb, nic_cmd, &no_cmd); + AXI_SLAVE_PORT_ASSIGN(tb, host_master, &pcie_slv_port); + AXI_MASTER_PORT_ASSIGN(tb, host_slave, &pcie_mst_port); + + // Instantiate simulation-only modules + ni = new NICInbound>(ni_mst, ni_control, L2_PKT_BUFF_START, L2_PKT_BUFF_SIZE); + no = new NICOutbound>(no_mst, no_cmd, conf->no_conf.network_G, conf->no_conf.max_pkt_size, conf->no_conf.max_network_queue_len); + pcie_slv = new PCIeSlave>(pcie_slv_port, conf->pcie_slv_conf.axi_aw_buffer, conf->pcie_slv_conf.axi_w_buffer, conf->pcie_slv_conf.axi_ar_buffer, conf->pcie_slv_conf.axi_r_buffer, conf->pcie_slv_conf.axi_b_buffer, conf->pcie_slv_conf.pcie_L, conf->pcie_slv_conf.pcie_G); + pcie_mst = new PCIeMaster>(pcie_mst_port); + + // Add simulation only modules + sim->add_module(*ni); + sim->add_module(*no); + sim->add_module(*pcie_slv); + sim->add_module(*pcie_mst); + + //before the reset! + char *slm_files_path = conf->slm_files_path; + if (slm_files_path==NULL) { + char *pspin_hw_env = getenv("PSPIN_HW"); + if (pspin_hw_env == NULL) { + printf("Error: you need to either specify where to read SLM files from or set PSPIN_HW env var and put slm files in sim_files/slm_files/!\n"); + return SPIN_ERR; + } + snprintf(slm_path, PATH_MAX, "%s/sim_files/slm_files/", pspin_hw_env); + } else { + snprintf(slm_path, PATH_MAX, "%s/", slm_files_path); + } + + // Send reset signal + sim->reset(); + + return SPIN_SUCCESS; +} + +int pspinsim_run() +{ + // Main loop + sim->run_all(); + + return SPIN_SUCCESS; +} + +int pspinsim_run_tick(uint8_t* done_flag) +{ + // Single step of the main loop + *done_flag = 0; + sim->run_single(); + if (sim->done()) *done_flag = 1; + + return SPIN_SUCCESS; +} + +int pspinsim_fini() +{ + printf("\n###### Statistics ######\n"); + for (auto it = sim->get_modules().begin(); it != sim->get_modules().end(); ++it){ + it->get().print_stats(); + printf("----------------------------------\n"); + } + delete sim; + + return SPIN_SUCCESS; +} + +int pspinsim_packet_trace_read(const char* pkt_file_path, const char* data_file_path) +{ + return ni->read_trace(pkt_file_path, data_file_path); +} + +int pspinsim_packet_add(spin_ec_t* ec, uint32_t msgid, uint8_t* pkt_data, size_t pkt_len, size_t pkt_l1_len, uint8_t eom, uint32_t wait_cycles, uint64_t user_ptr) +{ + her_descr_t her; + memcpy(&(her.mpq_meta), ec, sizeof(spin_ec_t)); + + her.msgid = msgid; + her.eom = eom; + her.her_addr = 0; //will be assigned later + her.her_size = pkt_len; + her.xfer_size = pkt_l1_len; + her.user_ptr = user_ptr; + + return ni->add_packet(her, pkt_data, pkt_len, wait_cycles); +} + +int pspinsim_packet_eos() +{ + ni->set_eos(); + return SPIN_SUCCESS; +} + +int pspinsim_cb_set_pkt_out(pkt_out_cb_t cb) +{ + NICOutbound>::out_packet_cb_t f(cb); + no->set_packet_out_cb(f); + return SPIN_SUCCESS; +} + + +int pspinsim_cb_set_pcie_slv_write(pcie_slv_write_cb_t cb) +{ + PCIeSlave>::slv_write_cb_t f(cb); + pcie_slv->set_slv_write_cb(f); + return SPIN_SUCCESS; +} + + +int pspinsim_cb_set_pcie_slv_read(pcie_slv_read_cb_t cb) +{ + PCIeSlave>::slv_read_cb_t f(cb); + pcie_slv->set_slv_read_cb(f); + return SPIN_SUCCESS; +} + +int pspinsim_cb_set_pcie_mst_write_completion(pcie_mst_write_cb_t cb) +{ + PCIeMaster>::mst_write_cb_t f(cb); + pcie_mst->set_mst_write_cb(f); + return SPIN_SUCCESS; +} + +int pspinsim_cb_set_pcie_mst_read_completion(pcie_mst_read_cb_t cb) +{ + PCIeMaster>::mst_read_cb_t f(cb); + pcie_mst->set_mst_read_cb(f); + return SPIN_SUCCESS; +} + +int pspinsim_cb_set_pkt_feedback(pkt_feedback_cb_t cb) +{ + NICInbound>::pkt_feedback_cb_t f(cb); + ni->set_feedback_cb(f); + return SPIN_SUCCESS; +} + +/* sPIN API functions (these are inteded to be into the actual API, no simulation) */ +int spin_nicmem_write(spin_nic_addr_t addr, void *data, size_t size, void* user_ptr) +{ + pcie_mst->nic_mem_write(addr, (uint8_t*) data, size, user_ptr); + return SPIN_SUCCESS; +} + +int spin_nicmem_read(spin_nic_addr_t addr, void *data, size_t size, void* user_ptr) +{ + pcie_mst->nic_mem_read(addr, (uint8_t*) data, size, user_ptr); + return SPIN_SUCCESS; +} + + +// this will be swapped with Timo's stuff +int spin_find_handler_by_name(char *binfile, char* handler_name, spin_nic_addr_t *handler_addr, size_t *handler_size) +{ + struct stat sb; + FILE *f = fopen(binfile, "rb"); + int fno = fileno(f); + fstat(fno, &sb); + + Elf32_Ehdr *elf_ptr = (Elf32_Ehdr*) mmap(NULL, sb.st_size, PROT_READ, MAP_PRIVATE, fno, 0); + uint32_t num_sections = elf_ptr->e_shnum; + + Elf32_Shdr *section_header_table = (Elf32_Shdr *)(((uint8_t *)elf_ptr) + elf_ptr->e_shoff); + + Elf32_Shdr *section_header_string_table = &(section_header_table[elf_ptr->e_shstrndx]); + char *sec_string_table = (char *)(((uint8_t *)elf_ptr) + section_header_string_table->sh_offset); + + //find string table for the symbols + char *sym_string_tab = NULL; + for (int i = 0; i < num_sections; i++) + { + //printf("section: %s\n", sec_string_table + section_header_table[i].sh_name); + char *sec_name = sec_string_table + section_header_table[i].sh_name; + if (!strcmp(sec_name, ".strtab")) + { + sym_string_tab = (char *)(((uint8_t *)elf_ptr) + section_header_table[i].sh_offset); + } + } + assert(sym_string_tab != NULL); + + for (int i = 0; i < num_sections; i++) + { + if (section_header_table[i].sh_type == SHT_SYMTAB) + { + //printf("sh type: %u; sh addr: %x\n", section_header_table[i].sh_type, section_header_table[i].sh_addr); + + Elf32_Sym *symbol_table = (Elf32_Sym *)(((uint8_t *)elf_ptr) + section_header_table[i].sh_offset); + uint32_t num_symbols = section_header_table[i].sh_size / sizeof(Elf32_Sym); + + for (int j = 0; j < num_symbols; j++) + { + char *sym_name = sym_string_tab + symbol_table[j].st_name; + + if (!strcmp(sym_name, handler_name)) + { + *handler_addr = symbol_table[j].st_value; + *handler_size = 4096; + break; + } + } + } + } + + munmap(elf_ptr, sb.st_size); + fclose(f); + + return SPIN_SUCCESS; +} diff --git a/hw/verilator_model/start_sim.sh b/hw/verilator_model/start_sim.sh new file mode 100755 index 0000000..b57e152 --- /dev/null +++ b/hw/verilator_model/start_sim.sh @@ -0,0 +1,9 @@ +#/bin/bash + +sim=pspin_release + +if [ "$1" -eq "1" ]; then + sim=pspin_debug +fi + +stdbuf -oL ${PSPIN_HW}/${PSPIN_SIM}/bin/$sim | tee transcript diff --git a/sourceme-template.sh b/sourceme-template.sh new file mode 100644 index 0000000..3df862a --- /dev/null +++ b/sourceme-template.sh @@ -0,0 +1,16 @@ +#ModelSim +#export PSPIN_SIM="modelsim_model" + +#Verilator +export PSPIN_SIM="verilator_model" + +#Update these! +export RISCV_GCC= +export PSPIN_HW= +export PSPIN_RT= + +#Don't change +export TARGET_VSIM=${PSPIN_HW}/$PSPIN_SIM +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/${PSPIN_HW}/verilator_model/lib/ +export TRACE_DIR="./" + diff --git a/sw/pulp-sdk/archi/.gitignore b/sw/pulp-sdk/archi/.gitignore new file mode 100644 index 0000000..fce4f97 --- /dev/null +++ b/sw/pulp-sdk/archi/.gitignore @@ -0,0 +1,6 @@ +*~ +build +build.log +.sconsign.dblite +include/archi/chips/gap9/memory_map.h +include/archi/chips/vega/memory_map.h \ No newline at end of file diff --git a/sw/pulp-sdk/archi/LICENSE b/sw/pulp-sdk/archi/LICENSE new file mode 100644 index 0000000..f433b1a --- /dev/null +++ b/sw/pulp-sdk/archi/LICENSE @@ -0,0 +1,177 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS diff --git a/sw/pulp-sdk/archi/Makefile b/sw/pulp-sdk/archi/Makefile new file mode 100644 index 0000000..64e6591 --- /dev/null +++ b/sw/pulp-sdk/archi/Makefile @@ -0,0 +1,69 @@ +build: + scons + +clean: + rm -f .sconsign.dblite + scons -c + +hwce_v4: + regmap --name=hwce --input-xls=doc/hwce/HWCE_v4_reference.xlsx --header=include/archi/hwce/hwce_v4.h + +hwce_v5: + regmap --name=hwce --input-xls=doc/hwce/HWCE_v5_reference.xlsx --header=include/archi/hwce/hwce_v5.h + +mchan_v7: + regmap --name=mchan --input-xls=doc/mchan/CL_DMA_v7_reference.xlsx --header=include/archi/dma/mchan_v7.h + +udma_mram_v1: + regmap --name=udma_mram --input-xls=doc/udma/MRAM_reference.xlsx --header=include/archi/udma/mram/udma_mram_v1.h + +udma_memcpy_v1: + regmap --name=udma_memcpy --input-xls=doc/udma/MEMCPY_v1_reference.xlsx --header=include/archi/udma/memcpy/v1/udma_memcpy_v1 + +udma_i2s_v2: + regmap --name=udma_i2s --input-xls=doc/udma/i2s/I2S_V2_reference.xlsx --header=include/archi/udma/i2s/udma_i2s_v2.h + +udma_i2s_v3: + regmap --name=udma_i2s --input-xls=doc/udma/i2s/I2S_V3_reference.xlsx --header=include/archi/udma/i2s/v3/udma_i2s_v3 + +udma_cpi_v1: + regmap --name=udma_cpi --input-xls=doc/udma/CAM_CPI_V1_reference.xlsx --header=include/archi/udma/cpi/udma_cpi_v1.h + +udma_hyper_v2: + regmap --name=hyper --input-xls=doc/HYPER_V2_reference.xlsx --header=include/archi/udma/hyper/udma_hyper_v2.h + +pmu_v3: + regmap --name=maestro --input-json=ips/pmu/pmu_v3.json --header=include/archi/maestro/maestro_v3.h + +gpio_v3: + regmap --name=gpio --input-xls=doc/gpio/APB_GPIO_V3_reference.xlsx --header=include/archi/gpio/gpio_v3.h + +pwm_v1: + regmap --name=pwm --input-xls=doc/pwm/pwm_v1.xlsx --header=include/archi/pwm/v1/pwm_v1 + +vega.apb_soc_ctrl: + regmap --name=apb_soc --input-xls=doc/vega/APB_SOC_CTRL_reference.xlsx --header=include/archi/chips/vega/apb_soc_ctrl.h + +gap9: udma_i2s_v3 + +vega: udma_i2s_v2 pmu_v3 udma_hyper_v2 mchan_v7 udma_mram_v1 hwce_v5 gpio_v3 vega.apb_soc_ctrl udma_cpi_v1 + regmap --name=pmu --input-json=chips/vega/pmu.json --header=include/archi/chips/vega/pmu.h + +gap: hwce_v4 udma_memcpy_v1 pwm_v1 + regmap --name=apb_soc --input-xls doc/gap/APB_SOC_CTRL_reference.xlsx --header=include/archi/chips/gap/apb_soc.h + +pulpissimo: udma_i2s_v2 + regmap --name=apb_soc --input-xls=doc/PULPISSIMO_APB_SOC_CTRL_reference.xlsx --header=include/archi/chips/pulpissimo/apb_soc_ctrl.h + +gen: + regmap --name=itc --input-json=ips/itc/itc_v1.json --header=include/archi/itc/itc_v1.h + regmap --name=udma_i2s --input-xls=doc/I2S_V1_reference.xlsx --header=include/archi/udma/i2s/udma_i2s_v1_new.h + regmap --name=maestro --input-json=ips/pmu/pmu_v2.json --header=include/archi/maestro/maestro_v2_new.h + regmap --name=pmu --input-json=chips/wolfe/pmu.json --header=include/archi/chips/wolfe/pmu.h + regmap --name=maestro --input-json=ips/pmu/pmu_v1.json --header=include/archi/maestro/maestro_v1_new.h + regmap --name=timer --input-xls=doc/TIMER_UNIT_reference.xlsx --header=include/archi/timer/timer_v2.h + regmap --name=rtc --input-xls=doc/RTC_UNIT_reference.xlsx --header=include/archi/rtc/rtc_v2.h + regmap --name=apb_soc --input-xls=doc/WOLFE_APB_SOC_CTRL_reference.xlsx --header=include/archi/chips/wolfe/apb_soc_ctrl_new.h + regmap --name=gpio --input-xls=doc/APB_GPIO_reference.xlsx --header=include/archi/gpio/gpio_v2_new.h + +.PHONY: build clean gen \ No newline at end of file diff --git a/sw/pulp-sdk/archi/SConstruct b/sw/pulp-sdk/archi/SConstruct new file mode 100644 index 0000000..74f3827 --- /dev/null +++ b/sw/pulp-sdk/archi/SConstruct @@ -0,0 +1,207 @@ +import os +import subprocess +import shlex +import pulp_config as plpconfig +import SCons.Util + +install_dir = os.environ.get('INSTALL_DIR') +target_install_dir = os.environ.get('TARGET_INSTALL_DIR') + +if install_dir is None: + install_dir = 'install' + +if target_install_dir is None: + target_install_dir = 'install' + +files = [ 'archi/pulp_defs.h', 'archi/pulp.h', 'archi/utils.h' ] +files.append('archi/gvsoc/gvsoc.h') + +try: + files += subprocess.check_output(shlex.split('plpfiles copy --item=archi_files')).decode('UTF-8').split() +except subprocess.CalledProcessError as e: + print (e.output) + raise + +configs = plpconfig.get_configs_from_env() + +def append_file(file): + global files + if not file in files: + files.append(file) + +def append_archi_files(file): + append_file(file + '.h') + append_file(file + '_accessors.h') + append_file(file + '_constants.h') + append_file(file + '_groups.h') + append_file(file + '_gvsoc.h') + append_file(file + '_macros.h') + append_file(file + '_regfields.h') + append_file(file + '_regmap.h') + append_file(file + '_regs.h') + append_file(file + '_structs.h') + + +for config in configs: + + # The old system is storing the path to archi files in the json file + # This has to be migrated so that only IP information is stored in the + # json file and this build system is them copying the archi files according + # to the IP information found in the json file. + + chip = config.get('**/chip/pulp_chip_family').get() + + # UDMA I2S + udma_i2s = config.get_child_int('**/udma/i2s/version') + if udma_i2s is not None: + if udma_i2s == 1: + append_file('archi/udma/i2s/udma_i2s_v%d_new.h' % udma_i2s) + else: + if udma_i2s >= 3: + append_archi_files('archi/udma/i2s/v%d/udma_i2s_v%d' % (udma_i2s, udma_i2s)) + else: + append_file('archi/udma/i2s/udma_i2s_v%d.h' % udma_i2s) + + # UDMA CPI + udma_cpi = config.get_child_int('**/udma/cpi/version') + if udma_cpi is not None: + append_file('archi/udma/cpi/udma_cpi_v%d.h' % udma_cpi) + if udma_cpi == 1: + append_file('archi/udma/cpi/udma_cpi_v%d_old.h' % udma_cpi) + + # UDMA HYPER + udma_hyper = config.get_child_int('**/udma/hyper/version') + if udma_hyper is not None: + append_file('archi/udma/hyper/udma_hyper_v%d.h' % udma_hyper) + + # UDMA MEMCPY + udma_memcpy = config.get_child_int('**/udma/tcdm/version') + if udma_memcpy is not None: + append_archi_files('archi/udma/memcpy/v1/udma_memcpy_v%d' % udma_memcpy) + + + # UDMA MRAM + udma_mram = config.get_child_int('**/udma/mram/version') + if udma_mram is not None: + append_file('archi/udma/mram/udma_mram_v%d.h' % udma_mram) + + + + # HWCE + hwce = config.get_child_int('**/hwce/version') + if hwce is not None: + append_file('archi/hwce/hwce_v%d.h' % hwce) + if hwce == 4: + append_file('archi/hwce/hwce_v%d_old.h' % hwce) + + + # RTC + rtc = config.get('**/soc/rtc') + if rtc is None: + rtc = config.get('**/chip/rtc') + if rtc is not None: + rtc_version = config.get_child_int('**/rtc/version') + if rtc_version == 1 or rtc_version is None: + append_file('archi/vendors/dolphin/rtc.h') + else: + append_file('archi/rtc/rtc_v%d.h' % (rtc_version)) + + # PMU + pmu = config.get_child_int('**/soc/pmu/version') + if pmu is None: + pmu = config.get_child_int('**/chip/pmu/version') + + if pmu is not None: + append_file('archi/maestro/maestro_v1_new.h') + if pmu >= 3: + append_file('archi/maestro/maestro_v%d.h' % pmu) + else: + append_file('archi/maestro/maestro_v%d.h' % pmu) + append_file('archi/maestro/maestro_v%d_new.h' % pmu) + + # ITC + itc = config.get_child_int('**/soc/fc_itc/version') + if itc is not None: + append_file('archi/itc/itc_v%d.h' % itc) + + # GPIO + gpio = config.get_child_int('**/gpio/version') + if gpio is not None: + append_file('archi/gpio/gpio_v%d.h' % gpio) + if gpio == 2: + append_file('archi/gpio/gpio_v%d_new.h' % gpio) + + # TIMER + timer = config.get_child_int('**/timer/version') + if timer is not None: + append_file('archi/timer/timer_v%d.h' % timer) + + + # Chip specific files can be included here + if chip == 'vega': + append_file('archi/pwm/pwm_v1.h') + append_file('archi/chips/vega/apb_soc_ctrl.h') + append_file('archi/chips/vega/pmu.h') + elif chip == 'gap9': + append_file('archi/pwm/pwm_v1.h') + append_file('archi/chips/gap9/apb_soc_ctrl.h') + append_file('archi/chips/gap9/pmu.h') + elif chip == 'pulpissimo': + append_file('archi/chips/pulpissimo/apb_soc_ctrl.h') + elif chip == 'pulp': + append_file('archi/chips/pulp/apb_soc_ctrl.h') + elif chip == 'gap': + append_file('archi/pwm/pwm_v1.h') + append_archi_files('archi/pwm/v1/pwm_v1') + elif chip == 'wolfe': + append_archi_files('archi/pwm/v1/pwm_v1') + append_file('archi/pwm/pwm_v1.h') + append_file('archi/chips/wolfe/pmu.h') + append_file('archi/chips/wolfe/apb_soc.h') + append_file('archi/chips/wolfe/apb_soc_ctrl_new.h') + elif chip == 'wolfe': + append_file('archi/pwm/pwm_v1.h') + elif chip == 'vivosoc3': + append_file('archi/chips/vivosoc3/fll.h') + append_file('archi/chips/vivosoc3/freq.h') + elif chip == 'vivosoc3_5': + append_file('archi/chips/vivosoc3_5/fll.h') + append_file('archi/chips/vivosoc3_5/freq.h') + elif chip == 'vivosoc3_1': + append_file('archi/chips/vivosoc3_1/fll.h') + append_file('archi/chips/vivosoc3_1/freq.h') + elif chip == 'vivosoc4': + append_file('archi/chips/vivosoc4/fll.h') + append_file('archi/chips/vivosoc4/freq.h') + + + if chip == 'vega' or chip == 'gap9': + out_file_path = 'archi/chips/%s/memory_map.h' % chip + + try: + os.makedirs(os.path.dirname(out_file_path)) + except: + pass + + with open('include/' + out_file_path, 'w') as out_file: + with open('include/archi/chips/%s/memory_map.h.in' % chip, 'r') as in_file: + content = in_file.read() + + content = content.replace('@l2_shared_size@', config.get_int('**/l2_shared/size')) + + out_file.write(content) + + append_file(out_file_path) + + + + +targets = [] + +for file in files: + file_path = os.path.join('include', file) + targets.append(InstallAs(os.path.join(install_dir, file_path), file_path)) + targets.append(InstallAs(os.path.join(target_install_dir, file_path), file_path)) + + +Default(targets) diff --git a/sw/pulp-sdk/archi/doc/APB_GPIO_reference.xlsx b/sw/pulp-sdk/archi/doc/APB_GPIO_reference.xlsx new file mode 120000 index 0000000..8d3d62f --- /dev/null +++ b/sw/pulp-sdk/archi/doc/APB_GPIO_reference.xlsx @@ -0,0 +1 @@ +../../../rtl/gap/docs/IP_REFERENCES/APB_GPIO_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/CL_EVENT_UNIT_reference.xlsx b/sw/pulp-sdk/archi/doc/CL_EVENT_UNIT_reference.xlsx new file mode 100644 index 0000000..5b8a45b Binary files /dev/null and b/sw/pulp-sdk/archi/doc/CL_EVENT_UNIT_reference.xlsx differ diff --git a/sw/pulp-sdk/archi/doc/FC_EVENT_UNIT_reference.xlsx b/sw/pulp-sdk/archi/doc/FC_EVENT_UNIT_reference.xlsx new file mode 100644 index 0000000..36e1a17 Binary files /dev/null and b/sw/pulp-sdk/archi/doc/FC_EVENT_UNIT_reference.xlsx differ diff --git a/sw/pulp-sdk/archi/doc/HYPER_V2_reference.xlsx b/sw/pulp-sdk/archi/doc/HYPER_V2_reference.xlsx new file mode 120000 index 0000000..5aef280 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/HYPER_V2_reference.xlsx @@ -0,0 +1 @@ +../../../rtl/vega/fe/ips/udma/udma_hyperbus_octospi/docs/HYPERBUS_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/PULPISSIMO_APB_SOC_CTRL_reference.xlsx b/sw/pulp-sdk/archi/doc/PULPISSIMO_APB_SOC_CTRL_reference.xlsx new file mode 100644 index 0000000..b67b776 Binary files /dev/null and b/sw/pulp-sdk/archi/doc/PULPISSIMO_APB_SOC_CTRL_reference.xlsx differ diff --git a/sw/pulp-sdk/archi/doc/RTC_UNIT_reference.xlsx b/sw/pulp-sdk/archi/doc/RTC_UNIT_reference.xlsx new file mode 100644 index 0000000..a7fcc8a Binary files /dev/null and b/sw/pulp-sdk/archi/doc/RTC_UNIT_reference.xlsx differ diff --git a/sw/pulp-sdk/archi/doc/TIMER_UNIT_reference.xlsx b/sw/pulp-sdk/archi/doc/TIMER_UNIT_reference.xlsx new file mode 120000 index 0000000..c6b50da --- /dev/null +++ b/sw/pulp-sdk/archi/doc/TIMER_UNIT_reference.xlsx @@ -0,0 +1 @@ +../../../rtl/vega/fe/ips/timer_unit/doc/TIMER_UNIT_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/WOLFE_APB_SOC_CTRL_reference.xlsx b/sw/pulp-sdk/archi/doc/WOLFE_APB_SOC_CTRL_reference.xlsx new file mode 100644 index 0000000..a852af4 Binary files /dev/null and b/sw/pulp-sdk/archi/doc/WOLFE_APB_SOC_CTRL_reference.xlsx differ diff --git a/sw/pulp-sdk/archi/doc/gap/APB_SOC_CTRL_reference.xlsx b/sw/pulp-sdk/archi/doc/gap/APB_SOC_CTRL_reference.xlsx new file mode 120000 index 0000000..b9a4173 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/gap/APB_SOC_CTRL_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/gap_rev1/docs/IP_REFERENCES/APB_SOC_CTRL_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/gpio/APB_GPIO_V3_reference.xlsx b/sw/pulp-sdk/archi/doc/gpio/APB_GPIO_V3_reference.xlsx new file mode 120000 index 0000000..3fab498 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/gpio/APB_GPIO_V3_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/vega/fe/ips/apb/apb_gpio/docs/APB_GPIO_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/hwce/HWCE_v4_reference.xlsx b/sw/pulp-sdk/archi/doc/hwce/HWCE_v4_reference.xlsx new file mode 120000 index 0000000..fbd272a --- /dev/null +++ b/sw/pulp-sdk/archi/doc/hwce/HWCE_v4_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/gap_master/docs/IP_REFERENCES/HWCE_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/hwce/HWCE_v5_reference.xlsx b/sw/pulp-sdk/archi/doc/hwce/HWCE_v5_reference.xlsx new file mode 120000 index 0000000..2f9c210 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/hwce/HWCE_v5_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/vega/fe/ips/hwce-new/docs/HWCE_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/mchan/CL_DMA_v7_reference.xlsx b/sw/pulp-sdk/archi/doc/mchan/CL_DMA_v7_reference.xlsx new file mode 120000 index 0000000..f8365f4 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/mchan/CL_DMA_v7_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/vega/fe/ips/mchan/doc/CL_DMA_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/pwm/pwm_v1.xlsx b/sw/pulp-sdk/archi/doc/pwm/pwm_v1.xlsx new file mode 120000 index 0000000..89d987b --- /dev/null +++ b/sw/pulp-sdk/archi/doc/pwm/pwm_v1.xlsx @@ -0,0 +1 @@ +../../../../rtl/gap8_revc/docs/IP_REFERENCES/APB_ADV_TIMER_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/udma/CAM_CPI_V1_reference.xlsx b/sw/pulp-sdk/archi/doc/udma/CAM_CPI_V1_reference.xlsx new file mode 120000 index 0000000..f749cf6 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/udma/CAM_CPI_V1_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/vega/fe/ips/udma/udma_camera/doc/CAM_CPI_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/udma/MEMCPY_v1_reference.xlsx b/sw/pulp-sdk/archi/doc/udma/MEMCPY_v1_reference.xlsx new file mode 120000 index 0000000..c4ce0d1 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/udma/MEMCPY_v1_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/gap8_revc/fe/ips/udma/doc/MEMCPY_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/udma/MRAM_reference.xlsx b/sw/pulp-sdk/archi/doc/udma/MRAM_reference.xlsx new file mode 120000 index 0000000..fe45789 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/udma/MRAM_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/vega/fe/ips/udma/udma_mram/docs/MRAM_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V1_reference.xlsx b/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V1_reference.xlsx new file mode 120000 index 0000000..75f5c57 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V1_reference.xlsx @@ -0,0 +1 @@ +../../../../../rtl/gap_rev1/fe/ips/udma/doc/I2S_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V2_reference.xlsx b/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V2_reference.xlsx new file mode 120000 index 0000000..8cd9a97 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V2_reference.xlsx @@ -0,0 +1 @@ +../../../../../rtl/vega/fe/ips/udma/udma_i2s/doc/I2S_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V3_reference.xlsx b/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V3_reference.xlsx new file mode 100644 index 0000000..eca5962 Binary files /dev/null and b/sw/pulp-sdk/archi/doc/udma/i2s/I2S_V3_reference.xlsx differ diff --git a/sw/pulp-sdk/archi/doc/vega/APB_SOC_CTRL_reference.xlsx b/sw/pulp-sdk/archi/doc/vega/APB_SOC_CTRL_reference.xlsx new file mode 120000 index 0000000..a5f9656 --- /dev/null +++ b/sw/pulp-sdk/archi/doc/vega/APB_SOC_CTRL_reference.xlsx @@ -0,0 +1 @@ +../../../../rtl/vega/docs/IP_REFERENCES/APB_SOC_CTRL_reference.xlsx \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/arnold/apb_soc.h b/sw/pulp-sdk/archi/include/archi/chips/arnold/apb_soc.h new file mode 100644 index 0000000..d49c543 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/arnold/apb_soc.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_ARNOLD_APB_SOC_H__ +#define __ARCHI_ARNOLD_APB_SOC_H__ + +#define APB_SOC_BOOT_OTHER 0 +#define APB_SOC_BOOT_JTAG 1 +#define APB_SOC_BOOT_SPI 2 +#define APB_SOC_BOOT_ROM 3 +#define APB_SOC_BOOT_PRELOAD 4 +#define APB_SOC_BOOT_HYPER 5 +#define APB_SOC_BOOT_SPIM 6 +#define APB_SOC_BOOT_SPIM_QPI 7 + +#define APB_SOC_PLT_OTHER 0 +#define APB_SOC_PLT_FPGA 1 +#define APB_SOC_PLT_RTL 2 +#define APB_SOC_PLT_VP 3 +#define APB_SOC_PLT_CHIP 4 + +//PADs configuration is made of 8bits out of which only the first 6 are used +//bit0 enable pull UP +//bit1 enable pull DOWN +//bit2 enable ST +//bit3 enable SlewRate Limit +//bit4..5 Driving Strength +//bit6..7 not used + +#define APB_SOC_BOOTADDR_OFFSET 0x04 +#define APB_SOC_INFO_OFFSET 0x00 //contains number of cores [31:16] and clusters [15:0] +#define APB_SOC_INFOEXTD_OFFSET 0x04 //not used at the moment +#define APB_SOC_NOTUSED0_OFFSET 0x08 //not used at the moment +#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C //not used at the moment + +#define APB_SOC_PADFUN0_OFFSET 0x10 +#define APB_SOC_PADCFG0_OFFSET 0x20 + +#define APB_SOC_PADFUN_OFFSET(g) (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins g*16+0 (bits [1:0]) to g*16+15 (bits [31:30]) +#define APB_SOC_PADFUN_NO(pad) ((pad) >> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/arnold/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/arnold/memory_map.h new file mode 100644 index 0000000..e05ca19 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/arnold/memory_map.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_ARNOLD_MEMORY_MAP_H__ +#define __ARCHI_ARNOLD_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_FC_HWPE_OFFSET 0x0000C000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_OFFSET 0x00000400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/arnold/properties.h b/sw/pulp-sdk/archi/include/archi/chips/arnold/properties.h new file mode 100644 index 0000000..cd6d238 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/arnold/properties.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_ARNOLD_PROPERTIES_H__ +#define __ARCHI_ARNOLD_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 3 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 2 +#define APB_SOC_VERSION 3 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 3 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define HWME_VERSION 1 +#define PADS_VERSION 2 + + +/* + * CORE IDS + */ + +#define ARCHI_FC_CID 31 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0x80 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/bigpulp/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/bigpulp/memory_map.h new file mode 100644 index 0000000..5444e49 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/bigpulp/memory_map.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_BIGPULP_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_BIGPULP_MEMORY_MAP_H__ + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + + +#define ARCHI_UART_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00003000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 +#define ARCHI_RAB_CFG_OFFSET 0x00030000 +#define ARCHI_MAILBOX_OFFSET 0x00021000 // Interface 1 + +#define ARCHI_UART_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UART_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_RAB_CFG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_RAB_CFG_OFFSET ) +#define ARCHI_MAILBOX_BASE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_MAILBOX_OFFSET ) + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x1B000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TRYX_OFFSET 0x00000BFC +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_TRYX_ADDR ( 0x10000000 + ARCHI_CLUSTER_PERIPHERALS_OFFSET + ARCHI_TRYX_OFFSET ) +#define ARCHI_TIMER_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_TIMER_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/bigpulp/properties.h b/sw/pulp-sdk/archi/include/archi/chips/bigpulp/properties.h new file mode 100644 index 0000000..190121e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/bigpulp/properties.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_BIGPULP_PROPERTIES_H__ +#define __ARCHI_CHIPS_BIGPULP_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 262144 + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_NO_L1_TINY 1 + + + +/* + * IP VERSIONS + */ + +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define EU_VERSION 3 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 +#if PULP_CHIP == CHIP_BIGPULP_ZU9EG +#define ARCHI_NB_CLUSTER 2 +#endif + + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/devchip/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/devchip/memory_map.h new file mode 100644 index 0000000..d84b39f --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/devchip/memory_map.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_DEVCHIP_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_DEVCHIP_MEMORY_MAP_H__ + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + + +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/devchip/properties.h b/sw/pulp-sdk/archi/include/archi/chips/devchip/properties.h new file mode 100644 index 0000000..f78bac7 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/devchip/properties.h @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_DEVCHIP_PROPERTIES_H__ +#define __ARCHI_CHIPS_DEVCHIP_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 65536 + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 +#define HWCE_VERSION 5 +#define PADS_VERSION 2 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1< +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Core information register +#define APB_SOC_INFO_OFFSET 0x0 + +// RFU +#define APB_SOC_NOTUSED0_OFFSET 0x4 + +// RFU +#define APB_SOC_NOTUSED1_OFFSET 0x8 + +// Isolate cluster register +#define APB_SOC_CL_ISOLATE_OFFSET 0xc + +// Cluster busy register +#define APB_SOC_CL_BUSY_OFFSET 0x6c + +// PMU bypass configuration register +#define APB_SOC_CL_BYPASS_OFFSET 0x70 + +// JTAG external register +#define APB_SOC_JTAGREG_OFFSET 0x74 + +// L2 sleep configuration register +#define APB_SOC_L2_SLEEP_OFFSET 0x78 + +// Alias for SAFE_PMU_SLEEPCTRL +#define APB_SOC_SLEEP_CTRL_OFFSET 0x7c + +// EOC and chip status register +#define APB_SOC_CORESTATUS_OFFSET 0xa0 + +// EOC and chip status register read mirror +#define APB_SOC_CORESTATUS_RO_OFFSET 0xc0 + +// DC/DC configuration register +#define APB_SOC_SAFE_PMU_RAR_OFFSET 0x100 + +// Sleep modes configuration register +#define APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET 0x104 + +// L2 rententive state configuration +#define APB_SOC_SAFE_PMU_FORCE_OFFSET 0x108 + +// Mux config register (pad 0-15) +#define APB_SOC_SAFE_PADFUN0_OFFSET 0x140 + +// Mux config register (pad 16-31) +#define APB_SOC_SAFE_PADFUN1_OFFSET 0x144 + +// Mux config register (pad 32-47) +#define APB_SOC_SAFE_PADFUN2_OFFSET 0x148 + +// Mux config register (pad 48-63) +#define APB_SOC_SAFE_PADFUN3_OFFSET 0x14c + +// Sleep config register (pad 0-15) +#define APB_SOC_SAFE_SLEEPPADCFG0_OFFSET 0x150 + +// Mux config register (pad 16-31) +#define APB_SOC_SAFE_SLEEPPADCFG1_OFFSET 0x154 + +// Mux config register (pad 32-47) +#define APB_SOC_SAFE_SLEEPPADCFG2_OFFSET 0x158 + +// Mux config register (pad 48-63) +#define APB_SOC_SAFE_SLEEPPADCFG3_OFFSET 0x15c + +// Enable Sleep mode for pads +#define APB_SOC_SAFE_PADSLEEP_OFFSET 0x160 + +// Function register (pad 0 to 3) +#define APB_SOC_SAFE_PADCFG0_OFFSET 0x180 + +// Function register (pad 4 to 7) +#define APB_SOC_SAFE_PADCFG1_OFFSET 0x184 + +// Function register (pad 8 to 11) +#define APB_SOC_SAFE_PADCFG2_OFFSET 0x188 + +// Function register (pad 12 to 15) +#define APB_SOC_SAFE_PADCFG3_OFFSET 0x18c + +// Function register (pad 16 to 19) +#define APB_SOC_SAFE_PADCFG4_OFFSET 0x190 + +// Function register (pad 20 to 23) +#define APB_SOC_SAFE_PADCFG5_OFFSET 0x194 + +// Function register (pad 24 to 27) +#define APB_SOC_SAFE_PADCFG6_OFFSET 0x198 + +// Function register (pad 28 to 31) +#define APB_SOC_SAFE_PADCFG7_OFFSET 0x19c + +// Function register (pad 32 to 35) +#define APB_SOC_SAFE_PADCFG8_OFFSET 0x1a0 + +// Function register (pad 36 to 39) +#define APB_SOC_SAFE_PADCFG9_OFFSET 0x1a4 + +// Function register (pad 40 to 43) +#define APB_SOC_SAFE_PADCFG10_OFFSET 0x1a8 + +// Function register (pad 44 to 47) +#define APB_SOC_SAFE_PADCFG11_OFFSET 0x1ac + +// Function register (pad 48 to 51) +#define APB_SOC_SAFE_PADCFG12_OFFSET 0x1b0 + +// Function register (pad 52 to 55) +#define APB_SOC_SAFE_PADCFG13_OFFSET 0x1b4 + +// Function register (pad 56 to 59) +#define APB_SOC_SAFE_PADCFG14_OFFSET 0x1b8 + +// Function register (pad 60 to 63) +#define APB_SOC_SAFE_PADCFG15_OFFSET 0x1bc + +// GPIO power domain pad input isolation register +#define APB_SOC_REG_GPIO_ISO_OFFSET 0x1c0 + +// CAM power domain pad input isolation register +#define APB_SOC_REG_CAM_ISO_OFFSET 0x1c4 + +// LVDS power domain pad input isolation register +#define APB_SOC_REG_LVDS_ISO_OFFSET 0x1c8 + + + +// +// REGISTERS FIELDS +// + +// Number of clusters (access: R) +#define APB_SOC_INFO_NB_CL_BIT 0 +#define APB_SOC_INFO_NB_CL_WIDTH 16 +#define APB_SOC_INFO_NB_CL_MASK 0xffff + +// Number of cores (access: R) +#define APB_SOC_INFO_NB_CORES_BIT 16 +#define APB_SOC_INFO_NB_CORES_WIDTH 16 +#define APB_SOC_INFO_NB_CORES_MASK 0xffff0000 + +// Isolate cluster. Inhibits AXI transactions from cluster to SoC: - 1'b0: Disable - 1'b1: Enable (access: R/W) +#define APB_SOC_CL_ISOLATE_EN_BIT 0 +#define APB_SOC_CL_ISOLATE_EN_WIDTH 1 +#define APB_SOC_CL_ISOLATE_EN_MASK 0x1 + +// Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) (access: R) +#define APB_SOC_CL_BUSY_BUSY_BIT 0 +#define APB_SOC_CL_BUSY_BUSY_WIDTH 1 +#define APB_SOC_CL_BUSY_BUSY_MASK 0x1 + +// Bypass Maestro PMU controller configuration bitfield: - 1b0: disabled - 1b1: enabled (access: R/W) +#define APB_SOC_CL_BYPASS_BYP_POW_BIT 0 +#define APB_SOC_CL_BYPASS_BYP_POW_WIDTH 1 +#define APB_SOC_CL_BYPASS_BYP_POW_MASK 0x1 + +// Bypass Maestro PMU configuration selection configuration bitfield: - 1b0: use default - 1b1: use user configuration (bitfields from bits 3 to 15 of CL_BYPASS register) (access: R/W) +#define APB_SOC_CL_BYPASS_BYP_CFG_BIT 1 +#define APB_SOC_CL_BYPASS_BYP_CFG_WIDTH 1 +#define APB_SOC_CL_BYPASS_BYP_CFG_MASK 0x2 + +// Cluster state configuration and status bitfield: - 1b0: off - 1b1: on Status information is correct only when bypass mode is enabled. (access: R/W) +#define APB_SOC_CL_BYPASS_CL_STATE_BIT 3 +#define APB_SOC_CL_BYPASS_CL_STATE_WIDTH 1 +#define APB_SOC_CL_BYPASS_CL_STATE_MASK 0x8 + +// Max current allowed on cluster TRC configuration bitfield. (access: R/W) +#define APB_SOC_CL_BYPASS_CURRSET_BIT 4 +#define APB_SOC_CL_BYPASS_CURRSET_WIDTH 3 +#define APB_SOC_CL_BYPASS_CURRSET_MASK 0x70 + +// Number of REFCLK 32kHz after cluster power ok has arised to release TR isolation configuration bitfield. (access: R/W) +#define APB_SOC_CL_BYPASS_PROG_DEL_BIT 7 +#define APB_SOC_CL_BYPASS_PROG_DEL_WIDTH 2 +#define APB_SOC_CL_BYPASS_PROG_DEL_MASK 0x180 + +// Bypass cluster clock and reset control by Maestro PMU configuration bitfield: - 1b0: disabled - 1b1: enabled (access: R/W) +#define APB_SOC_CL_BYPASS_BYP_CLK_BIT 9 +#define APB_SOC_CL_BYPASS_BYP_CLK_WIDTH 1 +#define APB_SOC_CL_BYPASS_BYP_CLK_MASK 0x200 + +// Cluster clock gate configuration bitfield: - 1b0: disabled - 1b1: enabled It should always be used before switching cluster FLL to shutdown or retentive mode. (access: R/W) +#define APB_SOC_CL_BYPASS_CG_BIT 10 +#define APB_SOC_CL_BYPASS_CG_WIDTH 1 +#define APB_SOC_CL_BYPASS_CG_MASK 0x400 + +// Cluster FLL shutdown configuration bitfield: - 1b0: FLL on - 1b1: FLL shutdown mode (access: R/W) +#define APB_SOC_CL_BYPASS_FLL_PWD_BIT 11 +#define APB_SOC_CL_BYPASS_FLL_PWD_WIDTH 1 +#define APB_SOC_CL_BYPASS_FLL_PWD_MASK 0x800 + +// Cluster FLL retentive configuration bitfield: - 1b0: FLL on - 1b1: FLL retentive mode (access: R/W) +#define APB_SOC_CL_BYPASS_FLL_RET_BIT 12 +#define APB_SOC_CL_BYPASS_FLL_RET_WIDTH 1 +#define APB_SOC_CL_BYPASS_FLL_RET_MASK 0x1000 + +// Cluster reset configuration bitfield: - 1b0: nothing - 1b1: reset the cluster (access: R/W) +#define APB_SOC_CL_BYPASS_RST_BIT 13 +#define APB_SOC_CL_BYPASS_RST_WIDTH 1 +#define APB_SOC_CL_BYPASS_RST_MASK 0x2000 + +// ? (access: R/W) +#define APB_SOC_CL_BYPASS_BYP_ISO_BIT 14 +#define APB_SOC_CL_BYPASS_BYP_ISO_WIDTH 1 +#define APB_SOC_CL_BYPASS_BYP_ISO_MASK 0x4000 + +// ? (access: R/W) +#define APB_SOC_CL_BYPASS_PWISO_BIT 15 +#define APB_SOC_CL_BYPASS_PWISO_WIDTH 1 +#define APB_SOC_CL_BYPASS_PWISO_MASK 0x8000 + +// Cluster power ok from cluster TRC status bitfield (access: R/W) +#define APB_SOC_CL_BYPASS_TRCPOWOK_BIT 16 +#define APB_SOC_CL_BYPASS_TRCPOWOK_WIDTH 1 +#define APB_SOC_CL_BYPASS_TRCPOWOK_MASK 0x10000 + +// Cluster power down from Maestro PMU status bitfield. (access: R/W) +#define APB_SOC_CL_BYPASS_PMUPOWDOWN_BIT 17 +#define APB_SOC_CL_BYPASS_PMUPOWDOWN_WIDTH 1 +#define APB_SOC_CL_BYPASS_PMUPOWDOWN_MASK 0x20000 + +// JTAG internal register used for synchronisation from external debugger (access: R/W) +#define APB_SOC_JTAGREG_INT_SYNC_BIT 0 +#define APB_SOC_JTAGREG_INT_SYNC_WIDTH 1 +#define APB_SOC_JTAGREG_INT_SYNC_MASK 0x1 + +// JTAG internal register used for selecting boot mode configuration from external debugger (access: R/W) +#define APB_SOC_JTAGREG_INT_BT_MD_BIT 1 +#define APB_SOC_JTAGREG_INT_BT_MD_WIDTH 3 +#define APB_SOC_JTAGREG_INT_BT_MD_MASK 0xe + +// JTAG external register used for synchronisation from external debugger (access: R) +#define APB_SOC_JTAGREG_EXT_SYNC_BIT 8 +#define APB_SOC_JTAGREG_EXT_SYNC_WIDTH 1 +#define APB_SOC_JTAGREG_EXT_SYNC_MASK 0x100 + +// JTAG external register used for selecting boot mode configuration from external debugger (access: R) +#define APB_SOC_JTAGREG_EXT_BT_MD_BIT 9 +#define APB_SOC_JTAGREG_EXT_BT_MD_WIDTH 3 +#define APB_SOC_JTAGREG_EXT_BT_MD_MASK 0xe00 + +// L2 memory sleep configuration (access: R/W) +#define APB_SOC_L2_SLEEP_L2_SLEEP_BIT 0 +#define APB_SOC_L2_SLEEP_L2_SLEEP_WIDTH 1 +#define APB_SOC_L2_SLEEP_L2_SLEEP_MASK 0x1 + +// Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) (access: R) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT 0 +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH 32 +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_MASK 0xffffffff + +// EOC and chip status register (access: R/W) +#define APB_SOC_CORESTATUS_STATUS_BIT 0 +#define APB_SOC_CORESTATUS_STATUS_WIDTH 32 +#define APB_SOC_CORESTATUS_STATUS_MASK 0xffffffff + +// EOC and chip status register (access: R) +#define APB_SOC_CORESTATUS_RO_STATUS_BIT 0 +#define APB_SOC_CORESTATUS_RO_STATUS_WIDTH 32 +#define APB_SOC_CORESTATUS_RO_STATUS_MASK 0xffffffff + +// DC/DC Nominal Voltage setting (access: R/W) +#define APB_SOC_SAFE_PMU_RAR_NV_VOLT_BIT 0 +#define APB_SOC_SAFE_PMU_RAR_NV_VOLT_WIDTH 5 +#define APB_SOC_SAFE_PMU_RAR_NV_VOLT_MASK 0x1f + +// DC/DC Medium Voltage setting (not used) (access: R/W) +#define APB_SOC_SAFE_PMU_RAR_MV_VOLT_BIT 8 +#define APB_SOC_SAFE_PMU_RAR_MV_VOLT_WIDTH 5 +#define APB_SOC_SAFE_PMU_RAR_MV_VOLT_MASK 0x1f00 + +// DC/DC Low Voltage setting (access: R/W) +#define APB_SOC_SAFE_PMU_RAR_LV_VOLT_BIT 16 +#define APB_SOC_SAFE_PMU_RAR_LV_VOLT_WIDTH 5 +#define APB_SOC_SAFE_PMU_RAR_LV_VOLT_MASK 0x1f0000 + +// DC/DC Retentive Voltage setting (access: R/W) +#define APB_SOC_SAFE_PMU_RAR_RV_VOLT_BIT 24 +#define APB_SOC_SAFE_PMU_RAR_RV_VOLT_WIDTH 5 +#define APB_SOC_SAFE_PMU_RAR_RV_VOLT_MASK 0x1f000000 + +// Configure retention mode for region 0 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_BIT 0 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_MASK 0x1 + +// Configure retention mode for region 1 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_BIT 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_MASK 0x2 + +// Configure retention mode for region 2 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_BIT 2 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_MASK 0x4 + +// Configure retention mode for region 3 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_BIT 3 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_MASK 0x8 + +// Configure retention mode for SoC FLL: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_BIT 4 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_MASK 0x10 + +// Configure retention mode for cluster FLL: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_BIT 5 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_MASK 0x20 + +// Select external wake-up source (GPIO ID): - 5'b00000: GPIO 0 - 5'b00001: GPIO 1 - 5'b00010: GPIO 2 - 5'b00011: GPIO 3 - 5'b00100: GPIO 4 - 5'b00101: GPIO 5 - 5'b00110: GPIO 6 - 5'b00111: GPIO 7 - 5'b01000: GPIO 8 - 5'b01001: GPIO 9 - 5'b01010: GPIO 10 - 5'b01011: GPIO 11 - 5'b01100: GPIO 12 - 5'b01101: GPIO 13 - 5'b01110: GPIO 14 - 5'b01111: GPIO 15 - 5'b10000: GPIO 16 - 5'b10001: GPIO 17 - 5'b10010: GPIO 18 - 5'b10011: GPIO 19 - 5'b10100: GPIO 20 - 5'b10101: GPIO 21 - 5'b10110: GPIO 22 - 5'b10111: GPIO 23 - 5'b11000: GPIO 24 - 5'b11001: GPIO 25 - 5'b11010: GPIO 26 - 5'b11011: GPIO 27 - 5'b11100: GPIO 28 - 5'b11101: GPIO 29 - 5'b11110: GPIO 30 - 5'b11111: GPIO 31 (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_BIT 6 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_WIDTH 5 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_MASK 0x7c0 + +// Select external wake-up mode: - 2'b00: rise event - 2'b01: fall event - 2'b10: high level - 2'b11: low level (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT 11 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH 2 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_MASK 0x1800 + +// Enable external wake-up; - 1'b0; external wake-up disabled - 1'b1: external wake-up enabled (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT 13 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_MASK 0x2000 + +// - (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_BIT 15 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_MASK 0x8000 + +// Warm bootmode: - 1'b0: Boot from ROM - 1'b1: Boot from L2 (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_BIT 16 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_MASK 0x10000 + +// External wake-up interrupt status (automatically resetted after read) - 1'b0: wake-up triggered by RTC - 1'b1: wake-up triggered by external event (access: R) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_BIT 17 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_MASK 0x20000 + +// Select boot type: - 2'b00: cold boot - 2'b01: deep sleep - 2'b10: retentive deep sleep (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_BIT 18 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_WIDTH 2 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_MASK 0xc0000 + +// Cluster state to restore after warm boot: - 1b0: off - 1b1: on (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_BIT 20 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_MASK 0x100000 + +// Force retentive state on region 0 of L2 memory: 1'b0: not state retentive 1'b1: state retentive (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_BIT 0 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_MASK 0x1 + +// Force retentive state on region 1 of L2 memory: 1'b0: not state retentive 1'b1: state retentive (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_BIT 1 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_MASK 0x2 + +// Force retentive state on region 2 of L2 memory: 1'b0: not state retentive 1'b1: state retentive (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_BIT 2 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_MASK 0x4 + +// Force retentive state on region 3 of L2 memory: 1'b0: not state retentive 1'b1: state retentive (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_BIT 3 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_MASK 0x8 + +// Force power down on region 0 of L2 memory: 1'b0: power up 1'b1: power down (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_BIT 4 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_MASK 0x10 + +// Force power down on region 1 of L2 memory: 1'b0: power up 1'b1: power down (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_BIT 5 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_MASK 0x20 + +// Force power down on region 2 of L2 memory: 1'b0: power up 1'b1: power down (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_BIT 6 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_MASK 0x40 + +// Force power down on region 3 of L2 memory: 1'b0: power up 1'b1: power down (access: R/W) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_BIT 7 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_WIDTH 1 +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_MASK 0x80 + +// Enable pad sleep mode: 1'b0: disable 1'b1: enable (access: R/W) +#define APB_SOC_SAFE_PADSLEEP_EN_BIT 0 +#define APB_SOC_SAFE_PADSLEEP_EN_WIDTH 1 +#define APB_SOC_SAFE_PADSLEEP_EN_MASK 0x1 + +// Configuration of GPIO domain pads isolation: - 1'b0: not isolated - 1'b1: isolated (access: R/W) +#define APB_SOC_REG_GPIO_ISO_ISO_BIT 0 +#define APB_SOC_REG_GPIO_ISO_ISO_WIDTH 1 +#define APB_SOC_REG_GPIO_ISO_ISO_MASK 0x1 + +// Configuration of CAM domain pads isolation: - 1'b0: not isolated - 1'b1: isolated (access: R/W) +#define APB_SOC_REG_CAM_ISO_ISO_BIT 0 +#define APB_SOC_REG_CAM_ISO_ISO_WIDTH 1 +#define APB_SOC_REG_CAM_ISO_ISO_MASK 0x1 + +// Configuration of LVDS domain pads isolation: - 1'b0: not isolated - 1'b1: isolated (access: R/W) +#define APB_SOC_REG_LVDS_ISO_ISO_BIT 0 +#define APB_SOC_REG_LVDS_ISO_ISO_WIDTH 1 +#define APB_SOC_REG_LVDS_ISO_ISO_MASK 0x1 + + + +// +// REGISTERS STRUCTS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef union { + struct { + unsigned int nb_cl :16; // Number of clusters + unsigned int nb_cores :16; // Number of cores + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_info_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_notused0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_notused1_t; + +typedef union { + struct { + unsigned int en :1 ; // Isolate cluster. Inhibits AXI transactions from cluster to SoC: - 1'b0: Disable - 1'b1: Enable + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_cl_isolate_t; + +typedef union { + struct { + unsigned int busy :1 ; // Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_cl_busy_t; + +typedef union { + struct { + unsigned int byp_pow :1 ; // Bypass Maestro PMU controller configuration bitfield: - 1b0: disabled - 1b1: enabled + unsigned int byp_cfg :1 ; // Bypass Maestro PMU configuration selection configuration bitfield: - 1b0: use default - 1b1: use user configuration (bitfields from bits 3 to 15 of CL_BYPASS register) + unsigned int padding0:1 ; + unsigned int cl_state :1 ; // Cluster state configuration and status bitfield: - 1b0: off - 1b1: on Status information is correct only when bypass mode is enabled. + unsigned int currset :3 ; // Max current allowed on cluster TRC configuration bitfield. + unsigned int prog_del :2 ; // Number of REFCLK 32kHz after cluster power ok has arised to release TR isolation configuration bitfield. + unsigned int byp_clk :1 ; // Bypass cluster clock and reset control by Maestro PMU configuration bitfield: - 1b0: disabled - 1b1: enabled + unsigned int cg :1 ; // Cluster clock gate configuration bitfield: - 1b0: disabled - 1b1: enabled It should always be used before switching cluster FLL to shutdown or retentive mode. + unsigned int fll_pwd :1 ; // Cluster FLL shutdown configuration bitfield: - 1b0: FLL on - 1b1: FLL shutdown mode + unsigned int fll_ret :1 ; // Cluster FLL retentive configuration bitfield: - 1b0: FLL on - 1b1: FLL retentive mode + unsigned int rst :1 ; // Cluster reset configuration bitfield: - 1b0: nothing - 1b1: reset the cluster + unsigned int byp_iso :1 ; // ? + unsigned int pwiso :1 ; // ? + unsigned int trcpowok :1 ; // Cluster power ok from cluster TRC status bitfield + unsigned int pmupowdown :1 ; // Cluster power down from Maestro PMU status bitfield. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_cl_bypass_t; + +typedef union { + struct { + unsigned int int_sync :1 ; // JTAG internal register used for synchronisation from external debugger + unsigned int int_bt_md :3 ; // JTAG internal register used for selecting boot mode configuration from external debugger + unsigned int padding0:4 ; + unsigned int ext_sync :1 ; // JTAG external register used for synchronisation from external debugger + unsigned int ext_bt_md :3 ; // JTAG external register used for selecting boot mode configuration from external debugger + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_jtagreg_t; + +typedef union { + struct { + unsigned int l2_sleep :1 ; // L2 memory sleep configuration + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_l2_sleep_t; + +typedef union { + struct { + unsigned int sleep_ctrl :32; // Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_sleep_ctrl_t; + +typedef union { + struct { + unsigned int status :32; // EOC and chip status register + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_corestatus_t; + +typedef union { + struct { + unsigned int status :32; // EOC and chip status register + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_corestatus_ro_t; + +typedef union { + struct { + unsigned int nv_volt :5 ; // DC/DC Nominal Voltage setting + unsigned int padding0:3 ; + unsigned int mv_volt :5 ; // DC/DC Medium Voltage setting (not used) + unsigned int padding1:3 ; + unsigned int lv_volt :5 ; // DC/DC Low Voltage setting + unsigned int padding2:3 ; + unsigned int rv_volt :5 ; // DC/DC Retentive Voltage setting + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_pmu_rar_t; + +typedef union { + struct { + unsigned int l2_r0 :1 ; // Configure retention mode for region 0 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive + unsigned int l2_r1 :1 ; // Configure retention mode for region 1 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive + unsigned int l2_r2 :1 ; // Configure retention mode for region 2 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive + unsigned int l2_r3 :1 ; // Configure retention mode for region 3 of L2 memory: - 1'b0: Non retentive - 1'b1: Retentive + unsigned int soc_fll :1 ; // Configure retention mode for SoC FLL: - 1'b0: Non retentive - 1'b1: Retentive + unsigned int cl_fll :1 ; // Configure retention mode for cluster FLL: - 1'b0: Non retentive - 1'b1: Retentive + unsigned int extwake_src :5 ; // Select external wake-up source (GPIO ID): - 5'b00000: GPIO 0 - 5'b00001: GPIO 1 - 5'b00010: GPIO 2 - 5'b00011: GPIO 3 - 5'b00100: GPIO 4 - 5'b00101: GPIO 5 - 5'b00110: GPIO 6 - 5'b00111: GPIO 7 - 5'b01000: GPIO 8 - 5'b01001: GPIO 9 - 5'b01010: GPIO 10 - 5'b01011: GPIO 11 - 5'b01100: GPIO 12 - 5'b01101: GPIO 13 - 5'b01110: GPIO 14 - 5'b01111: GPIO 15 - 5'b10000: GPIO 16 - 5'b10001: GPIO 17 - 5'b10010: GPIO 18 - 5'b10011: GPIO 19 - 5'b10100: GPIO 20 - 5'b10101: GPIO 21 - 5'b10110: GPIO 22 - 5'b10111: GPIO 23 - 5'b11000: GPIO 24 - 5'b11001: GPIO 25 - 5'b11010: GPIO 26 - 5'b11011: GPIO 27 - 5'b11100: GPIO 28 - 5'b11101: GPIO 29 - 5'b11110: GPIO 30 - 5'b11111: GPIO 31 + unsigned int extwake_type :2 ; // Select external wake-up mode: - 2'b00: rise event - 2'b01: fall event - 2'b10: high level - 2'b11: low level + unsigned int extwake_en :1 ; // Enable external wake-up; - 1'b0; external wake-up disabled - 1'b1: external wake-up enabled + unsigned int padding0:1 ; + unsigned int wakestate :1 ; // - + unsigned int btdev :1 ; // Warm bootmode: - 1'b0: Boot from ROM - 1'b1: Boot from L2 + unsigned int extint :1 ; // External wake-up interrupt status (automatically resetted after read) - 1'b0: wake-up triggered by RTC - 1'b1: wake-up triggered by external event + unsigned int bttype :2 ; // Select boot type: - 2'b00: cold boot - 2'b01: deep sleep - 2'b10: retentive deep sleep + unsigned int cl_wake :1 ; // Cluster state to restore after warm boot: - 1b0: off - 1b1: on + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_pmu_sleepctrl_t; + +typedef union { + struct { + unsigned int ret_l2_r0 :1 ; // Force retentive state on region 0 of L2 memory: 1'b0: not state retentive 1'b1: state retentive + unsigned int ret_l2_r1 :1 ; // Force retentive state on region 1 of L2 memory: 1'b0: not state retentive 1'b1: state retentive + unsigned int ret_l2_r2 :1 ; // Force retentive state on region 2 of L2 memory: 1'b0: not state retentive 1'b1: state retentive + unsigned int ret_l2_r3 :1 ; // Force retentive state on region 3 of L2 memory: 1'b0: not state retentive 1'b1: state retentive + unsigned int pd_l2_r0 :1 ; // Force power down on region 0 of L2 memory: 1'b0: power up 1'b1: power down + unsigned int pd_l2_r1 :1 ; // Force power down on region 1 of L2 memory: 1'b0: power up 1'b1: power down + unsigned int pd_l2_r2 :1 ; // Force power down on region 2 of L2 memory: 1'b0: power up 1'b1: power down + unsigned int pd_l2_r3 :1 ; // Force power down on region 3 of L2 memory: 1'b0: power up 1'b1: power down + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_pmu_force_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padfun0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padfun1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padfun2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padfun3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg3_t; + +typedef union { + struct { + unsigned int en :1 ; // Enable pad sleep mode: 1'b0: disable 1'b1: enable + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padsleep_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg4_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg5_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg6_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg7_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg8_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg9_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg10_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg11_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg12_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg13_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg14_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_padcfg15_t; + +typedef union { + struct { + unsigned int iso :1 ; // Configuration of GPIO domain pads isolation: - 1'b0: not isolated - 1'b1: isolated + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_gpio_iso_t; + +typedef union { + struct { + unsigned int iso :1 ; // Configuration of CAM domain pads isolation: - 1'b0: not isolated - 1'b1: isolated + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_cam_iso_t; + +typedef union { + struct { + unsigned int iso :1 ; // Configuration of LVDS domain pads isolation: - 1'b0: not isolated - 1'b1: isolated + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_lvds_iso_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_apb_soc_info : public vp::reg_32 +{ +public: + inline void nb_cl_set(uint32_t value) { this->set_field(value, APB_SOC_INFO_NB_CL_BIT, APB_SOC_INFO_NB_CL_WIDTH); } + inline uint32_t nb_cl_get() { return this->get_field(APB_SOC_INFO_NB_CL_BIT, APB_SOC_INFO_NB_CL_WIDTH); } + inline void nb_cores_set(uint32_t value) { this->set_field(value, APB_SOC_INFO_NB_CORES_BIT, APB_SOC_INFO_NB_CORES_WIDTH); } + inline uint32_t nb_cores_get() { return this->get_field(APB_SOC_INFO_NB_CORES_BIT, APB_SOC_INFO_NB_CORES_WIDTH); } +}; + +class vp_apb_soc_notused0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_notused1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_cl_isolate : public vp::reg_32 +{ +public: + inline void en_set(uint32_t value) { this->set_field(value, APB_SOC_CL_ISOLATE_EN_BIT, APB_SOC_CL_ISOLATE_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(APB_SOC_CL_ISOLATE_EN_BIT, APB_SOC_CL_ISOLATE_EN_WIDTH); } +}; + +class vp_apb_soc_cl_busy : public vp::reg_32 +{ +public: + inline void busy_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BUSY_BUSY_BIT, APB_SOC_CL_BUSY_BUSY_WIDTH); } + inline uint32_t busy_get() { return this->get_field(APB_SOC_CL_BUSY_BUSY_BIT, APB_SOC_CL_BUSY_BUSY_WIDTH); } +}; + +class vp_apb_soc_cl_bypass : public vp::reg_32 +{ +public: + inline void byp_pow_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_BYP_POW_BIT, APB_SOC_CL_BYPASS_BYP_POW_WIDTH); } + inline uint32_t byp_pow_get() { return this->get_field(APB_SOC_CL_BYPASS_BYP_POW_BIT, APB_SOC_CL_BYPASS_BYP_POW_WIDTH); } + inline void byp_cfg_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_BYP_CFG_BIT, APB_SOC_CL_BYPASS_BYP_CFG_WIDTH); } + inline uint32_t byp_cfg_get() { return this->get_field(APB_SOC_CL_BYPASS_BYP_CFG_BIT, APB_SOC_CL_BYPASS_BYP_CFG_WIDTH); } + inline void cl_state_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_CL_STATE_BIT, APB_SOC_CL_BYPASS_CL_STATE_WIDTH); } + inline uint32_t cl_state_get() { return this->get_field(APB_SOC_CL_BYPASS_CL_STATE_BIT, APB_SOC_CL_BYPASS_CL_STATE_WIDTH); } + inline void currset_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_CURRSET_BIT, APB_SOC_CL_BYPASS_CURRSET_WIDTH); } + inline uint32_t currset_get() { return this->get_field(APB_SOC_CL_BYPASS_CURRSET_BIT, APB_SOC_CL_BYPASS_CURRSET_WIDTH); } + inline void prog_del_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_PROG_DEL_BIT, APB_SOC_CL_BYPASS_PROG_DEL_WIDTH); } + inline uint32_t prog_del_get() { return this->get_field(APB_SOC_CL_BYPASS_PROG_DEL_BIT, APB_SOC_CL_BYPASS_PROG_DEL_WIDTH); } + inline void byp_clk_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_BYP_CLK_BIT, APB_SOC_CL_BYPASS_BYP_CLK_WIDTH); } + inline uint32_t byp_clk_get() { return this->get_field(APB_SOC_CL_BYPASS_BYP_CLK_BIT, APB_SOC_CL_BYPASS_BYP_CLK_WIDTH); } + inline void cg_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_CG_BIT, APB_SOC_CL_BYPASS_CG_WIDTH); } + inline uint32_t cg_get() { return this->get_field(APB_SOC_CL_BYPASS_CG_BIT, APB_SOC_CL_BYPASS_CG_WIDTH); } + inline void fll_pwd_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_FLL_PWD_BIT, APB_SOC_CL_BYPASS_FLL_PWD_WIDTH); } + inline uint32_t fll_pwd_get() { return this->get_field(APB_SOC_CL_BYPASS_FLL_PWD_BIT, APB_SOC_CL_BYPASS_FLL_PWD_WIDTH); } + inline void fll_ret_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_FLL_RET_BIT, APB_SOC_CL_BYPASS_FLL_RET_WIDTH); } + inline uint32_t fll_ret_get() { return this->get_field(APB_SOC_CL_BYPASS_FLL_RET_BIT, APB_SOC_CL_BYPASS_FLL_RET_WIDTH); } + inline void rst_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_RST_BIT, APB_SOC_CL_BYPASS_RST_WIDTH); } + inline uint32_t rst_get() { return this->get_field(APB_SOC_CL_BYPASS_RST_BIT, APB_SOC_CL_BYPASS_RST_WIDTH); } + inline void byp_iso_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_BYP_ISO_BIT, APB_SOC_CL_BYPASS_BYP_ISO_WIDTH); } + inline uint32_t byp_iso_get() { return this->get_field(APB_SOC_CL_BYPASS_BYP_ISO_BIT, APB_SOC_CL_BYPASS_BYP_ISO_WIDTH); } + inline void pwiso_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_PWISO_BIT, APB_SOC_CL_BYPASS_PWISO_WIDTH); } + inline uint32_t pwiso_get() { return this->get_field(APB_SOC_CL_BYPASS_PWISO_BIT, APB_SOC_CL_BYPASS_PWISO_WIDTH); } + inline void trcpowok_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_TRCPOWOK_BIT, APB_SOC_CL_BYPASS_TRCPOWOK_WIDTH); } + inline uint32_t trcpowok_get() { return this->get_field(APB_SOC_CL_BYPASS_TRCPOWOK_BIT, APB_SOC_CL_BYPASS_TRCPOWOK_WIDTH); } + inline void pmupowdown_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BYPASS_PMUPOWDOWN_BIT, APB_SOC_CL_BYPASS_PMUPOWDOWN_WIDTH); } + inline uint32_t pmupowdown_get() { return this->get_field(APB_SOC_CL_BYPASS_PMUPOWDOWN_BIT, APB_SOC_CL_BYPASS_PMUPOWDOWN_WIDTH); } +}; + +class vp_apb_soc_jtagreg : public vp::reg_32 +{ +public: + inline void int_sync_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_INT_SYNC_BIT, APB_SOC_JTAGREG_INT_SYNC_WIDTH); } + inline uint32_t int_sync_get() { return this->get_field(APB_SOC_JTAGREG_INT_SYNC_BIT, APB_SOC_JTAGREG_INT_SYNC_WIDTH); } + inline void int_bt_md_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_INT_BT_MD_BIT, APB_SOC_JTAGREG_INT_BT_MD_WIDTH); } + inline uint32_t int_bt_md_get() { return this->get_field(APB_SOC_JTAGREG_INT_BT_MD_BIT, APB_SOC_JTAGREG_INT_BT_MD_WIDTH); } + inline void ext_sync_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_EXT_SYNC_BIT, APB_SOC_JTAGREG_EXT_SYNC_WIDTH); } + inline uint32_t ext_sync_get() { return this->get_field(APB_SOC_JTAGREG_EXT_SYNC_BIT, APB_SOC_JTAGREG_EXT_SYNC_WIDTH); } + inline void ext_bt_md_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_EXT_BT_MD_BIT, APB_SOC_JTAGREG_EXT_BT_MD_WIDTH); } + inline uint32_t ext_bt_md_get() { return this->get_field(APB_SOC_JTAGREG_EXT_BT_MD_BIT, APB_SOC_JTAGREG_EXT_BT_MD_WIDTH); } +}; + +class vp_apb_soc_l2_sleep : public vp::reg_32 +{ +public: + inline void l2_sleep_set(uint32_t value) { this->set_field(value, APB_SOC_L2_SLEEP_L2_SLEEP_BIT, APB_SOC_L2_SLEEP_L2_SLEEP_WIDTH); } + inline uint32_t l2_sleep_get() { return this->get_field(APB_SOC_L2_SLEEP_L2_SLEEP_BIT, APB_SOC_L2_SLEEP_L2_SLEEP_WIDTH); } +}; + +class vp_apb_soc_sleep_ctrl : public vp::reg_32 +{ +public: + inline void sleep_ctrl_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH); } + inline uint32_t sleep_ctrl_get() { return this->get_field(APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH); } +}; + +class vp_apb_soc_corestatus : public vp::reg_32 +{ +public: + inline void status_set(uint32_t value) { this->set_field(value, APB_SOC_CORESTATUS_STATUS_BIT, APB_SOC_CORESTATUS_STATUS_WIDTH); } + inline uint32_t status_get() { return this->get_field(APB_SOC_CORESTATUS_STATUS_BIT, APB_SOC_CORESTATUS_STATUS_WIDTH); } +}; + +class vp_apb_soc_corestatus_ro : public vp::reg_32 +{ +public: + inline void status_set(uint32_t value) { this->set_field(value, APB_SOC_CORESTATUS_RO_STATUS_BIT, APB_SOC_CORESTATUS_RO_STATUS_WIDTH); } + inline uint32_t status_get() { return this->get_field(APB_SOC_CORESTATUS_RO_STATUS_BIT, APB_SOC_CORESTATUS_RO_STATUS_WIDTH); } +}; + +class vp_apb_soc_safe_pmu_rar : public vp::reg_32 +{ +public: + inline void nv_volt_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_RAR_NV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_NV_VOLT_WIDTH); } + inline uint32_t nv_volt_get() { return this->get_field(APB_SOC_SAFE_PMU_RAR_NV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_NV_VOLT_WIDTH); } + inline void mv_volt_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_RAR_MV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_MV_VOLT_WIDTH); } + inline uint32_t mv_volt_get() { return this->get_field(APB_SOC_SAFE_PMU_RAR_MV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_MV_VOLT_WIDTH); } + inline void lv_volt_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_RAR_LV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_LV_VOLT_WIDTH); } + inline uint32_t lv_volt_get() { return this->get_field(APB_SOC_SAFE_PMU_RAR_LV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_LV_VOLT_WIDTH); } + inline void rv_volt_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_RAR_RV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_RV_VOLT_WIDTH); } + inline uint32_t rv_volt_get() { return this->get_field(APB_SOC_SAFE_PMU_RAR_RV_VOLT_BIT, APB_SOC_SAFE_PMU_RAR_RV_VOLT_WIDTH); } +}; + +class vp_apb_soc_safe_pmu_sleepctrl : public vp::reg_32 +{ +public: + inline void l2_r0_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_WIDTH); } + inline uint32_t l2_r0_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_WIDTH); } + inline void l2_r1_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_WIDTH); } + inline uint32_t l2_r1_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_WIDTH); } + inline void l2_r2_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_WIDTH); } + inline uint32_t l2_r2_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_WIDTH); } + inline void l2_r3_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_WIDTH); } + inline uint32_t l2_r3_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_WIDTH); } + inline void soc_fll_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_WIDTH); } + inline uint32_t soc_fll_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_WIDTH); } + inline void cl_fll_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_WIDTH); } + inline uint32_t cl_fll_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_WIDTH); } + inline void extwake_src_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_WIDTH); } + inline uint32_t extwake_src_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_WIDTH); } + inline void extwake_type_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH); } + inline uint32_t extwake_type_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH); } + inline void extwake_en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH); } + inline uint32_t extwake_en_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH); } + inline void wakestate_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_WIDTH); } + inline uint32_t wakestate_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_WIDTH); } + inline void btdev_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_WIDTH); } + inline uint32_t btdev_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_WIDTH); } + inline void extint_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_WIDTH); } + inline uint32_t extint_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_WIDTH); } + inline void bttype_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_WIDTH); } + inline uint32_t bttype_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_WIDTH); } + inline void cl_wake_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_WIDTH); } + inline uint32_t cl_wake_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_WIDTH); } +}; + +class vp_apb_soc_safe_pmu_force : public vp::reg_32 +{ +public: + inline void ret_l2_r0_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_WIDTH); } + inline uint32_t ret_l2_r0_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_WIDTH); } + inline void ret_l2_r1_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_WIDTH); } + inline uint32_t ret_l2_r1_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_WIDTH); } + inline void ret_l2_r2_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_WIDTH); } + inline uint32_t ret_l2_r2_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_WIDTH); } + inline void ret_l2_r3_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_WIDTH); } + inline uint32_t ret_l2_r3_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_BIT, APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_WIDTH); } + inline void pd_l2_r0_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_WIDTH); } + inline uint32_t pd_l2_r0_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_WIDTH); } + inline void pd_l2_r1_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_WIDTH); } + inline uint32_t pd_l2_r1_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_WIDTH); } + inline void pd_l2_r2_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_WIDTH); } + inline uint32_t pd_l2_r2_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_WIDTH); } + inline void pd_l2_r3_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_WIDTH); } + inline uint32_t pd_l2_r3_get() { return this->get_field(APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_BIT, APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_WIDTH); } +}; + +class vp_apb_soc_safe_padfun0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padfun1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padfun2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padfun3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_sleeppadcfg0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_sleeppadcfg1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_sleeppadcfg2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_sleeppadcfg3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padsleep : public vp::reg_32 +{ +public: + inline void en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PADSLEEP_EN_BIT, APB_SOC_SAFE_PADSLEEP_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(APB_SOC_SAFE_PADSLEEP_EN_BIT, APB_SOC_SAFE_PADSLEEP_EN_WIDTH); } +}; + +class vp_apb_soc_safe_padcfg0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg4 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg5 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg6 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg7 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg8 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg9 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg10 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg11 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg12 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg13 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg14 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_padcfg15 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_reg_gpio_iso : public vp::reg_32 +{ +public: + inline void iso_set(uint32_t value) { this->set_field(value, APB_SOC_REG_GPIO_ISO_ISO_BIT, APB_SOC_REG_GPIO_ISO_ISO_WIDTH); } + inline uint32_t iso_get() { return this->get_field(APB_SOC_REG_GPIO_ISO_ISO_BIT, APB_SOC_REG_GPIO_ISO_ISO_WIDTH); } +}; + +class vp_apb_soc_reg_cam_iso : public vp::reg_32 +{ +public: + inline void iso_set(uint32_t value) { this->set_field(value, APB_SOC_REG_CAM_ISO_ISO_BIT, APB_SOC_REG_CAM_ISO_ISO_WIDTH); } + inline uint32_t iso_get() { return this->get_field(APB_SOC_REG_CAM_ISO_ISO_BIT, APB_SOC_REG_CAM_ISO_ISO_WIDTH); } +}; + +class vp_apb_soc_reg_lvds_iso : public vp::reg_32 +{ +public: + inline void iso_set(uint32_t value) { this->set_field(value, APB_SOC_REG_LVDS_ISO_ISO_BIT, APB_SOC_REG_LVDS_ISO_ISO_WIDTH); } + inline uint32_t iso_get() { return this->get_field(APB_SOC_REG_LVDS_ISO_ISO_BIT, APB_SOC_REG_LVDS_ISO_ISO_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef struct { + unsigned int info ; // Core information register + unsigned int notused0 ; // RFU + unsigned int notused1 ; // RFU + unsigned int cl_isolate ; // Isolate cluster register + unsigned int cl_busy ; // Cluster busy register + unsigned int cl_bypass ; // PMU bypass configuration register + unsigned int jtagreg ; // JTAG external register + unsigned int l2_sleep ; // L2 sleep configuration register + unsigned int sleep_ctrl ; // Alias for SAFE_PMU_SLEEPCTRL + unsigned int corestatus ; // EOC and chip status register + unsigned int corestatus_ro ; // EOC and chip status register read mirror + unsigned int safe_pmu_rar ; // DC/DC configuration register + unsigned int safe_pmu_sleepctrl; // Sleep modes configuration register + unsigned int safe_pmu_force ; // L2 rententive state configuration + unsigned int safe_padfun0 ; // Mux config register (pad 0-15) + unsigned int safe_padfun1 ; // Mux config register (pad 16-31) + unsigned int safe_padfun2 ; // Mux config register (pad 32-47) + unsigned int safe_padfun3 ; // Mux config register (pad 48-63) + unsigned int safe_sleeppadcfg0; // Sleep config register (pad 0-15) + unsigned int safe_sleeppadcfg1; // Mux config register (pad 16-31) + unsigned int safe_sleeppadcfg2; // Mux config register (pad 32-47) + unsigned int safe_sleeppadcfg3; // Mux config register (pad 48-63) + unsigned int safe_padsleep ; // Enable Sleep mode for pads + unsigned int safe_padcfg0 ; // Function register (pad 0 to 3) + unsigned int safe_padcfg1 ; // Function register (pad 4 to 7) + unsigned int safe_padcfg2 ; // Function register (pad 8 to 11) + unsigned int safe_padcfg3 ; // Function register (pad 12 to 15) + unsigned int safe_padcfg4 ; // Function register (pad 16 to 19) + unsigned int safe_padcfg5 ; // Function register (pad 20 to 23) + unsigned int safe_padcfg6 ; // Function register (pad 24 to 27) + unsigned int safe_padcfg7 ; // Function register (pad 28 to 31) + unsigned int safe_padcfg8 ; // Function register (pad 32 to 35) + unsigned int safe_padcfg9 ; // Function register (pad 36 to 39) + unsigned int safe_padcfg10 ; // Function register (pad 40 to 43) + unsigned int safe_padcfg11 ; // Function register (pad 44 to 47) + unsigned int safe_padcfg12 ; // Function register (pad 48 to 51) + unsigned int safe_padcfg13 ; // Function register (pad 52 to 55) + unsigned int safe_padcfg14 ; // Function register (pad 56 to 59) + unsigned int safe_padcfg15 ; // Function register (pad 60 to 63) + unsigned int reg_gpio_iso ; // GPIO power domain pad input isolation register + unsigned int reg_cam_iso ; // CAM power domain pad input isolation register + unsigned int reg_lvds_iso ; // LVDS power domain pad input isolation register +} __attribute__((packed)) apb_soc_apb_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +static inline uint32_t apb_soc_info_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_INFO_OFFSET); } +static inline void apb_soc_info_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_INFO_OFFSET, value); } + +static inline uint32_t apb_soc_notused0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_NOTUSED0_OFFSET); } +static inline void apb_soc_notused0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_NOTUSED0_OFFSET, value); } + +static inline uint32_t apb_soc_notused1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_NOTUSED1_OFFSET); } +static inline void apb_soc_notused1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_NOTUSED1_OFFSET, value); } + +static inline uint32_t apb_soc_cl_isolate_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CL_ISOLATE_OFFSET); } +static inline void apb_soc_cl_isolate_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CL_ISOLATE_OFFSET, value); } + +static inline uint32_t apb_soc_cl_busy_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CL_BUSY_OFFSET); } +static inline void apb_soc_cl_busy_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CL_BUSY_OFFSET, value); } + +static inline uint32_t apb_soc_cl_bypass_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CL_BYPASS_OFFSET); } +static inline void apb_soc_cl_bypass_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CL_BYPASS_OFFSET, value); } + +static inline uint32_t apb_soc_jtagreg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_JTAGREG_OFFSET); } +static inline void apb_soc_jtagreg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_JTAGREG_OFFSET, value); } + +static inline uint32_t apb_soc_l2_sleep_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_L2_SLEEP_OFFSET); } +static inline void apb_soc_l2_sleep_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_L2_SLEEP_OFFSET, value); } + +static inline uint32_t apb_soc_sleep_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SLEEP_CTRL_OFFSET); } +static inline void apb_soc_sleep_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SLEEP_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_corestatus_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CORESTATUS_OFFSET); } +static inline void apb_soc_corestatus_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CORESTATUS_OFFSET, value); } + +static inline uint32_t apb_soc_corestatus_ro_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CORESTATUS_RO_OFFSET); } +static inline void apb_soc_corestatus_ro_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CORESTATUS_RO_OFFSET, value); } + +static inline uint32_t apb_soc_safe_pmu_rar_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PMU_RAR_OFFSET); } +static inline void apb_soc_safe_pmu_rar_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PMU_RAR_OFFSET, value); } + +static inline uint32_t apb_soc_safe_pmu_sleepctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET); } +static inline void apb_soc_safe_pmu_sleepctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET, value); } + +static inline uint32_t apb_soc_safe_pmu_force_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PMU_FORCE_OFFSET); } +static inline void apb_soc_safe_pmu_force_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PMU_FORCE_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padfun0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADFUN0_OFFSET); } +static inline void apb_soc_safe_padfun0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADFUN0_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padfun1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADFUN1_OFFSET); } +static inline void apb_soc_safe_padfun1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADFUN1_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padfun2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADFUN2_OFFSET); } +static inline void apb_soc_safe_padfun2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADFUN2_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padfun3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADFUN3_OFFSET); } +static inline void apb_soc_safe_padfun3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADFUN3_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG0_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG0_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG1_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG1_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG2_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG2_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG3_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG3_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padsleep_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADSLEEP_OFFSET); } +static inline void apb_soc_safe_padsleep_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADSLEEP_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG0_OFFSET); } +static inline void apb_soc_safe_padcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG0_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG1_OFFSET); } +static inline void apb_soc_safe_padcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG1_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG2_OFFSET); } +static inline void apb_soc_safe_padcfg2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG2_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG3_OFFSET); } +static inline void apb_soc_safe_padcfg3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG3_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg4_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG4_OFFSET); } +static inline void apb_soc_safe_padcfg4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG4_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg5_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG5_OFFSET); } +static inline void apb_soc_safe_padcfg5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG5_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg6_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG6_OFFSET); } +static inline void apb_soc_safe_padcfg6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG6_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg7_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG7_OFFSET); } +static inline void apb_soc_safe_padcfg7_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG7_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg8_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG8_OFFSET); } +static inline void apb_soc_safe_padcfg8_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG8_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg9_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG9_OFFSET); } +static inline void apb_soc_safe_padcfg9_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG9_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg10_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG10_OFFSET); } +static inline void apb_soc_safe_padcfg10_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG10_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg11_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG11_OFFSET); } +static inline void apb_soc_safe_padcfg11_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG11_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg12_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG12_OFFSET); } +static inline void apb_soc_safe_padcfg12_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG12_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg13_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG13_OFFSET); } +static inline void apb_soc_safe_padcfg13_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG13_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg14_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG14_OFFSET); } +static inline void apb_soc_safe_padcfg14_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG14_OFFSET, value); } + +static inline uint32_t apb_soc_safe_padcfg15_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PADCFG15_OFFSET); } +static inline void apb_soc_safe_padcfg15_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PADCFG15_OFFSET, value); } + +static inline uint32_t apb_soc_reg_gpio_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_GPIO_ISO_OFFSET); } +static inline void apb_soc_reg_gpio_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_GPIO_ISO_OFFSET, value); } + +static inline uint32_t apb_soc_reg_cam_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_CAM_ISO_OFFSET); } +static inline void apb_soc_reg_cam_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_CAM_ISO_OFFSET, value); } + +static inline uint32_t apb_soc_reg_lvds_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_LVDS_ISO_OFFSET); } +static inline void apb_soc_reg_lvds_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_LVDS_ISO_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#define APB_SOC_INFO_NB_CL_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define APB_SOC_INFO_NB_CL_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define APB_SOC_INFO_NB_CL_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define APB_SOC_INFO_NB_CL(val) ((val) << 0) + +#define APB_SOC_INFO_NB_CORES_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define APB_SOC_INFO_NB_CORES_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define APB_SOC_INFO_NB_CORES_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define APB_SOC_INFO_NB_CORES(val) ((val) << 16) + +#define APB_SOC_CL_ISOLATE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CL_ISOLATE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CL_ISOLATE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CL_ISOLATE_EN(val) ((val) << 0) + +#define APB_SOC_CL_BUSY_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CL_BUSY_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CL_BUSY_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CL_BUSY_BUSY(val) ((val) << 0) + +#define APB_SOC_CL_BYPASS_BYP_POW_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CL_BYPASS_BYP_POW_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CL_BYPASS_BYP_POW_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CL_BYPASS_BYP_POW(val) ((val) << 0) + +#define APB_SOC_CL_BYPASS_BYP_CFG_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define APB_SOC_CL_BYPASS_BYP_CFG_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define APB_SOC_CL_BYPASS_BYP_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define APB_SOC_CL_BYPASS_BYP_CFG(val) ((val) << 1) + +#define APB_SOC_CL_BYPASS_CL_STATE_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define APB_SOC_CL_BYPASS_CL_STATE_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define APB_SOC_CL_BYPASS_CL_STATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define APB_SOC_CL_BYPASS_CL_STATE(val) ((val) << 3) + +#define APB_SOC_CL_BYPASS_CURRSET_GET(value) (ARCHI_BEXTRACTU((value),3,4)) +#define APB_SOC_CL_BYPASS_CURRSET_GETS(value) (ARCHI_BEXTRACT((value),3,4)) +#define APB_SOC_CL_BYPASS_CURRSET_SET(value,field) (ARCHI_BINSERT((value),(field),3,4)) +#define APB_SOC_CL_BYPASS_CURRSET(val) ((val) << 4) + +#define APB_SOC_CL_BYPASS_PROG_DEL_GET(value) (ARCHI_BEXTRACTU((value),2,7)) +#define APB_SOC_CL_BYPASS_PROG_DEL_GETS(value) (ARCHI_BEXTRACT((value),2,7)) +#define APB_SOC_CL_BYPASS_PROG_DEL_SET(value,field) (ARCHI_BINSERT((value),(field),2,7)) +#define APB_SOC_CL_BYPASS_PROG_DEL(val) ((val) << 7) + +#define APB_SOC_CL_BYPASS_BYP_CLK_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define APB_SOC_CL_BYPASS_BYP_CLK_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define APB_SOC_CL_BYPASS_BYP_CLK_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define APB_SOC_CL_BYPASS_BYP_CLK(val) ((val) << 9) + +#define APB_SOC_CL_BYPASS_CG_GET(value) (ARCHI_BEXTRACTU((value),1,10)) +#define APB_SOC_CL_BYPASS_CG_GETS(value) (ARCHI_BEXTRACT((value),1,10)) +#define APB_SOC_CL_BYPASS_CG_SET(value,field) (ARCHI_BINSERT((value),(field),1,10)) +#define APB_SOC_CL_BYPASS_CG(val) ((val) << 10) + +#define APB_SOC_CL_BYPASS_FLL_PWD_GET(value) (ARCHI_BEXTRACTU((value),1,11)) +#define APB_SOC_CL_BYPASS_FLL_PWD_GETS(value) (ARCHI_BEXTRACT((value),1,11)) +#define APB_SOC_CL_BYPASS_FLL_PWD_SET(value,field) (ARCHI_BINSERT((value),(field),1,11)) +#define APB_SOC_CL_BYPASS_FLL_PWD(val) ((val) << 11) + +#define APB_SOC_CL_BYPASS_FLL_RET_GET(value) (ARCHI_BEXTRACTU((value),1,12)) +#define APB_SOC_CL_BYPASS_FLL_RET_GETS(value) (ARCHI_BEXTRACT((value),1,12)) +#define APB_SOC_CL_BYPASS_FLL_RET_SET(value,field) (ARCHI_BINSERT((value),(field),1,12)) +#define APB_SOC_CL_BYPASS_FLL_RET(val) ((val) << 12) + +#define APB_SOC_CL_BYPASS_RST_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define APB_SOC_CL_BYPASS_RST_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define APB_SOC_CL_BYPASS_RST_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define APB_SOC_CL_BYPASS_RST(val) ((val) << 13) + +#define APB_SOC_CL_BYPASS_BYP_ISO_GET(value) (ARCHI_BEXTRACTU((value),1,14)) +#define APB_SOC_CL_BYPASS_BYP_ISO_GETS(value) (ARCHI_BEXTRACT((value),1,14)) +#define APB_SOC_CL_BYPASS_BYP_ISO_SET(value,field) (ARCHI_BINSERT((value),(field),1,14)) +#define APB_SOC_CL_BYPASS_BYP_ISO(val) ((val) << 14) + +#define APB_SOC_CL_BYPASS_PWISO_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define APB_SOC_CL_BYPASS_PWISO_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define APB_SOC_CL_BYPASS_PWISO_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define APB_SOC_CL_BYPASS_PWISO(val) ((val) << 15) + +#define APB_SOC_CL_BYPASS_TRCPOWOK_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define APB_SOC_CL_BYPASS_TRCPOWOK_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define APB_SOC_CL_BYPASS_TRCPOWOK_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define APB_SOC_CL_BYPASS_TRCPOWOK(val) ((val) << 16) + +#define APB_SOC_CL_BYPASS_PMUPOWDOWN_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define APB_SOC_CL_BYPASS_PMUPOWDOWN_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define APB_SOC_CL_BYPASS_PMUPOWDOWN_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define APB_SOC_CL_BYPASS_PMUPOWDOWN(val) ((val) << 17) + +#define APB_SOC_JTAGREG_INT_SYNC_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC(val) ((val) << 0) + +#define APB_SOC_JTAGREG_INT_BT_MD_GET(value) (ARCHI_BEXTRACTU((value),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD_GETS(value) (ARCHI_BEXTRACT((value),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD_SET(value,field) (ARCHI_BINSERT((value),(field),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD(val) ((val) << 1) + +#define APB_SOC_JTAGREG_EXT_SYNC_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC(val) ((val) << 8) + +#define APB_SOC_JTAGREG_EXT_BT_MD_GET(value) (ARCHI_BEXTRACTU((value),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD_GETS(value) (ARCHI_BEXTRACT((value),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD_SET(value,field) (ARCHI_BINSERT((value),(field),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD(val) ((val) << 9) + +#define APB_SOC_L2_SLEEP_L2_SLEEP_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_L2_SLEEP_L2_SLEEP_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_L2_SLEEP_L2_SLEEP_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_L2_SLEEP_L2_SLEEP(val) ((val) << 0) + +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL(val) ((val) << 0) + +#define APB_SOC_CORESTATUS_STATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_CORESTATUS_STATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_CORESTATUS_STATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_CORESTATUS_STATUS(val) ((val) << 0) + +#define APB_SOC_CORESTATUS_RO_STATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS(val) ((val) << 0) + +#define APB_SOC_SAFE_PMU_RAR_NV_VOLT_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define APB_SOC_SAFE_PMU_RAR_NV_VOLT_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define APB_SOC_SAFE_PMU_RAR_NV_VOLT_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define APB_SOC_SAFE_PMU_RAR_NV_VOLT(val) ((val) << 0) + +#define APB_SOC_SAFE_PMU_RAR_MV_VOLT_GET(value) (ARCHI_BEXTRACTU((value),5,8)) +#define APB_SOC_SAFE_PMU_RAR_MV_VOLT_GETS(value) (ARCHI_BEXTRACT((value),5,8)) +#define APB_SOC_SAFE_PMU_RAR_MV_VOLT_SET(value,field) (ARCHI_BINSERT((value),(field),5,8)) +#define APB_SOC_SAFE_PMU_RAR_MV_VOLT(val) ((val) << 8) + +#define APB_SOC_SAFE_PMU_RAR_LV_VOLT_GET(value) (ARCHI_BEXTRACTU((value),5,16)) +#define APB_SOC_SAFE_PMU_RAR_LV_VOLT_GETS(value) (ARCHI_BEXTRACT((value),5,16)) +#define APB_SOC_SAFE_PMU_RAR_LV_VOLT_SET(value,field) (ARCHI_BINSERT((value),(field),5,16)) +#define APB_SOC_SAFE_PMU_RAR_LV_VOLT(val) ((val) << 16) + +#define APB_SOC_SAFE_PMU_RAR_RV_VOLT_GET(value) (ARCHI_BEXTRACTU((value),5,24)) +#define APB_SOC_SAFE_PMU_RAR_RV_VOLT_GETS(value) (ARCHI_BEXTRACT((value),5,24)) +#define APB_SOC_SAFE_PMU_RAR_RV_VOLT_SET(value,field) (ARCHI_BINSERT((value),(field),5,24)) +#define APB_SOC_SAFE_PMU_RAR_RV_VOLT(val) ((val) << 24) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R0(val) ((val) << 0) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R1(val) ((val) << 1) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R2(val) ((val) << 2) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_L2_R3(val) ((val) << 3) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SOC_FLL(val) ((val) << 4) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_FLL(val) ((val) << 5) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_GET(value) (ARCHI_BEXTRACTU((value),5,6)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_GETS(value) (ARCHI_BEXTRACT((value),5,6)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_SET(value,field) (ARCHI_BINSERT((value),(field),5,6)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC(val) ((val) << 6) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_GET(value) (ARCHI_BEXTRACTU((value),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_GETS(value) (ARCHI_BEXTRACT((value),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_SET(value,field) (ARCHI_BINSERT((value),(field),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE(val) ((val) << 11) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN(val) ((val) << 13) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_WAKESTATE(val) ((val) << 15) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTDEV(val) ((val) << 16) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTINT(val) ((val) << 17) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_GET(value) (ARCHI_BEXTRACTU((value),2,18)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_GETS(value) (ARCHI_BEXTRACT((value),2,18)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE_SET(value,field) (ARCHI_BINSERT((value),(field),2,18)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_BTTYPE(val) ((val) << 18) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_GET(value) (ARCHI_BEXTRACTU((value),1,20)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_GETS(value) (ARCHI_BEXTRACT((value),1,20)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE_SET(value,field) (ARCHI_BINSERT((value),(field),1,20)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CL_WAKE(val) ((val) << 20) + +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R0_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R0(val) ((val) << 0) + +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R1_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R1(val) ((val) << 1) + +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R2_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R2(val) ((val) << 2) + +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R3_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define APB_SOC_SAFE_PMU_FORCE_RET_L2_R3(val) ((val) << 3) + +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R0_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R0(val) ((val) << 4) + +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R1_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R1(val) ((val) << 5) + +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R2_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R2(val) ((val) << 6) + +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_GET(value) (ARCHI_BEXTRACTU((value),1,7)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_GETS(value) (ARCHI_BEXTRACT((value),1,7)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R3_SET(value,field) (ARCHI_BINSERT((value),(field),1,7)) +#define APB_SOC_SAFE_PMU_FORCE_PD_L2_R3(val) ((val) << 7) + +#define APB_SOC_SAFE_PADSLEEP_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_SAFE_PADSLEEP_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_SAFE_PADSLEEP_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_SAFE_PADSLEEP_EN(val) ((val) << 0) + +#define APB_SOC_REG_GPIO_ISO_ISO_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_REG_GPIO_ISO_ISO_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_REG_GPIO_ISO_ISO_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_REG_GPIO_ISO_ISO(val) ((val) << 0) + +#define APB_SOC_REG_CAM_ISO_ISO_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_REG_CAM_ISO_ISO_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_REG_CAM_ISO_ISO_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_REG_CAM_ISO_ISO(val) ((val) << 0) + +#define APB_SOC_REG_LVDS_ISO_ISO_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_REG_LVDS_ISO_ISO_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_REG_LVDS_ISO_ISO_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_REG_LVDS_ISO_ISO(val) ((val) << 0) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/gap/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/gap/memory_map.h new file mode 100644 index 0000000..6d3dcde --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/gap/memory_map.h @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_GAP_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_GAP_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_ADDR 0x1c000000 +#define ARCHI_L2_SIZE 0x00080000 + +#define ARCHI_FC_TCDM_ADDR 0x1b000000 +#define ARCHI_FC_TCDM_SIZE 0x00004000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_PWM_OFFSET 0x00005000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_PMU_OFFSET 0x00007000 +#define ARCHI_RTC_BASE_OFFSET 0x00008000 +#define ARCHI_EFUSE_OFFSET 0x00009000 +#define ARCHI_STDOUT_OFFSET 0x00010000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_PWM_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PWM_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_PMU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PMU_OFFSET ) +#define ARCHI_EFUSE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_EFUSE_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_RTC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_RTC_BASE_OFFSET ) + + + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + + +/* + * FC PERIPHERALS + */ + +#define ARCHI_FC_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_FC_PERIPHERALS_ADDR ( ARCHI_FC_ADDR + ARCHI_FC_PERIPHERALS_OFFSET ) + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FC_TIMER_OFFSET 0x00000400 +#define ARCHI_FC_EU_OFFSET 0x00000800 +#define ARCHI_FC_ICACHE_OFFSET 0x00001400 + +#define ARCHI_FC_TIMER_ADDR ( ARCHI_FC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_FC_EU_ADDR ( ARCHI_FC_PERIPHERALS_ADDR + ARCHI_FC_EU_OFFSET ) +#define ARCHI_FC_ICACHE_ADDR ( ARCHI_FC_PERIPHERALS_ADDR + ARCHI_FC_ICACHE_OFFSET ) + + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/gap/padframe.h b/sw/pulp-sdk/archi/include/archi/chips/gap/padframe.h new file mode 100644 index 0000000..852f2d2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/gap/padframe.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_GAP_PADFRAME_H__ +#define __ARCHI_GAP_PADFRAME_H__ + +#define PLP_PAD_GPIO_0 8 +#define PLP_PAD_GPIO_1 9 +#define PLP_PAD_GPIO_2 10 +#define PLP_PAD_GPIO_3 11 +#define PLP_PAD_GPIO_0_A 12 +#define PLP_PAD_GPIO_1_A 13 +#define PLP_PAD_GPIO_2_A 14 +#define PLP_PAD_GPIO_3_A 15 +#define PLP_PAD_GPIO_4_A 16 +#define PLP_PAD_GPIO_5_A 17 +#define PLP_PAD_GPIO_4 18 +#define PLP_PAD_GPIO_5 19 +#define PLP_PAD_GPIO_6 20 +#define PLP_PAD_GPIO_7 21 +#define PLP_PAD_GPIO_8 22 +#define PLP_PAD_GPIO_9 23 +#define PLP_PAD_GPIO_10 24 +#define PLP_PAD_GPIO_11 25 +#define PLP_PAD_GPIO_12 26 +#define PLP_PAD_GPIO_13 27 +#define PLP_PAD_GPIO_14 28 +#define PLP_PAD_GPIO_15 29 +#define PLP_PAD_GPIO_16 30 +#define PLP_PAD_GPIO_17 31 +#define PLP_PAD_GPIO_18 32 +#define PLP_PAD_GPIO_19 33 +#define PLP_PAD_GPIO_20 34 +#define PLP_PAD_GPIO_21 35 +#define PLP_PAD_GPIO_22 36 +#define PLP_PAD_GPIO_23 37 +#define PLP_PAD_GPIO_24 38 +#define PLP_PAD_GPIO_25 39 +#define PLP_PAD_GPIO_26 42 +#define PLP_PAD_GPIO_27 43 +#define PLP_PAD_GPIO_28 45 +#define PLP_PAD_GPIO_29 47 +#define PLP_PAD_GPIO_30 48 +#define PLP_PAD_GPIO_31 49 + +#define PLP_PAD_RF_MISO 8 +#define PLP_PAD_RF_MOSI 9 +#define PLP_PAD_RF_CSN 10 +#define PLP_PAD_RF_SCK 11 +#define PLP_PAD_GPIO_PACTRL0 12 +#define PLP_PAD_GPIO_PACTRL1 13 +#define PLP_PAD_GPIO_PACTRL2 14 +#define PLP_PAD_GPIO_PACTRL3 15 +#define PLP_PAD_GPIO_PACTRL4 16 +#define PLP_PAD_GPIO_PACTRL5 17 +#define PLP_PAD_CAM_PCLK 18 +#define PLP_PAD_CAM_HSYNC 19 +#define PLP_PAD_CAM_DATA0 20 +#define PLP_PAD_CAM_DATA1 21 +#define PLP_PAD_CAM_DATA2 22 +#define PLP_PAD_CAM_DATA3 23 +#define PLP_PAD_CAM_DATA4 24 +#define PLP_PAD_CAM_DATA5 25 +#define PLP_PAD_CAM_DATA6 26 +#define PLP_PAD_CAM_DATA7 27 +#define PLP_PAD_CAM_VSYNC 28 +#define PLP_PAD_CAM_SDA 29 +#define PLP_PAD_CAM_SCL 30 +#define PLP_PAD_TIMER0_CH0 31 +#define PLP_PAD_TIMER0_CH1 32 +#define PLP_PAD_TIMER0_CH2 33 +#define PLP_PAD_TIMER0_CH3 34 +#define PLP_PAD_I2S1_SCK 35 +#define PLP_PAD_I2S1_WS 36 +#define PLP_PAD_I2S1_SDI 37 +#define PLP_PAD_UART_RX 38 +#define PLP_PAD_UART_TX 39 +#define PLP_PAD_SPIM_SDIO0 40 +#define PLP_PAD_SPIM_SDIO1 41 +#define PLP_PAD_SPIM_SDIO2 42 +#define PLP_PAD_SPIM_SDIO3 43 +#define PLP_PAD_SPIM_CSN0 44 +#define PLP_PAD_SPIM_CSN1 45 +#define PLP_PAD_SPIM_SCK 46 +#define PLP_PAD_SPIM1_CSN 47 +#define PLP_PAD_SPIM1_CS0 47 +#define PLP_PAD_SPIM1_MISO 48 +#define PLP_PAD_SPIM1_MOSI 49 +#define PLP_PAD_SPIM1_SCK 50 + +#define PLP_PAD_SPIS0_SDIO0 16 +#define PLP_PAD_SPIS0_SDIO1 17 +#define PLP_PAD_SPIS0_SCK 35 +#define PLP_PAD_SPIS0_CS 36 +#define PLP_PAD_SPIS0_SDIO2 37 +#define PLP_PAD_SPIS0_SDIO3 45 + +#define PLP_PAD_ORCA_TXSYNC 12 +#define PLP_PAD_ORCA_RXSYNC 13 +#define PLP_PAD_ORCA_TXI 14 +#define PLP_PAD_ORCA_TXQ 15 +#define PLP_PAD_ORCA_RXI 16 +#define PLP_PAD_ORCA_RXQ 17 +#define PLP_PAD_ORCA_CLK 30 + +#define PLP_PAD_HYPER_CKN 36 +#define PLP_PAD_HYPER_CK 37 +#define PLP_PAD_HYPER_DQ0 40 +#define PLP_PAD_HYPER_DQ1 41 +#define PLP_PAD_HYPER_DQ2 42 +#define PLP_PAD_HYPER_DQ3 43 +#define PLP_PAD_HYPER_DQ4 44 +#define PLP_PAD_HYPER_DQ5 45 +#define PLP_PAD_HYPER_DQ6 46 +#define PLP_PAD_HYPER_DQ7 47 +#define PLP_PAD_HYPER_CSN0 48 +#define PLP_PAD_HYPER_CSN1 49 +#define PLP_PAD_HYPER_RWDS 50 + +#define PLP_PAD_GPIO_DEFAULT 0 +#define PLP_PAD_GPIO_ALTERNATE1 1 +#define PLP_PAD_GPIO_ALTERNATE2 2 +#define PLP_PAD_GPIO_ALTERNATE3 3 + +#define PLP_PAD_GPIO_NUM 32 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/gap/properties.h b/sw/pulp-sdk/archi/include/archi/chips/gap/properties.h new file mode 100644 index 0000000..3bf4206 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/gap/properties.h @@ -0,0 +1,273 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_GAP_PROPERTIES_H__ +#define __ARCHI_CHIPS_GAP_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 +#define ARCHI_HAS_FC_TCDM 1 + +#define ARCHI_L1_SIZE 65536 + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define HWCE_VERSION 4 +#define MCHAN_VERSION 6 +#define EFUSE_VERSION 1 +#define PADS_VERSION 2 +#define PWM_VERSION 1 + + +/* + * SOC + */ + +#define ARCHI_PWM_NB 1 +#define ARCHI_PWM_NB_TIMERS 4 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 +#if PULP_CHIP != CHIP_GAP +#define ARCHI_HAS_CLUSTER_CLK_GATE 1 +#endif + +/* + * CLUSTER EVENT UNIT + */ + +//#define ARCHI_HAS_NO_BARRIER 1 +//#define ARCHI_HAS_NO_DISPATCH 1 +//#define ARCHI_HAS_NO_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 32 +#define ARCHI_HAS_FC_EU 1 +#define ARCHI_FC_HAS_ICACHE 1 +#define ARCHI_HAS_FC 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 0 // FIXME put it to the right value once the padframe is specified +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_SLEEP_CONTROL 0x104 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 8 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 8 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/gap9/apb_soc_ctrl.h b/sw/pulp-sdk/archi/include/archi/chips/gap9/apb_soc_ctrl.h new file mode 100644 index 0000000..e07d9ad --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/gap9/apb_soc_ctrl.h @@ -0,0 +1,1581 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_VEGA_APB_SOC_CTRL_H__ +#define __INCLUDE_ARCHI_CHIPS_VEGA_APB_SOC_CTRL_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Core information register +#define APB_SOC_INFO_OFFSET 0x0 + +// Boot address +#define APB_SOC_FC_BOOT_OFFSET 0x4 + +// FC Fetch enable +#define APB_SOC_FC_FETCH_OFFSET 0x8 + +// Isolate cluster register +#define APB_SOC_CL_ISOLATE_OFFSET 0xc + +// Mux config register (pad 0-15) +#define APB_SOC_PADFUN0_OFFSET 0x10 + +// Mux config register (pad 16-31) +#define APB_SOC_PADFUN1_OFFSET 0x14 + +// Mux config register (pad 32-47) +#define APB_SOC_PADFUN2_OFFSET 0x18 + +// Mux config register (pad 48-63) +#define APB_SOC_PADFUN3_OFFSET 0x1c + +// Function register (pad 0 to 3) +#define APB_SOC_PADCFG0_OFFSET 0x20 + +// Function register (pad 4 to 7) +#define APB_SOC_PADCFG1_OFFSET 0x24 + +// Function register (pad 8 to 11) +#define APB_SOC_PADCFG2_OFFSET 0x28 + +// Function register (pad 12 to 15) +#define APB_SOC_PADCFG3_OFFSET 0x2c + +// Function register (pad 16 to 19) +#define APB_SOC_PADCFG4_OFFSET 0x30 + +// Function register (pad 20 to 23) +#define APB_SOC_PADCFG5_OFFSET 0x34 + +// Function register (pad 24 to 27) +#define APB_SOC_PADCFG6_OFFSET 0x38 + +// Function register (pad 28 to 31) +#define APB_SOC_PADCFG7_OFFSET 0x3c + +// Function register (pad 32 to 35) +#define APB_SOC_PADCFG8_OFFSET 0x40 + +// Function register (pad 36 to 39) +#define APB_SOC_PADCFG9_OFFSET 0x44 + +// Function register (pad 40 to 43) +#define APB_SOC_PADCFG10_OFFSET 0x48 + +// Function register (pad 44 to 47) +#define APB_SOC_PADCFG11_OFFSET 0x4c + +// Function register (pad 48 to 51) +#define APB_SOC_PADCFG12_OFFSET 0x50 + +// Function register (pad 52 to 55) +#define APB_SOC_PADCFG13_OFFSET 0x54 + +// Function register (pad 56 to 59) +#define APB_SOC_PADCFG14_OFFSET 0x58 + +// Function register (pad 60 to 63) +#define APB_SOC_PADCFG15_OFFSET 0x5c + +// Cluster busy register +#define APB_SOC_CL_BUSY_OFFSET 0x6c + +// JTAG external register +#define APB_SOC_JTAGREG_OFFSET 0x74 + +// Alias for SAFE_PMU_SLEEPCTRL +#define APB_SOC_SLEEP_CTRL_OFFSET 0x7c + +// Clock divider for I3C +#define APB_SOC_CLK_DIV_I3C_OFFSET 0x80 + +// EOC and chip status register +#define APB_SOC_CORESTATUS_OFFSET 0xa0 + +// EOC and chip status register read mirror +#define APB_SOC_CORESTATUS_RO_OFFSET 0xc0 + +// Value of pad bootsel +#define APB_SOC_BOOTSEL_OFFSET 0xc4 + +// Clear WD timer +#define APB_SOC_WD_CLR_OFFSET 0xc8 + +// Clock selection for SOC,Cluster and Periph +#define APB_SOC_CLK_SEL_OFFSET 0xd0 + +// SOC Clock Divider settings +#define APB_SOC_CLK_DIV_SOC_OFFSET 0xd4 + +// Cluster Clock Divider settings +#define APB_SOC_CLK_DIV_CLU_OFFSET 0xd8 + +// Peripheral Clock Divider Settings +#define APB_SOC_CLK_DIV_PER_OFFSET 0xdc + +// nan +#define APB_SOC_SUPERVISOR_DBG_OFFSET 0xe0 + +// nan +#define APB_SOC_RWM_GRP0_OFFSET 0xe4 + +// nan +#define APB_SOC_RWM_GRP1_OFFSET 0xe8 + +// nan +#define APB_SOC_RWM_GRP2_OFFSET 0xec + +// nan +#define APB_SOC_RWM_GRP3_OFFSET 0xf0 + +// nan +#define APB_SOC_RWM_GRP4_OFFSET 0xf4 + +// nan +#define APB_SOC_RWM_GRP5_OFFSET 0xf8 + +// nan +#define APB_SOC_RWM_GRP6_OFFSET 0xfc + +// Sleep modes configuration register +#define APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET 0x104 + +// Enables and configures WatchDog Timer +#define APB_SOC_SAFE_WD_OFFSET 0x110 + +// Sleep config register (pad 0-7) +#define APB_SOC_SAFE_SLEEPPADCFG0_OFFSET 0x150 + +// Sleep config register (pad 8-15) +#define APB_SOC_SAFE_SLEEPPADCFG1_OFFSET 0x154 + +// Config timings for NEVA +#define APB_SOC_SAFE_NEVACF_OFFSET 0x164 + +// General purpouse register AO +#define APB_SOC_SAFE_GPREG_OFFSET 0x170 + +// L2 standby configuration +#define APB_SOC_SAFE_L2_BTRIM_STDBY_OFFSET 0x174 + +// FLL2 and FLL3 power control +#define APB_SOC_SAFE_FLL_CTRL_OFFSET 0x178 + +// L1 power control +#define APB_SOC_SAFE_L1_PWR_CTRL_OFFSET 0x17c + +// L2 power control +#define APB_SOC_SAFE_L2_PWR_CTRL_OFFSET 0x180 + +// GPIO power domain pad input isolation register +#define APB_SOC_REG_GPIO_ISO_OFFSET 0x1c0 + +// CAM power domain pad input isolation register +#define APB_SOC_REG_CAM_ISO_OFFSET 0x1c4 + +// LVDS power domain pad input isolation register +#define APB_SOC_REG_LVDS_ISO_OFFSET 0x1c8 + + + +// +// REGISTERS FIELDS +// + +// Number of clusters (access: R) +#define APB_SOC_INFO_NB_CL_BIT 0 +#define APB_SOC_INFO_NB_CL_WIDTH 16 +#define APB_SOC_INFO_NB_CL_MASK 0xffff + +// Number of cores (access: R) +#define APB_SOC_INFO_NB_CORES_BIT 16 +#define APB_SOC_INFO_NB_CORES_WIDTH 16 +#define APB_SOC_INFO_NB_CORES_MASK 0xffff0000 + +// FC Boot Address (access: R/W) +#define APB_SOC_FC_BOOT_ADDR_BIT 0 +#define APB_SOC_FC_BOOT_ADDR_WIDTH 32 +#define APB_SOC_FC_BOOT_ADDR_MASK 0xffffffff + +// FC Fetch Enable (access: R/W) +#define APB_SOC_FC_FETCH_FC_FE_BIT 0 +#define APB_SOC_FC_FETCH_FC_FE_WIDTH 1 +#define APB_SOC_FC_FETCH_FC_FE_MASK 0x1 + +// Isolate cluster. Inhibits AXI transactions from cluster to SoC: - 1'b0: Disable - 1'b1: Enable (access: R/W) +#define APB_SOC_CL_ISOLATE_EN_BIT 0 +#define APB_SOC_CL_ISOLATE_EN_WIDTH 1 +#define APB_SOC_CL_ISOLATE_EN_MASK 0x1 + +// Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) (access: R) +#define APB_SOC_CL_BUSY_BUSY_BIT 0 +#define APB_SOC_CL_BUSY_BUSY_WIDTH 1 +#define APB_SOC_CL_BUSY_BUSY_MASK 0x1 + +// JTAG internal register used for synchronisation from external debugger (access: R/W) +#define APB_SOC_JTAGREG_INT_SYNC_BIT 0 +#define APB_SOC_JTAGREG_INT_SYNC_WIDTH 1 +#define APB_SOC_JTAGREG_INT_SYNC_MASK 0x1 + +// JTAG internal register used for selecting boot mode configuration from external debugger (access: R/W) +#define APB_SOC_JTAGREG_INT_BT_MD_BIT 1 +#define APB_SOC_JTAGREG_INT_BT_MD_WIDTH 3 +#define APB_SOC_JTAGREG_INT_BT_MD_MASK 0xe + +// JTAG external register used for synchronisation from external debugger (access: R) +#define APB_SOC_JTAGREG_EXT_SYNC_BIT 8 +#define APB_SOC_JTAGREG_EXT_SYNC_WIDTH 1 +#define APB_SOC_JTAGREG_EXT_SYNC_MASK 0x100 + +// JTAG external register used for selecting boot mode configuration from external debugger (access: R) +#define APB_SOC_JTAGREG_EXT_BT_MD_BIT 9 +#define APB_SOC_JTAGREG_EXT_BT_MD_WIDTH 3 +#define APB_SOC_JTAGREG_EXT_BT_MD_MASK 0xe00 + +// Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) (access: R) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT 0 +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH 32 +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_MASK 0xffffffff + +// EOC and chip status register (access: R/W) +#define APB_SOC_CORESTATUS_STATUS_BIT 0 +#define APB_SOC_CORESTATUS_STATUS_WIDTH 32 +#define APB_SOC_CORESTATUS_STATUS_MASK 0xffffffff + +// EOC and chip status register (access: R) +#define APB_SOC_CORESTATUS_RO_STATUS_BIT 0 +#define APB_SOC_CORESTATUS_RO_STATUS_WIDTH 32 +#define APB_SOC_CORESTATUS_RO_STATUS_MASK 0xffffffff + +// SoC domain clock selection: - 1b0: First FLL is used (FLL1) - 1b1: Second FLL is used (FLL2) (access: R/W) +#define APB_SOC_CLK_SEL_CLK_SOC_BIT 0 +#define APB_SOC_CLK_SEL_CLK_SOC_WIDTH 1 +#define APB_SOC_CLK_SEL_CLK_SOC_MASK 0x1 + +// Cluster domain clock selection: - 2b00: First FLL is used (FLL1) - 2b01: Second FLL is used (FLL2) - 2b10: Third FLL is used (FLL3) (access: R/W) +#define APB_SOC_CLK_SEL_CLK_CLUSTER_BIT 1 +#define APB_SOC_CLK_SEL_CLK_CLUSTER_WIDTH 2 +#define APB_SOC_CLK_SEL_CLK_CLUSTER_MASK 0x6 + +// User value which is kept retentive after wakeup (even in non-retentive sleep). This value is only partially interpreted by the ROM code (TBD) to distinguish betweem cold boot, non-retentive sleep and retentive sleep. (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_BIT 0 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_WIDTH 3 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_MASK 0x7 + +// Enable smart wake-up; - 1'b0; smart wake-up disabled - 1'b1: smart wake-up enabled (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_BIT 9 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_MASK 0x200 + +// Enable RTC wake-up; - 1'b0; rtc wake-up disabled - 1'b1: rtc wake-up enabled (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_BIT 10 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_MASK 0x400 + +// Select external wake-up mode (through dedicated pin): - 2'b00: rise event - 2'b01: fall event - 2'b10: high level - 2'b11: low level (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT 11 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH 2 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_MASK 0x1800 + +// Enable external wake-up (through dedicated pin); - 1'b0; external wake-up disabled - 1'b1: external wake-up enabled (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT 13 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_MASK 0x2000 + +// Power state of the MRAM to restore after warm boot - 1'b0: MRAM OFF - 1'b1: MRAM ON (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_BIT 14 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_MASK 0x4000 + +// Power state of the cluster to restore after warm boot - 1'b0: cluster OFF - 1'b1: cluster ON (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_BIT 15 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_MASK 0x8000 + +// Configure retention mode of L2 memory. There is one bit per cut: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_BIT 16 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_WIDTH 16 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_MASK 0xffff0000 + +// Pad state when the chip is down with low-speed IOs ON: - 4b0000: Tristate with no pull-up and no pull-down - 4b0001: Tristate with pull-up - 4b0010: Tristate with pull-down - 4b0011: Drive 0 - 4b0100: Drive 1 (access: R/W) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_BIT 0 +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_WIDTH 4 +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_MASK 0xf + +// L2 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. (access: R/W) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_BIT 0 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_WIDTH 4 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_MASK 0xf + +// L2 cuts standby active low. One bit per L2 cut for 16 cuts, the cut is in standby when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. (access: R/W) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_BIT 4 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_WIDTH 16 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_MASK 0xffff0 + +// FLL2 power down. The FLL is powered down when this bit is 1b1. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_BIT 0 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_MASK 0x1 + +// FLL3 power down. The FLL is powered down when this bit is 1b1. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_BIT 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_MASK 0x2 + +// FLL2 reset active low. The FLL is reset when this bit is 1b0. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_BIT 2 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_MASK 0x4 + +// FLL3 reset active low. The FLL is reset when this bit is 1b0. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_BIT 3 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_MASK 0x8 + +// L1 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. (access: R/W) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_BIT 0 +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_WIDTH 4 +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_MASK 0xf + +// L1 cuts standby active low. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. (access: R/W) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_BIT 4 +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_WIDTH 2 +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_MASK 0x30 + +// L1 power down. The corresponding L1 part is powered down when this bit is 1b1. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. (access: R/W) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_BIT 6 +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_WIDTH 2 +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_MASK 0xc0 + +// L2 VDDDE active low. One bit per L2 cut for 16 cuts, the cut periphery is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. (access: R/W) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_BIT 0 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_WIDTH 16 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_MASK 0xffff + +// L2 VDDME active low. One bit per L2 cut for 16 cuts, the cut array is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. (access: R/W) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_BIT 16 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_WIDTH 16 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_MASK 0xffff0000 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int nb_cl :16; // Number of clusters + unsigned int nb_cores :16; // Number of cores + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_info_t; + +typedef union { + struct { + unsigned int addr :32; // FC Boot Address + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_fc_boot_t; + +typedef union { + struct { + unsigned int fc_fe :1 ; // FC Fetch Enable + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_fc_fetch_t; + +typedef union { + struct { + unsigned int en :1 ; // Isolate cluster. Inhibits AXI transactions from cluster to SoC: - 1'b0: Disable - 1'b1: Enable + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_cl_isolate_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg4_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg5_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg6_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg7_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg8_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg9_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg10_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg11_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg12_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg13_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg14_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg15_t; + +typedef union { + struct { + unsigned int busy :1 ; // Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_cl_busy_t; + +typedef union { + struct { + unsigned int int_sync :1 ; // JTAG internal register used for synchronisation from external debugger + unsigned int int_bt_md :3 ; // JTAG internal register used for selecting boot mode configuration from external debugger + unsigned int padding0:4 ; + unsigned int ext_sync :1 ; // JTAG external register used for synchronisation from external debugger + unsigned int ext_bt_md :3 ; // JTAG external register used for selecting boot mode configuration from external debugger + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_jtagreg_t; + +typedef union { + struct { + unsigned int sleep_ctrl :32; // Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_sleep_ctrl_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_i3c_t; + +typedef union { + struct { + unsigned int status :32; // EOC and chip status register + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_corestatus_t; + +typedef union { + struct { + unsigned int status :32; // EOC and chip status register + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_corestatus_ro_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_bootsel_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_wd_clr_t; + +typedef union { + struct { + unsigned int clk_soc :1 ; // SoC domain clock selection: - 1b0: First FLL is used (FLL1) - 1b1: Second FLL is used (FLL2) + unsigned int clk_cluster :2 ; // Cluster domain clock selection: - 2b00: First FLL is used (FLL1) - 2b01: Second FLL is used (FLL2) - 2b10: Third FLL is used (FLL3) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_sel_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_soc_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_clu_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_per_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_supervisor_dbg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp4_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp5_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp6_t; + +typedef union { + struct { + unsigned int reboot :3 ; // User value which is kept retentive after wakeup (even in non-retentive sleep). This value is only partially interpreted by the ROM code (TBD) to distinguish betweem cold boot, non-retentive sleep and retentive sleep. + unsigned int padding0:6 ; + unsigned int smartwake_en :1 ; // Enable smart wake-up; - 1'b0; smart wake-up disabled - 1'b1: smart wake-up enabled + unsigned int rtcwake_en :1 ; // Enable RTC wake-up; - 1'b0; rtc wake-up disabled - 1'b1: rtc wake-up enabled + unsigned int extwake_type :2 ; // Select external wake-up mode (through dedicated pin): - 2'b00: rise event - 2'b01: fall event - 2'b10: high level - 2'b11: low level + unsigned int extwake_en :1 ; // Enable external wake-up (through dedicated pin); - 1'b0; external wake-up disabled - 1'b1: external wake-up enabled + unsigned int mram_wakestate :1 ; // Power state of the MRAM to restore after warm boot - 1'b0: MRAM OFF - 1'b1: MRAM ON + unsigned int cluster_wakestate:1 ; // Power state of the cluster to restore after warm boot - 1'b0: cluster OFF - 1'b1: cluster ON + unsigned int ret_mem :16; // Configure retention mode of L2 memory. There is one bit per cut: - 1'b0: Non retentive - 1'b1: Retentive + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_pmu_sleepctrl_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_wd_t; + +typedef union { + struct { + unsigned int state :4 ; // Pad state when the chip is down with low-speed IOs ON: - 4b0000: Tristate with no pull-up and no pull-down - 4b0001: Tristate with pull-up - 4b0010: Tristate with pull-down - 4b0011: Drive 0 - 4b0100: Drive 1 + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_nevacf_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_gpreg_t; + +typedef union { + struct { + unsigned int btrim :4 ; // L2 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. + unsigned int stdby_n :16; // L2 cuts standby active low. One bit per L2 cut for 16 cuts, the cut is in standby when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_l2_btrim_stdby_t; + +typedef union { + struct { + unsigned int fll2_pwd :1 ; // FLL2 power down. The FLL is powered down when this bit is 1b1. + unsigned int fll3_pwd :1 ; // FLL3 power down. The FLL is powered down when this bit is 1b1. + unsigned int fll2_rstb :1 ; // FLL2 reset active low. The FLL is reset when this bit is 1b0. + unsigned int fll3_rstb :1 ; // FLL3 reset active low. The FLL is reset when this bit is 1b0. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_fll_ctrl_t; + +typedef union { + struct { + unsigned int btrim :4 ; // L1 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. + unsigned int stdby_n :2 ; // L1 cuts standby active low. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. + unsigned int pwd :2 ; // L1 power down. The corresponding L1 part is powered down when this bit is 1b1. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_l1_pwr_ctrl_t; + +typedef union { + struct { + unsigned int vddde_n :16; // L2 VDDDE active low. One bit per L2 cut for 16 cuts, the cut periphery is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. + unsigned int vddme_n :16; // L2 VDDME active low. One bit per L2 cut for 16 cuts, the cut array is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_l2_pwr_ctrl_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_gpio_iso_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_cam_iso_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_lvds_iso_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_apb_soc_info : public vp::reg_32 +{ +public: + inline void nb_cl_set(uint32_t value) { this->set_field(value, APB_SOC_INFO_NB_CL_BIT, APB_SOC_INFO_NB_CL_WIDTH); } + inline uint32_t nb_cl_get() { return this->get_field(APB_SOC_INFO_NB_CL_BIT, APB_SOC_INFO_NB_CL_WIDTH); } + inline void nb_cores_set(uint32_t value) { this->set_field(value, APB_SOC_INFO_NB_CORES_BIT, APB_SOC_INFO_NB_CORES_WIDTH); } + inline uint32_t nb_cores_get() { return this->get_field(APB_SOC_INFO_NB_CORES_BIT, APB_SOC_INFO_NB_CORES_WIDTH); } +}; + +class vp_apb_soc_fc_boot : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, APB_SOC_FC_BOOT_ADDR_BIT, APB_SOC_FC_BOOT_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(APB_SOC_FC_BOOT_ADDR_BIT, APB_SOC_FC_BOOT_ADDR_WIDTH); } +}; + +class vp_apb_soc_fc_fetch : public vp::reg_32 +{ +public: + inline void fc_fe_set(uint32_t value) { this->set_field(value, APB_SOC_FC_FETCH_FC_FE_BIT, APB_SOC_FC_FETCH_FC_FE_WIDTH); } + inline uint32_t fc_fe_get() { return this->get_field(APB_SOC_FC_FETCH_FC_FE_BIT, APB_SOC_FC_FETCH_FC_FE_WIDTH); } +}; + +class vp_apb_soc_cl_isolate : public vp::reg_32 +{ +public: + inline void en_set(uint32_t value) { this->set_field(value, APB_SOC_CL_ISOLATE_EN_BIT, APB_SOC_CL_ISOLATE_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(APB_SOC_CL_ISOLATE_EN_BIT, APB_SOC_CL_ISOLATE_EN_WIDTH); } +}; + +class vp_apb_soc_padfun0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padfun1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padfun2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padfun3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg4 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg5 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg6 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg7 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg8 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg9 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg10 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg11 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg12 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg13 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg14 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg15 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_cl_busy : public vp::reg_32 +{ +public: + inline void busy_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BUSY_BUSY_BIT, APB_SOC_CL_BUSY_BUSY_WIDTH); } + inline uint32_t busy_get() { return this->get_field(APB_SOC_CL_BUSY_BUSY_BIT, APB_SOC_CL_BUSY_BUSY_WIDTH); } +}; + +class vp_apb_soc_jtagreg : public vp::reg_32 +{ +public: + inline void int_sync_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_INT_SYNC_BIT, APB_SOC_JTAGREG_INT_SYNC_WIDTH); } + inline uint32_t int_sync_get() { return this->get_field(APB_SOC_JTAGREG_INT_SYNC_BIT, APB_SOC_JTAGREG_INT_SYNC_WIDTH); } + inline void int_bt_md_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_INT_BT_MD_BIT, APB_SOC_JTAGREG_INT_BT_MD_WIDTH); } + inline uint32_t int_bt_md_get() { return this->get_field(APB_SOC_JTAGREG_INT_BT_MD_BIT, APB_SOC_JTAGREG_INT_BT_MD_WIDTH); } + inline void ext_sync_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_EXT_SYNC_BIT, APB_SOC_JTAGREG_EXT_SYNC_WIDTH); } + inline uint32_t ext_sync_get() { return this->get_field(APB_SOC_JTAGREG_EXT_SYNC_BIT, APB_SOC_JTAGREG_EXT_SYNC_WIDTH); } + inline void ext_bt_md_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_EXT_BT_MD_BIT, APB_SOC_JTAGREG_EXT_BT_MD_WIDTH); } + inline uint32_t ext_bt_md_get() { return this->get_field(APB_SOC_JTAGREG_EXT_BT_MD_BIT, APB_SOC_JTAGREG_EXT_BT_MD_WIDTH); } +}; + +class vp_apb_soc_sleep_ctrl : public vp::reg_32 +{ +public: + inline void sleep_ctrl_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH); } + inline uint32_t sleep_ctrl_get() { return this->get_field(APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH); } +}; + +class vp_apb_soc_clk_div_i3c : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_corestatus : public vp::reg_32 +{ +public: + inline void status_set(uint32_t value) { this->set_field(value, APB_SOC_CORESTATUS_STATUS_BIT, APB_SOC_CORESTATUS_STATUS_WIDTH); } + inline uint32_t status_get() { return this->get_field(APB_SOC_CORESTATUS_STATUS_BIT, APB_SOC_CORESTATUS_STATUS_WIDTH); } +}; + +class vp_apb_soc_corestatus_ro : public vp::reg_32 +{ +public: + inline void status_set(uint32_t value) { this->set_field(value, APB_SOC_CORESTATUS_RO_STATUS_BIT, APB_SOC_CORESTATUS_RO_STATUS_WIDTH); } + inline uint32_t status_get() { return this->get_field(APB_SOC_CORESTATUS_RO_STATUS_BIT, APB_SOC_CORESTATUS_RO_STATUS_WIDTH); } +}; + +class vp_apb_soc_bootsel : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_wd_clr : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_clk_sel : public vp::reg_32 +{ +public: + inline void clk_soc_set(uint32_t value) { this->set_field(value, APB_SOC_CLK_SEL_CLK_SOC_BIT, APB_SOC_CLK_SEL_CLK_SOC_WIDTH); } + inline uint32_t clk_soc_get() { return this->get_field(APB_SOC_CLK_SEL_CLK_SOC_BIT, APB_SOC_CLK_SEL_CLK_SOC_WIDTH); } + inline void clk_cluster_set(uint32_t value) { this->set_field(value, APB_SOC_CLK_SEL_CLK_CLUSTER_BIT, APB_SOC_CLK_SEL_CLK_CLUSTER_WIDTH); } + inline uint32_t clk_cluster_get() { return this->get_field(APB_SOC_CLK_SEL_CLK_CLUSTER_BIT, APB_SOC_CLK_SEL_CLK_CLUSTER_WIDTH); } +}; + +class vp_apb_soc_clk_div_soc : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_clk_div_clu : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_clk_div_per : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_supervisor_dbg : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp4 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp5 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp6 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_pmu_sleepctrl : public vp::reg_32 +{ +public: + inline void reboot_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_WIDTH); } + inline uint32_t reboot_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_WIDTH); } + inline void smartwake_en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_WIDTH); } + inline uint32_t smartwake_en_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_WIDTH); } + inline void rtcwake_en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_WIDTH); } + inline uint32_t rtcwake_en_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_WIDTH); } + inline void extwake_type_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH); } + inline uint32_t extwake_type_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH); } + inline void extwake_en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH); } + inline uint32_t extwake_en_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH); } + inline void mram_wakestate_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_WIDTH); } + inline uint32_t mram_wakestate_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_WIDTH); } + inline void cluster_wakestate_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_WIDTH); } + inline uint32_t cluster_wakestate_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_WIDTH); } + inline void ret_mem_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_WIDTH); } + inline uint32_t ret_mem_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_WIDTH); } +}; + +class vp_apb_soc_safe_wd : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_sleeppadcfg0 : public vp::reg_32 +{ +public: + inline void state_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_SLEEPPADCFG0_STATE_BIT, APB_SOC_SAFE_SLEEPPADCFG0_STATE_WIDTH); } + inline uint32_t state_get() { return this->get_field(APB_SOC_SAFE_SLEEPPADCFG0_STATE_BIT, APB_SOC_SAFE_SLEEPPADCFG0_STATE_WIDTH); } +}; + +class vp_apb_soc_safe_sleeppadcfg1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_nevacf : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_gpreg : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_l2_btrim_stdby : public vp::reg_32 +{ +public: + inline void btrim_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_WIDTH); } + inline uint32_t btrim_get() { return this->get_field(APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_WIDTH); } + inline void stdby_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_WIDTH); } + inline uint32_t stdby_n_get() { return this->get_field(APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_WIDTH); } +}; + +class vp_apb_soc_safe_fll_ctrl : public vp::reg_32 +{ +public: + inline void fll2_pwd_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_WIDTH); } + inline uint32_t fll2_pwd_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_WIDTH); } + inline void fll3_pwd_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_WIDTH); } + inline uint32_t fll3_pwd_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_WIDTH); } + inline void fll2_rstb_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_WIDTH); } + inline uint32_t fll2_rstb_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_WIDTH); } + inline void fll3_rstb_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_WIDTH); } + inline uint32_t fll3_rstb_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_WIDTH); } +}; + +class vp_apb_soc_safe_l1_pwr_ctrl : public vp::reg_32 +{ +public: + inline void btrim_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_BIT, APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_WIDTH); } + inline uint32_t btrim_get() { return this->get_field(APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_BIT, APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_WIDTH); } + inline void stdby_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_BIT, APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_WIDTH); } + inline uint32_t stdby_n_get() { return this->get_field(APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_BIT, APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_WIDTH); } + inline void pwd_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L1_PWR_CTRL_PWD_BIT, APB_SOC_SAFE_L1_PWR_CTRL_PWD_WIDTH); } + inline uint32_t pwd_get() { return this->get_field(APB_SOC_SAFE_L1_PWR_CTRL_PWD_BIT, APB_SOC_SAFE_L1_PWR_CTRL_PWD_WIDTH); } +}; + +class vp_apb_soc_safe_l2_pwr_ctrl : public vp::reg_32 +{ +public: + inline void vddde_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_WIDTH); } + inline uint32_t vddde_n_get() { return this->get_field(APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_WIDTH); } + inline void vddme_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_WIDTH); } + inline uint32_t vddme_n_get() { return this->get_field(APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_WIDTH); } +}; + +class vp_apb_soc_reg_gpio_iso : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_reg_cam_iso : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_reg_lvds_iso : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int info ; // Core information register + unsigned int fc_boot ; // Boot address + unsigned int fc_fetch ; // FC Fetch enable + unsigned int cl_isolate ; // Isolate cluster register + unsigned int padfun0 ; // Mux config register (pad 0-15) + unsigned int padfun1 ; // Mux config register (pad 16-31) + unsigned int padfun2 ; // Mux config register (pad 32-47) + unsigned int padfun3 ; // Mux config register (pad 48-63) + unsigned int padcfg0 ; // Function register (pad 0 to 3) + unsigned int padcfg1 ; // Function register (pad 4 to 7) + unsigned int padcfg2 ; // Function register (pad 8 to 11) + unsigned int padcfg3 ; // Function register (pad 12 to 15) + unsigned int padcfg4 ; // Function register (pad 16 to 19) + unsigned int padcfg5 ; // Function register (pad 20 to 23) + unsigned int padcfg6 ; // Function register (pad 24 to 27) + unsigned int padcfg7 ; // Function register (pad 28 to 31) + unsigned int padcfg8 ; // Function register (pad 32 to 35) + unsigned int padcfg9 ; // Function register (pad 36 to 39) + unsigned int padcfg10 ; // Function register (pad 40 to 43) + unsigned int padcfg11 ; // Function register (pad 44 to 47) + unsigned int padcfg12 ; // Function register (pad 48 to 51) + unsigned int padcfg13 ; // Function register (pad 52 to 55) + unsigned int padcfg14 ; // Function register (pad 56 to 59) + unsigned int padcfg15 ; // Function register (pad 60 to 63) + unsigned int cl_busy ; // Cluster busy register + unsigned int jtagreg ; // JTAG external register + unsigned int sleep_ctrl ; // Alias for SAFE_PMU_SLEEPCTRL + unsigned int clk_div_i3c ; // Clock divider for I3C + unsigned int corestatus ; // EOC and chip status register + unsigned int corestatus_ro ; // EOC and chip status register read mirror + unsigned int bootsel ; // Value of pad bootsel + unsigned int wd_clr ; // Clear WD timer + unsigned int clk_sel ; // Clock selection for SOC,Cluster and Periph + unsigned int clk_div_soc ; // SOC Clock Divider settings + unsigned int clk_div_clu ; // Cluster Clock Divider settings + unsigned int clk_div_per ; // Peripheral Clock Divider Settings + unsigned int supervisor_dbg ; // nan + unsigned int rwm_grp0 ; // nan + unsigned int rwm_grp1 ; // nan + unsigned int rwm_grp2 ; // nan + unsigned int rwm_grp3 ; // nan + unsigned int rwm_grp4 ; // nan + unsigned int rwm_grp5 ; // nan + unsigned int rwm_grp6 ; // nan + unsigned int safe_pmu_sleepctrl; // Sleep modes configuration register + unsigned int safe_wd ; // Enables and configures WatchDog Timer + unsigned int safe_sleeppadcfg0; // Sleep config register (pad 0-7) + unsigned int safe_sleeppadcfg1; // Sleep config register (pad 8-15) + unsigned int safe_nevacf ; // Config timings for NEVA + unsigned int safe_gpreg ; // General purpouse register AO + unsigned int safe_l2_btrim_stdby; // L2 standby configuration + unsigned int safe_fll_ctrl ; // FLL2 and FLL3 power control + unsigned int safe_l1_pwr_ctrl; // L1 power control + unsigned int safe_l2_pwr_ctrl; // L2 power control + unsigned int reg_gpio_iso ; // GPIO power domain pad input isolation register + unsigned int reg_cam_iso ; // CAM power domain pad input isolation register + unsigned int reg_lvds_iso ; // LVDS power domain pad input isolation register +} __attribute__((packed)) apb_soc_apb_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t apb_soc_info_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_INFO_OFFSET); } +static inline void apb_soc_info_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_INFO_OFFSET, value); } + +static inline uint32_t apb_soc_fc_boot_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_FC_BOOT_OFFSET); } +static inline void apb_soc_fc_boot_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_FC_BOOT_OFFSET, value); } + +static inline uint32_t apb_soc_fc_fetch_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_FC_FETCH_OFFSET); } +static inline void apb_soc_fc_fetch_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_FC_FETCH_OFFSET, value); } + +static inline uint32_t apb_soc_cl_isolate_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CL_ISOLATE_OFFSET); } +static inline void apb_soc_cl_isolate_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CL_ISOLATE_OFFSET, value); } + +static inline uint32_t apb_soc_padfun0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN0_OFFSET); } +static inline void apb_soc_padfun0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN0_OFFSET, value); } + +static inline uint32_t apb_soc_padfun1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN1_OFFSET); } +static inline void apb_soc_padfun1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN1_OFFSET, value); } + +static inline uint32_t apb_soc_padfun2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN2_OFFSET); } +static inline void apb_soc_padfun2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN2_OFFSET, value); } + +static inline uint32_t apb_soc_padfun3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN3_OFFSET); } +static inline void apb_soc_padfun3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN3_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG0_OFFSET); } +static inline void apb_soc_padcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG0_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG1_OFFSET); } +static inline void apb_soc_padcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG1_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG2_OFFSET); } +static inline void apb_soc_padcfg2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG2_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG3_OFFSET); } +static inline void apb_soc_padcfg3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG3_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg4_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG4_OFFSET); } +static inline void apb_soc_padcfg4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG4_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg5_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG5_OFFSET); } +static inline void apb_soc_padcfg5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG5_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg6_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG6_OFFSET); } +static inline void apb_soc_padcfg6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG6_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg7_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG7_OFFSET); } +static inline void apb_soc_padcfg7_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG7_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg8_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG8_OFFSET); } +static inline void apb_soc_padcfg8_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG8_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg9_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG9_OFFSET); } +static inline void apb_soc_padcfg9_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG9_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg10_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG10_OFFSET); } +static inline void apb_soc_padcfg10_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG10_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg11_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG11_OFFSET); } +static inline void apb_soc_padcfg11_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG11_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg12_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG12_OFFSET); } +static inline void apb_soc_padcfg12_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG12_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg13_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG13_OFFSET); } +static inline void apb_soc_padcfg13_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG13_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg14_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG14_OFFSET); } +static inline void apb_soc_padcfg14_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG14_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg15_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG15_OFFSET); } +static inline void apb_soc_padcfg15_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG15_OFFSET, value); } + +static inline uint32_t apb_soc_cl_busy_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CL_BUSY_OFFSET); } +static inline void apb_soc_cl_busy_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CL_BUSY_OFFSET, value); } + +static inline uint32_t apb_soc_jtagreg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_JTAGREG_OFFSET); } +static inline void apb_soc_jtagreg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_JTAGREG_OFFSET, value); } + +static inline uint32_t apb_soc_sleep_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SLEEP_CTRL_OFFSET); } +static inline void apb_soc_sleep_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SLEEP_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_i3c_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_I3C_OFFSET); } +static inline void apb_soc_clk_div_i3c_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_I3C_OFFSET, value); } + +static inline uint32_t apb_soc_corestatus_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CORESTATUS_OFFSET); } +static inline void apb_soc_corestatus_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CORESTATUS_OFFSET, value); } + +static inline uint32_t apb_soc_corestatus_ro_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CORESTATUS_RO_OFFSET); } +static inline void apb_soc_corestatus_ro_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CORESTATUS_RO_OFFSET, value); } + +static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); } +static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); } + +static inline uint32_t apb_soc_wd_clr_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_WD_CLR_OFFSET); } +static inline void apb_soc_wd_clr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_WD_CLR_OFFSET, value); } + +static inline uint32_t apb_soc_clk_sel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_SEL_OFFSET); } +static inline void apb_soc_clk_sel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_SEL_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_soc_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_SOC_OFFSET); } +static inline void apb_soc_clk_div_soc_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_SOC_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_clu_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_CLU_OFFSET); } +static inline void apb_soc_clk_div_clu_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_CLU_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_per_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_PER_OFFSET); } +static inline void apb_soc_clk_div_per_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_PER_OFFSET, value); } + +static inline uint32_t apb_soc_supervisor_dbg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SUPERVISOR_DBG_OFFSET); } +static inline void apb_soc_supervisor_dbg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SUPERVISOR_DBG_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP0_OFFSET); } +static inline void apb_soc_rwm_grp0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP0_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP1_OFFSET); } +static inline void apb_soc_rwm_grp1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP1_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP2_OFFSET); } +static inline void apb_soc_rwm_grp2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP2_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP3_OFFSET); } +static inline void apb_soc_rwm_grp3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP3_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp4_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP4_OFFSET); } +static inline void apb_soc_rwm_grp4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP4_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp5_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP5_OFFSET); } +static inline void apb_soc_rwm_grp5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP5_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp6_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP6_OFFSET); } +static inline void apb_soc_rwm_grp6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP6_OFFSET, value); } + +static inline uint32_t apb_soc_safe_pmu_sleepctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET); } +static inline void apb_soc_safe_pmu_sleepctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET, value); } + +static inline uint32_t apb_soc_safe_wd_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_WD_OFFSET); } +static inline void apb_soc_safe_wd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_WD_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG0_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG0_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG1_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG1_OFFSET, value); } + +static inline uint32_t apb_soc_safe_nevacf_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_NEVACF_OFFSET); } +static inline void apb_soc_safe_nevacf_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_NEVACF_OFFSET, value); } + +static inline uint32_t apb_soc_safe_gpreg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_GPREG_OFFSET); } +static inline void apb_soc_safe_gpreg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_GPREG_OFFSET, value); } + +static inline uint32_t apb_soc_safe_l2_btrim_stdby_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_L2_BTRIM_STDBY_OFFSET); } +static inline void apb_soc_safe_l2_btrim_stdby_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_L2_BTRIM_STDBY_OFFSET, value); } + +static inline uint32_t apb_soc_safe_fll_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_FLL_CTRL_OFFSET); } +static inline void apb_soc_safe_fll_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_FLL_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_safe_l1_pwr_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_L1_PWR_CTRL_OFFSET); } +static inline void apb_soc_safe_l1_pwr_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_L1_PWR_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_safe_l2_pwr_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_L2_PWR_CTRL_OFFSET); } +static inline void apb_soc_safe_l2_pwr_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_L2_PWR_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_reg_gpio_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_GPIO_ISO_OFFSET); } +static inline void apb_soc_reg_gpio_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_GPIO_ISO_OFFSET, value); } + +static inline uint32_t apb_soc_reg_cam_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_CAM_ISO_OFFSET); } +static inline void apb_soc_reg_cam_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_CAM_ISO_OFFSET, value); } + +static inline uint32_t apb_soc_reg_lvds_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_LVDS_ISO_OFFSET); } +static inline void apb_soc_reg_lvds_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_LVDS_ISO_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define APB_SOC_INFO_NB_CL_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define APB_SOC_INFO_NB_CL_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define APB_SOC_INFO_NB_CL_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define APB_SOC_INFO_NB_CL(val) ((val) << 0) + +#define APB_SOC_INFO_NB_CORES_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define APB_SOC_INFO_NB_CORES_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define APB_SOC_INFO_NB_CORES_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define APB_SOC_INFO_NB_CORES(val) ((val) << 16) + +#define APB_SOC_FC_BOOT_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_FC_BOOT_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_FC_BOOT_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_FC_BOOT_ADDR(val) ((val) << 0) + +#define APB_SOC_FC_FETCH_FC_FE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_FC_FETCH_FC_FE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_FC_FETCH_FC_FE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_FC_FETCH_FC_FE(val) ((val) << 0) + +#define APB_SOC_CL_ISOLATE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CL_ISOLATE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CL_ISOLATE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CL_ISOLATE_EN(val) ((val) << 0) + +#define APB_SOC_CL_BUSY_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CL_BUSY_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CL_BUSY_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CL_BUSY_BUSY(val) ((val) << 0) + +#define APB_SOC_JTAGREG_INT_SYNC_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC(val) ((val) << 0) + +#define APB_SOC_JTAGREG_INT_BT_MD_GET(value) (ARCHI_BEXTRACTU((value),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD_GETS(value) (ARCHI_BEXTRACT((value),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD_SET(value,field) (ARCHI_BINSERT((value),(field),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD(val) ((val) << 1) + +#define APB_SOC_JTAGREG_EXT_SYNC_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC(val) ((val) << 8) + +#define APB_SOC_JTAGREG_EXT_BT_MD_GET(value) (ARCHI_BEXTRACTU((value),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD_GETS(value) (ARCHI_BEXTRACT((value),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD_SET(value,field) (ARCHI_BINSERT((value),(field),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD(val) ((val) << 9) + +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL(val) ((val) << 0) + +#define APB_SOC_CORESTATUS_STATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_CORESTATUS_STATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_CORESTATUS_STATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_CORESTATUS_STATUS(val) ((val) << 0) + +#define APB_SOC_CORESTATUS_RO_STATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS(val) ((val) << 0) + +#define APB_SOC_CLK_SEL_CLK_SOC_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CLK_SEL_CLK_SOC_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CLK_SEL_CLK_SOC_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CLK_SEL_CLK_SOC(val) ((val) << 0) + +#define APB_SOC_CLK_SEL_CLK_CLUSTER_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define APB_SOC_CLK_SEL_CLK_CLUSTER_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define APB_SOC_CLK_SEL_CLK_CLUSTER_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define APB_SOC_CLK_SEL_CLK_CLUSTER(val) ((val) << 1) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT(val) ((val) << 0) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN(val) ((val) << 9) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,10)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,10)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,10)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN(val) ((val) << 10) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_GET(value) (ARCHI_BEXTRACTU((value),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_GETS(value) (ARCHI_BEXTRACT((value),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_SET(value,field) (ARCHI_BINSERT((value),(field),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE(val) ((val) << 11) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN(val) ((val) << 13) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_GET(value) (ARCHI_BEXTRACTU((value),1,14)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_GETS(value) (ARCHI_BEXTRACT((value),1,14)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,14)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE(val) ((val) << 14) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE(val) ((val) << 15) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM(val) ((val) << 16) + +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE(val) ((val) << 0) + +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM(val) ((val) << 0) + +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_GET(value) (ARCHI_BEXTRACTU((value),16,4)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_GETS(value) (ARCHI_BEXTRACT((value),16,4)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_SET(value,field) (ARCHI_BINSERT((value),(field),16,4)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N(val) ((val) << 4) + +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD(val) ((val) << 0) + +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD(val) ((val) << 1) + +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB(val) ((val) << 2) + +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB(val) ((val) << 3) + +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM(val) ((val) << 0) + +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_GET(value) (ARCHI_BEXTRACTU((value),2,4)) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_GETS(value) (ARCHI_BEXTRACT((value),2,4)) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_SET(value,field) (ARCHI_BINSERT((value),(field),2,4)) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N(val) ((val) << 4) + +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_GET(value) (ARCHI_BEXTRACTU((value),2,6)) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_GETS(value) (ARCHI_BEXTRACT((value),2,6)) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_SET(value,field) (ARCHI_BINSERT((value),(field),2,6)) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD(val) ((val) << 6) + +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N(val) ((val) << 0) + +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N(val) ((val) << 16) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/gap9/memory_map.h.in b/sw/pulp-sdk/archi/include/archi/chips/gap9/memory_map.h.in new file mode 100644 index 0000000..63c751d --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/gap9/memory_map.h.in @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VEGA_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_VEGA_MEMORY_MAP_H__ + + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE @l2_shared_size@ + + + +/* + * MRAM + */ + +#define ARCHI_MRAM_ADDR 0x1D000000 + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_CVP_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_PWM_OFFSET 0x00005000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 /// FIXME: not soc eu but soc event generator +#define ARCHI_PMU_OFFSET 0x00007000 +#define ARCHI_RTC_BASE_OFFSET 0x00008000 +#define ARCHI_FC_ICACHE_OFFSET 0x00008800 +#define ARCHI_FC_ITC_OFFSET 0x00009000 +#define ARCHI_I3C0_OFFSET 0x0000A000 +#define ARCHI_I3C1_OFFSET 0x0000A800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_FC_TIMER1_OFFSET 0x0000B800 +#define ARCHI_DPHY_OFFSET 0x0000C000 +#define ARCHI_CSI2_OFFSET 0x0000D000 +#define ARCHI_MPU_OFFSET 0x0000E000 +#define ARCHI_EFUSE_OFFSET 0x0000F000 +#define ARCHI_DEBUG_OFFSET 0x00010000 +#define ARCHI_STDOUT_OFFSET 0x00020000 +#define ARCHI_QUIDDIKEY_OFFSET 0x00021000 + +#define ARCHI_FLL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FLL_OFFSET ) +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_PWM_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PWM_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_PMU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PMU_OFFSET ) +#define ARCHI_RTC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_RTC_BASE_OFFSET ) +#define ARCHI_FC_ICACHE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ICACHE_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_I3C0_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_I3C0_OFFSET ) +#define ARCHI_I3C1_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_I3C1_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +// #define ARCHI_FC_TIMER1_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER1_OFFSET ) +#define ARCHI_DPHY_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_DPHY_OFFSET ) +#define ARCHI_CSI2_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_CSI2_OFFSET ) +#define ARCHI_MPU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_MPU_OFFSET ) +#define ARCHI_EFUSE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_EFUSE_OFFSET ) +#define ARCHI_DEBUG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_DEBUG_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_QUIDDIKEY_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_QUIDDIKEY_OFFSET ) + + + +// VEGA HAL Handles definition +#define QUIDDIKEY_HANDLE ((halQuiddikeyHandle_t *)(ARCHI_QUIDDIKEY_ADDR)) +#define CSI2_HANDLE ((halCsi2Handle_t *)(ARCHI_CSI2_ADDR)) +#define DPHY_HANDLE ((halDphyHandle_t *)(ARCHI_DPHY_ADDR)) + +#define UDMA_CSI2_HANDLE(id) ((plpUdmaCsi2Handle_t *)(ARCHI_UDMA_ADDR + UDMA_CSI2_OFFSET(id))) + + + + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + +/* + * FC + */ +// NOTE: they are all in SOC PERIPH now + +#define ARCHI_FC_ADDR 0x00000000 +// #define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/gap9/pmu.h b/sw/pulp-sdk/archi/include/archi/chips/gap9/pmu.h new file mode 100644 index 0000000..01155f7 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/gap9/pmu.h @@ -0,0 +1,510 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_VEGA_PMU_H__ +#define __INCLUDE_ARCHI_CHIPS_VEGA_PMU_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_pmu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu0 +// + +#define PMU_ICU0_OFFSET 0x2 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu0_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu1 +// + +#define PMU_ICU1_OFFSET 0x3 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu1_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP dmu0 +// + +#define PMU_DMU0_OFFSET 0x4 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_dmu0_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu_soc +// + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// CUSTOM FIELDS +// +#define PMU_SOC_ON_NV 0x00 +#define PMU_SOC_ON_LV 0x01 +#define PMU_SOC_RET_OFF 0x02 +#define PMU_SOC_RET_NV 0x03 +#define PMU_SOC_RET_LV 0x04 +#define PMU_SOC_RET_RV 0x05 +#define PMU_SOC_EXT_OFF 0x06 +#define PMU_SOC_EXT_NV 0x07 +#define PMU_SOC_EXT_LV 0x08 +#define PMU_SOC_EXT_RV 0x09 +#define PMU_SOC_CKOFF_NV 0x11 +#define PMU_SOC_CKOFF_LV 0x12 +#define PMU_SOC_CKOFF_RV 0x13 + + + +// +// GROUP icu_cluster +// + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu_cluster_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// CUSTOM FIELDS +// +#define PMU_CLUSTER_ON_NV 0x00 +#define PMU_CLUSTER_ON_LV 0x01 +#define PMU_CLUSTER_RET_OFF 0x02 +#define PMU_CLUSTER_RET_NV 0x03 +#define PMU_CLUSTER_RET_LV 0x04 +#define PMU_CLUSTER_RET_RV 0x05 +#define PMU_CLUSTER_EXT_OFF 0x06 +#define PMU_CLUSTER_EXT_NV 0x07 +#define PMU_CLUSTER_EXT_LV 0x08 +#define PMU_CLUSTER_EXT_RV 0x09 +#define PMU_CLUSTER_CKOFF_NV 0x11 +#define PMU_CLUSTER_CKOFF_LV 0x12 +#define PMU_CLUSTER_CKOFF_RV 0x13 + + + +// +// CUSTOM FIELDS +// +#define PMU_BOOT 0x01 +#define PMU_SOC_ACTIVE_NV 0x01 +#define PMU_SOC_ACTIVE_LV 0x02 +#define PMU_SOC_CLUSTER_ACTIVE_NV 0x04 +#define PMU_SOC_CLUSTER_ACTIVE_LV 0x08 +#define PMU_DEEP_SLEEP_ALL_OFF 0x10 +#define PMU_DEEP_SLEEP_RETENTIVE 0x20 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/gap9/properties.h b/sw/pulp-sdk/archi/include/archi/chips/gap9/properties.h new file mode 100644 index 0000000..9ff3bb2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/gap9/properties.h @@ -0,0 +1,347 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VEGA_PROPERTIES_H__ +#define __ARCHI_CHIPS_VEGA_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 0x20000 + +#define ARCHI_MEMORY_POWER 1 + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define FLL_VERSION 1 +#define GPIO_VERSION 2 +#define UDMA_VERSION 3 +#define PERIPH_VERSION 3 +#define APB_SOC_VERSION 3 +#define ADV_TIMER_VERSION 1 +#define SOC_EU_VERSION 2 +#define PMU_VERSION 3 +#define FC_ICACHE_CTRL_VERSION 2 +#define ITC_VERSION 1 +#define I3C_VERSION 1 +#define TIMER_VERSION 2 +#define DPHY_VERSION 1 +#define CSI2_VERSION 1 +#define MPU_VERSION 1 +#define EFUSE_VERSION 1 +#define DEBUG_VERSION 1 +#define STDOUT_VERSION 2 +#define QUIDDIKEY_VERSION 1 +#define ROM_VERSION 2 +#define RTC_VERSION 1 + +#define EU_VERSION 3 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 7 +#define HWCE_VERSION 5 + +#define CL_CTRL_VERSION 2 +#define PADS_VERSION 2 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_CL_CID 0 + +// TAS = Test&Set +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_HAS_CC 1 +#define ARCHI_CC_CORE_ID 8 +#define ARCHI_CLUSTER_NB_PE 8 +#define ARCHI_HAS_CLUSTER_CLK_GATE 1 + + +/* + * CLUSTER EVENT UNIT + */ + +//#define ARCHI_HAS_NO_BARRIER 1 +//#define ARCHI_HAS_NO_DISPATCH 1 +//#define ARCHI_HAS_NO_MUTEX 1 + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 +#define ARCHI_FC_HAS_ICACHE 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/multino/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/multino/memory_map.h new file mode 100644 index 0000000..998871e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/multino/memory_map.h @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_MULTINO_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_MULTINO_MEMORY_MAP_H__ + + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + + +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UART_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SPIM_OFFSET 0x00005000 +#define ARCHI_STDOUT_OFFSET 0x00006000 +#define ARCHI_RAB_CFG_OFFSET 0x00030000 + + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UART_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UART_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SPIM_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SPIM_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_RAB_CFG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_RAB_CFG_OFFSET ) + + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x1B000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_TIMER_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_TIMER_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + + +#define ARCHI_TRYX_CTRL_ADDR ( 0x10200BFC ) + + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/multino/properties.h b/sw/pulp-sdk/archi/include/archi/chips/multino/properties.h new file mode 100644 index 0000000..ee45c17 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/multino/properties.h @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_MULTINO_PROPERTIES_H__ +#define __ARCHI_CHIPS_MULTINO_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_NO_L1_TINY 1 + +#define ARCHI_L1_SIZE 262144 + +/* + * IP VERSIONS + */ + +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define EU_VERSION 3 +#define RISCV_VERSION 4 +#define GPIO_VERSION 2 +#define PADS_VERSION 2 +#define MCHAN_VERSION 6 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 2 +#define ARCHI_NB_CLUSTER 2 + + + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/oprecompkw/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/oprecompkw/memory_map.h new file mode 100644 index 0000000..c6eca7b --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/oprecompkw/memory_map.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_OPRECOMPKW_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_OPRECOMPKW_MEMORY_MAP_H__ + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + + +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + + + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/oprecompkw/properties.h b/sw/pulp-sdk/archi/include/archi/chips/oprecompkw/properties.h new file mode 100644 index 0000000..020a134 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/oprecompkw/properties.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_OPRECOMPKW_PROPERTIES_H__ +#define __ARCHI_CHIPS_OPRECOMPKW_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 + +#define ARCHI_L1_SIZE 65536 +#define ARCHI_NO_L1_TINY 1 + + +/* + * IP VERSIONS + */ + +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define EU_VERSION 3 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 +#define ARCHI_HAS_MCHAN_64 1 + + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulp/apb_soc_ctrl.h b/sw/pulp-sdk/archi/include/archi/chips/pulp/apb_soc_ctrl.h new file mode 100644 index 0000000..fc38a90 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulp/apb_soc_ctrl.h @@ -0,0 +1,116 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_PULP_APB_SOC_CTRL_H__ +#define __INCLUDE_ARCHI_CHIPS_PULP_APB_SOC_CTRL_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Value of pad bootsel +#define APB_SOC_BOOTSEL_OFFSET 0xc4 + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_bootsel_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_apb_soc_bootsel : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int bootsel ; // Value of pad bootsel +} __attribute__((packed)) apb_soc_apb_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); } +static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulp/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/pulp/memory_map.h new file mode 100644 index 0000000..8c12def --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulp/memory_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_PULP_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_PULP_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulp/properties.h b/sw/pulp-sdk/archi/include/archi/chips/pulp/properties.h new file mode 100644 index 0000000..87e24f3 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulp/properties.h @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_PULP_PROPERTIES_H__ +#define __ARCHI_CHIPS_PULP_PROPERTIES_H__ + +/* + * FPGA + */ + +#define ARCHI_FPGA_FREQUENCY 5000000 + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L2_MULTI 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 3 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 2 +#define APB_SOC_VERSION 3 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 7 +#define PADS_VERSION 2 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 +#define ARCHI_NB_CLUSTER 1 + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 +#define ARCHI_HAS_FC 1 + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulp_v1/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/pulp_v1/memory_map.h new file mode 100644 index 0000000..9e57e4d --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulp_v1/memory_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_PULP_V1_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_PULP_V1_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulp_v1/properties.h b/sw/pulp-sdk/archi/include/archi/chips/pulp_v1/properties.h new file mode 100644 index 0000000..4d37b57 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulp_v1/properties.h @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_PULP_V1_PROPERTIES_H__ +#define __ARCHI_CHIPS_PULP_V1_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 65536 + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 +#define PADS_VERSION 2 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/apb_soc_ctrl.h b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/apb_soc_ctrl.h new file mode 100644 index 0000000..f364de1 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/apb_soc_ctrl.h @@ -0,0 +1,116 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_PULPISSIMO_APB_SOC_CTRL_H__ +#define __INCLUDE_ARCHI_CHIPS_PULPISSIMO_APB_SOC_CTRL_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Value of pad bootsel +#define APB_SOC_BOOTSEL_OFFSET 0xc4 + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_bootsel_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_apb_soc_bootsel : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int bootsel ; // Value of pad bootsel +} __attribute__((packed)) apb_soc_apb_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); } +static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/memory_map.h new file mode 100644 index 0000000..4e226bb --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/memory_map.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_PULPISSIMO_MEMORY_MAP_H__ +#define __ARCHI_PULPISSIMO_MEMORY_MAP_H__ + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_FC_HWPE_OFFSET 0x0000C000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + + + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_OFFSET 0x00000400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/properties.h b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/properties.h new file mode 100644 index 0000000..c2fa2f2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo/properties.h @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_PULPISSIMO_PROPERTIES_H__ +#define __ARCHI_PULPISSIMO_PROPERTIES_H__ + +/* + * FPGA + */ + +#define ARCHI_FPGA_FREQUENCY 5000000 + + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 3 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 2 +#define APB_SOC_VERSION 3 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define HWME_VERSION 1 +#define PADS_VERSION 2 + + +/* + * CORE IDS + */ + +#define ARCHI_FC_CID 31 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulpissimo_v1/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo_v1/memory_map.h new file mode 100644 index 0000000..dd444b0 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo_v1/memory_map.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_PULPISSIMO_V1_MEMORY_MAP_H__ +#define __ARCHI_PULPISSIMO_V1_MEMORY_MAP_H__ + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_FC_HWPE_OFFSET 0x0000C000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + + + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_OFFSET 0x00000400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/pulpissimo_v1/properties.h b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo_v1/properties.h new file mode 100644 index 0000000..7203804 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/pulpissimo_v1/properties.h @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_PULPISSIMO_V1_PROPERTIES_H__ +#define __ARCHI_PULPISSIMO_V1_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 3 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define HWME_VERSION 1 +#define PADS_VERSION 2 + + +/* + * CORE IDS + */ + +#define ARCHI_FC_CID 31 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/quentin/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/quentin/memory_map.h new file mode 100644 index 0000000..ef5a9cc --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/quentin/memory_map.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_QUENTIN_MEMORY_MAP_H__ +#define __ARCHI_QUENTIN_MEMORY_MAP_H__ + + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00007000 + +#define ARCHI_L2_SCM_ADDR 0x1c007000 +#define ARCHI_L2_SCM_SIZE 0x00001000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_FC_HWPE_OFFSET 0x0000C000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_OFFSET 0x00000400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/quentin/properties.h b/sw/pulp-sdk/archi/include/archi/chips/quentin/properties.h new file mode 100644 index 0000000..6a87179 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/quentin/properties.h @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_QUENTIN_PROPERTIES_H__ +#define __ARCHI_QUENTIN_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L2_SCM 1 + + + +/* + * MEMORY ALIAS + */ + +// Alias is deactivated to allow putting the code and data in scm +//#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 3 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define XNE_VERSION 1 +#define PADS_VERSION 2 + + + +/* + * CORE IDS + */ + +#define ARCHI_FC_CID 31 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define ARCHI_GPIO_INTTYPE_GPIO(inttype) ((inttype)*16) +#define ARCHI_GPIO_INTTYPE_SIZE 2 +#define ARCHI_GPIO_INTTYPE_BIT(pad) (((pad) & 0xF) << 1) +#define ARCHI_GPIO_INTTYPE_GET(gpio,value) (((value) >> ARCHI_GPIO_INTTYPE_BIT(gpio)) & ((1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 0 // FIXME put it to the right value once the padframe is specified +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_SLEEP_CONTROL 0x104 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 8 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 8 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vega/apb_soc_ctrl.h b/sw/pulp-sdk/archi/include/archi/chips/vega/apb_soc_ctrl.h new file mode 100644 index 0000000..e07d9ad --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vega/apb_soc_ctrl.h @@ -0,0 +1,1581 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_VEGA_APB_SOC_CTRL_H__ +#define __INCLUDE_ARCHI_CHIPS_VEGA_APB_SOC_CTRL_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Core information register +#define APB_SOC_INFO_OFFSET 0x0 + +// Boot address +#define APB_SOC_FC_BOOT_OFFSET 0x4 + +// FC Fetch enable +#define APB_SOC_FC_FETCH_OFFSET 0x8 + +// Isolate cluster register +#define APB_SOC_CL_ISOLATE_OFFSET 0xc + +// Mux config register (pad 0-15) +#define APB_SOC_PADFUN0_OFFSET 0x10 + +// Mux config register (pad 16-31) +#define APB_SOC_PADFUN1_OFFSET 0x14 + +// Mux config register (pad 32-47) +#define APB_SOC_PADFUN2_OFFSET 0x18 + +// Mux config register (pad 48-63) +#define APB_SOC_PADFUN3_OFFSET 0x1c + +// Function register (pad 0 to 3) +#define APB_SOC_PADCFG0_OFFSET 0x20 + +// Function register (pad 4 to 7) +#define APB_SOC_PADCFG1_OFFSET 0x24 + +// Function register (pad 8 to 11) +#define APB_SOC_PADCFG2_OFFSET 0x28 + +// Function register (pad 12 to 15) +#define APB_SOC_PADCFG3_OFFSET 0x2c + +// Function register (pad 16 to 19) +#define APB_SOC_PADCFG4_OFFSET 0x30 + +// Function register (pad 20 to 23) +#define APB_SOC_PADCFG5_OFFSET 0x34 + +// Function register (pad 24 to 27) +#define APB_SOC_PADCFG6_OFFSET 0x38 + +// Function register (pad 28 to 31) +#define APB_SOC_PADCFG7_OFFSET 0x3c + +// Function register (pad 32 to 35) +#define APB_SOC_PADCFG8_OFFSET 0x40 + +// Function register (pad 36 to 39) +#define APB_SOC_PADCFG9_OFFSET 0x44 + +// Function register (pad 40 to 43) +#define APB_SOC_PADCFG10_OFFSET 0x48 + +// Function register (pad 44 to 47) +#define APB_SOC_PADCFG11_OFFSET 0x4c + +// Function register (pad 48 to 51) +#define APB_SOC_PADCFG12_OFFSET 0x50 + +// Function register (pad 52 to 55) +#define APB_SOC_PADCFG13_OFFSET 0x54 + +// Function register (pad 56 to 59) +#define APB_SOC_PADCFG14_OFFSET 0x58 + +// Function register (pad 60 to 63) +#define APB_SOC_PADCFG15_OFFSET 0x5c + +// Cluster busy register +#define APB_SOC_CL_BUSY_OFFSET 0x6c + +// JTAG external register +#define APB_SOC_JTAGREG_OFFSET 0x74 + +// Alias for SAFE_PMU_SLEEPCTRL +#define APB_SOC_SLEEP_CTRL_OFFSET 0x7c + +// Clock divider for I3C +#define APB_SOC_CLK_DIV_I3C_OFFSET 0x80 + +// EOC and chip status register +#define APB_SOC_CORESTATUS_OFFSET 0xa0 + +// EOC and chip status register read mirror +#define APB_SOC_CORESTATUS_RO_OFFSET 0xc0 + +// Value of pad bootsel +#define APB_SOC_BOOTSEL_OFFSET 0xc4 + +// Clear WD timer +#define APB_SOC_WD_CLR_OFFSET 0xc8 + +// Clock selection for SOC,Cluster and Periph +#define APB_SOC_CLK_SEL_OFFSET 0xd0 + +// SOC Clock Divider settings +#define APB_SOC_CLK_DIV_SOC_OFFSET 0xd4 + +// Cluster Clock Divider settings +#define APB_SOC_CLK_DIV_CLU_OFFSET 0xd8 + +// Peripheral Clock Divider Settings +#define APB_SOC_CLK_DIV_PER_OFFSET 0xdc + +// nan +#define APB_SOC_SUPERVISOR_DBG_OFFSET 0xe0 + +// nan +#define APB_SOC_RWM_GRP0_OFFSET 0xe4 + +// nan +#define APB_SOC_RWM_GRP1_OFFSET 0xe8 + +// nan +#define APB_SOC_RWM_GRP2_OFFSET 0xec + +// nan +#define APB_SOC_RWM_GRP3_OFFSET 0xf0 + +// nan +#define APB_SOC_RWM_GRP4_OFFSET 0xf4 + +// nan +#define APB_SOC_RWM_GRP5_OFFSET 0xf8 + +// nan +#define APB_SOC_RWM_GRP6_OFFSET 0xfc + +// Sleep modes configuration register +#define APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET 0x104 + +// Enables and configures WatchDog Timer +#define APB_SOC_SAFE_WD_OFFSET 0x110 + +// Sleep config register (pad 0-7) +#define APB_SOC_SAFE_SLEEPPADCFG0_OFFSET 0x150 + +// Sleep config register (pad 8-15) +#define APB_SOC_SAFE_SLEEPPADCFG1_OFFSET 0x154 + +// Config timings for NEVA +#define APB_SOC_SAFE_NEVACF_OFFSET 0x164 + +// General purpouse register AO +#define APB_SOC_SAFE_GPREG_OFFSET 0x170 + +// L2 standby configuration +#define APB_SOC_SAFE_L2_BTRIM_STDBY_OFFSET 0x174 + +// FLL2 and FLL3 power control +#define APB_SOC_SAFE_FLL_CTRL_OFFSET 0x178 + +// L1 power control +#define APB_SOC_SAFE_L1_PWR_CTRL_OFFSET 0x17c + +// L2 power control +#define APB_SOC_SAFE_L2_PWR_CTRL_OFFSET 0x180 + +// GPIO power domain pad input isolation register +#define APB_SOC_REG_GPIO_ISO_OFFSET 0x1c0 + +// CAM power domain pad input isolation register +#define APB_SOC_REG_CAM_ISO_OFFSET 0x1c4 + +// LVDS power domain pad input isolation register +#define APB_SOC_REG_LVDS_ISO_OFFSET 0x1c8 + + + +// +// REGISTERS FIELDS +// + +// Number of clusters (access: R) +#define APB_SOC_INFO_NB_CL_BIT 0 +#define APB_SOC_INFO_NB_CL_WIDTH 16 +#define APB_SOC_INFO_NB_CL_MASK 0xffff + +// Number of cores (access: R) +#define APB_SOC_INFO_NB_CORES_BIT 16 +#define APB_SOC_INFO_NB_CORES_WIDTH 16 +#define APB_SOC_INFO_NB_CORES_MASK 0xffff0000 + +// FC Boot Address (access: R/W) +#define APB_SOC_FC_BOOT_ADDR_BIT 0 +#define APB_SOC_FC_BOOT_ADDR_WIDTH 32 +#define APB_SOC_FC_BOOT_ADDR_MASK 0xffffffff + +// FC Fetch Enable (access: R/W) +#define APB_SOC_FC_FETCH_FC_FE_BIT 0 +#define APB_SOC_FC_FETCH_FC_FE_WIDTH 1 +#define APB_SOC_FC_FETCH_FC_FE_MASK 0x1 + +// Isolate cluster. Inhibits AXI transactions from cluster to SoC: - 1'b0: Disable - 1'b1: Enable (access: R/W) +#define APB_SOC_CL_ISOLATE_EN_BIT 0 +#define APB_SOC_CL_ISOLATE_EN_WIDTH 1 +#define APB_SOC_CL_ISOLATE_EN_MASK 0x1 + +// Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) (access: R) +#define APB_SOC_CL_BUSY_BUSY_BIT 0 +#define APB_SOC_CL_BUSY_BUSY_WIDTH 1 +#define APB_SOC_CL_BUSY_BUSY_MASK 0x1 + +// JTAG internal register used for synchronisation from external debugger (access: R/W) +#define APB_SOC_JTAGREG_INT_SYNC_BIT 0 +#define APB_SOC_JTAGREG_INT_SYNC_WIDTH 1 +#define APB_SOC_JTAGREG_INT_SYNC_MASK 0x1 + +// JTAG internal register used for selecting boot mode configuration from external debugger (access: R/W) +#define APB_SOC_JTAGREG_INT_BT_MD_BIT 1 +#define APB_SOC_JTAGREG_INT_BT_MD_WIDTH 3 +#define APB_SOC_JTAGREG_INT_BT_MD_MASK 0xe + +// JTAG external register used for synchronisation from external debugger (access: R) +#define APB_SOC_JTAGREG_EXT_SYNC_BIT 8 +#define APB_SOC_JTAGREG_EXT_SYNC_WIDTH 1 +#define APB_SOC_JTAGREG_EXT_SYNC_MASK 0x100 + +// JTAG external register used for selecting boot mode configuration from external debugger (access: R) +#define APB_SOC_JTAGREG_EXT_BT_MD_BIT 9 +#define APB_SOC_JTAGREG_EXT_BT_MD_WIDTH 3 +#define APB_SOC_JTAGREG_EXT_BT_MD_MASK 0xe00 + +// Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) (access: R) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT 0 +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH 32 +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_MASK 0xffffffff + +// EOC and chip status register (access: R/W) +#define APB_SOC_CORESTATUS_STATUS_BIT 0 +#define APB_SOC_CORESTATUS_STATUS_WIDTH 32 +#define APB_SOC_CORESTATUS_STATUS_MASK 0xffffffff + +// EOC and chip status register (access: R) +#define APB_SOC_CORESTATUS_RO_STATUS_BIT 0 +#define APB_SOC_CORESTATUS_RO_STATUS_WIDTH 32 +#define APB_SOC_CORESTATUS_RO_STATUS_MASK 0xffffffff + +// SoC domain clock selection: - 1b0: First FLL is used (FLL1) - 1b1: Second FLL is used (FLL2) (access: R/W) +#define APB_SOC_CLK_SEL_CLK_SOC_BIT 0 +#define APB_SOC_CLK_SEL_CLK_SOC_WIDTH 1 +#define APB_SOC_CLK_SEL_CLK_SOC_MASK 0x1 + +// Cluster domain clock selection: - 2b00: First FLL is used (FLL1) - 2b01: Second FLL is used (FLL2) - 2b10: Third FLL is used (FLL3) (access: R/W) +#define APB_SOC_CLK_SEL_CLK_CLUSTER_BIT 1 +#define APB_SOC_CLK_SEL_CLK_CLUSTER_WIDTH 2 +#define APB_SOC_CLK_SEL_CLK_CLUSTER_MASK 0x6 + +// User value which is kept retentive after wakeup (even in non-retentive sleep). This value is only partially interpreted by the ROM code (TBD) to distinguish betweem cold boot, non-retentive sleep and retentive sleep. (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_BIT 0 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_WIDTH 3 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_MASK 0x7 + +// Enable smart wake-up; - 1'b0; smart wake-up disabled - 1'b1: smart wake-up enabled (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_BIT 9 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_MASK 0x200 + +// Enable RTC wake-up; - 1'b0; rtc wake-up disabled - 1'b1: rtc wake-up enabled (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_BIT 10 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_MASK 0x400 + +// Select external wake-up mode (through dedicated pin): - 2'b00: rise event - 2'b01: fall event - 2'b10: high level - 2'b11: low level (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT 11 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH 2 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_MASK 0x1800 + +// Enable external wake-up (through dedicated pin); - 1'b0; external wake-up disabled - 1'b1: external wake-up enabled (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT 13 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_MASK 0x2000 + +// Power state of the MRAM to restore after warm boot - 1'b0: MRAM OFF - 1'b1: MRAM ON (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_BIT 14 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_MASK 0x4000 + +// Power state of the cluster to restore after warm boot - 1'b0: cluster OFF - 1'b1: cluster ON (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_BIT 15 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_WIDTH 1 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_MASK 0x8000 + +// Configure retention mode of L2 memory. There is one bit per cut: - 1'b0: Non retentive - 1'b1: Retentive (access: R/W) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_BIT 16 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_WIDTH 16 +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_MASK 0xffff0000 + +// Pad state when the chip is down with low-speed IOs ON: - 4b0000: Tristate with no pull-up and no pull-down - 4b0001: Tristate with pull-up - 4b0010: Tristate with pull-down - 4b0011: Drive 0 - 4b0100: Drive 1 (access: R/W) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_BIT 0 +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_WIDTH 4 +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_MASK 0xf + +// L2 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. (access: R/W) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_BIT 0 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_WIDTH 4 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_MASK 0xf + +// L2 cuts standby active low. One bit per L2 cut for 16 cuts, the cut is in standby when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. (access: R/W) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_BIT 4 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_WIDTH 16 +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_MASK 0xffff0 + +// FLL2 power down. The FLL is powered down when this bit is 1b1. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_BIT 0 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_MASK 0x1 + +// FLL3 power down. The FLL is powered down when this bit is 1b1. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_BIT 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_MASK 0x2 + +// FLL2 reset active low. The FLL is reset when this bit is 1b0. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_BIT 2 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_MASK 0x4 + +// FLL3 reset active low. The FLL is reset when this bit is 1b0. (access: R/W) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_BIT 3 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_WIDTH 1 +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_MASK 0x8 + +// L1 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. (access: R/W) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_BIT 0 +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_WIDTH 4 +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_MASK 0xf + +// L1 cuts standby active low. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. (access: R/W) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_BIT 4 +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_WIDTH 2 +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_MASK 0x30 + +// L1 power down. The corresponding L1 part is powered down when this bit is 1b1. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. (access: R/W) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_BIT 6 +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_WIDTH 2 +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_MASK 0xc0 + +// L2 VDDDE active low. One bit per L2 cut for 16 cuts, the cut periphery is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. (access: R/W) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_BIT 0 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_WIDTH 16 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_MASK 0xffff + +// L2 VDDME active low. One bit per L2 cut for 16 cuts, the cut array is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. (access: R/W) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_BIT 16 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_WIDTH 16 +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_MASK 0xffff0000 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int nb_cl :16; // Number of clusters + unsigned int nb_cores :16; // Number of cores + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_info_t; + +typedef union { + struct { + unsigned int addr :32; // FC Boot Address + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_fc_boot_t; + +typedef union { + struct { + unsigned int fc_fe :1 ; // FC Fetch Enable + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_fc_fetch_t; + +typedef union { + struct { + unsigned int en :1 ; // Isolate cluster. Inhibits AXI transactions from cluster to SoC: - 1'b0: Disable - 1'b1: Enable + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_cl_isolate_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padfun3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg4_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg5_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg6_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg7_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg8_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg9_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg10_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg11_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg12_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg13_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg14_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_padcfg15_t; + +typedef union { + struct { + unsigned int busy :1 ; // Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_cl_busy_t; + +typedef union { + struct { + unsigned int int_sync :1 ; // JTAG internal register used for synchronisation from external debugger + unsigned int int_bt_md :3 ; // JTAG internal register used for selecting boot mode configuration from external debugger + unsigned int padding0:4 ; + unsigned int ext_sync :1 ; // JTAG external register used for synchronisation from external debugger + unsigned int ext_bt_md :3 ; // JTAG external register used for selecting boot mode configuration from external debugger + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_jtagreg_t; + +typedef union { + struct { + unsigned int sleep_ctrl :32; // Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_sleep_ctrl_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_i3c_t; + +typedef union { + struct { + unsigned int status :32; // EOC and chip status register + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_corestatus_t; + +typedef union { + struct { + unsigned int status :32; // EOC and chip status register + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_corestatus_ro_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_bootsel_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_wd_clr_t; + +typedef union { + struct { + unsigned int clk_soc :1 ; // SoC domain clock selection: - 1b0: First FLL is used (FLL1) - 1b1: Second FLL is used (FLL2) + unsigned int clk_cluster :2 ; // Cluster domain clock selection: - 2b00: First FLL is used (FLL1) - 2b01: Second FLL is used (FLL2) - 2b10: Third FLL is used (FLL3) + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_sel_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_soc_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_clu_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_clk_div_per_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_supervisor_dbg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp4_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp5_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rwm_grp6_t; + +typedef union { + struct { + unsigned int reboot :3 ; // User value which is kept retentive after wakeup (even in non-retentive sleep). This value is only partially interpreted by the ROM code (TBD) to distinguish betweem cold boot, non-retentive sleep and retentive sleep. + unsigned int padding0:6 ; + unsigned int smartwake_en :1 ; // Enable smart wake-up; - 1'b0; smart wake-up disabled - 1'b1: smart wake-up enabled + unsigned int rtcwake_en :1 ; // Enable RTC wake-up; - 1'b0; rtc wake-up disabled - 1'b1: rtc wake-up enabled + unsigned int extwake_type :2 ; // Select external wake-up mode (through dedicated pin): - 2'b00: rise event - 2'b01: fall event - 2'b10: high level - 2'b11: low level + unsigned int extwake_en :1 ; // Enable external wake-up (through dedicated pin); - 1'b0; external wake-up disabled - 1'b1: external wake-up enabled + unsigned int mram_wakestate :1 ; // Power state of the MRAM to restore after warm boot - 1'b0: MRAM OFF - 1'b1: MRAM ON + unsigned int cluster_wakestate:1 ; // Power state of the cluster to restore after warm boot - 1'b0: cluster OFF - 1'b1: cluster ON + unsigned int ret_mem :16; // Configure retention mode of L2 memory. There is one bit per cut: - 1'b0: Non retentive - 1'b1: Retentive + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_pmu_sleepctrl_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_wd_t; + +typedef union { + struct { + unsigned int state :4 ; // Pad state when the chip is down with low-speed IOs ON: - 4b0000: Tristate with no pull-up and no pull-down - 4b0001: Tristate with pull-up - 4b0010: Tristate with pull-down - 4b0011: Drive 0 - 4b0100: Drive 1 + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_sleeppadcfg1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_nevacf_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_gpreg_t; + +typedef union { + struct { + unsigned int btrim :4 ; // L2 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. + unsigned int stdby_n :16; // L2 cuts standby active low. One bit per L2 cut for 16 cuts, the cut is in standby when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_l2_btrim_stdby_t; + +typedef union { + struct { + unsigned int fll2_pwd :1 ; // FLL2 power down. The FLL is powered down when this bit is 1b1. + unsigned int fll3_pwd :1 ; // FLL3 power down. The FLL is powered down when this bit is 1b1. + unsigned int fll2_rstb :1 ; // FLL2 reset active low. The FLL is reset when this bit is 1b0. + unsigned int fll3_rstb :1 ; // FLL3 reset active low. The FLL is reset when this bit is 1b0. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_fll_ctrl_t; + +typedef union { + struct { + unsigned int btrim :4 ; // L1 cuts bias trim. This code is forwarded to all cuts and defines the level of current when the cut is in standby mode. 4b0000 is the least amount of current and 4b1110 is the most amount. 4bxxx1 is disabling the bias. + unsigned int stdby_n :2 ; // L1 cuts standby active low. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. + unsigned int pwd :2 ; // L1 power down. The corresponding L1 part is powered down when this bit is 1b1. First bit is for first L1 64Kbytes and second bit for second L1 64Kbytes. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_l1_pwr_ctrl_t; + +typedef union { + struct { + unsigned int vddde_n :16; // L2 VDDDE active low. One bit per L2 cut for 16 cuts, the cut periphery is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. + unsigned int vddme_n :16; // L2 VDDME active low. One bit per L2 cut for 16 cuts, the cut array is supplied when its corresponding bit is 0. The 4 last bits are for the private banks and the rest for the shared banks. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_safe_l2_pwr_ctrl_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_gpio_iso_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_cam_iso_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_reg_lvds_iso_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_apb_soc_info : public vp::reg_32 +{ +public: + inline void nb_cl_set(uint32_t value) { this->set_field(value, APB_SOC_INFO_NB_CL_BIT, APB_SOC_INFO_NB_CL_WIDTH); } + inline uint32_t nb_cl_get() { return this->get_field(APB_SOC_INFO_NB_CL_BIT, APB_SOC_INFO_NB_CL_WIDTH); } + inline void nb_cores_set(uint32_t value) { this->set_field(value, APB_SOC_INFO_NB_CORES_BIT, APB_SOC_INFO_NB_CORES_WIDTH); } + inline uint32_t nb_cores_get() { return this->get_field(APB_SOC_INFO_NB_CORES_BIT, APB_SOC_INFO_NB_CORES_WIDTH); } +}; + +class vp_apb_soc_fc_boot : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, APB_SOC_FC_BOOT_ADDR_BIT, APB_SOC_FC_BOOT_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(APB_SOC_FC_BOOT_ADDR_BIT, APB_SOC_FC_BOOT_ADDR_WIDTH); } +}; + +class vp_apb_soc_fc_fetch : public vp::reg_32 +{ +public: + inline void fc_fe_set(uint32_t value) { this->set_field(value, APB_SOC_FC_FETCH_FC_FE_BIT, APB_SOC_FC_FETCH_FC_FE_WIDTH); } + inline uint32_t fc_fe_get() { return this->get_field(APB_SOC_FC_FETCH_FC_FE_BIT, APB_SOC_FC_FETCH_FC_FE_WIDTH); } +}; + +class vp_apb_soc_cl_isolate : public vp::reg_32 +{ +public: + inline void en_set(uint32_t value) { this->set_field(value, APB_SOC_CL_ISOLATE_EN_BIT, APB_SOC_CL_ISOLATE_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(APB_SOC_CL_ISOLATE_EN_BIT, APB_SOC_CL_ISOLATE_EN_WIDTH); } +}; + +class vp_apb_soc_padfun0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padfun1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padfun2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padfun3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg4 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg5 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg6 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg7 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg8 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg9 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg10 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg11 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg12 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg13 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg14 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_padcfg15 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_cl_busy : public vp::reg_32 +{ +public: + inline void busy_set(uint32_t value) { this->set_field(value, APB_SOC_CL_BUSY_BUSY_BIT, APB_SOC_CL_BUSY_BUSY_WIDTH); } + inline uint32_t busy_get() { return this->get_field(APB_SOC_CL_BUSY_BUSY_BIT, APB_SOC_CL_BUSY_BUSY_WIDTH); } +}; + +class vp_apb_soc_jtagreg : public vp::reg_32 +{ +public: + inline void int_sync_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_INT_SYNC_BIT, APB_SOC_JTAGREG_INT_SYNC_WIDTH); } + inline uint32_t int_sync_get() { return this->get_field(APB_SOC_JTAGREG_INT_SYNC_BIT, APB_SOC_JTAGREG_INT_SYNC_WIDTH); } + inline void int_bt_md_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_INT_BT_MD_BIT, APB_SOC_JTAGREG_INT_BT_MD_WIDTH); } + inline uint32_t int_bt_md_get() { return this->get_field(APB_SOC_JTAGREG_INT_BT_MD_BIT, APB_SOC_JTAGREG_INT_BT_MD_WIDTH); } + inline void ext_sync_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_EXT_SYNC_BIT, APB_SOC_JTAGREG_EXT_SYNC_WIDTH); } + inline uint32_t ext_sync_get() { return this->get_field(APB_SOC_JTAGREG_EXT_SYNC_BIT, APB_SOC_JTAGREG_EXT_SYNC_WIDTH); } + inline void ext_bt_md_set(uint32_t value) { this->set_field(value, APB_SOC_JTAGREG_EXT_BT_MD_BIT, APB_SOC_JTAGREG_EXT_BT_MD_WIDTH); } + inline uint32_t ext_bt_md_get() { return this->get_field(APB_SOC_JTAGREG_EXT_BT_MD_BIT, APB_SOC_JTAGREG_EXT_BT_MD_WIDTH); } +}; + +class vp_apb_soc_sleep_ctrl : public vp::reg_32 +{ +public: + inline void sleep_ctrl_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH); } + inline uint32_t sleep_ctrl_get() { return this->get_field(APB_SOC_SLEEP_CTRL_SLEEP_CTRL_BIT, APB_SOC_SLEEP_CTRL_SLEEP_CTRL_WIDTH); } +}; + +class vp_apb_soc_clk_div_i3c : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_corestatus : public vp::reg_32 +{ +public: + inline void status_set(uint32_t value) { this->set_field(value, APB_SOC_CORESTATUS_STATUS_BIT, APB_SOC_CORESTATUS_STATUS_WIDTH); } + inline uint32_t status_get() { return this->get_field(APB_SOC_CORESTATUS_STATUS_BIT, APB_SOC_CORESTATUS_STATUS_WIDTH); } +}; + +class vp_apb_soc_corestatus_ro : public vp::reg_32 +{ +public: + inline void status_set(uint32_t value) { this->set_field(value, APB_SOC_CORESTATUS_RO_STATUS_BIT, APB_SOC_CORESTATUS_RO_STATUS_WIDTH); } + inline uint32_t status_get() { return this->get_field(APB_SOC_CORESTATUS_RO_STATUS_BIT, APB_SOC_CORESTATUS_RO_STATUS_WIDTH); } +}; + +class vp_apb_soc_bootsel : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_wd_clr : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_clk_sel : public vp::reg_32 +{ +public: + inline void clk_soc_set(uint32_t value) { this->set_field(value, APB_SOC_CLK_SEL_CLK_SOC_BIT, APB_SOC_CLK_SEL_CLK_SOC_WIDTH); } + inline uint32_t clk_soc_get() { return this->get_field(APB_SOC_CLK_SEL_CLK_SOC_BIT, APB_SOC_CLK_SEL_CLK_SOC_WIDTH); } + inline void clk_cluster_set(uint32_t value) { this->set_field(value, APB_SOC_CLK_SEL_CLK_CLUSTER_BIT, APB_SOC_CLK_SEL_CLK_CLUSTER_WIDTH); } + inline uint32_t clk_cluster_get() { return this->get_field(APB_SOC_CLK_SEL_CLK_CLUSTER_BIT, APB_SOC_CLK_SEL_CLK_CLUSTER_WIDTH); } +}; + +class vp_apb_soc_clk_div_soc : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_clk_div_clu : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_clk_div_per : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_supervisor_dbg : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp0 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp2 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp3 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp4 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp5 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rwm_grp6 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_pmu_sleepctrl : public vp::reg_32 +{ +public: + inline void reboot_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_WIDTH); } + inline uint32_t reboot_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_WIDTH); } + inline void smartwake_en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_WIDTH); } + inline uint32_t smartwake_en_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_WIDTH); } + inline void rtcwake_en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_WIDTH); } + inline uint32_t rtcwake_en_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_WIDTH); } + inline void extwake_type_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH); } + inline uint32_t extwake_type_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_WIDTH); } + inline void extwake_en_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH); } + inline uint32_t extwake_en_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_WIDTH); } + inline void mram_wakestate_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_WIDTH); } + inline uint32_t mram_wakestate_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_WIDTH); } + inline void cluster_wakestate_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_WIDTH); } + inline uint32_t cluster_wakestate_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_WIDTH); } + inline void ret_mem_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_WIDTH); } + inline uint32_t ret_mem_get() { return this->get_field(APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_BIT, APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_WIDTH); } +}; + +class vp_apb_soc_safe_wd : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_sleeppadcfg0 : public vp::reg_32 +{ +public: + inline void state_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_SLEEPPADCFG0_STATE_BIT, APB_SOC_SAFE_SLEEPPADCFG0_STATE_WIDTH); } + inline uint32_t state_get() { return this->get_field(APB_SOC_SAFE_SLEEPPADCFG0_STATE_BIT, APB_SOC_SAFE_SLEEPPADCFG0_STATE_WIDTH); } +}; + +class vp_apb_soc_safe_sleeppadcfg1 : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_nevacf : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_gpreg : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_safe_l2_btrim_stdby : public vp::reg_32 +{ +public: + inline void btrim_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_WIDTH); } + inline uint32_t btrim_get() { return this->get_field(APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_WIDTH); } + inline void stdby_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_WIDTH); } + inline uint32_t stdby_n_get() { return this->get_field(APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_BIT, APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_WIDTH); } +}; + +class vp_apb_soc_safe_fll_ctrl : public vp::reg_32 +{ +public: + inline void fll2_pwd_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_WIDTH); } + inline uint32_t fll2_pwd_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_WIDTH); } + inline void fll3_pwd_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_WIDTH); } + inline uint32_t fll3_pwd_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_WIDTH); } + inline void fll2_rstb_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_WIDTH); } + inline uint32_t fll2_rstb_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_WIDTH); } + inline void fll3_rstb_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_WIDTH); } + inline uint32_t fll3_rstb_get() { return this->get_field(APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_BIT, APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_WIDTH); } +}; + +class vp_apb_soc_safe_l1_pwr_ctrl : public vp::reg_32 +{ +public: + inline void btrim_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_BIT, APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_WIDTH); } + inline uint32_t btrim_get() { return this->get_field(APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_BIT, APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_WIDTH); } + inline void stdby_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_BIT, APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_WIDTH); } + inline uint32_t stdby_n_get() { return this->get_field(APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_BIT, APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_WIDTH); } + inline void pwd_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L1_PWR_CTRL_PWD_BIT, APB_SOC_SAFE_L1_PWR_CTRL_PWD_WIDTH); } + inline uint32_t pwd_get() { return this->get_field(APB_SOC_SAFE_L1_PWR_CTRL_PWD_BIT, APB_SOC_SAFE_L1_PWR_CTRL_PWD_WIDTH); } +}; + +class vp_apb_soc_safe_l2_pwr_ctrl : public vp::reg_32 +{ +public: + inline void vddde_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_WIDTH); } + inline uint32_t vddde_n_get() { return this->get_field(APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_WIDTH); } + inline void vddme_n_set(uint32_t value) { this->set_field(value, APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_WIDTH); } + inline uint32_t vddme_n_get() { return this->get_field(APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_BIT, APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_WIDTH); } +}; + +class vp_apb_soc_reg_gpio_iso : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_reg_cam_iso : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_reg_lvds_iso : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int info ; // Core information register + unsigned int fc_boot ; // Boot address + unsigned int fc_fetch ; // FC Fetch enable + unsigned int cl_isolate ; // Isolate cluster register + unsigned int padfun0 ; // Mux config register (pad 0-15) + unsigned int padfun1 ; // Mux config register (pad 16-31) + unsigned int padfun2 ; // Mux config register (pad 32-47) + unsigned int padfun3 ; // Mux config register (pad 48-63) + unsigned int padcfg0 ; // Function register (pad 0 to 3) + unsigned int padcfg1 ; // Function register (pad 4 to 7) + unsigned int padcfg2 ; // Function register (pad 8 to 11) + unsigned int padcfg3 ; // Function register (pad 12 to 15) + unsigned int padcfg4 ; // Function register (pad 16 to 19) + unsigned int padcfg5 ; // Function register (pad 20 to 23) + unsigned int padcfg6 ; // Function register (pad 24 to 27) + unsigned int padcfg7 ; // Function register (pad 28 to 31) + unsigned int padcfg8 ; // Function register (pad 32 to 35) + unsigned int padcfg9 ; // Function register (pad 36 to 39) + unsigned int padcfg10 ; // Function register (pad 40 to 43) + unsigned int padcfg11 ; // Function register (pad 44 to 47) + unsigned int padcfg12 ; // Function register (pad 48 to 51) + unsigned int padcfg13 ; // Function register (pad 52 to 55) + unsigned int padcfg14 ; // Function register (pad 56 to 59) + unsigned int padcfg15 ; // Function register (pad 60 to 63) + unsigned int cl_busy ; // Cluster busy register + unsigned int jtagreg ; // JTAG external register + unsigned int sleep_ctrl ; // Alias for SAFE_PMU_SLEEPCTRL + unsigned int clk_div_i3c ; // Clock divider for I3C + unsigned int corestatus ; // EOC and chip status register + unsigned int corestatus_ro ; // EOC and chip status register read mirror + unsigned int bootsel ; // Value of pad bootsel + unsigned int wd_clr ; // Clear WD timer + unsigned int clk_sel ; // Clock selection for SOC,Cluster and Periph + unsigned int clk_div_soc ; // SOC Clock Divider settings + unsigned int clk_div_clu ; // Cluster Clock Divider settings + unsigned int clk_div_per ; // Peripheral Clock Divider Settings + unsigned int supervisor_dbg ; // nan + unsigned int rwm_grp0 ; // nan + unsigned int rwm_grp1 ; // nan + unsigned int rwm_grp2 ; // nan + unsigned int rwm_grp3 ; // nan + unsigned int rwm_grp4 ; // nan + unsigned int rwm_grp5 ; // nan + unsigned int rwm_grp6 ; // nan + unsigned int safe_pmu_sleepctrl; // Sleep modes configuration register + unsigned int safe_wd ; // Enables and configures WatchDog Timer + unsigned int safe_sleeppadcfg0; // Sleep config register (pad 0-7) + unsigned int safe_sleeppadcfg1; // Sleep config register (pad 8-15) + unsigned int safe_nevacf ; // Config timings for NEVA + unsigned int safe_gpreg ; // General purpouse register AO + unsigned int safe_l2_btrim_stdby; // L2 standby configuration + unsigned int safe_fll_ctrl ; // FLL2 and FLL3 power control + unsigned int safe_l1_pwr_ctrl; // L1 power control + unsigned int safe_l2_pwr_ctrl; // L2 power control + unsigned int reg_gpio_iso ; // GPIO power domain pad input isolation register + unsigned int reg_cam_iso ; // CAM power domain pad input isolation register + unsigned int reg_lvds_iso ; // LVDS power domain pad input isolation register +} __attribute__((packed)) apb_soc_apb_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t apb_soc_info_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_INFO_OFFSET); } +static inline void apb_soc_info_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_INFO_OFFSET, value); } + +static inline uint32_t apb_soc_fc_boot_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_FC_BOOT_OFFSET); } +static inline void apb_soc_fc_boot_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_FC_BOOT_OFFSET, value); } + +static inline uint32_t apb_soc_fc_fetch_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_FC_FETCH_OFFSET); } +static inline void apb_soc_fc_fetch_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_FC_FETCH_OFFSET, value); } + +static inline uint32_t apb_soc_cl_isolate_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CL_ISOLATE_OFFSET); } +static inline void apb_soc_cl_isolate_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CL_ISOLATE_OFFSET, value); } + +static inline uint32_t apb_soc_padfun0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN0_OFFSET); } +static inline void apb_soc_padfun0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN0_OFFSET, value); } + +static inline uint32_t apb_soc_padfun1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN1_OFFSET); } +static inline void apb_soc_padfun1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN1_OFFSET, value); } + +static inline uint32_t apb_soc_padfun2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN2_OFFSET); } +static inline void apb_soc_padfun2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN2_OFFSET, value); } + +static inline uint32_t apb_soc_padfun3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADFUN3_OFFSET); } +static inline void apb_soc_padfun3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADFUN3_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG0_OFFSET); } +static inline void apb_soc_padcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG0_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG1_OFFSET); } +static inline void apb_soc_padcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG1_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG2_OFFSET); } +static inline void apb_soc_padcfg2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG2_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG3_OFFSET); } +static inline void apb_soc_padcfg3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG3_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg4_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG4_OFFSET); } +static inline void apb_soc_padcfg4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG4_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg5_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG5_OFFSET); } +static inline void apb_soc_padcfg5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG5_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg6_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG6_OFFSET); } +static inline void apb_soc_padcfg6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG6_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg7_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG7_OFFSET); } +static inline void apb_soc_padcfg7_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG7_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg8_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG8_OFFSET); } +static inline void apb_soc_padcfg8_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG8_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg9_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG9_OFFSET); } +static inline void apb_soc_padcfg9_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG9_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg10_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG10_OFFSET); } +static inline void apb_soc_padcfg10_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG10_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg11_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG11_OFFSET); } +static inline void apb_soc_padcfg11_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG11_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg12_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG12_OFFSET); } +static inline void apb_soc_padcfg12_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG12_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg13_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG13_OFFSET); } +static inline void apb_soc_padcfg13_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG13_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg14_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG14_OFFSET); } +static inline void apb_soc_padcfg14_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG14_OFFSET, value); } + +static inline uint32_t apb_soc_padcfg15_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_PADCFG15_OFFSET); } +static inline void apb_soc_padcfg15_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_PADCFG15_OFFSET, value); } + +static inline uint32_t apb_soc_cl_busy_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CL_BUSY_OFFSET); } +static inline void apb_soc_cl_busy_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CL_BUSY_OFFSET, value); } + +static inline uint32_t apb_soc_jtagreg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_JTAGREG_OFFSET); } +static inline void apb_soc_jtagreg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_JTAGREG_OFFSET, value); } + +static inline uint32_t apb_soc_sleep_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SLEEP_CTRL_OFFSET); } +static inline void apb_soc_sleep_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SLEEP_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_i3c_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_I3C_OFFSET); } +static inline void apb_soc_clk_div_i3c_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_I3C_OFFSET, value); } + +static inline uint32_t apb_soc_corestatus_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CORESTATUS_OFFSET); } +static inline void apb_soc_corestatus_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CORESTATUS_OFFSET, value); } + +static inline uint32_t apb_soc_corestatus_ro_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CORESTATUS_RO_OFFSET); } +static inline void apb_soc_corestatus_ro_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CORESTATUS_RO_OFFSET, value); } + +static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); } +static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); } + +static inline uint32_t apb_soc_wd_clr_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_WD_CLR_OFFSET); } +static inline void apb_soc_wd_clr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_WD_CLR_OFFSET, value); } + +static inline uint32_t apb_soc_clk_sel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_SEL_OFFSET); } +static inline void apb_soc_clk_sel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_SEL_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_soc_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_SOC_OFFSET); } +static inline void apb_soc_clk_div_soc_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_SOC_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_clu_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_CLU_OFFSET); } +static inline void apb_soc_clk_div_clu_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_CLU_OFFSET, value); } + +static inline uint32_t apb_soc_clk_div_per_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_CLK_DIV_PER_OFFSET); } +static inline void apb_soc_clk_div_per_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_CLK_DIV_PER_OFFSET, value); } + +static inline uint32_t apb_soc_supervisor_dbg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SUPERVISOR_DBG_OFFSET); } +static inline void apb_soc_supervisor_dbg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SUPERVISOR_DBG_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP0_OFFSET); } +static inline void apb_soc_rwm_grp0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP0_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP1_OFFSET); } +static inline void apb_soc_rwm_grp1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP1_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp2_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP2_OFFSET); } +static inline void apb_soc_rwm_grp2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP2_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp3_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP3_OFFSET); } +static inline void apb_soc_rwm_grp3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP3_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp4_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP4_OFFSET); } +static inline void apb_soc_rwm_grp4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP4_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp5_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP5_OFFSET); } +static inline void apb_soc_rwm_grp5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP5_OFFSET, value); } + +static inline uint32_t apb_soc_rwm_grp6_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RWM_GRP6_OFFSET); } +static inline void apb_soc_rwm_grp6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RWM_GRP6_OFFSET, value); } + +static inline uint32_t apb_soc_safe_pmu_sleepctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET); } +static inline void apb_soc_safe_pmu_sleepctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_PMU_SLEEPCTRL_OFFSET, value); } + +static inline uint32_t apb_soc_safe_wd_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_WD_OFFSET); } +static inline void apb_soc_safe_wd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_WD_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg0_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG0_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG0_OFFSET, value); } + +static inline uint32_t apb_soc_safe_sleeppadcfg1_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_SLEEPPADCFG1_OFFSET); } +static inline void apb_soc_safe_sleeppadcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_SLEEPPADCFG1_OFFSET, value); } + +static inline uint32_t apb_soc_safe_nevacf_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_NEVACF_OFFSET); } +static inline void apb_soc_safe_nevacf_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_NEVACF_OFFSET, value); } + +static inline uint32_t apb_soc_safe_gpreg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_GPREG_OFFSET); } +static inline void apb_soc_safe_gpreg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_GPREG_OFFSET, value); } + +static inline uint32_t apb_soc_safe_l2_btrim_stdby_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_L2_BTRIM_STDBY_OFFSET); } +static inline void apb_soc_safe_l2_btrim_stdby_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_L2_BTRIM_STDBY_OFFSET, value); } + +static inline uint32_t apb_soc_safe_fll_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_FLL_CTRL_OFFSET); } +static inline void apb_soc_safe_fll_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_FLL_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_safe_l1_pwr_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_L1_PWR_CTRL_OFFSET); } +static inline void apb_soc_safe_l1_pwr_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_L1_PWR_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_safe_l2_pwr_ctrl_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SAFE_L2_PWR_CTRL_OFFSET); } +static inline void apb_soc_safe_l2_pwr_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SAFE_L2_PWR_CTRL_OFFSET, value); } + +static inline uint32_t apb_soc_reg_gpio_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_GPIO_ISO_OFFSET); } +static inline void apb_soc_reg_gpio_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_GPIO_ISO_OFFSET, value); } + +static inline uint32_t apb_soc_reg_cam_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_CAM_ISO_OFFSET); } +static inline void apb_soc_reg_cam_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_CAM_ISO_OFFSET, value); } + +static inline uint32_t apb_soc_reg_lvds_iso_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_REG_LVDS_ISO_OFFSET); } +static inline void apb_soc_reg_lvds_iso_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_REG_LVDS_ISO_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define APB_SOC_INFO_NB_CL_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define APB_SOC_INFO_NB_CL_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define APB_SOC_INFO_NB_CL_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define APB_SOC_INFO_NB_CL(val) ((val) << 0) + +#define APB_SOC_INFO_NB_CORES_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define APB_SOC_INFO_NB_CORES_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define APB_SOC_INFO_NB_CORES_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define APB_SOC_INFO_NB_CORES(val) ((val) << 16) + +#define APB_SOC_FC_BOOT_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_FC_BOOT_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_FC_BOOT_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_FC_BOOT_ADDR(val) ((val) << 0) + +#define APB_SOC_FC_FETCH_FC_FE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_FC_FETCH_FC_FE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_FC_FETCH_FC_FE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_FC_FETCH_FC_FE(val) ((val) << 0) + +#define APB_SOC_CL_ISOLATE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CL_ISOLATE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CL_ISOLATE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CL_ISOLATE_EN(val) ((val) << 0) + +#define APB_SOC_CL_BUSY_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CL_BUSY_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CL_BUSY_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CL_BUSY_BUSY(val) ((val) << 0) + +#define APB_SOC_JTAGREG_INT_SYNC_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_JTAGREG_INT_SYNC(val) ((val) << 0) + +#define APB_SOC_JTAGREG_INT_BT_MD_GET(value) (ARCHI_BEXTRACTU((value),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD_GETS(value) (ARCHI_BEXTRACT((value),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD_SET(value,field) (ARCHI_BINSERT((value),(field),3,1)) +#define APB_SOC_JTAGREG_INT_BT_MD(val) ((val) << 1) + +#define APB_SOC_JTAGREG_EXT_SYNC_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define APB_SOC_JTAGREG_EXT_SYNC(val) ((val) << 8) + +#define APB_SOC_JTAGREG_EXT_BT_MD_GET(value) (ARCHI_BEXTRACTU((value),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD_GETS(value) (ARCHI_BEXTRACT((value),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD_SET(value,field) (ARCHI_BINSERT((value),(field),3,9)) +#define APB_SOC_JTAGREG_EXT_BT_MD(val) ((val) << 9) + +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_SLEEP_CTRL_SLEEP_CTRL(val) ((val) << 0) + +#define APB_SOC_CORESTATUS_STATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_CORESTATUS_STATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_CORESTATUS_STATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_CORESTATUS_STATUS(val) ((val) << 0) + +#define APB_SOC_CORESTATUS_RO_STATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define APB_SOC_CORESTATUS_RO_STATUS(val) ((val) << 0) + +#define APB_SOC_CLK_SEL_CLK_SOC_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_CLK_SEL_CLK_SOC_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_CLK_SEL_CLK_SOC_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_CLK_SEL_CLK_SOC(val) ((val) << 0) + +#define APB_SOC_CLK_SEL_CLK_CLUSTER_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define APB_SOC_CLK_SEL_CLK_CLUSTER_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define APB_SOC_CLK_SEL_CLK_CLUSTER_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define APB_SOC_CLK_SEL_CLK_CLUSTER(val) ((val) << 1) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_REBOOT(val) ((val) << 0) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_SMARTWAKE_EN(val) ((val) << 9) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,10)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,10)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,10)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RTCWAKE_EN(val) ((val) << 10) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_GET(value) (ARCHI_BEXTRACTU((value),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_GETS(value) (ARCHI_BEXTRACT((value),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_SET(value,field) (ARCHI_BINSERT((value),(field),2,11)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE(val) ((val) << 11) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN(val) ((val) << 13) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_GET(value) (ARCHI_BEXTRACTU((value),1,14)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_GETS(value) (ARCHI_BEXTRACT((value),1,14)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,14)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_MRAM_WAKESTATE(val) ((val) << 14) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_CLUSTER_WAKESTATE(val) ((val) << 15) + +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define APB_SOC_SAFE_PMU_SLEEPCTRL_RET_MEM(val) ((val) << 16) + +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define APB_SOC_SAFE_SLEEPPADCFG0_STATE(val) ((val) << 0) + +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_BTRIM(val) ((val) << 0) + +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_GET(value) (ARCHI_BEXTRACTU((value),16,4)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_GETS(value) (ARCHI_BEXTRACT((value),16,4)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N_SET(value,field) (ARCHI_BINSERT((value),(field),16,4)) +#define APB_SOC_SAFE_L2_BTRIM_STDBY_STDBY_N(val) ((val) << 4) + +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_PWD(val) ((val) << 0) + +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_PWD(val) ((val) << 1) + +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define APB_SOC_SAFE_FLL_CTRL_FLL2_RSTB(val) ((val) << 2) + +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define APB_SOC_SAFE_FLL_CTRL_FLL3_RSTB(val) ((val) << 3) + +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define APB_SOC_SAFE_L1_PWR_CTRL_BTRIM(val) ((val) << 0) + +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_GET(value) (ARCHI_BEXTRACTU((value),2,4)) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_GETS(value) (ARCHI_BEXTRACT((value),2,4)) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N_SET(value,field) (ARCHI_BINSERT((value),(field),2,4)) +#define APB_SOC_SAFE_L1_PWR_CTRL_STDBY_N(val) ((val) << 4) + +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_GET(value) (ARCHI_BEXTRACTU((value),2,6)) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_GETS(value) (ARCHI_BEXTRACT((value),2,6)) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD_SET(value,field) (ARCHI_BINSERT((value),(field),2,6)) +#define APB_SOC_SAFE_L1_PWR_CTRL_PWD(val) ((val) << 6) + +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDDE_N(val) ((val) << 0) + +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define APB_SOC_SAFE_L2_PWR_CTRL_VDDME_N(val) ((val) << 16) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vega/memory_map.h.in b/sw/pulp-sdk/archi/include/archi/chips/vega/memory_map.h.in new file mode 100644 index 0000000..63c751d --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vega/memory_map.h.in @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VEGA_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_VEGA_MEMORY_MAP_H__ + + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE @l2_shared_size@ + + + +/* + * MRAM + */ + +#define ARCHI_MRAM_ADDR 0x1D000000 + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_CVP_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_PWM_OFFSET 0x00005000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 /// FIXME: not soc eu but soc event generator +#define ARCHI_PMU_OFFSET 0x00007000 +#define ARCHI_RTC_BASE_OFFSET 0x00008000 +#define ARCHI_FC_ICACHE_OFFSET 0x00008800 +#define ARCHI_FC_ITC_OFFSET 0x00009000 +#define ARCHI_I3C0_OFFSET 0x0000A000 +#define ARCHI_I3C1_OFFSET 0x0000A800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_FC_TIMER1_OFFSET 0x0000B800 +#define ARCHI_DPHY_OFFSET 0x0000C000 +#define ARCHI_CSI2_OFFSET 0x0000D000 +#define ARCHI_MPU_OFFSET 0x0000E000 +#define ARCHI_EFUSE_OFFSET 0x0000F000 +#define ARCHI_DEBUG_OFFSET 0x00010000 +#define ARCHI_STDOUT_OFFSET 0x00020000 +#define ARCHI_QUIDDIKEY_OFFSET 0x00021000 + +#define ARCHI_FLL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FLL_OFFSET ) +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_PWM_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PWM_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_PMU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PMU_OFFSET ) +#define ARCHI_RTC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_RTC_BASE_OFFSET ) +#define ARCHI_FC_ICACHE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ICACHE_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_I3C0_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_I3C0_OFFSET ) +#define ARCHI_I3C1_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_I3C1_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +// #define ARCHI_FC_TIMER1_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER1_OFFSET ) +#define ARCHI_DPHY_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_DPHY_OFFSET ) +#define ARCHI_CSI2_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_CSI2_OFFSET ) +#define ARCHI_MPU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_MPU_OFFSET ) +#define ARCHI_EFUSE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_EFUSE_OFFSET ) +#define ARCHI_DEBUG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_DEBUG_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_QUIDDIKEY_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_QUIDDIKEY_OFFSET ) + + + +// VEGA HAL Handles definition +#define QUIDDIKEY_HANDLE ((halQuiddikeyHandle_t *)(ARCHI_QUIDDIKEY_ADDR)) +#define CSI2_HANDLE ((halCsi2Handle_t *)(ARCHI_CSI2_ADDR)) +#define DPHY_HANDLE ((halDphyHandle_t *)(ARCHI_DPHY_ADDR)) + +#define UDMA_CSI2_HANDLE(id) ((plpUdmaCsi2Handle_t *)(ARCHI_UDMA_ADDR + UDMA_CSI2_OFFSET(id))) + + + + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + +/* + * FC + */ +// NOTE: they are all in SOC PERIPH now + +#define ARCHI_FC_ADDR 0x00000000 +// #define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vega/pmu.h b/sw/pulp-sdk/archi/include/archi/chips/vega/pmu.h new file mode 100644 index 0000000..01155f7 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vega/pmu.h @@ -0,0 +1,510 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_VEGA_PMU_H__ +#define __INCLUDE_ARCHI_CHIPS_VEGA_PMU_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_pmu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu0 +// + +#define PMU_ICU0_OFFSET 0x2 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu0_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu1 +// + +#define PMU_ICU1_OFFSET 0x3 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu1_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP dmu0 +// + +#define PMU_DMU0_OFFSET 0x4 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_dmu0_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu_soc +// + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// CUSTOM FIELDS +// +#define PMU_SOC_ON_NV 0x00 +#define PMU_SOC_ON_LV 0x01 +#define PMU_SOC_RET_OFF 0x02 +#define PMU_SOC_RET_NV 0x03 +#define PMU_SOC_RET_LV 0x04 +#define PMU_SOC_RET_RV 0x05 +#define PMU_SOC_EXT_OFF 0x06 +#define PMU_SOC_EXT_NV 0x07 +#define PMU_SOC_EXT_LV 0x08 +#define PMU_SOC_EXT_RV 0x09 +#define PMU_SOC_CKOFF_NV 0x11 +#define PMU_SOC_CKOFF_LV 0x12 +#define PMU_SOC_CKOFF_RV 0x13 + + + +// +// GROUP icu_cluster +// + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu_cluster_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// CUSTOM FIELDS +// +#define PMU_CLUSTER_ON_NV 0x00 +#define PMU_CLUSTER_ON_LV 0x01 +#define PMU_CLUSTER_RET_OFF 0x02 +#define PMU_CLUSTER_RET_NV 0x03 +#define PMU_CLUSTER_RET_LV 0x04 +#define PMU_CLUSTER_RET_RV 0x05 +#define PMU_CLUSTER_EXT_OFF 0x06 +#define PMU_CLUSTER_EXT_NV 0x07 +#define PMU_CLUSTER_EXT_LV 0x08 +#define PMU_CLUSTER_EXT_RV 0x09 +#define PMU_CLUSTER_CKOFF_NV 0x11 +#define PMU_CLUSTER_CKOFF_LV 0x12 +#define PMU_CLUSTER_CKOFF_RV 0x13 + + + +// +// CUSTOM FIELDS +// +#define PMU_BOOT 0x01 +#define PMU_SOC_ACTIVE_NV 0x01 +#define PMU_SOC_ACTIVE_LV 0x02 +#define PMU_SOC_CLUSTER_ACTIVE_NV 0x04 +#define PMU_SOC_CLUSTER_ACTIVE_LV 0x08 +#define PMU_DEEP_SLEEP_ALL_OFF 0x10 +#define PMU_DEEP_SLEEP_RETENTIVE 0x20 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vega/properties.h b/sw/pulp-sdk/archi/include/archi/chips/vega/properties.h new file mode 100644 index 0000000..4897580 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vega/properties.h @@ -0,0 +1,347 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VEGA_PROPERTIES_H__ +#define __ARCHI_CHIPS_VEGA_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 0x20000 + +#define ARCHI_MEMORY_POWER 1 + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define FLL_VERSION 1 +#define GPIO_VERSION 2 +#define UDMA_VERSION 3 +#define PERIPH_VERSION 3 +#define APB_SOC_VERSION 3 +#define ADV_TIMER_VERSION 1 +#define SOC_EU_VERSION 2 +#define PMU_VERSION 3 +#define FC_ICACHE_CTRL_VERSION 2 +#define ITC_VERSION 1 +#define I3C_VERSION 1 +#define TIMER_VERSION 2 +#define DPHY_VERSION 1 +#define CSI2_VERSION 1 +#define MPU_VERSION 1 +#define EFUSE_VERSION 1 +#define DEBUG_VERSION 1 +#define STDOUT_VERSION 2 +#define QUIDDIKEY_VERSION 1 +#define ROM_VERSION 2 +#define RTC_VERSION 1 + +#define EU_VERSION 3 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 7 +#define HWCE_VERSION 5 + +#define CL_CTRL_VERSION 2 +#define PADS_VERSION 2 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_CL_CID 0 + +// TAS = Test&Set +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_HAS_CC 1 +#define ARCHI_CC_CORE_ID 8 +#define ARCHI_CLUSTER_NB_PE 8 +#define ARCHI_HAS_CLUSTER_CLK_GATE 1 + + +/* + * CLUSTER EVENT UNIT + */ + +//#define ARCHI_HAS_NO_BARRIER 1 +//#define ARCHI_HAS_NO_DISPATCH 1 +//#define ARCHI_HAS_NO_MUTEX 1 + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 +#define ARCHI_FC_HAS_ICACHE 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0x80 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/fll.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/fll.h new file mode 100644 index 0000000..eae92ee --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/fll.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC3_FLL_H__ +#define __ARCHI_CHIPS_VIVOSOC3_FLL_H__ + +// register address offsets +#define FLL_CONTROL_OFFSET 0x044 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FLL_RESET_OFFSET 0x048 +#define FLL_GPIO_OUTPUT 0x104 + +#define FLL_OFFSET 0x040 // base addr 0x1A100000 (ARCHI_SOC_PERIPHERALS_ADDR) + +#define FLL_SET_SEL_OFFSET 0x000 // base addr 0x1A100000 + fll * FLL_OFFSET +#define FLL_REF_CLK_OFFSET 0x004 +#define FLL_FSM_OBS_OFFSET 0x008 +#define FLL_SHARED_CONFIG_OFFSET 0x00C +#define FLL_SET_OFFSET 0x00C +#define FLL_FREQ_REGULATION_OFFSET 0x010 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CLK_GOOD_OFFSET 0x014 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CONFIG_OFFSET 0x018 // + set * FLL_SET_OFFSET +#define FLL_OBSERVATION_OFFSET 0x100 + +#define FLL_ANALOG_CLKIPC_OFFSET 0x4638 // base addr ARCHI_ANALOG_ADDR + +// register bitfields +#define FLL_SET_RSS_BIT 0 +#define FLL_SET_RSS_WIDTH 2 +#define FLL_SET_RSS_MASK (0x0003) + + +#define FLL_FREQ_REGULATION_LOW_BIT 0 +#define FLL_FREQ_REGULATION_LOW_WIDTH 14 +#define FLL_FREQ_REGULATION_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_REGULATION_HIGH_BIT 16 +#define FLL_FREQ_REGULATION_HIGH_WIDTH 14 +#define FLL_FREQ_REGULATION_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CLK_GOOD_LOW_BIT 0 +#define FLL_FREQ_CLK_GOOD_LOW_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_CLK_GOOD_HIGH_BIT 16 +#define FLL_FREQ_CLK_GOOD_HIGH_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CONFIG_LEVEL_BIT 0 +#define FLL_FREQ_CONFIG_LEVEL_WIDTH 4 +#define FLL_FREQ_CONFIG_LEVEL_MASK (0x0000000F) + +#define FLL_FREQ_CONFIG_DCO_LSB_BIT 4 +#define FLL_FREQ_CONFIG_DCO_LSB_WIDTH 3 +#define FLL_FREQ_CONFIG_DCO_LSB_MASK (0x00000070) + +#define FLL_FREQ_CONFIG_DCO_MSB_BIT 8 +#define FLL_FREQ_CONFIG_DCO_MSB_WIDTH 6 +#define FLL_FREQ_CONFIG_DCO_MSB_MASK (0x00003F00) + +#define FLL_FREQ_CONFIG_OL_BIT 16 +#define FLL_FREQ_CONFIG_OL_WIDTH 1 +#define FLL_FREQ_CONFIG_OL_MASK (0x00010000) + + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rss:1; /* Register set selection, 0b00 or 0b01 */ + unsigned int reserved_0:31; + }; + unsigned int raw; +} fll_reg_rss_t; + +typedef union { + struct { + unsigned int nref_reg_low:14; /* Regulation, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_reg_high:14; /* Regulation, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr0_t; + +typedef union { + struct { + unsigned int nref_cg_low:14; /* Clock good, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_cg_high:14; /* Clock good, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr1_t; + +typedef union { + struct { + unsigned int level:4; /* Start level of binary search, reset value: 0x0 */ + unsigned int dco_lsb:3; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_0:1; + unsigned int dco_msb:6; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_1:2; + unsigned int open_loop:1; /* Open-loop operation */ + unsigned int reserved_2:15; + }; + unsigned int raw; +} fll_reg_fcr2_t; + +#endif + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/freq.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/freq.h new file mode 100644 index 0000000..66506a6 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/freq.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC3_FREQ_H__ +#define __ARCHI_CHIPS_VIVOSOC3_FREQ_H__ + +// register address offsets +#define FREQ_CLK_TREE_CONF_GLOBAL_OFFSET 0x040 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FREQ_CLK_TREE_CONF_CL_OFFSET 0x050 +#define FREQ_CLK_TREE_CONF_SOC_OFFSET 0x054 +#define FREQ_CLK_TREE_CONF_PER_OFFSET 0x058 +#define FREQ_CLK_TREE_CONF_PM_OFFSET 0x05C + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/memory_map.h new file mode 100644 index 0000000..e4258d5 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/memory_map.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC3_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_VIVOSOC3_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00004000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c004000 +#define ARCHI_L2_PRIV1_SIZE 0x00004000 + +#define ARCHI_L2_SHARED_ADDR 0x1c008000 +#define ARCHI_L2_SHARED_SIZE 0x00010000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + + +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009000 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 +#define ARCHI_ANALOG_OFFSET 0x00010000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_ANALOG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_ANALOG_OFFSET ) + + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/properties.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/properties.h new file mode 100644 index 0000000..1f6754b --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3/properties.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC3_PROPERTIES_H__ +#define __ARCHI_CHIPS_VIVOSOC3_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 32768 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 +#define PADS_VERSION 2 +#define FLL_VERSION 1 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 + + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 2 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +// PADs configuration is made of 8bits out of which only the first 3 are used +// bit0 enable pull UP +// bit1 enable pull DOWN +// bit2 enable ST +// bit3..7 not used + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +// aliases +#define APB_SOC_PADS_CONFIG APB_SOC_PADCFG0_OFFSET + +// HAL compatibility definitions, functions not supported +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C +#define APB_SOC_BUSY_OFFSET 0x6C +#define APB_SOC_JTAG_REG 0x74 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/fll.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/fll.h new file mode 100644 index 0000000..c1ce3ea --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/fll.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC3_1_FLL_H__ +#define __ARCHI_CHIPS_VIVOSOC3_1_FLL_H__ + +// register address offsets +#define FLL_CONTROL_OFFSET 0x044 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FLL_RESET_OFFSET 0x048 +#define FLL_GPIO_OUTPUT 0x104 + +#define FLL_OFFSET 0x040 // base addr 0x1A100000 (ARCHI_SOC_PERIPHERALS_ADDR) + +#define FLL_SET_SEL_OFFSET 0x000 // base addr 0x1A100000 + fll * FLL_OFFSET +#define FLL_REF_CLK_OFFSET 0x004 +#define FLL_FSM_OBS_OFFSET 0x008 +#define FLL_SHARED_CONFIG_OFFSET 0x00C +#define FLL_SET_OFFSET 0x00C +#define FLL_FREQ_REGULATION_OFFSET 0x010 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CLK_GOOD_OFFSET 0x014 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CONFIG_OFFSET 0x018 // + set * FLL_SET_OFFSET +#define FLL_OBSERVATION_OFFSET 0x100 + +#define FLL_ANALOG_CLKIPC_OFFSET 0x4638 // base addr ARCHI_ANALOG_ADDR + +// register bitfields +#define FLL_SET_RSS_BIT 0 +#define FLL_SET_RSS_WIDTH 2 +#define FLL_SET_RSS_MASK (0x0003) + + +#define FLL_FREQ_REGULATION_LOW_BIT 0 +#define FLL_FREQ_REGULATION_LOW_WIDTH 14 +#define FLL_FREQ_REGULATION_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_REGULATION_HIGH_BIT 16 +#define FLL_FREQ_REGULATION_HIGH_WIDTH 14 +#define FLL_FREQ_REGULATION_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CLK_GOOD_LOW_BIT 0 +#define FLL_FREQ_CLK_GOOD_LOW_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_CLK_GOOD_HIGH_BIT 16 +#define FLL_FREQ_CLK_GOOD_HIGH_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CONFIG_LEVEL_BIT 0 +#define FLL_FREQ_CONFIG_LEVEL_WIDTH 4 +#define FLL_FREQ_CONFIG_LEVEL_MASK (0x0000000F) + +#define FLL_FREQ_CONFIG_DCO_LSB_BIT 4 +#define FLL_FREQ_CONFIG_DCO_LSB_WIDTH 3 +#define FLL_FREQ_CONFIG_DCO_LSB_MASK (0x00000070) + +#define FLL_FREQ_CONFIG_DCO_MSB_BIT 8 +#define FLL_FREQ_CONFIG_DCO_MSB_WIDTH 6 +#define FLL_FREQ_CONFIG_DCO_MSB_MASK (0x00003F00) + +#define FLL_FREQ_CONFIG_OL_BIT 16 +#define FLL_FREQ_CONFIG_OL_WIDTH 1 +#define FLL_FREQ_CONFIG_OL_MASK (0x00010000) + + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rss:1; /* Register set selection, 0b00 or 0b01 */ + unsigned int reserved_0:31; + }; + unsigned int raw; +} fll_reg_rss_t; + +typedef union { + struct { + unsigned int nref_reg_low:14; /* Regulation, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_reg_high:14; /* Regulation, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr0_t; + +typedef union { + struct { + unsigned int nref_cg_low:14; /* Clock good, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_cg_high:14; /* Clock good, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr1_t; + +typedef union { + struct { + unsigned int level:4; /* Start level of binary search, reset value: 0x0 */ + unsigned int dco_lsb:3; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_0:1; + unsigned int dco_msb:6; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_1:2; + unsigned int open_loop:1; /* Open-loop operation */ + unsigned int reserved_2:15; + }; + unsigned int raw; +} fll_reg_fcr2_t; + +#endif + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/freq.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/freq.h new file mode 100644 index 0000000..75280e2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/freq.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC3_1_FREQ_H__ +#define __ARCHI_CHIPS_VIVOSOC3_1_FREQ_H__ + +// register address offsets +#define FREQ_CLK_TREE_CONF_GLOBAL_OFFSET 0x040 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FREQ_CLK_TREE_CONF_CL_OFFSET 0x050 +#define FREQ_CLK_TREE_CONF_SOC_OFFSET 0x054 +#define FREQ_CLK_TREE_CONF_PER_OFFSET 0x058 +#define FREQ_CLK_TREE_CONF_PM_OFFSET 0x05C + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/memory_map.h new file mode 100644 index 0000000..74ef7f1 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/memory_map.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC3_1_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_VIVOSOC3_1_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00004000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c004000 +#define ARCHI_L2_PRIV1_SIZE 0x00004000 + +#define ARCHI_L2_SHARED_ADDR 0x1c008000 +#define ARCHI_L2_SHARED_SIZE 0x00010000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FLL_IF_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_APB_ADV_TIMER_OFFSET 0x00005000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_DEBUG_OFFSET 0x00008000 +#define ARCHI_FC_ITC_OFFSET 0x00009000 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 +#define ARCHI_ANALOG_OFFSET 0x00010000 + +#define ARCHI_FLL_IF_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FLL_IF_OFFSET ) +#define ARCHI_GPIO_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_APB_ADV_TIMER_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_ADV_TIMER_OFFSET) +#define ARCHI_SOC_EU_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_DEBUG_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_DEBUG_OFFSET ) +#define ARCHI_FC_ITC_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_ANALOG_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_ANALOG_OFFSET ) + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR (ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) (ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET 0x00000 +#define ARCHI_MCHAN_DEMUX_OFFSET 0x00400 + +#define ARCHI_DEMUX_PERIPHERALS_ADDR (ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/properties.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/properties.h new file mode 100755 index 0000000..e797fce --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_1/properties.h @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC3_1_PROPERTIES_H__ +#define __ARCHI_CHIPS_VIVOSOC3_1_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 32768 + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 3 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 3 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 +#define PADS_VERSION 2 +#define FLL_VERSION 1 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0x80 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/fll.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/fll.h new file mode 100644 index 0000000..3f72e0b --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/fll.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC3_5_FLL_H__ +#define __ARCHI_CHIPS_VIVOSOC3_5_FLL_H__ + +// register address offsets +#define FLL_CONTROL_OFFSET 0x044 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FLL_RESET_OFFSET 0x048 +#define FLL_GPIO_OUTPUT 0x104 + +#define FLL_OFFSET 0x040 // base addr 0x1A100000 (ARCHI_SOC_PERIPHERALS_ADDR) + +#define FLL_SET_SEL_OFFSET 0x000 // base addr 0x1A100000 + fll * FLL_OFFSET +#define FLL_REF_CLK_OFFSET 0x004 +#define FLL_FSM_OBS_OFFSET 0x008 +#define FLL_SHARED_CONFIG_OFFSET 0x00C +#define FLL_SET_OFFSET 0x00C +#define FLL_FREQ_REGULATION_OFFSET 0x010 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CLK_GOOD_OFFSET 0x014 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CONFIG_OFFSET 0x018 // + set * FLL_SET_OFFSET +#define FLL_OBSERVATION_OFFSET 0x100 + +#define FLL_ANALOG_CLKIPC_OFFSET 0x4638 // base addr ARCHI_ANALOG_ADDR + +// register bitfields +#define FLL_SET_RSS_BIT 0 +#define FLL_SET_RSS_WIDTH 2 +#define FLL_SET_RSS_MASK (0x0003) + + +#define FLL_FREQ_REGULATION_LOW_BIT 0 +#define FLL_FREQ_REGULATION_LOW_WIDTH 14 +#define FLL_FREQ_REGULATION_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_REGULATION_HIGH_BIT 16 +#define FLL_FREQ_REGULATION_HIGH_WIDTH 14 +#define FLL_FREQ_REGULATION_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CLK_GOOD_LOW_BIT 0 +#define FLL_FREQ_CLK_GOOD_LOW_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_CLK_GOOD_HIGH_BIT 16 +#define FLL_FREQ_CLK_GOOD_HIGH_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CONFIG_LEVEL_BIT 0 +#define FLL_FREQ_CONFIG_LEVEL_WIDTH 4 +#define FLL_FREQ_CONFIG_LEVEL_MASK (0x0000000F) + +#define FLL_FREQ_CONFIG_DCO_LSB_BIT 4 +#define FLL_FREQ_CONFIG_DCO_LSB_WIDTH 3 +#define FLL_FREQ_CONFIG_DCO_LSB_MASK (0x00000070) + +#define FLL_FREQ_CONFIG_DCO_MSB_BIT 8 +#define FLL_FREQ_CONFIG_DCO_MSB_WIDTH 6 +#define FLL_FREQ_CONFIG_DCO_MSB_MASK (0x00003F00) + +#define FLL_FREQ_CONFIG_OL_BIT 16 +#define FLL_FREQ_CONFIG_OL_WIDTH 1 +#define FLL_FREQ_CONFIG_OL_MASK (0x00010000) + + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rss:1; /* Register set selection, 0b00 or 0b01 */ + unsigned int reserved_0:31; + }; + unsigned int raw; +} fll_reg_rss_t; + +typedef union { + struct { + unsigned int nref_reg_low:14; /* Regulation, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_reg_high:14; /* Regulation, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr0_t; + +typedef union { + struct { + unsigned int nref_cg_low:14; /* Clock good, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_cg_high:14; /* Clock good, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr1_t; + +typedef union { + struct { + unsigned int level:4; /* Start level of binary search, reset value: 0x0 */ + unsigned int dco_lsb:3; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_0:1; + unsigned int dco_msb:6; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_1:2; + unsigned int open_loop:1; /* Open-loop operation */ + unsigned int reserved_2:15; + }; + unsigned int raw; +} fll_reg_fcr2_t; + +#endif + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/freq.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/freq.h new file mode 100644 index 0000000..06191ed --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/freq.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC3_5_FREQ_H__ +#define __ARCHI_CHIPS_VIVOSOC3_5_FREQ_H__ + +// register address offsets +#define FREQ_CLK_TREE_CONF_GLOBAL_OFFSET 0x040 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FREQ_CLK_TREE_CONF_CL_OFFSET 0x050 +#define FREQ_CLK_TREE_CONF_SOC_OFFSET 0x054 +#define FREQ_CLK_TREE_CONF_PER_OFFSET 0x058 +#define FREQ_CLK_TREE_CONF_PM_OFFSET 0x05C + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/memory_map.h new file mode 100644 index 0000000..12cdc4e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/memory_map.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC3_5_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_VIVOSOC3_5_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00004000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c004000 +#define ARCHI_L2_PRIV1_SIZE 0x00004000 + +#define ARCHI_L2_SHARED_ADDR 0x1c008000 +#define ARCHI_L2_SHARED_SIZE 0x00010000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + + +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009000 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 +#define ARCHI_ANALOG_OFFSET 0x00010000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_ANALOG_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_ANALOG_OFFSET ) + + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/properties.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/properties.h new file mode 100644 index 0000000..7dc58ab --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc3_5/properties.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC3_5_PROPERTIES_H__ +#define __ARCHI_CHIPS_VIVOSOC3_5_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 32768 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 +#define PADS_VERSION 2 +#define FLL_VERSION 1 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 + + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 2 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +// PADs configuration is made of 8bits out of which only the first 3 are used +// bit0 enable pull UP +// bit1 enable pull DOWN +// bit2 enable ST +// bit3..7 not used + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +// aliases +#define APB_SOC_PADS_CONFIG APB_SOC_PADCFG0_OFFSET + +// HAL compatibility definitions, functions not supported +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C +#define APB_SOC_BUSY_OFFSET 0x6C +#define APB_SOC_JTAG_REG 0x74 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/fll.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/fll.h new file mode 100644 index 0000000..7978df9 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/fll.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC4_FLL_H__ +#define __ARCHI_CHIPS_VIVOSOC4_FLL_H__ + +// register address offsets +#define FLL_CONTROL_OFFSET 0x044 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FLL_RESET_OFFSET 0x048 +#define FLL_GPIO_OUTPUT 0x104 + +#define FLL_OFFSET 0x040 // base addr 0x1A100000 (ARCHI_SOC_PERIPHERALS_ADDR) + +#define FLL_SET_SEL_OFFSET 0x000 // base addr 0x1A100000 + fll * FLL_OFFSET +#define FLL_REF_CLK_OFFSET 0x004 +#define FLL_FSM_OBS_OFFSET 0x008 +#define FLL_SHARED_CONFIG_OFFSET 0x00C +#define FLL_SET_OFFSET 0x00C +#define FLL_FREQ_REGULATION_OFFSET 0x010 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CLK_GOOD_OFFSET 0x014 // + set * FLL_SET_OFFSET +#define FLL_FREQ_CONFIG_OFFSET 0x018 // + set * FLL_SET_OFFSET +#define FLL_OBSERVATION_OFFSET 0x100 + +#define FLL_ANALOG_CLKIPC_OFFSET 0x4638 // base addr ARCHI_ANALOG_ADDR + +// register bitfields +#define FLL_SET_RSS_BIT 0 +#define FLL_SET_RSS_WIDTH 2 +#define FLL_SET_RSS_MASK (0x0003) + + +#define FLL_FREQ_REGULATION_LOW_BIT 0 +#define FLL_FREQ_REGULATION_LOW_WIDTH 14 +#define FLL_FREQ_REGULATION_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_REGULATION_HIGH_BIT 16 +#define FLL_FREQ_REGULATION_HIGH_WIDTH 14 +#define FLL_FREQ_REGULATION_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CLK_GOOD_LOW_BIT 0 +#define FLL_FREQ_CLK_GOOD_LOW_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_LOW_MASK (0x00003FFF) + +#define FLL_FREQ_CLK_GOOD_HIGH_BIT 16 +#define FLL_FREQ_CLK_GOOD_HIGH_WIDTH 14 +#define FLL_FREQ_CLK_GOOD_HIGH_MASK (0x3FFF0000) + + +#define FLL_FREQ_CONFIG_LEVEL_BIT 0 +#define FLL_FREQ_CONFIG_LEVEL_WIDTH 4 +#define FLL_FREQ_CONFIG_LEVEL_MASK (0x0000000F) + +#define FLL_FREQ_CONFIG_DCO_LSB_BIT 4 +#define FLL_FREQ_CONFIG_DCO_LSB_WIDTH 3 +#define FLL_FREQ_CONFIG_DCO_LSB_MASK (0x00000070) + +#define FLL_FREQ_CONFIG_DCO_MSB_BIT 8 +#define FLL_FREQ_CONFIG_DCO_MSB_WIDTH 6 +#define FLL_FREQ_CONFIG_DCO_MSB_MASK (0x00003F00) + +#define FLL_FREQ_CONFIG_OL_BIT 16 +#define FLL_FREQ_CONFIG_OL_WIDTH 1 +#define FLL_FREQ_CONFIG_OL_MASK (0x00010000) + + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rss:1; /* Register set selection, 0b00 or 0b01 */ + unsigned int reserved_0:31; + }; + unsigned int raw; +} fll_reg_rss_t; + +typedef union { + struct { + unsigned int nref_reg_low:14; /* Regulation, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_reg_high:14; /* Regulation, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr0_t; + +typedef union { + struct { + unsigned int nref_cg_low:14; /* Clock good, lower boundary, in ref clk cycles */ + unsigned int reserved_0:2; + unsigned int nref_cg_high:14; /* Clock good, upper boundary, in ref clk cycles */ + unsigned int reserved_1:2; + }; + unsigned int raw; +} fll_reg_fcr1_t; + +typedef union { + struct { + unsigned int level:4; /* Start level of binary search, reset value: 0x0 */ + unsigned int dco_lsb:3; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_0:1; + unsigned int dco_msb:6; /* Start point for the binary search, reset value: 0x0 */ + unsigned int reserved_1:2; + unsigned int open_loop:1; /* Open-loop operation */ + unsigned int reserved_2:15; + }; + unsigned int raw; +} fll_reg_fcr2_t; + +#endif + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/freq.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/freq.h new file mode 100644 index 0000000..97f5782 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/freq.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_CHIPS_VIVOSOC4_FREQ_H__ +#define __ARCHI_CHIPS_VIVOSOC4_FREQ_H__ + +// register address offsets +#define FREQ_CLK_TREE_CONF_GLOBAL_OFFSET 0x040 // base addr 0x1A104000 (ARCHI_APB_SOC_CTRL_ADDR) +#define FREQ_CLK_TREE_CONF_CL_OFFSET 0x050 +#define FREQ_CLK_TREE_CONF_SOC_OFFSET 0x054 +#define FREQ_CLK_TREE_CONF_PER_OFFSET 0x058 +#define FREQ_CLK_TREE_CONF_PM_OFFSET 0x05C + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/memory_map.h new file mode 100644 index 0000000..a924156 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/memory_map.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC4_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_VIVOSOC4_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00004000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c004000 +#define ARCHI_L2_PRIV1_SIZE 0x00004000 + +#define ARCHI_L2_SHARED_ADDR 0x1c008000 +#define ARCHI_L2_SHARED_SIZE 0x00010000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FLL_IF_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_APB_ADV_TIMER_OFFSET 0x00005000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_DEBUG_OFFSET 0x00008000 +#define ARCHI_FC_ITC_OFFSET 0x00009000 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 +#define ARCHI_ANALOG_OFFSET 0x00010000 + +#define ARCHI_FLL_IF_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FLL_IF_OFFSET ) +#define ARCHI_GPIO_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_APB_ADV_TIMER_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_ADV_TIMER_OFFSET) +#define ARCHI_SOC_EU_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_DEBUG_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_DEBUG_OFFSET ) +#define ARCHI_FC_ITC_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) +#define ARCHI_ANALOG_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_ANALOG_OFFSET ) + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR (ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) (ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR (ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET 0x00000 +#define ARCHI_MCHAN_DEMUX_OFFSET 0x00400 + +#define ARCHI_DEMUX_PERIPHERALS_ADDR (ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/properties.h b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/properties.h new file mode 100755 index 0000000..25a2240 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/vivosoc4/properties.h @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_VIVOSOC4_PROPERTIES_H__ +#define __ARCHI_CHIPS_VIVOSOC4_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L1_SIZE 32768 + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 3 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 3 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 +#define PADS_VERSION 2 +#define FLL_VERSION 1 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#define ARCHI_CLUSTER_NB_PE 8 + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 +#define APB_SOC_RAR 0x100 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + +#define APB_SOC_SLEEP_CONTROL 0x104 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#define ARCHI_APB_SOC_BYPASS_ENABLE_BIT 0 +#define ARCHI_APB_SOC_BYPASS_CLUSTER_POWER_BIT 1 +#define ARCHI_APB_SOC_BYPASS_CLUSTER_CLOCK_BIT 2 +#define ARCHI_APB_SOC_BYPASS_FLL_RETENTIVE_BIT 3 +#define ARCHI_APB_SOC_BYPASS_FLL_OFF_BIT 4 +#define ARCHI_APB_SOC_BYPASS_CLUSTER_RESET_BIT 5 +#define ARCHI_APB_SOC_BYPASS_CLUSTER_ISOLATE_BIT 6 +#define ARCHI_APB_SOC_BYPASS_CLUSTER_RETENTIVE_BIT 7 +#define ARCHI_APB_SOC_BYPASS_POWER_OK_BIT 8 +#define ARCHI_APB_SOC_BYPASS_CLOCK_OK_BIT 9 +#define ARCHI_APB_SOC_BYPASS_POWER_DOWN_BIT 10 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/wolfe/apb_soc_ctrl_new.h b/sw/pulp-sdk/archi/include/archi/chips/wolfe/apb_soc_ctrl_new.h new file mode 100644 index 0000000..d09e928 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/wolfe/apb_soc_ctrl_new.h @@ -0,0 +1,271 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_WOLFE_APB_SOC_CTRL_NEW_H__ +#define __INCLUDE_ARCHI_CHIPS_WOLFE_APB_SOC_CTRL_NEW_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Deep sleep control register +#define APB_SOC_SLEEP_CONTROL_OFFSET 0x104 + +// First RTC register +#define APB_SOC_RTC_FIRST_REG_OFFSET 0x1d0 + +// Last RTC register +#define APB_SOC_RTC_LAST_REG_OFFSET 0x1dc + + + +// +// REGISTERS FIELDS +// + +// FLL retention configuration. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_FLL_RET_BIT 0 +#define APB_SOC_SLEEP_CONTROL_FLL_RET_WIDTH 2 +#define APB_SOC_SLEEP_CONTROL_FLL_RET_MASK 0x3 + +// Memory retention configuration part 0. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_0_BIT 2 +#define APB_SOC_SLEEP_CONTROL_MEM_RET_0_WIDTH 1 +#define APB_SOC_SLEEP_CONTROL_MEM_RET_0_MASK 0x4 + +// External wakeup selection. This gives the GPIO numer which can wakeup the chip when it is in deep sleep mode. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_BIT 6 +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_WIDTH 5 +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_MASK 0x7c0 + +// External wakeup type. This tells the way the external GPIO can wakeup the chip while it is in deep sleep (raising edge, falling edge, etc). Possible values: - 0: Rising edge. - 1: Falling edge. - 2: Level high. - 3: Level low. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_BIT 11 +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_WIDTH 2 +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_MASK 0x1800 + +// External wakeup enable. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_BIT 13 +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_WIDTH 1 +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_MASK 0x2000 + +// Wake-up state. This specifies in which state the PMU should wakeup the chip. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_WAKEUP_BIT 14 +#define APB_SOC_SLEEP_CONTROL_WAKEUP_WIDTH 2 +#define APB_SOC_SLEEP_CONTROL_WAKEUP_MASK 0xc000 + +// Boot type. This is a user field written by the SW which is interpreted by the oot code and runtime after the chip has rebooted. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_BOOT_TYPE_BIT 18 +#define APB_SOC_SLEEP_CONTROL_BOOT_TYPE_WIDTH 2 +#define APB_SOC_SLEEP_CONTROL_BOOT_TYPE_MASK 0xc0000 + +// Cluster wakeup state. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_BIT 20 +#define APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_WIDTH 1 +#define APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_MASK 0x100000 + +// Memory retention configuration part 1. (access: R/W) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_1_BIT 21 +#define APB_SOC_SLEEP_CONTROL_MEM_RET_1_WIDTH 11 +#define APB_SOC_SLEEP_CONTROL_MEM_RET_1_MASK 0xffe00000 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int fll_ret :2 ; // FLL retention configuration. + unsigned int mem_ret_0 :1 ; // Memory retention configuration part 0. + unsigned int padding0:3 ; + unsigned int extwakeup_sel :5 ; // External wakeup selection. This gives the GPIO numer which can wakeup the chip when it is in deep sleep mode. + unsigned int extwakeup_type :2 ; // External wakeup type. This tells the way the external GPIO can wakeup the chip while it is in deep sleep (raising edge, falling edge, etc). Possible values: - 0: Rising edge. - 1: Falling edge. - 2: Level high. - 3: Level low. + unsigned int extwakeup_en :1 ; // External wakeup enable. + unsigned int wakeup :2 ; // Wake-up state. This specifies in which state the PMU should wakeup the chip. + unsigned int padding1:2 ; + unsigned int boot_type :2 ; // Boot type. This is a user field written by the SW which is interpreted by the oot code and runtime after the chip has rebooted. + unsigned int cluster_wakeup :1 ; // Cluster wakeup state. + unsigned int mem_ret_1 :11; // Memory retention configuration part 1. + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_sleep_control_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rtc_first_reg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_rtc_last_reg_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_apb_soc_sleep_control : public vp::reg_32 +{ +public: + inline void fll_ret_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_FLL_RET_BIT, APB_SOC_SLEEP_CONTROL_FLL_RET_WIDTH); } + inline uint32_t fll_ret_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_FLL_RET_BIT, APB_SOC_SLEEP_CONTROL_FLL_RET_WIDTH); } + inline void mem_ret_0_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_MEM_RET_0_BIT, APB_SOC_SLEEP_CONTROL_MEM_RET_0_WIDTH); } + inline uint32_t mem_ret_0_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_MEM_RET_0_BIT, APB_SOC_SLEEP_CONTROL_MEM_RET_0_WIDTH); } + inline void extwakeup_sel_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_BIT, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_WIDTH); } + inline uint32_t extwakeup_sel_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_BIT, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_WIDTH); } + inline void extwakeup_type_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_BIT, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_WIDTH); } + inline uint32_t extwakeup_type_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_BIT, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_WIDTH); } + inline void extwakeup_en_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_BIT, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_WIDTH); } + inline uint32_t extwakeup_en_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_BIT, APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_WIDTH); } + inline void wakeup_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_WAKEUP_BIT, APB_SOC_SLEEP_CONTROL_WAKEUP_WIDTH); } + inline uint32_t wakeup_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_WAKEUP_BIT, APB_SOC_SLEEP_CONTROL_WAKEUP_WIDTH); } + inline void boot_type_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_BOOT_TYPE_BIT, APB_SOC_SLEEP_CONTROL_BOOT_TYPE_WIDTH); } + inline uint32_t boot_type_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_BOOT_TYPE_BIT, APB_SOC_SLEEP_CONTROL_BOOT_TYPE_WIDTH); } + inline void cluster_wakeup_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_BIT, APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_WIDTH); } + inline uint32_t cluster_wakeup_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_BIT, APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_WIDTH); } + inline void mem_ret_1_set(uint32_t value) { this->set_field(value, APB_SOC_SLEEP_CONTROL_MEM_RET_1_BIT, APB_SOC_SLEEP_CONTROL_MEM_RET_1_WIDTH); } + inline uint32_t mem_ret_1_get() { return this->get_field(APB_SOC_SLEEP_CONTROL_MEM_RET_1_BIT, APB_SOC_SLEEP_CONTROL_MEM_RET_1_WIDTH); } +}; + +class vp_apb_soc_rtc_first_reg : public vp::reg_32 +{ +public: +}; + +class vp_apb_soc_rtc_last_reg : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int sleep_control ; // Deep sleep control register + unsigned int rtc_first_reg ; // First RTC register + unsigned int rtc_last_reg ; // Last RTC register +} __attribute__((packed)) apb_soc_apb_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t apb_soc_sleep_control_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_SLEEP_CONTROL_OFFSET); } +static inline void apb_soc_sleep_control_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_SLEEP_CONTROL_OFFSET, value); } + +static inline uint32_t apb_soc_rtc_first_reg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RTC_FIRST_REG_OFFSET); } +static inline void apb_soc_rtc_first_reg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RTC_FIRST_REG_OFFSET, value); } + +static inline uint32_t apb_soc_rtc_last_reg_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_RTC_LAST_REG_OFFSET); } +static inline void apb_soc_rtc_last_reg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_RTC_LAST_REG_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define APB_SOC_SLEEP_CONTROL_FLL_RET_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define APB_SOC_SLEEP_CONTROL_FLL_RET_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define APB_SOC_SLEEP_CONTROL_FLL_RET_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define APB_SOC_SLEEP_CONTROL_FLL_RET(val) ((val) << 0) + +#define APB_SOC_SLEEP_CONTROL_MEM_RET_0_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_0_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_0_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_0(val) ((val) << 2) + +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_GET(value) (ARCHI_BEXTRACTU((value),5,6)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_GETS(value) (ARCHI_BEXTRACT((value),5,6)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL_SET(value,field) (ARCHI_BINSERT((value),(field),5,6)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_SEL(val) ((val) << 6) + +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_GET(value) (ARCHI_BEXTRACTU((value),2,11)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_GETS(value) (ARCHI_BEXTRACT((value),2,11)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE_SET(value,field) (ARCHI_BINSERT((value),(field),2,11)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_TYPE(val) ((val) << 11) + +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define APB_SOC_SLEEP_CONTROL_EXTWAKEUP_EN(val) ((val) << 13) + +#define APB_SOC_SLEEP_CONTROL_WAKEUP_GET(value) (ARCHI_BEXTRACTU((value),2,14)) +#define APB_SOC_SLEEP_CONTROL_WAKEUP_GETS(value) (ARCHI_BEXTRACT((value),2,14)) +#define APB_SOC_SLEEP_CONTROL_WAKEUP_SET(value,field) (ARCHI_BINSERT((value),(field),2,14)) +#define APB_SOC_SLEEP_CONTROL_WAKEUP(val) ((val) << 14) + +#define APB_SOC_SLEEP_CONTROL_BOOT_TYPE_GET(value) (ARCHI_BEXTRACTU((value),2,18)) +#define APB_SOC_SLEEP_CONTROL_BOOT_TYPE_GETS(value) (ARCHI_BEXTRACT((value),2,18)) +#define APB_SOC_SLEEP_CONTROL_BOOT_TYPE_SET(value,field) (ARCHI_BINSERT((value),(field),2,18)) +#define APB_SOC_SLEEP_CONTROL_BOOT_TYPE(val) ((val) << 18) + +#define APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_GET(value) (ARCHI_BEXTRACTU((value),1,20)) +#define APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_GETS(value) (ARCHI_BEXTRACT((value),1,20)) +#define APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP_SET(value,field) (ARCHI_BINSERT((value),(field),1,20)) +#define APB_SOC_SLEEP_CONTROL_CLUSTER_WAKEUP(val) ((val) << 20) + +#define APB_SOC_SLEEP_CONTROL_MEM_RET_1_GET(value) (ARCHI_BEXTRACTU((value),11,21)) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_1_GETS(value) (ARCHI_BEXTRACT((value),11,21)) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_1_SET(value,field) (ARCHI_BINSERT((value),(field),11,21)) +#define APB_SOC_SLEEP_CONTROL_MEM_RET_1(val) ((val) << 21) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/wolfe/memory_map.h b/sw/pulp-sdk/archi/include/archi/chips/wolfe/memory_map.h new file mode 100644 index 0000000..84690a5 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/wolfe/memory_map.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_WOLFE_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_WOLFE_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x1c000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x1c008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x1c010000 +#define ARCHI_L2_SHARED_SIZE 0x00070000 + + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_PWM_OFFSET 0x00005000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_PMU_OFFSET 0x00007000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_PWM_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PWM_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_PMU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_PMU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET ) + + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x00000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) + + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/wolfe/pmu.h b/sw/pulp-sdk/archi/include/archi/chips/wolfe/pmu.h new file mode 100644 index 0000000..e473db2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/wolfe/pmu.h @@ -0,0 +1,330 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_WOLFE_PMU_H__ +#define __INCLUDE_ARCHI_CHIPS_WOLFE_PMU_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_pmu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu0 +// + +#define PMU_ICU0_OFFSET 0x2 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu0_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP icu1 +// + +#define PMU_ICU1_OFFSET 0x3 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_icu1_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP dmu0 +// + +#define PMU_DMU0_OFFSET 0x4 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) pmu_dmu0_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// CUSTOM FIELDS +// +#define PMU_BOOT -1 +#define PMU_SOC_ACTIVE_NV 0x00 +#define PMU_SOC_ACTIVE_LV 0x01 +#define PMU_SOC_CLUSTER_ACTIVE_NV 0x02 +#define PMU_SOC_CLUSTER_ACTIVE_LV 0x03 +#define PMU_DEEP_SLEEP 0x04 +#define PMU_DEEP_SLEEP_RETENTIVE 0x05 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/chips/wolfe/properties.h b/sw/pulp-sdk/archi/include/archi/chips/wolfe/properties.h new file mode 100644 index 0000000..e840e33 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/chips/wolfe/properties.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_WOLFE_PROPERTIES_H__ +#define __ARCHI_CHIPS_WOLFE_PROPERTIES_H__ + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L1 1 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + +#define ARCHI_L1_SIZE 65536 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 2 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 1 +#define APB_SOC_VERSION 2 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 6 +#define PADS_VERSION 2 +#define RTC_VERSION 2 +#define PWM_VERSION 1 + +/* + * SOC + */ + +#define ARCHI_PWM_NB 1 +#define ARCHI_PWM_NB_TIMERS 4 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#if PULP_CHIP == CHIP_WOLFE_16 +#define ARCHI_CLUSTER_NB_PE 16 +#else +#define ARCHI_CLUSTER_NB_PE 8 +#endif + + + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ + +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 + + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 2) + +#define ARCHI_CLUSTER_CTRL_EOC 0x0 +#define ARCHI_CLUSTER_CTRL_FETCH_EN 0x8 +#define ARCHI_CLUSTER_CTRL_EVENT 0x10 +#define ARCHI_CLUSTER_CTRL_CLUSTER_CFG 0x18 +#define ARCHI_CLUSTER_CTRL_CLUSTER_CLK_GATE 0x20 +#define ARCHI_CLUSTER_CTRL_DBG_STATUS 0x28 +#define ARCHI_CLUSTER_CTRL_DBG_HALT_MASK 0x38 +#define ARCHI_CLUSTER_CTRL_BOOTADDR(core) (0x40 + 4*(core)) +#define ARCHI_CLUSTER_CTRL_BOOTADDR_COREID(offset) (((offset) - ARCHI_CLUSTER_CTRL_BOOTADDR(0)) >> 2) + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/dma/mchan_v3.h b/sw/pulp-sdk/archi/include/archi/dma/mchan_v3.h new file mode 100644 index 0000000..746ad1b --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/dma/mchan_v3.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARCHI_DMA_MCHAN_V3_H +#define ARCHI_DMA_MCHAN_V3_H + +#define TCDM_ADDR_REG_OFFSET ( 0x0 ) +#define EXT_ADDR_REG_OFFSET ( 0x4 ) +#define CMD_QUEUE_OFFSET ( 0x8 ) +#define CMD_QUEUE_BUSY_REG_OFFSET ( 0xC ) + +#define ST1 0x0001 +#define ST2 0x0002 +#define ST4 0x0004 +#define ST8 0x0008 +#define ST16 0x0010 +#define ST32 0x0020 +#define ST64 0x0040 +#define ST128 0x0080 +#define ST256 0x0100 +#define ST512 0x0200 +#define ST1024 0x0400 +#define ST2048 0x0800 +#define ST4096 0x1000 +#define ST8192 0x2000 +#define ST16384 0x4000 + +#define LD1 0x8001 +#define LD2 0x8002 +#define LD4 0x8004 +#define LD8 0x8008 +#define LD16 0x8010 +#define LD32 0x8020 +#define LD64 0x8040 +#define LD128 0x8080 +#define LD256 0x8100 +#define LD512 0x8200 +#define LD1024 0x8400 +#define LD2048 0x8800 +#define LD4096 0x9000 +#define LD8192 0xA000 +#define LD16384 0xC000 + +#define MCHAN_TYPE_OFFSET 15 +#define MCHAN_TYPE(x) (((x) >> MCHAN_TYPE_OFFSET) & 1) + +#define MCHAN_SIZE_OFFSET 0 +#define MCHAN_SIZE(x) (((x) >> MCHAN_SIZE_OFFSET) & 0x7fff) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/dma/mchan_v5.h b/sw/pulp-sdk/archi/include/archi/dma/mchan_v5.h new file mode 100644 index 0000000..395467e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/dma/mchan_v5.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_DMA_MCHAN_V5_H__ +#define __ARCHI_DMA_MCHAN_V5_H__ + +#define MCHAN_COMMAND_QUEUE_OFFSET 0x0 +#define MCHAN_STATUS_REGISTER_OFFSET 0x4 + +#define MCHAN_SIZE_OFFSET 0 +#define MCHAN_LEN_WIDTH 16 +#define MCHAN_LEN_MASK ((1<> MCHAN_SIZE_OFFSET) & MCHAN_LEN_MASK) + +#define MCHAN_TYPE_OFFSET (MCHAN_LEN_WIDTH) +#define MCHAN_TYPE(x) (((x) >> MCHAN_TYPE_OFFSET) & 1) + +#define MCHAN_INCR_OFFSET (MCHAN_LEN_WIDTH + 1) +#define MCHAN_INCR(x) (((x) >> MCHAN_INCR_OFFSET) & 1) + +#define MCHAN_TWD_OFFSET (MCHAN_LEN_WIDTH + 2) +#define MCHAN_TWD(x) (((x) >> MCHAN_TWD_OFFSET) & 1) + +#define MCHAN_2D_STRIDE_OFFSET (16) +#define MCHAN_2D_STRIDE_WIDTH (16) +#define MCHAN_2D_STRIDE_MASK ((1<> MCHAN_2D_STRIDE_OFFSET) & MCHAN_2D_STRIDE_MASK) + +#define MCHAN_2D_LEN_OFFSET (0) +#define MCHAN_2D_LEN_WIDTH (16) +#define MCHAN_2D_LEN_MASK ((1<> MCHAN_2D_LEN_OFFSET) & MCHAN_2D_LEN_MASK) + +// Direction of the transfer +#define MCHAN_LOC_TO_EXT_MODE 0x0 // From inside the cluster to outside (e.g. L1 to L2) +#define MCHAN_EXT_TO_LOC_MODE 0x1 // From outside the cluster to inside the cluster (e.g. L2 to L1) +#define MCHAN_TX_MODE 0x0 +#define MCHAN_RX_MODE 0x1 + +// Address increment +#define MCHAN_FIX_MODE 0x0 // No increment, the access address is always the same, useful for streaming devices +#define MCHAN_INC_MODE 0x1 // Classic address increment + +// 1D or 2D transfer +#define MCHAN_LIN_MODE 0x0 // Classic linear (1D) mode +#define MCHAN_TWD_MODE 0x1 // 2D mode, for block transfer + +#define MCHAN_NB_COUNTERS 4 + + + + + + + + + + + + + + +// Register map + +#define PLP_DMA_QUEUE_OFFSET 0x0 +#define PLP_DMA_STATUS_OFFSET 0x4 + +// Command bitfield + +#define PLP_DMA_SIZE_BIT 0 +#define PLP_DMA_SIZE_WIDTH 16 +#define PLP_DMA_TYPE_BIT (PLP_DMA_SIZE_WIDTH) +#define PLP_DMA_INCR_BIT (PLP_DMA_SIZE_WIDTH + 1) +#define PLP_DMA_2D_BIT (PLP_DMA_SIZE_WIDTH + 2) + +#define PLP_DMA_LOC2EXT 0 +#define PLP_DMA_EXT2LOC 1 + +#define PLP_DMA_1D 0 +#define PLP_DMA_2D 1 + +#define PLP_DMA_FIX 0 +#define PLP_DMA_INC 1 + +// Stride bitfield + +#define PLP_DMA_2D_STRIDE_BIT 16 +#define PLP_DMA_2D_STRIDE_WIDTH 16 + +#define PLP_DMA_2D_LEN_BIT 0 +#define PLP_DMA_2D_LEN_WIDTH 16 + +// Macros +#define PLP_DMA_SIZE_GET(x) (((x) >> PLP_DMA_SIZE_BIT) & ((1<> PLP_DMA_TYPE_BIT) & 1) +#define PLP_DMA_INCR_GET(x) (((x) >> PLP_DMA_INCR_BIT) & 1) +#define PLP_DMA_2D_GET(x) (((x) >> PLP_DMA_2D_BIT) & 1) + +#define PLP_DMA_2D_STRIDE_GET(x) (((x) >> PLP_DMA_2D_STRIDE_BIT) & ((1<> PLP_DMA_2D_LEN_BIT) & ((1<> PLP_DMA_SIZE_BIT) & ((1<> PLP_DMA_TYPE_BIT) & 1) +#define PLP_DMA_INCR_GET(x) (((x) >> PLP_DMA_INCR_BIT) & 1) +#define PLP_DMA_2D_GET(x) (((x) >> PLP_DMA_2D_BIT) & 1) +#define PLP_DMA_ELE_GET(x) (((x) >> PLP_DMA_ELE_BIT) & 1) +#define PLP_DMA_ILE_GET(x) (((x) >> PLP_DMA_ILE_BIT) & 1) +#define PLP_DMA_BLE_GET(x) (((x) >> PLP_DMA_BLE_BIT) & 1) + +#define PLP_DMA_2D_STRIDE_GET(x) (((x) >> PLP_DMA_2D_STRIDE_BIT) & ((1<> PLP_DMA_2D_LEN_BIT) & ((1< +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Cluster DMA configuration register. +#define MCHAN_CMD_OFFSET 0x0 + +// Cluster DMA status register. +#define MCHAN_STATUS_OFFSET 0x4 + + + +// +// REGISTERS FIELDS +// + +// Format is operation dependent. See below. (access: R/W) +#define MCHAN_CMD_CMD_BIT 0 +#define MCHAN_CMD_CMD_WIDTH 32 +#define MCHAN_CMD_CMD_MASK 0xffffffff + +// Format is operation dependent. See below. (access: R/W) +#define MCHAN_STATUS_STATUS_BIT 0 +#define MCHAN_STATUS_STATUS_WIDTH 32 +#define MCHAN_STATUS_STATUS_MASK 0xffffffff + +// Transfer length in bytes configuration bitfield. (access: W) +#define MCHAN_CMD_CMD_LEN_BIT 0 +#define MCHAN_CMD_CMD_LEN_WIDTH 17 +#define MCHAN_CMD_CMD_LEN_MASK 0x1ffff + +// Transfer direction configuration bitfield: - 1'b0: L1 to L2 - 1'b1: L2 to L2 (access: W) +#define MCHAN_CMD_CMD_TYPE_BIT 17 +#define MCHAN_CMD_CMD_TYPE_WIDTH 1 +#define MCHAN_CMD_CMD_TYPE_MASK 0x20000 + +// Transfer incremental configuration bitfield: - 1'b0: non incremental - 1'b1: incremental (access: W) +#define MCHAN_CMD_CMD_INC_BIT 18 +#define MCHAN_CMD_CMD_INC_WIDTH 1 +#define MCHAN_CMD_CMD_INC_MASK 0x40000 + +// Transfer type configuration bitfield: - 1'b0: linear transfer in EXT interface - 1'b1: 2D transfer in EXT interface (access: W) +#define MCHAN_CMD_CMD__2D_EXT_BIT 19 +#define MCHAN_CMD_CMD__2D_EXT_WIDTH 1 +#define MCHAN_CMD_CMD__2D_EXT_MASK 0x80000 + +// Transfer event generation configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: W) +#define MCHAN_CMD_CMD_ELE_BIT 20 +#define MCHAN_CMD_CMD_ELE_WIDTH 1 +#define MCHAN_CMD_CMD_ELE_MASK 0x100000 + +// Transfer interrupt generation configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: W) +#define MCHAN_CMD_CMD_ILE_BIT 21 +#define MCHAN_CMD_CMD_ILE_WIDTH 1 +#define MCHAN_CMD_CMD_ILE_MASK 0x200000 + +// Transfer event or interrupt broadcast configuration bitfield: - 1'b0: event or interrupt is routed to the cluster core who initiated the transfer - 1'b1: event or interrupt are broadcasted to all cluster cores (access: W) +#define MCHAN_CMD_CMD_BLE_BIT 22 +#define MCHAN_CMD_CMD_BLE_WIDTH 1 +#define MCHAN_CMD_CMD_BLE_MASK 0x400000 + +// Transfer type configuration bitfield: - 1'b0: linear transfer in TCDM interface - 1'b1: 2D transfer in TCDM interface (access: W) +#define MCHAN_CMD_CMD__2D_TCDM_BIT 23 +#define MCHAN_CMD_CMD__2D_TCDM_WIDTH 1 +#define MCHAN_CMD_CMD__2D_TCDM_MASK 0x800000 + +// Transfer identifier value bitfield. (access: R) +#define MCHAN_CMD_GET_TID_TID_BIT 0 +#define MCHAN_CMD_GET_TID_TID_WIDTH 4 +#define MCHAN_CMD_GET_TID_TID_MASK 0xf + +// Transfer L1 base address configuration bitfield. (access: W) +#define MCHAN_CMD_TCDM_ADDR_ADDR_BIT 0 +#define MCHAN_CMD_TCDM_ADDR_ADDR_WIDTH 32 +#define MCHAN_CMD_TCDM_ADDR_ADDR_MASK 0xffffffff + +// Transfer L2 base address configuration bitfield. (access: W) +#define MCHAN_CMD_EXT_ADDR_ADDR_BIT 0 +#define MCHAN_CMD_EXT_ADDR_ADDR_WIDTH 32 +#define MCHAN_CMD_EXT_ADDR_ADDR_MASK 0xffffffff + +// EXT 2D transfer conut value configuration bitfield. (access: W) +#define MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_BIT 0 +#define MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_WIDTH 32 +#define MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_MASK 0xffffffff + +// EXT 2D transfer stride value configuration bitfield. (access: W) +#define MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_BIT 0 +#define MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_WIDTH 32 +#define MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_MASK 0xffffffff + +// TCDM 2D transfer conut value configuration bitfield. (access: W) +#define MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_BIT 0 +#define MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_WIDTH 32 +#define MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_MASK 0xffffffff + +// TCDM 2D transfer stride value configuration bitfield. (access: W) +#define MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_BIT 0 +#define MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_WIDTH 32 +#define MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_MASK 0xffffffff + +// Transfer status bitfield: TID_TR[i]=1'b1 means that transfer with TID i is active. (access: R) +#define MCHAN_STATUS_STATUS_TID_TR_BIT 0 +#define MCHAN_STATUS_STATUS_TID_TR_WIDTH 16 +#define MCHAN_STATUS_STATUS_TID_TR_MASK 0xffff + +// Transfer status bitfield: - TID_TR[i]=1'b0 means that transfer allocator with TID i-16 is free. - TID_TR[i]=1'b1 means that transfer allocator with TID i-16 is reserved. (access: R) +#define MCHAN_STATUS_STATUS_TID_ALLOC_BIT 16 +#define MCHAN_STATUS_STATUS_TID_ALLOC_WIDTH 16 +#define MCHAN_STATUS_STATUS_TID_ALLOC_MASK 0xffff0000 + +// Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i. (access: W) +#define MCHAN_STATUS_FREE_TID_TID_FREE_BIT 0 +#define MCHAN_STATUS_FREE_TID_TID_FREE_WIDTH 16 +#define MCHAN_STATUS_FREE_TID_TID_FREE_MASK 0xffff + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int cmd :32; // Format is operation dependent. See below. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_t; + +typedef union { + struct { + unsigned int status :32; // Format is operation dependent. See below. + }; + unsigned int raw; +} __attribute__((packed)) mchan_status_t; + +typedef union { + struct { + unsigned int len :17; // Transfer length in bytes configuration bitfield. + unsigned int type :1 ; // Transfer direction configuration bitfield: - 1'b0: L1 to L2 - 1'b1: L2 to L2 + unsigned int inc :1 ; // Transfer incremental configuration bitfield: - 1'b0: non incremental - 1'b1: incremental + unsigned int _2d_ext :1 ; // Transfer type configuration bitfield: - 1'b0: linear transfer in EXT interface - 1'b1: 2D transfer in EXT interface + unsigned int ele :1 ; // Transfer event generation configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int ile :1 ; // Transfer interrupt generation configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int ble :1 ; // Transfer event or interrupt broadcast configuration bitfield: - 1'b0: event or interrupt is routed to the cluster core who initiated the transfer - 1'b1: event or interrupt are broadcasted to all cluster cores + unsigned int _2d_tcdm :1 ; // Transfer type configuration bitfield: - 1'b0: linear transfer in TCDM interface - 1'b1: 2D transfer in TCDM interface + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_cmd_t; + +typedef union { + struct { + unsigned int tid :4 ; // Transfer identifier value bitfield. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_get_tid_t; + +typedef union { + struct { + unsigned int addr :32; // Transfer L1 base address configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_tcdm_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Transfer L2 base address configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_ext_addr_t; + +typedef union { + struct { + unsigned int _2d_ext_count :32; // EXT 2D transfer conut value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_2d_ext_count_t; + +typedef union { + struct { + unsigned int _2d_ext_stride :32; // EXT 2D transfer stride value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_2d_ext_stride_t; + +typedef union { + struct { + unsigned int _2d_tcdm_count :32; // TCDM 2D transfer conut value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_2d_tcdm_count_t; + +typedef union { + struct { + unsigned int _2d_tcdm_stride :32; // TCDM 2D transfer stride value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) mchan_cmd_2d_tcdm_stride_t; + +typedef union { + struct { + unsigned int tid_tr :16; // Transfer status bitfield: TID_TR[i]=1'b1 means that transfer with TID i is active. + unsigned int tid_alloc :16; // Transfer status bitfield: - TID_TR[i]=1'b0 means that transfer allocator with TID i-16 is free. - TID_TR[i]=1'b1 means that transfer allocator with TID i-16 is reserved. + }; + unsigned int raw; +} __attribute__((packed)) mchan_status_status_t; + +typedef union { + struct { + unsigned int tid_free :16; // Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i. + }; + unsigned int raw; +} __attribute__((packed)) mchan_status_free_tid_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_mchan_cmd : public vp::reg_32 +{ +public: + inline void cmd_set(uint32_t value) { this->set_field(value, MCHAN_CMD_CMD_BIT, MCHAN_CMD_CMD_WIDTH); } + inline uint32_t cmd_get() { return this->get_field(MCHAN_CMD_CMD_BIT, MCHAN_CMD_CMD_WIDTH); } +}; + +class vp_mchan_status : public vp::reg_32 +{ +public: + inline void status_set(uint32_t value) { this->set_field(value, MCHAN_STATUS_STATUS_BIT, MCHAN_STATUS_STATUS_WIDTH); } + inline uint32_t status_get() { return this->get_field(MCHAN_STATUS_STATUS_BIT, MCHAN_STATUS_STATUS_WIDTH); } +}; + +class vp_mchan_cmd_tcdm_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, MCHAN_CMD_TCDM_ADDR_ADDR_BIT, MCHAN_CMD_TCDM_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(MCHAN_CMD_TCDM_ADDR_ADDR_BIT, MCHAN_CMD_TCDM_ADDR_ADDR_WIDTH); } +}; + +class vp_mchan_cmd_ext_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, MCHAN_CMD_EXT_ADDR_ADDR_BIT, MCHAN_CMD_EXT_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(MCHAN_CMD_EXT_ADDR_ADDR_BIT, MCHAN_CMD_EXT_ADDR_ADDR_WIDTH); } +}; + +class vp_mchan_cmd_2d_ext_count : public vp::reg_32 +{ +public: + inline void _2d_ext_count_set(uint32_t value) { this->set_field(value, MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_BIT, MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_WIDTH); } + inline uint32_t _2d_ext_count_get() { return this->get_field(MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_BIT, MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_WIDTH); } +}; + +class vp_mchan_cmd_2d_ext_stride : public vp::reg_32 +{ +public: + inline void _2d_ext_stride_set(uint32_t value) { this->set_field(value, MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_BIT, MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_WIDTH); } + inline uint32_t _2d_ext_stride_get() { return this->get_field(MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_BIT, MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_WIDTH); } +}; + +class vp_mchan_cmd_2d_tcdm_count : public vp::reg_32 +{ +public: + inline void _2d_tcdm_count_set(uint32_t value) { this->set_field(value, MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_BIT, MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_WIDTH); } + inline uint32_t _2d_tcdm_count_get() { return this->get_field(MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_BIT, MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_WIDTH); } +}; + +class vp_mchan_cmd_2d_tcdm_stride : public vp::reg_32 +{ +public: + inline void _2d_tcdm_stride_set(uint32_t value) { this->set_field(value, MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_BIT, MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_WIDTH); } + inline uint32_t _2d_tcdm_stride_get() { return this->get_field(MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_BIT, MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_WIDTH); } +}; + +class vp_mchan_status_status : public vp::reg_16 +{ +public: + inline void tid_tr_set(uint16_t value) { this->set_field(value, MCHAN_STATUS_STATUS_TID_TR_BIT, MCHAN_STATUS_STATUS_TID_TR_WIDTH); } + inline uint16_t tid_tr_get() { return this->get_field(MCHAN_STATUS_STATUS_TID_TR_BIT, MCHAN_STATUS_STATUS_TID_TR_WIDTH); } + inline void tid_alloc_set(uint16_t value) { this->set_field(value, MCHAN_STATUS_STATUS_TID_ALLOC_BIT, MCHAN_STATUS_STATUS_TID_ALLOC_WIDTH); } + inline uint16_t tid_alloc_get() { return this->get_field(MCHAN_STATUS_STATUS_TID_ALLOC_BIT, MCHAN_STATUS_STATUS_TID_ALLOC_WIDTH); } +}; + +class vp_mchan_status_free_tid : public vp::reg_16 +{ +public: + inline void tid_free_set(uint16_t value) { this->set_field(value, MCHAN_STATUS_FREE_TID_TID_FREE_BIT, MCHAN_STATUS_FREE_TID_TID_FREE_WIDTH); } + inline uint16_t tid_free_get() { return this->get_field(MCHAN_STATUS_FREE_TID_TID_FREE_BIT, MCHAN_STATUS_FREE_TID_TID_FREE_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int cmd ; // Cluster DMA configuration register. + unsigned int status ; // Cluster DMA status register. + unsigned int cmd_cmd ; // Transfer length in bytes configuration bitfield. + unsigned int cmd_get_tid ; // Transfer identifier value bitfield. + unsigned int cmd_tcdm_addr ; // Transfer L1 base address configuration bitfield. + unsigned int cmd_ext_addr ; // Transfer L2 base address configuration bitfield. + unsigned int cmd_2d_ext_count; // EXT 2D transfer conut value configuration bitfield. + unsigned int cmd_2d_ext_stride; // EXT 2D transfer stride value configuration bitfield. + unsigned int cmd_2d_tcdm_count; // TCDM 2D transfer conut value configuration bitfield. + unsigned int cmd_2d_tcdm_stride; // TCDM 2D transfer stride value configuration bitfield. + unsigned int status_status ; // Transfer status bitfield: TID_TR[i]=1'b1 means that transfer with TID i is active. + unsigned int status_free_tid ; // Transfer canceller configuration bitfield. Writing a 1'b1 in TID_FREE[i] will free transfer with TID i. +} __attribute__((packed)) mchan_mchan_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t mchan_cmd_get(uint32_t base) { return ARCHI_READ(base, MCHAN_CMD_OFFSET); } +static inline void mchan_cmd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MCHAN_CMD_OFFSET, value); } + +static inline uint32_t mchan_status_get(uint32_t base) { return ARCHI_READ(base, MCHAN_STATUS_OFFSET); } +static inline void mchan_status_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MCHAN_STATUS_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MCHAN_CMD_CMD_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_CMD_CMD_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_CMD_CMD_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_CMD_CMD(val) ((val) << 0) + +#define MCHAN_STATUS_STATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_STATUS_STATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_STATUS_STATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_STATUS_STATUS(val) ((val) << 0) + +#define MCHAN_CMD_CMD_LEN_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define MCHAN_CMD_CMD_LEN_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define MCHAN_CMD_CMD_LEN_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define MCHAN_CMD_CMD_LEN(val) ((val) << 0) + +#define MCHAN_CMD_CMD_TYPE_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define MCHAN_CMD_CMD_TYPE_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define MCHAN_CMD_CMD_TYPE_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define MCHAN_CMD_CMD_TYPE(val) ((val) << 17) + +#define MCHAN_CMD_CMD_INC_GET(value) (ARCHI_BEXTRACTU((value),1,18)) +#define MCHAN_CMD_CMD_INC_GETS(value) (ARCHI_BEXTRACT((value),1,18)) +#define MCHAN_CMD_CMD_INC_SET(value,field) (ARCHI_BINSERT((value),(field),1,18)) +#define MCHAN_CMD_CMD_INC(val) ((val) << 18) + +#define MCHAN_CMD_CMD__2D_EXT_GET(value) (ARCHI_BEXTRACTU((value),1,19)) +#define MCHAN_CMD_CMD__2D_EXT_GETS(value) (ARCHI_BEXTRACT((value),1,19)) +#define MCHAN_CMD_CMD__2D_EXT_SET(value,field) (ARCHI_BINSERT((value),(field),1,19)) +#define MCHAN_CMD_CMD__2D_EXT(val) ((val) << 19) + +#define MCHAN_CMD_CMD_ELE_GET(value) (ARCHI_BEXTRACTU((value),1,20)) +#define MCHAN_CMD_CMD_ELE_GETS(value) (ARCHI_BEXTRACT((value),1,20)) +#define MCHAN_CMD_CMD_ELE_SET(value,field) (ARCHI_BINSERT((value),(field),1,20)) +#define MCHAN_CMD_CMD_ELE(val) ((val) << 20) + +#define MCHAN_CMD_CMD_ILE_GET(value) (ARCHI_BEXTRACTU((value),1,21)) +#define MCHAN_CMD_CMD_ILE_GETS(value) (ARCHI_BEXTRACT((value),1,21)) +#define MCHAN_CMD_CMD_ILE_SET(value,field) (ARCHI_BINSERT((value),(field),1,21)) +#define MCHAN_CMD_CMD_ILE(val) ((val) << 21) + +#define MCHAN_CMD_CMD_BLE_GET(value) (ARCHI_BEXTRACTU((value),1,22)) +#define MCHAN_CMD_CMD_BLE_GETS(value) (ARCHI_BEXTRACT((value),1,22)) +#define MCHAN_CMD_CMD_BLE_SET(value,field) (ARCHI_BINSERT((value),(field),1,22)) +#define MCHAN_CMD_CMD_BLE(val) ((val) << 22) + +#define MCHAN_CMD_CMD__2D_TCDM_GET(value) (ARCHI_BEXTRACTU((value),1,23)) +#define MCHAN_CMD_CMD__2D_TCDM_GETS(value) (ARCHI_BEXTRACT((value),1,23)) +#define MCHAN_CMD_CMD__2D_TCDM_SET(value,field) (ARCHI_BINSERT((value),(field),1,23)) +#define MCHAN_CMD_CMD__2D_TCDM(val) ((val) << 23) + +#define MCHAN_CMD_GET_TID_TID_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define MCHAN_CMD_GET_TID_TID_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define MCHAN_CMD_GET_TID_TID_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define MCHAN_CMD_GET_TID_TID(val) ((val) << 0) + +#define MCHAN_CMD_TCDM_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_CMD_TCDM_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_CMD_TCDM_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_CMD_TCDM_ADDR_ADDR(val) ((val) << 0) + +#define MCHAN_CMD_EXT_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_CMD_EXT_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_CMD_EXT_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_CMD_EXT_ADDR_ADDR(val) ((val) << 0) + +#define MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_CMD_2D_EXT_COUNT__2D_EXT_COUNT(val) ((val) << 0) + +#define MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_CMD_2D_EXT_STRIDE__2D_EXT_STRIDE(val) ((val) << 0) + +#define MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_CMD_2D_TCDM_COUNT__2D_TCDM_COUNT(val) ((val) << 0) + +#define MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define MCHAN_CMD_2D_TCDM_STRIDE__2D_TCDM_STRIDE(val) ((val) << 0) + +#define MCHAN_STATUS_STATUS_TID_TR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define MCHAN_STATUS_STATUS_TID_TR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define MCHAN_STATUS_STATUS_TID_TR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define MCHAN_STATUS_STATUS_TID_TR(val) ((val) << 0) + +#define MCHAN_STATUS_STATUS_TID_ALLOC_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define MCHAN_STATUS_STATUS_TID_ALLOC_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define MCHAN_STATUS_STATUS_TID_ALLOC_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define MCHAN_STATUS_STATUS_TID_ALLOC(val) ((val) << 16) + +#define MCHAN_STATUS_FREE_TID_TID_FREE_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define MCHAN_STATUS_FREE_TID_TID_FREE_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define MCHAN_STATUS_FREE_TID_TID_FREE_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define MCHAN_STATUS_FREE_TID_TID_FREE(val) ((val) << 0) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/efuse/efuse_v1.h b/sw/pulp-sdk/archi/include/archi/efuse/efuse_v1.h new file mode 100644 index 0000000..98adf35 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/efuse/efuse_v1.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_EFUSE_EFUSE_V1_H__ +#define __ARCHI_EFUSE_EFUSE_V1_H__ + +#define EFUSE_CMD_OFFSET 0x000 +#define EFUSE_CFG_OFFSET 0x004 +#define EFUSE_REGS_OFFSET 0x200 + +#define EFUSE_CMD_READ 0x1 +#define EFUSE_CMD_WRITE 0x2 +#define EFUSE_CMD_SLEEP 0x4 + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/eu/eu_v1.h b/sw/pulp-sdk/archi/include/archi/eu/eu_v1.h new file mode 100644 index 0000000..fad814c --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/eu/eu_v1.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_EU_EU_V1_H_ +#define __ARCHI_EU_EU_V1_H_ + +#define PULP_CKG_MAX_NB_BARRIERS 18 + +#define PULP_NB_GP_EVENTS 3 + // TODO this is wrong should be 1 !!! +#define PULP_FIRST_GP_EVENT 0 +#define PULP_HW_BAR_EVENT 0 + + +#define PULP_DEMUX_CORE_CLKGATE_OFFSET 0x0 +#define PULP_DEMUX_EV_BUFFER_CLEAR_OFFSET 0x4 + +#define PULP_BODYBIAS_SRAM0_OFFSET 0x0 +#define PULP_BODYBIAS_SRAM1_OFFSET 0x4 +#define PULP_BODYBIAS_SRAM2_OFFSET 0x8 +#define PULP_BODYBIAS_SRAM3_OFFSET 0xC +#define PULP_BODYBIAS_CORE0_OFFSET 0x10 +#define PULP_BODYBIAS_CORE1_OFFSET 0x14 +#define PULP_BODYBIAS_CORE2_OFFSET 0x18 +#define PULP_BODYBIAS_CORE3_OFFSET 0x1C + +#define PULP_CLKGATE_SRAM0_OFFSET 0x100 +#define PULP_CLKGATE_SRAM1_OFFSET 0x104 +#define PULP_CLKGATE_SRAM2_OFFSET 0x108 +#define PULP_CLKGATE_SRAM3_OFFSET 0x10C +#define PULP_CLKGATE_SCM_OFFSET 0x124 +#define PULP_CLKGATE_STATUS 0x170 + +#define PULP_CLKGATE_TRIGG_BARRIER 0x35c +#define PULP_CLKGATE_WAIT_BARRIER 0x36c +#define PULP_CLKGATE_SET_BARRIER 0x374 +#define PULP_CLKGATE_SET_BARRIER_SIZE (0x4*PULP_CKG_MAX_NB_BARRIERS) + + +#define PULP_EV_MASK_LOW 0x100 +#define PULP_EV_MASK_LOW_SIZE 0x040 + +#define PULP_EV_BUFFER_LOW 0x180 +#define PULP_EV_BUFFER_LOW_SIZE 0x040 + +#define PULP_CORE_CLKGATE 0x308 + +#define PULP_EVNT_GEN 0x30C + +#define PULP_EVNT_GEN_GP0 0x360 +#define PULP_EVNT_GEN_GP1 0x364 +#define PULP_EVNT_GEN_GP2 0x368 + + +#define PULP_DEMUX_IRQ_BUFFER_CLEAR_OFFSET 0x8 +#define PULP_IRQ_MASK_LOW_BASE 0X200 +#define PULP_IRQ_MASK_LOW_SIZE 0X040 +#define PULP_IRQ_MASK_HIGH_BASE 0X240 +#define PULP_IRQ_MASK_HIGH_SIZE 0X040 +#define PULP_IRQ_BUFFER_LOW_BASE 0X280 +#define PULP_IRQ_BUFFER_LOW_SIZE 0X040 +#define PULP_IRQ_BUFFER_HIGH_BASE 0X2C0 +#define PULP_IRQ_BUFFER_HIGH_SIZE 0X040 + +#define PULP_READ_IRQ_ID_BASE 0X31C +#define PULP_READ_IRQ_ID_SIZE 0X040 + + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/eu/eu_v3.h b/sw/pulp-sdk/archi/include/archi/eu/eu_v3.h new file mode 100644 index 0000000..f74983c --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/eu/eu_v3.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_EU_EU_V3_H__ +#define __ARCHI_EU_EU_V3_H__ + +/* + * Register memory map + */ + +// Global offsets +#define EU_CORES_AREA_OFFSET 0x0000 +#define EU_CORES_AREA_SIZE 0x0400 +#define EU_CORE_AREA_SIZE_LOG2 6 +#define EU_CORE_AREA_SIZE (1<>EU_CORE_AREA_SIZE_LOG2) +#define EU_ROM_AREA_OFFSET_GET(coreId) (EU_CORE_AREA_OFFSET_GET(coreId) + EU_ROM_AREA_OFFSET) +#define EU_BARRIER_AREA_OFFSET_GET(barrier) ((barrier)*EU_BARRIER_SIZE) +#define EU_BARRIER_AREA_BARRIERID_GET(offset) (((offset) & (EU_BARRIER_AREA_SIZE - 1)) >> EU_BARRIER_SIZE_LOG2) +#define EU_MUTEX_AREA_OFFSET_GET(mutex) ((mutex)*EU_MUTEX_AREA_SIZE) +#define EU_MUTEX_AREA_MUTEXID_GET(offset) (((offset) & (EU_MUTEX_AREA_SIZE - 1)) >> 2) +#define EU_DISPATCH_AREA_OFFSET_GET(dispatch) ((dispatch)*EU_DISPATCH_AREA_SIZE) +#define EU_DISPATCH_AREA_DISPATCHID_GET(dispatch) (((offset) & (EU_DISPATCH_AREA_SIZE - 1)) >> 3) + +// Core area +#define EU_CORE_TRIGG_SW_EVENT_OFFSET(event) (EU_CORE_TRIGG_SW_EVENT + ((event)*0x4)) +#define EU_CORE_TRIGG_SW_EVENT_WAIT_OFFSET(event) (EU_CORE_TRIGG_SW_EVENT_WAIT + ((event)*0x4)) +#define EU_CORE_TRIGG_SW_EVENT_WAIT_CLEAR_OFFSET(event) (EU_CORE_TRIGG_SW_EVENT_WAIT_CLEAR + ((event)*0x4)) + +// ROM area +#define EU_ROM_EVENT_SOURCE_OFFSET(event) (EU_ROM_EVENT_SOURCE + ((event)*0x4)) + +// TODO should be moved to chip part ? +#define PULP_NB_GP_EVENTS 8 +#define PULP_FIRST_GP_EVENT 0 +#define PULP_TIMER0_EVENT 10 +#define PULP_TIMER1_EVENT 11 + // TODO the real value is not yet specified +#define EVENT_HWCE 15 +#define PULP_HW_BAR_EVENT 16 +#define PULP_MUTEX_EVENT 17 +#define PULP_DISPATCH_EVENT 18 +#define PULP_LOOP_EVENT 19 +#if PULP_CHIP_FAMILY == CHIP_GAP +#define PULP_FC_SOC_EVENTS_EVENT 27 +#else +#define PULP_FC_SOC_EVENTS_EVENT 26 +#endif +#define PULP_SOC_EVENTS_EVENT 27 +#define PULP_SOC_TRIGGER_EVENT 28 +#define PULP_SOC_LOCK_EVENT 29 +#define PULP_SOC_HW_BAR_EVENT 30 + +// SOC areas +#define EU_SOC_BARRIER_AREA_OFFSET_GET(barrier) ((barrier)*EU_SOC_BARRIER_SIZE) +#define EU_SOC_BARRIER_AREA_BARRIERID_GET(offset) (((offset) & (EU_SOC_BARRIER_AREA_SIZE - 1)) >> EU_SOC_BARRIER_SIZE_LOG2) + +#define EU_SOC_LOCK_AREA_OFFSET_GET(lock) ((lock)*EU_SOC_LOCK_SIZE) +#define EU_SOC_LOCK_AREA_LOCKID_GET(offset) (((offset) & (EU_SOC_LOCK_AREA_SIZE - 1)) >> EU_SOC_LOCK_SIZE_LOG2) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/fll/fll_v0.h b/sw/pulp-sdk/archi/include/archi/fll/fll_v0.h new file mode 100644 index 0000000..65aa27b --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/fll/fll_v0.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_FLL_FLL_V0_H__ +#define __ARCHI_FLL_FLL_V0_H__ + +#define SOC_FLL_CONFIG_REG_1 ( ARCHI_FLL_ADDR + 0x04 ) +#define SOC_FLL_CONFIG_REG_2 ( ARCHI_FLL_ADDR + 0x08 ) +#define SOC_FLL_CONFIG_REG_3 ( ARCHI_FLL_ADDR + 0x0C ) +#define SOC_FLL_LOCK_REG ( ARCHI_FLL_ADDR + 0x20 ) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/fll/fll_v1.h b/sw/pulp-sdk/archi/include/archi/fll/fll_v1.h new file mode 100644 index 0000000..e371ae3 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/fll/fll_v1.h @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_FLL_FLL_V1_H__ +#define __ARCHI_FLL_FLL_V1_H__ + + +#define FLL_STATUS_OFFSET 0x000 +#define FLL_CONF1_OFFSET 0x004 +#define FLL_CONF2_OFFSET 0x008 +#define FLL_INTEGRATOR_OFFSET 0x00C + + +#define FLL_STATUS_MULT_FACTOR_BIT 0 +#define FLL_STATUS_MULT_FACTOR_WIDTH 16 +#define FLL_STATUS_MULT_FACTOR_MASK (0xFFFF) + + + +#define FLL_CONF1_MODE_BIT 31 +#define FLL_CONF1_MODE_WIDTH 1 +#define FLL_CONF1_MODE_MASK (0x80000000) + +#define FLL_CONF1_LOCK_BIT 30 +#define FLL_CONF1_LOCK_WIDTH 1 +#define FLL_CONF1_LOCK_MASK (0x40000000) + +#define FLL_CONF1_DIV_BIT 26 +#define FLL_CONF1_DIV_WIDTH 4 +#define FLL_CONF1_DIV_MASK (0x3C000000) + +#define FLL_CONF1_DCO_BIT 16 +#define FLL_CONF1_DCO_WIDTH 10 +#define FLL_CONF1_DCO_MASK (0x03FF0000) + +#define FLL_CONF1_MULT_FACTOR_BIT 0 +#define FLL_CONF1_MULT_FACTOR_WIDTH 16 +#define FLL_CONF1_MULT_FACTOR_MASK (0xFFFF) + +#define FLL_CONF1_MODE_STANDALONE 0 +#define FLL_CONF1_MODE_NORMAL 1 + + + +#define FLL_CONF2_GAIN_BIT 0 +#define FLL_CONF2_GAIN_WIDTH 4 +#define FLL_CONF2_GAIN_MASK (0x0000000F) + +#define FLL_CONF2_DEASSERT_CYCLES_BIT 4 +#define FLL_CONF2_DEASSERT_CYCLES_WIDTH 6 +#define FLL_CONF2_DEASSERT_CYCLES_MASK (0x000003F0) + +#define FLL_CONF2_ASSERT_CYCLES_BIT 10 +#define FLL_CONF2_ASSERT_CYCLES_WIDTH 6 +#define FLL_CONF2_ASSERT_CYCLES_MASK (0x0000FC00) + +#define FLL_CONF2_TOLERANCE_BIT 16 +#define FLL_CONF2_TOLERANCE_WIDTH 12 +#define FLL_CONF2_TOLERANCE_MASK (0x0FFF0000) + +#define FLL_CONF2_STA_CLOCK_BIT 29 +#define FLL_CONF2_STA_CLOCK_WIDTH 1 +#define FLL_CONF2_STA_CLOCK_MASK (0x20000000) + +#define FLL_CONF2_OPEN_LOOP_BIT 30 +#define FLL_CONF2_OPEN_LOOP_WIDTH 1 +#define FLL_CONF2_OPEN_LOOP_MASK (0x40000000) + +#define FLL_CONF2_DITHERING_BIT 31 +#define FLL_CONF2_DITHERING_WIDTH 1 +#define FLL_CONF2_DITHERING_MASK (0x80000000) + + + +#define FLL_INTEGRATOR_INT_BIT 16 +#define FLL_INTEGRATOR_INT_WIDTH 10 +#define FLL_INTEGRATOR_INT_MASK (0x03FF0000) + +#define FLL_INTEGRATOR_FRACT_BIT 6 +#define FLL_INTEGRATOR_FRACT_WIDTH 10 +#define FLL_INTEGRATOR_FRACT_MASK (0x0000FFC0) + + + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(_ASMLANGUAGE) + +typedef union { + struct { + unsigned int actual_mult_factor:16; /* Fll current multiplication factor */ + unsigned int reserved:16; + }; + unsigned int raw; +} fll_reg_status_t; + +typedef union { + struct { + unsigned int mult_factor:16; /* Fll requested multiplication factor, reset: 0x5f5. + If RefClk=32768 and Div=2 Freq= 24.98 MHz */ + unsigned int dco_input:10; /* DCO input code for stand alone mode, reset: 0x121 */ + unsigned int clock_out_divider:4; /* Fll clock output divider, reset: 0x1 e.g div 2 */ + unsigned int output_lock_enable:1;/* Fll output gated by lock signal (active high), reset 1 */ + unsigned int mode:1; /* Fll mode. 0: stand alone (unlocked), 1: normal, reset 0 */ + }; + unsigned int raw; +} fll_reg_conf1_t; + +typedef union { + struct { + unsigned int loop_gain:4; /* Fll loop gain, reset: 0x9 */ + unsigned int de_assert_cycles:6; /* Normal mode: number of refclock unstable cycles till lock de-assert + Standalone mode: lower 6 bits of lock assert counter. Reset: 0x10 */ + unsigned int assert_cycles:6; /* Normal mode: number of refclock stable cycles till lock assert + Standalone mode: upper 6 bits of lock assert counter. Reset: 0x10 */ + unsigned int lock_tolerance:12; /* Lock tolerance: margin arounf the target mult factor where clock is + considered as stable. Reset: 0x200 + With Fmax=250Mhw (Div=2^4), Fmin=32K (Div=2^15) + Tolerance: 32K*(512/16)=1.048MHz .. 512 Hz */ + unsigned int pad:1; + unsigned int config_clock_sel:1; /* Select ref clock when mode = standalone, 0:RefClock, 1: DcoOut. Reset:1 */ + unsigned int open_loop:1; /* When 1 clock operates in open loop when locked */ + unsigned int dithering:1; /* When 1 Dithering is enabled */ + }; + unsigned int raw; +} fll_reg_conf2_t; + +typedef union { + struct { + unsigned int pad1:6; + unsigned int state_fract_part:10; /* Integrator state: fractional part (dithering input unit) */ + unsigned int state_int_part:10; /* Integratot state: integer part (DCO input bits) */ + unsigned int pad2:6; + }; + unsigned int raw; +} fll_reg_integrator_t; + +#endif + + + +#define FLL_STATUS_MULT_FACTOR_GET(value) ((((unsigned int)(value)) >> 0) & 0xFFFF) +#define FLL_STATUS_MULT_FACTOR_SET(dst,src,factor) (__BITINSERT((dst),(src),16,0)) +#define FLL_STATUS_MULT_FACTOR(factor) ((factor) << 16) + + +#define FLL_CONF1_MODE_GET(value) ((((unsigned int)(value)) >> 16) & 0x1) +#define FLL_CONF1_MODE_SET(dst,src) (__BITINSERT((dst),(src),1,31)) +#define FLL_CONF1_MODE(factor) ((factor) << 31) + +#define FLL_CONF1_LOCK_GET(value) ((((unsigned int)(value)) >> 16) & 0x1) +#define FLL_CONF1_LOCK_SET(dst,src) (__BITINSERT((dst),(src),30,1)) +#define FLL_CONF1_LOCK(factor) ((factor) << 30) + +#define FLL_CONF1_DIV_GET(value) ((((unsigned int)(value)) >> 26) & 0xF) +#define FLL_CONF1_DIV_SET(dst,src) (__BITINSERT((dst),(src),26,4)) +#define FLL_CONF1_DIV(factor) ((factor) << 26) + +#define FLL_CONF1_DCO_GET(value) ((((unsigned int)(value)) >> 16) & 0x3FF) +#define FLL_CONF1_DCO_SET(dst,src) (__BITINSERT((dst),(src),16,10)) +#define FLL_CONF1_DCO(factor) ((factor) << 16) + +#define FLL_CONF1_MULT_FACTOR_GET(value) ((((unsigned int)(value)) >> 0) &0xFFFF) +#define FLL_CONF1_MULT_FACTOR_SET(dst,src) (__BITINSERT((dst),(src),0,16)) +#define FLL_CONF1_MULT_FACTOR(factor) ((factor) << 0) + + + +#define FLL_CONF2_GAIN_GET(value) ((((unsigned int)(value)) >> 0) & 0xF) +#define FLL_CONF2_GAIN_SET(dst,src) (__BITINSERT((dst),(src),4,0)) +#define FLL_CONF2_GAIN(value) ((value) << 0) + +#define FLL_CONF2_ASSERT_CYCLES_GET(value) ((((unsigned int)(value)) >> 4) & 0x3F) +#define FLL_CONF2_ASSERT_CYCLES_SET(dst,src) (__BITINSERT((dst),(src),6,4)) +#define FLL_CONF2_ASSERT_CYCLES(value) ((value) << 4) + +#define FLL_CONF2_DEASSERT_CYCLES_GET(value) ((((unsigned int)(value)) >> 10) & 0x3F) +#define FLL_CONF2_DEASSERT_CYCLES_SET(dst,src) (__BITINSERT((dst),(src),6,10)) +#define FLL_CONF2_DEASSERT_CYCLES(value) ((value) << 10) + +#define FLL_CONF2_TOLERANCE_GET(value) ((((unsigned int)(value)) >> 16) & 0xFFF) +#define FLL_CONF2_TOLERANCE_SET(dst,src) (__BITINSERT((dst),(src),12,16)) +#define FLL_CONF2_TOLERANCE(value) ((value) << 16) + +#define FLL_CONF2_STA_CLOCK_GET(value) ((((unsigned int)(value)) >> 29) & 0x1) +#define FLL_CONF2_STA_CLOCK_SET(dst,src) (__BITINSERT((dst),(src),1,29)) +#define FLL_CONF2_STA_CLOCK(value) ((value) << 29) + +#define FLL_CONF2_OPEN_LOOP_GET(value) ((((unsigned int)(value)) >> 30) & 0x1) +#define FLL_CONF2_OPEN_LOOP_SET(dst,src) (__BITINSERT((dst),(src),1,30)) +#define FLL_CONF2_OPEN_LOOP(value) ((value) << 30) + +#define FLL_CONF2_DITHER_GET(value) ((((unsigned int)(value)) >> 31) & 0x1) +#define FLL_CONF2_DITHER_SET(dst,src) (__BITINSERT((dst),(src),1,31)) +#define FLL_CONF2_DITHER(value) ((value) << 31) + + + +#define FLL_INTEGRATOR_FRACT_GET(value) ((((unsigned int)(value)) >> 6) & 0x3FF) +#define FLL_INTEGRATOR_FRACT_SET(dst,src) (__BITINSERT((dst),(src),6,10)) +#define FLL_INTEGRATOR_FRACT(value) ((value) << 6) + +#define FLL_INTEGRATOR_INT_GET(value) ((((unsigned int)(value)) >> 16) & 0x3FF) +#define FLL_INTEGRATOR_INT_SET(dst,src) (__BITINSERT((dst),(src),16,10)) +#define FLL_INTEGRATOR_INT(value) ((value) << 16) + + + + + + +/* Maximum Log2(DCO Frequency) */ +#define FLL_LOG2_MAXDCO 29 +/* Maximum Log2(Clok Divider) */ +#define FLL_LOG2_MAXDIV 15 +/* Maximum Log2(Multiplier) */ +#define FLL_LOG2_MAXM (FLL_LOG2_MAXDCO - ARCHI_REF_CLOCK_LOG2) + + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/gpio/gpio_v2.h b/sw/pulp-sdk/archi/include/archi/gpio/gpio_v2.h new file mode 100644 index 0000000..479846d --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/gpio/gpio_v2.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_GPIO_GPIO_V2_H__ +#define __ARCHI_GPIO_GPIO_V2_H__ + +#include "archi/gpio/gpio_v2_new.h" + +#define ARCHI_GPIO_PADDIR 0x0 // Direction i:0..31, GPIOi => Bit[i] = 1 Output, Bit[i] = 0 Input (Default) +#define ARCHI_GPIO_PADIN 0x4 // i:0..31, Bit[i] Received bit from GPIOi +#define ARCHI_GPIO_PADOUT 0x8 // i:0..31, Bit[i] Bit to transmit through GPIOi +#define ARCHI_GPIO_INTEN 0xC // i:0..31, Bit[i]=1 Enable Event for GPIOi +#define ARCHI_GPIO_INTTYPE0 0x10 // Interrupt Condition i:0..15, Bit[2*i:2*i+1] = 00 Falling edge on GPIOi + // = 01 Raising edge on GPIOi + // = 11 Raising then falling edge on GPIOi +#define ARCHI_GPIO_INTTYPE1 0x14 // Interrupt Condition i:0..15, Bit[2*i:2*i+1] = 00 Falling edge on GPIOi+16 + // = 01 Raising edge on GPIOi+16 + // = 11 Raising the falling edge on GPIOi+16 +#define ARCHI_GPIO_INTSTATUS 0x18 // Interrupt Status i:0..31, Bit[i]=1 Event received for GPIOi, bit is cleared when readen +#define GPIO_INTSTATUS_OFFSET ARCHI_GPIO_INTSTATUS +#define ARCHI_GPIO_EN 0x1C + +#define ARCHI_GPIO_PADCFG0 0x20 +#define ARCHI_GPIO_PADCFG1 0x24 +#define ARCHI_GPIO_PADCFG2 0x28 +#define ARCHI_GPIO_PADCFG3 0x2C +#define ARCHI_GPIO_PADCFG4 0x30 +#define ARCHI_GPIO_PADCFG5 0x34 +#define ARCHI_GPIO_PADCFG6 0x38 +#define ARCHI_GPIO_PADCFG7 0x3C + + +#define ARCHI_GPIO_PADDIR_IN 0 +#define ARCHI_GPIO_PADDIR_OUT 1 + +#define ARCHI_GPIO_INTTYPE_RISE 1 +#define ARCHI_GPIO_INTTYPE_FALL 0 +#define ARCHI_GPIO_INTTYPE_RISE_AND_FALL 2 + +#define ARCHI_GPIO_INTTYPE(id) (ARCHI_GPIO_INTTYPE0 + (id)*4) +#define ARCHI_GPIO_INTTYPE_NO(gpio) ((gpio) >> 4) +#define ARCHI_GPIO_INTTYPE_GPIO(inttype) ((inttype)*16) +#define ARCHI_GPIO_INTTYPE_SIZE 2 +#define ARCHI_GPIO_INTTYPE_BIT(pad) (((pad) & 0xF) << 1) +#define ARCHI_GPIO_INTTYPE_GET(gpio,value) (((value) >> ARCHI_GPIO_INTTYPE_BIT(gpio)) & ((1<> 2) +#define ARCHI_GPIO_PADCFG_GROUP(gpio) ((gpio) & ((1<<2)-1)) + + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + int pull:1; + int strength:1; + int reserved:6; +} __attribute__((packed)) gpio_padcfg_group_t; + +typedef union { + gpio_padcfg_group_t pin[4]; + uint32_t raw; +} __attribute__((packed)) gpio_reg_padcfg_t; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/gpio/gpio_v2_new.h b/sw/pulp-sdk/archi/include/archi/gpio/gpio_v2_new.h new file mode 100644 index 0000000..615d3f0 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/gpio/gpio_v2_new.h @@ -0,0 +1,1346 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_GPIO_GPIO_V2_NEW_H__ +#define __INCLUDE_ARCHI_GPIO_GPIO_V2_NEW_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// GPIO pad direction configuration +#define GPIO_APBGPIO_PADDIR_OFFSET 0x0 + +// GPIO pad input value +#define GPIO_APBGPIO_PADIN_OFFSET 0x4 + +// GPIO pad output value +#define GPIO_APBGPIO_PADOUT_OFFSET 0x8 + +// GPIO pad interrupt enable configuration +#define GPIO_APBGPIO_INTEN_OFFSET 0xc + +// GPIO pad interrupt type bit 0 configuration +#define GPIO_APBGPIO_INTTYPE0_OFFSET 0x10 + +// GPIO pad interrupt type bit 1 configuration +#define GPIO_APBGPIO_INTTYPE1_OFFSET 0x14 + +// GPIO pad interrupt status +#define GPIO_APBGPIO_INTSTATUS_OFFSET 0x18 + +// GPIO pad enable configuration +#define GPIO_APBGPIO_GPIOEN_OFFSET 0x1c + +// GPIO pad pin 0 to 3 configuration +#define GPIO_APBGPIO_PADCFG0_OFFSET 0x20 + +// GPIO pad pin 4 to 7 configuration +#define GPIO_APBGPIO_PADCFG1_OFFSET 0x24 + +// GPIO pad pin 8 to 11 configuration +#define GPIO_APBGPIO_PADCFG2_OFFSET 0x28 + +// GPIO pad pin 12 to 15 configuration +#define GPIO_APBGPIO_PADCFG3_OFFSET 0x2c + +// GPIO pad pin 16 to 19 configuration +#define GPIO_APBGPIO_PADCFG4_OFFSET 0x30 + +// GPIO pad pin 20 to 23 configuration +#define GPIO_APBGPIO_PADCFG5_OFFSET 0x34 + +// GPIO pad pin 24 to 27 configuration +#define GPIO_APBGPIO_PADCFG6_OFFSET 0x38 + +// GPIO pad pin 28 to 31 configuration +#define GPIO_APBGPIO_PADCFG7_OFFSET 0x3c + + + +// +// REGISTERS FIELDS +// + +// Configure direction of the 32 GPIOs: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] (access: R/W) +#define GPIO_APBGPIO_PADDIR_DIR_BIT 0 +#define GPIO_APBGPIO_PADDIR_DIR_WIDTH 32 +#define GPIO_APBGPIO_PADDIR_DIR_MASK 0xffffffff + +// Read value of the 32 GPIOs. (access: R) +#define GPIO_APBGPIO_PADIN_DATA_IN_BIT 0 +#define GPIO_APBGPIO_PADIN_DATA_IN_WIDTH 32 +#define GPIO_APBGPIO_PADIN_DATA_IN_MASK 0xffffffff + +// Write value to the 32 GPIOs. (access: R/W) +#define GPIO_APBGPIO_PADOUT_DATA_OUT_BIT 0 +#define GPIO_APBGPIO_PADOUT_DATA_OUT_WIDTH 32 +#define GPIO_APBGPIO_PADOUT_DATA_OUT_MASK 0xffffffff + +// Configure interrupt mode for the 32 GPIOs: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] (access: R/W) +#define GPIO_APBGPIO_INTEN_INTEN_BIT 0 +#define GPIO_APBGPIO_INTEN_INTEN_WIDTH 32 +#define GPIO_APBGPIO_INTEN_INTEN_MASK 0xffffffff + +// Configure interrupt condition for the GPIO[15:0]: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) +#define GPIO_APBGPIO_INTTYPE0_INTTYPE0_BIT 0 +#define GPIO_APBGPIO_INTTYPE0_INTTYPE0_WIDTH 32 +#define GPIO_APBGPIO_INTTYPE0_INTTYPE0_MASK 0xffffffff + +// Configure interrupt condition for the GPIO[31:16]: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) +#define GPIO_APBGPIO_INTTYPE1_INTTYPE1_BIT 0 +#define GPIO_APBGPIO_INTTYPE1_INTTYPE1_WIDTH 32 +#define GPIO_APBGPIO_INTTYPE1_INTTYPE1_MASK 0xffffffff + +// Interrupt status flags for the 32 GPIOs. - bit[i]=1 when interrupt received on GPIO[i] Register is cleared when read. GPIO interrupt line is also cleared when this register is red. (access: R) +#define GPIO_APBGPIO_INTSTATUS_INTSTATUS_BIT 0 +#define GPIO_APBGPIO_INTSTATUS_INTSTATUS_WIDTH 32 +#define GPIO_APBGPIO_INTSTATUS_INTSTATUS_MASK 0xffffffff + +// Configure clock enable for the 32 GPIOs: - bit[i]=1'b0: disable mode for GPIO[i] - bit[i]=1'b1: enable mode for GPIO[i] GPIOs are gathered by groups of 4. The clock-gating of one group is done only if all 4 GPIOs are disabled. (access: R/W) +#define GPIO_APBGPIO_GPIOEN_GPIOEN_BIT 0 +#define GPIO_APBGPIO_GPIOEN_GPIOEN_WIDTH 32 +#define GPIO_APBGPIO_GPIOEN_GPIOEN_MASK 0xffffffff + +// Configure pull activation for GPIO[0]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_MASK 0x1 + +// Configure drive strength for GPIO[0]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_MASK 0x2 + +// Configure pull activation for GPIO[1]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_MASK 0x100 + +// Configure drive strength for GPIO[1]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_MASK 0x200 + +// Configure pull activation for GPIO[2]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_MASK 0x10000 + +// Configure drive strength for GPIO[2]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_MASK 0x20000 + +// Configure pull activation for GPIO[3]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[3]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_MASK 0x2000000 + +// Configure pull activation for GPIO[4]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_MASK 0x1 + +// Configure drive strength for GPIO[4]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_MASK 0x2 + +// Configure pull activation for GPIO[5]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_MASK 0x100 + +// Configure drive strength for GPIO[5]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_MASK 0x200 + +// Configure pull activation for GPIO[6]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_MASK 0x10000 + +// Configure drive strength for GPIO[6]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_MASK 0x20000 + +// Configure pull activation for GPIO[7]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[7]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_MASK 0x2000000 + +// Configure pull activation for GPIO[8]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_MASK 0x1 + +// Configure drive strength for GPIO[8]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_MASK 0x2 + +// Configure pull activation for GPIO[9]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_MASK 0x100 + +// Configure drive strength for GPIO[9]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_MASK 0x200 + +// Configure pull activation for GPIO[10]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_MASK 0x10000 + +// Configure drive strength for GPIO[10]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_MASK 0x20000 + +// Configure pull activation for GPIO[11]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[11]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_MASK 0x2000000 + +// Configure pull activation for GPIO[12]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_MASK 0x1 + +// Configure drive strength for GPIO[12]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_MASK 0x2 + +// Configure pull activation for GPIO[13]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_MASK 0x100 + +// Configure drive strength for GPIO[13]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_MASK 0x200 + +// Configure pull activation for GPIO[14]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_MASK 0x10000 + +// Configure drive strength for GPIO[14]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_MASK 0x20000 + +// Configure pull activation for GPIO[15]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[15]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_MASK 0x2000000 + +// Configure pull activation for GPIO[16]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_MASK 0x1 + +// Configure drive strength for GPIO[16]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_MASK 0x2 + +// Configure pull activation for GPIO[17]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_MASK 0x100 + +// Configure drive strength for GPIO[17]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_MASK 0x200 + +// Configure pull activation for GPIO[18]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_MASK 0x10000 + +// Configure drive strength for GPIO[18]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_MASK 0x20000 + +// Configure pull activation for GPIO[19]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[19]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_MASK 0x2000000 + +// Configure pull activation for GPIO[20]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_MASK 0x1 + +// Configure drive strength for GPIO[20]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_MASK 0x2 + +// Configure pull activation for GPIO[21]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_MASK 0x100 + +// Configure drive strength for GPIO[21]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_MASK 0x200 + +// Configure pull activation for GPIO[22]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_MASK 0x10000 + +// Configure drive strength for GPIO[22]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_MASK 0x20000 + +// Configure pull activation for GPIO[23]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[23]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_MASK 0x2000000 + +// Configure pull activation for GPIO[24]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_MASK 0x1 + +// Configure drive strength for GPIO[24]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_MASK 0x2 + +// Configure pull activation for GPIO[25]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_MASK 0x100 + +// Configure drive strength for GPIO[25]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_MASK 0x200 + +// Configure pull activation for GPIO[26]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_MASK 0x10000 + +// Configure drive strength for GPIO[26]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_MASK 0x20000 + +// Configure pull activation for GPIO[27]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[27]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_MASK 0x2000000 + +// Configure pull activation for GPIO[28]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_BIT 0 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_MASK 0x1 + +// Configure drive strength for GPIO[28]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_BIT 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_MASK 0x2 + +// Configure pull activation for GPIO[29]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_BIT 8 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_MASK 0x100 + +// Configure drive strength for GPIO[29]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_BIT 9 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_MASK 0x200 + +// Configure pull activation for GPIO[30]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_BIT 16 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_MASK 0x10000 + +// Configure drive strength for GPIO[30]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_BIT 17 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_MASK 0x20000 + +// Configure pull activation for GPIO[31]: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_BIT 24 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_MASK 0x1000000 + +// Configure drive strength for GPIO[31]: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_BIT 25 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_WIDTH 1 +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_MASK 0x2000000 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int dir :32; // Configure direction of the 32 GPIOs: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_paddir_t; + +typedef union { + struct { + unsigned int data_in :32; // Read value of the 32 GPIOs. + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padin_t; + +typedef union { + struct { + unsigned int data_out :32; // Write value to the 32 GPIOs. + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padout_t; + +typedef union { + struct { + unsigned int inten :32; // Configure interrupt mode for the 32 GPIOs: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_inten_t; + +typedef union { + struct { + unsigned int inttype0 :32; // Configure interrupt condition for the GPIO[15:0]: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_inttype0_t; + +typedef union { + struct { + unsigned int inttype1 :32; // Configure interrupt condition for the GPIO[31:16]: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_inttype1_t; + +typedef union { + struct { + unsigned int intstatus :32; // Interrupt status flags for the 32 GPIOs. - bit[i]=1 when interrupt received on GPIO[i] Register is cleared when read. GPIO interrupt line is also cleared when this register is red. + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_intstatus_t; + +typedef union { + struct { + unsigned int gpioen :32; // Configure clock enable for the 32 GPIOs: - bit[i]=1'b0: disable mode for GPIO[i] - bit[i]=1'b1: enable mode for GPIO[i] GPIOs are gathered by groups of 4. The clock-gating of one group is done only if all 4 GPIOs are disabled. + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_gpioen_t; + +typedef union { + struct { + unsigned int padcfg0_gpio0_pe:1 ; // Configure pull activation for GPIO[0]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg0_gpio0_ds:1 ; // Configure drive strength for GPIO[0]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg0_gpio1_pe:1 ; // Configure pull activation for GPIO[1]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg0_gpio1_ds:1 ; // Configure drive strength for GPIO[1]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg0_gpio2_pe:1 ; // Configure pull activation for GPIO[2]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg0_gpio2_ds:1 ; // Configure drive strength for GPIO[2]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg0_gpio3_pe:1 ; // Configure pull activation for GPIO[3]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg0_gpio3_ds:1 ; // Configure drive strength for GPIO[3]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg0_t; + +typedef union { + struct { + unsigned int padcfg1_gpio4_pe:1 ; // Configure pull activation for GPIO[4]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg1_gpio4_ds:1 ; // Configure drive strength for GPIO[4]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg1_gpio5_pe:1 ; // Configure pull activation for GPIO[5]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg1_gpio5_ds:1 ; // Configure drive strength for GPIO[5]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg1_gpio6_pe:1 ; // Configure pull activation for GPIO[6]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg1_gpio6_ds:1 ; // Configure drive strength for GPIO[6]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg1_gpio7_pe:1 ; // Configure pull activation for GPIO[7]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg1_gpio7_ds:1 ; // Configure drive strength for GPIO[7]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg1_t; + +typedef union { + struct { + unsigned int padcfg2_gpio8_pe:1 ; // Configure pull activation for GPIO[8]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg2_gpio8_ds:1 ; // Configure drive strength for GPIO[8]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg2_gpio9_pe:1 ; // Configure pull activation for GPIO[9]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg2_gpio9_ds:1 ; // Configure drive strength for GPIO[9]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg2_gpio10_pe:1 ; // Configure pull activation for GPIO[10]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg2_gpio10_ds:1 ; // Configure drive strength for GPIO[10]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg2_gpio11_pe:1 ; // Configure pull activation for GPIO[11]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg2_gpio11_ds:1 ; // Configure drive strength for GPIO[11]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg2_t; + +typedef union { + struct { + unsigned int padcfg3_gpio12_pe:1 ; // Configure pull activation for GPIO[12]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg3_gpio12_ds:1 ; // Configure drive strength for GPIO[12]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg3_gpio13_pe:1 ; // Configure pull activation for GPIO[13]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg3_gpio13_ds:1 ; // Configure drive strength for GPIO[13]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg3_gpio14_pe:1 ; // Configure pull activation for GPIO[14]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg3_gpio14_ds:1 ; // Configure drive strength for GPIO[14]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg3_gpio15_pe:1 ; // Configure pull activation for GPIO[15]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg3_gpio15_ds:1 ; // Configure drive strength for GPIO[15]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg3_t; + +typedef union { + struct { + unsigned int padcfg4_gpio16_pe:1 ; // Configure pull activation for GPIO[16]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg4_gpio16_ds:1 ; // Configure drive strength for GPIO[16]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg4_gpio17_pe:1 ; // Configure pull activation for GPIO[17]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg4_gpio17_ds:1 ; // Configure drive strength for GPIO[17]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg4_gpio18_pe:1 ; // Configure pull activation for GPIO[18]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg4_gpio18_ds:1 ; // Configure drive strength for GPIO[18]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg4_gpio19_pe:1 ; // Configure pull activation for GPIO[19]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg4_gpio19_ds:1 ; // Configure drive strength for GPIO[19]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg4_t; + +typedef union { + struct { + unsigned int padcfg5_gpio20_pe:1 ; // Configure pull activation for GPIO[20]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg5_gpio20_ds:1 ; // Configure drive strength for GPIO[20]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg5_gpio21_pe:1 ; // Configure pull activation for GPIO[21]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg5_gpio21_ds:1 ; // Configure drive strength for GPIO[21]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg5_gpio22_pe:1 ; // Configure pull activation for GPIO[22]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg5_gpio22_ds:1 ; // Configure drive strength for GPIO[22]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg5_gpio23_pe:1 ; // Configure pull activation for GPIO[23]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg5_gpio23_ds:1 ; // Configure drive strength for GPIO[23]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg5_t; + +typedef union { + struct { + unsigned int padcfg6_gpio24_pe:1 ; // Configure pull activation for GPIO[24]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg6_gpio24_ds:1 ; // Configure drive strength for GPIO[24]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg6_gpio25_pe:1 ; // Configure pull activation for GPIO[25]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg6_gpio25_ds:1 ; // Configure drive strength for GPIO[25]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg6_gpio26_pe:1 ; // Configure pull activation for GPIO[26]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg6_gpio26_ds:1 ; // Configure drive strength for GPIO[26]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg6_gpio27_pe:1 ; // Configure pull activation for GPIO[27]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg6_gpio27_ds:1 ; // Configure drive strength for GPIO[27]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg6_t; + +typedef union { + struct { + unsigned int padcfg7_gpio28_pe:1 ; // Configure pull activation for GPIO[28]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg7_gpio28_ds:1 ; // Configure drive strength for GPIO[28]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding0:6 ; + unsigned int padcfg7_gpio29_pe:1 ; // Configure pull activation for GPIO[29]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg7_gpio29_ds:1 ; // Configure drive strength for GPIO[29]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding1:6 ; + unsigned int padcfg7_gpio30_pe:1 ; // Configure pull activation for GPIO[30]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg7_gpio30_ds:1 ; // Configure drive strength for GPIO[30]: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int padding2:6 ; + unsigned int padcfg7_gpio31_pe:1 ; // Configure pull activation for GPIO[31]: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int padcfg7_gpio31_ds:1 ; // Configure drive strength for GPIO[31]: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_apbgpio_padcfg7_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_gpio_apbgpio_paddir : public vp::reg_32 +{ +public: + inline void dir_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADDIR_DIR_BIT, GPIO_APBGPIO_PADDIR_DIR_WIDTH); } + inline uint32_t dir_get() { return this->get_field(GPIO_APBGPIO_PADDIR_DIR_BIT, GPIO_APBGPIO_PADDIR_DIR_WIDTH); } +}; + +class vp_gpio_apbgpio_padin : public vp::reg_32 +{ +public: + inline void data_in_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADIN_DATA_IN_BIT, GPIO_APBGPIO_PADIN_DATA_IN_WIDTH); } + inline uint32_t data_in_get() { return this->get_field(GPIO_APBGPIO_PADIN_DATA_IN_BIT, GPIO_APBGPIO_PADIN_DATA_IN_WIDTH); } +}; + +class vp_gpio_apbgpio_padout : public vp::reg_32 +{ +public: + inline void data_out_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADOUT_DATA_OUT_BIT, GPIO_APBGPIO_PADOUT_DATA_OUT_WIDTH); } + inline uint32_t data_out_get() { return this->get_field(GPIO_APBGPIO_PADOUT_DATA_OUT_BIT, GPIO_APBGPIO_PADOUT_DATA_OUT_WIDTH); } +}; + +class vp_gpio_apbgpio_inten : public vp::reg_32 +{ +public: + inline void inten_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_INTEN_INTEN_BIT, GPIO_APBGPIO_INTEN_INTEN_WIDTH); } + inline uint32_t inten_get() { return this->get_field(GPIO_APBGPIO_INTEN_INTEN_BIT, GPIO_APBGPIO_INTEN_INTEN_WIDTH); } +}; + +class vp_gpio_apbgpio_inttype0 : public vp::reg_32 +{ +public: + inline void inttype0_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_INTTYPE0_INTTYPE0_BIT, GPIO_APBGPIO_INTTYPE0_INTTYPE0_WIDTH); } + inline uint32_t inttype0_get() { return this->get_field(GPIO_APBGPIO_INTTYPE0_INTTYPE0_BIT, GPIO_APBGPIO_INTTYPE0_INTTYPE0_WIDTH); } +}; + +class vp_gpio_apbgpio_inttype1 : public vp::reg_32 +{ +public: + inline void inttype1_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_INTTYPE1_INTTYPE1_BIT, GPIO_APBGPIO_INTTYPE1_INTTYPE1_WIDTH); } + inline uint32_t inttype1_get() { return this->get_field(GPIO_APBGPIO_INTTYPE1_INTTYPE1_BIT, GPIO_APBGPIO_INTTYPE1_INTTYPE1_WIDTH); } +}; + +class vp_gpio_apbgpio_intstatus : public vp::reg_32 +{ +public: + inline void intstatus_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_INTSTATUS_INTSTATUS_BIT, GPIO_APBGPIO_INTSTATUS_INTSTATUS_WIDTH); } + inline uint32_t intstatus_get() { return this->get_field(GPIO_APBGPIO_INTSTATUS_INTSTATUS_BIT, GPIO_APBGPIO_INTSTATUS_INTSTATUS_WIDTH); } +}; + +class vp_gpio_apbgpio_gpioen : public vp::reg_32 +{ +public: + inline void gpioen_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_GPIOEN_GPIOEN_BIT, GPIO_APBGPIO_GPIOEN_GPIOEN_WIDTH); } + inline uint32_t gpioen_get() { return this->get_field(GPIO_APBGPIO_GPIOEN_GPIOEN_BIT, GPIO_APBGPIO_GPIOEN_GPIOEN_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg0 : public vp::reg_32 +{ +public: + inline void padcfg0_gpio0_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_WIDTH); } + inline uint32_t padcfg0_gpio0_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_WIDTH); } + inline void padcfg0_gpio0_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_WIDTH); } + inline uint32_t padcfg0_gpio0_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_WIDTH); } + inline void padcfg0_gpio1_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_WIDTH); } + inline uint32_t padcfg0_gpio1_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_WIDTH); } + inline void padcfg0_gpio1_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_WIDTH); } + inline uint32_t padcfg0_gpio1_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_WIDTH); } + inline void padcfg0_gpio2_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_WIDTH); } + inline uint32_t padcfg0_gpio2_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_WIDTH); } + inline void padcfg0_gpio2_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_WIDTH); } + inline uint32_t padcfg0_gpio2_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_WIDTH); } + inline void padcfg0_gpio3_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_WIDTH); } + inline uint32_t padcfg0_gpio3_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_WIDTH); } + inline void padcfg0_gpio3_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_WIDTH); } + inline uint32_t padcfg0_gpio3_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_BIT, GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg1 : public vp::reg_32 +{ +public: + inline void padcfg1_gpio4_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_WIDTH); } + inline uint32_t padcfg1_gpio4_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_WIDTH); } + inline void padcfg1_gpio4_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_WIDTH); } + inline uint32_t padcfg1_gpio4_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_WIDTH); } + inline void padcfg1_gpio5_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_WIDTH); } + inline uint32_t padcfg1_gpio5_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_WIDTH); } + inline void padcfg1_gpio5_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_WIDTH); } + inline uint32_t padcfg1_gpio5_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_WIDTH); } + inline void padcfg1_gpio6_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_WIDTH); } + inline uint32_t padcfg1_gpio6_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_WIDTH); } + inline void padcfg1_gpio6_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_WIDTH); } + inline uint32_t padcfg1_gpio6_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_WIDTH); } + inline void padcfg1_gpio7_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_WIDTH); } + inline uint32_t padcfg1_gpio7_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_WIDTH); } + inline void padcfg1_gpio7_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_WIDTH); } + inline uint32_t padcfg1_gpio7_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_BIT, GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg2 : public vp::reg_32 +{ +public: + inline void padcfg2_gpio8_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_WIDTH); } + inline uint32_t padcfg2_gpio8_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_WIDTH); } + inline void padcfg2_gpio8_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_WIDTH); } + inline uint32_t padcfg2_gpio8_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_WIDTH); } + inline void padcfg2_gpio9_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_WIDTH); } + inline uint32_t padcfg2_gpio9_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_WIDTH); } + inline void padcfg2_gpio9_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_WIDTH); } + inline uint32_t padcfg2_gpio9_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_WIDTH); } + inline void padcfg2_gpio10_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_WIDTH); } + inline uint32_t padcfg2_gpio10_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_WIDTH); } + inline void padcfg2_gpio10_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_WIDTH); } + inline uint32_t padcfg2_gpio10_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_WIDTH); } + inline void padcfg2_gpio11_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_WIDTH); } + inline uint32_t padcfg2_gpio11_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_WIDTH); } + inline void padcfg2_gpio11_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_WIDTH); } + inline uint32_t padcfg2_gpio11_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_BIT, GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg3 : public vp::reg_32 +{ +public: + inline void padcfg3_gpio12_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_WIDTH); } + inline uint32_t padcfg3_gpio12_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_WIDTH); } + inline void padcfg3_gpio12_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_WIDTH); } + inline uint32_t padcfg3_gpio12_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_WIDTH); } + inline void padcfg3_gpio13_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_WIDTH); } + inline uint32_t padcfg3_gpio13_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_WIDTH); } + inline void padcfg3_gpio13_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_WIDTH); } + inline uint32_t padcfg3_gpio13_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_WIDTH); } + inline void padcfg3_gpio14_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_WIDTH); } + inline uint32_t padcfg3_gpio14_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_WIDTH); } + inline void padcfg3_gpio14_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_WIDTH); } + inline uint32_t padcfg3_gpio14_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_WIDTH); } + inline void padcfg3_gpio15_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_WIDTH); } + inline uint32_t padcfg3_gpio15_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_WIDTH); } + inline void padcfg3_gpio15_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_WIDTH); } + inline uint32_t padcfg3_gpio15_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_BIT, GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg4 : public vp::reg_32 +{ +public: + inline void padcfg4_gpio16_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_WIDTH); } + inline uint32_t padcfg4_gpio16_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_WIDTH); } + inline void padcfg4_gpio16_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_WIDTH); } + inline uint32_t padcfg4_gpio16_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_WIDTH); } + inline void padcfg4_gpio17_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_WIDTH); } + inline uint32_t padcfg4_gpio17_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_WIDTH); } + inline void padcfg4_gpio17_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_WIDTH); } + inline uint32_t padcfg4_gpio17_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_WIDTH); } + inline void padcfg4_gpio18_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_WIDTH); } + inline uint32_t padcfg4_gpio18_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_WIDTH); } + inline void padcfg4_gpio18_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_WIDTH); } + inline uint32_t padcfg4_gpio18_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_WIDTH); } + inline void padcfg4_gpio19_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_WIDTH); } + inline uint32_t padcfg4_gpio19_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_WIDTH); } + inline void padcfg4_gpio19_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_WIDTH); } + inline uint32_t padcfg4_gpio19_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_BIT, GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg5 : public vp::reg_32 +{ +public: + inline void padcfg5_gpio20_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_WIDTH); } + inline uint32_t padcfg5_gpio20_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_WIDTH); } + inline void padcfg5_gpio20_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_WIDTH); } + inline uint32_t padcfg5_gpio20_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_WIDTH); } + inline void padcfg5_gpio21_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_WIDTH); } + inline uint32_t padcfg5_gpio21_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_WIDTH); } + inline void padcfg5_gpio21_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_WIDTH); } + inline uint32_t padcfg5_gpio21_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_WIDTH); } + inline void padcfg5_gpio22_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_WIDTH); } + inline uint32_t padcfg5_gpio22_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_WIDTH); } + inline void padcfg5_gpio22_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_WIDTH); } + inline uint32_t padcfg5_gpio22_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_WIDTH); } + inline void padcfg5_gpio23_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_WIDTH); } + inline uint32_t padcfg5_gpio23_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_WIDTH); } + inline void padcfg5_gpio23_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_WIDTH); } + inline uint32_t padcfg5_gpio23_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_BIT, GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg6 : public vp::reg_32 +{ +public: + inline void padcfg6_gpio24_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_WIDTH); } + inline uint32_t padcfg6_gpio24_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_WIDTH); } + inline void padcfg6_gpio24_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_WIDTH); } + inline uint32_t padcfg6_gpio24_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_WIDTH); } + inline void padcfg6_gpio25_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_WIDTH); } + inline uint32_t padcfg6_gpio25_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_WIDTH); } + inline void padcfg6_gpio25_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_WIDTH); } + inline uint32_t padcfg6_gpio25_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_WIDTH); } + inline void padcfg6_gpio26_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_WIDTH); } + inline uint32_t padcfg6_gpio26_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_WIDTH); } + inline void padcfg6_gpio26_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_WIDTH); } + inline uint32_t padcfg6_gpio26_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_WIDTH); } + inline void padcfg6_gpio27_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_WIDTH); } + inline uint32_t padcfg6_gpio27_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_WIDTH); } + inline void padcfg6_gpio27_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_WIDTH); } + inline uint32_t padcfg6_gpio27_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_BIT, GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_WIDTH); } +}; + +class vp_gpio_apbgpio_padcfg7 : public vp::reg_32 +{ +public: + inline void padcfg7_gpio28_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_WIDTH); } + inline uint32_t padcfg7_gpio28_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_WIDTH); } + inline void padcfg7_gpio28_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_WIDTH); } + inline uint32_t padcfg7_gpio28_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_WIDTH); } + inline void padcfg7_gpio29_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_WIDTH); } + inline uint32_t padcfg7_gpio29_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_WIDTH); } + inline void padcfg7_gpio29_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_WIDTH); } + inline uint32_t padcfg7_gpio29_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_WIDTH); } + inline void padcfg7_gpio30_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_WIDTH); } + inline uint32_t padcfg7_gpio30_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_WIDTH); } + inline void padcfg7_gpio30_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_WIDTH); } + inline uint32_t padcfg7_gpio30_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_WIDTH); } + inline void padcfg7_gpio31_pe_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_WIDTH); } + inline uint32_t padcfg7_gpio31_pe_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_WIDTH); } + inline void padcfg7_gpio31_ds_set(uint32_t value) { this->set_field(value, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_WIDTH); } + inline uint32_t padcfg7_gpio31_ds_get() { return this->get_field(GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_BIT, GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int apbgpio_paddir ; // GPIO pad direction configuration + unsigned int apbgpio_padin ; // GPIO pad input value + unsigned int apbgpio_padout ; // GPIO pad output value + unsigned int apbgpio_inten ; // GPIO pad interrupt enable configuration + unsigned int apbgpio_inttype0; // GPIO pad interrupt type bit 0 configuration + unsigned int apbgpio_inttype1; // GPIO pad interrupt type bit 1 configuration + unsigned int apbgpio_intstatus; // GPIO pad interrupt status + unsigned int apbgpio_gpioen ; // GPIO pad enable configuration + unsigned int apbgpio_padcfg0 ; // GPIO pad pin 0 to 3 configuration + unsigned int apbgpio_padcfg1 ; // GPIO pad pin 4 to 7 configuration + unsigned int apbgpio_padcfg2 ; // GPIO pad pin 8 to 11 configuration + unsigned int apbgpio_padcfg3 ; // GPIO pad pin 12 to 15 configuration + unsigned int apbgpio_padcfg4 ; // GPIO pad pin 16 to 19 configuration + unsigned int apbgpio_padcfg5 ; // GPIO pad pin 20 to 23 configuration + unsigned int apbgpio_padcfg6 ; // GPIO pad pin 24 to 27 configuration + unsigned int apbgpio_padcfg7 ; // GPIO pad pin 28 to 31 configuration +} __attribute__((packed)) gpio_gpio_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t gpio_apbgpio_paddir_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADDIR_OFFSET); } +static inline void gpio_apbgpio_paddir_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADDIR_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padin_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADIN_OFFSET); } +static inline void gpio_apbgpio_padin_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADIN_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padout_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADOUT_OFFSET); } +static inline void gpio_apbgpio_padout_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADOUT_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_inten_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_INTEN_OFFSET); } +static inline void gpio_apbgpio_inten_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_INTEN_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_inttype0_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_INTTYPE0_OFFSET); } +static inline void gpio_apbgpio_inttype0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_INTTYPE0_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_inttype1_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_INTTYPE1_OFFSET); } +static inline void gpio_apbgpio_inttype1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_INTTYPE1_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_intstatus_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_INTSTATUS_OFFSET); } +static inline void gpio_apbgpio_intstatus_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_INTSTATUS_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_gpioen_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_GPIOEN_OFFSET); } +static inline void gpio_apbgpio_gpioen_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_GPIOEN_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg0_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG0_OFFSET); } +static inline void gpio_apbgpio_padcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG0_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg1_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG1_OFFSET); } +static inline void gpio_apbgpio_padcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG1_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg2_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG2_OFFSET); } +static inline void gpio_apbgpio_padcfg2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG2_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg3_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG3_OFFSET); } +static inline void gpio_apbgpio_padcfg3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG3_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg4_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG4_OFFSET); } +static inline void gpio_apbgpio_padcfg4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG4_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg5_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG5_OFFSET); } +static inline void gpio_apbgpio_padcfg5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG5_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg6_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG6_OFFSET); } +static inline void gpio_apbgpio_padcfg6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG6_OFFSET, value); } + +static inline uint32_t gpio_apbgpio_padcfg7_get(uint32_t base) { return ARCHI_READ(base, GPIO_APBGPIO_PADCFG7_OFFSET); } +static inline void gpio_apbgpio_padcfg7_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_APBGPIO_PADCFG7_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define GPIO_APBGPIO_PADDIR_DIR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_PADDIR_DIR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_PADDIR_DIR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_PADDIR_DIR(val) ((val) << 0) + +#define GPIO_APBGPIO_PADIN_DATA_IN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_PADIN_DATA_IN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_PADIN_DATA_IN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_PADIN_DATA_IN(val) ((val) << 0) + +#define GPIO_APBGPIO_PADOUT_DATA_OUT_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_PADOUT_DATA_OUT_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_PADOUT_DATA_OUT_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_PADOUT_DATA_OUT(val) ((val) << 0) + +#define GPIO_APBGPIO_INTEN_INTEN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_INTEN_INTEN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_INTEN_INTEN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_INTEN_INTEN(val) ((val) << 0) + +#define GPIO_APBGPIO_INTTYPE0_INTTYPE0_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_INTTYPE0_INTTYPE0_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_INTTYPE0_INTTYPE0_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_INTTYPE0_INTTYPE0(val) ((val) << 0) + +#define GPIO_APBGPIO_INTTYPE1_INTTYPE1_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_INTTYPE1_INTTYPE1_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_INTTYPE1_INTTYPE1_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_INTTYPE1_INTTYPE1(val) ((val) << 0) + +#define GPIO_APBGPIO_INTSTATUS_INTSTATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_INTSTATUS_INTSTATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_INTSTATUS_INTSTATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_INTSTATUS_INTSTATUS(val) ((val) << 0) + +#define GPIO_APBGPIO_GPIOEN_GPIOEN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_APBGPIO_GPIOEN_GPIOEN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_APBGPIO_GPIOEN_GPIOEN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_APBGPIO_GPIOEN_GPIOEN(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO0_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO1_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO2_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG0_PADCFG0_GPIO3_DS(val) ((val) << 25) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO4_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO5_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO6_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG1_PADCFG1_GPIO7_DS(val) ((val) << 25) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO8_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO9_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO10_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG2_PADCFG2_GPIO11_DS(val) ((val) << 25) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO12_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO13_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO14_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG3_PADCFG3_GPIO15_DS(val) ((val) << 25) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO16_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO17_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO18_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG4_PADCFG4_GPIO19_DS(val) ((val) << 25) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO20_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO21_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO22_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG5_PADCFG5_GPIO23_DS(val) ((val) << 25) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO24_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO25_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO26_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG6_PADCFG6_GPIO27_DS(val) ((val) << 25) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_PE(val) ((val) << 0) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO28_DS(val) ((val) << 1) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_PE(val) ((val) << 8) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO29_DS(val) ((val) << 9) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_PE(val) ((val) << 16) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO30_DS(val) ((val) << 17) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_PE(val) ((val) << 24) + +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define GPIO_APBGPIO_PADCFG7_PADCFG7_GPIO31_DS(val) ((val) << 25) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/gpio/gpio_v3.h b/sw/pulp-sdk/archi/include/archi/gpio/gpio_v3.h new file mode 100644 index 0000000..54eebc2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/gpio/gpio_v3.h @@ -0,0 +1,992 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_GPIO_GPIO_V3_H__ +#define __INCLUDE_ARCHI_GPIO_GPIO_V3_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// GPIO pad direction configuration register. +#define GPIO_PADDIR_OFFSET 0x0 + +// GPIO enable register. +#define GPIO_GPIOEN_OFFSET 0x4 + +// GPIO pad input value register. +#define GPIO_PADIN_OFFSET 0x8 + +// GPIO pad output value register. +#define GPIO_PADOUT_OFFSET 0xc + +// GPIO pad output set register. +#define GPIO_PADOUTSET_OFFSET 0x10 + +// GPIO pad output clear register. +#define GPIO_PADOUTCLR_OFFSET 0x14 + +// GPIO pad interrupt enable configuration register. +#define GPIO_INTEN_OFFSET 0x18 + +// GPIO pad interrupt type gpio 0 to 15 register. +#define GPIO_INTTYPE0_OFFSET 0x1c + +// GPIO pad interrupt type gpio 16 to 31 register. +#define GPIO_INTTYPE1_OFFSET 0x20 + +// GPIO pad interrupt status register. +#define GPIO_INTSTATUS_OFFSET 0x24 + +// GPIO pad pin 0 to 7 configuration register. +#define GPIO_PADCFG0_OFFSET 0x28 + +// GPIO pad pin 8 to 15 configuration register. +#define GPIO_PADCFG1_OFFSET 0x2c + +// GPIO pad pin 16 to 23 configuration register. +#define GPIO_PADCFG2_OFFSET 0x30 + +// GPIO pad pin 24 to 31 configuration register. +#define GPIO_PADCFG3_OFFSET 0x34 + +// GPIO pad direction configuration register. +#define GPIO_PADDIR_32_63_OFFSET 0x38 + +// GPIO enable register. +#define GPIO_GPIOEN_32_63_OFFSET 0x3c + +// GPIO pad input value register. +#define GPIO_PADIN_32_63_OFFSET 0x40 + +// GPIO pad output value register. +#define GPIO_PADOUT_32_63_OFFSET 0x44 + +// GPIO pad output set register. +#define GPIO_PADOUTSET_32_63_OFFSET 0x48 + +// GPIO pad output clear register. +#define GPIO_PADOUTCLR_32_63_OFFSET 0x4c + +// GPIO pad interrupt enable configuration register. +#define GPIO_INTEN_32_63_OFFSET 0x50 + +// GPIO pad interrupt type gpio 32 to 47 register. +#define GPIO_INTTYPE_32_47_OFFSET 0x54 + +// GPIO pad interrupt type gpio 48 to 63 register. +#define GPIO_INTTYPE_48_63_OFFSET 0x58 + +// GPIO pad interrupt status register. +#define GPIO_INTSTATUS_32_63_OFFSET 0x5c + +// GPIO pad pin 32 to 39 configuration register. +#define GPIO_PADCFG_32_39_OFFSET 0x60 + +// GPIO pad pin 40 to 47 configuration register. +#define GPIO_PADCFG_40_47_OFFSET 0x64 + +// GPIO pad pin 48 to 55 configuration register. +#define GPIO_PADCFG_48_55_OFFSET 0x68 + +// GPIO pad pin 56 to 63 configuration register. +#define GPIO_PADCFG_56_63_OFFSET 0x6c + + + +// +// REGISTERS FIELDS +// + +// GPIO[31:0] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] (access: R/W) +#define GPIO_PADDIR_DIR_BIT 0 +#define GPIO_PADDIR_DIR_WIDTH 32 +#define GPIO_PADDIR_DIR_MASK 0xffffffff + +// GPIO[31:0] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. Clock must be enabled for a GPIO if it's direction is configured in input mode. (access: R/W) +#define GPIO_GPIOEN_GPIOEN_BIT 0 +#define GPIO_GPIOEN_GPIOEN_WIDTH 32 +#define GPIO_GPIOEN_GPIOEN_MASK 0xffffffff + +// GPIO[31:0] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. (access: R) +#define GPIO_PADIN_DATA_IN_BIT 0 +#define GPIO_PADIN_DATA_IN_WIDTH 32 +#define GPIO_PADIN_DATA_IN_MASK 0xffffffff + +// GPIO[31:0] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. (access: R/W) +#define GPIO_PADOUT_DATA_OUT_BIT 0 +#define GPIO_PADOUT_DATA_OUT_WIDTH 32 +#define GPIO_PADOUT_DATA_OUT_MASK 0xffffffff + +// GPIO[31:0] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 (access: W) +#define GPIO_PADOUTSET_DATA_SET_BIT 0 +#define GPIO_PADOUTSET_DATA_SET_WIDTH 32 +#define GPIO_PADOUTSET_DATA_SET_MASK 0xffffffff + +// GPIO[31:0] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] (access: W) +#define GPIO_PADOUTCLR_DATA_CLEAR_BIT 0 +#define GPIO_PADOUTCLR_DATA_CLEAR_WIDTH 32 +#define GPIO_PADOUTCLR_DATA_CLEAR_MASK 0xffffffff + +// GPIO[31:0] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] (access: R/W) +#define GPIO_INTEN_INTEN_BIT 0 +#define GPIO_INTEN_INTEN_WIDTH 32 +#define GPIO_INTEN_INTEN_MASK 0xffffffff + +// GPIO[15:0] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) +#define GPIO_INTTYPE0_INTTYPE0_BIT 0 +#define GPIO_INTTYPE0_INTTYPE0_WIDTH 32 +#define GPIO_INTTYPE0_INTTYPE0_MASK 0xffffffff + +// GPIO[31:16] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) +#define GPIO_INTTYPE1_INTTYPE1_BIT 0 +#define GPIO_INTTYPE1_INTTYPE1_WIDTH 32 +#define GPIO_INTTYPE1_INTTYPE1_MASK 0xffffffff + +// GPIO[31:0] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. (access: R) +#define GPIO_INTSTATUS_INTSTATUS_BIT 0 +#define GPIO_INTSTATUS_INTSTATUS_WIDTH 32 +#define GPIO_INTSTATUS_INTSTATUS_MASK 0xffffffff + +// GPIO[0] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_PADCFG0_GPIO0_CFG_BIT 0 +#define GPIO_PADCFG0_GPIO0_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO0_CFG_MASK 0xf + +// GPIO[0] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_PADCFG0_GPIO1_CFG_BIT 4 +#define GPIO_PADCFG0_GPIO1_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO1_CFG_MASK 0xf0 + +// GPIO[1] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_PADCFG0_GPIO2_CFG_BIT 8 +#define GPIO_PADCFG0_GPIO2_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO2_CFG_MASK 0xf00 + +// GPIO[1] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_PADCFG0_GPIO3_CFG_BIT 12 +#define GPIO_PADCFG0_GPIO3_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO3_CFG_MASK 0xf000 + +// GPIO[2] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_PADCFG0_GPIO4_CFG_BIT 16 +#define GPIO_PADCFG0_GPIO4_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO4_CFG_MASK 0xf0000 + +// GPIO[2] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_PADCFG0_GPIO5_CFG_BIT 20 +#define GPIO_PADCFG0_GPIO5_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO5_CFG_MASK 0xf00000 + +// GPIO[3] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_PADCFG0_GPIO6_CFG_BIT 24 +#define GPIO_PADCFG0_GPIO6_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO6_CFG_MASK 0xf000000 + +// GPIO[3] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_PADCFG0_GPIO7_CFG_BIT 28 +#define GPIO_PADCFG0_GPIO7_CFG_WIDTH 4 +#define GPIO_PADCFG0_GPIO7_CFG_MASK 0xf0000000 + +// GPIO[4] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) +#define GPIO_PADCFG1_GPIO4_PE_BIT 0 +#define GPIO_PADCFG1_GPIO4_PE_WIDTH 1 +#define GPIO_PADCFG1_GPIO4_PE_MASK 0x1 + +// GPIO[4] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) +#define GPIO_PADCFG1_GPIO4_DS_BIT 1 +#define GPIO_PADCFG1_GPIO4_DS_WIDTH 1 +#define GPIO_PADCFG1_GPIO4_DS_MASK 0x2 + +// GPIO[63:32] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] (access: R/W) +#define GPIO_PADDIR_32_63_DIR_BIT 0 +#define GPIO_PADDIR_32_63_DIR_WIDTH 32 +#define GPIO_PADDIR_32_63_DIR_MASK 0xffffffff + +// GPIO[63:32] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. Clock must be enabled for a GPIO if it's direction is configured in input mode. (access: R/W) +#define GPIO_GPIOEN_32_63_GPIOEN_BIT 0 +#define GPIO_GPIOEN_32_63_GPIOEN_WIDTH 32 +#define GPIO_GPIOEN_32_63_GPIOEN_MASK 0xffffffff + +// GPIO[63:32] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. (access: R) +#define GPIO_PADIN_32_63_DATA_IN_BIT 0 +#define GPIO_PADIN_32_63_DATA_IN_WIDTH 32 +#define GPIO_PADIN_32_63_DATA_IN_MASK 0xffffffff + +// GPIO[63:32] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. (access: R/W) +#define GPIO_PADOUT_32_63_DATA_OUT_BIT 0 +#define GPIO_PADOUT_32_63_DATA_OUT_WIDTH 32 +#define GPIO_PADOUT_32_63_DATA_OUT_MASK 0xffffffff + +// GPIO[63:32] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 (access: W) +#define GPIO_PADOUTSET_32_63_DATA_SET_BIT 0 +#define GPIO_PADOUTSET_32_63_DATA_SET_WIDTH 32 +#define GPIO_PADOUTSET_32_63_DATA_SET_MASK 0xffffffff + +// GPIO[63:32] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] (access: W) +#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_BIT 0 +#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_WIDTH 32 +#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_MASK 0xffffffff + +// GPIO[63:32] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] (access: R/W) +#define GPIO_INTEN_32_63_INTEN_BIT 0 +#define GPIO_INTEN_32_63_INTEN_WIDTH 32 +#define GPIO_INTEN_32_63_INTEN_MASK 0xffffffff + +// GPIO[47:32] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) +#define GPIO_INTTYPE_32_47_INTTYPE0_BIT 0 +#define GPIO_INTTYPE_32_47_INTTYPE0_WIDTH 32 +#define GPIO_INTTYPE_32_47_INTTYPE0_MASK 0xffffffff + +// GPIO[63:48] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) +#define GPIO_INTTYPE_48_63_INTTYPE1_BIT 0 +#define GPIO_INTTYPE_48_63_INTTYPE1_WIDTH 32 +#define GPIO_INTTYPE_48_63_INTTYPE1_MASK 0xffffffff + +// GPIO[63:32] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. (access: R) +#define GPIO_INTSTATUS_32_63_INTSTATUS_BIT 0 +#define GPIO_INTSTATUS_32_63_INTSTATUS_WIDTH 32 +#define GPIO_INTSTATUS_32_63_INTSTATUS_MASK 0xffffffff + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int dir :32; // GPIO[31:0] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_paddir_t; + +typedef union { + struct { + unsigned int gpioen :32; // GPIO[31:0] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. Clock must be enabled for a GPIO if it's direction is configured in input mode. + }; + unsigned int raw; +} __attribute__((packed)) gpio_gpioen_t; + +typedef union { + struct { + unsigned int data_in :32; // GPIO[31:0] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. + }; + unsigned int raw; +} __attribute__((packed)) gpio_padin_t; + +typedef union { + struct { + unsigned int data_out :32; // GPIO[31:0] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. + }; + unsigned int raw; +} __attribute__((packed)) gpio_padout_t; + +typedef union { + struct { + unsigned int data_set :32; // GPIO[31:0] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 + }; + unsigned int raw; +} __attribute__((packed)) gpio_padoutset_t; + +typedef union { + struct { + unsigned int data_clear :32; // GPIO[31:0] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_padoutclr_t; + +typedef union { + struct { + unsigned int inten :32; // GPIO[31:0] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_inten_t; + +typedef union { + struct { + unsigned int inttype0 :32; // GPIO[15:0] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU + }; + unsigned int raw; +} __attribute__((packed)) gpio_inttype0_t; + +typedef union { + struct { + unsigned int inttype1 :32; // GPIO[31:16] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU + }; + unsigned int raw; +} __attribute__((packed)) gpio_inttype1_t; + +typedef union { + struct { + unsigned int intstatus :32; // GPIO[31:0] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. + }; + unsigned int raw; +} __attribute__((packed)) gpio_intstatus_t; + +typedef union { + struct { + unsigned int gpio0_cfg :4 ; // GPIO[0] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int gpio1_cfg :4 ; // GPIO[0] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int gpio2_cfg :4 ; // GPIO[1] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int gpio3_cfg :4 ; // GPIO[1] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int gpio4_cfg :4 ; // GPIO[2] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int gpio5_cfg :4 ; // GPIO[2] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength + unsigned int gpio6_cfg :4 ; // GPIO[3] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int gpio7_cfg :4 ; // GPIO[3] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg0_t; + +typedef union { + struct { + unsigned int gpio4_pe :1 ; // GPIO[4] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled + unsigned int gpio4_ds :1 ; // GPIO[4] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg2_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg3_t; + +typedef union { + struct { + unsigned int dir :32; // GPIO[63:32] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_paddir_32_63_t; + +typedef union { + struct { + unsigned int gpioen :32; // GPIO[63:32] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. Clock must be enabled for a GPIO if it's direction is configured in input mode. + }; + unsigned int raw; +} __attribute__((packed)) gpio_gpioen_32_63_t; + +typedef union { + struct { + unsigned int data_in :32; // GPIO[63:32] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. + }; + unsigned int raw; +} __attribute__((packed)) gpio_padin_32_63_t; + +typedef union { + struct { + unsigned int data_out :32; // GPIO[63:32] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. + }; + unsigned int raw; +} __attribute__((packed)) gpio_padout_32_63_t; + +typedef union { + struct { + unsigned int data_set :32; // GPIO[63:32] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 + }; + unsigned int raw; +} __attribute__((packed)) gpio_padoutset_32_63_t; + +typedef union { + struct { + unsigned int data_clear :32; // GPIO[63:32] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_padoutclr_32_63_t; + +typedef union { + struct { + unsigned int inten :32; // GPIO[63:32] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] + }; + unsigned int raw; +} __attribute__((packed)) gpio_inten_32_63_t; + +typedef union { + struct { + unsigned int inttype0 :32; // GPIO[47:32] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU + }; + unsigned int raw; +} __attribute__((packed)) gpio_inttype_32_47_t; + +typedef union { + struct { + unsigned int inttype1 :32; // GPIO[63:48] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU + }; + unsigned int raw; +} __attribute__((packed)) gpio_inttype_48_63_t; + +typedef union { + struct { + unsigned int intstatus :32; // GPIO[63:32] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. + }; + unsigned int raw; +} __attribute__((packed)) gpio_intstatus_32_63_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg_32_39_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg_40_47_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg_48_55_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) gpio_padcfg_56_63_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_gpio_paddir : public vp::reg_32 +{ +public: + inline void dir_set(uint32_t value) { this->set_field(value, GPIO_PADDIR_DIR_BIT, GPIO_PADDIR_DIR_WIDTH); } + inline uint32_t dir_get() { return this->get_field(GPIO_PADDIR_DIR_BIT, GPIO_PADDIR_DIR_WIDTH); } +}; + +class vp_gpio_gpioen : public vp::reg_32 +{ +public: + inline void gpioen_set(uint32_t value) { this->set_field(value, GPIO_GPIOEN_GPIOEN_BIT, GPIO_GPIOEN_GPIOEN_WIDTH); } + inline uint32_t gpioen_get() { return this->get_field(GPIO_GPIOEN_GPIOEN_BIT, GPIO_GPIOEN_GPIOEN_WIDTH); } +}; + +class vp_gpio_padin : public vp::reg_32 +{ +public: + inline void data_in_set(uint32_t value) { this->set_field(value, GPIO_PADIN_DATA_IN_BIT, GPIO_PADIN_DATA_IN_WIDTH); } + inline uint32_t data_in_get() { return this->get_field(GPIO_PADIN_DATA_IN_BIT, GPIO_PADIN_DATA_IN_WIDTH); } +}; + +class vp_gpio_padout : public vp::reg_32 +{ +public: + inline void data_out_set(uint32_t value) { this->set_field(value, GPIO_PADOUT_DATA_OUT_BIT, GPIO_PADOUT_DATA_OUT_WIDTH); } + inline uint32_t data_out_get() { return this->get_field(GPIO_PADOUT_DATA_OUT_BIT, GPIO_PADOUT_DATA_OUT_WIDTH); } +}; + +class vp_gpio_padoutset : public vp::reg_32 +{ +public: + inline void data_set_set(uint32_t value) { this->set_field(value, GPIO_PADOUTSET_DATA_SET_BIT, GPIO_PADOUTSET_DATA_SET_WIDTH); } + inline uint32_t data_set_get() { return this->get_field(GPIO_PADOUTSET_DATA_SET_BIT, GPIO_PADOUTSET_DATA_SET_WIDTH); } +}; + +class vp_gpio_padoutclr : public vp::reg_32 +{ +public: + inline void data_clear_set(uint32_t value) { this->set_field(value, GPIO_PADOUTCLR_DATA_CLEAR_BIT, GPIO_PADOUTCLR_DATA_CLEAR_WIDTH); } + inline uint32_t data_clear_get() { return this->get_field(GPIO_PADOUTCLR_DATA_CLEAR_BIT, GPIO_PADOUTCLR_DATA_CLEAR_WIDTH); } +}; + +class vp_gpio_inten : public vp::reg_32 +{ +public: + inline void inten_set(uint32_t value) { this->set_field(value, GPIO_INTEN_INTEN_BIT, GPIO_INTEN_INTEN_WIDTH); } + inline uint32_t inten_get() { return this->get_field(GPIO_INTEN_INTEN_BIT, GPIO_INTEN_INTEN_WIDTH); } +}; + +class vp_gpio_inttype0 : public vp::reg_32 +{ +public: + inline void inttype0_set(uint32_t value) { this->set_field(value, GPIO_INTTYPE0_INTTYPE0_BIT, GPIO_INTTYPE0_INTTYPE0_WIDTH); } + inline uint32_t inttype0_get() { return this->get_field(GPIO_INTTYPE0_INTTYPE0_BIT, GPIO_INTTYPE0_INTTYPE0_WIDTH); } +}; + +class vp_gpio_inttype1 : public vp::reg_32 +{ +public: + inline void inttype1_set(uint32_t value) { this->set_field(value, GPIO_INTTYPE1_INTTYPE1_BIT, GPIO_INTTYPE1_INTTYPE1_WIDTH); } + inline uint32_t inttype1_get() { return this->get_field(GPIO_INTTYPE1_INTTYPE1_BIT, GPIO_INTTYPE1_INTTYPE1_WIDTH); } +}; + +class vp_gpio_intstatus : public vp::reg_32 +{ +public: + inline void intstatus_set(uint32_t value) { this->set_field(value, GPIO_INTSTATUS_INTSTATUS_BIT, GPIO_INTSTATUS_INTSTATUS_WIDTH); } + inline uint32_t intstatus_get() { return this->get_field(GPIO_INTSTATUS_INTSTATUS_BIT, GPIO_INTSTATUS_INTSTATUS_WIDTH); } +}; + +class vp_gpio_padcfg0 : public vp::reg_32 +{ +public: + inline void gpio0_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO0_CFG_BIT, GPIO_PADCFG0_GPIO0_CFG_WIDTH); } + inline uint32_t gpio0_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO0_CFG_BIT, GPIO_PADCFG0_GPIO0_CFG_WIDTH); } + inline void gpio1_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO1_CFG_BIT, GPIO_PADCFG0_GPIO1_CFG_WIDTH); } + inline uint32_t gpio1_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO1_CFG_BIT, GPIO_PADCFG0_GPIO1_CFG_WIDTH); } + inline void gpio2_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO2_CFG_BIT, GPIO_PADCFG0_GPIO2_CFG_WIDTH); } + inline uint32_t gpio2_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO2_CFG_BIT, GPIO_PADCFG0_GPIO2_CFG_WIDTH); } + inline void gpio3_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO3_CFG_BIT, GPIO_PADCFG0_GPIO3_CFG_WIDTH); } + inline uint32_t gpio3_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO3_CFG_BIT, GPIO_PADCFG0_GPIO3_CFG_WIDTH); } + inline void gpio4_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO4_CFG_BIT, GPIO_PADCFG0_GPIO4_CFG_WIDTH); } + inline uint32_t gpio4_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO4_CFG_BIT, GPIO_PADCFG0_GPIO4_CFG_WIDTH); } + inline void gpio5_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO5_CFG_BIT, GPIO_PADCFG0_GPIO5_CFG_WIDTH); } + inline uint32_t gpio5_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO5_CFG_BIT, GPIO_PADCFG0_GPIO5_CFG_WIDTH); } + inline void gpio6_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO6_CFG_BIT, GPIO_PADCFG0_GPIO6_CFG_WIDTH); } + inline uint32_t gpio6_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO6_CFG_BIT, GPIO_PADCFG0_GPIO6_CFG_WIDTH); } + inline void gpio7_cfg_set(uint32_t value) { this->set_field(value, GPIO_PADCFG0_GPIO7_CFG_BIT, GPIO_PADCFG0_GPIO7_CFG_WIDTH); } + inline uint32_t gpio7_cfg_get() { return this->get_field(GPIO_PADCFG0_GPIO7_CFG_BIT, GPIO_PADCFG0_GPIO7_CFG_WIDTH); } +}; + +class vp_gpio_padcfg1 : public vp::reg_32 +{ +public: + inline void gpio4_pe_set(uint32_t value) { this->set_field(value, GPIO_PADCFG1_GPIO4_PE_BIT, GPIO_PADCFG1_GPIO4_PE_WIDTH); } + inline uint32_t gpio4_pe_get() { return this->get_field(GPIO_PADCFG1_GPIO4_PE_BIT, GPIO_PADCFG1_GPIO4_PE_WIDTH); } + inline void gpio4_ds_set(uint32_t value) { this->set_field(value, GPIO_PADCFG1_GPIO4_DS_BIT, GPIO_PADCFG1_GPIO4_DS_WIDTH); } + inline uint32_t gpio4_ds_get() { return this->get_field(GPIO_PADCFG1_GPIO4_DS_BIT, GPIO_PADCFG1_GPIO4_DS_WIDTH); } +}; + +class vp_gpio_padcfg2 : public vp::reg_32 +{ +public: +}; + +class vp_gpio_padcfg3 : public vp::reg_32 +{ +public: +}; + +class vp_gpio_paddir_32_63 : public vp::reg_32 +{ +public: + inline void dir_set(uint32_t value) { this->set_field(value, GPIO_PADDIR_32_63_DIR_BIT, GPIO_PADDIR_32_63_DIR_WIDTH); } + inline uint32_t dir_get() { return this->get_field(GPIO_PADDIR_32_63_DIR_BIT, GPIO_PADDIR_32_63_DIR_WIDTH); } +}; + +class vp_gpio_gpioen_32_63 : public vp::reg_32 +{ +public: + inline void gpioen_set(uint32_t value) { this->set_field(value, GPIO_GPIOEN_32_63_GPIOEN_BIT, GPIO_GPIOEN_32_63_GPIOEN_WIDTH); } + inline uint32_t gpioen_get() { return this->get_field(GPIO_GPIOEN_32_63_GPIOEN_BIT, GPIO_GPIOEN_32_63_GPIOEN_WIDTH); } +}; + +class vp_gpio_padin_32_63 : public vp::reg_32 +{ +public: + inline void data_in_set(uint32_t value) { this->set_field(value, GPIO_PADIN_32_63_DATA_IN_BIT, GPIO_PADIN_32_63_DATA_IN_WIDTH); } + inline uint32_t data_in_get() { return this->get_field(GPIO_PADIN_32_63_DATA_IN_BIT, GPIO_PADIN_32_63_DATA_IN_WIDTH); } +}; + +class vp_gpio_padout_32_63 : public vp::reg_32 +{ +public: + inline void data_out_set(uint32_t value) { this->set_field(value, GPIO_PADOUT_32_63_DATA_OUT_BIT, GPIO_PADOUT_32_63_DATA_OUT_WIDTH); } + inline uint32_t data_out_get() { return this->get_field(GPIO_PADOUT_32_63_DATA_OUT_BIT, GPIO_PADOUT_32_63_DATA_OUT_WIDTH); } +}; + +class vp_gpio_padoutset_32_63 : public vp::reg_32 +{ +public: + inline void data_set_set(uint32_t value) { this->set_field(value, GPIO_PADOUTSET_32_63_DATA_SET_BIT, GPIO_PADOUTSET_32_63_DATA_SET_WIDTH); } + inline uint32_t data_set_get() { return this->get_field(GPIO_PADOUTSET_32_63_DATA_SET_BIT, GPIO_PADOUTSET_32_63_DATA_SET_WIDTH); } +}; + +class vp_gpio_padoutclr_32_63 : public vp::reg_32 +{ +public: + inline void data_clear_set(uint32_t value) { this->set_field(value, GPIO_PADOUTCLR_32_63_DATA_CLEAR_BIT, GPIO_PADOUTCLR_32_63_DATA_CLEAR_WIDTH); } + inline uint32_t data_clear_get() { return this->get_field(GPIO_PADOUTCLR_32_63_DATA_CLEAR_BIT, GPIO_PADOUTCLR_32_63_DATA_CLEAR_WIDTH); } +}; + +class vp_gpio_inten_32_63 : public vp::reg_32 +{ +public: + inline void inten_set(uint32_t value) { this->set_field(value, GPIO_INTEN_32_63_INTEN_BIT, GPIO_INTEN_32_63_INTEN_WIDTH); } + inline uint32_t inten_get() { return this->get_field(GPIO_INTEN_32_63_INTEN_BIT, GPIO_INTEN_32_63_INTEN_WIDTH); } +}; + +class vp_gpio_inttype_32_47 : public vp::reg_32 +{ +public: + inline void inttype0_set(uint32_t value) { this->set_field(value, GPIO_INTTYPE_32_47_INTTYPE0_BIT, GPIO_INTTYPE_32_47_INTTYPE0_WIDTH); } + inline uint32_t inttype0_get() { return this->get_field(GPIO_INTTYPE_32_47_INTTYPE0_BIT, GPIO_INTTYPE_32_47_INTTYPE0_WIDTH); } +}; + +class vp_gpio_inttype_48_63 : public vp::reg_32 +{ +public: + inline void inttype1_set(uint32_t value) { this->set_field(value, GPIO_INTTYPE_48_63_INTTYPE1_BIT, GPIO_INTTYPE_48_63_INTTYPE1_WIDTH); } + inline uint32_t inttype1_get() { return this->get_field(GPIO_INTTYPE_48_63_INTTYPE1_BIT, GPIO_INTTYPE_48_63_INTTYPE1_WIDTH); } +}; + +class vp_gpio_intstatus_32_63 : public vp::reg_32 +{ +public: + inline void intstatus_set(uint32_t value) { this->set_field(value, GPIO_INTSTATUS_32_63_INTSTATUS_BIT, GPIO_INTSTATUS_32_63_INTSTATUS_WIDTH); } + inline uint32_t intstatus_get() { return this->get_field(GPIO_INTSTATUS_32_63_INTSTATUS_BIT, GPIO_INTSTATUS_32_63_INTSTATUS_WIDTH); } +}; + +class vp_gpio_padcfg_32_39 : public vp::reg_32 +{ +public: +}; + +class vp_gpio_padcfg_40_47 : public vp::reg_32 +{ +public: +}; + +class vp_gpio_padcfg_48_55 : public vp::reg_32 +{ +public: +}; + +class vp_gpio_padcfg_56_63 : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int paddir ; // GPIO pad direction configuration register. + unsigned int gpioen ; // GPIO enable register. + unsigned int padin ; // GPIO pad input value register. + unsigned int padout ; // GPIO pad output value register. + unsigned int padoutset ; // GPIO pad output set register. + unsigned int padoutclr ; // GPIO pad output clear register. + unsigned int inten ; // GPIO pad interrupt enable configuration register. + unsigned int inttype0 ; // GPIO pad interrupt type gpio 0 to 15 register. + unsigned int inttype1 ; // GPIO pad interrupt type gpio 16 to 31 register. + unsigned int intstatus ; // GPIO pad interrupt status register. + unsigned int padcfg0 ; // GPIO pad pin 0 to 7 configuration register. + unsigned int padcfg1 ; // GPIO pad pin 8 to 15 configuration register. + unsigned int padcfg2 ; // GPIO pad pin 16 to 23 configuration register. + unsigned int padcfg3 ; // GPIO pad pin 24 to 31 configuration register. + unsigned int paddir_32_63 ; // GPIO pad direction configuration register. + unsigned int gpioen_32_63 ; // GPIO enable register. + unsigned int padin_32_63 ; // GPIO pad input value register. + unsigned int padout_32_63 ; // GPIO pad output value register. + unsigned int padoutset_32_63 ; // GPIO pad output set register. + unsigned int padoutclr_32_63 ; // GPIO pad output clear register. + unsigned int inten_32_63 ; // GPIO pad interrupt enable configuration register. + unsigned int inttype_32_47 ; // GPIO pad interrupt type gpio 32 to 47 register. + unsigned int inttype_48_63 ; // GPIO pad interrupt type gpio 48 to 63 register. + unsigned int intstatus_32_63 ; // GPIO pad interrupt status register. + unsigned int padcfg_32_39 ; // GPIO pad pin 32 to 39 configuration register. + unsigned int padcfg_40_47 ; // GPIO pad pin 40 to 47 configuration register. + unsigned int padcfg_48_55 ; // GPIO pad pin 48 to 55 configuration register. + unsigned int padcfg_56_63 ; // GPIO pad pin 56 to 63 configuration register. +} __attribute__((packed)) gpio_gpio_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t gpio_paddir_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADDIR_OFFSET); } +static inline void gpio_paddir_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADDIR_OFFSET, value); } + +static inline uint32_t gpio_gpioen_get(uint32_t base) { return ARCHI_READ(base, GPIO_GPIOEN_OFFSET); } +static inline void gpio_gpioen_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_GPIOEN_OFFSET, value); } + +static inline uint32_t gpio_padin_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADIN_OFFSET); } +static inline void gpio_padin_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADIN_OFFSET, value); } + +static inline uint32_t gpio_padout_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADOUT_OFFSET); } +static inline void gpio_padout_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADOUT_OFFSET, value); } + +static inline uint32_t gpio_padoutset_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADOUTSET_OFFSET); } +static inline void gpio_padoutset_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADOUTSET_OFFSET, value); } + +static inline uint32_t gpio_padoutclr_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADOUTCLR_OFFSET); } +static inline void gpio_padoutclr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADOUTCLR_OFFSET, value); } + +static inline uint32_t gpio_inten_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTEN_OFFSET); } +static inline void gpio_inten_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTEN_OFFSET, value); } + +static inline uint32_t gpio_inttype0_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTTYPE0_OFFSET); } +static inline void gpio_inttype0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTTYPE0_OFFSET, value); } + +static inline uint32_t gpio_inttype1_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTTYPE1_OFFSET); } +static inline void gpio_inttype1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTTYPE1_OFFSET, value); } + +static inline uint32_t gpio_intstatus_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTSTATUS_OFFSET); } +static inline void gpio_intstatus_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTSTATUS_OFFSET, value); } + +static inline uint32_t gpio_padcfg0_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG0_OFFSET); } +static inline void gpio_padcfg0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG0_OFFSET, value); } + +static inline uint32_t gpio_padcfg1_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG1_OFFSET); } +static inline void gpio_padcfg1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG1_OFFSET, value); } + +static inline uint32_t gpio_padcfg2_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG2_OFFSET); } +static inline void gpio_padcfg2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG2_OFFSET, value); } + +static inline uint32_t gpio_padcfg3_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG3_OFFSET); } +static inline void gpio_padcfg3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG3_OFFSET, value); } + +static inline uint32_t gpio_paddir_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADDIR_32_63_OFFSET); } +static inline void gpio_paddir_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADDIR_32_63_OFFSET, value); } + +static inline uint32_t gpio_gpioen_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_GPIOEN_32_63_OFFSET); } +static inline void gpio_gpioen_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_GPIOEN_32_63_OFFSET, value); } + +static inline uint32_t gpio_padin_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADIN_32_63_OFFSET); } +static inline void gpio_padin_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADIN_32_63_OFFSET, value); } + +static inline uint32_t gpio_padout_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADOUT_32_63_OFFSET); } +static inline void gpio_padout_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADOUT_32_63_OFFSET, value); } + +static inline uint32_t gpio_padoutset_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADOUTSET_32_63_OFFSET); } +static inline void gpio_padoutset_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADOUTSET_32_63_OFFSET, value); } + +static inline uint32_t gpio_padoutclr_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADOUTCLR_32_63_OFFSET); } +static inline void gpio_padoutclr_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADOUTCLR_32_63_OFFSET, value); } + +static inline uint32_t gpio_inten_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTEN_32_63_OFFSET); } +static inline void gpio_inten_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTEN_32_63_OFFSET, value); } + +static inline uint32_t gpio_inttype_32_47_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTTYPE_32_47_OFFSET); } +static inline void gpio_inttype_32_47_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTTYPE_32_47_OFFSET, value); } + +static inline uint32_t gpio_inttype_48_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTTYPE_48_63_OFFSET); } +static inline void gpio_inttype_48_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTTYPE_48_63_OFFSET, value); } + +static inline uint32_t gpio_intstatus_32_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_INTSTATUS_32_63_OFFSET); } +static inline void gpio_intstatus_32_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_INTSTATUS_32_63_OFFSET, value); } + +static inline uint32_t gpio_padcfg_32_39_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG_32_39_OFFSET); } +static inline void gpio_padcfg_32_39_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG_32_39_OFFSET, value); } + +static inline uint32_t gpio_padcfg_40_47_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG_40_47_OFFSET); } +static inline void gpio_padcfg_40_47_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG_40_47_OFFSET, value); } + +static inline uint32_t gpio_padcfg_48_55_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG_48_55_OFFSET); } +static inline void gpio_padcfg_48_55_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG_48_55_OFFSET, value); } + +static inline uint32_t gpio_padcfg_56_63_get(uint32_t base) { return ARCHI_READ(base, GPIO_PADCFG_56_63_OFFSET); } +static inline void gpio_padcfg_56_63_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, GPIO_PADCFG_56_63_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define GPIO_PADDIR_DIR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADDIR_DIR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADDIR_DIR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADDIR_DIR(val) ((val) << 0) + +#define GPIO_GPIOEN_GPIOEN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_GPIOEN_GPIOEN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_GPIOEN_GPIOEN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_GPIOEN_GPIOEN(val) ((val) << 0) + +#define GPIO_PADIN_DATA_IN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADIN_DATA_IN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADIN_DATA_IN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADIN_DATA_IN(val) ((val) << 0) + +#define GPIO_PADOUT_DATA_OUT_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADOUT_DATA_OUT_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADOUT_DATA_OUT_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADOUT_DATA_OUT(val) ((val) << 0) + +#define GPIO_PADOUTSET_DATA_SET_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADOUTSET_DATA_SET_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADOUTSET_DATA_SET_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADOUTSET_DATA_SET(val) ((val) << 0) + +#define GPIO_PADOUTCLR_DATA_CLEAR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADOUTCLR_DATA_CLEAR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADOUTCLR_DATA_CLEAR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADOUTCLR_DATA_CLEAR(val) ((val) << 0) + +#define GPIO_INTEN_INTEN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTEN_INTEN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTEN_INTEN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTEN_INTEN(val) ((val) << 0) + +#define GPIO_INTTYPE0_INTTYPE0_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTTYPE0_INTTYPE0_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTTYPE0_INTTYPE0_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTTYPE0_INTTYPE0(val) ((val) << 0) + +#define GPIO_INTTYPE1_INTTYPE1_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTTYPE1_INTTYPE1_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTTYPE1_INTTYPE1_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTTYPE1_INTTYPE1(val) ((val) << 0) + +#define GPIO_INTSTATUS_INTSTATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTSTATUS_INTSTATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTSTATUS_INTSTATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTSTATUS_INTSTATUS(val) ((val) << 0) + +#define GPIO_PADCFG0_GPIO0_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define GPIO_PADCFG0_GPIO0_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define GPIO_PADCFG0_GPIO0_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define GPIO_PADCFG0_GPIO0_CFG(val) ((val) << 0) + +#define GPIO_PADCFG0_GPIO1_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,4)) +#define GPIO_PADCFG0_GPIO1_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,4)) +#define GPIO_PADCFG0_GPIO1_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,4)) +#define GPIO_PADCFG0_GPIO1_CFG(val) ((val) << 4) + +#define GPIO_PADCFG0_GPIO2_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,8)) +#define GPIO_PADCFG0_GPIO2_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,8)) +#define GPIO_PADCFG0_GPIO2_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,8)) +#define GPIO_PADCFG0_GPIO2_CFG(val) ((val) << 8) + +#define GPIO_PADCFG0_GPIO3_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,12)) +#define GPIO_PADCFG0_GPIO3_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,12)) +#define GPIO_PADCFG0_GPIO3_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,12)) +#define GPIO_PADCFG0_GPIO3_CFG(val) ((val) << 12) + +#define GPIO_PADCFG0_GPIO4_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,16)) +#define GPIO_PADCFG0_GPIO4_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,16)) +#define GPIO_PADCFG0_GPIO4_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,16)) +#define GPIO_PADCFG0_GPIO4_CFG(val) ((val) << 16) + +#define GPIO_PADCFG0_GPIO5_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,20)) +#define GPIO_PADCFG0_GPIO5_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,20)) +#define GPIO_PADCFG0_GPIO5_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,20)) +#define GPIO_PADCFG0_GPIO5_CFG(val) ((val) << 20) + +#define GPIO_PADCFG0_GPIO6_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,24)) +#define GPIO_PADCFG0_GPIO6_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,24)) +#define GPIO_PADCFG0_GPIO6_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,24)) +#define GPIO_PADCFG0_GPIO6_CFG(val) ((val) << 24) + +#define GPIO_PADCFG0_GPIO7_CFG_GET(value) (ARCHI_BEXTRACTU((value),4,28)) +#define GPIO_PADCFG0_GPIO7_CFG_GETS(value) (ARCHI_BEXTRACT((value),4,28)) +#define GPIO_PADCFG0_GPIO7_CFG_SET(value,field) (ARCHI_BINSERT((value),(field),4,28)) +#define GPIO_PADCFG0_GPIO7_CFG(val) ((val) << 28) + +#define GPIO_PADCFG1_GPIO4_PE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define GPIO_PADCFG1_GPIO4_PE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define GPIO_PADCFG1_GPIO4_PE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define GPIO_PADCFG1_GPIO4_PE(val) ((val) << 0) + +#define GPIO_PADCFG1_GPIO4_DS_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define GPIO_PADCFG1_GPIO4_DS_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define GPIO_PADCFG1_GPIO4_DS_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define GPIO_PADCFG1_GPIO4_DS(val) ((val) << 1) + +#define GPIO_PADDIR_32_63_DIR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADDIR_32_63_DIR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADDIR_32_63_DIR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADDIR_32_63_DIR(val) ((val) << 0) + +#define GPIO_GPIOEN_32_63_GPIOEN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_GPIOEN_32_63_GPIOEN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_GPIOEN_32_63_GPIOEN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_GPIOEN_32_63_GPIOEN(val) ((val) << 0) + +#define GPIO_PADIN_32_63_DATA_IN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADIN_32_63_DATA_IN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADIN_32_63_DATA_IN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADIN_32_63_DATA_IN(val) ((val) << 0) + +#define GPIO_PADOUT_32_63_DATA_OUT_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADOUT_32_63_DATA_OUT_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADOUT_32_63_DATA_OUT_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADOUT_32_63_DATA_OUT(val) ((val) << 0) + +#define GPIO_PADOUTSET_32_63_DATA_SET_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADOUTSET_32_63_DATA_SET_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADOUTSET_32_63_DATA_SET_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADOUTSET_32_63_DATA_SET(val) ((val) << 0) + +#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_PADOUTCLR_32_63_DATA_CLEAR(val) ((val) << 0) + +#define GPIO_INTEN_32_63_INTEN_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTEN_32_63_INTEN_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTEN_32_63_INTEN_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTEN_32_63_INTEN(val) ((val) << 0) + +#define GPIO_INTTYPE_32_47_INTTYPE0_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTTYPE_32_47_INTTYPE0_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTTYPE_32_47_INTTYPE0_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTTYPE_32_47_INTTYPE0(val) ((val) << 0) + +#define GPIO_INTTYPE_48_63_INTTYPE1_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTTYPE_48_63_INTTYPE1_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTTYPE_48_63_INTTYPE1_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTTYPE_48_63_INTTYPE1(val) ((val) << 0) + +#define GPIO_INTSTATUS_32_63_INTSTATUS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define GPIO_INTSTATUS_32_63_INTSTATUS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define GPIO_INTSTATUS_32_63_INTSTATUS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define GPIO_INTSTATUS_32_63_INTSTATUS(val) ((val) << 0) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/gvsoc/gvsoc.h b/sw/pulp-sdk/archi/include/archi/gvsoc/gvsoc.h new file mode 100644 index 0000000..85a3dee --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/gvsoc/gvsoc.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_GVSOC_GVSOC_H__ +#define __ARCHI_GVSOC_GVSOC_H__ + +#define GV_SEMIHOSTING_FIRST_CUSTOM 0x1000 + +#define GV_SEMIHOSTING_VCD_CONFIGURE 0x1000 +#define GV_SEMIHOSTING_VCD_OPEN_TRACE 0x1001 +#define GV_SEMIHOSTING_VCD_CONF_TRACE 0x1002 +#define GV_SEMIHOSTING_VCD_DUMP_TRACE 0x1003 +#define GV_SEMIHOSTING_VCD_DUMP_TRACE_STRING 0x1004 + +#define GV_SEMIHOSTING_TRACE_OPEN 0x1010 +#define GV_SEMIHOSTING_TRACE_ENABLE 0x1011 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/hwce/hwce_v4.h b/sw/pulp-sdk/archi/include/archi/hwce/hwce_v4.h new file mode 100644 index 0000000..d1c79b7 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/hwce/hwce_v4.h @@ -0,0 +1,1806 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_HWCE_HWCE_V4_H__ +#define __INCLUDE_ARCHI_HWCE_HWCE_V4_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Trigger the execution of an offloaded job +#define HWCE_TRIGGER_OFFSET 0x0 + +// Acquire the lock to offload job +#define HWCE_ACQUIRE_OFFSET 0x4 + +// Number of concluded jobs since last read +#define HWCE_FINISHED_JOBS_OFFSET 0x8 + +// Status of the HWCE +#define HWCE_STATUS_OFFSET 0xc + +// ID of the currently running job +#define HWCE_RUNNING_JOB_OFFSET 0x10 + +// Reset HWCE to known idle state +#define HWCE_SOFT_CLEAR_OFFSET 0x14 + +// Generic configuration register 0 +#define HWCE_GEN_CONFIG0_OFFSET 0x20 + +// Generic configuration register 1 +#define HWCE_GEN_CONFIG1_OFFSET 0x24 + +// Total number of words to be read for yin and yout +#define HWCE_Y_TRANS_SIZE_OFFSET 0x40 + +// Line stride and length for yin and yout +#define HWCE_Y_LINE_STRIDE_LENGTH_OFFSET 0x44 + +// Feature (block) stride and length for yin and yout +#define HWCE_Y_FEAT_STRIDE_LENGTH_OFFSET 0x48 + +// Base address of yout[3] +#define HWCE_Y_OUT_3_BASE_ADDR_OFFSET 0x4c + +// Base address of yout[2] +#define HWCE_Y_OUT_2_BASE_ADDR_OFFSET 0x50 + +// Base address of yout[1] +#define HWCE_Y_OUT_1_BASE_ADDR_OFFSET 0x54 + +// Base address of yout[0] +#define HWCE_Y_OUT_0_BASE_ADDR_OFFSET 0x58 + +// Base address of yin[3] +#define HWCE_Y_IN_3_BASE_ADDR_OFFSET 0x5c + +// Base address of yin[2] +#define HWCE_Y_IN_2_BASE_ADDR_OFFSET 0x60 + +// Base address of yin[1] +#define HWCE_Y_IN_1_BASE_ADDR_OFFSET 0x64 + +// Base address of yin[0] +#define HWCE_Y_IN_0_BASE_ADDR_OFFSET 0x68 + +// Total number of words to be read for xin +#define HWCE_X_TRANS_SIZE_OFFSET 0x6c + +// Line stride and length for xin +#define HWCE_X_LINE_STRIDE_LENGTH_OFFSET 0x70 + +// Feature (block) stride and length for xin +#define HWCE_X_FEAT_STRIDE_LENGTH_OFFSET 0x74 + +// Base address of xin +#define HWCE_X_IN_BASE_ADDR_OFFSET 0x78 + +// Base address of W +#define HWCE_W_BASE_ADDR_OFFSET 0x7c + +// Job configuration register 0 +#define HWCE_JOB_CONFIG0_OFFSET 0x80 + +// Job configuration register 1 +#define HWCE_JOB_CONFIG1_OFFSET 0x84 + +// Total number of words to be read for yin and yout +#define HWCE_Y_TRANS_SIZE_CTX0_OFFSET 0x140 + +// Line stride and length for yin and yout +#define HWCE_Y_LINE_STRIDE_LENGTH_CTX0_OFFSET 0x144 + +// Feature (block) stride and length for yin and yout +#define HWCE_Y_FEAT_STRIDE_LENGTH_CTX0_OFFSET 0x148 + +// Base address of yout[3] +#define HWCE_Y_OUT_3_BASE_ADDR_CTX0_OFFSET 0x14c + +// Base address of yout[2] +#define HWCE_Y_OUT_2_BASE_ADDR_CTX0_OFFSET 0x150 + +// Base address of yout[1] +#define HWCE_Y_OUT_1_BASE_ADDR_CTX0_OFFSET 0x154 + +// Base address of yout[0] +#define HWCE_Y_OUT_0_BASE_ADDR_CTX0_OFFSET 0x158 + +// Base address of yin[3] +#define HWCE_Y_IN_3_BASE_ADDR_CTX0_OFFSET 0x15c + +// Base address of yin[2] +#define HWCE_Y_IN_2_BASE_ADDR_CTX0_OFFSET 0x160 + +// Base address of yin[1] +#define HWCE_Y_IN_1_BASE_ADDR_CTX0_OFFSET 0x164 + +// Base address of yin[0] +#define HWCE_Y_IN_0_BASE_ADDR_CTX0_OFFSET 0x168 + +// Total number of words to be read for xin +#define HWCE_X_TRANS_SIZE_CTX0_OFFSET 0x16c + +// Line stride and length for xin +#define HWCE_X_LINE_STRIDE_LENGTH_CTX0_OFFSET 0x170 + +// Feature (block) stride and length for xin +#define HWCE_X_FEAT_STRIDE_LENGTH_CTX0_OFFSET 0x174 + +// Base address of xin +#define HWCE_X_IN_BASE_ADDR_CTX0_OFFSET 0x178 + +// Base address of W +#define HWCE_W_BASE_ADDR_CTX0_OFFSET 0x17c + +// Job configuration register 0 +#define HWCE_JOB_CONFIG0_CTX0_OFFSET 0x180 + +// Job configuration register 1 +#define HWCE_JOB_CONFIG1_CTX0_OFFSET 0x184 + +// Total number of words to be read for yin and yout +#define HWCE_Y_TRANS_SIZE_CTX1_OFFSET 0x240 + +// Line stride and length for yin and yout +#define HWCE_Y_LINE_STRIDE_LENGTH_CTX1_OFFSET 0x244 + +// Feature (block) stride and length for yin and yout +#define HWCE_Y_FEAT_STRIDE_LENGTH_CTX1_OFFSET 0x248 + +// Base address of yout[3] +#define HWCE_Y_OUT_3_BASE_ADDR_CTX1_OFFSET 0x24c + +// Base address of yout[2] +#define HWCE_Y_OUT_2_BASE_ADDR_CTX1_OFFSET 0x250 + +// Base address of yout[1] +#define HWCE_Y_OUT_1_BASE_ADDR_CTX1_OFFSET 0x254 + +// Base address of yout[0] +#define HWCE_Y_OUT_0_BASE_ADDR_CTX1_OFFSET 0x258 + +// Base address of yin[3] +#define HWCE_Y_IN_3_BASE_ADDR_CTX1_OFFSET 0x25c + +// Base address of yin[2] +#define HWCE_Y_IN_2_BASE_ADDR_CTX1_OFFSET 0x260 + +// Base address of yin[1] +#define HWCE_Y_IN_1_BASE_ADDR_CTX1_OFFSET 0x264 + +// Base address of yin[0] +#define HWCE_Y_IN_0_BASE_ADDR_CTX1_OFFSET 0x268 + +// Total number of words to be read for xin +#define HWCE_X_TRANS_SIZE_CTX1_OFFSET 0x26c + +// Line stride and length for xin +#define HWCE_X_LINE_STRIDE_LENGTH_CTX1_OFFSET 0x270 + +// Feature (block) stride and length for xin +#define HWCE_X_FEAT_STRIDE_LENGTH_CTX1_OFFSET 0x274 + +// Base address of xin +#define HWCE_X_IN_BASE_ADDR_CTX1_OFFSET 0x278 + +// Base address of W +#define HWCE_W_BASE_ADDR_CTX1_OFFSET 0x27c + +// Job configuration register 0 +#define HWCE_JOB_CONFIG0_CTX1_OFFSET 0x280 + +// Job configuration register 1 +#define HWCE_JOB_CONFIG1_CTX1_OFFSET 0x284 + + + +// +// REGISTERS FIELDS +// + +// Write of any value will close the current offload phase by releasing the job offload lock and inserting the currently offloaded job in the control queue. (access: W) +#define HWCE_TRIGGER_ANY_BIT 0 +#define HWCE_TRIGGER_ANY_WIDTH 32 +#define HWCE_TRIGGER_ANY_MASK 0xffffffff + +// If ERR is 0 then the ID of the offloaded job. Otherwise, part of the error code (access: R) +#define HWCE_ACQUIRE_ID_ERR_BIT 0 +#define HWCE_ACQUIRE_ID_ERR_WIDTH 8 +#define HWCE_ACQUIRE_ID_ERR_MASK 0xff + +// An error code if one of the following conditions apply: 1. if the context copy is going on, it will answer 0xfffffffd (-3) 2. else, if the job offload lock has been established, it will answer 0xfffffffe (-2) 3. else, if the job queue is full, it will answer 0xffffffff (-1) (access: R) +#define HWCE_ACQUIRE_ERR_BIT 8 +#define HWCE_ACQUIRE_ERR_WIDTH 24 +#define HWCE_ACQUIRE_ERR_MASK 0xffffff00 + +// The number of jobs that the HWCE executed and finished since the last time the same FINISHED_JOBS register was accessed. A read to FINISHED_JOBS returns: - 0x0 if no job was completed since the last access - 0x1 if a single job was completed since the last access - 0x2 if two or more jobs were completed since the last access (access: R) +#define HWCE_FINISHED_JOBS_JOBS_BIT 0 +#define HWCE_FINISHED_JOBS_JOBS_WIDTH 32 +#define HWCE_FINISHED_JOBS_JOBS_MASK 0xffffffff + +// Status of the HWCE - 1'b0 Not running a job - 1'b1 Running a job (access: R) +#define HWCE_STATUS_ST_BIT 0 +#define HWCE_STATUS_ST_WIDTH 1 +#define HWCE_STATUS_ST_MASK 0x1 + +// ID of the currently running job (access: R) +#define HWCE_RUNNING_JOB_ID_BIT 0 +#define HWCE_RUNNING_JOB_ID_WIDTH 8 +#define HWCE_RUNNING_JOB_ID_MASK 0xff + +// A write of any value to this register will reset the HWCE to its idle state. (access: W) +#define HWCE_SOFT_CLEAR_ANY_BIT 0 +#define HWCE_SOFT_CLEAR_ANY_WIDTH 32 +#define HWCE_SOFT_CLEAR_ANY_MASK 0xffffffff + +// Fixed-point format. Pixels will be shifted to the right by QF bits in the normalization step after the sum-of-products stage. (access: R/W) +#define HWCE_GEN_CONFIG0_QF_BIT 0 +#define HWCE_GEN_CONFIG0_QF_WIDTH 6 +#define HWCE_GEN_CONFIG0_QF_MASK 0x3f + +// Operation type: - 1'b0 - Normal convolution - 1'b1 - Does not flip weights (i.e. implements a stencil instead of a mathematical convolution). (access: R/W) +#define HWCE_GEN_CONFIG0_NF_BIT 6 +#define HWCE_GEN_CONFIG0_NF_WIDTH 1 +#define HWCE_GEN_CONFIG0_NF_MASK 0x40 + +// No y_in mode: - 1'b0 - Normal operation - 1'b1 - Disable loading of y_in and add a constant set in the CONFIG2 register (access: R/W) +#define HWCE_GEN_CONFIG0_NY_BIT 7 +#define HWCE_GEN_CONFIG0_NY_WIDTH 1 +#define HWCE_GEN_CONFIG0_NY_MASK 0x80 + +// Set unsigned multiplication - 1'b0 - Consider multiplication results as signed fixed-point numbers. - 1'b1 - Consider multiplication results as unsigned fixed-point numbers. (access: R/W) +#define HWCE_GEN_CONFIG0_UNS_BIT 8 +#define HWCE_GEN_CONFIG0_UNS_WIDTH 1 +#define HWCE_GEN_CONFIG0_UNS_MASK 0x100 + +// Vector mode: - 2'b00 - mode is scalar (1 feat/cycle, 1x16-bit weights). - 2'b01 - mode is vectorial 2 (2 feat/cycle, 2x8-bit weights). - 2'b10 - mode is vectorial 4 (4 feat/cycle, 4x4-bit weights). (access: R/W) +#define HWCE_GEN_CONFIG0_VECT_BIT 9 +#define HWCE_GEN_CONFIG0_VECT_WIDTH 2 +#define HWCE_GEN_CONFIG0_VECT_MASK 0x600 + +// Convolution mode: - 2'b00 - mode is 5x5. - 2'b01 - mode is 3x3. - 2'b10 - mode is 4x7. (access: R/W) +#define HWCE_GEN_CONFIG0_CONV_BIT 11 +#define HWCE_GEN_CONFIG0_CONV_WIDTH 2 +#define HWCE_GEN_CONFIG0_CONV_MASK 0x1800 + +// No job copy: - 1'b0 - do job copy - 1'b1 - don't do job copy (access: R/W) +#define HWCE_GEN_CONFIG0_NCP_BIT 13 +#define HWCE_GEN_CONFIG0_NCP_WIDTH 1 +#define HWCE_GEN_CONFIG0_NCP_MASK 0x2000 + +// Stride between one FILTER_SIZExFILTER_SIZE filter and the next. (access: R/W) +#define HWCE_GEN_CONFIG0_WSTRIDE_BIT 16 +#define HWCE_GEN_CONFIG0_WSTRIDE_WIDTH 16 +#define HWCE_GEN_CONFIG0_WSTRIDE_MASK 0xffff0000 + +// Shift input pixels to the left by this number of positions when PIXMODE is not 16bit. (access: R/W) +#define HWCE_GEN_CONFIG1_PIXSHIFTL_BIT 0 +#define HWCE_GEN_CONFIG1_PIXSHIFTL_WIDTH 5 +#define HWCE_GEN_CONFIG1_PIXSHIFTL_MASK 0x1f + +// Input pixel size - 2'b00 16bit - 2'b01 - 8bit - 2'b10 - 4bit - 2'b11 16bit bis (access: R/W) +#define HWCE_GEN_CONFIG1_PIXMODE_BIT 8 +#define HWCE_GEN_CONFIG1_PIXMODE_WIDTH 2 +#define HWCE_GEN_CONFIG1_PIXMODE_MASK 0x300 + +// Shift output pixels to the right by this number of positions when PIXMODE is not 16bit. (access: R/W) +#define HWCE_GEN_CONFIG1_PIXSHIFTR_BIT 16 +#define HWCE_GEN_CONFIG1_PIXSHIFTR_WIDTH 5 +#define HWCE_GEN_CONFIG1_PIXSHIFTR_MASK 0x1f0000 + +// Contains the total number of words (i.e. double 16bit pixels, quad 8bit pixels, etc.) to be read / written by the streaming source and sink interfaces for yin and yout streams. (access: R/W) +#define HWCE_Y_TRANS_SIZE_SIZE_BIT 0 +#define HWCE_Y_TRANS_SIZE_SIZE_WIDTH 32 +#define HWCE_Y_TRANS_SIZE_SIZE_MASK 0xffffffff + +// Length of a line in number of words (access: R/W) +#define HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_BIT 0 +#define HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_WIDTH 16 +#define HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_MASK 0xffff + +// Distance in bytes between two consecutive lines. (access: R/W) +#define HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_BIT 16 +#define HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_WIDTH 16 +#define HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_MASK 0xffff0000 + +// Length of a line in number of words (access: R/W) +#define HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_BIT 0 +#define HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_WIDTH 16 +#define HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_MASK 0xffff + +// Distance in bytes between two consecutive lines. (access: R/W) +#define HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_BIT 16 +#define HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_WIDTH 16 +#define HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_MASK 0xffff0000 + +// Pointer into cluster L1 memory (4x4 bit mode) (access: R/W) +#define HWCE_Y_OUT_3_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_OUT_3_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_OUT_3_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (4x4 bit mode) (access: R/W) +#define HWCE_Y_OUT_2_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_OUT_2_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_OUT_2_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (4x4 bit and 2x8 bit modes) (access: R/W) +#define HWCE_Y_OUT_1_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_OUT_1_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_OUT_1_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (4x4 bit, 2x8 bit and 1x16 bit modes) (access: R/W) +#define HWCE_Y_OUT_0_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_OUT_0_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_OUT_0_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (4x4 bit mode) (access: R/W) +#define HWCE_Y_IN_3_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_IN_3_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_IN_3_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (4x4 bit mode) (access: R/W) +#define HWCE_Y_IN_2_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_IN_2_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_IN_2_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (4x4 bit and 2x8 bit modes) (access: R/W) +#define HWCE_Y_IN_1_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_IN_1_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_IN_1_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (4x4 bit, 2x8 bit and 1x16 bit modes) (access: R/W) +#define HWCE_Y_IN_0_BASE_ADDR_ADDR_BIT 0 +#define HWCE_Y_IN_0_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_Y_IN_0_BASE_ADDR_ADDR_MASK 0xffffffff + +// Contains the total number of words (i.e. double 16bit pixels, quad 8bit pixels, etc.) to be read / written by the streaming source interface for the xin stream. (access: R/W) +#define HWCE_X_TRANS_SIZE_SIZE_BIT 0 +#define HWCE_X_TRANS_SIZE_SIZE_WIDTH 32 +#define HWCE_X_TRANS_SIZE_SIZE_MASK 0xffffffff + +// Length of a line in number of words (access: R/W) +#define HWCE_X_LINE_STRIDE_LENGTH_LENGTH_BIT 0 +#define HWCE_X_LINE_STRIDE_LENGTH_LENGTH_WIDTH 16 +#define HWCE_X_LINE_STRIDE_LENGTH_LENGTH_MASK 0xffff + +// Distance in bytes between two consecutive lines. (access: R/W) +#define HWCE_X_LINE_STRIDE_LENGTH_STRIDE_BIT 16 +#define HWCE_X_LINE_STRIDE_LENGTH_STRIDE_WIDTH 16 +#define HWCE_X_LINE_STRIDE_LENGTH_STRIDE_MASK 0xffff0000 + +// Length of a line in number of words (access: R/W) +#define HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_BIT 0 +#define HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_WIDTH 16 +#define HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_MASK 0xffff + +// Distance in bytes between two consecutive lines. (access: R/W) +#define HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_BIT 16 +#define HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_WIDTH 16 +#define HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_MASK 0xffff0000 + +// Pointer into cluster L1 memory (access: R/W) +#define HWCE_X_IN_BASE_ADDR_ADDR_BIT 0 +#define HWCE_X_IN_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_X_IN_BASE_ADDR_ADDR_MASK 0xffffffff + +// Pointer into cluster L1 memory (access: R/W) +#define HWCE_W_BASE_ADDR_ADDR_BIT 0 +#define HWCE_W_BASE_ADDR_ADDR_WIDTH 32 +#define HWCE_W_BASE_ADDR_ADDR_MASK 0xffffffff + +// Linebuffer virtual length. Set to the same number as X_LINE_LENGTH. Acceptable LBUFLEN values range between 2 and LINEBUF_LENGTH. (access: R/W) +#define HWCE_JOB_CONFIG0_LBUFLEN_BIT 0 +#define HWCE_JOB_CONFIG0_LBUFLEN_WIDTH 10 +#define HWCE_JOB_CONFIG0_LBUFLEN_MASK 0x3ff + +// Constant to sum instead of yin if the NY flag is active in the CONFIG1 register. (access: R/W) +#define HWCE_JOB_CONFIG0_NOYCONST_BIT 16 +#define HWCE_JOB_CONFIG0_NOYCONST_WIDTH 16 +#define HWCE_JOB_CONFIG0_NOYCONST_MASK 0xffff0000 + +// Vector mode mask. Defaults to 0x0, which means that all vectors are enabled. Can be used to disable unused vector routes when using approximate vector or 3x3 mode. The bits are reversed in order, so bit 3 indicates vector 0, bit 2 vector 1, etc. (access: R/W) +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_BIT 0 +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_WIDTH 4 +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_MASK 0xf + +// Output feature (OF) counter wrap parameter. If both WIF and WOF are 1'b0, the looping mechanism is disabled (access: R/W) +#define HWCE_JOB_CONFIG1_WOF_PARAM_BIT 8 +#define HWCE_JOB_CONFIG1_WOF_PARAM_WIDTH 6 +#define HWCE_JOB_CONFIG1_WOF_PARAM_MASK 0x3f00 + +// Input feature (IF) counter wrap parameter. If both WIF and WOF are 1'b0, the looping mechanism is disabled (access: R/W) +#define HWCE_JOB_CONFIG1_WIF_PARAM_BIT 16 +#define HWCE_JOB_CONFIG1_WIF_PARAM_WIDTH 6 +#define HWCE_JOB_CONFIG1_WIF_PARAM_MASK 0x3f0000 + +// Loop order: - 1'b0 - output features (OF) are the outer loop - 1'b1 - input features (IF) are the outer loop (access: R/W) +#define HWCE_JOB_CONFIG1_LO_BIT 24 +#define HWCE_JOB_CONFIG1_LO_WIDTH 1 +#define HWCE_JOB_CONFIG1_LO_MASK 0x1000000 + +// Looping mechanism: - 1'b0 - both counters work as inner loops - 1'b1 - outer loop feature address is updated only when the feature counter reaches the wrap parameter, inner loop feature address is updated when the counter is less than the wrap parameter and reset when it is reached (access: R/W) +#define HWCE_JOB_CONFIG1_LN_BIT 25 +#define HWCE_JOB_CONFIG1_LN_WIDTH 1 +#define HWCE_JOB_CONFIG1_LN_MASK 0x2000000 + + + +// +// REGISTERS STRUCTS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef union { + struct { + unsigned int any :32; // Write of any value will close the current offload phase by releasing the job offload lock and inserting the currently offloaded job in the control queue. + }; + unsigned int raw; +} __attribute__((packed)) hwce_trigger_t; + +typedef union { + struct { + unsigned int id_err :8 ; // If ERR is 0 then the ID of the offloaded job. Otherwise, part of the error code + unsigned int err :24; // An error code if one of the following conditions apply: 1. if the context copy is going on, it will answer 0xfffffffd (-3) 2. else, if the job offload lock has been established, it will answer 0xfffffffe (-2) 3. else, if the job queue is full, it will answer 0xffffffff (-1) + }; + unsigned int raw; +} __attribute__((packed)) hwce_acquire_t; + +typedef union { + struct { + unsigned int jobs :32; // The number of jobs that the HWCE executed and finished since the last time the same FINISHED_JOBS register was accessed. A read to FINISHED_JOBS returns: - 0x0 if no job was completed since the last access - 0x1 if a single job was completed since the last access - 0x2 if two or more jobs were completed since the last access + }; + unsigned int raw; +} __attribute__((packed)) hwce_finished_jobs_t; + +typedef union { + struct { + unsigned int st :1 ; // Status of the HWCE - 1'b0 Not running a job - 1'b1 Running a job + }; + unsigned int raw; +} __attribute__((packed)) hwce_status_t; + +typedef union { + struct { + unsigned int id :8 ; // ID of the currently running job + }; + unsigned int raw; +} __attribute__((packed)) hwce_running_job_t; + +typedef union { + struct { + unsigned int any :32; // A write of any value to this register will reset the HWCE to its idle state. + }; + unsigned int raw; +} __attribute__((packed)) hwce_soft_clear_t; + +typedef union { + struct { + unsigned int qf :6 ; // Fixed-point format. Pixels will be shifted to the right by QF bits in the normalization step after the sum-of-products stage. + unsigned int nf :1 ; // Operation type: - 1'b0 - Normal convolution - 1'b1 - Does not flip weights (i.e. implements a stencil instead of a mathematical convolution). + unsigned int ny :1 ; // No y_in mode: - 1'b0 - Normal operation - 1'b1 - Disable loading of y_in and add a constant set in the CONFIG2 register + unsigned int uns :1 ; // Set unsigned multiplication - 1'b0 - Consider multiplication results as signed fixed-point numbers. - 1'b1 - Consider multiplication results as unsigned fixed-point numbers. + unsigned int vect :2 ; // Vector mode: - 2'b00 - mode is scalar (1 feat/cycle, 1x16-bit weights). - 2'b01 - mode is vectorial 2 (2 feat/cycle, 2x8-bit weights). - 2'b10 - mode is vectorial 4 (4 feat/cycle, 4x4-bit weights). + unsigned int conv :2 ; // Convolution mode: - 2'b00 - mode is 5x5. - 2'b01 - mode is 3x3. - 2'b10 - mode is 4x7. + unsigned int ncp :1 ; // No job copy: - 1'b0 - do job copy - 1'b1 - don't do job copy + unsigned int padding0:2 ; + unsigned int wstride :16; // Stride between one FILTER_SIZExFILTER_SIZE filter and the next. + }; + unsigned int raw; +} __attribute__((packed)) hwce_gen_config0_t; + +typedef union { + struct { + unsigned int pixshiftl :5 ; // Shift input pixels to the left by this number of positions when PIXMODE is not 16bit. + unsigned int padding0:3 ; + unsigned int pixmode :2 ; // Input pixel size - 2'b00 16bit - 2'b01 - 8bit - 2'b10 - 4bit - 2'b11 16bit bis + unsigned int padding1:6 ; + unsigned int pixshiftr :5 ; // Shift output pixels to the right by this number of positions when PIXMODE is not 16bit. + }; + unsigned int raw; +} __attribute__((packed)) hwce_gen_config1_t; + +typedef union { + struct { + unsigned int size :32; // Contains the total number of words (i.e. double 16bit pixels, quad 8bit pixels, etc.) to be read / written by the streaming source and sink interfaces for yin and yout streams. + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_trans_size_t; + +typedef union { + struct { + unsigned int length :16; // Length of a line in number of words + unsigned int stride :16; // Distance in bytes between two consecutive lines. + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_line_stride_length_t; + +typedef union { + struct { + unsigned int length :16; // Length of a line in number of words + unsigned int stride :16; // Distance in bytes between two consecutive lines. + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_feat_stride_length_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit mode) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_3_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit mode) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_2_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit and 2x8 bit modes) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_1_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit, 2x8 bit and 1x16 bit modes) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_0_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit mode) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_3_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit mode) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_2_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit and 2x8 bit modes) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_1_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory (4x4 bit, 2x8 bit and 1x16 bit modes) + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_0_base_addr_t; + +typedef union { + struct { + unsigned int size :32; // Contains the total number of words (i.e. double 16bit pixels, quad 8bit pixels, etc.) to be read / written by the streaming source interface for the xin stream. + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_trans_size_t; + +typedef union { + struct { + unsigned int length :16; // Length of a line in number of words + unsigned int stride :16; // Distance in bytes between two consecutive lines. + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_line_stride_length_t; + +typedef union { + struct { + unsigned int length :16; // Length of a line in number of words + unsigned int stride :16; // Distance in bytes between two consecutive lines. + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_feat_stride_length_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_in_base_addr_t; + +typedef union { + struct { + unsigned int addr :32; // Pointer into cluster L1 memory + }; + unsigned int raw; +} __attribute__((packed)) hwce_w_base_addr_t; + +typedef union { + struct { + unsigned int lbuflen :10; // Linebuffer virtual length. Set to the same number as X_LINE_LENGTH. Acceptable LBUFLEN values range between 2 and LINEBUF_LENGTH. + unsigned int padding0:6 ; + unsigned int noyconst :16; // Constant to sum instead of yin if the NY flag is active in the CONFIG1 register. + }; + unsigned int raw; +} __attribute__((packed)) hwce_job_config0_t; + +typedef union { + struct { + unsigned int vect_disable_mask:4 ; // Vector mode mask. Defaults to 0x0, which means that all vectors are enabled. Can be used to disable unused vector routes when using approximate vector or 3x3 mode. The bits are reversed in order, so bit 3 indicates vector 0, bit 2 vector 1, etc. + unsigned int padding0:4 ; + unsigned int wof_param :6 ; // Output feature (OF) counter wrap parameter. If both WIF and WOF are 1'b0, the looping mechanism is disabled + unsigned int padding1:2 ; + unsigned int wif_param :6 ; // Input feature (IF) counter wrap parameter. If both WIF and WOF are 1'b0, the looping mechanism is disabled + unsigned int padding2:2 ; + unsigned int lo :1 ; // Loop order: - 1'b0 - output features (OF) are the outer loop - 1'b1 - input features (IF) are the outer loop + unsigned int ln :1 ; // Looping mechanism: - 1'b0 - both counters work as inner loops - 1'b1 - outer loop feature address is updated only when the feature counter reaches the wrap parameter, inner loop feature address is updated when the counter is less than the wrap parameter and reset when it is reached + }; + unsigned int raw; +} __attribute__((packed)) hwce_job_config1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_trans_size_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_line_stride_length_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_feat_stride_length_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_3_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_2_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_1_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_0_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_3_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_2_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_1_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_0_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_trans_size_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_line_stride_length_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_feat_stride_length_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_in_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_w_base_addr_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_job_config0_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_job_config1_ctx0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_trans_size_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_line_stride_length_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_feat_stride_length_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_3_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_2_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_1_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_out_0_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_3_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_2_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_1_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_y_in_0_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_trans_size_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_line_stride_length_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_feat_stride_length_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_x_in_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_w_base_addr_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_job_config0_ctx1_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hwce_job_config1_ctx1_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_hwce_trigger : public vp::reg_32 +{ +public: + inline void any_set(uint32_t value) { this->set_field(value, HWCE_TRIGGER_ANY_BIT, HWCE_TRIGGER_ANY_WIDTH); } + inline uint32_t any_get() { return this->get_field(HWCE_TRIGGER_ANY_BIT, HWCE_TRIGGER_ANY_WIDTH); } +}; + +class vp_hwce_acquire : public vp::reg_32 +{ +public: + inline void id_err_set(uint32_t value) { this->set_field(value, HWCE_ACQUIRE_ID_ERR_BIT, HWCE_ACQUIRE_ID_ERR_WIDTH); } + inline uint32_t id_err_get() { return this->get_field(HWCE_ACQUIRE_ID_ERR_BIT, HWCE_ACQUIRE_ID_ERR_WIDTH); } + inline void err_set(uint32_t value) { this->set_field(value, HWCE_ACQUIRE_ERR_BIT, HWCE_ACQUIRE_ERR_WIDTH); } + inline uint32_t err_get() { return this->get_field(HWCE_ACQUIRE_ERR_BIT, HWCE_ACQUIRE_ERR_WIDTH); } +}; + +class vp_hwce_finished_jobs : public vp::reg_32 +{ +public: + inline void jobs_set(uint32_t value) { this->set_field(value, HWCE_FINISHED_JOBS_JOBS_BIT, HWCE_FINISHED_JOBS_JOBS_WIDTH); } + inline uint32_t jobs_get() { return this->get_field(HWCE_FINISHED_JOBS_JOBS_BIT, HWCE_FINISHED_JOBS_JOBS_WIDTH); } +}; + +class vp_hwce_status : public vp::reg_32 +{ +public: + inline void st_set(uint32_t value) { this->set_field(value, HWCE_STATUS_ST_BIT, HWCE_STATUS_ST_WIDTH); } + inline uint32_t st_get() { return this->get_field(HWCE_STATUS_ST_BIT, HWCE_STATUS_ST_WIDTH); } +}; + +class vp_hwce_running_job : public vp::reg_32 +{ +public: + inline void id_set(uint32_t value) { this->set_field(value, HWCE_RUNNING_JOB_ID_BIT, HWCE_RUNNING_JOB_ID_WIDTH); } + inline uint32_t id_get() { return this->get_field(HWCE_RUNNING_JOB_ID_BIT, HWCE_RUNNING_JOB_ID_WIDTH); } +}; + +class vp_hwce_soft_clear : public vp::reg_32 +{ +public: + inline void any_set(uint32_t value) { this->set_field(value, HWCE_SOFT_CLEAR_ANY_BIT, HWCE_SOFT_CLEAR_ANY_WIDTH); } + inline uint32_t any_get() { return this->get_field(HWCE_SOFT_CLEAR_ANY_BIT, HWCE_SOFT_CLEAR_ANY_WIDTH); } +}; + +class vp_hwce_gen_config0 : public vp::reg_32 +{ +public: + inline void qf_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_QF_BIT, HWCE_GEN_CONFIG0_QF_WIDTH); } + inline uint32_t qf_get() { return this->get_field(HWCE_GEN_CONFIG0_QF_BIT, HWCE_GEN_CONFIG0_QF_WIDTH); } + inline void nf_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_NF_BIT, HWCE_GEN_CONFIG0_NF_WIDTH); } + inline uint32_t nf_get() { return this->get_field(HWCE_GEN_CONFIG0_NF_BIT, HWCE_GEN_CONFIG0_NF_WIDTH); } + inline void ny_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_NY_BIT, HWCE_GEN_CONFIG0_NY_WIDTH); } + inline uint32_t ny_get() { return this->get_field(HWCE_GEN_CONFIG0_NY_BIT, HWCE_GEN_CONFIG0_NY_WIDTH); } + inline void uns_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_UNS_BIT, HWCE_GEN_CONFIG0_UNS_WIDTH); } + inline uint32_t uns_get() { return this->get_field(HWCE_GEN_CONFIG0_UNS_BIT, HWCE_GEN_CONFIG0_UNS_WIDTH); } + inline void vect_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_VECT_BIT, HWCE_GEN_CONFIG0_VECT_WIDTH); } + inline uint32_t vect_get() { return this->get_field(HWCE_GEN_CONFIG0_VECT_BIT, HWCE_GEN_CONFIG0_VECT_WIDTH); } + inline void conv_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_CONV_BIT, HWCE_GEN_CONFIG0_CONV_WIDTH); } + inline uint32_t conv_get() { return this->get_field(HWCE_GEN_CONFIG0_CONV_BIT, HWCE_GEN_CONFIG0_CONV_WIDTH); } + inline void ncp_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_NCP_BIT, HWCE_GEN_CONFIG0_NCP_WIDTH); } + inline uint32_t ncp_get() { return this->get_field(HWCE_GEN_CONFIG0_NCP_BIT, HWCE_GEN_CONFIG0_NCP_WIDTH); } + inline void wstride_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG0_WSTRIDE_BIT, HWCE_GEN_CONFIG0_WSTRIDE_WIDTH); } + inline uint32_t wstride_get() { return this->get_field(HWCE_GEN_CONFIG0_WSTRIDE_BIT, HWCE_GEN_CONFIG0_WSTRIDE_WIDTH); } +}; + +class vp_hwce_gen_config1 : public vp::reg_32 +{ +public: + inline void pixshiftl_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG1_PIXSHIFTL_BIT, HWCE_GEN_CONFIG1_PIXSHIFTL_WIDTH); } + inline uint32_t pixshiftl_get() { return this->get_field(HWCE_GEN_CONFIG1_PIXSHIFTL_BIT, HWCE_GEN_CONFIG1_PIXSHIFTL_WIDTH); } + inline void pixmode_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG1_PIXMODE_BIT, HWCE_GEN_CONFIG1_PIXMODE_WIDTH); } + inline uint32_t pixmode_get() { return this->get_field(HWCE_GEN_CONFIG1_PIXMODE_BIT, HWCE_GEN_CONFIG1_PIXMODE_WIDTH); } + inline void pixshiftr_set(uint32_t value) { this->set_field(value, HWCE_GEN_CONFIG1_PIXSHIFTR_BIT, HWCE_GEN_CONFIG1_PIXSHIFTR_WIDTH); } + inline uint32_t pixshiftr_get() { return this->get_field(HWCE_GEN_CONFIG1_PIXSHIFTR_BIT, HWCE_GEN_CONFIG1_PIXSHIFTR_WIDTH); } +}; + +class vp_hwce_y_trans_size : public vp::reg_32 +{ +public: + inline void size_set(uint32_t value) { this->set_field(value, HWCE_Y_TRANS_SIZE_SIZE_BIT, HWCE_Y_TRANS_SIZE_SIZE_WIDTH); } + inline uint32_t size_get() { return this->get_field(HWCE_Y_TRANS_SIZE_SIZE_BIT, HWCE_Y_TRANS_SIZE_SIZE_WIDTH); } +}; + +class vp_hwce_y_line_stride_length : public vp::reg_32 +{ +public: + inline void length_set(uint32_t value) { this->set_field(value, HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_BIT, HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_WIDTH); } + inline uint32_t length_get() { return this->get_field(HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_BIT, HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_WIDTH); } + inline void stride_set(uint32_t value) { this->set_field(value, HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_BIT, HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_WIDTH); } + inline uint32_t stride_get() { return this->get_field(HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_BIT, HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_WIDTH); } +}; + +class vp_hwce_y_feat_stride_length : public vp::reg_32 +{ +public: + inline void length_set(uint32_t value) { this->set_field(value, HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_BIT, HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_WIDTH); } + inline uint32_t length_get() { return this->get_field(HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_BIT, HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_WIDTH); } + inline void stride_set(uint32_t value) { this->set_field(value, HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_BIT, HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_WIDTH); } + inline uint32_t stride_get() { return this->get_field(HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_BIT, HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_WIDTH); } +}; + +class vp_hwce_y_out_3_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_OUT_3_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_3_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_OUT_3_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_3_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_y_out_2_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_OUT_2_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_2_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_OUT_2_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_2_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_y_out_1_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_OUT_1_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_1_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_OUT_1_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_1_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_y_out_0_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_OUT_0_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_0_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_OUT_0_BASE_ADDR_ADDR_BIT, HWCE_Y_OUT_0_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_y_in_3_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_IN_3_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_3_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_IN_3_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_3_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_y_in_2_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_IN_2_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_2_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_IN_2_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_2_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_y_in_1_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_IN_1_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_1_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_IN_1_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_1_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_y_in_0_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_Y_IN_0_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_0_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_Y_IN_0_BASE_ADDR_ADDR_BIT, HWCE_Y_IN_0_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_x_trans_size : public vp::reg_32 +{ +public: + inline void size_set(uint32_t value) { this->set_field(value, HWCE_X_TRANS_SIZE_SIZE_BIT, HWCE_X_TRANS_SIZE_SIZE_WIDTH); } + inline uint32_t size_get() { return this->get_field(HWCE_X_TRANS_SIZE_SIZE_BIT, HWCE_X_TRANS_SIZE_SIZE_WIDTH); } +}; + +class vp_hwce_x_line_stride_length : public vp::reg_32 +{ +public: + inline void length_set(uint32_t value) { this->set_field(value, HWCE_X_LINE_STRIDE_LENGTH_LENGTH_BIT, HWCE_X_LINE_STRIDE_LENGTH_LENGTH_WIDTH); } + inline uint32_t length_get() { return this->get_field(HWCE_X_LINE_STRIDE_LENGTH_LENGTH_BIT, HWCE_X_LINE_STRIDE_LENGTH_LENGTH_WIDTH); } + inline void stride_set(uint32_t value) { this->set_field(value, HWCE_X_LINE_STRIDE_LENGTH_STRIDE_BIT, HWCE_X_LINE_STRIDE_LENGTH_STRIDE_WIDTH); } + inline uint32_t stride_get() { return this->get_field(HWCE_X_LINE_STRIDE_LENGTH_STRIDE_BIT, HWCE_X_LINE_STRIDE_LENGTH_STRIDE_WIDTH); } +}; + +class vp_hwce_x_feat_stride_length : public vp::reg_32 +{ +public: + inline void length_set(uint32_t value) { this->set_field(value, HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_BIT, HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_WIDTH); } + inline uint32_t length_get() { return this->get_field(HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_BIT, HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_WIDTH); } + inline void stride_set(uint32_t value) { this->set_field(value, HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_BIT, HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_WIDTH); } + inline uint32_t stride_get() { return this->get_field(HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_BIT, HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_WIDTH); } +}; + +class vp_hwce_x_in_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_X_IN_BASE_ADDR_ADDR_BIT, HWCE_X_IN_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_X_IN_BASE_ADDR_ADDR_BIT, HWCE_X_IN_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_w_base_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, HWCE_W_BASE_ADDR_ADDR_BIT, HWCE_W_BASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(HWCE_W_BASE_ADDR_ADDR_BIT, HWCE_W_BASE_ADDR_ADDR_WIDTH); } +}; + +class vp_hwce_job_config0 : public vp::reg_32 +{ +public: + inline void lbuflen_set(uint32_t value) { this->set_field(value, HWCE_JOB_CONFIG0_LBUFLEN_BIT, HWCE_JOB_CONFIG0_LBUFLEN_WIDTH); } + inline uint32_t lbuflen_get() { return this->get_field(HWCE_JOB_CONFIG0_LBUFLEN_BIT, HWCE_JOB_CONFIG0_LBUFLEN_WIDTH); } + inline void noyconst_set(uint32_t value) { this->set_field(value, HWCE_JOB_CONFIG0_NOYCONST_BIT, HWCE_JOB_CONFIG0_NOYCONST_WIDTH); } + inline uint32_t noyconst_get() { return this->get_field(HWCE_JOB_CONFIG0_NOYCONST_BIT, HWCE_JOB_CONFIG0_NOYCONST_WIDTH); } +}; + +class vp_hwce_job_config1 : public vp::reg_32 +{ +public: + inline void vect_disable_mask_set(uint32_t value) { this->set_field(value, HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_BIT, HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_WIDTH); } + inline uint32_t vect_disable_mask_get() { return this->get_field(HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_BIT, HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_WIDTH); } + inline void wof_param_set(uint32_t value) { this->set_field(value, HWCE_JOB_CONFIG1_WOF_PARAM_BIT, HWCE_JOB_CONFIG1_WOF_PARAM_WIDTH); } + inline uint32_t wof_param_get() { return this->get_field(HWCE_JOB_CONFIG1_WOF_PARAM_BIT, HWCE_JOB_CONFIG1_WOF_PARAM_WIDTH); } + inline void wif_param_set(uint32_t value) { this->set_field(value, HWCE_JOB_CONFIG1_WIF_PARAM_BIT, HWCE_JOB_CONFIG1_WIF_PARAM_WIDTH); } + inline uint32_t wif_param_get() { return this->get_field(HWCE_JOB_CONFIG1_WIF_PARAM_BIT, HWCE_JOB_CONFIG1_WIF_PARAM_WIDTH); } + inline void lo_set(uint32_t value) { this->set_field(value, HWCE_JOB_CONFIG1_LO_BIT, HWCE_JOB_CONFIG1_LO_WIDTH); } + inline uint32_t lo_get() { return this->get_field(HWCE_JOB_CONFIG1_LO_BIT, HWCE_JOB_CONFIG1_LO_WIDTH); } + inline void ln_set(uint32_t value) { this->set_field(value, HWCE_JOB_CONFIG1_LN_BIT, HWCE_JOB_CONFIG1_LN_WIDTH); } + inline uint32_t ln_get() { return this->get_field(HWCE_JOB_CONFIG1_LN_BIT, HWCE_JOB_CONFIG1_LN_WIDTH); } +}; + +class vp_hwce_y_trans_size_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_line_stride_length_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_feat_stride_length_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_3_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_2_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_1_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_0_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_3_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_2_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_1_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_0_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_trans_size_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_line_stride_length_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_feat_stride_length_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_in_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_w_base_addr_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_job_config0_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_job_config1_ctx0 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_trans_size_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_line_stride_length_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_feat_stride_length_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_3_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_2_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_1_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_out_0_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_3_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_2_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_1_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_y_in_0_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_trans_size_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_line_stride_length_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_feat_stride_length_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_x_in_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_w_base_addr_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_job_config0_ctx1 : public vp::reg_32 +{ +public: +}; + +class vp_hwce_job_config1_ctx1 : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef struct { + unsigned int trigger ; // Trigger the execution of an offloaded job + unsigned int acquire ; // Acquire the lock to offload job + unsigned int finished_jobs ; // Number of concluded jobs since last read + unsigned int status ; // Status of the HWCE + unsigned int running_job ; // ID of the currently running job + unsigned int soft_clear ; // Reset HWCE to known idle state + unsigned int gen_config0 ; // Generic configuration register 0 + unsigned int gen_config1 ; // Generic configuration register 1 + unsigned int y_trans_size ; // Total number of words to be read for yin and yout + unsigned int y_line_stride_length; // Line stride and length for yin and yout + unsigned int y_feat_stride_length; // Feature (block) stride and length for yin and yout + unsigned int y_out_3_base_addr; // Base address of yout[3] + unsigned int y_out_2_base_addr; // Base address of yout[2] + unsigned int y_out_1_base_addr; // Base address of yout[1] + unsigned int y_out_0_base_addr; // Base address of yout[0] + unsigned int y_in_3_base_addr; // Base address of yin[3] + unsigned int y_in_2_base_addr; // Base address of yin[2] + unsigned int y_in_1_base_addr; // Base address of yin[1] + unsigned int y_in_0_base_addr; // Base address of yin[0] + unsigned int x_trans_size ; // Total number of words to be read for xin + unsigned int x_line_stride_length; // Line stride and length for xin + unsigned int x_feat_stride_length; // Feature (block) stride and length for xin + unsigned int x_in_base_addr ; // Base address of xin + unsigned int w_base_addr ; // Base address of W + unsigned int job_config0 ; // Job configuration register 0 + unsigned int job_config1 ; // Job configuration register 1 + unsigned int y_trans_size_ctx0; // Total number of words to be read for yin and yout + unsigned int y_line_stride_length_ctx0; // Line stride and length for yin and yout + unsigned int y_feat_stride_length_ctx0; // Feature (block) stride and length for yin and yout + unsigned int y_out_3_base_addr_ctx0; // Base address of yout[3] + unsigned int y_out_2_base_addr_ctx0; // Base address of yout[2] + unsigned int y_out_1_base_addr_ctx0; // Base address of yout[1] + unsigned int y_out_0_base_addr_ctx0; // Base address of yout[0] + unsigned int y_in_3_base_addr_ctx0; // Base address of yin[3] + unsigned int y_in_2_base_addr_ctx0; // Base address of yin[2] + unsigned int y_in_1_base_addr_ctx0; // Base address of yin[1] + unsigned int y_in_0_base_addr_ctx0; // Base address of yin[0] + unsigned int x_trans_size_ctx0; // Total number of words to be read for xin + unsigned int x_line_stride_length_ctx0; // Line stride and length for xin + unsigned int x_feat_stride_length_ctx0; // Feature (block) stride and length for xin + unsigned int x_in_base_addr_ctx0; // Base address of xin + unsigned int w_base_addr_ctx0; // Base address of W + unsigned int job_config0_ctx0; // Job configuration register 0 + unsigned int job_config1_ctx0; // Job configuration register 1 + unsigned int y_trans_size_ctx1; // Total number of words to be read for yin and yout + unsigned int y_line_stride_length_ctx1; // Line stride and length for yin and yout + unsigned int y_feat_stride_length_ctx1; // Feature (block) stride and length for yin and yout + unsigned int y_out_3_base_addr_ctx1; // Base address of yout[3] + unsigned int y_out_2_base_addr_ctx1; // Base address of yout[2] + unsigned int y_out_1_base_addr_ctx1; // Base address of yout[1] + unsigned int y_out_0_base_addr_ctx1; // Base address of yout[0] + unsigned int y_in_3_base_addr_ctx1; // Base address of yin[3] + unsigned int y_in_2_base_addr_ctx1; // Base address of yin[2] + unsigned int y_in_1_base_addr_ctx1; // Base address of yin[1] + unsigned int y_in_0_base_addr_ctx1; // Base address of yin[0] + unsigned int x_trans_size_ctx1; // Total number of words to be read for xin + unsigned int x_line_stride_length_ctx1; // Line stride and length for xin + unsigned int x_feat_stride_length_ctx1; // Feature (block) stride and length for xin + unsigned int x_in_base_addr_ctx1; // Base address of xin + unsigned int w_base_addr_ctx1; // Base address of W + unsigned int job_config0_ctx1; // Job configuration register 0 + unsigned int job_config1_ctx1; // Job configuration register 1 +} __attribute__((packed)) hwce_hwce_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +static inline uint32_t hwce_trigger_get(uint32_t base) { return ARCHI_READ(base, HWCE_TRIGGER_OFFSET); } +static inline void hwce_trigger_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_TRIGGER_OFFSET, value); } + +static inline uint32_t hwce_acquire_get(uint32_t base) { return ARCHI_READ(base, HWCE_ACQUIRE_OFFSET); } +static inline void hwce_acquire_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_ACQUIRE_OFFSET, value); } + +static inline uint32_t hwce_finished_jobs_get(uint32_t base) { return ARCHI_READ(base, HWCE_FINISHED_JOBS_OFFSET); } +static inline void hwce_finished_jobs_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_FINISHED_JOBS_OFFSET, value); } + +static inline uint32_t hwce_status_get(uint32_t base) { return ARCHI_READ(base, HWCE_STATUS_OFFSET); } +static inline void hwce_status_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_STATUS_OFFSET, value); } + +static inline uint32_t hwce_running_job_get(uint32_t base) { return ARCHI_READ(base, HWCE_RUNNING_JOB_OFFSET); } +static inline void hwce_running_job_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_RUNNING_JOB_OFFSET, value); } + +static inline uint32_t hwce_soft_clear_get(uint32_t base) { return ARCHI_READ(base, HWCE_SOFT_CLEAR_OFFSET); } +static inline void hwce_soft_clear_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_SOFT_CLEAR_OFFSET, value); } + +static inline uint32_t hwce_gen_config0_get(uint32_t base) { return ARCHI_READ(base, HWCE_GEN_CONFIG0_OFFSET); } +static inline void hwce_gen_config0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_GEN_CONFIG0_OFFSET, value); } + +static inline uint32_t hwce_gen_config1_get(uint32_t base) { return ARCHI_READ(base, HWCE_GEN_CONFIG1_OFFSET); } +static inline void hwce_gen_config1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_GEN_CONFIG1_OFFSET, value); } + +static inline uint32_t hwce_y_trans_size_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_TRANS_SIZE_OFFSET); } +static inline void hwce_y_trans_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_TRANS_SIZE_OFFSET, value); } + +static inline uint32_t hwce_y_line_stride_length_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_LINE_STRIDE_LENGTH_OFFSET); } +static inline void hwce_y_line_stride_length_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_LINE_STRIDE_LENGTH_OFFSET, value); } + +static inline uint32_t hwce_y_feat_stride_length_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_FEAT_STRIDE_LENGTH_OFFSET); } +static inline void hwce_y_feat_stride_length_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_FEAT_STRIDE_LENGTH_OFFSET, value); } + +static inline uint32_t hwce_y_out_3_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_3_BASE_ADDR_OFFSET); } +static inline void hwce_y_out_3_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_3_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_y_out_2_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_2_BASE_ADDR_OFFSET); } +static inline void hwce_y_out_2_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_2_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_y_out_1_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_1_BASE_ADDR_OFFSET); } +static inline void hwce_y_out_1_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_1_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_y_out_0_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_0_BASE_ADDR_OFFSET); } +static inline void hwce_y_out_0_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_0_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_y_in_3_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_3_BASE_ADDR_OFFSET); } +static inline void hwce_y_in_3_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_3_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_y_in_2_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_2_BASE_ADDR_OFFSET); } +static inline void hwce_y_in_2_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_2_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_y_in_1_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_1_BASE_ADDR_OFFSET); } +static inline void hwce_y_in_1_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_1_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_y_in_0_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_0_BASE_ADDR_OFFSET); } +static inline void hwce_y_in_0_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_0_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_x_trans_size_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_TRANS_SIZE_OFFSET); } +static inline void hwce_x_trans_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_TRANS_SIZE_OFFSET, value); } + +static inline uint32_t hwce_x_line_stride_length_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_LINE_STRIDE_LENGTH_OFFSET); } +static inline void hwce_x_line_stride_length_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_LINE_STRIDE_LENGTH_OFFSET, value); } + +static inline uint32_t hwce_x_feat_stride_length_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_FEAT_STRIDE_LENGTH_OFFSET); } +static inline void hwce_x_feat_stride_length_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_FEAT_STRIDE_LENGTH_OFFSET, value); } + +static inline uint32_t hwce_x_in_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_IN_BASE_ADDR_OFFSET); } +static inline void hwce_x_in_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_IN_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_w_base_addr_get(uint32_t base) { return ARCHI_READ(base, HWCE_W_BASE_ADDR_OFFSET); } +static inline void hwce_w_base_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_W_BASE_ADDR_OFFSET, value); } + +static inline uint32_t hwce_job_config0_get(uint32_t base) { return ARCHI_READ(base, HWCE_JOB_CONFIG0_OFFSET); } +static inline void hwce_job_config0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_JOB_CONFIG0_OFFSET, value); } + +static inline uint32_t hwce_job_config1_get(uint32_t base) { return ARCHI_READ(base, HWCE_JOB_CONFIG1_OFFSET); } +static inline void hwce_job_config1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_JOB_CONFIG1_OFFSET, value); } + +static inline uint32_t hwce_y_trans_size_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_TRANS_SIZE_CTX0_OFFSET); } +static inline void hwce_y_trans_size_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_TRANS_SIZE_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_line_stride_length_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_LINE_STRIDE_LENGTH_CTX0_OFFSET); } +static inline void hwce_y_line_stride_length_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_LINE_STRIDE_LENGTH_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_feat_stride_length_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_FEAT_STRIDE_LENGTH_CTX0_OFFSET); } +static inline void hwce_y_feat_stride_length_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_FEAT_STRIDE_LENGTH_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_out_3_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_3_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_out_3_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_3_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_out_2_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_2_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_out_2_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_2_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_out_1_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_1_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_out_1_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_1_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_out_0_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_0_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_out_0_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_0_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_in_3_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_3_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_in_3_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_3_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_in_2_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_2_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_in_2_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_2_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_in_1_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_1_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_in_1_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_1_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_in_0_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_0_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_y_in_0_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_0_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_x_trans_size_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_TRANS_SIZE_CTX0_OFFSET); } +static inline void hwce_x_trans_size_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_TRANS_SIZE_CTX0_OFFSET, value); } + +static inline uint32_t hwce_x_line_stride_length_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_LINE_STRIDE_LENGTH_CTX0_OFFSET); } +static inline void hwce_x_line_stride_length_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_LINE_STRIDE_LENGTH_CTX0_OFFSET, value); } + +static inline uint32_t hwce_x_feat_stride_length_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_FEAT_STRIDE_LENGTH_CTX0_OFFSET); } +static inline void hwce_x_feat_stride_length_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_FEAT_STRIDE_LENGTH_CTX0_OFFSET, value); } + +static inline uint32_t hwce_x_in_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_IN_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_x_in_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_IN_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_w_base_addr_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_W_BASE_ADDR_CTX0_OFFSET); } +static inline void hwce_w_base_addr_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_W_BASE_ADDR_CTX0_OFFSET, value); } + +static inline uint32_t hwce_job_config0_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_JOB_CONFIG0_CTX0_OFFSET); } +static inline void hwce_job_config0_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_JOB_CONFIG0_CTX0_OFFSET, value); } + +static inline uint32_t hwce_job_config1_ctx0_get(uint32_t base) { return ARCHI_READ(base, HWCE_JOB_CONFIG1_CTX0_OFFSET); } +static inline void hwce_job_config1_ctx0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_JOB_CONFIG1_CTX0_OFFSET, value); } + +static inline uint32_t hwce_y_trans_size_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_TRANS_SIZE_CTX1_OFFSET); } +static inline void hwce_y_trans_size_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_TRANS_SIZE_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_line_stride_length_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_LINE_STRIDE_LENGTH_CTX1_OFFSET); } +static inline void hwce_y_line_stride_length_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_LINE_STRIDE_LENGTH_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_feat_stride_length_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_FEAT_STRIDE_LENGTH_CTX1_OFFSET); } +static inline void hwce_y_feat_stride_length_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_FEAT_STRIDE_LENGTH_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_out_3_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_3_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_out_3_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_3_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_out_2_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_2_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_out_2_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_2_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_out_1_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_1_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_out_1_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_1_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_out_0_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_OUT_0_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_out_0_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_OUT_0_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_in_3_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_3_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_in_3_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_3_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_in_2_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_2_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_in_2_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_2_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_in_1_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_1_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_in_1_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_1_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_y_in_0_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_Y_IN_0_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_y_in_0_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_Y_IN_0_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_x_trans_size_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_TRANS_SIZE_CTX1_OFFSET); } +static inline void hwce_x_trans_size_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_TRANS_SIZE_CTX1_OFFSET, value); } + +static inline uint32_t hwce_x_line_stride_length_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_LINE_STRIDE_LENGTH_CTX1_OFFSET); } +static inline void hwce_x_line_stride_length_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_LINE_STRIDE_LENGTH_CTX1_OFFSET, value); } + +static inline uint32_t hwce_x_feat_stride_length_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_FEAT_STRIDE_LENGTH_CTX1_OFFSET); } +static inline void hwce_x_feat_stride_length_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_FEAT_STRIDE_LENGTH_CTX1_OFFSET, value); } + +static inline uint32_t hwce_x_in_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_X_IN_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_x_in_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_X_IN_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_w_base_addr_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_W_BASE_ADDR_CTX1_OFFSET); } +static inline void hwce_w_base_addr_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_W_BASE_ADDR_CTX1_OFFSET, value); } + +static inline uint32_t hwce_job_config0_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_JOB_CONFIG0_CTX1_OFFSET); } +static inline void hwce_job_config0_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_JOB_CONFIG0_CTX1_OFFSET, value); } + +static inline uint32_t hwce_job_config1_ctx1_get(uint32_t base) { return ARCHI_READ(base, HWCE_JOB_CONFIG1_CTX1_OFFSET); } +static inline void hwce_job_config1_ctx1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HWCE_JOB_CONFIG1_CTX1_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#define HWCE_TRIGGER_ANY_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_TRIGGER_ANY_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_TRIGGER_ANY_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_TRIGGER_ANY(val) ((val) << 0) + +#define HWCE_ACQUIRE_ID_ERR_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define HWCE_ACQUIRE_ID_ERR_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define HWCE_ACQUIRE_ID_ERR_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define HWCE_ACQUIRE_ID_ERR(val) ((val) << 0) + +#define HWCE_ACQUIRE_ERR_GET(value) (ARCHI_BEXTRACTU((value),24,8)) +#define HWCE_ACQUIRE_ERR_GETS(value) (ARCHI_BEXTRACT((value),24,8)) +#define HWCE_ACQUIRE_ERR_SET(value,field) (ARCHI_BINSERT((value),(field),24,8)) +#define HWCE_ACQUIRE_ERR(val) ((val) << 8) + +#define HWCE_FINISHED_JOBS_JOBS_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_FINISHED_JOBS_JOBS_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_FINISHED_JOBS_JOBS_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_FINISHED_JOBS_JOBS(val) ((val) << 0) + +#define HWCE_STATUS_ST_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define HWCE_STATUS_ST_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define HWCE_STATUS_ST_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define HWCE_STATUS_ST(val) ((val) << 0) + +#define HWCE_RUNNING_JOB_ID_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define HWCE_RUNNING_JOB_ID_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define HWCE_RUNNING_JOB_ID_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define HWCE_RUNNING_JOB_ID(val) ((val) << 0) + +#define HWCE_SOFT_CLEAR_ANY_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_SOFT_CLEAR_ANY_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_SOFT_CLEAR_ANY_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_SOFT_CLEAR_ANY(val) ((val) << 0) + +#define HWCE_GEN_CONFIG0_QF_GET(value) (ARCHI_BEXTRACTU((value),6,0)) +#define HWCE_GEN_CONFIG0_QF_GETS(value) (ARCHI_BEXTRACT((value),6,0)) +#define HWCE_GEN_CONFIG0_QF_SET(value,field) (ARCHI_BINSERT((value),(field),6,0)) +#define HWCE_GEN_CONFIG0_QF(val) ((val) << 0) + +#define HWCE_GEN_CONFIG0_NF_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define HWCE_GEN_CONFIG0_NF_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define HWCE_GEN_CONFIG0_NF_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define HWCE_GEN_CONFIG0_NF(val) ((val) << 6) + +#define HWCE_GEN_CONFIG0_NY_GET(value) (ARCHI_BEXTRACTU((value),1,7)) +#define HWCE_GEN_CONFIG0_NY_GETS(value) (ARCHI_BEXTRACT((value),1,7)) +#define HWCE_GEN_CONFIG0_NY_SET(value,field) (ARCHI_BINSERT((value),(field),1,7)) +#define HWCE_GEN_CONFIG0_NY(val) ((val) << 7) + +#define HWCE_GEN_CONFIG0_UNS_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define HWCE_GEN_CONFIG0_UNS_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define HWCE_GEN_CONFIG0_UNS_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define HWCE_GEN_CONFIG0_UNS(val) ((val) << 8) + +#define HWCE_GEN_CONFIG0_VECT_GET(value) (ARCHI_BEXTRACTU((value),2,9)) +#define HWCE_GEN_CONFIG0_VECT_GETS(value) (ARCHI_BEXTRACT((value),2,9)) +#define HWCE_GEN_CONFIG0_VECT_SET(value,field) (ARCHI_BINSERT((value),(field),2,9)) +#define HWCE_GEN_CONFIG0_VECT(val) ((val) << 9) + +#define HWCE_GEN_CONFIG0_CONV_GET(value) (ARCHI_BEXTRACTU((value),2,11)) +#define HWCE_GEN_CONFIG0_CONV_GETS(value) (ARCHI_BEXTRACT((value),2,11)) +#define HWCE_GEN_CONFIG0_CONV_SET(value,field) (ARCHI_BINSERT((value),(field),2,11)) +#define HWCE_GEN_CONFIG0_CONV(val) ((val) << 11) + +#define HWCE_GEN_CONFIG0_NCP_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define HWCE_GEN_CONFIG0_NCP_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define HWCE_GEN_CONFIG0_NCP_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define HWCE_GEN_CONFIG0_NCP(val) ((val) << 13) + +#define HWCE_GEN_CONFIG0_WSTRIDE_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define HWCE_GEN_CONFIG0_WSTRIDE_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define HWCE_GEN_CONFIG0_WSTRIDE_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define HWCE_GEN_CONFIG0_WSTRIDE(val) ((val) << 16) + +#define HWCE_GEN_CONFIG1_PIXSHIFTL_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define HWCE_GEN_CONFIG1_PIXSHIFTL_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define HWCE_GEN_CONFIG1_PIXSHIFTL_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define HWCE_GEN_CONFIG1_PIXSHIFTL(val) ((val) << 0) + +#define HWCE_GEN_CONFIG1_PIXMODE_GET(value) (ARCHI_BEXTRACTU((value),2,8)) +#define HWCE_GEN_CONFIG1_PIXMODE_GETS(value) (ARCHI_BEXTRACT((value),2,8)) +#define HWCE_GEN_CONFIG1_PIXMODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,8)) +#define HWCE_GEN_CONFIG1_PIXMODE(val) ((val) << 8) + +#define HWCE_GEN_CONFIG1_PIXSHIFTR_GET(value) (ARCHI_BEXTRACTU((value),5,16)) +#define HWCE_GEN_CONFIG1_PIXSHIFTR_GETS(value) (ARCHI_BEXTRACT((value),5,16)) +#define HWCE_GEN_CONFIG1_PIXSHIFTR_SET(value,field) (ARCHI_BINSERT((value),(field),5,16)) +#define HWCE_GEN_CONFIG1_PIXSHIFTR(val) ((val) << 16) + +#define HWCE_Y_TRANS_SIZE_SIZE_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_TRANS_SIZE_SIZE_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_TRANS_SIZE_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_TRANS_SIZE_SIZE(val) ((val) << 0) + +#define HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define HWCE_Y_LINE_STRIDE_LENGTH_LENGTH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define HWCE_Y_LINE_STRIDE_LENGTH_LENGTH(val) ((val) << 0) + +#define HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define HWCE_Y_LINE_STRIDE_LENGTH_STRIDE_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define HWCE_Y_LINE_STRIDE_LENGTH_STRIDE(val) ((val) << 16) + +#define HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define HWCE_Y_FEAT_STRIDE_LENGTH_LENGTH(val) ((val) << 0) + +#define HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define HWCE_Y_FEAT_STRIDE_LENGTH_STRIDE(val) ((val) << 16) + +#define HWCE_Y_OUT_3_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_OUT_3_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_OUT_3_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_OUT_3_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_Y_OUT_2_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_OUT_2_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_OUT_2_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_OUT_2_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_Y_OUT_1_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_OUT_1_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_OUT_1_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_OUT_1_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_Y_OUT_0_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_OUT_0_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_OUT_0_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_OUT_0_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_Y_IN_3_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_IN_3_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_IN_3_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_IN_3_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_Y_IN_2_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_IN_2_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_IN_2_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_IN_2_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_Y_IN_1_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_IN_1_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_IN_1_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_IN_1_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_Y_IN_0_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_Y_IN_0_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_Y_IN_0_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_Y_IN_0_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_X_TRANS_SIZE_SIZE_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_X_TRANS_SIZE_SIZE_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_X_TRANS_SIZE_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_X_TRANS_SIZE_SIZE(val) ((val) << 0) + +#define HWCE_X_LINE_STRIDE_LENGTH_LENGTH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define HWCE_X_LINE_STRIDE_LENGTH_LENGTH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define HWCE_X_LINE_STRIDE_LENGTH_LENGTH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define HWCE_X_LINE_STRIDE_LENGTH_LENGTH(val) ((val) << 0) + +#define HWCE_X_LINE_STRIDE_LENGTH_STRIDE_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define HWCE_X_LINE_STRIDE_LENGTH_STRIDE_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define HWCE_X_LINE_STRIDE_LENGTH_STRIDE_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define HWCE_X_LINE_STRIDE_LENGTH_STRIDE(val) ((val) << 16) + +#define HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define HWCE_X_FEAT_STRIDE_LENGTH_LENGTH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define HWCE_X_FEAT_STRIDE_LENGTH_LENGTH(val) ((val) << 0) + +#define HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define HWCE_X_FEAT_STRIDE_LENGTH_STRIDE_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define HWCE_X_FEAT_STRIDE_LENGTH_STRIDE(val) ((val) << 16) + +#define HWCE_X_IN_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_X_IN_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_X_IN_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_X_IN_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_W_BASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define HWCE_W_BASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define HWCE_W_BASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define HWCE_W_BASE_ADDR_ADDR(val) ((val) << 0) + +#define HWCE_JOB_CONFIG0_LBUFLEN_GET(value) (ARCHI_BEXTRACTU((value),10,0)) +#define HWCE_JOB_CONFIG0_LBUFLEN_GETS(value) (ARCHI_BEXTRACT((value),10,0)) +#define HWCE_JOB_CONFIG0_LBUFLEN_SET(value,field) (ARCHI_BINSERT((value),(field),10,0)) +#define HWCE_JOB_CONFIG0_LBUFLEN(val) ((val) << 0) + +#define HWCE_JOB_CONFIG0_NOYCONST_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define HWCE_JOB_CONFIG0_NOYCONST_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define HWCE_JOB_CONFIG0_NOYCONST_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define HWCE_JOB_CONFIG0_NOYCONST(val) ((val) << 16) + +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK(val) ((val) << 0) + +#define HWCE_JOB_CONFIG1_WOF_PARAM_GET(value) (ARCHI_BEXTRACTU((value),6,8)) +#define HWCE_JOB_CONFIG1_WOF_PARAM_GETS(value) (ARCHI_BEXTRACT((value),6,8)) +#define HWCE_JOB_CONFIG1_WOF_PARAM_SET(value,field) (ARCHI_BINSERT((value),(field),6,8)) +#define HWCE_JOB_CONFIG1_WOF_PARAM(val) ((val) << 8) + +#define HWCE_JOB_CONFIG1_WIF_PARAM_GET(value) (ARCHI_BEXTRACTU((value),6,16)) +#define HWCE_JOB_CONFIG1_WIF_PARAM_GETS(value) (ARCHI_BEXTRACT((value),6,16)) +#define HWCE_JOB_CONFIG1_WIF_PARAM_SET(value,field) (ARCHI_BINSERT((value),(field),6,16)) +#define HWCE_JOB_CONFIG1_WIF_PARAM(val) ((val) << 16) + +#define HWCE_JOB_CONFIG1_LO_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define HWCE_JOB_CONFIG1_LO_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define HWCE_JOB_CONFIG1_LO_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define HWCE_JOB_CONFIG1_LO(val) ((val) << 24) + +#define HWCE_JOB_CONFIG1_LN_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define HWCE_JOB_CONFIG1_LN_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define HWCE_JOB_CONFIG1_LN_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define HWCE_JOB_CONFIG1_LN(val) ((val) << 25) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/hwce/hwce_v4_old.h b/sw/pulp-sdk/archi/include/archi/hwce/hwce_v4_old.h new file mode 100644 index 0000000..ac5abc0 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/hwce/hwce_v4_old.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_HWCE_HWCE_V4_H__ +#define __ARCHI_HWCE_HWCE_V4_H__ + +#define HWCE_ADDR_BASE ARCHI_HWCE_ADDR + +#define HWCE_TRIGGER 0x00 +#define HWCE_ACQUIRE 0x04 +#define HWCE_FINISHED 0x08 +#define HWCE_STATUS 0x0C +#define HWCE_RUNNING_JOB 0x10 +#define HWCE_SOFT_CLEAR 0x14 +#define HWCE_GEN_CONFIG0 0x20 +#define HWCE_GEN_CONFIG1 0x24 + +#define HWCE_Y_TRANS_SIZE 0x40 +#define HWCE_Y_LINE_STRIDE_LENGTH 0x44 +#define HWCE_Y_FEAT_STRIDE_LENGTH 0x48 +#define HWCE_Y_OUT_3_BASE_ADDR 0x4C +#define HWCE_Y_OUT_2_BASE_ADDR 0x50 +#define HWCE_Y_OUT_1_BASE_ADDR 0x54 +#define HWCE_Y_OUT_0_BASE_ADDR 0x58 +#define HWCE_Y_IN_3_BASE_ADDR 0x5C +#define HWCE_Y_IN_2_BASE_ADDR 0x60 +#define HWCE_Y_IN_1_BASE_ADDR 0x64 +#define HWCE_Y_IN_0_BASE_ADDR 0x68 +#define HWCE_X_TRANS_SIZE 0x6C +#define HWCE_X_LINE_STRIDE_LENGTH 0x70 +#define HWCE_X_FEAT_STRIDE_LENGTH 0x74 +#define HWCE_X_IN_BASE_ADDR 0x78 +#define HWCE_W_BASE_ADDR 0x7C +#define HWCE_JOB_CONFIG0 0x80 +#define HWCE_JOB_CONFIG1 0x84 + +#define HWCE_NB_IO_REGS 18 + +#define HWCE_ACQUIRE_CONTEXT_COPY -3 +#define HWCE_ACQUIRE_LOCKED -2 +#define HWCE_ACQUIRE_QUEUE_FULL -1 +#define HWCE_ACQUIRE_READY 0 + +#define HWCE_GEN_CONFIG0_WSTRIDE(x) ((x) >> 16) +#define HWCE_GEN_CONFIG0_NCP(x) (((x) >> 13) & 0x1) +#define HWCE_GEN_CONFIG0_CONV(x) (((x) >> 11) & 0x3) +#define HWCE_GEN_CONFIG0_VECT(x) (((x) >> 9) & 0x3) +#define HWCE_GEN_CONFIG0_UNS(x) (((x) >> 8) & 1) +#define HWCE_GEN_CONFIG0_NY(x) (((x) >> 7) & 1) +#define HWCE_GEN_CONFIG0_NF(x) (((x) >> 6) & 1) +#define HWCE_GEN_CONFIG0_QF(x) ((x) & 0x3f) + +#define HWCE_GEN_CONFIG0_CONV_5x5 0 +#define HWCE_GEN_CONFIG0_CONV_3x3 1 +#define HWCE_GEN_CONFIG0_CONV_4x7 2 + +#define HWCE_GEN_CONFIG0_VECT_1 0 +#define HWCE_GEN_CONFIG0_VECT_2 1 +#define HWCE_GEN_CONFIG0_VECT_4 2 + +#define HWCE_GEN_CONFIG1_PIXSHIFTR(x) (((x) >> 16) & 0x1F) +#define HWCE_GEN_CONFIG1_PIXMODE(x) (((x) >> 8) & 0x3) +#define HWCE_GEN_CONFIG1_PIXSHIFTL(x) (((x) >> 0) & 0x1F) + +#define HWCE_JOB_CONFIG0_NOYCONST(x) ((x) >> 16) +#define HWCE_JOB_CONFIG0_LBUFLEN(x) ((x) & 0x3ff) + +#define HWCE_JOB_CONFIG1_LO(x) (((x) >> 24) & 0x1) +#define HWCE_JOB_CONFIG1_WIF(x) (((x) >> 16) & 0x3F) +#define HWCE_JOB_CONFIG1_WOF(x) (((x) >> 8) & 0x1F) +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK(x) (((x) >> 0) & 0xF) + +#define HWCE_JOB_STRIDE(x) ((x) >> 16) +#define HWCE_JOB_LENGTH(x) ((x) & 0xffff) + +/* utility constants - used by hwce_rt and other libs */ + +// linebuffer width in 16-bit half-words +#define HWCE_LBSIZE 32 + +// loop order modes +#define HWCE_LOOP_ORDER_OLD 0 +#define HWCE_LOOP_ORDER_OF_IF 2 +#define HWCE_LOOP_ORDER_IF_OF 3 + +// 8-bit and 4-bit pixel modes +#define HWCE_PIXMODE_16BIT 0 +#define HWCE_PIXMODE_8BIT 1 +#define HWCE_PIXMODE_4BIT 2 + +// y_in modes +#define HWCE_Y_IN_MODE_ON 1 +#define HWCE_Y_IN_MODE_OFF 0 + +// disable vectors +#define HWCE_VECT_DISABLE(y0, y1, y2, y3) ( y0 << 3 | y1 << 2 | y2 << 1 | y3 ) + +// conv mode +#define HWCE_CONVMODE_5x5 HWCE_GEN_CONFIG0_CONV_5x5 +#define HWCE_CONVMODE_3x3 HWCE_GEN_CONFIG0_CONV_3x3 +#define HWCE_CONVMODE_4x7 HWCE_GEN_CONFIG0_CONV_4x7 + +// vect mode +#define HWCE_VECTMODE_1 HWCE_GEN_CONFIG0_VECT_1 +#define HWCE_VECTMODE_2 HWCE_GEN_CONFIG0_VECT_2 +#define HWCE_VECTMODE_4 HWCE_GEN_CONFIG0_VECT_4 + +// sign mode +#define HWCE_SIGNMODE_SIGNED 1 +#define HWCE_SIGNMODE_UNSIGNED 0 + +// weight order +#define HWCE_WEIGHTORDER_AUTOCORR 1 +#define HWCE_WEIGHTORDER_CONV 0 + +// job copy mechanism +#define HWCE_JOBCOPY_ON 1 +#define HWCE_JOBCOPY_OFF 0 + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/hwce/hwce_v5.h b/sw/pulp-sdk/archi/include/archi/hwce/hwce_v5.h new file mode 100644 index 0000000..07fc8ae --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/hwce/hwce_v5.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_HWCE_HWCE_V5_H__ +#define __ARCHI_HWCE_HWCE_V5_H__ + +#define HWCE_TRIGGER 0x00 +#define HWCE_ACQUIRE 0x04 +#define HWCE_FINISHED 0x08 +#define HWCE_STATUS 0x0C +#define HWCE_RUNNING_JOB 0x10 +#define HWCE_SOFT_CLEAR 0x14 +#define HWCE_OFFLOADER_ID 0x18 +#define HWCE_SW_EVT 0x1C + +#define HWCE_GEN_CONFIG0 0x20 +#define HWCE_GEN_CONFIG1 0x24 +#define HWCE_GEN_CONFIG2 0x28 + +#define HWCE_Y_TRANS_SIZE 0x40 +#define HWCE_Y_LINE_STRIDE_LENGTH 0x44 +#define HWCE_Y_FEAT_STRIDE_LENGTH 0x48 +#define HWCE_Y_OUT_3_BASE_ADDR 0x4C +#define HWCE_Y_OUT_2_BASE_ADDR 0x50 +#define HWCE_Y_OUT_1_BASE_ADDR 0x54 +#define HWCE_Y_OUT_0_BASE_ADDR 0x58 +#define HWCE_Y_IN_3_BASE_ADDR 0x5C +#define HWCE_Y_IN_2_BASE_ADDR 0x60 +#define HWCE_Y_IN_1_BASE_ADDR 0x64 +#define HWCE_Y_IN_0_BASE_ADDR 0x68 +#define HWCE_X_TRANS_SIZE 0x6C +#define HWCE_X_LINE_STRIDE_LENGTH 0x70 +#define HWCE_X_FEAT_STRIDE_LENGTH 0x74 +#define HWCE_X_IN_BASE_ADDR 0x78 +#define HWCE_W_BASE_ADDR 0x7C +#define HWCE_JOB_CONFIG0 0x80 +#define HWCE_JOB_CONFIG1 0x84 +#define HWCE_JOB_CONFIG2 0x88 +#define HWCE_TH_BASE_ADDR 0x8C +#define HWCE_LBUFXTRANSSIZE_ADDR 0x90 + +#define HWCE_NB_IO_REGS 19 + +#define HWCE_ACQUIRE_CONTEXT_COPY -3 +#define HWCE_ACQUIRE_LOCKED -2 +#define HWCE_ACQUIRE_QUEUE_FULL -1 +#define HWCE_ACQUIRE_READY 0 + +#define HWCE_GEN_CONFIG0_WSTRIDE(x) ((x) >> 16) +#define HWCE_GEN_CONFIG0_NCP(x) (((x) >> 13) & 0x1) +#define HWCE_GEN_CONFIG0_CONV(x) (((x) >> 11) & 0x3) +#define HWCE_GEN_CONFIG0_VECT(x) (((x) >> 9) & 0x3) +#define HWCE_GEN_CONFIG0_UNS(x) (((x) >> 8) & 1) +#define HWCE_GEN_CONFIG0_NY(x) (((x) >> 7) & 1) +#define HWCE_GEN_CONFIG0_NF(x) (((x) >> 6) & 1) +#define HWCE_GEN_CONFIG0_QF(x) ((x) & 0x3f) + +#define HWCE_GEN_CONFIG0_CONV_5x5 0 +#define HWCE_GEN_CONFIG0_CONV_3x3 1 +#define HWCE_GEN_CONFIG0_CONV_4x7 2 + +#define HWCE_GEN_CONFIG0_VECT_1 0 +#define HWCE_GEN_CONFIG0_VECT_2 1 +#define HWCE_GEN_CONFIG0_VECT_4 2 + +#define HWCE_GEN_CONFIG1_PIXSHIFTR(x) (((x) >> 16) & 0x1F) +#define HWCE_GEN_CONFIG1_PIXMODE(x) (((x) >> 8) & 0x3) +#define HWCE_GEN_CONFIG1_PIXSHIFTL(x) (((x) >> 0) & 0x1F) + +#define HWCE_JOB_CONFIG0_NOYCONST(x) ((x) >> 16) +#define HWCE_JOB_CONFIG0_LBUFLEN(x) ((x) & 0x3ff) + +#define HWCE_JOB_CONFIG1_LO(x) (((x) >> 24) & 0x1) +#define HWCE_JOB_CONFIG1_WIF(x) (((x) >> 16) & 0x3F) +#define HWCE_JOB_CONFIG1_WOF(x) (((x) >> 8) & 0x1F) +#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK(x) (((x) >> 0) & 0xF) + +#define HWCE_JOB_STRIDE(x) ((x) >> 16) +#define HWCE_JOB_LENGTH(x) ((x) & 0xffff) + +/* utility constants - used by hwce_rt and other libs */ + +// linebuffer width in 16-bit half-words +#define HWCE_LBSIZE 32 + +// loop order modes +#define HWCE_LOOP_ORDER_OF_IF 0 +#define HWCE_LOOP_ORDER_IF_OF 1 + +// quantization modes +#define HWCE_QMODE_16BIT 0 +#define HWCE_QMODE_8BIT 4 +#define HWCE_QMODE_4BIT 3 +#define HWCE_QMODE_2BIT 2 +#define HWCE_QMODE_1BIT 1 + +// y_in modes +#define HWCE_Y_IN_MODE_ON 1 +#define HWCE_Y_IN_MODE_OFF 0 + +// disable vectors +#define HWCE_VECT_DISABLE(y0, y1, y2, y3) ( y0 << 3 | y1 << 2 | y2 << 1 | y3 ) + +// conv mode +#define HWCE_CONVMODE_5x5 HWCE_GEN_CONFIG0_CONV_5x5 +#define HWCE_CONVMODE_3x3 HWCE_GEN_CONFIG0_CONV_3x3 +#define HWCE_CONVMODE_4x7 HWCE_GEN_CONFIG0_CONV_4x7 + +// vect mode +#define HWCE_VECTMODE_1 HWCE_GEN_CONFIG0_VECT_1 +#define HWCE_VECTMODE_2 HWCE_GEN_CONFIG0_VECT_2 +#define HWCE_VECTMODE_4 HWCE_GEN_CONFIG0_VECT_4 + +// sign mode +#define HWCE_SIGNMODE_SIGNED 1 +#define HWCE_SIGNMODE_UNSIGNED 0 + +// weight order +#define HWCE_WEIGHTORDER_AUTOCORR 1 +#define HWCE_WEIGHTORDER_CONV 0 + +// job copy mechanism +#define HWCE_JOBCOPY_ON 1 +#define HWCE_JOBCOPY_OFF 0 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/hwme/hwme_v1.h b/sw/pulp-sdk/archi/include/archi/hwme/hwme_v1.h new file mode 100644 index 0000000..79eebec --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/hwme/hwme_v1.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Authors: Francesco Conti + */ + +#ifndef __ARCHI_HWME_V1_H__ +#define __ARCHI_HWME_V1_H__ + +/* + * Control and generic configuration register layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0000 | 31: 0 | 0xffffffff || TRIGGER + * 1 | 0x0004 | 31: 0 | 0xffffffff || ACQUIRE + * 2 | 0x0008 | 31: 0 | 0xffffffff || EVT_ENABLE + * 3 | 0x000c | 31: 0 | 0xffffffff || STATUS + * 4 | 0x0010 | 31: 0 | 0xffffffff || RUNNING_JOB + * 5 | 0x0014 | 31: 0 | 0xffffffff || SOFT_CLEAR + * 6-7 | | | || Reserved + * 8 | 0x0020 | 31: 0 | 0xffffffff || BYTECODE0 [31:0] + * 9 | 0x0024 | 31: 0 | 0xffffffff || BYTECODE1 [63:32] + * 10 | 0x0028 | 31: 0 | 0xffffffff || BYTECODE2 [95:64] + * 11 | 0x002c | 31: 0 | 0xffffffff || BYTECODE3 [127:96] + * 12 | 0x0030 | 31: 0 | 0xffffffff || BYTECODE4 [159:128] + * 13 | 0x0034 | 31:16 | 0xffff0000 || LOOPS0 [15:0] + * | | 15: 0 | 0x0000ffff || BYTECODE5 [175:160] + * 14 | 0x0038 | 31: 0 | 0xffffffff || LOOPS1 [47:16] + * 15 | | 31: 0 | 0xffffffff || Reserved + * ================================================================================ + * + * Job-dependent registers layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0040 | 31: 0 | 0xffffffff || A_ADDR + * 1 | 0x0044 | 31: 0 | 0xffffffff || B_ADDR + * 2 | 0x0048 | 31: 0 | 0xffffffff || C_ADDR + * 3 | 0x004c | 31: 0 | 0xffffffff || D_ADDR + * 4 | 0x0050 | 31: 0 | 0xffffffff || NB_ITER + * 5 | 0x0054 | 31: 0 | 0xffffffff || LEN_ITER + * 6 | 0x0058 | 31:16 | 0xffff0000 || SHIFT + * | | 0: 0 | 0x00000001 || SIMPLEMUL + * 7 | 0x005c | 31: 0 | 0xffffffff || VECTSTRIDE + * 8 | 0x0060 | 31: 0 | 0xffffffff || VECTSTRIDE2 + * ================================================================================ + * + */ + +#define HWME_TRIGGER 0x00 +#define HWME_ACQUIRE 0x04 +#define HWME_FINISHED 0x08 +#define HWME_STATUS 0x0c +#define HWME_RUNNING_JOB 0x10 +#define HWME_SOFT_CLEAR 0x14 + +#define HWME_BYTECODE 0x20 +#define HWME_BYTECODE0_OFFS 0x00 +#define HWME_BYTECODE1_OFFS 0x04 +#define HWME_BYTECODE2_OFFS 0x08 +#define HWME_BYTECODE3_OFFS 0x0c +#define HWME_BYTECODE4_OFFS 0x10 +#define HWME_BYTECODE5_LOOPS0_OFFS 0x14 +#define HWME_LOOPS1_OFFS 0x18 + +#define HWME_A_ADDR 0x40 +#define HWME_B_ADDR 0x44 +#define HWME_C_ADDR 0x48 +#define HWME_D_ADDR 0x4c +#define HWME_NB_ITER 0x50 +#define HWME_LEN_ITER 0x54 +#define HWME_SHIFT_SIMPLEMUL 0x58 +#define HWME_VECTSTRIDE 0x5c +#define HWME_VECTSTRIDE2 0x60 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/itc/itc_v1.h b/sw/pulp-sdk/archi/include/archi/itc/itc_v1.h new file mode 100644 index 0000000..bf15bea --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/itc/itc_v1.h @@ -0,0 +1,268 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_ITC_ITC_V1_H__ +#define __INCLUDE_ARCHI_ITC_ITC_V1_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +#define ITC_MASK_OFFSET 0x0 + +#define ITC_MASK_SET_OFFSET 0x4 + +#define ITC_MASK_CLR_OFFSET 0x8 + +#define ITC_STATUS_OFFSET 0xc + +#define ITC_STATUS_SET_OFFSET 0x10 + +#define ITC_STATUS_CLR_OFFSET 0x14 + +#define ITC_ACK_OFFSET 0x18 + +#define ITC_ACK_SET_OFFSET 0x1c + +#define ITC_ACK_CLR_OFFSET 0x20 + +#define ITC_FIFO_OFFSET 0x24 + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_mask_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_mask_set_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_mask_clr_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_status_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_status_set_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_status_clr_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_ack_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_ack_set_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_ack_clr_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) itc_fifo_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_itc_mask : public vp::reg_32 +{ +public: +}; + +class vp_itc_mask_set : public vp::reg_32 +{ +public: +}; + +class vp_itc_mask_clr : public vp::reg_32 +{ +public: +}; + +class vp_itc_status : public vp::reg_32 +{ +public: +}; + +class vp_itc_status_set : public vp::reg_32 +{ +public: +}; + +class vp_itc_status_clr : public vp::reg_32 +{ +public: +}; + +class vp_itc_ack : public vp::reg_32 +{ +public: +}; + +class vp_itc_ack_set : public vp::reg_32 +{ +public: +}; + +class vp_itc_ack_clr : public vp::reg_32 +{ +public: +}; + +class vp_itc_fifo : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int mask ; + unsigned int mask_set ; + unsigned int mask_clr ; + unsigned int status ; + unsigned int status_set ; + unsigned int status_clr ; + unsigned int ack ; + unsigned int ack_set ; + unsigned int ack_clr ; + unsigned int fifo ; +} __attribute__((packed)) itc_itc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t itc_mask_get(uint32_t base) { return ARCHI_READ(base, ITC_MASK_OFFSET); } +static inline void itc_mask_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_MASK_OFFSET, value); } + +static inline uint32_t itc_mask_set_get(uint32_t base) { return ARCHI_READ(base, ITC_MASK_SET_OFFSET); } +static inline void itc_mask_set_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_MASK_SET_OFFSET, value); } + +static inline uint32_t itc_mask_clr_get(uint32_t base) { return ARCHI_READ(base, ITC_MASK_CLR_OFFSET); } +static inline void itc_mask_clr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_MASK_CLR_OFFSET, value); } + +static inline uint32_t itc_status_get(uint32_t base) { return ARCHI_READ(base, ITC_STATUS_OFFSET); } +static inline void itc_status_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_STATUS_OFFSET, value); } + +static inline uint32_t itc_status_set_get(uint32_t base) { return ARCHI_READ(base, ITC_STATUS_SET_OFFSET); } +static inline void itc_status_set_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_STATUS_SET_OFFSET, value); } + +static inline uint32_t itc_status_clr_get(uint32_t base) { return ARCHI_READ(base, ITC_STATUS_CLR_OFFSET); } +static inline void itc_status_clr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_STATUS_CLR_OFFSET, value); } + +static inline uint32_t itc_ack_get(uint32_t base) { return ARCHI_READ(base, ITC_ACK_OFFSET); } +static inline void itc_ack_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_ACK_OFFSET, value); } + +static inline uint32_t itc_ack_set_get(uint32_t base) { return ARCHI_READ(base, ITC_ACK_SET_OFFSET); } +static inline void itc_ack_set_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_ACK_SET_OFFSET, value); } + +static inline uint32_t itc_ack_clr_get(uint32_t base) { return ARCHI_READ(base, ITC_ACK_CLR_OFFSET); } +static inline void itc_ack_clr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_ACK_CLR_OFFSET, value); } + +static inline uint32_t itc_fifo_get(uint32_t base) { return ARCHI_READ(base, ITC_FIFO_OFFSET); } +static inline void itc_fifo_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, ITC_FIFO_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/maestro/maestro_v1.h b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v1.h new file mode 100644 index 0000000..630c85e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v1.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_MAESTRO_MAESTRO_V1_H__ +#define __ARCHI_MAESTRO_MAESTRO_V1_H__ + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/maestro/maestro_v1_new.h b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v1_new.h new file mode 100644 index 0000000..5f3274d --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v1_new.h @@ -0,0 +1,1472 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_MAESTRO_MAESTRO_V1_NEW_H__ +#define __INCLUDE_ARCHI_MAESTRO_MAESTRO_V1_NEW_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// PICL control register +#define MAESTRO_DLC_PCTRL_OFFSET 0x0 + +// PICL data read register +#define MAESTRO_PRDATA_OFFSET 0x4 + +// Status register +#define MAESTRO_DLC_SR_OFFSET 0x8 + +// Interrupt Mask register +#define MAESTRO_DLC_IMR_OFFSET 0xc + +// Interrupt flag register +#define MAESTRO_DLC_IFR_OFFSET 0x10 + +// icu_ok interrupt flag register +#define MAESTRO_DLC_IOIFR_OFFSET 0x14 + +// icu_delayed interrupt flag register +#define MAESTRO_DLC_IDIFR_OFFSET 0x18 + +// icu_mode_changed interrupt flags register +#define MAESTRO_DLC_IMCIFR_OFFSET 0x1c + + + +// +// REGISTERS FIELDS +// + +// Start of PICL access sequence. A rising edge of the start bit starts a PICL picl transfer. Start bit remains high until the end of the sequence, which means that no new access can be performed if an access is on going. (access: R/W) +#define MAESTRO_DLC_PCTRL_START_BIT 0 +#define MAESTRO_DLC_PCTRL_START_WIDTH 1 +#define MAESTRO_DLC_PCTRL_START_MASK 0x1 +#define MAESTRO_DLC_PCTRL_START_RESET 0x0 + +// Address of the transfer on the PICL bus. (access: R/W) +#define MAESTRO_DLC_PCTRL_PADDR_BIT 1 +#define MAESTRO_DLC_PCTRL_PADDR_WIDTH 14 +#define MAESTRO_DLC_PCTRL_PADDR_MASK 0x7ffe +#define MAESTRO_DLC_PCTRL_PADDR_RESET 0x0 + +// Direction of the transfer on the PICL bus. dir = 1 means read operation, dir = 0 means write operation. (access: R/W) +#define MAESTRO_DLC_PCTRL_DIR_BIT 15 +#define MAESTRO_DLC_PCTRL_DIR_WIDTH 1 +#define MAESTRO_DLC_PCTRL_DIR_MASK 0x8000 +#define MAESTRO_DLC_PCTRL_DIR_RESET 0x0 + +// Data to write on the PICL bus. (access: R/W) +#define MAESTRO_DLC_PCTRL_PWDATA_BIT 16 +#define MAESTRO_DLC_PCTRL_PWDATA_WIDTH 16 +#define MAESTRO_DLC_PCTRL_PWDATA_MASK 0xffff0000 +#define MAESTRO_DLC_PCTRL_PWDATA_RESET 0x0 + +// Data read on the PICL bus. This data is valid after a PICL read operation, when the picl_busy bit of the DLC_SR register becomes low. (access: R) +#define MAESTRO_PRDATA_PRDATA_BIT 0 +#define MAESTRO_PRDATA_PRDATA_WIDTH 8 +#define MAESTRO_PRDATA_PRDATA_MASK 0xff +#define MAESTRO_PRDATA_PRDATA_RESET 0x0 + +// This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. (access: R) +#define MAESTRO_DLC_SR_PICL_BUSY_BIT 0 +#define MAESTRO_DLC_SR_PICL_BUSY_WIDTH 1 +#define MAESTRO_DLC_SR_PICL_BUSY_MASK 0x1 +#define MAESTRO_DLC_SR_PICL_BUSY_RESET 0x0 + +// This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. (access: R) +#define MAESTRO_DLC_SR_SCU_BUSY_BIT 1 +#define MAESTRO_DLC_SR_SCU_BUSY_WIDTH 1 +#define MAESTRO_DLC_SR_SCU_BUSY_MASK 0x2 +#define MAESTRO_DLC_SR_SCU_BUSY_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_BIT 0 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_MASK 0x1 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT 1 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_MASK 0x2 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT 2 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK 0x4 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_BIT 3 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_MASK 0x8 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_BIT 4 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_MASK 0x10 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IOIFR register is set. Cleared when reading DCL_IOIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT 0 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_MASK 0x1 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IDIFR register is set. Cleared when reading DCL_IDIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT 1 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_MASK 0x2 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IMCIFR register is set. Cleared when reading DCL_IMCIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT 2 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK 0x4 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_RESET 0x0 + +// Set to 1 when PICL transfer is finish. Cleared writting 1 to the bit 3 of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT 3 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_MASK 0x8 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_RESET 0x0 + +// Set to 1 when SCU sequence is finished. Cleared when writting 1 to the bit 4 of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT 4 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_MASK 0x10 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_ok_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_ok_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT 1 +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_delayed_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_delayed_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT 1 +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_mode_changed_irq[ ] occurs. A read this register clears the register and the bit icu_mode_changed_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT 1 +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int start :1 ; // Start of PICL access sequence. A rising edge of the start bit starts a PICL picl transfer. Start bit remains high until the end of the sequence, which means that no new access can be performed if an access is on going. + unsigned int paddr :14; // Address of the transfer on the PICL bus. + unsigned int dir :1 ; // Direction of the transfer on the PICL bus. dir = 1 means read operation, dir = 0 means write operation. + unsigned int pwdata :16; // Data to write on the PICL bus. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_pctrl_t; + +typedef union { + struct { + unsigned int prdata :8 ; // Data read on the PICL bus. This data is valid after a PICL read operation, when the picl_busy bit of the DLC_SR register becomes low. + }; + unsigned int raw; +} __attribute__((packed)) maestro_prdata_t; + +typedef union { + struct { + unsigned int picl_busy :1 ; // This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. + unsigned int scu_busy :1 ; // This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_sr_t; + +typedef union { + struct { + unsigned int icu_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int icu_delayed_mask:1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int icu_mode_changed_mask:1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int picl_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int scu_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_imr_t; + +typedef union { + struct { + unsigned int icu_ok_flag :1 ; // Set to 1 when at least one of the bit of the DLC_IOIFR register is set. Cleared when reading DCL_IOIFR register. + unsigned int icu_delayed_flag:1 ; // Set to 1 when at least one of the bit of the DLC_IDIFR register is set. Cleared when reading DCL_IDIFR register. + unsigned int icu_mode_changed_flag:1 ; // Set to 1 when at least one of the bit of the DLC_IMCIFR register is set. Cleared when reading DCL_IMCIFR register. + unsigned int picl_ok_flag :1 ; // Set to 1 when PICL transfer is finish. Cleared writting 1 to the bit 3 of the DLC_IFR register. + unsigned int scu_ok_flag :1 ; // Set to 1 when SCU sequence is finished. Cleared when writting 1 to the bit 4 of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_ifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_ok_flags :31; // Bit set to 1 when a rising edge of the signal i_icu_ok_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_ok_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_ioifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_delayed_flags:31; // Bit set to 1 when a rising edge of the signal i_icu_delayed_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_delayed_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_idifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_mode_changed_flags:31; // Bit set to 1 when a rising edge of the signal i_icu_mode_changed_irq[ ] occurs. A read this register clears the register and the bit icu_mode_changed_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_imcifr_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_dlc_pctrl : public vp::reg_32 +{ +public: + inline void start_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_START_BIT, MAESTRO_DLC_PCTRL_START_WIDTH); } + inline uint32_t start_get() { return this->get_field(MAESTRO_DLC_PCTRL_START_BIT, MAESTRO_DLC_PCTRL_START_WIDTH); } + inline void paddr_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_PADDR_BIT, MAESTRO_DLC_PCTRL_PADDR_WIDTH); } + inline uint32_t paddr_get() { return this->get_field(MAESTRO_DLC_PCTRL_PADDR_BIT, MAESTRO_DLC_PCTRL_PADDR_WIDTH); } + inline void dir_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_DIR_BIT, MAESTRO_DLC_PCTRL_DIR_WIDTH); } + inline uint32_t dir_get() { return this->get_field(MAESTRO_DLC_PCTRL_DIR_BIT, MAESTRO_DLC_PCTRL_DIR_WIDTH); } + inline void pwdata_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_PWDATA_BIT, MAESTRO_DLC_PCTRL_PWDATA_WIDTH); } + inline uint32_t pwdata_get() { return this->get_field(MAESTRO_DLC_PCTRL_PWDATA_BIT, MAESTRO_DLC_PCTRL_PWDATA_WIDTH); } +}; + +class vp_maestro_prdata : public vp::reg_32 +{ +public: + inline void prdata_set(uint32_t value) { this->set_field(value, MAESTRO_PRDATA_PRDATA_BIT, MAESTRO_PRDATA_PRDATA_WIDTH); } + inline uint32_t prdata_get() { return this->get_field(MAESTRO_PRDATA_PRDATA_BIT, MAESTRO_PRDATA_PRDATA_WIDTH); } +}; + +class vp_maestro_dlc_sr : public vp::reg_32 +{ +public: + inline void picl_busy_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_SR_PICL_BUSY_BIT, MAESTRO_DLC_SR_PICL_BUSY_WIDTH); } + inline uint32_t picl_busy_get() { return this->get_field(MAESTRO_DLC_SR_PICL_BUSY_BIT, MAESTRO_DLC_SR_PICL_BUSY_WIDTH); } + inline void scu_busy_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_SR_SCU_BUSY_BIT, MAESTRO_DLC_SR_SCU_BUSY_WIDTH); } + inline uint32_t scu_busy_get() { return this->get_field(MAESTRO_DLC_SR_SCU_BUSY_BIT, MAESTRO_DLC_SR_SCU_BUSY_WIDTH); } +}; + +class vp_maestro_dlc_imr : public vp::reg_32 +{ +public: + inline void icu_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_OK_MASK_BIT, MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH); } + inline uint32_t icu_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_OK_MASK_BIT, MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH); } + inline void icu_delayed_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH); } + inline uint32_t icu_delayed_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH); } + inline void icu_mode_changed_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH); } + inline uint32_t icu_mode_changed_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH); } + inline void picl_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_PICL_OK_MASK_BIT, MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH); } + inline uint32_t picl_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_PICL_OK_MASK_BIT, MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH); } + inline void scu_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_SCU_OK_MASK_BIT, MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH); } + inline uint32_t scu_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_SCU_OK_MASK_BIT, MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH); } +}; + +class vp_maestro_dlc_ifr : public vp::reg_32 +{ +public: + inline void icu_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT, MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH); } + inline uint32_t icu_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT, MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH); } + inline void icu_delayed_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH); } + inline uint32_t icu_delayed_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH); } + inline void icu_mode_changed_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH); } + inline uint32_t icu_mode_changed_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH); } + inline void picl_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT, MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH); } + inline uint32_t picl_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT, MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH); } + inline void scu_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT, MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH); } + inline uint32_t scu_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT, MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH); } +}; + +class vp_maestro_dlc_ioifr : public vp::reg_32 +{ +public: + inline void icu_ok_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH); } + inline uint32_t icu_ok_flags_get() { return this->get_field(MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH); } +}; + +class vp_maestro_dlc_idifr : public vp::reg_32 +{ +public: + inline void icu_delayed_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH); } + inline uint32_t icu_delayed_flags_get() { return this->get_field(MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH); } +}; + +class vp_maestro_dlc_imcifr : public vp::reg_32 +{ +public: + inline void icu_mode_changed_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH); } + inline uint32_t icu_mode_changed_flags_get() { return this->get_field(MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int dlc_pctrl ; // PICL control register + unsigned int prdata ; // PICL data read register + unsigned int dlc_sr ; // Status register + unsigned int dlc_imr ; // Interrupt Mask register + unsigned int dlc_ifr ; // Interrupt flag register + unsigned int dlc_ioifr ; // icu_ok interrupt flag register + unsigned int dlc_idifr ; // icu_delayed interrupt flag register + unsigned int dlc_imcifr ; // icu_mode_changed interrupt flags register +} __attribute__((packed)) maestro_maestro_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_dlc_pctrl_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_PCTRL_OFFSET); } +static inline void maestro_dlc_pctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_PCTRL_OFFSET, value); } + +static inline uint32_t maestro_prdata_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_PRDATA_OFFSET); } +static inline void maestro_prdata_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_PRDATA_OFFSET, value); } + +static inline uint32_t maestro_dlc_sr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_SR_OFFSET); } +static inline void maestro_dlc_sr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_SR_OFFSET, value); } + +static inline uint32_t maestro_dlc_imr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IMR_OFFSET); } +static inline void maestro_dlc_imr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IMR_OFFSET, value); } + +static inline uint32_t maestro_dlc_ifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IFR_OFFSET); } +static inline void maestro_dlc_ifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_ioifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IOIFR_OFFSET); } +static inline void maestro_dlc_ioifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IOIFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_idifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IDIFR_OFFSET); } +static inline void maestro_dlc_idifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IDIFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_imcifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IMCIFR_OFFSET); } +static inline void maestro_dlc_imcifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IMCIFR_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_DLC_PCTRL_START_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_PCTRL_START_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_PCTRL_START_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_PCTRL_START(val) ((val) << 0) + +#define MAESTRO_DLC_PCTRL_PADDR_GET(value) (ARCHI_BEXTRACTU((value),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR_GETS(value) (ARCHI_BEXTRACT((value),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR_SET(value,field) (ARCHI_BINSERT((value),(field),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR(val) ((val) << 1) + +#define MAESTRO_DLC_PCTRL_DIR_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define MAESTRO_DLC_PCTRL_DIR_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define MAESTRO_DLC_PCTRL_DIR_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define MAESTRO_DLC_PCTRL_DIR(val) ((val) << 15) + +#define MAESTRO_DLC_PCTRL_PWDATA_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA(val) ((val) << 16) + +#define MAESTRO_PRDATA_PRDATA_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_PRDATA_PRDATA_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_PRDATA_PRDATA_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_PRDATA_PRDATA(val) ((val) << 0) + +#define MAESTRO_DLC_SR_PICL_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY(val) ((val) << 0) + +#define MAESTRO_DLC_SR_SCU_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY(val) ((val) << 1) + +#define MAESTRO_DLC_IMR_ICU_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK(val) ((val) << 0) + +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK(val) ((val) << 1) + +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK(val) ((val) << 2) + +#define MAESTRO_DLC_IMR_PICL_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK(val) ((val) << 3) + +#define MAESTRO_DLC_IMR_SCU_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK(val) ((val) << 4) + +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG(val) ((val) << 0) + +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG(val) ((val) << 1) + +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG(val) ((val) << 2) + +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG(val) ((val) << 3) + +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG(val) ((val) << 4) + +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS(val) ((val) << 1) + +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS(val) ((val) << 1) + +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS(val) ((val) << 1) + +#endif + + + +// +// GROUP wiu +// + +#define MAESTRO_WIU_OFFSET 0x0 + + + +// +// REGISTERS +// + +// Interrupt Sequence Processing Mask registers +#define MAESTRO_WIU_ISPMR_0_OFFSET 0x0 + +// Interrupt Sequence Processing Mask registers +#define MAESTRO_WIU_ISPMR_1_OFFSET 0x1 + +// Interrupt Flag register +#define MAESTRO_WIU_IFR_0_OFFSET 0x2 + +// Interrupt Flag register +#define MAESTRO_WIU_IFR_1_OFFSET 0x3 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_0_OFFSET 0x4 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_1_OFFSET 0x5 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_2_OFFSET 0x6 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_3_OFFSET 0x7 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_4_OFFSET 0x8 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_5_OFFSET 0x9 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_6_OFFSET 0xa + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_7_OFFSET 0xb + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_8_OFFSET 0xc + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_9_OFFSET 0xd + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_10_OFFSET 0xe + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_11_OFFSET 0xf + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_12_OFFSET 0x10 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_13_OFFSET 0x11 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_14_OFFSET 0x12 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_15_OFFSET 0x13 + + + +// +// REGISTERS FIELDS +// + +// A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] (access: R/W) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT 0 +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH 8 +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_MASK 0xff +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_RESET 0x0 + +// A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] (access: R/W) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT 0 +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH 8 +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_MASK 0xff +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_RESET 0x0 + +// Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. (access: R/W) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT 0 +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH 8 +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_MASK 0xff +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_RESET 0x0 + +// Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. (access: R/W) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT 0 +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH 8 +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_MASK 0xff +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT 0 +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH 5 +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_MASK 0x1f +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT 0 +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH 5 +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_MASK 0x1f +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT 0 +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH 5 +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_MASK 0x1f +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT 0 +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH 5 +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_MASK 0x1f +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT 0 +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH 5 +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_MASK 0x1f +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT 0 +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH 5 +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_MASK 0x1f +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT 0 +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH 5 +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_MASK 0x1f +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT 0 +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH 5 +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_MASK 0x1f +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT 0 +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH 5 +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_MASK 0x1f +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT 0 +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH 5 +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_MASK 0x1f +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT 0 +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH 5 +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_MASK 0x1f +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT 0 +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH 5 +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_MASK 0x1f +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT 0 +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH 5 +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_MASK 0x1f +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT 0 +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH 5 +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_MASK 0x1f +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT 0 +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH 5 +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_MASK 0x1f +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT 0 +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH 5 +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_MASK 0x1f +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int mask_modechg_en_irq:8 ; // A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ispmr_0_t; + +typedef union { + struct { + unsigned int mask_modechg_en_irq:8 ; // A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ispmr_1_t; + +typedef union { + struct { + unsigned int flag_irq :8 ; // Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ifr_0_t; + +typedef union { + struct { + unsigned int flag_irq :8 ; // Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ifr_1_t; + +typedef union { + struct { + unsigned int seq_sel_irq_0 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_0_t; + +typedef union { + struct { + unsigned int seq_sel_irq_1 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_1_t; + +typedef union { + struct { + unsigned int seq_sel_irq_2 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_2_t; + +typedef union { + struct { + unsigned int seq_sel_irq_3 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_3_t; + +typedef union { + struct { + unsigned int seq_sel_irq_4 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_4_t; + +typedef union { + struct { + unsigned int seq_sel_irq_5 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_5_t; + +typedef union { + struct { + unsigned int seq_sel_irq_6 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_6_t; + +typedef union { + struct { + unsigned int seq_sel_irq_7 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_7_t; + +typedef union { + struct { + unsigned int seq_sel_irq_8 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_8_t; + +typedef union { + struct { + unsigned int seq_sel_irq_9 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_9_t; + +typedef union { + struct { + unsigned int seq_sel_irq_10 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_10_t; + +typedef union { + struct { + unsigned int seq_sel_irq_11 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_11_t; + +typedef union { + struct { + unsigned int seq_sel_irq_12 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_12_t; + +typedef union { + struct { + unsigned int seq_sel_irq_13 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_13_t; + +typedef union { + struct { + unsigned int seq_sel_irq_14 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_14_t; + +typedef union { + struct { + unsigned int seq_sel_irq_15 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_15_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_wiu_ispmr_0 : public vp::reg_8 +{ +public: + inline void mask_modechg_en_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH); } + inline uint8_t mask_modechg_en_irq_get() { return this->get_field(MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ispmr_1 : public vp::reg_8 +{ +public: + inline void mask_modechg_en_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH); } + inline uint8_t mask_modechg_en_irq_get() { return this->get_field(MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ifr_0 : public vp::reg_8 +{ +public: + inline void flag_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH); } + inline uint8_t flag_irq_get() { return this->get_field(MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ifr_1 : public vp::reg_8 +{ +public: + inline void flag_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH); } + inline uint8_t flag_irq_get() { return this->get_field(MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_icr_0 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_0_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH); } + inline uint8_t seq_sel_irq_0_get() { return this->get_field(MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH); } +}; + +class vp_maestro_wiu_icr_1 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_1_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH); } + inline uint8_t seq_sel_irq_1_get() { return this->get_field(MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH); } +}; + +class vp_maestro_wiu_icr_2 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_2_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH); } + inline uint8_t seq_sel_irq_2_get() { return this->get_field(MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH); } +}; + +class vp_maestro_wiu_icr_3 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_3_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH); } + inline uint8_t seq_sel_irq_3_get() { return this->get_field(MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH); } +}; + +class vp_maestro_wiu_icr_4 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_4_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH); } + inline uint8_t seq_sel_irq_4_get() { return this->get_field(MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH); } +}; + +class vp_maestro_wiu_icr_5 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_5_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH); } + inline uint8_t seq_sel_irq_5_get() { return this->get_field(MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH); } +}; + +class vp_maestro_wiu_icr_6 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_6_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH); } + inline uint8_t seq_sel_irq_6_get() { return this->get_field(MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH); } +}; + +class vp_maestro_wiu_icr_7 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_7_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH); } + inline uint8_t seq_sel_irq_7_get() { return this->get_field(MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH); } +}; + +class vp_maestro_wiu_icr_8 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_8_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH); } + inline uint8_t seq_sel_irq_8_get() { return this->get_field(MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH); } +}; + +class vp_maestro_wiu_icr_9 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_9_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH); } + inline uint8_t seq_sel_irq_9_get() { return this->get_field(MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH); } +}; + +class vp_maestro_wiu_icr_10 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_10_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH); } + inline uint8_t seq_sel_irq_10_get() { return this->get_field(MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH); } +}; + +class vp_maestro_wiu_icr_11 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_11_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH); } + inline uint8_t seq_sel_irq_11_get() { return this->get_field(MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH); } +}; + +class vp_maestro_wiu_icr_12 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_12_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH); } + inline uint8_t seq_sel_irq_12_get() { return this->get_field(MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH); } +}; + +class vp_maestro_wiu_icr_13 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_13_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH); } + inline uint8_t seq_sel_irq_13_get() { return this->get_field(MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH); } +}; + +class vp_maestro_wiu_icr_14 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_14_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH); } + inline uint8_t seq_sel_irq_14_get() { return this->get_field(MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH); } +}; + +class vp_maestro_wiu_icr_15 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_15_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH); } + inline uint8_t seq_sel_irq_15_get() { return this->get_field(MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int wiu_ispmr_0 ; // Interrupt Sequence Processing Mask registers + unsigned int wiu_ispmr_1 ; // Interrupt Sequence Processing Mask registers + unsigned int wiu_ifr_0 ; // Interrupt Flag register + unsigned int wiu_ifr_1 ; // Interrupt Flag register + unsigned int wiu_icr_0 ; // Interrupt Control registers + unsigned int wiu_icr_1 ; // Interrupt Control registers + unsigned int wiu_icr_2 ; // Interrupt Control registers + unsigned int wiu_icr_3 ; // Interrupt Control registers + unsigned int wiu_icr_4 ; // Interrupt Control registers + unsigned int wiu_icr_5 ; // Interrupt Control registers + unsigned int wiu_icr_6 ; // Interrupt Control registers + unsigned int wiu_icr_7 ; // Interrupt Control registers + unsigned int wiu_icr_8 ; // Interrupt Control registers + unsigned int wiu_icr_9 ; // Interrupt Control registers + unsigned int wiu_icr_10 ; // Interrupt Control registers + unsigned int wiu_icr_11 ; // Interrupt Control registers + unsigned int wiu_icr_12 ; // Interrupt Control registers + unsigned int wiu_icr_13 ; // Interrupt Control registers + unsigned int wiu_icr_14 ; // Interrupt Control registers + unsigned int wiu_icr_15 ; // Interrupt Control registers +} __attribute__((packed)) maestro_wiu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_wiu_ispmr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ISPMR_0_OFFSET); } +static inline void maestro_wiu_ispmr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ISPMR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_ispmr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ISPMR_1_OFFSET); } +static inline void maestro_wiu_ispmr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ISPMR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_ifr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_IFR_0_OFFSET); } +static inline void maestro_wiu_ifr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_IFR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_ifr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_IFR_1_OFFSET); } +static inline void maestro_wiu_ifr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_IFR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_0_OFFSET); } +static inline void maestro_wiu_icr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_1_OFFSET); } +static inline void maestro_wiu_icr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_2_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_2_OFFSET); } +static inline void maestro_wiu_icr_2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_2_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_3_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_3_OFFSET); } +static inline void maestro_wiu_icr_3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_3_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_4_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_4_OFFSET); } +static inline void maestro_wiu_icr_4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_4_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_5_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_5_OFFSET); } +static inline void maestro_wiu_icr_5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_5_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_6_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_6_OFFSET); } +static inline void maestro_wiu_icr_6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_6_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_7_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_7_OFFSET); } +static inline void maestro_wiu_icr_7_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_7_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_8_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_8_OFFSET); } +static inline void maestro_wiu_icr_8_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_8_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_9_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_9_OFFSET); } +static inline void maestro_wiu_icr_9_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_9_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_10_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_10_OFFSET); } +static inline void maestro_wiu_icr_10_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_10_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_11_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_11_OFFSET); } +static inline void maestro_wiu_icr_11_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_11_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_12_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_12_OFFSET); } +static inline void maestro_wiu_icr_12_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_12_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_13_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_13_OFFSET); } +static inline void maestro_wiu_icr_13_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_13_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_14_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_14_OFFSET); } +static inline void maestro_wiu_icr_14_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_14_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_15_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_15_OFFSET); } +static inline void maestro_wiu_icr_15_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_15_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15(val) ((val) << 0) + +#endif + + + +// +// GROUP icu +// + + + +// +// REGISTERS +// + +// ICU control register +#define MAESTRO_ICU_CTRL_OFFSET 0x0 + +// ICU mode register +#define MAESTRO_ICU_MODE_OFFSET 0x1 + +// Island mode register +#define MAESTRO_ISLAND_MODE_OFFSET 0x2 + +// DMU mode register 0 +#define MAESTRO_DMU_MODE_OFFSET 0x3 + + + +// +// REGISTERS FIELDS +// + +// When a new mode corresponding to one of sixteen mode of the island mode table of the ICU is written as mode transition sequence is started to reach the written mode. (access: R/W) +#define MAESTRO_ICU_CTRL_ICU_CTRL_BIT 0 +#define MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH 4 +#define MAESTRO_ICU_CTRL_ICU_CTRL_MASK 0xf +#define MAESTRO_ICU_CTRL_ICU_CTRL_RESET 0x0 + +// Returns the current mode of the ICU when icu_mode_defined is low. (access: R) +#define MAESTRO_ICU_MODE_ICU_MODE_BIT 0 +#define MAESTRO_ICU_MODE_ICU_MODE_WIDTH 4 +#define MAESTRO_ICU_MODE_ICU_MODE_MASK 0xf +#define MAESTRO_ICU_MODE_ICU_MODE_RESET 0xf + +// When high, indicates that the current mode of the ICU is not defined in the mode table of the ICU When low, the value of the current mode is given by the icu_mode bits (access: R) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT 4 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH 1 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_MASK 0x10 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_RESET 0x1 + +// Mode of the island. (access: R) +#define MAESTRO_ISLAND_MODE_ISL_MODE_BIT 0 +#define MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH 2 +#define MAESTRO_ISLAND_MODE_ISL_MODE_MASK 0x3 +#define MAESTRO_ISLAND_MODE_ISL_MODE_RESET 0x0 + +// Mode of the DMU 0. (access: R) +#define MAESTRO_DMU_MODE_ISL_MODE_BIT 0 +#define MAESTRO_DMU_MODE_ISL_MODE_WIDTH 2 +#define MAESTRO_DMU_MODE_ISL_MODE_MASK 0x3 +#define MAESTRO_DMU_MODE_ISL_MODE_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int icu_ctrl :4 ; // When a new mode corresponding to one of sixteen mode of the island mode table of the ICU is written as mode transition sequence is started to reach the written mode. + }; + unsigned int raw; +} __attribute__((packed)) maestro_icu_ctrl_t; + +typedef union { + struct { + unsigned int icu_mode :4 ; // Returns the current mode of the ICU when icu_mode_defined is low. + unsigned int icu_mode_defined:1 ; // When high, indicates that the current mode of the ICU is not defined in the mode table of the ICU When low, the value of the current mode is given by the icu_mode bits + }; + unsigned int raw; +} __attribute__((packed)) maestro_icu_mode_t; + +typedef union { + struct { + unsigned int isl_mode :2 ; // Mode of the island. + }; + unsigned int raw; +} __attribute__((packed)) maestro_island_mode_t; + +typedef union { + struct { + unsigned int isl_mode :2 ; // Mode of the DMU 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dmu_mode_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_icu_ctrl : public vp::reg_8 +{ +public: + inline void icu_ctrl_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_CTRL_ICU_CTRL_BIT, MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH); } + inline uint8_t icu_ctrl_get() { return this->get_field(MAESTRO_ICU_CTRL_ICU_CTRL_BIT, MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH); } +}; + +class vp_maestro_icu_mode : public vp::reg_8 +{ +public: + inline void icu_mode_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_MODE_ICU_MODE_BIT, MAESTRO_ICU_MODE_ICU_MODE_WIDTH); } + inline uint8_t icu_mode_get() { return this->get_field(MAESTRO_ICU_MODE_ICU_MODE_BIT, MAESTRO_ICU_MODE_ICU_MODE_WIDTH); } + inline void icu_mode_defined_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH); } + inline uint8_t icu_mode_defined_get() { return this->get_field(MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH); } +}; + +class vp_maestro_island_mode : public vp::reg_8 +{ +public: + inline void isl_mode_set(uint8_t value) { this->set_field(value, MAESTRO_ISLAND_MODE_ISL_MODE_BIT, MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH); } + inline uint8_t isl_mode_get() { return this->get_field(MAESTRO_ISLAND_MODE_ISL_MODE_BIT, MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH); } +}; + +class vp_maestro_dmu_mode : public vp::reg_8 +{ +public: + inline void isl_mode_set(uint8_t value) { this->set_field(value, MAESTRO_DMU_MODE_ISL_MODE_BIT, MAESTRO_DMU_MODE_ISL_MODE_WIDTH); } + inline uint8_t isl_mode_get() { return this->get_field(MAESTRO_DMU_MODE_ISL_MODE_BIT, MAESTRO_DMU_MODE_ISL_MODE_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int icu_ctrl ; // ICU control register + unsigned int icu_mode ; // ICU mode register + unsigned int island_mode ; // Island mode register + unsigned int dmu_mode ; // DMU mode register 0 +} __attribute__((packed)) maestro_icu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_icu_ctrl_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ICU_CTRL_OFFSET); } +static inline void maestro_icu_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ICU_CTRL_OFFSET, value); } + +static inline uint32_t maestro_icu_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ICU_MODE_OFFSET); } +static inline void maestro_icu_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ICU_MODE_OFFSET, value); } + +static inline uint32_t maestro_island_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ISLAND_MODE_OFFSET); } +static inline void maestro_island_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ISLAND_MODE_OFFSET, value); } + +static inline uint32_t maestro_dmu_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DMU_MODE_OFFSET); } +static inline void maestro_dmu_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DMU_MODE_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_ICU_CTRL_ICU_CTRL_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL(val) ((val) << 0) + +#define MAESTRO_ICU_MODE_ICU_MODE_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE(val) ((val) << 0) + +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED(val) ((val) << 4) + +#define MAESTRO_ISLAND_MODE_ISL_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE(val) ((val) << 0) + +#define MAESTRO_DMU_MODE_ISL_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE(val) ((val) << 0) + +#endif + + + +// +// CUSTOM FIELDS +// +#define MAESTRO_ICU_SUPPLY_EXT 0x0 +#define MAESTRO_ICU_SUPPLY_RET 0x1 +#define MAESTRO_ICU_SUPPLY_CKOFF 0x2 +#define MAESTRO_ICU_SUPPLY_ON 0x3 +#define MAESTRO_ICU_REGU_NONE 0x7 +#define MAESTRO_ICU_REGU_OFF 0x0 +#define MAESTRO_ICU_REGU_RV 0x1 +#define MAESTRO_ICU_REGU_LV 0x2 +#define MAESTRO_ICU_REGU_MV 0x3 +#define MAESTRO_ICU_REGU_NV 0x4 +#define MAESTRO_ICU_CLK_FNONE 0x7 +#define MAESTRO_ICU_CLK_FOFF 0x0 +#define MAESTRO_ICU_CLK_LF 0x1 +#define MAESTRO_ICU_CLK_MF 0x2 +#define MAESTRO_ICU_CLK_NF 0x3 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/maestro/maestro_v2.h b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v2.h new file mode 100644 index 0000000..bafa8ca --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v2.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_MAESTRO_MAESTRO_V2_H__ +#define __ARCHI_MAESTRO_MAESTRO_V2_H__ + +#define ARCHI_PMU_BYPASS_ENABLE_BIT 0 +#define ARCHI_PMU_BYPASS_CLUSTER_POWER_BIT 1 +#define ARCHI_PMU_BYPASS_CLUSTER_CLOCK_BIT 2 +#define ARCHI_PMU_BYPASS_FLL_RETENTIVE_BIT 3 +#define ARCHI_PMU_BYPASS_FLL_OFF_BIT 4 +#define ARCHI_PMU_BYPASS_CLUSTER_RESET_BIT 5 +#define ARCHI_PMU_BYPASS_CLUSTER_ISOLATE_BIT 6 +#define ARCHI_PMU_BYPASS_CLUSTER_RETENTIVE_BIT 7 +#define ARCHI_PMU_BYPASS_POWER_OK_BIT 8 +#define ARCHI_PMU_BYPASS_CLOCK_OK_BIT 9 +#define ARCHI_PMU_BYPASS_POWER_DOWN_BIT 10 + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/maestro/maestro_v2_new.h b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v2_new.h new file mode 100644 index 0000000..afeeb83 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v2_new.h @@ -0,0 +1,1472 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_MAESTRO_MAESTRO_V2_NEW_H__ +#define __INCLUDE_ARCHI_MAESTRO_MAESTRO_V2_NEW_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// PICL control register +#define MAESTRO_DLC_PCTRL_OFFSET 0x0 + +// PICL data read register +#define MAESTRO_PRDATA_OFFSET 0x4 + +// Status register +#define MAESTRO_DLC_SR_OFFSET 0x8 + +// Interrupt Mask register +#define MAESTRO_DLC_IMR_OFFSET 0xc + +// Interrupt flag register +#define MAESTRO_DLC_IFR_OFFSET 0x10 + +// icu_ok interrupt flag register +#define MAESTRO_DLC_IOIFR_OFFSET 0x14 + +// icu_delayed interrupt flag register +#define MAESTRO_DLC_IDIFR_OFFSET 0x18 + +// icu_mode_changed interrupt flags register +#define MAESTRO_DLC_IMCIFR_OFFSET 0x1c + + + +// +// REGISTERS FIELDS +// + +// Start of PICL access sequence. A rising edge of the start bit starts a PICL picl transfer. Start bit remains high until the end of the sequence, which means that no new access can be performed if an access is on going. (access: R/W) +#define MAESTRO_DLC_PCTRL_START_BIT 0 +#define MAESTRO_DLC_PCTRL_START_WIDTH 1 +#define MAESTRO_DLC_PCTRL_START_MASK 0x1 +#define MAESTRO_DLC_PCTRL_START_RESET 0x0 + +// Address of the transfer on the PICL bus. (access: R/W) +#define MAESTRO_DLC_PCTRL_PADDR_BIT 1 +#define MAESTRO_DLC_PCTRL_PADDR_WIDTH 14 +#define MAESTRO_DLC_PCTRL_PADDR_MASK 0x7ffe +#define MAESTRO_DLC_PCTRL_PADDR_RESET 0x0 + +// Direction of the transfer on the PICL bus. dir = 1 means read operation, dir = 0 means write operation. (access: R/W) +#define MAESTRO_DLC_PCTRL_DIR_BIT 15 +#define MAESTRO_DLC_PCTRL_DIR_WIDTH 1 +#define MAESTRO_DLC_PCTRL_DIR_MASK 0x8000 +#define MAESTRO_DLC_PCTRL_DIR_RESET 0x0 + +// Data to write on the PICL bus. (access: R/W) +#define MAESTRO_DLC_PCTRL_PWDATA_BIT 16 +#define MAESTRO_DLC_PCTRL_PWDATA_WIDTH 16 +#define MAESTRO_DLC_PCTRL_PWDATA_MASK 0xffff0000 +#define MAESTRO_DLC_PCTRL_PWDATA_RESET 0x0 + +// Data read on the PICL bus. This data is valid after a PICL read operation, when the picl_busy bit of the DLC_SR register becomes low. (access: R) +#define MAESTRO_PRDATA_PRDATA_BIT 0 +#define MAESTRO_PRDATA_PRDATA_WIDTH 8 +#define MAESTRO_PRDATA_PRDATA_MASK 0xff +#define MAESTRO_PRDATA_PRDATA_RESET 0x0 + +// This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. (access: R) +#define MAESTRO_DLC_SR_PICL_BUSY_BIT 0 +#define MAESTRO_DLC_SR_PICL_BUSY_WIDTH 1 +#define MAESTRO_DLC_SR_PICL_BUSY_MASK 0x1 +#define MAESTRO_DLC_SR_PICL_BUSY_RESET 0x0 + +// This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. (access: R) +#define MAESTRO_DLC_SR_SCU_BUSY_BIT 1 +#define MAESTRO_DLC_SR_SCU_BUSY_WIDTH 1 +#define MAESTRO_DLC_SR_SCU_BUSY_MASK 0x2 +#define MAESTRO_DLC_SR_SCU_BUSY_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_BIT 0 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_MASK 0x1 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT 1 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_MASK 0x2 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT 2 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK 0x4 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_BIT 3 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_MASK 0x8 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_BIT 4 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_MASK 0x10 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IOIFR register is set. Cleared when reading DCL_IOIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT 0 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_MASK 0x1 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IDIFR register is set. Cleared when reading DCL_IDIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT 1 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_MASK 0x2 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IMCIFR register is set. Cleared when reading DCL_IMCIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT 2 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK 0x4 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_RESET 0x0 + +// Set to 1 when PICL transfer is finish. Cleared writting 1 to the bit 3 of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT 3 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_MASK 0x8 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_RESET 0x0 + +// Set to 1 when SCU sequence is finished. Cleared when writting 1 to the bit 4 of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT 4 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_MASK 0x10 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_ok_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_ok_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT 1 +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_delayed_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_delayed_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT 1 +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_mode_changed_irq[ ] occurs. A read this register clears the register and the bit icu_mode_changed_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT 1 +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int start :1 ; // Start of PICL access sequence. A rising edge of the start bit starts a PICL picl transfer. Start bit remains high until the end of the sequence, which means that no new access can be performed if an access is on going. + unsigned int paddr :14; // Address of the transfer on the PICL bus. + unsigned int dir :1 ; // Direction of the transfer on the PICL bus. dir = 1 means read operation, dir = 0 means write operation. + unsigned int pwdata :16; // Data to write on the PICL bus. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_pctrl_t; + +typedef union { + struct { + unsigned int prdata :8 ; // Data read on the PICL bus. This data is valid after a PICL read operation, when the picl_busy bit of the DLC_SR register becomes low. + }; + unsigned int raw; +} __attribute__((packed)) maestro_prdata_t; + +typedef union { + struct { + unsigned int picl_busy :1 ; // This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. + unsigned int scu_busy :1 ; // This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_sr_t; + +typedef union { + struct { + unsigned int icu_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int icu_delayed_mask:1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int icu_mode_changed_mask:1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int picl_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int scu_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_imr_t; + +typedef union { + struct { + unsigned int icu_ok_flag :1 ; // Set to 1 when at least one of the bit of the DLC_IOIFR register is set. Cleared when reading DCL_IOIFR register. + unsigned int icu_delayed_flag:1 ; // Set to 1 when at least one of the bit of the DLC_IDIFR register is set. Cleared when reading DCL_IDIFR register. + unsigned int icu_mode_changed_flag:1 ; // Set to 1 when at least one of the bit of the DLC_IMCIFR register is set. Cleared when reading DCL_IMCIFR register. + unsigned int picl_ok_flag :1 ; // Set to 1 when PICL transfer is finish. Cleared writting 1 to the bit 3 of the DLC_IFR register. + unsigned int scu_ok_flag :1 ; // Set to 1 when SCU sequence is finished. Cleared when writting 1 to the bit 4 of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_ifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_ok_flags :31; // Bit set to 1 when a rising edge of the signal i_icu_ok_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_ok_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_ioifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_delayed_flags:31; // Bit set to 1 when a rising edge of the signal i_icu_delayed_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_delayed_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_idifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_mode_changed_flags:31; // Bit set to 1 when a rising edge of the signal i_icu_mode_changed_irq[ ] occurs. A read this register clears the register and the bit icu_mode_changed_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_imcifr_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_dlc_pctrl : public vp::reg_32 +{ +public: + inline void start_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_START_BIT, MAESTRO_DLC_PCTRL_START_WIDTH); } + inline uint32_t start_get() { return this->get_field(MAESTRO_DLC_PCTRL_START_BIT, MAESTRO_DLC_PCTRL_START_WIDTH); } + inline void paddr_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_PADDR_BIT, MAESTRO_DLC_PCTRL_PADDR_WIDTH); } + inline uint32_t paddr_get() { return this->get_field(MAESTRO_DLC_PCTRL_PADDR_BIT, MAESTRO_DLC_PCTRL_PADDR_WIDTH); } + inline void dir_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_DIR_BIT, MAESTRO_DLC_PCTRL_DIR_WIDTH); } + inline uint32_t dir_get() { return this->get_field(MAESTRO_DLC_PCTRL_DIR_BIT, MAESTRO_DLC_PCTRL_DIR_WIDTH); } + inline void pwdata_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_PWDATA_BIT, MAESTRO_DLC_PCTRL_PWDATA_WIDTH); } + inline uint32_t pwdata_get() { return this->get_field(MAESTRO_DLC_PCTRL_PWDATA_BIT, MAESTRO_DLC_PCTRL_PWDATA_WIDTH); } +}; + +class vp_maestro_prdata : public vp::reg_32 +{ +public: + inline void prdata_set(uint32_t value) { this->set_field(value, MAESTRO_PRDATA_PRDATA_BIT, MAESTRO_PRDATA_PRDATA_WIDTH); } + inline uint32_t prdata_get() { return this->get_field(MAESTRO_PRDATA_PRDATA_BIT, MAESTRO_PRDATA_PRDATA_WIDTH); } +}; + +class vp_maestro_dlc_sr : public vp::reg_32 +{ +public: + inline void picl_busy_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_SR_PICL_BUSY_BIT, MAESTRO_DLC_SR_PICL_BUSY_WIDTH); } + inline uint32_t picl_busy_get() { return this->get_field(MAESTRO_DLC_SR_PICL_BUSY_BIT, MAESTRO_DLC_SR_PICL_BUSY_WIDTH); } + inline void scu_busy_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_SR_SCU_BUSY_BIT, MAESTRO_DLC_SR_SCU_BUSY_WIDTH); } + inline uint32_t scu_busy_get() { return this->get_field(MAESTRO_DLC_SR_SCU_BUSY_BIT, MAESTRO_DLC_SR_SCU_BUSY_WIDTH); } +}; + +class vp_maestro_dlc_imr : public vp::reg_32 +{ +public: + inline void icu_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_OK_MASK_BIT, MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH); } + inline uint32_t icu_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_OK_MASK_BIT, MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH); } + inline void icu_delayed_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH); } + inline uint32_t icu_delayed_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH); } + inline void icu_mode_changed_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH); } + inline uint32_t icu_mode_changed_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH); } + inline void picl_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_PICL_OK_MASK_BIT, MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH); } + inline uint32_t picl_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_PICL_OK_MASK_BIT, MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH); } + inline void scu_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_SCU_OK_MASK_BIT, MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH); } + inline uint32_t scu_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_SCU_OK_MASK_BIT, MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH); } +}; + +class vp_maestro_dlc_ifr : public vp::reg_32 +{ +public: + inline void icu_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT, MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH); } + inline uint32_t icu_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT, MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH); } + inline void icu_delayed_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH); } + inline uint32_t icu_delayed_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH); } + inline void icu_mode_changed_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH); } + inline uint32_t icu_mode_changed_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH); } + inline void picl_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT, MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH); } + inline uint32_t picl_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT, MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH); } + inline void scu_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT, MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH); } + inline uint32_t scu_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT, MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH); } +}; + +class vp_maestro_dlc_ioifr : public vp::reg_32 +{ +public: + inline void icu_ok_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH); } + inline uint32_t icu_ok_flags_get() { return this->get_field(MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH); } +}; + +class vp_maestro_dlc_idifr : public vp::reg_32 +{ +public: + inline void icu_delayed_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH); } + inline uint32_t icu_delayed_flags_get() { return this->get_field(MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH); } +}; + +class vp_maestro_dlc_imcifr : public vp::reg_32 +{ +public: + inline void icu_mode_changed_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH); } + inline uint32_t icu_mode_changed_flags_get() { return this->get_field(MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int dlc_pctrl ; // PICL control register + unsigned int prdata ; // PICL data read register + unsigned int dlc_sr ; // Status register + unsigned int dlc_imr ; // Interrupt Mask register + unsigned int dlc_ifr ; // Interrupt flag register + unsigned int dlc_ioifr ; // icu_ok interrupt flag register + unsigned int dlc_idifr ; // icu_delayed interrupt flag register + unsigned int dlc_imcifr ; // icu_mode_changed interrupt flags register +} __attribute__((packed)) maestro_maestro_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_dlc_pctrl_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_PCTRL_OFFSET); } +static inline void maestro_dlc_pctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_PCTRL_OFFSET, value); } + +static inline uint32_t maestro_prdata_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_PRDATA_OFFSET); } +static inline void maestro_prdata_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_PRDATA_OFFSET, value); } + +static inline uint32_t maestro_dlc_sr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_SR_OFFSET); } +static inline void maestro_dlc_sr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_SR_OFFSET, value); } + +static inline uint32_t maestro_dlc_imr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IMR_OFFSET); } +static inline void maestro_dlc_imr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IMR_OFFSET, value); } + +static inline uint32_t maestro_dlc_ifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IFR_OFFSET); } +static inline void maestro_dlc_ifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_ioifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IOIFR_OFFSET); } +static inline void maestro_dlc_ioifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IOIFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_idifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IDIFR_OFFSET); } +static inline void maestro_dlc_idifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IDIFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_imcifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IMCIFR_OFFSET); } +static inline void maestro_dlc_imcifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IMCIFR_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_DLC_PCTRL_START_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_PCTRL_START_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_PCTRL_START_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_PCTRL_START(val) ((val) << 0) + +#define MAESTRO_DLC_PCTRL_PADDR_GET(value) (ARCHI_BEXTRACTU((value),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR_GETS(value) (ARCHI_BEXTRACT((value),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR_SET(value,field) (ARCHI_BINSERT((value),(field),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR(val) ((val) << 1) + +#define MAESTRO_DLC_PCTRL_DIR_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define MAESTRO_DLC_PCTRL_DIR_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define MAESTRO_DLC_PCTRL_DIR_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define MAESTRO_DLC_PCTRL_DIR(val) ((val) << 15) + +#define MAESTRO_DLC_PCTRL_PWDATA_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA(val) ((val) << 16) + +#define MAESTRO_PRDATA_PRDATA_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_PRDATA_PRDATA_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_PRDATA_PRDATA_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_PRDATA_PRDATA(val) ((val) << 0) + +#define MAESTRO_DLC_SR_PICL_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY(val) ((val) << 0) + +#define MAESTRO_DLC_SR_SCU_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY(val) ((val) << 1) + +#define MAESTRO_DLC_IMR_ICU_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK(val) ((val) << 0) + +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK(val) ((val) << 1) + +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK(val) ((val) << 2) + +#define MAESTRO_DLC_IMR_PICL_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK(val) ((val) << 3) + +#define MAESTRO_DLC_IMR_SCU_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK(val) ((val) << 4) + +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG(val) ((val) << 0) + +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG(val) ((val) << 1) + +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG(val) ((val) << 2) + +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG(val) ((val) << 3) + +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG(val) ((val) << 4) + +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS(val) ((val) << 1) + +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS(val) ((val) << 1) + +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS(val) ((val) << 1) + +#endif + + + +// +// GROUP wiu +// + +#define MAESTRO_WIU_OFFSET 0x1 + + + +// +// REGISTERS +// + +// Interrupt Sequence Processing Mask registers +#define MAESTRO_WIU_ISPMR_0_OFFSET 0x0 + +// Interrupt Sequence Processing Mask registers +#define MAESTRO_WIU_ISPMR_1_OFFSET 0x1 + +// Interrupt Flag register +#define MAESTRO_WIU_IFR_0_OFFSET 0x2 + +// Interrupt Flag register +#define MAESTRO_WIU_IFR_1_OFFSET 0x3 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_0_OFFSET 0x4 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_1_OFFSET 0x5 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_2_OFFSET 0x6 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_3_OFFSET 0x7 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_4_OFFSET 0x8 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_5_OFFSET 0x9 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_6_OFFSET 0xa + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_7_OFFSET 0xb + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_8_OFFSET 0xc + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_9_OFFSET 0xd + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_10_OFFSET 0xe + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_11_OFFSET 0xf + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_12_OFFSET 0x10 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_13_OFFSET 0x11 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_14_OFFSET 0x12 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_15_OFFSET 0x13 + + + +// +// REGISTERS FIELDS +// + +// A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] (access: R/W) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT 0 +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH 8 +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_MASK 0xff +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_RESET 0x0 + +// A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] (access: R/W) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT 0 +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH 8 +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_MASK 0xff +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_RESET 0x0 + +// Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. (access: R/W) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT 0 +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH 8 +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_MASK 0xff +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_RESET 0x0 + +// Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. (access: R/W) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT 0 +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH 8 +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_MASK 0xff +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT 0 +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH 5 +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_MASK 0x1f +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT 0 +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH 5 +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_MASK 0x1f +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT 0 +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH 5 +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_MASK 0x1f +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT 0 +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH 5 +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_MASK 0x1f +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT 0 +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH 5 +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_MASK 0x1f +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT 0 +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH 5 +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_MASK 0x1f +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT 0 +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH 5 +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_MASK 0x1f +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT 0 +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH 5 +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_MASK 0x1f +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT 0 +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH 5 +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_MASK 0x1f +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT 0 +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH 5 +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_MASK 0x1f +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT 0 +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH 5 +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_MASK 0x1f +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT 0 +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH 5 +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_MASK 0x1f +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT 0 +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH 5 +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_MASK 0x1f +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT 0 +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH 5 +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_MASK 0x1f +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT 0 +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH 5 +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_MASK 0x1f +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT 0 +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH 5 +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_MASK 0x1f +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int mask_modechg_en_irq:8 ; // A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ispmr_0_t; + +typedef union { + struct { + unsigned int mask_modechg_en_irq:8 ; // A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ispmr_1_t; + +typedef union { + struct { + unsigned int flag_irq :8 ; // Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ifr_0_t; + +typedef union { + struct { + unsigned int flag_irq :8 ; // Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ifr_1_t; + +typedef union { + struct { + unsigned int seq_sel_irq_0 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_0_t; + +typedef union { + struct { + unsigned int seq_sel_irq_1 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_1_t; + +typedef union { + struct { + unsigned int seq_sel_irq_2 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_2_t; + +typedef union { + struct { + unsigned int seq_sel_irq_3 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_3_t; + +typedef union { + struct { + unsigned int seq_sel_irq_4 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_4_t; + +typedef union { + struct { + unsigned int seq_sel_irq_5 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_5_t; + +typedef union { + struct { + unsigned int seq_sel_irq_6 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_6_t; + +typedef union { + struct { + unsigned int seq_sel_irq_7 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_7_t; + +typedef union { + struct { + unsigned int seq_sel_irq_8 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_8_t; + +typedef union { + struct { + unsigned int seq_sel_irq_9 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_9_t; + +typedef union { + struct { + unsigned int seq_sel_irq_10 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_10_t; + +typedef union { + struct { + unsigned int seq_sel_irq_11 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_11_t; + +typedef union { + struct { + unsigned int seq_sel_irq_12 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_12_t; + +typedef union { + struct { + unsigned int seq_sel_irq_13 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_13_t; + +typedef union { + struct { + unsigned int seq_sel_irq_14 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_14_t; + +typedef union { + struct { + unsigned int seq_sel_irq_15 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_15_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_wiu_ispmr_0 : public vp::reg_8 +{ +public: + inline void mask_modechg_en_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH); } + inline uint8_t mask_modechg_en_irq_get() { return this->get_field(MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ispmr_1 : public vp::reg_8 +{ +public: + inline void mask_modechg_en_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH); } + inline uint8_t mask_modechg_en_irq_get() { return this->get_field(MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ifr_0 : public vp::reg_8 +{ +public: + inline void flag_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH); } + inline uint8_t flag_irq_get() { return this->get_field(MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ifr_1 : public vp::reg_8 +{ +public: + inline void flag_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH); } + inline uint8_t flag_irq_get() { return this->get_field(MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_icr_0 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_0_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH); } + inline uint8_t seq_sel_irq_0_get() { return this->get_field(MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH); } +}; + +class vp_maestro_wiu_icr_1 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_1_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH); } + inline uint8_t seq_sel_irq_1_get() { return this->get_field(MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH); } +}; + +class vp_maestro_wiu_icr_2 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_2_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH); } + inline uint8_t seq_sel_irq_2_get() { return this->get_field(MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH); } +}; + +class vp_maestro_wiu_icr_3 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_3_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH); } + inline uint8_t seq_sel_irq_3_get() { return this->get_field(MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH); } +}; + +class vp_maestro_wiu_icr_4 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_4_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH); } + inline uint8_t seq_sel_irq_4_get() { return this->get_field(MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH); } +}; + +class vp_maestro_wiu_icr_5 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_5_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH); } + inline uint8_t seq_sel_irq_5_get() { return this->get_field(MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH); } +}; + +class vp_maestro_wiu_icr_6 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_6_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH); } + inline uint8_t seq_sel_irq_6_get() { return this->get_field(MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH); } +}; + +class vp_maestro_wiu_icr_7 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_7_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH); } + inline uint8_t seq_sel_irq_7_get() { return this->get_field(MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH); } +}; + +class vp_maestro_wiu_icr_8 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_8_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH); } + inline uint8_t seq_sel_irq_8_get() { return this->get_field(MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH); } +}; + +class vp_maestro_wiu_icr_9 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_9_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH); } + inline uint8_t seq_sel_irq_9_get() { return this->get_field(MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH); } +}; + +class vp_maestro_wiu_icr_10 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_10_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH); } + inline uint8_t seq_sel_irq_10_get() { return this->get_field(MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH); } +}; + +class vp_maestro_wiu_icr_11 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_11_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH); } + inline uint8_t seq_sel_irq_11_get() { return this->get_field(MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH); } +}; + +class vp_maestro_wiu_icr_12 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_12_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH); } + inline uint8_t seq_sel_irq_12_get() { return this->get_field(MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH); } +}; + +class vp_maestro_wiu_icr_13 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_13_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH); } + inline uint8_t seq_sel_irq_13_get() { return this->get_field(MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH); } +}; + +class vp_maestro_wiu_icr_14 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_14_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH); } + inline uint8_t seq_sel_irq_14_get() { return this->get_field(MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH); } +}; + +class vp_maestro_wiu_icr_15 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_15_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH); } + inline uint8_t seq_sel_irq_15_get() { return this->get_field(MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int wiu_ispmr_0 ; // Interrupt Sequence Processing Mask registers + unsigned int wiu_ispmr_1 ; // Interrupt Sequence Processing Mask registers + unsigned int wiu_ifr_0 ; // Interrupt Flag register + unsigned int wiu_ifr_1 ; // Interrupt Flag register + unsigned int wiu_icr_0 ; // Interrupt Control registers + unsigned int wiu_icr_1 ; // Interrupt Control registers + unsigned int wiu_icr_2 ; // Interrupt Control registers + unsigned int wiu_icr_3 ; // Interrupt Control registers + unsigned int wiu_icr_4 ; // Interrupt Control registers + unsigned int wiu_icr_5 ; // Interrupt Control registers + unsigned int wiu_icr_6 ; // Interrupt Control registers + unsigned int wiu_icr_7 ; // Interrupt Control registers + unsigned int wiu_icr_8 ; // Interrupt Control registers + unsigned int wiu_icr_9 ; // Interrupt Control registers + unsigned int wiu_icr_10 ; // Interrupt Control registers + unsigned int wiu_icr_11 ; // Interrupt Control registers + unsigned int wiu_icr_12 ; // Interrupt Control registers + unsigned int wiu_icr_13 ; // Interrupt Control registers + unsigned int wiu_icr_14 ; // Interrupt Control registers + unsigned int wiu_icr_15 ; // Interrupt Control registers +} __attribute__((packed)) maestro_wiu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_wiu_ispmr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ISPMR_0_OFFSET); } +static inline void maestro_wiu_ispmr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ISPMR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_ispmr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ISPMR_1_OFFSET); } +static inline void maestro_wiu_ispmr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ISPMR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_ifr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_IFR_0_OFFSET); } +static inline void maestro_wiu_ifr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_IFR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_ifr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_IFR_1_OFFSET); } +static inline void maestro_wiu_ifr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_IFR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_0_OFFSET); } +static inline void maestro_wiu_icr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_1_OFFSET); } +static inline void maestro_wiu_icr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_2_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_2_OFFSET); } +static inline void maestro_wiu_icr_2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_2_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_3_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_3_OFFSET); } +static inline void maestro_wiu_icr_3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_3_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_4_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_4_OFFSET); } +static inline void maestro_wiu_icr_4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_4_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_5_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_5_OFFSET); } +static inline void maestro_wiu_icr_5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_5_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_6_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_6_OFFSET); } +static inline void maestro_wiu_icr_6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_6_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_7_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_7_OFFSET); } +static inline void maestro_wiu_icr_7_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_7_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_8_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_8_OFFSET); } +static inline void maestro_wiu_icr_8_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_8_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_9_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_9_OFFSET); } +static inline void maestro_wiu_icr_9_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_9_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_10_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_10_OFFSET); } +static inline void maestro_wiu_icr_10_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_10_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_11_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_11_OFFSET); } +static inline void maestro_wiu_icr_11_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_11_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_12_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_12_OFFSET); } +static inline void maestro_wiu_icr_12_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_12_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_13_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_13_OFFSET); } +static inline void maestro_wiu_icr_13_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_13_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_14_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_14_OFFSET); } +static inline void maestro_wiu_icr_14_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_14_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_15_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_15_OFFSET); } +static inline void maestro_wiu_icr_15_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_15_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15(val) ((val) << 0) + +#endif + + + +// +// GROUP icu +// + + + +// +// REGISTERS +// + +// ICU control register +#define MAESTRO_ICU_CTRL_OFFSET 0x0 + +// ICU mode register +#define MAESTRO_ICU_MODE_OFFSET 0x1 + +// Island mode register +#define MAESTRO_ISLAND_MODE_OFFSET 0x2 + +// DMU mode register 0 +#define MAESTRO_DMU_MODE_OFFSET 0x3 + + + +// +// REGISTERS FIELDS +// + +// When a new mode corresponding to one of sixteen mode of the island mode table of the ICU is written as mode transition sequence is started to reach the written mode. (access: R/W) +#define MAESTRO_ICU_CTRL_ICU_CTRL_BIT 0 +#define MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH 4 +#define MAESTRO_ICU_CTRL_ICU_CTRL_MASK 0xf +#define MAESTRO_ICU_CTRL_ICU_CTRL_RESET 0x0 + +// Returns the current mode of the ICU when icu_mode_defined is low. (access: R) +#define MAESTRO_ICU_MODE_ICU_MODE_BIT 0 +#define MAESTRO_ICU_MODE_ICU_MODE_WIDTH 4 +#define MAESTRO_ICU_MODE_ICU_MODE_MASK 0xf +#define MAESTRO_ICU_MODE_ICU_MODE_RESET 0xf + +// When high, indicates that the current mode of the ICU is not defined in the mode table of the ICU When low, the value of the current mode is given by the icu_mode bits (access: R) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT 4 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH 1 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_MASK 0x10 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_RESET 0x1 + +// Mode of the island. (access: R) +#define MAESTRO_ISLAND_MODE_ISL_MODE_BIT 0 +#define MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH 2 +#define MAESTRO_ISLAND_MODE_ISL_MODE_MASK 0x3 +#define MAESTRO_ISLAND_MODE_ISL_MODE_RESET 0x0 + +// Mode of the DMU 0. (access: R) +#define MAESTRO_DMU_MODE_ISL_MODE_BIT 0 +#define MAESTRO_DMU_MODE_ISL_MODE_WIDTH 2 +#define MAESTRO_DMU_MODE_ISL_MODE_MASK 0x3 +#define MAESTRO_DMU_MODE_ISL_MODE_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int icu_ctrl :4 ; // When a new mode corresponding to one of sixteen mode of the island mode table of the ICU is written as mode transition sequence is started to reach the written mode. + }; + unsigned int raw; +} __attribute__((packed)) maestro_icu_ctrl_t; + +typedef union { + struct { + unsigned int icu_mode :4 ; // Returns the current mode of the ICU when icu_mode_defined is low. + unsigned int icu_mode_defined:1 ; // When high, indicates that the current mode of the ICU is not defined in the mode table of the ICU When low, the value of the current mode is given by the icu_mode bits + }; + unsigned int raw; +} __attribute__((packed)) maestro_icu_mode_t; + +typedef union { + struct { + unsigned int isl_mode :2 ; // Mode of the island. + }; + unsigned int raw; +} __attribute__((packed)) maestro_island_mode_t; + +typedef union { + struct { + unsigned int isl_mode :2 ; // Mode of the DMU 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dmu_mode_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_icu_ctrl : public vp::reg_8 +{ +public: + inline void icu_ctrl_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_CTRL_ICU_CTRL_BIT, MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH); } + inline uint8_t icu_ctrl_get() { return this->get_field(MAESTRO_ICU_CTRL_ICU_CTRL_BIT, MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH); } +}; + +class vp_maestro_icu_mode : public vp::reg_8 +{ +public: + inline void icu_mode_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_MODE_ICU_MODE_BIT, MAESTRO_ICU_MODE_ICU_MODE_WIDTH); } + inline uint8_t icu_mode_get() { return this->get_field(MAESTRO_ICU_MODE_ICU_MODE_BIT, MAESTRO_ICU_MODE_ICU_MODE_WIDTH); } + inline void icu_mode_defined_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH); } + inline uint8_t icu_mode_defined_get() { return this->get_field(MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH); } +}; + +class vp_maestro_island_mode : public vp::reg_8 +{ +public: + inline void isl_mode_set(uint8_t value) { this->set_field(value, MAESTRO_ISLAND_MODE_ISL_MODE_BIT, MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH); } + inline uint8_t isl_mode_get() { return this->get_field(MAESTRO_ISLAND_MODE_ISL_MODE_BIT, MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH); } +}; + +class vp_maestro_dmu_mode : public vp::reg_8 +{ +public: + inline void isl_mode_set(uint8_t value) { this->set_field(value, MAESTRO_DMU_MODE_ISL_MODE_BIT, MAESTRO_DMU_MODE_ISL_MODE_WIDTH); } + inline uint8_t isl_mode_get() { return this->get_field(MAESTRO_DMU_MODE_ISL_MODE_BIT, MAESTRO_DMU_MODE_ISL_MODE_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int icu_ctrl ; // ICU control register + unsigned int icu_mode ; // ICU mode register + unsigned int island_mode ; // Island mode register + unsigned int dmu_mode ; // DMU mode register 0 +} __attribute__((packed)) maestro_icu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_icu_ctrl_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ICU_CTRL_OFFSET); } +static inline void maestro_icu_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ICU_CTRL_OFFSET, value); } + +static inline uint32_t maestro_icu_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ICU_MODE_OFFSET); } +static inline void maestro_icu_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ICU_MODE_OFFSET, value); } + +static inline uint32_t maestro_island_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ISLAND_MODE_OFFSET); } +static inline void maestro_island_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ISLAND_MODE_OFFSET, value); } + +static inline uint32_t maestro_dmu_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DMU_MODE_OFFSET); } +static inline void maestro_dmu_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DMU_MODE_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_ICU_CTRL_ICU_CTRL_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL(val) ((val) << 0) + +#define MAESTRO_ICU_MODE_ICU_MODE_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE(val) ((val) << 0) + +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED(val) ((val) << 4) + +#define MAESTRO_ISLAND_MODE_ISL_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE(val) ((val) << 0) + +#define MAESTRO_DMU_MODE_ISL_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE(val) ((val) << 0) + +#endif + + + +// +// CUSTOM FIELDS +// +#define MAESTRO_ICU_SUPPLY_EXT 0x0 +#define MAESTRO_ICU_SUPPLY_RET 0x1 +#define MAESTRO_ICU_SUPPLY_CKOFF 0x2 +#define MAESTRO_ICU_SUPPLY_ON 0x3 +#define MAESTRO_ICU_REGU_NONE 0x7 +#define MAESTRO_ICU_REGU_OFF 0x0 +#define MAESTRO_ICU_REGU_RV 0x1 +#define MAESTRO_ICU_REGU_LV 0x2 +#define MAESTRO_ICU_REGU_MV 0x3 +#define MAESTRO_ICU_REGU_NV 0x4 +#define MAESTRO_ICU_CLK_FNONE 0x7 +#define MAESTRO_ICU_CLK_FOFF 0x0 +#define MAESTRO_ICU_CLK_LF 0x1 +#define MAESTRO_ICU_CLK_MF 0x2 +#define MAESTRO_ICU_CLK_NF 0x3 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/maestro/maestro_v3.h b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v3.h new file mode 100644 index 0000000..0bca3ac --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/maestro/maestro_v3.h @@ -0,0 +1,1545 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_MAESTRO_MAESTRO_V3_H__ +#define __INCLUDE_ARCHI_MAESTRO_MAESTRO_V3_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// PICL control register +#define MAESTRO_DLC_PCTRL_OFFSET 0x0 + +// PICL data read register +#define MAESTRO_PRDATA_OFFSET 0x4 + +// Status register +#define MAESTRO_DLC_SR_OFFSET 0x8 + +// Interrupt Mask register +#define MAESTRO_DLC_IMR_OFFSET 0xc + +// Interrupt flag register +#define MAESTRO_DLC_IFR_OFFSET 0x10 + +// icu_ok interrupt flag register +#define MAESTRO_DLC_IOIFR_OFFSET 0x14 + +// icu_delayed interrupt flag register +#define MAESTRO_DLC_IDIFR_OFFSET 0x18 + +// icu_mode_changed interrupt flags register +#define MAESTRO_DLC_IMCIFR_OFFSET 0x1c + + + +// +// REGISTERS FIELDS +// + +// Start of PICL access sequence. A rising edge of the start bit starts a PICL picl transfer. Start bit remains high until the end of the sequence, which means that no new access can be performed if an access is on going. (access: R/W) +#define MAESTRO_DLC_PCTRL_START_BIT 0 +#define MAESTRO_DLC_PCTRL_START_WIDTH 1 +#define MAESTRO_DLC_PCTRL_START_MASK 0x1 +#define MAESTRO_DLC_PCTRL_START_RESET 0x0 + +// Address of the transfer on the PICL bus. (access: R/W) +#define MAESTRO_DLC_PCTRL_PADDR_BIT 1 +#define MAESTRO_DLC_PCTRL_PADDR_WIDTH 14 +#define MAESTRO_DLC_PCTRL_PADDR_MASK 0x7ffe +#define MAESTRO_DLC_PCTRL_PADDR_RESET 0x0 + +// Direction of the transfer on the PICL bus. dir = 1 means read operation, dir = 0 means write operation. (access: R/W) +#define MAESTRO_DLC_PCTRL_DIR_BIT 15 +#define MAESTRO_DLC_PCTRL_DIR_WIDTH 1 +#define MAESTRO_DLC_PCTRL_DIR_MASK 0x8000 +#define MAESTRO_DLC_PCTRL_DIR_RESET 0x0 + +// Data to write on the PICL bus. (access: R/W) +#define MAESTRO_DLC_PCTRL_PWDATA_BIT 16 +#define MAESTRO_DLC_PCTRL_PWDATA_WIDTH 16 +#define MAESTRO_DLC_PCTRL_PWDATA_MASK 0xffff0000 +#define MAESTRO_DLC_PCTRL_PWDATA_RESET 0x0 + +// Data read on the PICL bus. This data is valid after a PICL read operation, when the picl_busy bit of the DLC_SR register becomes low. (access: R) +#define MAESTRO_PRDATA_PRDATA_BIT 0 +#define MAESTRO_PRDATA_PRDATA_WIDTH 8 +#define MAESTRO_PRDATA_PRDATA_MASK 0xff +#define MAESTRO_PRDATA_PRDATA_RESET 0x0 + +// This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. (access: R) +#define MAESTRO_DLC_SR_PICL_BUSY_BIT 0 +#define MAESTRO_DLC_SR_PICL_BUSY_WIDTH 1 +#define MAESTRO_DLC_SR_PICL_BUSY_MASK 0x1 +#define MAESTRO_DLC_SR_PICL_BUSY_RESET 0x0 + +// This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. (access: R) +#define MAESTRO_DLC_SR_SCU_BUSY_BIT 1 +#define MAESTRO_DLC_SR_SCU_BUSY_WIDTH 1 +#define MAESTRO_DLC_SR_SCU_BUSY_MASK 0x2 +#define MAESTRO_DLC_SR_SCU_BUSY_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_BIT 0 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_MASK 0x1 +#define MAESTRO_DLC_IMR_ICU_OK_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT 1 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_MASK 0x2 +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT 2 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK 0x4 +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_BIT 3 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_MASK 0x8 +#define MAESTRO_DLC_IMR_PICL_OK_MASK_RESET 0x0 + +// A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. (access: R/W) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_BIT 4 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH 1 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_MASK 0x10 +#define MAESTRO_DLC_IMR_SCU_OK_MASK_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IOIFR register is set. Cleared when reading DCL_IOIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT 0 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_MASK 0x1 +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IDIFR register is set. Cleared when reading DCL_IDIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT 1 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_MASK 0x2 +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_RESET 0x0 + +// Set to 1 when at least one of the bit of the DLC_IMCIFR register is set. Cleared when reading DCL_IMCIFR register. (access: R) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT 2 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK 0x4 +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_RESET 0x0 + +// Set to 1 when PICL transfer is finish. Cleared writting 1 to the bit 3 of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT 3 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_MASK 0x8 +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_RESET 0x0 + +// Set to 1 when SCU sequence is finished. Cleared when writting 1 to the bit 4 of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT 4 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH 1 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_MASK 0x10 +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_ok_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_ok_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT 1 +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_delayed_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_delayed_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT 1 +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_RESET 0x0 + +// Bit set to 1 when a rising edge of the signal i_icu_mode_changed_irq[ ] occurs. A read this register clears the register and the bit icu_mode_changed_flag of the DLC_IFR register. (access: R) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT 1 +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH 31 +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_MASK 0xfffffffe +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int start :1 ; // Start of PICL access sequence. A rising edge of the start bit starts a PICL picl transfer. Start bit remains high until the end of the sequence, which means that no new access can be performed if an access is on going. + unsigned int paddr :14; // Address of the transfer on the PICL bus. + unsigned int dir :1 ; // Direction of the transfer on the PICL bus. dir = 1 means read operation, dir = 0 means write operation. + unsigned int pwdata :16; // Data to write on the PICL bus. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_pctrl_t; + +typedef union { + struct { + unsigned int prdata :8 ; // Data read on the PICL bus. This data is valid after a PICL read operation, when the picl_busy bit of the DLC_SR register becomes low. + }; + unsigned int raw; +} __attribute__((packed)) maestro_prdata_t; + +typedef union { + struct { + unsigned int picl_busy :1 ; // This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. + unsigned int scu_busy :1 ; // This bit is set to 1 if when a SCU sequence is on going. This bit is cleared at the end of the sequence. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_sr_t; + +typedef union { + struct { + unsigned int icu_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int icu_delayed_mask:1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int icu_mode_changed_mask:1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int picl_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + unsigned int scu_ok_mask :1 ; // A read return the current value of the mask. Writing 1 set the mask, writing 0 clears the mask. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_imr_t; + +typedef union { + struct { + unsigned int icu_ok_flag :1 ; // Set to 1 when at least one of the bit of the DLC_IOIFR register is set. Cleared when reading DCL_IOIFR register. + unsigned int icu_delayed_flag:1 ; // Set to 1 when at least one of the bit of the DLC_IDIFR register is set. Cleared when reading DCL_IDIFR register. + unsigned int icu_mode_changed_flag:1 ; // Set to 1 when at least one of the bit of the DLC_IMCIFR register is set. Cleared when reading DCL_IMCIFR register. + unsigned int picl_ok_flag :1 ; // Set to 1 when PICL transfer is finish. Cleared writting 1 to the bit 3 of the DLC_IFR register. + unsigned int scu_ok_flag :1 ; // Set to 1 when SCU sequence is finished. Cleared when writting 1 to the bit 4 of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_ifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_ok_flags :31; // Bit set to 1 when a rising edge of the signal i_icu_ok_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_ok_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_ioifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_delayed_flags:31; // Bit set to 1 when a rising edge of the signal i_icu_delayed_irq[ ] occurs and MSP is requester of the change mode order of the ICU . A read this register clears the register and the bit icu_delayed_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_idifr_t; + +typedef union { + struct { + unsigned int padding0:1 ; + unsigned int icu_mode_changed_flags:31; // Bit set to 1 when a rising edge of the signal i_icu_mode_changed_irq[ ] occurs. A read this register clears the register and the bit icu_mode_changed_flag of the DLC_IFR register. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dlc_imcifr_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_dlc_pctrl : public vp::reg_32 +{ +public: + inline void start_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_START_BIT, MAESTRO_DLC_PCTRL_START_WIDTH); } + inline uint32_t start_get() { return this->get_field(MAESTRO_DLC_PCTRL_START_BIT, MAESTRO_DLC_PCTRL_START_WIDTH); } + inline void paddr_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_PADDR_BIT, MAESTRO_DLC_PCTRL_PADDR_WIDTH); } + inline uint32_t paddr_get() { return this->get_field(MAESTRO_DLC_PCTRL_PADDR_BIT, MAESTRO_DLC_PCTRL_PADDR_WIDTH); } + inline void dir_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_DIR_BIT, MAESTRO_DLC_PCTRL_DIR_WIDTH); } + inline uint32_t dir_get() { return this->get_field(MAESTRO_DLC_PCTRL_DIR_BIT, MAESTRO_DLC_PCTRL_DIR_WIDTH); } + inline void pwdata_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_PCTRL_PWDATA_BIT, MAESTRO_DLC_PCTRL_PWDATA_WIDTH); } + inline uint32_t pwdata_get() { return this->get_field(MAESTRO_DLC_PCTRL_PWDATA_BIT, MAESTRO_DLC_PCTRL_PWDATA_WIDTH); } +}; + +class vp_maestro_prdata : public vp::reg_32 +{ +public: + inline void prdata_set(uint32_t value) { this->set_field(value, MAESTRO_PRDATA_PRDATA_BIT, MAESTRO_PRDATA_PRDATA_WIDTH); } + inline uint32_t prdata_get() { return this->get_field(MAESTRO_PRDATA_PRDATA_BIT, MAESTRO_PRDATA_PRDATA_WIDTH); } +}; + +class vp_maestro_dlc_sr : public vp::reg_32 +{ +public: + inline void picl_busy_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_SR_PICL_BUSY_BIT, MAESTRO_DLC_SR_PICL_BUSY_WIDTH); } + inline uint32_t picl_busy_get() { return this->get_field(MAESTRO_DLC_SR_PICL_BUSY_BIT, MAESTRO_DLC_SR_PICL_BUSY_WIDTH); } + inline void scu_busy_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_SR_SCU_BUSY_BIT, MAESTRO_DLC_SR_SCU_BUSY_WIDTH); } + inline uint32_t scu_busy_get() { return this->get_field(MAESTRO_DLC_SR_SCU_BUSY_BIT, MAESTRO_DLC_SR_SCU_BUSY_WIDTH); } +}; + +class vp_maestro_dlc_imr : public vp::reg_32 +{ +public: + inline void icu_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_OK_MASK_BIT, MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH); } + inline uint32_t icu_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_OK_MASK_BIT, MAESTRO_DLC_IMR_ICU_OK_MASK_WIDTH); } + inline void icu_delayed_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH); } + inline uint32_t icu_delayed_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_DELAYED_MASK_BIT, MAESTRO_DLC_IMR_ICU_DELAYED_MASK_WIDTH); } + inline void icu_mode_changed_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH); } + inline uint32_t icu_mode_changed_mask_get() { return this->get_field(MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_BIT, MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_WIDTH); } + inline void picl_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_PICL_OK_MASK_BIT, MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH); } + inline uint32_t picl_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_PICL_OK_MASK_BIT, MAESTRO_DLC_IMR_PICL_OK_MASK_WIDTH); } + inline void scu_ok_mask_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMR_SCU_OK_MASK_BIT, MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH); } + inline uint32_t scu_ok_mask_get() { return this->get_field(MAESTRO_DLC_IMR_SCU_OK_MASK_BIT, MAESTRO_DLC_IMR_SCU_OK_MASK_WIDTH); } +}; + +class vp_maestro_dlc_ifr : public vp::reg_32 +{ +public: + inline void icu_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT, MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH); } + inline uint32_t icu_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_OK_FLAG_BIT, MAESTRO_DLC_IFR_ICU_OK_FLAG_WIDTH); } + inline void icu_delayed_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH); } + inline uint32_t icu_delayed_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_WIDTH); } + inline void icu_mode_changed_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH); } + inline uint32_t icu_mode_changed_flag_get() { return this->get_field(MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_BIT, MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_WIDTH); } + inline void picl_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT, MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH); } + inline uint32_t picl_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_PICL_OK_FLAG_BIT, MAESTRO_DLC_IFR_PICL_OK_FLAG_WIDTH); } + inline void scu_ok_flag_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT, MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH); } + inline uint32_t scu_ok_flag_get() { return this->get_field(MAESTRO_DLC_IFR_SCU_OK_FLAG_BIT, MAESTRO_DLC_IFR_SCU_OK_FLAG_WIDTH); } +}; + +class vp_maestro_dlc_ioifr : public vp::reg_32 +{ +public: + inline void icu_ok_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH); } + inline uint32_t icu_ok_flags_get() { return this->get_field(MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_BIT, MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_WIDTH); } +}; + +class vp_maestro_dlc_idifr : public vp::reg_32 +{ +public: + inline void icu_delayed_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH); } + inline uint32_t icu_delayed_flags_get() { return this->get_field(MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_BIT, MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_WIDTH); } +}; + +class vp_maestro_dlc_imcifr : public vp::reg_32 +{ +public: + inline void icu_mode_changed_flags_set(uint32_t value) { this->set_field(value, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH); } + inline uint32_t icu_mode_changed_flags_get() { return this->get_field(MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_BIT, MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int dlc_pctrl ; // PICL control register + unsigned int prdata ; // PICL data read register + unsigned int dlc_sr ; // Status register + unsigned int dlc_imr ; // Interrupt Mask register + unsigned int dlc_ifr ; // Interrupt flag register + unsigned int dlc_ioifr ; // icu_ok interrupt flag register + unsigned int dlc_idifr ; // icu_delayed interrupt flag register + unsigned int dlc_imcifr ; // icu_mode_changed interrupt flags register +} __attribute__((packed)) maestro_maestro_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_dlc_pctrl_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_PCTRL_OFFSET); } +static inline void maestro_dlc_pctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_PCTRL_OFFSET, value); } + +static inline uint32_t maestro_prdata_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_PRDATA_OFFSET); } +static inline void maestro_prdata_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_PRDATA_OFFSET, value); } + +static inline uint32_t maestro_dlc_sr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_SR_OFFSET); } +static inline void maestro_dlc_sr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_SR_OFFSET, value); } + +static inline uint32_t maestro_dlc_imr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IMR_OFFSET); } +static inline void maestro_dlc_imr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IMR_OFFSET, value); } + +static inline uint32_t maestro_dlc_ifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IFR_OFFSET); } +static inline void maestro_dlc_ifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_ioifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IOIFR_OFFSET); } +static inline void maestro_dlc_ioifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IOIFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_idifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IDIFR_OFFSET); } +static inline void maestro_dlc_idifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IDIFR_OFFSET, value); } + +static inline uint32_t maestro_dlc_imcifr_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DLC_IMCIFR_OFFSET); } +static inline void maestro_dlc_imcifr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DLC_IMCIFR_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_DLC_PCTRL_START_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_PCTRL_START_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_PCTRL_START_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_PCTRL_START(val) ((val) << 0) + +#define MAESTRO_DLC_PCTRL_PADDR_GET(value) (ARCHI_BEXTRACTU((value),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR_GETS(value) (ARCHI_BEXTRACT((value),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR_SET(value,field) (ARCHI_BINSERT((value),(field),14,1)) +#define MAESTRO_DLC_PCTRL_PADDR(val) ((val) << 1) + +#define MAESTRO_DLC_PCTRL_DIR_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define MAESTRO_DLC_PCTRL_DIR_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define MAESTRO_DLC_PCTRL_DIR_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define MAESTRO_DLC_PCTRL_DIR(val) ((val) << 15) + +#define MAESTRO_DLC_PCTRL_PWDATA_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define MAESTRO_DLC_PCTRL_PWDATA(val) ((val) << 16) + +#define MAESTRO_PRDATA_PRDATA_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_PRDATA_PRDATA_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_PRDATA_PRDATA_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_PRDATA_PRDATA(val) ((val) << 0) + +#define MAESTRO_DLC_SR_PICL_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_SR_PICL_BUSY(val) ((val) << 0) + +#define MAESTRO_DLC_SR_SCU_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_SR_SCU_BUSY(val) ((val) << 1) + +#define MAESTRO_DLC_IMR_ICU_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_IMR_ICU_OK_MASK(val) ((val) << 0) + +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_IMR_ICU_DELAYED_MASK(val) ((val) << 1) + +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define MAESTRO_DLC_IMR_ICU_MODE_CHANGED_MASK(val) ((val) << 2) + +#define MAESTRO_DLC_IMR_PICL_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define MAESTRO_DLC_IMR_PICL_OK_MASK(val) ((val) << 3) + +#define MAESTRO_DLC_IMR_SCU_OK_MASK_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_DLC_IMR_SCU_OK_MASK(val) ((val) << 4) + +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define MAESTRO_DLC_IFR_ICU_OK_FLAG(val) ((val) << 0) + +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define MAESTRO_DLC_IFR_ICU_DELAYED_FLAG(val) ((val) << 1) + +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define MAESTRO_DLC_IFR_ICU_MODE_CHANGED_FLAG(val) ((val) << 2) + +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define MAESTRO_DLC_IFR_PICL_OK_FLAG(val) ((val) << 3) + +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_DLC_IFR_SCU_OK_FLAG(val) ((val) << 4) + +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IOIFR_ICU_OK_FLAGS(val) ((val) << 1) + +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IDIFR_ICU_DELAYED_FLAGS(val) ((val) << 1) + +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_GET(value) (ARCHI_BEXTRACTU((value),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_GETS(value) (ARCHI_BEXTRACT((value),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS_SET(value,field) (ARCHI_BINSERT((value),(field),31,1)) +#define MAESTRO_DLC_IMCIFR_ICU_MODE_CHANGED_FLAGS(val) ((val) << 1) + +#endif + + + +// +// GROUP dlc +// + +#define MAESTRO_DLC_OFFSET 0x0 + + + +// +// REGISTERS +// + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { +} __attribute__((packed)) maestro_dlc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + + + +// +// GROUP wiu +// + +#define MAESTRO_WIU_OFFSET 0x1 + + + +// +// REGISTERS +// + +// Interrupt Sequence Processing Mask registers +#define MAESTRO_WIU_ISPMR_0_OFFSET 0x0 + +// Interrupt Sequence Processing Mask registers +#define MAESTRO_WIU_ISPMR_1_OFFSET 0x1 + +// Interrupt Flag register +#define MAESTRO_WIU_IFR_0_OFFSET 0x2 + +// Interrupt Flag register +#define MAESTRO_WIU_IFR_1_OFFSET 0x3 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_0_OFFSET 0x4 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_1_OFFSET 0x5 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_2_OFFSET 0x6 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_3_OFFSET 0x7 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_4_OFFSET 0x8 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_5_OFFSET 0x9 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_6_OFFSET 0xa + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_7_OFFSET 0xb + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_8_OFFSET 0xc + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_9_OFFSET 0xd + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_10_OFFSET 0xe + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_11_OFFSET 0xf + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_12_OFFSET 0x10 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_13_OFFSET 0x11 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_14_OFFSET 0x12 + +// Interrupt Control registers +#define MAESTRO_WIU_ICR_15_OFFSET 0x13 + + + +// +// REGISTERS FIELDS +// + +// A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] (access: R/W) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT 0 +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH 8 +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_MASK 0xff +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_RESET 0x0 + +// A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] (access: R/W) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT 0 +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH 8 +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_MASK 0xff +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_RESET 0x0 + +// Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. (access: R/W) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT 0 +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH 8 +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_MASK 0xff +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_RESET 0x0 + +// Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. (access: R/W) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT 0 +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH 8 +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_MASK 0xff +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT 0 +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH 5 +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_MASK 0x1f +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT 0 +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH 5 +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_MASK 0x1f +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT 0 +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH 5 +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_MASK 0x1f +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT 0 +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH 5 +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_MASK 0x1f +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT 0 +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH 5 +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_MASK 0x1f +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT 0 +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH 5 +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_MASK 0x1f +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT 0 +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH 5 +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_MASK 0x1f +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT 0 +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH 5 +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_MASK 0x1f +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT 0 +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH 5 +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_MASK 0x1f +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT 0 +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH 5 +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_MASK 0x1f +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT 0 +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH 5 +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_MASK 0x1f +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT 0 +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH 5 +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_MASK 0x1f +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT 0 +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH 5 +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_MASK 0x1f +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT 0 +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH 5 +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_MASK 0x1f +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT 0 +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH 5 +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_MASK 0x1f +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_RESET 0x0 + +// Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active (access: R/W) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT 0 +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH 5 +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_MASK 0x1f +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int mask_modechg_en_irq:8 ; // A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ispmr_0_t; + +typedef union { + struct { + unsigned int mask_modechg_en_irq:8 ; // A read of this register return the value of the mask. Writing 1 to the bit , set the mask of the interrupt i_irq[ ] + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ispmr_1_t; + +typedef union { + struct { + unsigned int flag_irq :8 ; // Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ifr_0_t; + +typedef union { + struct { + unsigned int flag_irq :8 ; // Bit is set when a rising egde of the signal i_irq [ 8 * + ] occurs or when writing the bit to 1. Bit is cleared when the associated SCU sequence is finished or when writing 0 to the bit of the WIU_ISPMR_m register or when writing the bit to 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_ifr_1_t; + +typedef union { + struct { + unsigned int seq_sel_irq_0 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_0_t; + +typedef union { + struct { + unsigned int seq_sel_irq_1 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_1_t; + +typedef union { + struct { + unsigned int seq_sel_irq_2 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_2_t; + +typedef union { + struct { + unsigned int seq_sel_irq_3 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_3_t; + +typedef union { + struct { + unsigned int seq_sel_irq_4 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_4_t; + +typedef union { + struct { + unsigned int seq_sel_irq_5 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_5_t; + +typedef union { + struct { + unsigned int seq_sel_irq_6 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_6_t; + +typedef union { + struct { + unsigned int seq_sel_irq_7 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_7_t; + +typedef union { + struct { + unsigned int seq_sel_irq_8 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_8_t; + +typedef union { + struct { + unsigned int seq_sel_irq_9 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_9_t; + +typedef union { + struct { + unsigned int seq_sel_irq_10 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_10_t; + +typedef union { + struct { + unsigned int seq_sel_irq_11 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_11_t; + +typedef union { + struct { + unsigned int seq_sel_irq_12 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_12_t; + +typedef union { + struct { + unsigned int seq_sel_irq_13 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_13_t; + +typedef union { + struct { + unsigned int seq_sel_irq_14 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_14_t; + +typedef union { + struct { + unsigned int seq_sel_irq_15 :5 ; // Defines the sequence which has to be executed when the interrupt i_irq[

] becomes active + }; + unsigned int raw; +} __attribute__((packed)) maestro_wiu_icr_15_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_wiu_ispmr_0 : public vp::reg_8 +{ +public: + inline void mask_modechg_en_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH); } + inline uint8_t mask_modechg_en_irq_get() { return this->get_field(MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ispmr_1 : public vp::reg_8 +{ +public: + inline void mask_modechg_en_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH); } + inline uint8_t mask_modechg_en_irq_get() { return this->get_field(MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_BIT, MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ifr_0 : public vp::reg_8 +{ +public: + inline void flag_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH); } + inline uint8_t flag_irq_get() { return this->get_field(MAESTRO_WIU_IFR_0_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_0_FLAG_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_ifr_1 : public vp::reg_8 +{ +public: + inline void flag_irq_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH); } + inline uint8_t flag_irq_get() { return this->get_field(MAESTRO_WIU_IFR_1_FLAG_IRQ_BIT, MAESTRO_WIU_IFR_1_FLAG_IRQ_WIDTH); } +}; + +class vp_maestro_wiu_icr_0 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_0_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH); } + inline uint8_t seq_sel_irq_0_get() { return this->get_field(MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_BIT, MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_WIDTH); } +}; + +class vp_maestro_wiu_icr_1 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_1_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH); } + inline uint8_t seq_sel_irq_1_get() { return this->get_field(MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_BIT, MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_WIDTH); } +}; + +class vp_maestro_wiu_icr_2 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_2_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH); } + inline uint8_t seq_sel_irq_2_get() { return this->get_field(MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_BIT, MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_WIDTH); } +}; + +class vp_maestro_wiu_icr_3 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_3_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH); } + inline uint8_t seq_sel_irq_3_get() { return this->get_field(MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_BIT, MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_WIDTH); } +}; + +class vp_maestro_wiu_icr_4 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_4_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH); } + inline uint8_t seq_sel_irq_4_get() { return this->get_field(MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_BIT, MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_WIDTH); } +}; + +class vp_maestro_wiu_icr_5 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_5_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH); } + inline uint8_t seq_sel_irq_5_get() { return this->get_field(MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_BIT, MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_WIDTH); } +}; + +class vp_maestro_wiu_icr_6 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_6_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH); } + inline uint8_t seq_sel_irq_6_get() { return this->get_field(MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_BIT, MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_WIDTH); } +}; + +class vp_maestro_wiu_icr_7 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_7_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH); } + inline uint8_t seq_sel_irq_7_get() { return this->get_field(MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_BIT, MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_WIDTH); } +}; + +class vp_maestro_wiu_icr_8 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_8_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH); } + inline uint8_t seq_sel_irq_8_get() { return this->get_field(MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_BIT, MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_WIDTH); } +}; + +class vp_maestro_wiu_icr_9 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_9_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH); } + inline uint8_t seq_sel_irq_9_get() { return this->get_field(MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_BIT, MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_WIDTH); } +}; + +class vp_maestro_wiu_icr_10 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_10_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH); } + inline uint8_t seq_sel_irq_10_get() { return this->get_field(MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_BIT, MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_WIDTH); } +}; + +class vp_maestro_wiu_icr_11 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_11_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH); } + inline uint8_t seq_sel_irq_11_get() { return this->get_field(MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_BIT, MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_WIDTH); } +}; + +class vp_maestro_wiu_icr_12 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_12_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH); } + inline uint8_t seq_sel_irq_12_get() { return this->get_field(MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_BIT, MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_WIDTH); } +}; + +class vp_maestro_wiu_icr_13 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_13_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH); } + inline uint8_t seq_sel_irq_13_get() { return this->get_field(MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_BIT, MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_WIDTH); } +}; + +class vp_maestro_wiu_icr_14 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_14_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH); } + inline uint8_t seq_sel_irq_14_get() { return this->get_field(MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_BIT, MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_WIDTH); } +}; + +class vp_maestro_wiu_icr_15 : public vp::reg_8 +{ +public: + inline void seq_sel_irq_15_set(uint8_t value) { this->set_field(value, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH); } + inline uint8_t seq_sel_irq_15_get() { return this->get_field(MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_BIT, MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int wiu_ispmr_0 ; // Interrupt Sequence Processing Mask registers + unsigned int wiu_ispmr_1 ; // Interrupt Sequence Processing Mask registers + unsigned int wiu_ifr_0 ; // Interrupt Flag register + unsigned int wiu_ifr_1 ; // Interrupt Flag register + unsigned int wiu_icr_0 ; // Interrupt Control registers + unsigned int wiu_icr_1 ; // Interrupt Control registers + unsigned int wiu_icr_2 ; // Interrupt Control registers + unsigned int wiu_icr_3 ; // Interrupt Control registers + unsigned int wiu_icr_4 ; // Interrupt Control registers + unsigned int wiu_icr_5 ; // Interrupt Control registers + unsigned int wiu_icr_6 ; // Interrupt Control registers + unsigned int wiu_icr_7 ; // Interrupt Control registers + unsigned int wiu_icr_8 ; // Interrupt Control registers + unsigned int wiu_icr_9 ; // Interrupt Control registers + unsigned int wiu_icr_10 ; // Interrupt Control registers + unsigned int wiu_icr_11 ; // Interrupt Control registers + unsigned int wiu_icr_12 ; // Interrupt Control registers + unsigned int wiu_icr_13 ; // Interrupt Control registers + unsigned int wiu_icr_14 ; // Interrupt Control registers + unsigned int wiu_icr_15 ; // Interrupt Control registers +} __attribute__((packed)) maestro_wiu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_wiu_ispmr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ISPMR_0_OFFSET); } +static inline void maestro_wiu_ispmr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ISPMR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_ispmr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ISPMR_1_OFFSET); } +static inline void maestro_wiu_ispmr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ISPMR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_ifr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_IFR_0_OFFSET); } +static inline void maestro_wiu_ifr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_IFR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_ifr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_IFR_1_OFFSET); } +static inline void maestro_wiu_ifr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_IFR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_0_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_0_OFFSET); } +static inline void maestro_wiu_icr_0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_0_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_1_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_1_OFFSET); } +static inline void maestro_wiu_icr_1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_1_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_2_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_2_OFFSET); } +static inline void maestro_wiu_icr_2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_2_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_3_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_3_OFFSET); } +static inline void maestro_wiu_icr_3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_3_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_4_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_4_OFFSET); } +static inline void maestro_wiu_icr_4_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_4_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_5_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_5_OFFSET); } +static inline void maestro_wiu_icr_5_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_5_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_6_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_6_OFFSET); } +static inline void maestro_wiu_icr_6_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_6_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_7_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_7_OFFSET); } +static inline void maestro_wiu_icr_7_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_7_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_8_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_8_OFFSET); } +static inline void maestro_wiu_icr_8_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_8_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_9_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_9_OFFSET); } +static inline void maestro_wiu_icr_9_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_9_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_10_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_10_OFFSET); } +static inline void maestro_wiu_icr_10_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_10_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_11_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_11_OFFSET); } +static inline void maestro_wiu_icr_11_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_11_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_12_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_12_OFFSET); } +static inline void maestro_wiu_icr_12_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_12_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_13_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_13_OFFSET); } +static inline void maestro_wiu_icr_13_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_13_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_14_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_14_OFFSET); } +static inline void maestro_wiu_icr_14_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_14_OFFSET, value); } + +static inline uint32_t maestro_wiu_icr_15_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_WIU_ICR_15_OFFSET); } +static inline void maestro_wiu_icr_15_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_WIU_ICR_15_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_ISPMR_0_MASK_MODECHG_EN_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_ISPMR_1_MASK_MODECHG_EN_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_IFR_0_FLAG_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define MAESTRO_WIU_IFR_1_FLAG_IRQ(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_0_SEQ_SEL_IRQ_0(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_1_SEQ_SEL_IRQ_1(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_2_SEQ_SEL_IRQ_2(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_3_SEQ_SEL_IRQ_3(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_4_SEQ_SEL_IRQ_4(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_5_SEQ_SEL_IRQ_5(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_6_SEQ_SEL_IRQ_6(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_7_SEQ_SEL_IRQ_7(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_8_SEQ_SEL_IRQ_8(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_9_SEQ_SEL_IRQ_9(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_10_SEQ_SEL_IRQ_10(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_11_SEQ_SEL_IRQ_11(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_12_SEQ_SEL_IRQ_12(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_13_SEQ_SEL_IRQ_13(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_14_SEQ_SEL_IRQ_14(val) ((val) << 0) + +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define MAESTRO_WIU_ICR_15_SEQ_SEL_IRQ_15(val) ((val) << 0) + +#endif + + + +// +// GROUP icu +// + + + +// +// REGISTERS +// + +// ICU control register +#define MAESTRO_ICU_CTRL_OFFSET 0x0 + +// ICU mode register +#define MAESTRO_ICU_MODE_OFFSET 0x1 + +// Island mode register +#define MAESTRO_ISLAND_MODE_OFFSET 0x2 + +// DMU mode register 0 +#define MAESTRO_DMU_MODE_OFFSET 0x3 + + + +// +// REGISTERS FIELDS +// + +// When a new mode corresponding to one of sixteen mode of the island mode table of the ICU is written as mode transition sequence is started to reach the written mode. (access: R/W) +#define MAESTRO_ICU_CTRL_ICU_CTRL_BIT 0 +#define MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH 4 +#define MAESTRO_ICU_CTRL_ICU_CTRL_MASK 0xf +#define MAESTRO_ICU_CTRL_ICU_CTRL_RESET 0x0 + +// Returns the current mode of the ICU when icu_mode_defined is low. (access: R) +#define MAESTRO_ICU_MODE_ICU_MODE_BIT 0 +#define MAESTRO_ICU_MODE_ICU_MODE_WIDTH 4 +#define MAESTRO_ICU_MODE_ICU_MODE_MASK 0xf +#define MAESTRO_ICU_MODE_ICU_MODE_RESET 0xf + +// When high, indicates that the current mode of the ICU is not defined in the mode table of the ICU When low, the value of the current mode is given by the icu_mode bits (access: R) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT 4 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH 1 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_MASK 0x10 +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_RESET 0x1 + +// Mode of the island. (access: R) +#define MAESTRO_ISLAND_MODE_ISL_MODE_BIT 0 +#define MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH 2 +#define MAESTRO_ISLAND_MODE_ISL_MODE_MASK 0x3 +#define MAESTRO_ISLAND_MODE_ISL_MODE_RESET 0x0 + +// Mode of the DMU 0. (access: R) +#define MAESTRO_DMU_MODE_ISL_MODE_BIT 0 +#define MAESTRO_DMU_MODE_ISL_MODE_WIDTH 2 +#define MAESTRO_DMU_MODE_ISL_MODE_MASK 0x3 +#define MAESTRO_DMU_MODE_ISL_MODE_RESET 0x0 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int icu_ctrl :4 ; // When a new mode corresponding to one of sixteen mode of the island mode table of the ICU is written as mode transition sequence is started to reach the written mode. + }; + unsigned int raw; +} __attribute__((packed)) maestro_icu_ctrl_t; + +typedef union { + struct { + unsigned int icu_mode :4 ; // Returns the current mode of the ICU when icu_mode_defined is low. + unsigned int icu_mode_defined:1 ; // When high, indicates that the current mode of the ICU is not defined in the mode table of the ICU When low, the value of the current mode is given by the icu_mode bits + }; + unsigned int raw; +} __attribute__((packed)) maestro_icu_mode_t; + +typedef union { + struct { + unsigned int isl_mode :2 ; // Mode of the island. + }; + unsigned int raw; +} __attribute__((packed)) maestro_island_mode_t; + +typedef union { + struct { + unsigned int isl_mode :2 ; // Mode of the DMU 0. + }; + unsigned int raw; +} __attribute__((packed)) maestro_dmu_mode_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_maestro_icu_ctrl : public vp::reg_8 +{ +public: + inline void icu_ctrl_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_CTRL_ICU_CTRL_BIT, MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH); } + inline uint8_t icu_ctrl_get() { return this->get_field(MAESTRO_ICU_CTRL_ICU_CTRL_BIT, MAESTRO_ICU_CTRL_ICU_CTRL_WIDTH); } +}; + +class vp_maestro_icu_mode : public vp::reg_8 +{ +public: + inline void icu_mode_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_MODE_ICU_MODE_BIT, MAESTRO_ICU_MODE_ICU_MODE_WIDTH); } + inline uint8_t icu_mode_get() { return this->get_field(MAESTRO_ICU_MODE_ICU_MODE_BIT, MAESTRO_ICU_MODE_ICU_MODE_WIDTH); } + inline void icu_mode_defined_set(uint8_t value) { this->set_field(value, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH); } + inline uint8_t icu_mode_defined_get() { return this->get_field(MAESTRO_ICU_MODE_ICU_MODE_DEFINED_BIT, MAESTRO_ICU_MODE_ICU_MODE_DEFINED_WIDTH); } +}; + +class vp_maestro_island_mode : public vp::reg_8 +{ +public: + inline void isl_mode_set(uint8_t value) { this->set_field(value, MAESTRO_ISLAND_MODE_ISL_MODE_BIT, MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH); } + inline uint8_t isl_mode_get() { return this->get_field(MAESTRO_ISLAND_MODE_ISL_MODE_BIT, MAESTRO_ISLAND_MODE_ISL_MODE_WIDTH); } +}; + +class vp_maestro_dmu_mode : public vp::reg_8 +{ +public: + inline void isl_mode_set(uint8_t value) { this->set_field(value, MAESTRO_DMU_MODE_ISL_MODE_BIT, MAESTRO_DMU_MODE_ISL_MODE_WIDTH); } + inline uint8_t isl_mode_get() { return this->get_field(MAESTRO_DMU_MODE_ISL_MODE_BIT, MAESTRO_DMU_MODE_ISL_MODE_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int icu_ctrl ; // ICU control register + unsigned int icu_mode ; // ICU mode register + unsigned int island_mode ; // Island mode register + unsigned int dmu_mode ; // DMU mode register 0 +} __attribute__((packed)) maestro_icu_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t maestro_icu_ctrl_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ICU_CTRL_OFFSET); } +static inline void maestro_icu_ctrl_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ICU_CTRL_OFFSET, value); } + +static inline uint32_t maestro_icu_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ICU_MODE_OFFSET); } +static inline void maestro_icu_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ICU_MODE_OFFSET, value); } + +static inline uint32_t maestro_island_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_ISLAND_MODE_OFFSET); } +static inline void maestro_island_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_ISLAND_MODE_OFFSET, value); } + +static inline uint32_t maestro_dmu_mode_get(uint32_t base) { return ARCHI_READ(base, MAESTRO_DMU_MODE_OFFSET); } +static inline void maestro_dmu_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, MAESTRO_DMU_MODE_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define MAESTRO_ICU_CTRL_ICU_CTRL_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define MAESTRO_ICU_CTRL_ICU_CTRL(val) ((val) << 0) + +#define MAESTRO_ICU_MODE_ICU_MODE_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define MAESTRO_ICU_MODE_ICU_MODE(val) ((val) << 0) + +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define MAESTRO_ICU_MODE_ICU_MODE_DEFINED(val) ((val) << 4) + +#define MAESTRO_ISLAND_MODE_ISL_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define MAESTRO_ISLAND_MODE_ISL_MODE(val) ((val) << 0) + +#define MAESTRO_DMU_MODE_ISL_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define MAESTRO_DMU_MODE_ISL_MODE(val) ((val) << 0) + +#endif + + + +// +// CUSTOM FIELDS +// +#define MAESTRO_ICU_SUPPLY_EXT 0x0 +#define MAESTRO_ICU_SUPPLY_RET 0x1 +#define MAESTRO_ICU_SUPPLY_CKOFF 0x2 +#define MAESTRO_ICU_SUPPLY_ON 0x3 +#define MAESTRO_ICU_REGU_NONE 0x7 +#define MAESTRO_ICU_REGU_OFF 0x0 +#define MAESTRO_ICU_REGU_RV 0x1 +#define MAESTRO_ICU_REGU_LV 0x2 +#define MAESTRO_ICU_REGU_MV 0x3 +#define MAESTRO_ICU_REGU_NV 0x4 +#define MAESTRO_ICU_CLK_FNONE 0x7 +#define MAESTRO_ICU_CLK_FOFF 0x0 +#define MAESTRO_ICU_CLK_LF 0x1 +#define MAESTRO_ICU_CLK_MF 0x2 +#define MAESTRO_ICU_CLK_NF 0x3 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/mailbox/mailbox_v0.h b/sw/pulp-sdk/archi/include/archi/mailbox/mailbox_v0.h new file mode 100644 index 0000000..8013c9f --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/mailbox/mailbox_v0.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_MAILBOX_V0_H__ +#define __ARCHI_MAILBOX_V0_H__ + +#if PULP_CHIP_FAMILY != CHIP_BIGPULP +#error This file must be included only for bigpulp chip +#endif + +/* MAILBOX REGISTERS */ +#define MAILBOX_REG_WRDATA ( ARCHI_MAILBOX_BASE_ADDR + 0x0 ) +#define MAILBOX_REG_RDDATA ( ARCHI_MAILBOX_BASE_ADDR + 0x8 ) +#define MAILBOX_REG_STATUS ( ARCHI_MAILBOX_BASE_ADDR + 0x10) +#define MAILBOX_REG_ERROR ( ARCHI_MAILBOX_BASE_ADDR + 0x14) +#define MAILBOX_REG_IS ( ARCHI_MAILBOX_BASE_ADDR + 0x20) +#define MAILBOX_REG_IE ( ARCHI_MAILBOX_BASE_ADDR + 0x24) + +/* SIGNALING */ +#define PULP_READY ( 0x01U ) +#define PULP_START ( 0x02U ) +#define PULP_BUSY ( 0x03U ) +#define PULP_DONE ( 0x04U ) +#define PULP_STOP ( 0x0FU ) + +#define HOST_READY ( 0x1000U ) +#define HOST_DONE ( 0x3000U ) + +#define MBOX_N_BITS_REQ_TYPE ( 4U ) // number of MSBs to specify the type +#define RAB_UPDATE_N_BITS_ELEM ( 8U ) // number of bits to specify the mask of elements to be updated +#define RAB_UPDATE_N_BITS_TYPE ( 2U ) // number of bits to specify the update type + +#define TO_RUNTIME ( 0x10000000U ) // bypass PULP driver +#define RAB_UPDATE ( 0x20000000U ) // handled by PULP driver +#define RAB_SWITCH ( 0x30000000U ) // handled by PULP driver + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/or1k/spr-defs.h b/sw/pulp-sdk/archi/include/archi/or1k/spr-defs.h new file mode 100644 index 0000000..ec4c6ec --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/or1k/spr-defs.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARCHI_OR1K_SPR_DEFS_H +#define _ARCHI_OR1K_SPR_DEFS_H + +/* Definition of special-purpose registers (SPRs). */ +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_SR (SPRGROUP_SYS + 17) +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) + +/* PULP registers */ +#define SPR_CORE_ID (SPRGROUP_SYS + 0x680) +#define SPR_CLUSTER_ID (SPRGROUP_SYS + 0x681) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCER (SPRGROUP_PC + 32) +#define SPR_PCMR (SPRGROUP_PC + 33) + + +/* + * Bit definitions for the Supervision Register + * + */ + + +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ + +#define SPR_PCER_CYCLES 0 /* Count the number of cycles the core was running */ +#define SPR_PCER_INSTR 1 /* Count the number of instructions executed */ +#define SPR_PCER_LD_STALL 2 /* Number of load data hazards */ +#define SPR_PCER_JMP_STALL 3 /* Number of jump register data hazards */ +#define SPR_PCER_IMISS 4 /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */ +#define SPR_PCER_WBRANCH 5 /* Number of wrong predicted branches */ +#define SPR_PCER_WBRANCH_CYC 6 /* Cycles wasted due to wrong predicted branches */ +#define SPR_PCER_LD 7 /* Number of memory loads executed. Misaligned accesses are counted twice */ +#define SPR_PCER_ST 8 /* Number of memory stores executed. Misaligned accesses are counted twice */ +#define SPR_PCER_JUMP 9 /* Number of jump instructions seen, i.e. j, jr, jal, jalr */ +#define SPR_PCER_BRANCH 10 /* Number of jump instructions seen, i.e. bf, bnf */ +#define SPR_PCER_DELAY_NOP 11 /* Number of empty delay slots, i.e. delay slots filled with a nop */ +#define SPR_PCER_LD_EXT 12 /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ +#define SPR_PCER_ST_EXT 13 /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ +#define SPR_PCER_LD_EXT_CYC 14 /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */ +#define SPR_PCER_ST_EXT_CYC 15 /* Cycles used for memory stores to EXT. Every non-TCDM access is considered external */ +#define SPR_PCER_TCDM_CONT 16 /* Cycles wasted due to TCDM/log-interconnect contention */ + +#define CSR_PCER_NB_EVENTS 17 +#define SPR_PCER_NB_EVENTS 17 +#define CSR_PCER_NB_INTERNAL_EVENTS 12 + +#define CSR_NB_PCCR 31 + +// Gives from the event ID, the HW mask that can be stored (with an OR with other events mask) to the PCER +#define SPR_PCER_EVENT_MASK(eventId) (1<<(eventId)) +#define SPR_PCER_ALL_EVENTS_MASK 0xffffffff + +#define SPR_PCMR_ACTIVE 0x1 /* Activate counting */ +#define SPR_PCMR_SATURATE 0x2 /* Activate saturation */ + + + + +#endif /* SPR_DEFS__H */ diff --git a/sw/pulp-sdk/archi/include/archi/pulp.h b/sw/pulp-sdk/archi/include/archi/pulp.h new file mode 100644 index 0000000..baac01e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pulp.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_PULP_H__ +#define __ARCHI_PULP_H__ + +#include "archi/pulp_defs.h" +#include "archi/utils.h" + +#define __A_PULP_CHIP_INC(x) #x +#define _A_PULP_CHIP_INC(x) __A_PULP_CHIP_INC(archi/chips/x/pulp.h) +#define A_PULP_CHIP_INC(x) _A_PULP_CHIP_INC(x) + +#if defined(PULP_CHIP_FAMILY) +#include A_PULP_CHIP_INC(PULP_CHIP_FAMILY_STR) +#else +#include A_PULP_CHIP_INC(PULP_CHIP_STR) +#endif + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/pulp_defs.h b/sw/pulp-sdk/archi/include/archi/pulp_defs.h new file mode 100644 index 0000000..167a139 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pulp_defs.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_PULP_DEFS_H__ +#define __ARCHI_PULP_DEFS_H__ + +#define CHIP_MIA 0 +#define CHIP_HONEY 1 +#define CHIP_FULMINE 2 +#define CHIP_PULP4 3 +#define CHIP_PULPEVO 4 +#define CHIP_PULP4Z 5 +#define CHIP_PULP3 6 +#define CHIP_BIGPULP 7 +#define CHIP_BIGPULP_Z_7020 8 +#define CHIP_BIGPULP_Z_7045 9 +#define CHIP_BIGPULP_Z_7045_O 19 +#define CHIP_BIGPULP_Z_7045_RISCV 20 +#define CHIP_GAP 10 +#define CHIP_GAP8 10 +#define CHIP_VIVOSOC2 11 +#define CHIP_FULMINE8 12 +#define CHIP_EXACONV 13 +#define CHIP_WOLFE 14 +#define CHIP_NEURAGHE 15 +#define CHIP_PATRONUS 16 +#define CHIP_VIVOSOC3 17 +#define CHIP_VIVOSOC2_1 18 +#define CHIP_PULPINO 21 +#define CHIP_QUENTIN 22 +#define CHIP_KERBIN 23 +#define CHIP_OPRECOMPKW 24 +#define CHIP_LUPO 25 +#define CHIP_DEVCHIP 26 +#define CHIP_PULPISSIMO 27 +#define CHIP_BIGPULP_ZUX 28 +#define CHIP_PULP 29 +#define CHIP_MULTINO 30 +#define CHIP_VEGA 31 +#define CHIP_HERO_Z_7045 32 +#define CHIP_OPRECOMPKW_SA 33 +#define CHIP_OPRECOMPKW_SFLOAT 34 +#define CHIP_OPRECOMPKW_SFLOAT_SA 35 +#define CHIP_ARNOLD 36 +#define CHIP_BIGPULP_STANDALONE 37 +#define CHIP_GAP_REV1 38 +#define CHIP_USOC_V1 39 +#define CHIP_BIGPULP_JUNO 40 +#define CHIP_BIGPULP_ZU9EG 41 +#define CHIP_PULPISSIMO_V1 42 +#define CHIP_VIVOSOC3_5 43 +#define CHIP_PULP_V1 44 +#define CHIP_VIVOSOC3_1 45 +#define CHIP_GAP8_REVC 46 +#define CHIP_GAP9 47 +#define CHIP_VIVOSOC4 48 +#define CHIP_WOLFE_16 49 + +#define CORE_OR1K_V1 0 +#define CORE_OR1K_V2 1 +#define CORE_OR1K_V3 2 +#define CORE_OR1K_V4 3 +#define CORE_OR1K_V5 4 + +#define CORE_RISCV_V1 100 +#define CORE_RISCV_V2 101 +#define CORE_RISCV_V3 102 +#define CORE_RISCV_V4 103 + +#define ARCHI_PLATFORM_OTHER 0 +#define ARCHI_PLATFORM_FPGA 1 +#define ARCHI_PLATFORM_RTL 2 +#define ARCHI_PLATFORM_GVSOC 3 +#define ARCHI_PLATFORM_BOARD 4 + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/pwm/pwm_v1.h b/sw/pulp-sdk/archi/include/archi/pwm/pwm_v1.h new file mode 100644 index 0000000..2b14c62 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/pwm_v1.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna and + * GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_PWM_PWM_V1_H__ +#define __ARCHI_PWM_PWM_V1_H__ + +#include "archi/pulp.h" + +#define PWM_TIMER_TO_TIMER_OFFSET 0x40 + +#define PWM_TIMER_CMD_OFFSET 0x00 +#define PWM_TIMER_CONFIG_OFFSET 0x04 +#define PWM_TIMER_THRESHOLD_OFFSET 0x08 +#define PWM_TIMER_TH_CHANNEL_OFFSET 0x0C +#define PWM_TIMER_LUT_CHANNEL_OFFSET 0x1C +#define PWM_TIMER_COUNTER_OFFSET 0x2C + +#define PWM_CHANNEL_TO_CHANNEL_OFFSET 0x04 + +/* Timer Base: PWM_BASE_ADDR + Timer*PWM_TIMER_TO_TIMER_OFFSET + Config: + PWM_TIMER_CONFIG_OFFSET + Threhsold: + PWM_TIMER_THRESHOLD_OFFSET + Channel Thresh: + PWM_TIMER_TH_CHANNEL_OFFSET + Channel*PWM_CHANNEL_TO_CHANNEL_OFFSET + Channel LUT: + PWM_TIMER_LUT_CHANNEL_OFFSET + Channel*PWM_CHANNEL_TO_CHANNEL_OFFSET +*/ +#define PWM_TIMER_BASE_ADDR(timer) (ARCHI_PWM_ADDR + timer*PWM_TIMER_TO_TIMER_OFFSET) +#define PWM_TIMER_CMD_ADDR(timer) (PWM_TIMER_BASE_ADDR(timer) + PWM_TIMER_CMD_OFFSET) +#define PWM_TIMER_CONFIG_ADDR(timer) (PWM_TIMER_BASE_ADDR(timer) + PWM_TIMER_CONFIG_OFFSET) +#define PWM_TIMER_THRESHOLD_ADDR(timer) (PWM_TIMER_BASE_ADDR(timer) + PWM_TIMER_THRESHOLD_OFFSET) +#define PWM_TIMER_TH_CHANNEL_ADDR(timer, channel) (PWM_TIMER_BASE_ADDR(timer) + PWM_TIMER_TH_CHANNEL_OFFSET + (channel*PWM_CHANNEL_TO_CHANNEL_OFFSET)) +#define PWM_TIMER_LUT_CHANNEL_ADDR(timer, channel) (PWM_TIMER_BASE_ADDR(timer) + PWM_TIMER_LUT_CHANNEL_OFFSET + (channel*PWM_CHANNEL_TO_CHANNEL_OFFSET)) +#define PWM_TIMER_COUNTER_ADDR(timer) (PWM_TIMER_BASE_ADDR(timer) + PWM_TIMER_COUNTER_OFFSET) + +#define REG_EVENT_CFG (ARCHI_PWM_ADDR + 0x100) +#define REG_PWM_TIMER_EN (ARCHI_PWM_ADDR + 0X104) + +#define PWM_TIMER_EN(timer) (0x1< +#include "archi/utils.h" + +#endif + +#include "pwm_v1_regs.h" +#include "pwm_v1_regfields.h" +#include "pwm_v1_structs.h" +#include "pwm_v1_regmap.h" +#include "pwm_v1_accessors.h" +#include "pwm_v1_macros.h" +#include "pwm_v1_groups.h" +#include "pwm_v1_constants.h" + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_accessors.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_accessors.h new file mode 100644 index 0000000..02e793e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_accessors.h @@ -0,0 +1,145 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_ACCESSORS_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_ACCESSORS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +static inline uint32_t pwm_t0_cmd_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_CMD_OFFSET); } +static inline void pwm_t0_cmd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_CMD_OFFSET, value); } + +static inline uint32_t pwm_t0_config_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_CONFIG_OFFSET); } +static inline void pwm_t0_config_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_CONFIG_OFFSET, value); } + +static inline uint32_t pwm_t0_threshold_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_THRESHOLD_OFFSET); } +static inline void pwm_t0_threshold_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_THRESHOLD_OFFSET, value); } + +static inline uint32_t pwm_t0_th_channel0_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_TH_CHANNEL0_OFFSET); } +static inline void pwm_t0_th_channel0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_TH_CHANNEL0_OFFSET, value); } + +static inline uint32_t pwm_t0_th_channel1_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_TH_CHANNEL1_OFFSET); } +static inline void pwm_t0_th_channel1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_TH_CHANNEL1_OFFSET, value); } + +static inline uint32_t pwm_t0_th_channel2_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_TH_CHANNEL2_OFFSET); } +static inline void pwm_t0_th_channel2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_TH_CHANNEL2_OFFSET, value); } + +static inline uint32_t pwm_t0_th_channel3_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_TH_CHANNEL3_OFFSET); } +static inline void pwm_t0_th_channel3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_TH_CHANNEL3_OFFSET, value); } + +static inline uint32_t pwm_t0_counter_get(uint32_t base) { return ARCHI_READ(base, PWM_T0_COUNTER_OFFSET); } +static inline void pwm_t0_counter_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T0_COUNTER_OFFSET, value); } + +static inline uint32_t pwm_t1_cmd_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_CMD_OFFSET); } +static inline void pwm_t1_cmd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_CMD_OFFSET, value); } + +static inline uint32_t pwm_t1_config_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_CONFIG_OFFSET); } +static inline void pwm_t1_config_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_CONFIG_OFFSET, value); } + +static inline uint32_t pwm_t1_threshold_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_THRESHOLD_OFFSET); } +static inline void pwm_t1_threshold_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_THRESHOLD_OFFSET, value); } + +static inline uint32_t pwm_t1_th_channel0_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_TH_CHANNEL0_OFFSET); } +static inline void pwm_t1_th_channel0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_TH_CHANNEL0_OFFSET, value); } + +static inline uint32_t pwm_t1_th_channel1_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_TH_CHANNEL1_OFFSET); } +static inline void pwm_t1_th_channel1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_TH_CHANNEL1_OFFSET, value); } + +static inline uint32_t pwm_t1_th_channel2_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_TH_CHANNEL2_OFFSET); } +static inline void pwm_t1_th_channel2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_TH_CHANNEL2_OFFSET, value); } + +static inline uint32_t pwm_t1_th_channel3_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_TH_CHANNEL3_OFFSET); } +static inline void pwm_t1_th_channel3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_TH_CHANNEL3_OFFSET, value); } + +static inline uint32_t pwm_t1_counter_get(uint32_t base) { return ARCHI_READ(base, PWM_T1_COUNTER_OFFSET); } +static inline void pwm_t1_counter_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T1_COUNTER_OFFSET, value); } + +static inline uint32_t pwm_t2_cmd_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_CMD_OFFSET); } +static inline void pwm_t2_cmd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_CMD_OFFSET, value); } + +static inline uint32_t pwm_t2_config_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_CONFIG_OFFSET); } +static inline void pwm_t2_config_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_CONFIG_OFFSET, value); } + +static inline uint32_t pwm_t2_threshold_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_THRESHOLD_OFFSET); } +static inline void pwm_t2_threshold_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_THRESHOLD_OFFSET, value); } + +static inline uint32_t pwm_t2_th_channel0_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_TH_CHANNEL0_OFFSET); } +static inline void pwm_t2_th_channel0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_TH_CHANNEL0_OFFSET, value); } + +static inline uint32_t pwm_t2_th_channel1_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_TH_CHANNEL1_OFFSET); } +static inline void pwm_t2_th_channel1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_TH_CHANNEL1_OFFSET, value); } + +static inline uint32_t pwm_t2_th_channel2_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_TH_CHANNEL2_OFFSET); } +static inline void pwm_t2_th_channel2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_TH_CHANNEL2_OFFSET, value); } + +static inline uint32_t pwm_t2_th_channel3_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_TH_CHANNEL3_OFFSET); } +static inline void pwm_t2_th_channel3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_TH_CHANNEL3_OFFSET, value); } + +static inline uint32_t pwm_t2_counter_get(uint32_t base) { return ARCHI_READ(base, PWM_T2_COUNTER_OFFSET); } +static inline void pwm_t2_counter_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T2_COUNTER_OFFSET, value); } + +static inline uint32_t pwm_t3_cmd_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_CMD_OFFSET); } +static inline void pwm_t3_cmd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_CMD_OFFSET, value); } + +static inline uint32_t pwm_t3_config_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_CONFIG_OFFSET); } +static inline void pwm_t3_config_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_CONFIG_OFFSET, value); } + +static inline uint32_t pwm_t3_threshold_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_THRESHOLD_OFFSET); } +static inline void pwm_t3_threshold_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_THRESHOLD_OFFSET, value); } + +static inline uint32_t pwm_t3_th_channel0_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_TH_CHANNEL0_OFFSET); } +static inline void pwm_t3_th_channel0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_TH_CHANNEL0_OFFSET, value); } + +static inline uint32_t pwm_t3_th_channel1_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_TH_CHANNEL1_OFFSET); } +static inline void pwm_t3_th_channel1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_TH_CHANNEL1_OFFSET, value); } + +static inline uint32_t pwm_t3_th_channel2_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_TH_CHANNEL2_OFFSET); } +static inline void pwm_t3_th_channel2_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_TH_CHANNEL2_OFFSET, value); } + +static inline uint32_t pwm_t3_th_channel3_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_TH_CHANNEL3_OFFSET); } +static inline void pwm_t3_th_channel3_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_TH_CHANNEL3_OFFSET, value); } + +static inline uint32_t pwm_t3_counter_get(uint32_t base) { return ARCHI_READ(base, PWM_T3_COUNTER_OFFSET); } +static inline void pwm_t3_counter_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_T3_COUNTER_OFFSET, value); } + +static inline uint32_t pwm_event_cfg_get(uint32_t base) { return ARCHI_READ(base, PWM_EVENT_CFG_OFFSET); } +static inline void pwm_event_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_EVENT_CFG_OFFSET, value); } + +static inline uint32_t pwm_cg_get(uint32_t base) { return ARCHI_READ(base, PWM_CG_OFFSET); } +static inline void pwm_cg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, PWM_CG_OFFSET, value); } + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_constants.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_constants.h new file mode 100644 index 0000000..7942869 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_constants.h @@ -0,0 +1,33 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_CONSTANTS_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_CONSTANTS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_groups.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_groups.h new file mode 100644 index 0000000..072d56c --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_groups.h @@ -0,0 +1,33 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_GROUPS_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_GROUPS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_gvsoc.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_gvsoc.h new file mode 100644 index 0000000..da2d7b2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_gvsoc.h @@ -0,0 +1,385 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_GVSOC_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_GVSOC_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_pwm_t0_cmd : public vp::reg_32 +{ +public: + inline void start_set(uint32_t value) { this->set_field(value, PWM_T0_CMD_START_BIT, PWM_T0_CMD_START_WIDTH); } + inline uint32_t start_get() { return this->get_field(PWM_T0_CMD_START_BIT, PWM_T0_CMD_START_WIDTH); } + inline void stop_set(uint32_t value) { this->set_field(value, PWM_T0_CMD_STOP_BIT, PWM_T0_CMD_STOP_WIDTH); } + inline uint32_t stop_get() { return this->get_field(PWM_T0_CMD_STOP_BIT, PWM_T0_CMD_STOP_WIDTH); } + inline void update_set(uint32_t value) { this->set_field(value, PWM_T0_CMD_UPDATE_BIT, PWM_T0_CMD_UPDATE_WIDTH); } + inline uint32_t update_get() { return this->get_field(PWM_T0_CMD_UPDATE_BIT, PWM_T0_CMD_UPDATE_WIDTH); } + inline void reset_set(uint32_t value) { this->set_field(value, PWM_T0_CMD_RESET_BIT, PWM_T0_CMD_RESET_WIDTH); } + inline uint32_t reset_get() { return this->get_field(PWM_T0_CMD_RESET_BIT, PWM_T0_CMD_RESET_WIDTH); } + inline void arm_set(uint32_t value) { this->set_field(value, PWM_T0_CMD_ARM_BIT, PWM_T0_CMD_ARM_WIDTH); } + inline uint32_t arm_get() { return this->get_field(PWM_T0_CMD_ARM_BIT, PWM_T0_CMD_ARM_WIDTH); } +}; + +class vp_pwm_t0_config : public vp::reg_32 +{ +public: + inline void insel_set(uint32_t value) { this->set_field(value, PWM_T0_CONFIG_INSEL_BIT, PWM_T0_CONFIG_INSEL_WIDTH); } + inline uint32_t insel_get() { return this->get_field(PWM_T0_CONFIG_INSEL_BIT, PWM_T0_CONFIG_INSEL_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T0_CONFIG_MODE_BIT, PWM_T0_CONFIG_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T0_CONFIG_MODE_BIT, PWM_T0_CONFIG_MODE_WIDTH); } + inline void clksel_set(uint32_t value) { this->set_field(value, PWM_T0_CONFIG_CLKSEL_BIT, PWM_T0_CONFIG_CLKSEL_WIDTH); } + inline uint32_t clksel_get() { return this->get_field(PWM_T0_CONFIG_CLKSEL_BIT, PWM_T0_CONFIG_CLKSEL_WIDTH); } + inline void updownsel_set(uint32_t value) { this->set_field(value, PWM_T0_CONFIG_UPDOWNSEL_BIT, PWM_T0_CONFIG_UPDOWNSEL_WIDTH); } + inline uint32_t updownsel_get() { return this->get_field(PWM_T0_CONFIG_UPDOWNSEL_BIT, PWM_T0_CONFIG_UPDOWNSEL_WIDTH); } + inline void presc_set(uint32_t value) { this->set_field(value, PWM_T0_CONFIG_PRESC_BIT, PWM_T0_CONFIG_PRESC_WIDTH); } + inline uint32_t presc_get() { return this->get_field(PWM_T0_CONFIG_PRESC_BIT, PWM_T0_CONFIG_PRESC_WIDTH); } +}; + +class vp_pwm_t0_threshold : public vp::reg_32 +{ +public: + inline void th_lo_set(uint32_t value) { this->set_field(value, PWM_T0_THRESHOLD_TH_LO_BIT, PWM_T0_THRESHOLD_TH_LO_WIDTH); } + inline uint32_t th_lo_get() { return this->get_field(PWM_T0_THRESHOLD_TH_LO_BIT, PWM_T0_THRESHOLD_TH_LO_WIDTH); } + inline void th_hi_set(uint32_t value) { this->set_field(value, PWM_T0_THRESHOLD_TH_HI_BIT, PWM_T0_THRESHOLD_TH_HI_WIDTH); } + inline uint32_t th_hi_get() { return this->get_field(PWM_T0_THRESHOLD_TH_HI_BIT, PWM_T0_THRESHOLD_TH_HI_WIDTH); } +}; + +class vp_pwm_t0_th_channel0 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL0_TH_BIT, PWM_T0_TH_CHANNEL0_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T0_TH_CHANNEL0_TH_BIT, PWM_T0_TH_CHANNEL0_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL0_MODE_BIT, PWM_T0_TH_CHANNEL0_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T0_TH_CHANNEL0_MODE_BIT, PWM_T0_TH_CHANNEL0_MODE_WIDTH); } +}; + +class vp_pwm_t0_th_channel1 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL1_TH_BIT, PWM_T0_TH_CHANNEL1_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T0_TH_CHANNEL1_TH_BIT, PWM_T0_TH_CHANNEL1_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL1_MODE_BIT, PWM_T0_TH_CHANNEL1_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T0_TH_CHANNEL1_MODE_BIT, PWM_T0_TH_CHANNEL1_MODE_WIDTH); } +}; + +class vp_pwm_t0_th_channel2 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL2_TH_BIT, PWM_T0_TH_CHANNEL2_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T0_TH_CHANNEL2_TH_BIT, PWM_T0_TH_CHANNEL2_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL2_MODE_BIT, PWM_T0_TH_CHANNEL2_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T0_TH_CHANNEL2_MODE_BIT, PWM_T0_TH_CHANNEL2_MODE_WIDTH); } +}; + +class vp_pwm_t0_th_channel3 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL3_TH_BIT, PWM_T0_TH_CHANNEL3_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T0_TH_CHANNEL3_TH_BIT, PWM_T0_TH_CHANNEL3_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T0_TH_CHANNEL3_MODE_BIT, PWM_T0_TH_CHANNEL3_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T0_TH_CHANNEL3_MODE_BIT, PWM_T0_TH_CHANNEL3_MODE_WIDTH); } +}; + +class vp_pwm_t0_counter : public vp::reg_32 +{ +public: +}; + +class vp_pwm_t1_cmd : public vp::reg_32 +{ +public: + inline void start_set(uint32_t value) { this->set_field(value, PWM_T1_CMD_START_BIT, PWM_T1_CMD_START_WIDTH); } + inline uint32_t start_get() { return this->get_field(PWM_T1_CMD_START_BIT, PWM_T1_CMD_START_WIDTH); } + inline void stop_set(uint32_t value) { this->set_field(value, PWM_T1_CMD_STOP_BIT, PWM_T1_CMD_STOP_WIDTH); } + inline uint32_t stop_get() { return this->get_field(PWM_T1_CMD_STOP_BIT, PWM_T1_CMD_STOP_WIDTH); } + inline void update_set(uint32_t value) { this->set_field(value, PWM_T1_CMD_UPDATE_BIT, PWM_T1_CMD_UPDATE_WIDTH); } + inline uint32_t update_get() { return this->get_field(PWM_T1_CMD_UPDATE_BIT, PWM_T1_CMD_UPDATE_WIDTH); } + inline void reset_set(uint32_t value) { this->set_field(value, PWM_T1_CMD_RESET_BIT, PWM_T1_CMD_RESET_WIDTH); } + inline uint32_t reset_get() { return this->get_field(PWM_T1_CMD_RESET_BIT, PWM_T1_CMD_RESET_WIDTH); } + inline void arm_set(uint32_t value) { this->set_field(value, PWM_T1_CMD_ARM_BIT, PWM_T1_CMD_ARM_WIDTH); } + inline uint32_t arm_get() { return this->get_field(PWM_T1_CMD_ARM_BIT, PWM_T1_CMD_ARM_WIDTH); } +}; + +class vp_pwm_t1_config : public vp::reg_32 +{ +public: + inline void insel_set(uint32_t value) { this->set_field(value, PWM_T1_CONFIG_INSEL_BIT, PWM_T1_CONFIG_INSEL_WIDTH); } + inline uint32_t insel_get() { return this->get_field(PWM_T1_CONFIG_INSEL_BIT, PWM_T1_CONFIG_INSEL_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T1_CONFIG_MODE_BIT, PWM_T1_CONFIG_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T1_CONFIG_MODE_BIT, PWM_T1_CONFIG_MODE_WIDTH); } + inline void clksel_set(uint32_t value) { this->set_field(value, PWM_T1_CONFIG_CLKSEL_BIT, PWM_T1_CONFIG_CLKSEL_WIDTH); } + inline uint32_t clksel_get() { return this->get_field(PWM_T1_CONFIG_CLKSEL_BIT, PWM_T1_CONFIG_CLKSEL_WIDTH); } + inline void updownsel_set(uint32_t value) { this->set_field(value, PWM_T1_CONFIG_UPDOWNSEL_BIT, PWM_T1_CONFIG_UPDOWNSEL_WIDTH); } + inline uint32_t updownsel_get() { return this->get_field(PWM_T1_CONFIG_UPDOWNSEL_BIT, PWM_T1_CONFIG_UPDOWNSEL_WIDTH); } + inline void presc_set(uint32_t value) { this->set_field(value, PWM_T1_CONFIG_PRESC_BIT, PWM_T1_CONFIG_PRESC_WIDTH); } + inline uint32_t presc_get() { return this->get_field(PWM_T1_CONFIG_PRESC_BIT, PWM_T1_CONFIG_PRESC_WIDTH); } +}; + +class vp_pwm_t1_threshold : public vp::reg_32 +{ +public: + inline void th_lo_set(uint32_t value) { this->set_field(value, PWM_T1_THRESHOLD_TH_LO_BIT, PWM_T1_THRESHOLD_TH_LO_WIDTH); } + inline uint32_t th_lo_get() { return this->get_field(PWM_T1_THRESHOLD_TH_LO_BIT, PWM_T1_THRESHOLD_TH_LO_WIDTH); } + inline void th_hi_set(uint32_t value) { this->set_field(value, PWM_T1_THRESHOLD_TH_HI_BIT, PWM_T1_THRESHOLD_TH_HI_WIDTH); } + inline uint32_t th_hi_get() { return this->get_field(PWM_T1_THRESHOLD_TH_HI_BIT, PWM_T1_THRESHOLD_TH_HI_WIDTH); } +}; + +class vp_pwm_t1_th_channel0 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL0_TH_BIT, PWM_T1_TH_CHANNEL0_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T1_TH_CHANNEL0_TH_BIT, PWM_T1_TH_CHANNEL0_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL0_MODE_BIT, PWM_T1_TH_CHANNEL0_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T1_TH_CHANNEL0_MODE_BIT, PWM_T1_TH_CHANNEL0_MODE_WIDTH); } +}; + +class vp_pwm_t1_th_channel1 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL1_TH_BIT, PWM_T1_TH_CHANNEL1_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T1_TH_CHANNEL1_TH_BIT, PWM_T1_TH_CHANNEL1_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL1_MODE_BIT, PWM_T1_TH_CHANNEL1_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T1_TH_CHANNEL1_MODE_BIT, PWM_T1_TH_CHANNEL1_MODE_WIDTH); } +}; + +class vp_pwm_t1_th_channel2 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL2_TH_BIT, PWM_T1_TH_CHANNEL2_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T1_TH_CHANNEL2_TH_BIT, PWM_T1_TH_CHANNEL2_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL2_MODE_BIT, PWM_T1_TH_CHANNEL2_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T1_TH_CHANNEL2_MODE_BIT, PWM_T1_TH_CHANNEL2_MODE_WIDTH); } +}; + +class vp_pwm_t1_th_channel3 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL3_TH_BIT, PWM_T1_TH_CHANNEL3_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T1_TH_CHANNEL3_TH_BIT, PWM_T1_TH_CHANNEL3_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T1_TH_CHANNEL3_MODE_BIT, PWM_T1_TH_CHANNEL3_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T1_TH_CHANNEL3_MODE_BIT, PWM_T1_TH_CHANNEL3_MODE_WIDTH); } +}; + +class vp_pwm_t1_counter : public vp::reg_32 +{ +public: +}; + +class vp_pwm_t2_cmd : public vp::reg_32 +{ +public: + inline void start_set(uint32_t value) { this->set_field(value, PWM_T2_CMD_START_BIT, PWM_T2_CMD_START_WIDTH); } + inline uint32_t start_get() { return this->get_field(PWM_T2_CMD_START_BIT, PWM_T2_CMD_START_WIDTH); } + inline void stop_set(uint32_t value) { this->set_field(value, PWM_T2_CMD_STOP_BIT, PWM_T2_CMD_STOP_WIDTH); } + inline uint32_t stop_get() { return this->get_field(PWM_T2_CMD_STOP_BIT, PWM_T2_CMD_STOP_WIDTH); } + inline void update_set(uint32_t value) { this->set_field(value, PWM_T2_CMD_UPDATE_BIT, PWM_T2_CMD_UPDATE_WIDTH); } + inline uint32_t update_get() { return this->get_field(PWM_T2_CMD_UPDATE_BIT, PWM_T2_CMD_UPDATE_WIDTH); } + inline void reset_set(uint32_t value) { this->set_field(value, PWM_T2_CMD_RESET_BIT, PWM_T2_CMD_RESET_WIDTH); } + inline uint32_t reset_get() { return this->get_field(PWM_T2_CMD_RESET_BIT, PWM_T2_CMD_RESET_WIDTH); } + inline void arm_set(uint32_t value) { this->set_field(value, PWM_T2_CMD_ARM_BIT, PWM_T2_CMD_ARM_WIDTH); } + inline uint32_t arm_get() { return this->get_field(PWM_T2_CMD_ARM_BIT, PWM_T2_CMD_ARM_WIDTH); } +}; + +class vp_pwm_t2_config : public vp::reg_32 +{ +public: + inline void insel_set(uint32_t value) { this->set_field(value, PWM_T2_CONFIG_INSEL_BIT, PWM_T2_CONFIG_INSEL_WIDTH); } + inline uint32_t insel_get() { return this->get_field(PWM_T2_CONFIG_INSEL_BIT, PWM_T2_CONFIG_INSEL_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T2_CONFIG_MODE_BIT, PWM_T2_CONFIG_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T2_CONFIG_MODE_BIT, PWM_T2_CONFIG_MODE_WIDTH); } + inline void clksel_set(uint32_t value) { this->set_field(value, PWM_T2_CONFIG_CLKSEL_BIT, PWM_T2_CONFIG_CLKSEL_WIDTH); } + inline uint32_t clksel_get() { return this->get_field(PWM_T2_CONFIG_CLKSEL_BIT, PWM_T2_CONFIG_CLKSEL_WIDTH); } + inline void updownsel_set(uint32_t value) { this->set_field(value, PWM_T2_CONFIG_UPDOWNSEL_BIT, PWM_T2_CONFIG_UPDOWNSEL_WIDTH); } + inline uint32_t updownsel_get() { return this->get_field(PWM_T2_CONFIG_UPDOWNSEL_BIT, PWM_T2_CONFIG_UPDOWNSEL_WIDTH); } + inline void presc_set(uint32_t value) { this->set_field(value, PWM_T2_CONFIG_PRESC_BIT, PWM_T2_CONFIG_PRESC_WIDTH); } + inline uint32_t presc_get() { return this->get_field(PWM_T2_CONFIG_PRESC_BIT, PWM_T2_CONFIG_PRESC_WIDTH); } +}; + +class vp_pwm_t2_threshold : public vp::reg_32 +{ +public: + inline void th_lo_set(uint32_t value) { this->set_field(value, PWM_T2_THRESHOLD_TH_LO_BIT, PWM_T2_THRESHOLD_TH_LO_WIDTH); } + inline uint32_t th_lo_get() { return this->get_field(PWM_T2_THRESHOLD_TH_LO_BIT, PWM_T2_THRESHOLD_TH_LO_WIDTH); } + inline void th_hi_set(uint32_t value) { this->set_field(value, PWM_T2_THRESHOLD_TH_HI_BIT, PWM_T2_THRESHOLD_TH_HI_WIDTH); } + inline uint32_t th_hi_get() { return this->get_field(PWM_T2_THRESHOLD_TH_HI_BIT, PWM_T2_THRESHOLD_TH_HI_WIDTH); } +}; + +class vp_pwm_t2_th_channel0 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL0_TH_BIT, PWM_T2_TH_CHANNEL0_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T2_TH_CHANNEL0_TH_BIT, PWM_T2_TH_CHANNEL0_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL0_MODE_BIT, PWM_T2_TH_CHANNEL0_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T2_TH_CHANNEL0_MODE_BIT, PWM_T2_TH_CHANNEL0_MODE_WIDTH); } +}; + +class vp_pwm_t2_th_channel1 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL1_TH_BIT, PWM_T2_TH_CHANNEL1_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T2_TH_CHANNEL1_TH_BIT, PWM_T2_TH_CHANNEL1_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL1_MODE_BIT, PWM_T2_TH_CHANNEL1_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T2_TH_CHANNEL1_MODE_BIT, PWM_T2_TH_CHANNEL1_MODE_WIDTH); } +}; + +class vp_pwm_t2_th_channel2 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL2_TH_BIT, PWM_T2_TH_CHANNEL2_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T2_TH_CHANNEL2_TH_BIT, PWM_T2_TH_CHANNEL2_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL2_MODE_BIT, PWM_T2_TH_CHANNEL2_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T2_TH_CHANNEL2_MODE_BIT, PWM_T2_TH_CHANNEL2_MODE_WIDTH); } +}; + +class vp_pwm_t2_th_channel3 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL3_TH_BIT, PWM_T2_TH_CHANNEL3_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T2_TH_CHANNEL3_TH_BIT, PWM_T2_TH_CHANNEL3_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T2_TH_CHANNEL3_MODE_BIT, PWM_T2_TH_CHANNEL3_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T2_TH_CHANNEL3_MODE_BIT, PWM_T2_TH_CHANNEL3_MODE_WIDTH); } +}; + +class vp_pwm_t2_counter : public vp::reg_32 +{ +public: +}; + +class vp_pwm_t3_cmd : public vp::reg_32 +{ +public: + inline void start_set(uint32_t value) { this->set_field(value, PWM_T3_CMD_START_BIT, PWM_T3_CMD_START_WIDTH); } + inline uint32_t start_get() { return this->get_field(PWM_T3_CMD_START_BIT, PWM_T3_CMD_START_WIDTH); } + inline void stop_set(uint32_t value) { this->set_field(value, PWM_T3_CMD_STOP_BIT, PWM_T3_CMD_STOP_WIDTH); } + inline uint32_t stop_get() { return this->get_field(PWM_T3_CMD_STOP_BIT, PWM_T3_CMD_STOP_WIDTH); } + inline void update_set(uint32_t value) { this->set_field(value, PWM_T3_CMD_UPDATE_BIT, PWM_T3_CMD_UPDATE_WIDTH); } + inline uint32_t update_get() { return this->get_field(PWM_T3_CMD_UPDATE_BIT, PWM_T3_CMD_UPDATE_WIDTH); } + inline void reset_set(uint32_t value) { this->set_field(value, PWM_T3_CMD_RESET_BIT, PWM_T3_CMD_RESET_WIDTH); } + inline uint32_t reset_get() { return this->get_field(PWM_T3_CMD_RESET_BIT, PWM_T3_CMD_RESET_WIDTH); } + inline void arm_set(uint32_t value) { this->set_field(value, PWM_T3_CMD_ARM_BIT, PWM_T3_CMD_ARM_WIDTH); } + inline uint32_t arm_get() { return this->get_field(PWM_T3_CMD_ARM_BIT, PWM_T3_CMD_ARM_WIDTH); } +}; + +class vp_pwm_t3_config : public vp::reg_32 +{ +public: + inline void insel_set(uint32_t value) { this->set_field(value, PWM_T3_CONFIG_INSEL_BIT, PWM_T3_CONFIG_INSEL_WIDTH); } + inline uint32_t insel_get() { return this->get_field(PWM_T3_CONFIG_INSEL_BIT, PWM_T3_CONFIG_INSEL_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T3_CONFIG_MODE_BIT, PWM_T3_CONFIG_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T3_CONFIG_MODE_BIT, PWM_T3_CONFIG_MODE_WIDTH); } + inline void clksel_set(uint32_t value) { this->set_field(value, PWM_T3_CONFIG_CLKSEL_BIT, PWM_T3_CONFIG_CLKSEL_WIDTH); } + inline uint32_t clksel_get() { return this->get_field(PWM_T3_CONFIG_CLKSEL_BIT, PWM_T3_CONFIG_CLKSEL_WIDTH); } + inline void updownsel_set(uint32_t value) { this->set_field(value, PWM_T3_CONFIG_UPDOWNSEL_BIT, PWM_T3_CONFIG_UPDOWNSEL_WIDTH); } + inline uint32_t updownsel_get() { return this->get_field(PWM_T3_CONFIG_UPDOWNSEL_BIT, PWM_T3_CONFIG_UPDOWNSEL_WIDTH); } + inline void presc_set(uint32_t value) { this->set_field(value, PWM_T3_CONFIG_PRESC_BIT, PWM_T3_CONFIG_PRESC_WIDTH); } + inline uint32_t presc_get() { return this->get_field(PWM_T3_CONFIG_PRESC_BIT, PWM_T3_CONFIG_PRESC_WIDTH); } +}; + +class vp_pwm_t3_threshold : public vp::reg_32 +{ +public: + inline void th_lo_set(uint32_t value) { this->set_field(value, PWM_T3_THRESHOLD_TH_LO_BIT, PWM_T3_THRESHOLD_TH_LO_WIDTH); } + inline uint32_t th_lo_get() { return this->get_field(PWM_T3_THRESHOLD_TH_LO_BIT, PWM_T3_THRESHOLD_TH_LO_WIDTH); } + inline void th_hi_set(uint32_t value) { this->set_field(value, PWM_T3_THRESHOLD_TH_HI_BIT, PWM_T3_THRESHOLD_TH_HI_WIDTH); } + inline uint32_t th_hi_get() { return this->get_field(PWM_T3_THRESHOLD_TH_HI_BIT, PWM_T3_THRESHOLD_TH_HI_WIDTH); } +}; + +class vp_pwm_t3_th_channel0 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL0_TH_BIT, PWM_T3_TH_CHANNEL0_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T3_TH_CHANNEL0_TH_BIT, PWM_T3_TH_CHANNEL0_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL0_MODE_BIT, PWM_T3_TH_CHANNEL0_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T3_TH_CHANNEL0_MODE_BIT, PWM_T3_TH_CHANNEL0_MODE_WIDTH); } +}; + +class vp_pwm_t3_th_channel1 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL1_TH_BIT, PWM_T3_TH_CHANNEL1_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T3_TH_CHANNEL1_TH_BIT, PWM_T3_TH_CHANNEL1_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL1_MODE_BIT, PWM_T3_TH_CHANNEL1_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T3_TH_CHANNEL1_MODE_BIT, PWM_T3_TH_CHANNEL1_MODE_WIDTH); } +}; + +class vp_pwm_t3_th_channel2 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL2_TH_BIT, PWM_T3_TH_CHANNEL2_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T3_TH_CHANNEL2_TH_BIT, PWM_T3_TH_CHANNEL2_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL2_MODE_BIT, PWM_T3_TH_CHANNEL2_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T3_TH_CHANNEL2_MODE_BIT, PWM_T3_TH_CHANNEL2_MODE_WIDTH); } +}; + +class vp_pwm_t3_th_channel3 : public vp::reg_32 +{ +public: + inline void th_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL3_TH_BIT, PWM_T3_TH_CHANNEL3_TH_WIDTH); } + inline uint32_t th_get() { return this->get_field(PWM_T3_TH_CHANNEL3_TH_BIT, PWM_T3_TH_CHANNEL3_TH_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, PWM_T3_TH_CHANNEL3_MODE_BIT, PWM_T3_TH_CHANNEL3_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(PWM_T3_TH_CHANNEL3_MODE_BIT, PWM_T3_TH_CHANNEL3_MODE_WIDTH); } +}; + +class vp_pwm_t3_counter : public vp::reg_32 +{ +public: +}; + +class vp_pwm_event_cfg : public vp::reg_32 +{ +public: + inline void sel0_set(uint32_t value) { this->set_field(value, PWM_EVENT_CFG_SEL0_BIT, PWM_EVENT_CFG_SEL0_WIDTH); } + inline uint32_t sel0_get() { return this->get_field(PWM_EVENT_CFG_SEL0_BIT, PWM_EVENT_CFG_SEL0_WIDTH); } + inline void sel1_set(uint32_t value) { this->set_field(value, PWM_EVENT_CFG_SEL1_BIT, PWM_EVENT_CFG_SEL1_WIDTH); } + inline uint32_t sel1_get() { return this->get_field(PWM_EVENT_CFG_SEL1_BIT, PWM_EVENT_CFG_SEL1_WIDTH); } + inline void sel2_set(uint32_t value) { this->set_field(value, PWM_EVENT_CFG_SEL2_BIT, PWM_EVENT_CFG_SEL2_WIDTH); } + inline uint32_t sel2_get() { return this->get_field(PWM_EVENT_CFG_SEL2_BIT, PWM_EVENT_CFG_SEL2_WIDTH); } + inline void sel3_set(uint32_t value) { this->set_field(value, PWM_EVENT_CFG_SEL3_BIT, PWM_EVENT_CFG_SEL3_WIDTH); } + inline uint32_t sel3_get() { return this->get_field(PWM_EVENT_CFG_SEL3_BIT, PWM_EVENT_CFG_SEL3_WIDTH); } + inline void ena_set(uint32_t value) { this->set_field(value, PWM_EVENT_CFG_ENA_BIT, PWM_EVENT_CFG_ENA_WIDTH); } + inline uint32_t ena_get() { return this->get_field(PWM_EVENT_CFG_ENA_BIT, PWM_EVENT_CFG_ENA_WIDTH); } +}; + +class vp_pwm_cg : public vp::reg_32 +{ +public: + inline void ena_set(uint32_t value) { this->set_field(value, PWM_CG_ENA_BIT, PWM_CG_ENA_WIDTH); } + inline uint32_t ena_get() { return this->get_field(PWM_CG_ENA_BIT, PWM_CG_ENA_WIDTH); } +}; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_macros.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_macros.h new file mode 100644 index 0000000..2602cab --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_macros.h @@ -0,0 +1,473 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_MACROS_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_MACROS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS FIELDS MACROS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#define PWM_T0_CMD_START_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define PWM_T0_CMD_START_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define PWM_T0_CMD_START_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define PWM_T0_CMD_START(val) ((val) << 0) + +#define PWM_T0_CMD_STOP_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define PWM_T0_CMD_STOP_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define PWM_T0_CMD_STOP_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define PWM_T0_CMD_STOP(val) ((val) << 1) + +#define PWM_T0_CMD_UPDATE_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define PWM_T0_CMD_UPDATE_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define PWM_T0_CMD_UPDATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define PWM_T0_CMD_UPDATE(val) ((val) << 2) + +#define PWM_T0_CMD_RESET_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define PWM_T0_CMD_RESET_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define PWM_T0_CMD_RESET_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define PWM_T0_CMD_RESET(val) ((val) << 3) + +#define PWM_T0_CMD_ARM_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define PWM_T0_CMD_ARM_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define PWM_T0_CMD_ARM_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define PWM_T0_CMD_ARM(val) ((val) << 4) + +#define PWM_T0_CONFIG_INSEL_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define PWM_T0_CONFIG_INSEL_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define PWM_T0_CONFIG_INSEL_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define PWM_T0_CONFIG_INSEL(val) ((val) << 0) + +#define PWM_T0_CONFIG_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,8)) +#define PWM_T0_CONFIG_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,8)) +#define PWM_T0_CONFIG_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,8)) +#define PWM_T0_CONFIG_MODE(val) ((val) << 8) + +#define PWM_T0_CONFIG_CLKSEL_GET(value) (ARCHI_BEXTRACTU((value),1,11)) +#define PWM_T0_CONFIG_CLKSEL_GETS(value) (ARCHI_BEXTRACT((value),1,11)) +#define PWM_T0_CONFIG_CLKSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,11)) +#define PWM_T0_CONFIG_CLKSEL(val) ((val) << 11) + +#define PWM_T0_CONFIG_UPDOWNSEL_GET(value) (ARCHI_BEXTRACTU((value),1,12)) +#define PWM_T0_CONFIG_UPDOWNSEL_GETS(value) (ARCHI_BEXTRACT((value),1,12)) +#define PWM_T0_CONFIG_UPDOWNSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,12)) +#define PWM_T0_CONFIG_UPDOWNSEL(val) ((val) << 12) + +#define PWM_T0_CONFIG_PRESC_GET(value) (ARCHI_BEXTRACTU((value),8,16)) +#define PWM_T0_CONFIG_PRESC_GETS(value) (ARCHI_BEXTRACT((value),8,16)) +#define PWM_T0_CONFIG_PRESC_SET(value,field) (ARCHI_BINSERT((value),(field),8,16)) +#define PWM_T0_CONFIG_PRESC(val) ((val) << 16) + +#define PWM_T0_THRESHOLD_TH_LO_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T0_THRESHOLD_TH_LO_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T0_THRESHOLD_TH_LO_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T0_THRESHOLD_TH_LO(val) ((val) << 0) + +#define PWM_T0_THRESHOLD_TH_HI_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define PWM_T0_THRESHOLD_TH_HI_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define PWM_T0_THRESHOLD_TH_HI_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define PWM_T0_THRESHOLD_TH_HI(val) ((val) << 16) + +#define PWM_T0_TH_CHANNEL0_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T0_TH_CHANNEL0_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T0_TH_CHANNEL0_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T0_TH_CHANNEL0_TH(val) ((val) << 0) + +#define PWM_T0_TH_CHANNEL0_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T0_TH_CHANNEL0_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T0_TH_CHANNEL0_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T0_TH_CHANNEL0_MODE(val) ((val) << 16) + +#define PWM_T0_TH_CHANNEL1_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T0_TH_CHANNEL1_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T0_TH_CHANNEL1_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T0_TH_CHANNEL1_TH(val) ((val) << 0) + +#define PWM_T0_TH_CHANNEL1_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T0_TH_CHANNEL1_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T0_TH_CHANNEL1_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T0_TH_CHANNEL1_MODE(val) ((val) << 16) + +#define PWM_T0_TH_CHANNEL2_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T0_TH_CHANNEL2_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T0_TH_CHANNEL2_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T0_TH_CHANNEL2_TH(val) ((val) << 0) + +#define PWM_T0_TH_CHANNEL2_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T0_TH_CHANNEL2_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T0_TH_CHANNEL2_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T0_TH_CHANNEL2_MODE(val) ((val) << 16) + +#define PWM_T0_TH_CHANNEL3_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T0_TH_CHANNEL3_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T0_TH_CHANNEL3_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T0_TH_CHANNEL3_TH(val) ((val) << 0) + +#define PWM_T0_TH_CHANNEL3_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T0_TH_CHANNEL3_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T0_TH_CHANNEL3_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T0_TH_CHANNEL3_MODE(val) ((val) << 16) + +#define PWM_T1_CMD_START_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define PWM_T1_CMD_START_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define PWM_T1_CMD_START_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define PWM_T1_CMD_START(val) ((val) << 0) + +#define PWM_T1_CMD_STOP_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define PWM_T1_CMD_STOP_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define PWM_T1_CMD_STOP_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define PWM_T1_CMD_STOP(val) ((val) << 1) + +#define PWM_T1_CMD_UPDATE_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define PWM_T1_CMD_UPDATE_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define PWM_T1_CMD_UPDATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define PWM_T1_CMD_UPDATE(val) ((val) << 2) + +#define PWM_T1_CMD_RESET_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define PWM_T1_CMD_RESET_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define PWM_T1_CMD_RESET_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define PWM_T1_CMD_RESET(val) ((val) << 3) + +#define PWM_T1_CMD_ARM_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define PWM_T1_CMD_ARM_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define PWM_T1_CMD_ARM_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define PWM_T1_CMD_ARM(val) ((val) << 4) + +#define PWM_T1_CONFIG_INSEL_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define PWM_T1_CONFIG_INSEL_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define PWM_T1_CONFIG_INSEL_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define PWM_T1_CONFIG_INSEL(val) ((val) << 0) + +#define PWM_T1_CONFIG_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,8)) +#define PWM_T1_CONFIG_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,8)) +#define PWM_T1_CONFIG_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,8)) +#define PWM_T1_CONFIG_MODE(val) ((val) << 8) + +#define PWM_T1_CONFIG_CLKSEL_GET(value) (ARCHI_BEXTRACTU((value),1,11)) +#define PWM_T1_CONFIG_CLKSEL_GETS(value) (ARCHI_BEXTRACT((value),1,11)) +#define PWM_T1_CONFIG_CLKSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,11)) +#define PWM_T1_CONFIG_CLKSEL(val) ((val) << 11) + +#define PWM_T1_CONFIG_UPDOWNSEL_GET(value) (ARCHI_BEXTRACTU((value),1,12)) +#define PWM_T1_CONFIG_UPDOWNSEL_GETS(value) (ARCHI_BEXTRACT((value),1,12)) +#define PWM_T1_CONFIG_UPDOWNSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,12)) +#define PWM_T1_CONFIG_UPDOWNSEL(val) ((val) << 12) + +#define PWM_T1_CONFIG_PRESC_GET(value) (ARCHI_BEXTRACTU((value),8,16)) +#define PWM_T1_CONFIG_PRESC_GETS(value) (ARCHI_BEXTRACT((value),8,16)) +#define PWM_T1_CONFIG_PRESC_SET(value,field) (ARCHI_BINSERT((value),(field),8,16)) +#define PWM_T1_CONFIG_PRESC(val) ((val) << 16) + +#define PWM_T1_THRESHOLD_TH_LO_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T1_THRESHOLD_TH_LO_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T1_THRESHOLD_TH_LO_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T1_THRESHOLD_TH_LO(val) ((val) << 0) + +#define PWM_T1_THRESHOLD_TH_HI_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define PWM_T1_THRESHOLD_TH_HI_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define PWM_T1_THRESHOLD_TH_HI_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define PWM_T1_THRESHOLD_TH_HI(val) ((val) << 16) + +#define PWM_T1_TH_CHANNEL0_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T1_TH_CHANNEL0_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T1_TH_CHANNEL0_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T1_TH_CHANNEL0_TH(val) ((val) << 0) + +#define PWM_T1_TH_CHANNEL0_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T1_TH_CHANNEL0_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T1_TH_CHANNEL0_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T1_TH_CHANNEL0_MODE(val) ((val) << 16) + +#define PWM_T1_TH_CHANNEL1_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T1_TH_CHANNEL1_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T1_TH_CHANNEL1_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T1_TH_CHANNEL1_TH(val) ((val) << 0) + +#define PWM_T1_TH_CHANNEL1_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T1_TH_CHANNEL1_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T1_TH_CHANNEL1_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T1_TH_CHANNEL1_MODE(val) ((val) << 16) + +#define PWM_T1_TH_CHANNEL2_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T1_TH_CHANNEL2_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T1_TH_CHANNEL2_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T1_TH_CHANNEL2_TH(val) ((val) << 0) + +#define PWM_T1_TH_CHANNEL2_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T1_TH_CHANNEL2_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T1_TH_CHANNEL2_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T1_TH_CHANNEL2_MODE(val) ((val) << 16) + +#define PWM_T1_TH_CHANNEL3_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T1_TH_CHANNEL3_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T1_TH_CHANNEL3_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T1_TH_CHANNEL3_TH(val) ((val) << 0) + +#define PWM_T1_TH_CHANNEL3_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T1_TH_CHANNEL3_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T1_TH_CHANNEL3_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T1_TH_CHANNEL3_MODE(val) ((val) << 16) + +#define PWM_T2_CMD_START_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define PWM_T2_CMD_START_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define PWM_T2_CMD_START_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define PWM_T2_CMD_START(val) ((val) << 0) + +#define PWM_T2_CMD_STOP_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define PWM_T2_CMD_STOP_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define PWM_T2_CMD_STOP_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define PWM_T2_CMD_STOP(val) ((val) << 1) + +#define PWM_T2_CMD_UPDATE_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define PWM_T2_CMD_UPDATE_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define PWM_T2_CMD_UPDATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define PWM_T2_CMD_UPDATE(val) ((val) << 2) + +#define PWM_T2_CMD_RESET_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define PWM_T2_CMD_RESET_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define PWM_T2_CMD_RESET_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define PWM_T2_CMD_RESET(val) ((val) << 3) + +#define PWM_T2_CMD_ARM_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define PWM_T2_CMD_ARM_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define PWM_T2_CMD_ARM_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define PWM_T2_CMD_ARM(val) ((val) << 4) + +#define PWM_T2_CONFIG_INSEL_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define PWM_T2_CONFIG_INSEL_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define PWM_T2_CONFIG_INSEL_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define PWM_T2_CONFIG_INSEL(val) ((val) << 0) + +#define PWM_T2_CONFIG_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,8)) +#define PWM_T2_CONFIG_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,8)) +#define PWM_T2_CONFIG_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,8)) +#define PWM_T2_CONFIG_MODE(val) ((val) << 8) + +#define PWM_T2_CONFIG_CLKSEL_GET(value) (ARCHI_BEXTRACTU((value),1,11)) +#define PWM_T2_CONFIG_CLKSEL_GETS(value) (ARCHI_BEXTRACT((value),1,11)) +#define PWM_T2_CONFIG_CLKSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,11)) +#define PWM_T2_CONFIG_CLKSEL(val) ((val) << 11) + +#define PWM_T2_CONFIG_UPDOWNSEL_GET(value) (ARCHI_BEXTRACTU((value),1,12)) +#define PWM_T2_CONFIG_UPDOWNSEL_GETS(value) (ARCHI_BEXTRACT((value),1,12)) +#define PWM_T2_CONFIG_UPDOWNSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,12)) +#define PWM_T2_CONFIG_UPDOWNSEL(val) ((val) << 12) + +#define PWM_T2_CONFIG_PRESC_GET(value) (ARCHI_BEXTRACTU((value),8,16)) +#define PWM_T2_CONFIG_PRESC_GETS(value) (ARCHI_BEXTRACT((value),8,16)) +#define PWM_T2_CONFIG_PRESC_SET(value,field) (ARCHI_BINSERT((value),(field),8,16)) +#define PWM_T2_CONFIG_PRESC(val) ((val) << 16) + +#define PWM_T2_THRESHOLD_TH_LO_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T2_THRESHOLD_TH_LO_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T2_THRESHOLD_TH_LO_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T2_THRESHOLD_TH_LO(val) ((val) << 0) + +#define PWM_T2_THRESHOLD_TH_HI_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define PWM_T2_THRESHOLD_TH_HI_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define PWM_T2_THRESHOLD_TH_HI_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define PWM_T2_THRESHOLD_TH_HI(val) ((val) << 16) + +#define PWM_T2_TH_CHANNEL0_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T2_TH_CHANNEL0_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T2_TH_CHANNEL0_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T2_TH_CHANNEL0_TH(val) ((val) << 0) + +#define PWM_T2_TH_CHANNEL0_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T2_TH_CHANNEL0_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T2_TH_CHANNEL0_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T2_TH_CHANNEL0_MODE(val) ((val) << 16) + +#define PWM_T2_TH_CHANNEL1_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T2_TH_CHANNEL1_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T2_TH_CHANNEL1_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T2_TH_CHANNEL1_TH(val) ((val) << 0) + +#define PWM_T2_TH_CHANNEL1_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T2_TH_CHANNEL1_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T2_TH_CHANNEL1_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T2_TH_CHANNEL1_MODE(val) ((val) << 16) + +#define PWM_T2_TH_CHANNEL2_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T2_TH_CHANNEL2_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T2_TH_CHANNEL2_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T2_TH_CHANNEL2_TH(val) ((val) << 0) + +#define PWM_T2_TH_CHANNEL2_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T2_TH_CHANNEL2_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T2_TH_CHANNEL2_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T2_TH_CHANNEL2_MODE(val) ((val) << 16) + +#define PWM_T2_TH_CHANNEL3_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T2_TH_CHANNEL3_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T2_TH_CHANNEL3_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T2_TH_CHANNEL3_TH(val) ((val) << 0) + +#define PWM_T2_TH_CHANNEL3_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T2_TH_CHANNEL3_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T2_TH_CHANNEL3_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T2_TH_CHANNEL3_MODE(val) ((val) << 16) + +#define PWM_T3_CMD_START_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define PWM_T3_CMD_START_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define PWM_T3_CMD_START_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define PWM_T3_CMD_START(val) ((val) << 0) + +#define PWM_T3_CMD_STOP_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define PWM_T3_CMD_STOP_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define PWM_T3_CMD_STOP_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define PWM_T3_CMD_STOP(val) ((val) << 1) + +#define PWM_T3_CMD_UPDATE_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define PWM_T3_CMD_UPDATE_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define PWM_T3_CMD_UPDATE_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define PWM_T3_CMD_UPDATE(val) ((val) << 2) + +#define PWM_T3_CMD_RESET_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define PWM_T3_CMD_RESET_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define PWM_T3_CMD_RESET_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define PWM_T3_CMD_RESET(val) ((val) << 3) + +#define PWM_T3_CMD_ARM_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define PWM_T3_CMD_ARM_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define PWM_T3_CMD_ARM_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define PWM_T3_CMD_ARM(val) ((val) << 4) + +#define PWM_T3_CONFIG_INSEL_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define PWM_T3_CONFIG_INSEL_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define PWM_T3_CONFIG_INSEL_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define PWM_T3_CONFIG_INSEL(val) ((val) << 0) + +#define PWM_T3_CONFIG_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,8)) +#define PWM_T3_CONFIG_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,8)) +#define PWM_T3_CONFIG_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,8)) +#define PWM_T3_CONFIG_MODE(val) ((val) << 8) + +#define PWM_T3_CONFIG_CLKSEL_GET(value) (ARCHI_BEXTRACTU((value),1,11)) +#define PWM_T3_CONFIG_CLKSEL_GETS(value) (ARCHI_BEXTRACT((value),1,11)) +#define PWM_T3_CONFIG_CLKSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,11)) +#define PWM_T3_CONFIG_CLKSEL(val) ((val) << 11) + +#define PWM_T3_CONFIG_UPDOWNSEL_GET(value) (ARCHI_BEXTRACTU((value),1,12)) +#define PWM_T3_CONFIG_UPDOWNSEL_GETS(value) (ARCHI_BEXTRACT((value),1,12)) +#define PWM_T3_CONFIG_UPDOWNSEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,12)) +#define PWM_T3_CONFIG_UPDOWNSEL(val) ((val) << 12) + +#define PWM_T3_CONFIG_PRESC_GET(value) (ARCHI_BEXTRACTU((value),8,16)) +#define PWM_T3_CONFIG_PRESC_GETS(value) (ARCHI_BEXTRACT((value),8,16)) +#define PWM_T3_CONFIG_PRESC_SET(value,field) (ARCHI_BINSERT((value),(field),8,16)) +#define PWM_T3_CONFIG_PRESC(val) ((val) << 16) + +#define PWM_T3_THRESHOLD_TH_LO_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T3_THRESHOLD_TH_LO_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T3_THRESHOLD_TH_LO_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T3_THRESHOLD_TH_LO(val) ((val) << 0) + +#define PWM_T3_THRESHOLD_TH_HI_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define PWM_T3_THRESHOLD_TH_HI_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define PWM_T3_THRESHOLD_TH_HI_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define PWM_T3_THRESHOLD_TH_HI(val) ((val) << 16) + +#define PWM_T3_TH_CHANNEL0_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T3_TH_CHANNEL0_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T3_TH_CHANNEL0_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T3_TH_CHANNEL0_TH(val) ((val) << 0) + +#define PWM_T3_TH_CHANNEL0_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T3_TH_CHANNEL0_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T3_TH_CHANNEL0_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T3_TH_CHANNEL0_MODE(val) ((val) << 16) + +#define PWM_T3_TH_CHANNEL1_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T3_TH_CHANNEL1_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T3_TH_CHANNEL1_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T3_TH_CHANNEL1_TH(val) ((val) << 0) + +#define PWM_T3_TH_CHANNEL1_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T3_TH_CHANNEL1_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T3_TH_CHANNEL1_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T3_TH_CHANNEL1_MODE(val) ((val) << 16) + +#define PWM_T3_TH_CHANNEL2_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T3_TH_CHANNEL2_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T3_TH_CHANNEL2_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T3_TH_CHANNEL2_TH(val) ((val) << 0) + +#define PWM_T3_TH_CHANNEL2_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T3_TH_CHANNEL2_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T3_TH_CHANNEL2_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T3_TH_CHANNEL2_MODE(val) ((val) << 16) + +#define PWM_T3_TH_CHANNEL3_TH_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_T3_TH_CHANNEL3_TH_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_T3_TH_CHANNEL3_TH_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_T3_TH_CHANNEL3_TH(val) ((val) << 0) + +#define PWM_T3_TH_CHANNEL3_MODE_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define PWM_T3_TH_CHANNEL3_MODE_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define PWM_T3_TH_CHANNEL3_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define PWM_T3_TH_CHANNEL3_MODE(val) ((val) << 16) + +#define PWM_EVENT_CFG_SEL0_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define PWM_EVENT_CFG_SEL0_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define PWM_EVENT_CFG_SEL0_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define PWM_EVENT_CFG_SEL0(val) ((val) << 0) + +#define PWM_EVENT_CFG_SEL1_GET(value) (ARCHI_BEXTRACTU((value),4,4)) +#define PWM_EVENT_CFG_SEL1_GETS(value) (ARCHI_BEXTRACT((value),4,4)) +#define PWM_EVENT_CFG_SEL1_SET(value,field) (ARCHI_BINSERT((value),(field),4,4)) +#define PWM_EVENT_CFG_SEL1(val) ((val) << 4) + +#define PWM_EVENT_CFG_SEL2_GET(value) (ARCHI_BEXTRACTU((value),4,8)) +#define PWM_EVENT_CFG_SEL2_GETS(value) (ARCHI_BEXTRACT((value),4,8)) +#define PWM_EVENT_CFG_SEL2_SET(value,field) (ARCHI_BINSERT((value),(field),4,8)) +#define PWM_EVENT_CFG_SEL2(val) ((val) << 8) + +#define PWM_EVENT_CFG_SEL3_GET(value) (ARCHI_BEXTRACTU((value),4,12)) +#define PWM_EVENT_CFG_SEL3_GETS(value) (ARCHI_BEXTRACT((value),4,12)) +#define PWM_EVENT_CFG_SEL3_SET(value,field) (ARCHI_BINSERT((value),(field),4,12)) +#define PWM_EVENT_CFG_SEL3(val) ((val) << 12) + +#define PWM_EVENT_CFG_ENA_GET(value) (ARCHI_BEXTRACTU((value),4,16)) +#define PWM_EVENT_CFG_ENA_GETS(value) (ARCHI_BEXTRACT((value),4,16)) +#define PWM_EVENT_CFG_ENA_SET(value,field) (ARCHI_BINSERT((value),(field),4,16)) +#define PWM_EVENT_CFG_ENA(val) ((val) << 16) + +#define PWM_CG_ENA_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define PWM_CG_ENA_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define PWM_CG_ENA_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define PWM_CG_ENA(val) ((val) << 0) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regfields.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regfields.h new file mode 100644 index 0000000..a0abc45 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regfields.h @@ -0,0 +1,469 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_REGFIELDS_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_REGFIELDS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS FIELDS +// + +// ADV_TIMER0 start command bitfield. (access: R/W) +#define PWM_T0_CMD_START_BIT 0 +#define PWM_T0_CMD_START_WIDTH 1 +#define PWM_T0_CMD_START_MASK 0x1 + +// ADV_TIMER0 stop command bitfield. (access: R/W) +#define PWM_T0_CMD_STOP_BIT 1 +#define PWM_T0_CMD_STOP_WIDTH 1 +#define PWM_T0_CMD_STOP_MASK 0x2 + +// ADV_TIMER0 update command bitfield. (access: R/W) +#define PWM_T0_CMD_UPDATE_BIT 2 +#define PWM_T0_CMD_UPDATE_WIDTH 1 +#define PWM_T0_CMD_UPDATE_MASK 0x4 + +// ADV_TIMER0 reset command bitfield. (access: R/W) +#define PWM_T0_CMD_RESET_BIT 3 +#define PWM_T0_CMD_RESET_WIDTH 1 +#define PWM_T0_CMD_RESET_MASK 0x8 + +// ADV_TIMER0 arm command bitfield. (access: R/W) +#define PWM_T0_CMD_ARM_BIT 4 +#define PWM_T0_CMD_ARM_WIDTH 1 +#define PWM_T0_CMD_ARM_MASK 0x10 + +// ADV_TIMER0 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 (access: R/W) +#define PWM_T0_CONFIG_INSEL_BIT 0 +#define PWM_T0_CONFIG_INSEL_WIDTH 8 +#define PWM_T0_CONFIG_INSEL_MASK 0xff + +// ADV_TIMER0 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed (access: R/W) +#define PWM_T0_CONFIG_MODE_BIT 8 +#define PWM_T0_CONFIG_MODE_WIDTH 3 +#define PWM_T0_CONFIG_MODE_MASK 0x700 + +// ADV_TIMER0 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz (access: R/W) +#define PWM_T0_CONFIG_CLKSEL_BIT 11 +#define PWM_T0_CONFIG_CLKSEL_WIDTH 1 +#define PWM_T0_CONFIG_CLKSEL_MASK 0x800 + +// ADV_TIMER0 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. (access: R/W) +#define PWM_T0_CONFIG_UPDOWNSEL_BIT 12 +#define PWM_T0_CONFIG_UPDOWNSEL_WIDTH 1 +#define PWM_T0_CONFIG_UPDOWNSEL_MASK 0x1000 + +// ADV_TIMER0 prescaler value configuration bitfield. (access: R/W) +#define PWM_T0_CONFIG_PRESC_BIT 16 +#define PWM_T0_CONFIG_PRESC_WIDTH 8 +#define PWM_T0_CONFIG_PRESC_MASK 0xff0000 + +// ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. (access: R/W) +#define PWM_T0_THRESHOLD_TH_LO_BIT 0 +#define PWM_T0_THRESHOLD_TH_LO_WIDTH 16 +#define PWM_T0_THRESHOLD_TH_LO_MASK 0xffff + +// ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value. (access: R/W) +#define PWM_T0_THRESHOLD_TH_HI_BIT 16 +#define PWM_T0_THRESHOLD_TH_HI_WIDTH 16 +#define PWM_T0_THRESHOLD_TH_HI_MASK 0xffff0000 + +// ADV_TIMER0 channel 0 threshold configuration bitfield. (access: R/W) +#define PWM_T0_TH_CHANNEL0_TH_BIT 0 +#define PWM_T0_TH_CHANNEL0_TH_WIDTH 16 +#define PWM_T0_TH_CHANNEL0_TH_MASK 0xffff + +// ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T0_TH_CHANNEL0_MODE_BIT 16 +#define PWM_T0_TH_CHANNEL0_MODE_WIDTH 3 +#define PWM_T0_TH_CHANNEL0_MODE_MASK 0x70000 + +// ADV_TIMER0 channel 1 threshold configuration bitfield. (access: R/W) +#define PWM_T0_TH_CHANNEL1_TH_BIT 0 +#define PWM_T0_TH_CHANNEL1_TH_WIDTH 16 +#define PWM_T0_TH_CHANNEL1_TH_MASK 0xffff + +// ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T0_TH_CHANNEL1_MODE_BIT 16 +#define PWM_T0_TH_CHANNEL1_MODE_WIDTH 3 +#define PWM_T0_TH_CHANNEL1_MODE_MASK 0x70000 + +// ADV_TIMER0 channel 2 threshold configuration bitfield. (access: R/W) +#define PWM_T0_TH_CHANNEL2_TH_BIT 0 +#define PWM_T0_TH_CHANNEL2_TH_WIDTH 16 +#define PWM_T0_TH_CHANNEL2_TH_MASK 0xffff + +// ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T0_TH_CHANNEL2_MODE_BIT 16 +#define PWM_T0_TH_CHANNEL2_MODE_WIDTH 3 +#define PWM_T0_TH_CHANNEL2_MODE_MASK 0x70000 + +// ADV_TIMER0 channel 3 threshold configuration bitfield. (access: R/W) +#define PWM_T0_TH_CHANNEL3_TH_BIT 0 +#define PWM_T0_TH_CHANNEL3_TH_WIDTH 16 +#define PWM_T0_TH_CHANNEL3_TH_MASK 0xffff + +// ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T0_TH_CHANNEL3_MODE_BIT 16 +#define PWM_T0_TH_CHANNEL3_MODE_WIDTH 3 +#define PWM_T0_TH_CHANNEL3_MODE_MASK 0x70000 + +// ADV_TIMER1 start command bitfield. (access: R/W) +#define PWM_T1_CMD_START_BIT 0 +#define PWM_T1_CMD_START_WIDTH 1 +#define PWM_T1_CMD_START_MASK 0x1 + +// ADV_TIMER1 stop command bitfield. (access: R/W) +#define PWM_T1_CMD_STOP_BIT 1 +#define PWM_T1_CMD_STOP_WIDTH 1 +#define PWM_T1_CMD_STOP_MASK 0x2 + +// ADV_TIMER1 update command bitfield. (access: R/W) +#define PWM_T1_CMD_UPDATE_BIT 2 +#define PWM_T1_CMD_UPDATE_WIDTH 1 +#define PWM_T1_CMD_UPDATE_MASK 0x4 + +// ADV_TIMER1 reset command bitfield. (access: R/W) +#define PWM_T1_CMD_RESET_BIT 3 +#define PWM_T1_CMD_RESET_WIDTH 1 +#define PWM_T1_CMD_RESET_MASK 0x8 + +// ADV_TIMER1 arm command bitfield. (access: R/W) +#define PWM_T1_CMD_ARM_BIT 4 +#define PWM_T1_CMD_ARM_WIDTH 1 +#define PWM_T1_CMD_ARM_MASK 0x10 + +// ADV_TIMER1 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 (access: R/W) +#define PWM_T1_CONFIG_INSEL_BIT 0 +#define PWM_T1_CONFIG_INSEL_WIDTH 8 +#define PWM_T1_CONFIG_INSEL_MASK 0xff + +// ADV_TIMER1 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed (access: R/W) +#define PWM_T1_CONFIG_MODE_BIT 8 +#define PWM_T1_CONFIG_MODE_WIDTH 3 +#define PWM_T1_CONFIG_MODE_MASK 0x700 + +// ADV_TIMER1 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz (access: R/W) +#define PWM_T1_CONFIG_CLKSEL_BIT 11 +#define PWM_T1_CONFIG_CLKSEL_WIDTH 1 +#define PWM_T1_CONFIG_CLKSEL_MASK 0x800 + +// ADV_TIMER1 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. (access: R/W) +#define PWM_T1_CONFIG_UPDOWNSEL_BIT 12 +#define PWM_T1_CONFIG_UPDOWNSEL_WIDTH 1 +#define PWM_T1_CONFIG_UPDOWNSEL_MASK 0x1000 + +// ADV_TIMER1 prescaler value configuration bitfield. (access: R/W) +#define PWM_T1_CONFIG_PRESC_BIT 16 +#define PWM_T1_CONFIG_PRESC_WIDTH 8 +#define PWM_T1_CONFIG_PRESC_MASK 0xff0000 + +// ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value. (access: R/W) +#define PWM_T1_THRESHOLD_TH_LO_BIT 0 +#define PWM_T1_THRESHOLD_TH_LO_WIDTH 16 +#define PWM_T1_THRESHOLD_TH_LO_MASK 0xffff + +// ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value. (access: R/W) +#define PWM_T1_THRESHOLD_TH_HI_BIT 16 +#define PWM_T1_THRESHOLD_TH_HI_WIDTH 16 +#define PWM_T1_THRESHOLD_TH_HI_MASK 0xffff0000 + +// ADV_TIMER1 channel 0 threshold configuration bitfield. (access: R/W) +#define PWM_T1_TH_CHANNEL0_TH_BIT 0 +#define PWM_T1_TH_CHANNEL0_TH_WIDTH 16 +#define PWM_T1_TH_CHANNEL0_TH_MASK 0xffff + +// ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T1_TH_CHANNEL0_MODE_BIT 16 +#define PWM_T1_TH_CHANNEL0_MODE_WIDTH 3 +#define PWM_T1_TH_CHANNEL0_MODE_MASK 0x70000 + +// ADV_TIMER1 channel 1 threshold configuration bitfield. (access: R/W) +#define PWM_T1_TH_CHANNEL1_TH_BIT 0 +#define PWM_T1_TH_CHANNEL1_TH_WIDTH 16 +#define PWM_T1_TH_CHANNEL1_TH_MASK 0xffff + +// ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T1_TH_CHANNEL1_MODE_BIT 16 +#define PWM_T1_TH_CHANNEL1_MODE_WIDTH 3 +#define PWM_T1_TH_CHANNEL1_MODE_MASK 0x70000 + +// ADV_TIMER1 channel 2 threshold configuration bitfield. (access: R/W) +#define PWM_T1_TH_CHANNEL2_TH_BIT 0 +#define PWM_T1_TH_CHANNEL2_TH_WIDTH 16 +#define PWM_T1_TH_CHANNEL2_TH_MASK 0xffff + +// ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T1_TH_CHANNEL2_MODE_BIT 16 +#define PWM_T1_TH_CHANNEL2_MODE_WIDTH 3 +#define PWM_T1_TH_CHANNEL2_MODE_MASK 0x70000 + +// ADV_TIMER1 channel 3 threshold configuration bitfield. (access: R/W) +#define PWM_T1_TH_CHANNEL3_TH_BIT 0 +#define PWM_T1_TH_CHANNEL3_TH_WIDTH 16 +#define PWM_T1_TH_CHANNEL3_TH_MASK 0xffff + +// ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T1_TH_CHANNEL3_MODE_BIT 16 +#define PWM_T1_TH_CHANNEL3_MODE_WIDTH 3 +#define PWM_T1_TH_CHANNEL3_MODE_MASK 0x70000 + +// ADV_TIMER2 start command bitfield. (access: R/W) +#define PWM_T2_CMD_START_BIT 0 +#define PWM_T2_CMD_START_WIDTH 1 +#define PWM_T2_CMD_START_MASK 0x1 + +// ADV_TIMER2 stop command bitfield. (access: R/W) +#define PWM_T2_CMD_STOP_BIT 1 +#define PWM_T2_CMD_STOP_WIDTH 1 +#define PWM_T2_CMD_STOP_MASK 0x2 + +// ADV_TIMER2 update command bitfield. (access: R/W) +#define PWM_T2_CMD_UPDATE_BIT 2 +#define PWM_T2_CMD_UPDATE_WIDTH 1 +#define PWM_T2_CMD_UPDATE_MASK 0x4 + +// ADV_TIMER2 reset command bitfield. (access: R/W) +#define PWM_T2_CMD_RESET_BIT 3 +#define PWM_T2_CMD_RESET_WIDTH 1 +#define PWM_T2_CMD_RESET_MASK 0x8 + +// ADV_TIMER2 arm command bitfield. (access: R/W) +#define PWM_T2_CMD_ARM_BIT 4 +#define PWM_T2_CMD_ARM_WIDTH 1 +#define PWM_T2_CMD_ARM_MASK 0x10 + +// ADV_TIMER2 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 (access: R/W) +#define PWM_T2_CONFIG_INSEL_BIT 0 +#define PWM_T2_CONFIG_INSEL_WIDTH 8 +#define PWM_T2_CONFIG_INSEL_MASK 0xff + +// ADV_TIMER2 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed (access: R/W) +#define PWM_T2_CONFIG_MODE_BIT 8 +#define PWM_T2_CONFIG_MODE_WIDTH 3 +#define PWM_T2_CONFIG_MODE_MASK 0x700 + +// ADV_TIMER2 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz (access: R/W) +#define PWM_T2_CONFIG_CLKSEL_BIT 11 +#define PWM_T2_CONFIG_CLKSEL_WIDTH 1 +#define PWM_T2_CONFIG_CLKSEL_MASK 0x800 + +// ADV_TIMER2 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. (access: R/W) +#define PWM_T2_CONFIG_UPDOWNSEL_BIT 12 +#define PWM_T2_CONFIG_UPDOWNSEL_WIDTH 1 +#define PWM_T2_CONFIG_UPDOWNSEL_MASK 0x1000 + +// ADV_TIMER2 prescaler value configuration bitfield. (access: R/W) +#define PWM_T2_CONFIG_PRESC_BIT 16 +#define PWM_T2_CONFIG_PRESC_WIDTH 8 +#define PWM_T2_CONFIG_PRESC_MASK 0xff0000 + +// ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value. (access: R/W) +#define PWM_T2_THRESHOLD_TH_LO_BIT 0 +#define PWM_T2_THRESHOLD_TH_LO_WIDTH 16 +#define PWM_T2_THRESHOLD_TH_LO_MASK 0xffff + +// ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value. (access: R/W) +#define PWM_T2_THRESHOLD_TH_HI_BIT 16 +#define PWM_T2_THRESHOLD_TH_HI_WIDTH 16 +#define PWM_T2_THRESHOLD_TH_HI_MASK 0xffff0000 + +// ADV_TIMER2 channel 0 threshold configuration bitfield. (access: R/W) +#define PWM_T2_TH_CHANNEL0_TH_BIT 0 +#define PWM_T2_TH_CHANNEL0_TH_WIDTH 16 +#define PWM_T2_TH_CHANNEL0_TH_MASK 0xffff + +// ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T2_TH_CHANNEL0_MODE_BIT 16 +#define PWM_T2_TH_CHANNEL0_MODE_WIDTH 3 +#define PWM_T2_TH_CHANNEL0_MODE_MASK 0x70000 + +// ADV_TIMER2 channel 1 threshold configuration bitfield. (access: R/W) +#define PWM_T2_TH_CHANNEL1_TH_BIT 0 +#define PWM_T2_TH_CHANNEL1_TH_WIDTH 16 +#define PWM_T2_TH_CHANNEL1_TH_MASK 0xffff + +// ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T2_TH_CHANNEL1_MODE_BIT 16 +#define PWM_T2_TH_CHANNEL1_MODE_WIDTH 3 +#define PWM_T2_TH_CHANNEL1_MODE_MASK 0x70000 + +// ADV_TIMER2 channel 2 threshold configuration bitfield. (access: R/W) +#define PWM_T2_TH_CHANNEL2_TH_BIT 0 +#define PWM_T2_TH_CHANNEL2_TH_WIDTH 16 +#define PWM_T2_TH_CHANNEL2_TH_MASK 0xffff + +// ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T2_TH_CHANNEL2_MODE_BIT 16 +#define PWM_T2_TH_CHANNEL2_MODE_WIDTH 3 +#define PWM_T2_TH_CHANNEL2_MODE_MASK 0x70000 + +// ADV_TIMER2 channel 3 threshold configuration bitfield. (access: R/W) +#define PWM_T2_TH_CHANNEL3_TH_BIT 0 +#define PWM_T2_TH_CHANNEL3_TH_WIDTH 16 +#define PWM_T2_TH_CHANNEL3_TH_MASK 0xffff + +// ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T2_TH_CHANNEL3_MODE_BIT 16 +#define PWM_T2_TH_CHANNEL3_MODE_WIDTH 3 +#define PWM_T2_TH_CHANNEL3_MODE_MASK 0x70000 + +// ADV_TIMER3 start command bitfield. (access: R/W) +#define PWM_T3_CMD_START_BIT 0 +#define PWM_T3_CMD_START_WIDTH 1 +#define PWM_T3_CMD_START_MASK 0x1 + +// ADV_TIMER3 stop command bitfield. (access: R/W) +#define PWM_T3_CMD_STOP_BIT 1 +#define PWM_T3_CMD_STOP_WIDTH 1 +#define PWM_T3_CMD_STOP_MASK 0x2 + +// ADV_TIMER3 update command bitfield. (access: R/W) +#define PWM_T3_CMD_UPDATE_BIT 2 +#define PWM_T3_CMD_UPDATE_WIDTH 1 +#define PWM_T3_CMD_UPDATE_MASK 0x4 + +// ADV_TIMER3 reset command bitfield. (access: R/W) +#define PWM_T3_CMD_RESET_BIT 3 +#define PWM_T3_CMD_RESET_WIDTH 1 +#define PWM_T3_CMD_RESET_MASK 0x8 + +// ADV_TIMER3 arm command bitfield. (access: R/W) +#define PWM_T3_CMD_ARM_BIT 4 +#define PWM_T3_CMD_ARM_WIDTH 1 +#define PWM_T3_CMD_ARM_MASK 0x10 + +// ADV_TIMER3 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 (access: R/W) +#define PWM_T3_CONFIG_INSEL_BIT 0 +#define PWM_T3_CONFIG_INSEL_WIDTH 8 +#define PWM_T3_CONFIG_INSEL_MASK 0xff + +// ADV_TIMER3 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed (access: R/W) +#define PWM_T3_CONFIG_MODE_BIT 8 +#define PWM_T3_CONFIG_MODE_WIDTH 3 +#define PWM_T3_CONFIG_MODE_MASK 0x700 + +// ADV_TIMER3 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz (access: R/W) +#define PWM_T3_CONFIG_CLKSEL_BIT 11 +#define PWM_T3_CONFIG_CLKSEL_WIDTH 1 +#define PWM_T3_CONFIG_CLKSEL_MASK 0x800 + +// ADV_TIMER3 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. (access: R/W) +#define PWM_T3_CONFIG_UPDOWNSEL_BIT 12 +#define PWM_T3_CONFIG_UPDOWNSEL_WIDTH 1 +#define PWM_T3_CONFIG_UPDOWNSEL_MASK 0x1000 + +// ADV_TIMER3 prescaler value configuration bitfield. (access: R/W) +#define PWM_T3_CONFIG_PRESC_BIT 16 +#define PWM_T3_CONFIG_PRESC_WIDTH 8 +#define PWM_T3_CONFIG_PRESC_MASK 0xff0000 + +// ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value. (access: R/W) +#define PWM_T3_THRESHOLD_TH_LO_BIT 0 +#define PWM_T3_THRESHOLD_TH_LO_WIDTH 16 +#define PWM_T3_THRESHOLD_TH_LO_MASK 0xffff + +// ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value. (access: R/W) +#define PWM_T3_THRESHOLD_TH_HI_BIT 16 +#define PWM_T3_THRESHOLD_TH_HI_WIDTH 16 +#define PWM_T3_THRESHOLD_TH_HI_MASK 0xffff0000 + +// ADV_TIMER3 channel 0 threshold configuration bitfield. (access: R/W) +#define PWM_T3_TH_CHANNEL0_TH_BIT 0 +#define PWM_T3_TH_CHANNEL0_TH_WIDTH 16 +#define PWM_T3_TH_CHANNEL0_TH_MASK 0xffff + +// ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T3_TH_CHANNEL0_MODE_BIT 16 +#define PWM_T3_TH_CHANNEL0_MODE_WIDTH 3 +#define PWM_T3_TH_CHANNEL0_MODE_MASK 0x70000 + +// ADV_TIMER3 channel 1 threshold configuration bitfield. (access: R/W) +#define PWM_T3_TH_CHANNEL1_TH_BIT 0 +#define PWM_T3_TH_CHANNEL1_TH_WIDTH 16 +#define PWM_T3_TH_CHANNEL1_TH_MASK 0xffff + +// ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T3_TH_CHANNEL1_MODE_BIT 16 +#define PWM_T3_TH_CHANNEL1_MODE_WIDTH 3 +#define PWM_T3_TH_CHANNEL1_MODE_MASK 0x70000 + +// ADV_TIMER3 channel 2 threshold configuration bitfield. (access: R/W) +#define PWM_T3_TH_CHANNEL2_TH_BIT 0 +#define PWM_T3_TH_CHANNEL2_TH_WIDTH 16 +#define PWM_T3_TH_CHANNEL2_TH_MASK 0xffff + +// ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T3_TH_CHANNEL2_MODE_BIT 16 +#define PWM_T3_TH_CHANNEL2_MODE_WIDTH 3 +#define PWM_T3_TH_CHANNEL2_MODE_MASK 0x70000 + +// ADV_TIMER3 channel 3 threshold configuration bitfield. (access: R/W) +#define PWM_T3_TH_CHANNEL3_TH_BIT 0 +#define PWM_T3_TH_CHANNEL3_TH_WIDTH 16 +#define PWM_T3_TH_CHANNEL3_TH_MASK 0xffff + +// ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. (access: R/W) +#define PWM_T3_TH_CHANNEL3_MODE_BIT 16 +#define PWM_T3_TH_CHANNEL3_MODE_WIDTH 3 +#define PWM_T3_TH_CHANNEL3_MODE_MASK 0x70000 + +// ADV_TIMER output event 0 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. (access: R/W) +#define PWM_EVENT_CFG_SEL0_BIT 0 +#define PWM_EVENT_CFG_SEL0_WIDTH 4 +#define PWM_EVENT_CFG_SEL0_MASK 0xf + +// ADV_TIMER output event 1 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. (access: R/W) +#define PWM_EVENT_CFG_SEL1_BIT 4 +#define PWM_EVENT_CFG_SEL1_WIDTH 4 +#define PWM_EVENT_CFG_SEL1_MASK 0xf0 + +// ADV_TIMER output event 2 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. (access: R/W) +#define PWM_EVENT_CFG_SEL2_BIT 8 +#define PWM_EVENT_CFG_SEL2_WIDTH 4 +#define PWM_EVENT_CFG_SEL2_MASK 0xf00 + +// ADV_TIMER output event 3 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. (access: R/W) +#define PWM_EVENT_CFG_SEL3_BIT 12 +#define PWM_EVENT_CFG_SEL3_WIDTH 4 +#define PWM_EVENT_CFG_SEL3_MASK 0xf000 + +// ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation. (access: R/W) +#define PWM_EVENT_CFG_ENA_BIT 16 +#define PWM_EVENT_CFG_ENA_WIDTH 4 +#define PWM_EVENT_CFG_ENA_MASK 0xf0000 + +// ADV_TIMER clock gating configuration bitfield. - ENA[i]=0: clock gate ADV_TIMERi. - ENA[i]=1: enable ADV_TIMERi. (access: R/W) +#define PWM_CG_ENA_BIT 0 +#define PWM_CG_ENA_WIDTH 16 +#define PWM_CG_ENA_MASK 0xffff + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regmap.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regmap.h new file mode 100644 index 0000000..c2dedfe --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regmap.h @@ -0,0 +1,80 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_REGMAP_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_REGMAP_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS GLOBAL STRUCT +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef struct { + unsigned int t0_cmd ; // ADV_TIMER0 command register. + unsigned int t0_config ; // ADV_TIMER0 configuration register. + unsigned int t0_threshold ; // ADV_TIMER0 threshold configuration register. + unsigned int t0_th_channel0 ; // ADV_TIMER0 channel 0 threshold configuration register. + unsigned int t0_th_channel1 ; // ADV_TIMER0 channel 1 threshold configuration register. + unsigned int t0_th_channel2 ; // ADV_TIMER0 channel 2 threshold configuration register. + unsigned int t0_th_channel3 ; // ADV_TIMER0 channel 3 threshold configuration register. + unsigned int t0_counter ; // ADV_TIMER0 counter register. + unsigned int t1_cmd ; // ADV_TIMER1 command register. + unsigned int t1_config ; // ADV_TIMER1 configuration register. + unsigned int t1_threshold ; // ADV_TIMER1 threshold configuration register. + unsigned int t1_th_channel0 ; // ADV_TIMER1 channel 0 threshold configuration register. + unsigned int t1_th_channel1 ; // ADV_TIMER1 channel 1 threshold configuration register. + unsigned int t1_th_channel2 ; // ADV_TIMER1 channel 2 threshold configuration register. + unsigned int t1_th_channel3 ; // ADV_TIMER1 channel 3 threshold configuration register. + unsigned int t1_counter ; // ADV_TIMER1 counter register. + unsigned int t2_cmd ; // ADV_TIMER2 command register. + unsigned int t2_config ; // ADV_TIMER2 configuration register. + unsigned int t2_threshold ; // ADV_TIMER2 threshold configuration register. + unsigned int t2_th_channel0 ; // ADV_TIMER2 channel 0 threshold configuration register. + unsigned int t2_th_channel1 ; // ADV_TIMER2 channel 1 threshold configuration register. + unsigned int t2_th_channel2 ; // ADV_TIMER2 channel 2 threshold configuration register. + unsigned int t2_th_channel3 ; // ADV_TIMER2 channel 3 threshold configuration register. + unsigned int t2_counter ; // ADV_TIMER2 counter register. + unsigned int t3_cmd ; // ADV_TIMER3 command register. + unsigned int t3_config ; // ADV_TIMER3 configuration register. + unsigned int t3_threshold ; // ADV_TIMER3 threshold configuration register. + unsigned int t3_th_channel0 ; // ADV_TIMER3 channel 0 threshold configuration register. + unsigned int t3_th_channel1 ; // ADV_TIMER3 channel 1 threshold configuration register. + unsigned int t3_th_channel2 ; // ADV_TIMER3 channel 2 threshold configuration register. + unsigned int t3_th_channel3 ; // ADV_TIMER3 channel 3 threshold configuration register. + unsigned int t3_counter ; // ADV_TIMER3 counter register. + unsigned int event_cfg ; // ADV_TIMERS events configuration register. + unsigned int cg ; // ADV_TIMERS channels clock gating configuration register. +} __attribute__((packed)) pwm_pwm_t; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regs.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regs.h new file mode 100644 index 0000000..bd43cd8 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_regs.h @@ -0,0 +1,141 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_REGS_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_REGS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// ADV_TIMER0 command register. +#define PWM_T0_CMD_OFFSET 0x0 + +// ADV_TIMER0 configuration register. +#define PWM_T0_CONFIG_OFFSET 0x4 + +// ADV_TIMER0 threshold configuration register. +#define PWM_T0_THRESHOLD_OFFSET 0x8 + +// ADV_TIMER0 channel 0 threshold configuration register. +#define PWM_T0_TH_CHANNEL0_OFFSET 0xc + +// ADV_TIMER0 channel 1 threshold configuration register. +#define PWM_T0_TH_CHANNEL1_OFFSET 0x10 + +// ADV_TIMER0 channel 2 threshold configuration register. +#define PWM_T0_TH_CHANNEL2_OFFSET 0x14 + +// ADV_TIMER0 channel 3 threshold configuration register. +#define PWM_T0_TH_CHANNEL3_OFFSET 0x18 + +// ADV_TIMER0 counter register. +#define PWM_T0_COUNTER_OFFSET 0x2c + +// ADV_TIMER1 command register. +#define PWM_T1_CMD_OFFSET 0x40 + +// ADV_TIMER1 configuration register. +#define PWM_T1_CONFIG_OFFSET 0x44 + +// ADV_TIMER1 threshold configuration register. +#define PWM_T1_THRESHOLD_OFFSET 0x48 + +// ADV_TIMER1 channel 0 threshold configuration register. +#define PWM_T1_TH_CHANNEL0_OFFSET 0x4c + +// ADV_TIMER1 channel 1 threshold configuration register. +#define PWM_T1_TH_CHANNEL1_OFFSET 0x50 + +// ADV_TIMER1 channel 2 threshold configuration register. +#define PWM_T1_TH_CHANNEL2_OFFSET 0x54 + +// ADV_TIMER1 channel 3 threshold configuration register. +#define PWM_T1_TH_CHANNEL3_OFFSET 0x58 + +// ADV_TIMER1 counter register. +#define PWM_T1_COUNTER_OFFSET 0x6c + +// ADV_TIMER2 command register. +#define PWM_T2_CMD_OFFSET 0x80 + +// ADV_TIMER2 configuration register. +#define PWM_T2_CONFIG_OFFSET 0x84 + +// ADV_TIMER2 threshold configuration register. +#define PWM_T2_THRESHOLD_OFFSET 0x88 + +// ADV_TIMER2 channel 0 threshold configuration register. +#define PWM_T2_TH_CHANNEL0_OFFSET 0x8c + +// ADV_TIMER2 channel 1 threshold configuration register. +#define PWM_T2_TH_CHANNEL1_OFFSET 0x90 + +// ADV_TIMER2 channel 2 threshold configuration register. +#define PWM_T2_TH_CHANNEL2_OFFSET 0x94 + +// ADV_TIMER2 channel 3 threshold configuration register. +#define PWM_T2_TH_CHANNEL3_OFFSET 0x98 + +// ADV_TIMER2 counter register. +#define PWM_T2_COUNTER_OFFSET 0xac + +// ADV_TIMER3 command register. +#define PWM_T3_CMD_OFFSET 0xc0 + +// ADV_TIMER3 configuration register. +#define PWM_T3_CONFIG_OFFSET 0xc4 + +// ADV_TIMER3 threshold configuration register. +#define PWM_T3_THRESHOLD_OFFSET 0xc8 + +// ADV_TIMER3 channel 0 threshold configuration register. +#define PWM_T3_TH_CHANNEL0_OFFSET 0xcc + +// ADV_TIMER3 channel 1 threshold configuration register. +#define PWM_T3_TH_CHANNEL1_OFFSET 0xd0 + +// ADV_TIMER3 channel 2 threshold configuration register. +#define PWM_T3_TH_CHANNEL2_OFFSET 0xd4 + +// ADV_TIMER3 channel 3 threshold configuration register. +#define PWM_T3_TH_CHANNEL3_OFFSET 0xd8 + +// ADV_TIMER3 counter register. +#define PWM_T3_COUNTER_OFFSET 0xec + +// ADV_TIMERS events configuration register. +#define PWM_EVENT_CFG_OFFSET 0x100 + +// ADV_TIMERS channels clock gating configuration register. +#define PWM_CG_OFFSET 0x104 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_structs.h b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_structs.h new file mode 100644 index 0000000..5076808 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/pwm/v1/pwm_v1_structs.h @@ -0,0 +1,337 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_PWM_V1_PWM_V1_STRUCTS_H__ +#define __INCLUDE_ARCHI_PWM_V1_PWM_V1_STRUCTS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS STRUCTS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef union { + struct { + unsigned int start :1 ; // ADV_TIMER0 start command bitfield. + unsigned int stop :1 ; // ADV_TIMER0 stop command bitfield. + unsigned int update :1 ; // ADV_TIMER0 update command bitfield. + unsigned int reset :1 ; // ADV_TIMER0 reset command bitfield. + unsigned int arm :1 ; // ADV_TIMER0 arm command bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_cmd_t; + +typedef union { + struct { + unsigned int insel :8 ; // ADV_TIMER0 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 + unsigned int mode :3 ; // ADV_TIMER0 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed + unsigned int clksel :1 ; // ADV_TIMER0 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz + unsigned int updownsel :1 ; // ADV_TIMER0 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. + unsigned int padding0:3 ; + unsigned int presc :8 ; // ADV_TIMER0 prescaler value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_config_t; + +typedef union { + struct { + unsigned int th_lo :16; // ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. + unsigned int th_hi :16; // ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_threshold_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER0 channel 0 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_th_channel0_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER0 channel 1 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER0 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_th_channel1_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER0 channel 2 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER0 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_th_channel2_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER0 channel 3 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER0 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_th_channel3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) pwm_t0_counter_t; + +typedef union { + struct { + unsigned int start :1 ; // ADV_TIMER1 start command bitfield. + unsigned int stop :1 ; // ADV_TIMER1 stop command bitfield. + unsigned int update :1 ; // ADV_TIMER1 update command bitfield. + unsigned int reset :1 ; // ADV_TIMER1 reset command bitfield. + unsigned int arm :1 ; // ADV_TIMER1 arm command bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_cmd_t; + +typedef union { + struct { + unsigned int insel :8 ; // ADV_TIMER1 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 + unsigned int mode :3 ; // ADV_TIMER1 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed + unsigned int clksel :1 ; // ADV_TIMER1 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz + unsigned int updownsel :1 ; // ADV_TIMER1 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. + unsigned int padding0:3 ; + unsigned int presc :8 ; // ADV_TIMER1 prescaler value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_config_t; + +typedef union { + struct { + unsigned int th_lo :16; // ADV_TIMER1 threshold low part configuration bitfield. It defines start counter value. + unsigned int th_hi :16; // ADV_TIMER1 threshold high part configuration bitfield. It defines end counter value. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_threshold_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER1 channel 0 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER1 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_th_channel0_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER1 channel 1 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER1 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_th_channel1_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER1 channel 2 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER1 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_th_channel2_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER1 channel 3 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER1 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_th_channel3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) pwm_t1_counter_t; + +typedef union { + struct { + unsigned int start :1 ; // ADV_TIMER2 start command bitfield. + unsigned int stop :1 ; // ADV_TIMER2 stop command bitfield. + unsigned int update :1 ; // ADV_TIMER2 update command bitfield. + unsigned int reset :1 ; // ADV_TIMER2 reset command bitfield. + unsigned int arm :1 ; // ADV_TIMER2 arm command bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_cmd_t; + +typedef union { + struct { + unsigned int insel :8 ; // ADV_TIMER2 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 + unsigned int mode :3 ; // ADV_TIMER2 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed + unsigned int clksel :1 ; // ADV_TIMER2 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz + unsigned int updownsel :1 ; // ADV_TIMER2 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. + unsigned int padding0:3 ; + unsigned int presc :8 ; // ADV_TIMER2 prescaler value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_config_t; + +typedef union { + struct { + unsigned int th_lo :16; // ADV_TIMER2 threshold low part configuration bitfield. It defines start counter value. + unsigned int th_hi :16; // ADV_TIMER2 threshold high part configuration bitfield. It defines end counter value. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_threshold_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER2 channel 0 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER2 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_th_channel0_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER2 channel 1 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER2 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_th_channel1_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER2 channel 2 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER2 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_th_channel2_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER2 channel 3 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER2 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_th_channel3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) pwm_t2_counter_t; + +typedef union { + struct { + unsigned int start :1 ; // ADV_TIMER3 start command bitfield. + unsigned int stop :1 ; // ADV_TIMER3 stop command bitfield. + unsigned int update :1 ; // ADV_TIMER3 update command bitfield. + unsigned int reset :1 ; // ADV_TIMER3 reset command bitfield. + unsigned int arm :1 ; // ADV_TIMER3 arm command bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_cmd_t; + +typedef union { + struct { + unsigned int insel :8 ; // ADV_TIMER3 input source configuration bitfield: - 0-31: GPIO[0] to GPIO[31] - 32-35: Channel 0 to 3 of ADV_TIMER0 - 36-39: Channel 0 to 3 of ADV_TIMER1 - 40-43: Channel 0 to 3 of ADV_TIMER2 - 44-47: Channel 0 to 3 of ADV_TIMER3 + unsigned int mode :3 ; // ADV_TIMER3 trigger mode configuration bitfield: - 3'h0: trigger event at each clock cycle. - 3'h1: trigger event if input source is 0 - 3'h2: trigger event if input source is 1 - 3'h3: trigger event on input source rising edge - 3'h4: trigger event on input source falling edge - 3'h5: trigger event on input source falling or rising edge - 3'h6: trigger event on input source rising edge when armed - 3'h7: trigger event on input source falling edge when armed + unsigned int clksel :1 ; // ADV_TIMER3 clock source configuration bitfield: - 1'b0: FLL - 1'b1: reference clock at 32kHz + unsigned int updownsel :1 ; // ADV_TIMER3 center-aligned mode configuration bitfield: - 1'b0: The counter counts up and down alternatively. - 1'b1: The counter counts up and resets to 0 when reach threshold. + unsigned int padding0:3 ; + unsigned int presc :8 ; // ADV_TIMER3 prescaler value configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_config_t; + +typedef union { + struct { + unsigned int th_lo :16; // ADV_TIMER3 threshold low part configuration bitfield. It defines start counter value. + unsigned int th_hi :16; // ADV_TIMER3 threshold high part configuration bitfield. It defines end counter value. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_threshold_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER3 channel 0 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER3 channel 0 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_th_channel0_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER3 channel 1 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER3 channel 1 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_th_channel1_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER3 channel 2 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER3 channel 2 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_th_channel2_t; + +typedef union { + struct { + unsigned int th :16; // ADV_TIMER3 channel 3 threshold configuration bitfield. + unsigned int mode :3 ; // ADV_TIMER3 channel 3 threshold match action on channel output signal configuration bitfield: - 3'h0: set. - 3'h1: toggle then next threshold match action is clear. - 3'h2: set then next threshold match action is clear. - 3'h3: toggle. - 3'h4: clear. - 3'h5: toggle then next threshold match action is set. - 3'h6: clear then next threshold match action is set. + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_th_channel3_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) pwm_t3_counter_t; + +typedef union { + struct { + unsigned int sel0 :4 ; // ADV_TIMER output event 0 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. + unsigned int sel1 :4 ; // ADV_TIMER output event 1 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. + unsigned int sel2 :4 ; // ADV_TIMER output event 2 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. + unsigned int sel3 :4 ; // ADV_TIMER output event 3 source configuration bitfiled: - 4'h0: ADV_TIMER0 channel 0. - 4'h1: ADV_TIMER0 channel 1. - 4'h2: ADV_TIMER0 channel 2. - 4'h3: ADV_TIMER0 channel 3. - 4'h4: ADV_TIMER1 channel 0. - 4'h5: ADV_TIMER1 channel 1. - 4'h6: ADV_TIMER1 channel 2. - 4'h7: ADV_TIMER1 channel 3. - 4'h8: ADV_TIMER2 channel 0. - 4'h9: ADV_TIMER2 channel 1. - 4'hA: ADV_TIMER2 channel 2. - 4'hB: ADV_TIMER2 channel 3. - 4'hC: ADV_TIMER3 channel 0. - 4'hD: ADV_TIMER3 channel 1. - 4'hE: ADV_TIMER3 channel 2. - 4'hF: ADV_TIMER3 channel 3. + unsigned int ena :4 ; // ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation. + }; + unsigned int raw; +} __attribute__((packed)) pwm_event_cfg_t; + +typedef union { + struct { + unsigned int ena :16; // ADV_TIMER clock gating configuration bitfield. - ENA[i]=0: clock gate ADV_TIMERi. - ENA[i]=1: enable ADV_TIMERi. + }; + unsigned int raw; +} __attribute__((packed)) pwm_cg_t; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/rab/rab_v1.h b/sw/pulp-sdk/archi/include/archi/rab/rab_v1.h new file mode 100644 index 0000000..5fd5e6e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/rab/rab_v1.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_RAB_V1_H__ +#define __ARCHI_RAB_V1_H__ + +#include "archi/pulp.h" // for ARCHI_RAB_CFG_ADDR, RAB_L1_N_SLICES_PORT_0, + // RAB_L1_N_SLICES_PORT_1, RAB_L2_N_ENTRIES_PER_SET, RAB_L2_N_SETS + +// This struct represents the information in the L1 TLB hardware. +typedef struct { + volatile uint32_t word[8]; +} rab_cfg_t; + +// L1 addresses and pointers +#define RAB_CFG_L1_ADDR ((unsigned)(ARCHI_RAB_CFG_ADDR) + 4*8) +#define RAB_CFG_BPTR ((rab_cfg_t*)(RAB_CFG_L1_ADDR) + (RAB_L1_N_SLICES_PORT_0)) +#define RAB_CFG_EPTR ((RAB_CFG_BPTR) + (RAB_L1_N_SLICES_PORT_1)) + +#define RAB_CFG_FLAG_EN ((unsigned)(1 << 0)) +#define RAB_CFG_FLAG_RDEN ((unsigned)(1 << 1)) +#define RAB_CFG_FLAG_WREN ((unsigned)(1 << 2)) +#define RAB_CFG_FLAG_COHERENT ((unsigned)(1 << 3)) // cache-coherent with host + +// These types represents the information in the L2 TLB hardware. +typedef volatile uint32_t rab_cfg_l2_varam_t; +typedef volatile uint32_t rab_cfg_l2_param_t; + +// L2 addresses and pointers +#define RAB_CFG_L2_ADDR ((unsigned)(ARCHI_RAB_CFG_ADDR) + 2*0x4000) +#define RAB_CFG_L2_VARAM_PTR(i_set, i_entry) \ + ((rab_cfg_l2_varam_t*)(RAB_CFG_L2_ADDR + i_set*RAB_L2_N_ENTRIES_PER_SET*4 + i_entry*4)) +#define RAB_CFG_L2_PARAM_PTR(i_set, i_entry) \ + ((rab_cfg_l2_param_t*)(RAB_CFG_L2_ADDR + i_set*RAB_L2_N_ENTRIES_PER_SET*4 + i_entry*4 \ + + RAB_L2_N_SETS*RAB_L2_N_ENTRIES_PER_SET*4)) + +#define RAB_CFG_L2_SET_PFN_MASK ((unsigned)(RAB_L2_N_SETS-1)) + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/riscv/builtins_v2.h b/sw/pulp-sdk/archi/include/archi/riscv/builtins_v2.h new file mode 100644 index 0000000..529a937 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/riscv/builtins_v2.h @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_RISCV_BUILTINS_V2_H__ +#define __HAL_RISCV_BUILTINS_V2_H__ +#ifdef ARCHI_CORE_HAS_PULPV2 +/* ARITHMETIC SECTION */ +typedef signed short v2s __attribute__((vector_size (4))); +typedef unsigned short v2u __attribute__((vector_size (4))); + +typedef signed char v4s __attribute__((vector_size (4))); +typedef unsigned char v4u __attribute__((vector_size (4))); + +#ifdef __EMUL__ +typedef void * rt_pointerT; +#else +typedef unsigned int rt_pointerT; +#endif +/* Packing of scalars into vectors */ +#define __PACK2(x, y) __builtin_pulp_pack2((signed short) (x), (signed short) (y)) +#define __PACKU2(x, y) __builtin_pulp_pack2((unsigned short) (x), (unsigned short) (y)) + +#define __PACK4(x, y, z, t) __builtin_pulp_pack4((signed char) (x), (signed char) (y), (signed char) (z), (signed char) (t)) +#define __PACKU4(x, y, z, t) __builtin_pulp_pack4((unsigned char) (x), (unsigned char) (y), (unsigned char) (z), (unsigned char) (t)) + +/* Max */ +#define __MAX(a, b) __builtin_pulp_maxsi((a), (b)) + +#define __MAX2(x, y) __builtin_pulp_max2((x), (y)) +#define __MAX4(x, y) __builtin_pulp_max4((x), (y)) + +#define __MAXU2(x, y) __builtin_pulp_maxu2((x), (y)) +#define __MAXU4(x, y) __builtin_pulp_maxu4((x), (y)) + +/* Min */ +#define __MIN2(x, y) __builtin_pulp_min2((x), (y)) +#define __MIN4(x, y) __builtin_pulp_min4((x), (y)) + +#define __MINU2(x, y) __builtin_pulp_minu2((x), (y)) +#define __MINU4(x, y) __builtin_pulp_minu4((x), (y)) + +/* Clip */ +#define __CLIP(x, precision) __builtin_pulp_clip((x), -(1<<(precision)), (1<(y)?(x):(y)) +#define __MAX2(x, y) ((v2s) {((signed short)(x)[0]>(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]>(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __MAX4(x, y) ((v4s) {((signed char)(x)[0]>(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]>(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]>(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]>(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __MAXU2(x, y) ((v2u) {((unsigned short)(x)[0]>(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]>(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __MAXU4(x, y) ((v4u) {((unsigned char)(x)[0]>(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]>(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]>(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]>(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Min */ +#define __MIN2(x, y) ((v2s) {((signed short)(x)[0]<(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]<(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __MIN4(x, y) ((v4s) {((signed char)(x)[0]<(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]<(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]<(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]<(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __MINU2(x, y) ((v2u) {((unsigned short)(x)[0]<(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]<(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __MINU4(x, y) ((v4u) {((unsigned char)(x)[0]<(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]<(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]<(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]<(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Clip */ +#define __CLIP(x, precision) ((x)<(-(1<<(precision)))?(-(1<<(precision))):(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x))) +#define __CLIP_R(x, bound) (((x)<=-((bound)+1))?(-((bound)+1)):(((x)>=(bound))?(bound):(x))) + +#define __CLIPU(x, precision) ((x)<0)?0:(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x)) +#define __CLIPU_R(x, bound) (((x)<=0)?(0):(((x)>=(bound))?(bound):(x))) + +/* Abs */ +#define __ABS2(x) ((v2u) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1]}) +#define __ABS4(x) ((v4u) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1], \ + ((x)[2]<0)?-(x)[2]:(x)[2], ((x)[3]<0)?-(x)[3]:(x)[3]}) + +/* Unary minus */ +#define __NEG2(x) ((v2s) {-(x)[0], -(x)[1]} +#define __NEG4(x) ((v4s) {-(x)[0], -(x)[1], -(x)[2], -(x)[3]} + +/* Addition */ +#define __ADD2(x, y) ((v2s) {(x)[0]+(y)[0], (x)[1]+(y)[1]} +#define __ADD4(x, y) ((v4s) {(x)[0]+(y)[0], (x)[1]+(y)[1], (x)[2]+(y)[2], (x)[3]+(y)[3]} + +/* Substraction */ +#define __SUB2(x, y) ((v2s) {(x)[0]-(y)[0], (x)[1]-(y)[1]} +#define __SUB4(x, y) ((v4s) {(x)[0]-(y)[0], (x)[1]-(y)[1], (x)[2]-(y)[2], (x)[3]-(y)[3]} + +/* Average */ +#define __AVG2(x, y) ((v2s) {((x)[0]+(y)[0])>>1, ((x)[1]+(y)[1])>>1} +#define __AVG4(x, y) ((v4s) {((x)[0]+(y)[0])>>1, ((x)[1]+(y)[1])>>1, ((x)[2]+(y)[2])>>1, ((x)[3]+(y)[3])>>1} + +/* Average unsigned */ +#define __AVGU2(x, y) ((v2u) {((unsigned short)(x)[0]+(unsigned short)(y)[0])>>1, ((unsigned short)(x)[1]+(unsigned short)(y)[1])>>1} +#define __AVGU4(x, y) ((v4u) {((unsigned char)(x)[0]+(unsigned char)(y)[0])>>1, ((unsigned char)(x)[1]+(unsigned char)(y)[1])>>1, \ + ((unsigned char)(x)[2]+(unsigned char)(y)[2])>>1, ((unsigned char)(x)[3]+(unsigned char)(y)[3])>>1} + +/* Bitwise and */ +#define __AND2(x, y) ((v2s) {(x)[0]&(y)[0], (x)[1]&(y)[1]} +#define __AND4(x, y) ((v4s) {(x)[0]&(y)[0], (x)[1]&(y)[1], (x)[2]&(y)[2], (x)[3]&(y)[3]} + +/* Bitwise or */ +#define __OR2(x, y) ((v2s) {(x)[0]|(y)[0], (x)[1]|(y)[1]} +#define __OR4(x, y) ((v4s) {(x)[0]|(y)[0], (x)[1]|(y)[1], (x)[2]|(y)[2], (x)[3]|(y)[3]} + +/* Bitwise exor */ +#define __EXOR2(x, y) ((v2s) {(x)[0]^(y)[0], (x)[1]^(y)[1]} +#define __EXOR4(x, y) ((v4s) {(x)[0]^(y)[0], (x)[1]^(y)[1], (x)[2]^(y)[2], (x)[3]^(y)[3]} + +/* Logical shift right */ +#define __SRL2(x, y) ((v2u) {((unsigned short)(x)[0]>>(unsigned short)(y)[0]), ((unsigned short)(x)[1]>>(unsigned short)(y)[1])} +#define __SRL4(x, y) ((v4u) {((unsigned char)(x)[0]>>(unsigned char)(y)[0]), ((unsigned char)(x)[1]>>(unsigned char)(y)[1]), \ + ((unsigned char)(x)[2]>>(unsigned char)(y)[2]), ((unsigned char)(x)[3]>>(unsigned char)(y)[3])} + +/* Arithmetic shift right */ +#define __SRA2(x, y) ((v2s) {((signed short)(x)[0]>>(signed short)(y)[0]), ((signed short)(x)[1]>>(signed short)(y)[1])} +#define __SRA4(x, y) ((v4s) {((signed char)(x)[0]>>(signed char)(y)[0]), ((signed char)(x)[1]>>(signed char)(y)[1]), \ + ((signed char)(x)[2]>>(signed char)(y)[2]), ((signed char)(x)[3]>>(signed char)(y)[3])} + +/* Logical shift left */ +#define __SLL2(x, y) ((v2s) {(x)[0]<<(y)[0], (x)[1]<<(y)[1]} +#define __SLL4(x, y) ((v4s) {(x)[0]<<(y)[0], (x)[1]<<(y)[1], (x)[2]<<(y)[2], (x)[3]<<(y)[3]} + +/* Mac */ +#define __MAC(Acc, x, y) ((Acc) + ((x) * (y))) +#define __MSU(Acc, x, y) ((Acc) - ((x) * (y))) + +#define __MACS(Acc, x, y) ((Acc) + ((short int) (x) * (short int) (y))) +#define __MACHHS(Acc, x, y) ((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) +#define __MACU(Acc, x, y) ((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) +#define __MACHHU(Acc, x, y) ((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + +#define __MACSN(Acc, x, y, n) (((Acc) + ((short int) (x) * (short int) (y)))>>(n)) +#define __MACUN(Acc, x, y, n) (((Acc) + ((unsigned short int) (x) * (unsigned short int) (y)))>>(n)) +#define __MACSRN(Acc, x, y, n) ((((Acc) + ((short int) (x) * (short int) (y))) + (1<<((n)-1))) >> (n)) +#define __MACURN(Acc, x, y, n) ((((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) + (1<<((n)-1))) >> (n)) + +#define __MACHHSN(Acc, x, y, n) (((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) >> (n)) +#define __MACHHUN(Acc, x, y, n) (((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) >> (n)) +#define __MACHHSRN(Acc, x, y, n) ((((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) + (1<<((n)-1))) >> (n)) +#define __MACHHURN(Acc, x, y, n) ((((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + (n))) + +/* Multiplications */ +#define __MULS(x, y) (((short int) (x) * (short int) (y))) +#define __MULU(x, y) (((unsigned short int) (x) * (unsigned short int) (y))) +#define __MULHHS(x, y) (((short int) ((x)>>16) * (short int) ((y)>>16))) +#define __MULHHU(x, y) (((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + +#define __MULSN(x, y, n) (((short int) (x) * (short int) (y))>>(n)) +#define __MULSRN(x, y, n) ((((short int) (x) * (short int) (y)) + (1<<((n)-1)))>>(n)) +#define __MULUN(x, y, n) (((unsigned short int) (x) * (unsigned short int) (y))>>(n)) +#define __MULURN(x, y, n) ((((unsigned short int) (x) * (unsigned short int) (y)) + (1<<((n)-1)))>>(n)) + +#define __MULHHSN(x, y, n) ((((short int) ((x)>>16) * (short int) ((y)>>16)))>>(n)) +#define __MULHHSRN(x, y, n) (((((short int) ((x)>>16) * (short int) ((y)>>16)))+(1<<((n)-1)))>>(n)) +#define __MULHHUN(x, y, n) ((((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16)))>>(n)) +#define __MULHHURN(x, y, n) (((((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16)))+(1<<((n)-1)))>>(n)) + +/* Vectorial product and sum of products */ +#define __DOTP2(x, y) ( (short)(x)[0]*(short)(y)[0] + (short)(x)[1]*(short)(y)[1]) +#define __DOTPU2(x, y) ( (unsigned short)(x)[0]*(unsigned short)(y)[0] + (unsigned short)(x)[1]*(unsigned short)(y)[1]) +#define __DOTPUS2(x, y) ( (unsigned short)(x)[0]*(short)(y)[0] + (unsigned short)(x)[1]*(short)(y)[1]) + +#define __DOTPSC2(x, y) ( (short)(x)[0]*(short)(y) + (short)(x)[1]*(short)(y)) +#define __DOTPUSC2(x, y) ( (unsigned short)(x)[0]*(unsigned short)(y) + (unsigned short)(x)[1]*(unsigned short)(y)) +#define __DOTPUSSC2(x, y) ( (unsigned short)(x)[0]*(short)(y) + (unsigned short)(x)[1]*(short)(y)) + +#define __SUMDOTP2(x, y, z) ((z)+(short)(x)[0]*(short)(y)[0] + (short)(x)[1]*(short)(y)[1]) +#define __SUMDOTPU2(x, y, z) ((z)+(unsigned short)(x)[0]*(unsigned short)(y)[0] + (unsigned short)(x)[1]*(unsigned short)(y)[1]) +#define __SUMDOTPUS2(x, y, z) ((z)+(unsigned short)(x)[0]*(short)(y)[0] + (unsigned short)(x)[1]*(short)(y)[1]) + +#define __SUMDOTPSC2(x, y, z) ((z)+(short)(x)[0]*(short)(y) + (short)(x)[1]*(short)(y)) +#define __SUMDOTPUSC2(x, y, z) ((z)+(unsigned short)(x)[0]*(unsigned short)(y) + (unsigned short)(x)[1]*(unsigned short)(y)) +#define __SUMDOTPUSSC2(x, y, z) ((z)+(unsigned short)(x)[0]*(short)(y) + (unsigned short)(x)[1]*(short)(y)) + +#define __DOTP4(x, y) ( (char)(x)[0]*(char)(y)[0] + (char)(x)[1]*(char)(y)[1] + (char)(x)[2]*(char)(y)[2] + (char)(x)[3]*(char)(y)[3]) +#define __DOTPU4(x, y) ( (unsigned char)(x)[0]*(unsigned char)(y)[0] + (unsigned char)(x)[1]*(unsigned char)(y)[1] + \ + (unsigned char)(x)[2]*(unsigned char)(y)[2] + (unsigned char)(x)[3]*(unsigned char)(y)[3]) +#define __DOTPUS4(x, y) ( (unsigned char)(x)[0]*(char)(y)[0] + (unsigned char)(x)[1]*(char)(y)[1] + \ + (unsigned char)(x)[2]*(char)(y)[2] + (unsigned char)(x)[3]*(char)(y)[3]) + +#define __DOTPSC4(x, y) ( (char)(x)[0]*(char)(y) + (char)(x)[1]*(char)(y) + (char)(x)[2]*(char)(y) + (char)(x)[3]*(char)(y)) +#define __DOTPUSC4(x, y) ( (unsigned char)(x)[0]*(unsigned char)(y) + (unsigned char)(x)[1]*(unsigned char)(y) + \ + (unsigned char)(x)[2]*(unsigned char)(y) + (unsigned char)(x)[3]*(unsigned char)(y)) +#define __DOTPUSSC4(x, y) ( (unsigned char)(x)[0]*(char)(y) + (unsigned char)(x)[1]*(char)(y) + \ + (unsigned char)(x)[2]*(char)(y) + (unsigned char)(x)[3]*(char)(y)) + +#define __SUMDOTP4(x, y, z) ((z)+(char)(x)[0]*(char)(y)[0] + (char)(x)[1]*(char)(y)[1] + (char)(x)[2]*(char)(y)[2] + (char)(x)[3]*(char)(y)[3]) +#define __SUMDOTPU4(x, y, z) ((z)+(unsigned char)(x)[0]*(unsigned char)(y)[0] + (unsigned char)(x)[1]*(unsigned char)(y)[1] + \ + (unsigned char)(x)[2]*(unsigned char)(y)[2] + (unsigned char)(x)[3]*(unsigned char)(y)[3]) +#define __SUMDOTPUS4(x, y, z) ((z)+(unsigned char)(x)[0]*(char)(y)[0] + (unsigned char)(x)[1]*(char)(y)[1] + \ + (unsigned char)(x)[2]*(char)(y)[2] + (unsigned char)(x)[3]*(char)(y)[3]) + +#define __SUMDOTPSC4(x, y, z) ((z)+(char)(x)[0]*(char)(y) + (char)(x)[1]*(char)(y) + (char)(x)[2]*(char)(y) + (char)(x)[3]*(char)(y)) +#define __SUMDOTPUSC4(x, y, z) ((z)+(unsigned char)(x)[0]*(unsigned char)(y) + (unsigned char)(x)[1]*(unsigned char)(y) + \ + (unsigned char)(x)[2]*(unsigned char)(y) + (unsigned char)(x)[3]*(unsigned char)(y)) +#define __SUMDOTPUSSC4(x, y, z) ((z)+(unsigned char)(x)[0]*(char)(y) + (unsigned char)(x)[1]*(char)(y) + \ + (unsigned char)(x)[2]*(char)(y) + (unsigned char)(x)[3]*(char)(y)) + +#ifdef ARCHI_CORE_HAS_CPLX + +/* Complex Multiplication, Q15x15 into Q15, with optional post scaling by 1 or 2 */ +#define __CPLXMULS(x, y) ((v2s) {(signed short) ((((long long) (x)[0]*(long long) (y)[0]) - ((long long) (x)[1]*(long long) (y)[1]))>>15), \ + (signed short) ((((long long) (x)[0]*(long long) (y)[1]) + ((long long) (x)[1]*(long long) (y)[0]))>>15)}) +#define __CPLXMULSDIV2(x, y) (__CPLXMULS(x, y)>>(v2s){1,1}) +#define __CPLXMULSDIV4(x, y) (__CPLXMULS(x, y)>>(v2s){2,2}) + +/* Complex conjugate */ +#define __CPLXCONJ(x) ((v2s) {(x)[0], -(x)[1]}) + +/* Complex substration, result rotated by -pi/2 */ +#define __SUB2ROTMJ(x, y) ((v2s) {(x)[1]-(y)[1], (y)[0]-(x)[0]}) + +/* Complex addition with post scaling by 1 or 2 */ +#define __ADD2DIV2(x, y) (((x)+(y))>>(v2s) {1, 1}) +#define __ADD2DIV4(x, y) (((x)+(y))>>(v2s) {2, 2}) + +#define __ADD4DIV2(x, y) (((x)+(y))>>(v4s) {1, 1, 1, 1}) +#define __ADD4DIV4(x, y) (((x)+(y))>>(v4s) {2, 2, 2, 2}) + +/* Complex substraction with post scaling by 1 or 2 */ +#define __SUB2DIV2(x, y) (((x)-(y))>>(v2s) {1, 1}) +#define __SUB2DIV4(x, y) (((x)-(y))>>(v2s) {2, 2}) + +#define __SUB4DIV2(x, y) (((x)-(y))>>(v4s) {1, 1, 1, 1}) +#define __SUB4DIV4(x, y) (((x)-(y))>>(v4s) {2, 2, 2, 2}) + +/* Complex subtraction with post scaling by 1 or 2 */ +#define __SUB2DIV2(x, y) (((x)-(y))>>(v2s) {1, 1}) +#define __SUB2DIV4(x, y) (((x)-(y))>>(v2s) {2, 2}) + +/* Viterbi Max and Viterbi Select, pair of Q15 */ +#define __VITMAX(x, y) (_VitT1_Flag=((x)[1]<=(y)[1])?1:0, _VitT0_Flag=((x)[0]<=(y)[0])?1:0,\ + (v2s) {((x)[0]>(y)[0])?(x)[0]:(y)[0], ((x)[1]>(y)[1])?(x)[1]:(y)[1]}) +#define __VITSEL(x, y) (v2s) {(_VitT0_Flag?(y)[0]:(x)[0])<<1|_VitT0_Flag, (_VitT1_Flag?(y)[1]:(x)[1])<<1|_VitT1_Flag} + +#endif + +/* Position of the most significant bit of x */ +#define __FL1(x) (31 - __builtin_clz((x))) + +/* Number of sign bits */ +#define __CLB(x) (__builtin_clrsb((x))) + +/* Bit set */ +#define __BITSET(x, size, off) ((x) | (((1<<(size))-1)<<(off))) +#define __BITSET_R(x, size, off) ((x) | (((1<<(size))-1)<<(off))) +#define __BITSET_R_SAFE(x, size, off) ((x) | (((1<<((size)&0x1F))-1)<<((off)&0x1F))) + +/* Bit clr */ +#define __BITCLR(x, size, off) ((x) & ~(((1<<(size))-1)<<(off))) +#define __BITCLR_R(x, size, off) ((x) & ~(((1<<(size))-1)<<(off))) +#define __BITCLR_R_SAFE(x, size, off) ((x) & ~(((1<<((size)&0x1F))-1)<<((off)&0x1F))) + +/* Bit Extraction */ +#define __BITEXTRACT(x, size, off) (((((x)>>(off))&((unsigned int)(1<<(size))-1))<<(32-(size)))>>(32-(size))) +#define __BITEXTRACTU(x, size, off) (((x)>>(off))&((unsigned int)(1<<(size))-1)) + +#define __BITEXTRACT_R(x, size, off) (((((x)>>(off))&((unsigned int)(1<<(size))-1))<<(32-(size)))>>(32-(size))) +#define __BITEXTRACTU_R(x, size, off) (((x)>>(off))&((unsigned int)(1<<(size))-1)) + +#define __BITEXTRACT_R_SAFE(x, size, off) (((((x)>>((off)&0x1F))&((unsigned int)(1<<((((size)>32)?32:(size))))-1))<<(32-((((size)>32)?32:(size)))))>>(32-((((size)>32)?32:(size))))) +#define __BITEXTRACTU_R_SAFE(x, size, off) (((x)>>((off)&0x1F))&((unsigned int)(1<<((((size)>32)?32:(size))))-1)) + +/* Bit insertion */ +#define __BITINSERT(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) +#define __BITINSERT_R(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) +#define __BITINSERT_R_SAFE(dst, src, size, off) (((dst) & ~(((1<<(((size)>32)?32:(size)))-1)<<((off)&0x1F))) | (((src) & ((1<<(((size)>32)?32:(size)))-1))<<((off)&0x1F))) + +/* 1 bit rotation to the right, 32 bits input */ +#define __ROTR(x) ((((x)>>1)&0x7FFFFFFF) | ((x)<<31)) + +/* Add with normalization */ +#define __ADDNORMU(x, y, scale) ((unsigned int)((x) + (y))>>(scale)) +#define __ADDNORMU_REG(x, y, scale) ((unsigned int)((x) + (y))>>(scale)) +#define __ADDNORM(x, y, scale) ((int)((x) + (y))>>(scale)) +#define __ADDNORM_REG(x, y, scale) ((int)((x) + (y))>>(scale)) + +/* Add with normalization and rounding */ +#define __ADDROUNDNORMU(x, y, scale) ((unsigned int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __ADDROUNDNORMU_REG(x, y, scale) ((unsigned int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __ADDROUNDNORM(x, y, scale) ((int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __ADDROUNDNORM_REG(x, y, scale) ((int)((x) + (y) + (1<<((scale)-1)))>>(scale)) + +/* Sub with normalization */ +#define __SUBNORMU(x, y, scale) ((unsigned int)((x) - (y))>>(scale)) +#define __SUBNORMU_REG(x, y, scale) ((unsigned int)((x) - (y))>>(scale)) +#define __SUBNORM(x, y, scale) ((int)((x) - (y))>>(scale)) +#define __SUBNORM_REG(x, y, scale) ((int)((x) - (y))>>(scale)) + +/* Sub with normalization and rounding */ +#define __SUBROUNDNORMU(x, y, scale) ((unsigned int)((x) - (y) + (1<<((scale)-1)))>>(scale)) +#define __SUBROUNDNORMU_REG(x, y, scale) ((unsigned int)((x) - (y) + (1<<((scale)-1)))>>(scale)) +#define __SUBROUNDNORM(x, y, scale) ((int)((x) - (y) + (1<<((scale)-1)))>>(scale)) +#define __SUBROUNDNORM_REG(x, y, scale) ((int)((x) - (y) + (1<<((scale)-1)))>>(scale)) + +/* Normalization and rounding */ +#define __ROUNDNORMU(x, scale) ((unsigned int)((x) + (1<<((scale)-1)))>>(scale)) +#define __ROUNDNORMU_REG(x, scale) ((unsigned int)((x) + (1<<((scale)-1)))>>(scale)) +#define __ROUNDNORM(x, scale) ((int)((x) + (1<<((scale)-1)))>>(scale)) +#define __ROUNDNORM_REG(x, scale) ((int)((x) + (1<<((scale)-1)))>>(scale)) +#define __COREID() 0 +#define __CLUSTERID() 0 +#define __NCORE() 1 + +#define __SPRWRITE(x, y) +#define __SPRREAD(x) ((int) 0) +#define __SPRREAD_VOL(x) ((int) 0) + +#define __READ_BASE_OFF(base, off) ((int) 0) +#define __WRITE_BASE_OFF(base, off, val) + +#define __READ_BASE_OFF_VOL(base, off) ((int) 0) +#define __READ_BASE_OFF_HALF_VOL(base, off) ((int) 0) +#define __READ_BASE_OFF_BYTE_VOL(base, off) ((int) 0) + +#define __WRITE_BASE_OFF_VOL(x, base, off) +#define __WRITE_BASE_OFF_HALF_VOL(x, base, off) +#define __WRITE_BASE_OFF_BYTE_VOL(x, base, off) +/* Utilities, Target independant */ +#define FIX2FP(Val, Precision) ((float) (Val) / (float) (1<<(Precision))) +#define FP2FIXR(Val, Precision) ((int)((Val)*((1 << (Precision))-1) + 0.5)) +#define FP2FIX(Val, Precision) ((int)((Val)*((1 << (Precision))-1))) +#endif +#endif diff --git a/sw/pulp-sdk/archi/include/archi/riscv/pcer_v1.h b/sw/pulp-sdk/archi/include/archi/riscv/pcer_v1.h new file mode 100644 index 0000000..c9f92bf --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/riscv/pcer_v1.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARCHI_RISCV_PCER_V1_H +#define _ARCHI_RISCV_PCER_V1_H + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define CSR_PCER_CYCLES 0 /* Count the number of cycles the core was running */ +#define CSR_PCER_INSTR 1 /* Count the number of instructions executed */ +#define CSR_PCER_LD_STALL 2 /* Number of load use hazards */ +#define CSR_PCER_JMP_STALL 3 /* Number of jump register hazards */ +#define CSR_PCER_IMISS 4 /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */ +#define CSR_PCER_LD 5 /* Number of memory loads executed. Misaligned accesses are counted twice */ +#define CSR_PCER_ST 6 /* Number of memory stores executed. Misaligned accesses are counted twice */ +#define CSR_PCER_JUMP 7 /* Number of jump instructions seen, i.e. j, jr, jal, jalr */ +#define CSR_PCER_BRANCH 8 /* Number of branch instructions seen, i.e. bf, bnf */ +#define CSR_PCER_TAKEN_BRANCH 9 /* Number of taken branch instructions seen, i.e. bf, bnf */ +#define CSR_PCER_RVC 10 /* Number of compressed instructions */ +#define CSR_PCER_LD_EXT 11 /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ +#define CSR_PCER_ST_EXT 12 /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ +#define CSR_PCER_LD_EXT_CYC 13 /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */ +#define CSR_PCER_ST_EXT_CYC 14 /* Cycles used for memory stores to EXT. Every non-TCDM access is considered external */ +#define CSR_PCER_TCDM_CONT 15 /* Cycles wasted due to TCDM/log-interconnect contention */ +#define CSR_PCER_CSR_HAZARD 16 +#define CSR_PCER_APU_TY_CONF 17 +#define CSR_PCER_APU_CONT 18 +#define CSR_PCER_APU_DEP 19 +#define CSR_PCER_APU_WB 20 + + +#define CSR_PCER_NB_EVENTS 16 +#define CSR_PCER_NB_INTERNAL_EVENTS 11 +#define CSR_NB_PCCR 31 + +// Gives from the event ID, the HW mask that can be stored (with an OR with other events mask) to the PCER +#define CSR_PCER_EVENT_MASK(eventId) (1<<(eventId)) +#define CSR_PCER_ALL_EVENTS_MASK 0xffffffff + +#define CSR_PCMR_ACTIVE 0x1 /* Activate counting */ +#define CSR_PCMR_SATURATE 0x2 /* Activate saturation */ + +#define CSR_PCER_NAME(id) (id == 0 ? "Cycles" : id == 1 ? "Instructions" : id == 2 ? "LD_Stall" : id == 3 ? "Jmp_Stall" : id == 4 ? "IMISS" : id == 5 ? "LD" : id == 6 ? "ST" : id == 7 ? "JUMP" : id == 8 ? "BRANCH" : id == 9 ? "TAKEN_BRANCH" : id == 10 ? "RVC" : id == 11 ? "LD_EXT" : id == 12 ? "ST_EXT" : id == 13 ? "LD_EXT_CYC" : id == 14 ? "ST_EXT_CYC" : id == 15 ? "TCDM_CONT" : "NA") + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/riscv/pcer_v2.h b/sw/pulp-sdk/archi/include/archi/riscv/pcer_v2.h new file mode 100644 index 0000000..c329258 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/riscv/pcer_v2.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARCHI_RISCV_PCER_V1_H +#define _ARCHI_RISCV_PCER_V1_H + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define CSR_PCER_CYCLES 0 /* Count the number of cycles the core was running */ +#define CSR_PCER_INSTR 1 /* Count the number of instructions executed */ +#define CSR_PCER_LD_STALL 2 /* Number of load use hazards */ +#define CSR_PCER_JMP_STALL 3 /* Number of jump register hazards */ +#define CSR_PCER_IMISS 4 /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */ +#define CSR_PCER_LD 5 /* Number of memory loads executed. Misaligned accesses are counted twice */ +#define CSR_PCER_ST 6 /* Number of memory stores executed. Misaligned accesses are counted twice */ +#define CSR_PCER_JUMP 7 /* Number of jump instructions seen, i.e. j, jr, jal, jalr */ +#define CSR_PCER_BRANCH 8 /* Number of branch instructions seen, i.e. bf, bnf */ +#define CSR_PCER_TAKEN_BRANCH 9 /* Number of taken branch instructions seen, i.e. bf, bnf */ +#define CSR_PCER_RVC 10 /* Number of compressed instructions */ +#define CSR_PCER_ELW 11 /* Cycles wasted due to ELW instruction */ +#define CSR_PCER_LD_EXT 12 /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ +#define CSR_PCER_ST_EXT 13 /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ +#define CSR_PCER_LD_EXT_CYC 14 /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */ +#define CSR_PCER_ST_EXT_CYC 15 /* Cycles used for memory stores to EXT. Every non-TCDM access is considered external */ +#define CSR_PCER_TCDM_CONT 16 /* Cycles wasted due to TCDM/log-interconnect contention */ + + +#define CSR_PCER_NB_EVENTS 17 +#define CSR_PCER_NB_INTERNAL_EVENTS 12 +#define CSR_NB_PCCR 31 + +// Gives from the event ID, the HW mask that can be stored (with an OR with other events mask) to the PCER +#define CSR_PCER_EVENT_MASK(eventId) (1<<(eventId)) +#define CSR_PCER_ALL_EVENTS_MASK 0xffffffff + +#define CSR_PCMR_ACTIVE 0x1 /* Activate counting */ +#define CSR_PCMR_SATURATE 0x2 /* Activate saturation */ + +#define CSR_PCER_NAME(id) (id == 0 ? "Cycles" : id == 1 ? "Instructions" : id == 2 ? "LD_Stall" : id == 3 ? "Jmp_Stall" : id == 4 ? "IMISS" : id == 5 ? "LD" : id == 6 ? "ST" : id == 7 ? "JUMP" : id == 8 ? "BRANCH" : id == 9 ? "TAKEN_BRANCH" : id == 10 ? "RVC" : id == 11 ? "ELW" : id == 12 ? "LD_EXT" : id == 13 ? "ST_EXT" : id == 14 ? "LD_EXT_CYC" : id == 15 ? "ST_EXT_CYC" : id == 16 ? "TCDM_CONT" : "NA") + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/riscv/priv_1.9.h b/sw/pulp-sdk/archi/include/archi/riscv/priv_1.9.h new file mode 100644 index 0000000..ac03cbb --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/riscv/priv_1.9.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARCHI_RISCV_PRIV_1_9_H +#define _ARCHI_RISCV_PRIV_1_9_H + +#define RV_CSR_MSTATUS 0x300 +#define RV_CSR_MEPC 0x341 +#define RV_CSR_MCAUSE 0x342 +#define RV_CSR_MTVAL 0x343 +#define RV_CSR_MESTATUS 0x7C0 +#define RV_CSR_MISA 0xF10 +#define RV_CSR_MIMPID 0xF13 +#define RV_CSR_MHARTID 0xF14 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/riscv/priv_1_10.h b/sw/pulp-sdk/archi/include/archi/riscv/priv_1_10.h new file mode 100644 index 0000000..df6a5ff --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/riscv/priv_1_10.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARCHI_RISCV_PRIV_1_9_H +#define _ARCHI_RISCV_PRIV_1_9_H + +#define RV_CSR_MSTATUS 0x300 +#define RV_CSR_MEPC 0x341 +#define RV_CSR_MCAUSE 0x342 +#define RV_CSR_MTVAL 0x343 +#define RV_CSR_MESTATUS 0x7C0 +#ifdef RISCV_1_7 +#define RV_CSR_MCPUID 0xF00 +#define RV_CSR_MIMPID 0xF01 +#define RV_CSR_MHARTID 0xF10 +#else +#define RV_CSR_MISA 0xF10 +#define RV_CSR_MIMPID 0xF13 +#define RV_CSR_MHARTID 0xF14 +#endif + +#define CSR_PCCR(N) (0x780 + (N)) +#define CSR_PCER 0xCC0 +#define CSR_PCMR 0xCC1 + +#define CSR_STACK_CONF 0x7D0 +#define CSR_STACK_START 0x7D1 +#define CSR_STACK_END 0x7D2 + +#define CSR_MESTATUS_INTEN_BIT 0 +#define CSR_MESTATUS_PRV_BIT 1 + +#define CSR_MESTATUS_PRV_MACH 3 + +#define CSR_HWLOOP0_START 0x7C0 +#define CSR_HWLOOP0_END 0x7C1 +#define CSR_HWLOOP0_COUNTER 0x7C2 +#define CSR_HWLOOP1_START 0x7C4 +#define CSR_HWLOOP1_END 0x7C5 +#define CSR_HWLOOP1_COUNTER 0x7C6 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/riscv/priv_1_7.h b/sw/pulp-sdk/archi/include/archi/riscv/priv_1_7.h new file mode 100644 index 0000000..f3c9180 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/riscv/priv_1_7.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARCHI_RISCV_PRIV_1_7_H +#define _ARCHI_RISCV_PRIV_1_7_H + +#define CSR_MSTATUS 0x300 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MESTATUS 0x7C0 +#define CSR_MCPUID 0xF00 +#define CSR_MIMPID 0xF01 +#define CSR_MHARTID 0xF10 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/riscv/priv_1_9.h b/sw/pulp-sdk/archi/include/archi/riscv/priv_1_9.h new file mode 100644 index 0000000..d06f85f --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/riscv/priv_1_9.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARCHI_RISCV_PRIV_1_9_H +#define _ARCHI_RISCV_PRIV_1_9_H + +#define RV_CSR_MSTATUS 0x300 +#define RV_CSR_MEPC 0x341 +#define RV_CSR_MCAUSE 0x342 +#define RV_CSR_MTVAL 0x343 +#define RV_CSR_MESTATUS 0x7C0 +#ifdef RISCV_1_7 +#define RV_CSR_MCPUID 0xF00 +#define RV_CSR_MIMPID 0xF01 +#define RV_CSR_MHARTID 0xF10 +#else +#define RV_CSR_MISA 0xF10 +#define RV_CSR_MIMPID 0xF13 +#define RV_CSR_MHARTID 0xF14 +#endif + +#define CSR_PCCR(N) (0x780 + (N)) +#define CSR_PCER 0x7A0 +#define CSR_PCMR 0x7A1 + +#define CSR_STACK_CONF 0x7D0 +#define CSR_STACK_START 0x7D1 +#define CSR_STACK_END 0x7D2 + +#define CSR_MESTATUS_INTEN_BIT 0 +#define CSR_MESTATUS_PRV_BIT 1 + +#define CSR_MESTATUS_PRV_MACH 3 + +#define CSR_HWLOOP0_START 0x7B0 +#define CSR_HWLOOP0_END 0x7B1 +#define CSR_HWLOOP0_COUNTER 0x7B2 +#define CSR_HWLOOP1_START 0x7B4 +#define CSR_HWLOOP1_END 0x7B5 +#define CSR_HWLOOP1_COUNTER 0x7B6 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/rtc/rtc_v2.h b/sw/pulp-sdk/archi/include/archi/rtc/rtc_v2.h new file mode 100644 index 0000000..1c341c8 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/rtc/rtc_v2.h @@ -0,0 +1,473 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_RTC_RTC_V2_H__ +#define __INCLUDE_ARCHI_RTC_RTC_V2_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Clock register +#define RTC_CLOCK_OFFSET 0x0 + +// Alarm register +#define RTC_ALARM_OFFSET 0x4 + +// Timer register +#define RTC_TIMER_OFFSET 0x8 + +// Date register +#define RTC_DATE_OFFSET 0xc + + + +// +// REGISTERS FIELDS +// + +// First digit of clock seconds. (access: R/W) +#define RTC_CLOCK_SECONDS_0_BIT 0 +#define RTC_CLOCK_SECONDS_0_WIDTH 4 +#define RTC_CLOCK_SECONDS_0_MASK 0xf + +// Second digit of clock seconds. (access: R/W) +#define RTC_CLOCK_SECONDS_1_BIT 4 +#define RTC_CLOCK_SECONDS_1_WIDTH 4 +#define RTC_CLOCK_SECONDS_1_MASK 0xf0 + +// First digit of clock minutes. (access: R/W) +#define RTC_CLOCK_MINUTES_0_BIT 8 +#define RTC_CLOCK_MINUTES_0_WIDTH 4 +#define RTC_CLOCK_MINUTES_0_MASK 0xf00 + +// Second digit of clock minutes. (access: R/W) +#define RTC_CLOCK_MINUTES_1_BIT 12 +#define RTC_CLOCK_MINUTES_1_WIDTH 4 +#define RTC_CLOCK_MINUTES_1_MASK 0xf000 + +// First digit of clock hours. (access: R/W) +#define RTC_CLOCK_HOURS_0_BIT 16 +#define RTC_CLOCK_HOURS_0_WIDTH 4 +#define RTC_CLOCK_HOURS_0_MASK 0xf0000 + +// Second digit of clock hours. (access: R/W) +#define RTC_CLOCK_HOURS_1_BIT 20 +#define RTC_CLOCK_HOURS_1_WIDTH 2 +#define RTC_CLOCK_HOURS_1_MASK 0x300000 + +// MSB part of second counter initial value. The second counter is incremented every 1/32768 seconds and is incrementing by 1 the number of seconds when it reaches 32768. When the clock is written, bits 0 to 4 are set to 0 and bits 5 to 14 are set to the value of this field. (access: R/W) +#define RTC_CLOCK_INIT_SEC_COUNT_BIT 22 +#define RTC_CLOCK_INIT_SEC_COUNT_WIDTH 10 +#define RTC_CLOCK_INIT_SEC_COUNT_MASK 0xffc00000 + +// First digit of alarm seconds. (access: R/W) +#define RTC_ALARM_SECONDS_0_BIT 0 +#define RTC_ALARM_SECONDS_0_WIDTH 8 +#define RTC_ALARM_SECONDS_0_MASK 0xff + +// Second digit of alarm seconds. (access: R/W) +#define RTC_ALARM_SECONDS_1_BIT 0 +#define RTC_ALARM_SECONDS_1_WIDTH 8 +#define RTC_ALARM_SECONDS_1_MASK 0xff + +// First digit of alarm minutes. (access: R/W) +#define RTC_ALARM_MINUTES_0_BIT 8 +#define RTC_ALARM_MINUTES_0_WIDTH 8 +#define RTC_ALARM_MINUTES_0_MASK 0xff00 + +// Second digit of alarm minutes. (access: R/W) +#define RTC_ALARM_MINUTES_1_BIT 8 +#define RTC_ALARM_MINUTES_1_WIDTH 8 +#define RTC_ALARM_MINUTES_1_MASK 0xff00 + +// First digit of alarm hours. (access: R/W) +#define RTC_ALARM_HOURS_0_BIT 16 +#define RTC_ALARM_HOURS_0_WIDTH 6 +#define RTC_ALARM_HOURS_0_MASK 0x3f0000 + +// Second digit of alarm hours. (access: R/W) +#define RTC_ALARM_HOURS_1_BIT 16 +#define RTC_ALARM_HOURS_1_WIDTH 6 +#define RTC_ALARM_HOURS_1_MASK 0x3f0000 + +// Alarm enable. When set to 1, an event is generated when the alarm is matching the clock. (access: R/W) +#define RTC_ALARM_ENABLE_BIT 31 +#define RTC_ALARM_ENABLE_WIDTH 1 +#define RTC_ALARM_ENABLE_MASK 0x80000000 + +// Timer target. When the timer is enabled, an event is generated when the timer counter is matching this field. (access: R/W) +#define RTC_TIMER_TARGET_BIT 0 +#define RTC_TIMER_TARGET_WIDTH 17 +#define RTC_TIMER_TARGET_MASK 0x1ffff + +// Timer retrig. When set to 1, the timer is still enabled after an event is generated when the timer counter is matching the timer target. If it is set to 0, the timer is disabled after the event is generated. (access: R/W) +#define RTC_TIMER_RETRIG_BIT 30 +#define RTC_TIMER_RETRIG_WIDTH 1 +#define RTC_TIMER_RETRIG_MASK 0x40000000 + +// Timer enable. When set to 1, the timer counter is incremented every 1/32768 seconds and an event is generated when the timer counter is matching the timer target. (access: R/W) +#define RTC_TIMER_ENABLE_BIT 31 +#define RTC_TIMER_ENABLE_WIDTH 1 +#define RTC_TIMER_ENABLE_MASK 0x80000000 + +// First digit of date day. (access: R/W) +#define RTC_DATE_DAY_0_BIT 0 +#define RTC_DATE_DAY_0_WIDTH 6 +#define RTC_DATE_DAY_0_MASK 0x3f + +// Second digit of date day. (access: R/W) +#define RTC_DATE_DAY_1_BIT 0 +#define RTC_DATE_DAY_1_WIDTH 6 +#define RTC_DATE_DAY_1_MASK 0x3f + +// First digit of date month. (access: R/W) +#define RTC_DATE_MONTH_0_BIT 8 +#define RTC_DATE_MONTH_0_WIDTH 5 +#define RTC_DATE_MONTH_0_MASK 0x1f00 + +// Second digit of date month. (access: R/W) +#define RTC_DATE_MONTH_1_BIT 8 +#define RTC_DATE_MONTH_1_WIDTH 5 +#define RTC_DATE_MONTH_1_MASK 0x1f00 + +// First digit of date year. (access: R/W) +#define RTC_DATE_YEAR_0_BIT 16 +#define RTC_DATE_YEAR_0_WIDTH 14 +#define RTC_DATE_YEAR_0_MASK 0x3fff0000 + +// Second digit of date year. (access: R/W) +#define RTC_DATE_YEAR_1_BIT 16 +#define RTC_DATE_YEAR_1_WIDTH 14 +#define RTC_DATE_YEAR_1_MASK 0x3fff0000 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int seconds_0 :4 ; // First digit of clock seconds. + unsigned int seconds_1 :4 ; // Second digit of clock seconds. + unsigned int minutes_0 :4 ; // First digit of clock minutes. + unsigned int minutes_1 :4 ; // Second digit of clock minutes. + unsigned int hours_0 :4 ; // First digit of clock hours. + unsigned int hours_1 :2 ; // Second digit of clock hours. + unsigned int init_sec_count :10; // MSB part of second counter initial value. The second counter is incremented every 1/32768 seconds and is incrementing by 1 the number of seconds when it reaches 32768. When the clock is written, bits 0 to 4 are set to 0 and bits 5 to 14 are set to the value of this field. + }; + unsigned int raw; +} __attribute__((packed)) rtc_clock_t; + +typedef union { + struct { + unsigned int seconds_0 :8 ; // First digit of alarm seconds. + unsigned int seconds_1 :8 ; // Second digit of alarm seconds. + unsigned int minutes_0 :8 ; // First digit of alarm minutes. + unsigned int minutes_1 :8 ; // Second digit of alarm minutes. + unsigned int hours_0 :6 ; // First digit of alarm hours. + unsigned int hours_1 :6 ; // Second digit of alarm hours. + unsigned int padding0:9 ; + unsigned int enable :1 ; // Alarm enable. When set to 1, an event is generated when the alarm is matching the clock. + }; + unsigned int raw; +} __attribute__((packed)) rtc_alarm_t; + +typedef union { + struct { + unsigned int target :17; // Timer target. When the timer is enabled, an event is generated when the timer counter is matching this field. + unsigned int padding0:13; + unsigned int retrig :1 ; // Timer retrig. When set to 1, the timer is still enabled after an event is generated when the timer counter is matching the timer target. If it is set to 0, the timer is disabled after the event is generated. + unsigned int enable :1 ; // Timer enable. When set to 1, the timer counter is incremented every 1/32768 seconds and an event is generated when the timer counter is matching the timer target. + }; + unsigned int raw; +} __attribute__((packed)) rtc_timer_t; + +typedef union { + struct { + unsigned int day_0 :6 ; // First digit of date day. + unsigned int day_1 :6 ; // Second digit of date day. + unsigned int padding0:2 ; + unsigned int month_0 :5 ; // First digit of date month. + unsigned int month_1 :5 ; // Second digit of date month. + unsigned int padding1:3 ; + unsigned int year_0 :14; // First digit of date year. + unsigned int year_1 :14; // Second digit of date year. + }; + unsigned int raw; +} __attribute__((packed)) rtc_date_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_rtc_clock : public vp::reg_32 +{ +public: + inline void seconds_0_set(uint32_t value) { this->set_field(value, RTC_CLOCK_SECONDS_0_BIT, RTC_CLOCK_SECONDS_0_WIDTH); } + inline uint32_t seconds_0_get() { return this->get_field(RTC_CLOCK_SECONDS_0_BIT, RTC_CLOCK_SECONDS_0_WIDTH); } + inline void seconds_1_set(uint32_t value) { this->set_field(value, RTC_CLOCK_SECONDS_1_BIT, RTC_CLOCK_SECONDS_1_WIDTH); } + inline uint32_t seconds_1_get() { return this->get_field(RTC_CLOCK_SECONDS_1_BIT, RTC_CLOCK_SECONDS_1_WIDTH); } + inline void minutes_0_set(uint32_t value) { this->set_field(value, RTC_CLOCK_MINUTES_0_BIT, RTC_CLOCK_MINUTES_0_WIDTH); } + inline uint32_t minutes_0_get() { return this->get_field(RTC_CLOCK_MINUTES_0_BIT, RTC_CLOCK_MINUTES_0_WIDTH); } + inline void minutes_1_set(uint32_t value) { this->set_field(value, RTC_CLOCK_MINUTES_1_BIT, RTC_CLOCK_MINUTES_1_WIDTH); } + inline uint32_t minutes_1_get() { return this->get_field(RTC_CLOCK_MINUTES_1_BIT, RTC_CLOCK_MINUTES_1_WIDTH); } + inline void hours_0_set(uint32_t value) { this->set_field(value, RTC_CLOCK_HOURS_0_BIT, RTC_CLOCK_HOURS_0_WIDTH); } + inline uint32_t hours_0_get() { return this->get_field(RTC_CLOCK_HOURS_0_BIT, RTC_CLOCK_HOURS_0_WIDTH); } + inline void hours_1_set(uint32_t value) { this->set_field(value, RTC_CLOCK_HOURS_1_BIT, RTC_CLOCK_HOURS_1_WIDTH); } + inline uint32_t hours_1_get() { return this->get_field(RTC_CLOCK_HOURS_1_BIT, RTC_CLOCK_HOURS_1_WIDTH); } + inline void init_sec_count_set(uint32_t value) { this->set_field(value, RTC_CLOCK_INIT_SEC_COUNT_BIT, RTC_CLOCK_INIT_SEC_COUNT_WIDTH); } + inline uint32_t init_sec_count_get() { return this->get_field(RTC_CLOCK_INIT_SEC_COUNT_BIT, RTC_CLOCK_INIT_SEC_COUNT_WIDTH); } +}; + +class vp_rtc_alarm : public vp::reg_32 +{ +public: + inline void seconds_0_set(uint32_t value) { this->set_field(value, RTC_ALARM_SECONDS_0_BIT, RTC_ALARM_SECONDS_0_WIDTH); } + inline uint32_t seconds_0_get() { return this->get_field(RTC_ALARM_SECONDS_0_BIT, RTC_ALARM_SECONDS_0_WIDTH); } + inline void seconds_1_set(uint32_t value) { this->set_field(value, RTC_ALARM_SECONDS_1_BIT, RTC_ALARM_SECONDS_1_WIDTH); } + inline uint32_t seconds_1_get() { return this->get_field(RTC_ALARM_SECONDS_1_BIT, RTC_ALARM_SECONDS_1_WIDTH); } + inline void minutes_0_set(uint32_t value) { this->set_field(value, RTC_ALARM_MINUTES_0_BIT, RTC_ALARM_MINUTES_0_WIDTH); } + inline uint32_t minutes_0_get() { return this->get_field(RTC_ALARM_MINUTES_0_BIT, RTC_ALARM_MINUTES_0_WIDTH); } + inline void minutes_1_set(uint32_t value) { this->set_field(value, RTC_ALARM_MINUTES_1_BIT, RTC_ALARM_MINUTES_1_WIDTH); } + inline uint32_t minutes_1_get() { return this->get_field(RTC_ALARM_MINUTES_1_BIT, RTC_ALARM_MINUTES_1_WIDTH); } + inline void hours_0_set(uint32_t value) { this->set_field(value, RTC_ALARM_HOURS_0_BIT, RTC_ALARM_HOURS_0_WIDTH); } + inline uint32_t hours_0_get() { return this->get_field(RTC_ALARM_HOURS_0_BIT, RTC_ALARM_HOURS_0_WIDTH); } + inline void hours_1_set(uint32_t value) { this->set_field(value, RTC_ALARM_HOURS_1_BIT, RTC_ALARM_HOURS_1_WIDTH); } + inline uint32_t hours_1_get() { return this->get_field(RTC_ALARM_HOURS_1_BIT, RTC_ALARM_HOURS_1_WIDTH); } + inline void enable_set(uint32_t value) { this->set_field(value, RTC_ALARM_ENABLE_BIT, RTC_ALARM_ENABLE_WIDTH); } + inline uint32_t enable_get() { return this->get_field(RTC_ALARM_ENABLE_BIT, RTC_ALARM_ENABLE_WIDTH); } +}; + +class vp_rtc_timer : public vp::reg_32 +{ +public: + inline void target_set(uint32_t value) { this->set_field(value, RTC_TIMER_TARGET_BIT, RTC_TIMER_TARGET_WIDTH); } + inline uint32_t target_get() { return this->get_field(RTC_TIMER_TARGET_BIT, RTC_TIMER_TARGET_WIDTH); } + inline void retrig_set(uint32_t value) { this->set_field(value, RTC_TIMER_RETRIG_BIT, RTC_TIMER_RETRIG_WIDTH); } + inline uint32_t retrig_get() { return this->get_field(RTC_TIMER_RETRIG_BIT, RTC_TIMER_RETRIG_WIDTH); } + inline void enable_set(uint32_t value) { this->set_field(value, RTC_TIMER_ENABLE_BIT, RTC_TIMER_ENABLE_WIDTH); } + inline uint32_t enable_get() { return this->get_field(RTC_TIMER_ENABLE_BIT, RTC_TIMER_ENABLE_WIDTH); } +}; + +class vp_rtc_date : public vp::reg_32 +{ +public: + inline void day_0_set(uint32_t value) { this->set_field(value, RTC_DATE_DAY_0_BIT, RTC_DATE_DAY_0_WIDTH); } + inline uint32_t day_0_get() { return this->get_field(RTC_DATE_DAY_0_BIT, RTC_DATE_DAY_0_WIDTH); } + inline void day_1_set(uint32_t value) { this->set_field(value, RTC_DATE_DAY_1_BIT, RTC_DATE_DAY_1_WIDTH); } + inline uint32_t day_1_get() { return this->get_field(RTC_DATE_DAY_1_BIT, RTC_DATE_DAY_1_WIDTH); } + inline void month_0_set(uint32_t value) { this->set_field(value, RTC_DATE_MONTH_0_BIT, RTC_DATE_MONTH_0_WIDTH); } + inline uint32_t month_0_get() { return this->get_field(RTC_DATE_MONTH_0_BIT, RTC_DATE_MONTH_0_WIDTH); } + inline void month_1_set(uint32_t value) { this->set_field(value, RTC_DATE_MONTH_1_BIT, RTC_DATE_MONTH_1_WIDTH); } + inline uint32_t month_1_get() { return this->get_field(RTC_DATE_MONTH_1_BIT, RTC_DATE_MONTH_1_WIDTH); } + inline void year_0_set(uint32_t value) { this->set_field(value, RTC_DATE_YEAR_0_BIT, RTC_DATE_YEAR_0_WIDTH); } + inline uint32_t year_0_get() { return this->get_field(RTC_DATE_YEAR_0_BIT, RTC_DATE_YEAR_0_WIDTH); } + inline void year_1_set(uint32_t value) { this->set_field(value, RTC_DATE_YEAR_1_BIT, RTC_DATE_YEAR_1_WIDTH); } + inline uint32_t year_1_get() { return this->get_field(RTC_DATE_YEAR_1_BIT, RTC_DATE_YEAR_1_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int clock ; // Clock register + unsigned int alarm ; // Alarm register + unsigned int timer ; // Timer register + unsigned int date ; // Date register +} __attribute__((packed)) rtc_rtc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t rtc_clock_get(uint32_t base) { return ARCHI_READ(base, RTC_CLOCK_OFFSET); } +static inline void rtc_clock_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, RTC_CLOCK_OFFSET, value); } + +static inline uint32_t rtc_alarm_get(uint32_t base) { return ARCHI_READ(base, RTC_ALARM_OFFSET); } +static inline void rtc_alarm_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, RTC_ALARM_OFFSET, value); } + +static inline uint32_t rtc_timer_get(uint32_t base) { return ARCHI_READ(base, RTC_TIMER_OFFSET); } +static inline void rtc_timer_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, RTC_TIMER_OFFSET, value); } + +static inline uint32_t rtc_date_get(uint32_t base) { return ARCHI_READ(base, RTC_DATE_OFFSET); } +static inline void rtc_date_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, RTC_DATE_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define RTC_CLOCK_SECONDS_0_GET(value) (ARCHI_BEXTRACTU((value),4,0)) +#define RTC_CLOCK_SECONDS_0_GETS(value) (ARCHI_BEXTRACT((value),4,0)) +#define RTC_CLOCK_SECONDS_0_SET(value,field) (ARCHI_BINSERT((value),(field),4,0)) +#define RTC_CLOCK_SECONDS_0(val) ((val) << 0) + +#define RTC_CLOCK_SECONDS_1_GET(value) (ARCHI_BEXTRACTU((value),4,4)) +#define RTC_CLOCK_SECONDS_1_GETS(value) (ARCHI_BEXTRACT((value),4,4)) +#define RTC_CLOCK_SECONDS_1_SET(value,field) (ARCHI_BINSERT((value),(field),4,4)) +#define RTC_CLOCK_SECONDS_1(val) ((val) << 4) + +#define RTC_CLOCK_MINUTES_0_GET(value) (ARCHI_BEXTRACTU((value),4,8)) +#define RTC_CLOCK_MINUTES_0_GETS(value) (ARCHI_BEXTRACT((value),4,8)) +#define RTC_CLOCK_MINUTES_0_SET(value,field) (ARCHI_BINSERT((value),(field),4,8)) +#define RTC_CLOCK_MINUTES_0(val) ((val) << 8) + +#define RTC_CLOCK_MINUTES_1_GET(value) (ARCHI_BEXTRACTU((value),4,12)) +#define RTC_CLOCK_MINUTES_1_GETS(value) (ARCHI_BEXTRACT((value),4,12)) +#define RTC_CLOCK_MINUTES_1_SET(value,field) (ARCHI_BINSERT((value),(field),4,12)) +#define RTC_CLOCK_MINUTES_1(val) ((val) << 12) + +#define RTC_CLOCK_HOURS_0_GET(value) (ARCHI_BEXTRACTU((value),4,16)) +#define RTC_CLOCK_HOURS_0_GETS(value) (ARCHI_BEXTRACT((value),4,16)) +#define RTC_CLOCK_HOURS_0_SET(value,field) (ARCHI_BINSERT((value),(field),4,16)) +#define RTC_CLOCK_HOURS_0(val) ((val) << 16) + +#define RTC_CLOCK_HOURS_1_GET(value) (ARCHI_BEXTRACTU((value),2,20)) +#define RTC_CLOCK_HOURS_1_GETS(value) (ARCHI_BEXTRACT((value),2,20)) +#define RTC_CLOCK_HOURS_1_SET(value,field) (ARCHI_BINSERT((value),(field),2,20)) +#define RTC_CLOCK_HOURS_1(val) ((val) << 20) + +#define RTC_CLOCK_INIT_SEC_COUNT_GET(value) (ARCHI_BEXTRACTU((value),10,22)) +#define RTC_CLOCK_INIT_SEC_COUNT_GETS(value) (ARCHI_BEXTRACT((value),10,22)) +#define RTC_CLOCK_INIT_SEC_COUNT_SET(value,field) (ARCHI_BINSERT((value),(field),10,22)) +#define RTC_CLOCK_INIT_SEC_COUNT(val) ((val) << 22) + +#define RTC_ALARM_SECONDS_0_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define RTC_ALARM_SECONDS_0_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define RTC_ALARM_SECONDS_0_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define RTC_ALARM_SECONDS_0(val) ((val) << 0) + +#define RTC_ALARM_SECONDS_1_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define RTC_ALARM_SECONDS_1_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define RTC_ALARM_SECONDS_1_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define RTC_ALARM_SECONDS_1(val) ((val) << 0) + +#define RTC_ALARM_MINUTES_0_GET(value) (ARCHI_BEXTRACTU((value),8,8)) +#define RTC_ALARM_MINUTES_0_GETS(value) (ARCHI_BEXTRACT((value),8,8)) +#define RTC_ALARM_MINUTES_0_SET(value,field) (ARCHI_BINSERT((value),(field),8,8)) +#define RTC_ALARM_MINUTES_0(val) ((val) << 8) + +#define RTC_ALARM_MINUTES_1_GET(value) (ARCHI_BEXTRACTU((value),8,8)) +#define RTC_ALARM_MINUTES_1_GETS(value) (ARCHI_BEXTRACT((value),8,8)) +#define RTC_ALARM_MINUTES_1_SET(value,field) (ARCHI_BINSERT((value),(field),8,8)) +#define RTC_ALARM_MINUTES_1(val) ((val) << 8) + +#define RTC_ALARM_HOURS_0_GET(value) (ARCHI_BEXTRACTU((value),6,16)) +#define RTC_ALARM_HOURS_0_GETS(value) (ARCHI_BEXTRACT((value),6,16)) +#define RTC_ALARM_HOURS_0_SET(value,field) (ARCHI_BINSERT((value),(field),6,16)) +#define RTC_ALARM_HOURS_0(val) ((val) << 16) + +#define RTC_ALARM_HOURS_1_GET(value) (ARCHI_BEXTRACTU((value),6,16)) +#define RTC_ALARM_HOURS_1_GETS(value) (ARCHI_BEXTRACT((value),6,16)) +#define RTC_ALARM_HOURS_1_SET(value,field) (ARCHI_BINSERT((value),(field),6,16)) +#define RTC_ALARM_HOURS_1(val) ((val) << 16) + +#define RTC_ALARM_ENABLE_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define RTC_ALARM_ENABLE_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define RTC_ALARM_ENABLE_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define RTC_ALARM_ENABLE(val) ((val) << 31) + +#define RTC_TIMER_TARGET_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define RTC_TIMER_TARGET_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define RTC_TIMER_TARGET_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define RTC_TIMER_TARGET(val) ((val) << 0) + +#define RTC_TIMER_RETRIG_GET(value) (ARCHI_BEXTRACTU((value),1,30)) +#define RTC_TIMER_RETRIG_GETS(value) (ARCHI_BEXTRACT((value),1,30)) +#define RTC_TIMER_RETRIG_SET(value,field) (ARCHI_BINSERT((value),(field),1,30)) +#define RTC_TIMER_RETRIG(val) ((val) << 30) + +#define RTC_TIMER_ENABLE_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define RTC_TIMER_ENABLE_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define RTC_TIMER_ENABLE_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define RTC_TIMER_ENABLE(val) ((val) << 31) + +#define RTC_DATE_DAY_0_GET(value) (ARCHI_BEXTRACTU((value),6,0)) +#define RTC_DATE_DAY_0_GETS(value) (ARCHI_BEXTRACT((value),6,0)) +#define RTC_DATE_DAY_0_SET(value,field) (ARCHI_BINSERT((value),(field),6,0)) +#define RTC_DATE_DAY_0(val) ((val) << 0) + +#define RTC_DATE_DAY_1_GET(value) (ARCHI_BEXTRACTU((value),6,0)) +#define RTC_DATE_DAY_1_GETS(value) (ARCHI_BEXTRACT((value),6,0)) +#define RTC_DATE_DAY_1_SET(value,field) (ARCHI_BINSERT((value),(field),6,0)) +#define RTC_DATE_DAY_1(val) ((val) << 0) + +#define RTC_DATE_MONTH_0_GET(value) (ARCHI_BEXTRACTU((value),5,8)) +#define RTC_DATE_MONTH_0_GETS(value) (ARCHI_BEXTRACT((value),5,8)) +#define RTC_DATE_MONTH_0_SET(value,field) (ARCHI_BINSERT((value),(field),5,8)) +#define RTC_DATE_MONTH_0(val) ((val) << 8) + +#define RTC_DATE_MONTH_1_GET(value) (ARCHI_BEXTRACTU((value),5,8)) +#define RTC_DATE_MONTH_1_GETS(value) (ARCHI_BEXTRACT((value),5,8)) +#define RTC_DATE_MONTH_1_SET(value,field) (ARCHI_BINSERT((value),(field),5,8)) +#define RTC_DATE_MONTH_1(val) ((val) << 8) + +#define RTC_DATE_YEAR_0_GET(value) (ARCHI_BEXTRACTU((value),14,16)) +#define RTC_DATE_YEAR_0_GETS(value) (ARCHI_BEXTRACT((value),14,16)) +#define RTC_DATE_YEAR_0_SET(value,field) (ARCHI_BINSERT((value),(field),14,16)) +#define RTC_DATE_YEAR_0(val) ((val) << 16) + +#define RTC_DATE_YEAR_1_GET(value) (ARCHI_BEXTRACTU((value),14,16)) +#define RTC_DATE_YEAR_1_GETS(value) (ARCHI_BEXTRACT((value),14,16)) +#define RTC_DATE_YEAR_1_SET(value,field) (ARCHI_BINSERT((value),(field),14,16)) +#define RTC_DATE_YEAR_1(val) ((val) << 16) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v1.h b/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v1.h new file mode 100644 index 0000000..7edbdcc --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v1.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_SOC_EU_SOC_EU_V1_H__ +#define __ARCHI_SOC_EU_SOC_EU_V1_H__ + +#define SOC_EU_EVENT 0x00 +#define SOC_FC_FIRST_MASK 0x04 +#define SOC_FC_MASK_MSB 0x04 +#define SOC_FC_MASK_LSB 0x08 +#define SOC_CL_FIRST_MASK 0x0c +#define SOC_CL_MASK_MSB 0x0c +#define SOC_CL_MASK_LSB 0x10 +#define SOC_PR_FIRST_MASK 0x14 +#define SOC_PR_MASK_MSB 0x14 +#define SOC_PR_MASK_LSB 0x18 +#define SOC_ERR_MASK_MSB 0x1c +#define SOC_ERR_MASK_LSB 0x20 +#define SOC_TIMER_SEL_HI 0x24 +#define SOC_TIMER_SEL_LO 0x28 + +#define SOC_NB_EVENT_REGS 2 + +#define SOC_FC_MASK(x) (SOC_FC_FIRST_MASK + (x)*4) +#define SOC_CL_MASK(x) (SOC_CL_FIRST_MASK + (x)*4) +#define SOC_PR_MASK(x) (SOC_PR_FIRST_MASK + (x)*4) + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v2.h b/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v2.h new file mode 100644 index 0000000..768497a --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v2.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_SOC_EU_SOC_EU_V2_H__ +#define __ARCHI_SOC_EU_SOC_EU_V2_H__ + +#define SOC_EU_EVENT 0x00 +#define SOC_FC_FIRST_MASK 0x04 +#define SOC_CL_FIRST_MASK 0x24 +#define SOC_PR_FIRST_MASK 0x44 +#define SOC_ERR_FIRST_MASK 0x64 +#define SOC_TIMER_SEL_HI 0x84 +#define SOC_TIMER_SEL_LO 0x88 + +#define SOC_EU_EVENT_0 0x1 +#define SOC_EU_EVENT_1 0x2 +#define SOC_EU_EVENT_2 0x4 +#define SOC_EU_EVENT_3 0x8 +#define SOC_EU_EVENT_4 0x10 +#define SOC_EU_EVENT_5 0x20 +#define SOC_EU_EVENT_6 0x40 +#define SOC_EU_EVENT_7 0x80 + +#define SOC_TIMER_SEL_ENABLE_SHIFT 31 +#define SOC_TIMER_SEL_EVT_SHIFT 0 +#define SOC_TIMER_SEL_EVT_WIDTH 8 +#define SOC_TIMER_SEL_EVT_MASK ((~0U) >> (32 - SOC_TIMER_SEL_EVT_WIDTH)) +// #define SOC_TIMER_SEL_EVT_MASK 0xff + +#define SOC_TIMER_SEL_ENABLE_DISABLED 0 +#define SOC_TIMER_SEL_ENABLE_ENABLED 1 + +#define SOC_TIMER_SEL_ENABLE_DIS (0 << SOC_TIMER_SEL_ENABLE_SHIFT) +#define SOC_TIMER_SEL_ENABLE_ENA (1 << SOC_TIMER_SEL_ENABLE_SHIFT) +#define SOC_TIMER_SEL_EVT_VAL(val) ((val) << SOC_TIMER_SEL_EVT_SHIFT) + +// related to XX_FIRST_MASK registers +#define SOC_NB_EVENT_REGS 8 +#define SOC_NB_EVENT_TARGETS 3 + +#define SOC_FC_MASK(x) (SOC_FC_FIRST_MASK + (x)*4) +#define SOC_CL_MASK(x) (SOC_CL_FIRST_MASK + (x)*4) +#define SOC_PR_MASK(x) (SOC_PR_FIRST_MASK + (x)*4) + +#define ARCHI_SOC_EVENT_PERIPH_EVT_BASE(periph) ((periph)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT) + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v3.h b/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v3.h new file mode 100644 index 0000000..5bbc569 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/soc_eu/soc_eu_v3.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_SOC_EU_SOC_EU_V3_H__ +#define __ARCHI_SOC_EU_SOC_EU_V3_H__ + + +#define SOC_EU_EVENT 0x00 +#define SOC_FC_FIRST_MASK 0x10 +#define SOC_CL_FIRST_MASK 0x20 +#define SOC_PR_FIRST_MASK 0x30 +#define SOC_ERR_FIRST_MASK 0x40 +#define SOC_TIMER_SEL_HI 0x08 +#define SOC_TIMER_SEL_LO 0x0C + +// compatibility definitions +#define SOC_FC_MASK_LSB SOC_FC_FIRST_MASK +#define SOC_FC_MASK_MSB (SOC_FC_FIRST_MASK + 0x4) +#define SOC_CL_MASK_LSB SOC_CL_FIRST_MASK +#define SOC_CL_MASK_MSB (SOC_CL_FIRST_MASK + 0x4) +#define SOC_PR_MASK_LSB SOC_PR_FIRST_MASK +#define SOC_PR_MASK_MSB (SOC_PR_FIRST_MASK + 0x4) + +#define SOC_EU_EVENT_0 0x1 +#define SOC_EU_EVENT_1 0x2 +#define SOC_EU_EVENT_2 0x4 +#define SOC_EU_EVENT_3 0x8 +#define SOC_EU_EVENT_4 0x10 +#define SOC_EU_EVENT_5 0x20 +#define SOC_EU_EVENT_6 0x40 +#define SOC_EU_EVENT_7 0x80 + +#define SOC_TIMER_SEL_ENABLE_SHIFT 31 +#define SOC_TIMER_SEL_EVT_SHIFT 0 +#define SOC_TIMER_SEL_EVT_WIDTH 8 +#define SOC_TIMER_SEL_EVT_MASK ((~0U) >> (32 - SOC_TIMER_SEL_EVT_WIDTH)) +// #define SOC_TIMER_SEL_EVT_MASK 0xff + +#define SOC_TIMER_SEL_ENABLE_DISABLED 0 +#define SOC_TIMER_SEL_ENABLE_ENABLED 1 + +#define SOC_TIMER_SEL_ENABLE_DIS (0 << SOC_TIMER_SEL_ENABLE_SHIFT) +#define SOC_TIMER_SEL_ENABLE_ENA (1 << SOC_TIMER_SEL_ENABLE_SHIFT) +#define SOC_TIMER_SEL_EVT_VAL(val) ((val) << SOC_TIMER_SEL_EVT_SHIFT) + +// related to XX_FIRST_MASK registers +#define SOC_NB_EVENT_REGS 4 +#define SOC_NB_EVENT_TARGETS 3 + +#define SOC_FC_MASK(x) (SOC_FC_FIRST_MASK + (x)*4) +#define SOC_CL_MASK(x) (SOC_CL_FIRST_MASK + (x)*4) +#define SOC_PR_MASK(x) (SOC_PR_FIRST_MASK + (x)*4) + +#define ARCHI_SOC_EVENT_PERIPH_EVT_BASE(periph) ((periph)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT) + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/spim/spi_v1.h b/sw/pulp-sdk/archi/include/archi/spim/spi_v1.h new file mode 100644 index 0000000..c172881 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/spim/spi_v1.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_SPIM_SPI_V1_H__ +#define __ARCHI_SPIM_SPI_V1_H__ + +#define PULP_SPI_OFFSET 0xA102000 + +#define PULP_SPI_FIFO_SIZE 8 + +#define PULP_SPI_QPI 1 +#define PULP_SPI_NO_QPI 0 + +#define PULP_SPI_CMD_RD 0 +#define PULP_SPI_CMD_WR 1 +#define PULP_SPI_CMD_QRD 2 +#define PULP_SPI_CMD_QWR 3 +#define PULP_SPI_CMD_SWRST 4 + +#define PULP_SPI_CSN0 0 +#define PULP_SPI_CSN1 1 +#define PULP_SPI_CSN2 2 +#define PULP_SPI_CSN3 3 + +#define PULP_SPI_REG_STATUS ( 0x00 ) +#define PULP_SPI_REG_CLKDIV ( 0x04 ) +#define PULP_SPI_REG_SPICMD ( 0x08 ) +#define PULP_SPI_REG_SPIADR ( 0x0C ) +#define PULP_SPI_REG_SPILEN ( 0x10 ) +#define PULP_SPI_REG_SPIDUM ( 0x14 ) +#define PULP_SPI_REG_TXFIFO ( 0x18 ) +#define PULP_SPI_REG_RXFIFO ( 0x20 ) +#define PULP_SPI_REG_INTCFG ( 0x24 ) +#define PULP_SPI_REG_INTSTA ( 0x28 ) + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/stdout/stdout_v2.h b/sw/pulp-sdk/archi/include/archi/stdout/stdout_v2.h new file mode 100644 index 0000000..f7c8aff --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/stdout/stdout_v2.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARCHI_STDOUT_STDOUT_V2_H +#define ARCHI_STDOUT_STDOUT_V2_H + +#define STDOUT_PUTC_OFFSET 0x0 +#define STDOUT_OPEN_OFFSET 0x2000 +#define STDOUT_OPEN_END_OFFSET 0x3000 +#define STDOUT_READ_OFFSET 0x4000 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/stdout/stdout_v3.h b/sw/pulp-sdk/archi/include/archi/stdout/stdout_v3.h new file mode 100644 index 0000000..f7c8aff --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/stdout/stdout_v3.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARCHI_STDOUT_STDOUT_V2_H +#define ARCHI_STDOUT_STDOUT_V2_H + +#define STDOUT_PUTC_OFFSET 0x0 +#define STDOUT_OPEN_OFFSET 0x2000 +#define STDOUT_OPEN_END_OFFSET 0x3000 +#define STDOUT_READ_OFFSET 0x4000 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/timer/timer_v2.h b/sw/pulp-sdk/archi/include/archi/timer/timer_v2.h new file mode 100644 index 0000000..d695564 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/timer/timer_v2.h @@ -0,0 +1,617 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_TIMER_TIMER_V2_H__ +#define __INCLUDE_ARCHI_TIMER_TIMER_V2_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Timer Low Configuration register. +#define TIMER_CFG_LO_OFFSET 0x0 + +// Timer High Configuration register. +#define TIMER_CFG_HI_OFFSET 0x4 + +// Timer Low counter value register. +#define TIMER_CNT_LO_OFFSET 0x8 + +// Timer High counter value register. +#define TIMER_CNT_HI_OFFSET 0xc + +// Timer Low comparator value register. +#define TIMER_CMP_LO_OFFSET 0x10 + +// Timer High comparator value register. +#define TIMER_CMP_HI_OFFSET 0x14 + +// Start Timer Low counting register. +#define TIMER_START_LO_OFFSET 0x18 + +// Start Timer High counting register. +#define TIMER_START_HI_OFFSET 0x1c + +// Reset Timer Low counter register. +#define TIMER_RESET_LO_OFFSET 0x20 + +// Reset Timer High counter register. +#define TIMER_RESET_HI_OFFSET 0x24 + + + +// +// REGISTERS FIELDS +// + +// Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_LO_ENABLE_BIT 0 +#define TIMER_CFG_LO_ENABLE_WIDTH 1 +#define TIMER_CFG_LO_ENABLE_MASK 0x1 + +// Timer low counter reset command bitfield. Cleared after Timer Low reset execution. (access: R/W) +#define TIMER_CFG_LO_RESET_BIT 1 +#define TIMER_CFG_LO_RESET_WIDTH 1 +#define TIMER_CFG_LO_RESET_MASK 0x2 + +// Timer low compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_LO_IRQEN_BIT 2 +#define TIMER_CFG_LO_IRQEN_WIDTH 1 +#define TIMER_CFG_LO_IRQEN_MASK 0x4 + +// Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_LO_IEM_BIT 3 +#define TIMER_CFG_LO_IEM_WIDTH 1 +#define TIMER_CFG_LO_IEM_MASK 0x8 + +// Timer low continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs. (access: R/W) +#define TIMER_CFG_LO_MODE_BIT 4 +#define TIMER_CFG_LO_MODE_WIDTH 1 +#define TIMER_CFG_LO_MODE_MASK 0x10 + +// Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low when compare match with CMP_LO occurs. (access: R/W) +#define TIMER_CFG_LO_ONE_S_BIT 5 +#define TIMER_CFG_LO_ONE_S_WIDTH 1 +#define TIMER_CFG_LO_ONE_S_MASK 0x20 + +// Timer low prescaler enable configuration bitfield:- 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_LO_PEN_BIT 6 +#define TIMER_CFG_LO_PEN_WIDTH 1 +#define TIMER_CFG_LO_PEN_MASK 0x40 + +// Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz (access: R/W) +#define TIMER_CFG_LO_CCFG_BIT 7 +#define TIMER_CFG_LO_CCFG_WIDTH 1 +#define TIMER_CFG_LO_CCFG_MASK 0x80 + +// Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL) (access: R/W) +#define TIMER_CFG_LO_PVAL_BIT 8 +#define TIMER_CFG_LO_PVAL_WIDTH 8 +#define TIMER_CFG_LO_PVAL_MASK 0xff00 + +// Timer low + Timer high 64bit cascaded mode configuration bitfield. (access: R/W) +#define TIMER_CFG_LO_CASC_BIT 31 +#define TIMER_CFG_LO_CASC_WIDTH 1 +#define TIMER_CFG_LO_CASC_MASK 0x80000000 + +// Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_HI_ENABLE_BIT 0 +#define TIMER_CFG_HI_ENABLE_WIDTH 1 +#define TIMER_CFG_HI_ENABLE_MASK 0x1 + +// Timer high counter reset command bitfield. Cleared after Timer high reset execution. (access: W) +#define TIMER_CFG_HI_RESET_BIT 1 +#define TIMER_CFG_HI_RESET_WIDTH 1 +#define TIMER_CFG_HI_RESET_MASK 0x2 + +// Timer high compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_HI_IRQEN_BIT 2 +#define TIMER_CFG_HI_IRQEN_WIDTH 1 +#define TIMER_CFG_HI_IRQEN_MASK 0x4 + +// Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_HI_IEM_BIT 3 +#define TIMER_CFG_HI_IEM_WIDTH 1 +#define TIMER_CFG_HI_IEM_MASK 0x8 + +// Timer high continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_LO occurs. (access: R/W) +#define TIMER_CFG_HI_MODE_BIT 4 +#define TIMER_CFG_HI_MODE_WIDTH 1 +#define TIMER_CFG_HI_MODE_MASK 0x10 + +// Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer high when compare match with CMP_LO occurs. (access: R/W) +#define TIMER_CFG_HI_ONE_S_BIT 5 +#define TIMER_CFG_HI_ONE_S_WIDTH 1 +#define TIMER_CFG_HI_ONE_S_MASK 0x20 + +// Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define TIMER_CFG_HI_PEN_BIT 6 +#define TIMER_CFG_HI_PEN_WIDTH 1 +#define TIMER_CFG_HI_PEN_MASK 0x40 + +// Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz (access: R/W) +#define TIMER_CFG_HI_CLKCFG_BIT 7 +#define TIMER_CFG_HI_CLKCFG_WIDTH 1 +#define TIMER_CFG_HI_CLKCFG_MASK 0x80 + +// Timer Low counter value bitfield. (access: R/W) +#define TIMER_CNT_LO_CNT_LO_BIT 0 +#define TIMER_CNT_LO_CNT_LO_WIDTH 32 +#define TIMER_CNT_LO_CNT_LO_MASK 0xffffffff + +// Timer High counter value bitfield. (access: R/W) +#define TIMER_CNT_HI_CNT_HI_BIT 0 +#define TIMER_CNT_HI_CNT_HI_WIDTH 32 +#define TIMER_CNT_HI_CNT_HI_MASK 0xffffffff + +// Timer Low comparator value bitfield. (access: R/W) +#define TIMER_CMP_LO_CMP_LO_BIT 0 +#define TIMER_CMP_LO_CMP_LO_WIDTH 32 +#define TIMER_CMP_LO_CMP_LO_MASK 0xffffffff + +// Timer High comparator value bitfield. (access: R/W) +#define TIMER_CMP_HI_CMP_HI_BIT 0 +#define TIMER_CMP_HI_CMP_HI_WIDTH 32 +#define TIMER_CMP_HI_CMP_HI_MASK 0xffffffff + +// Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set. (access: W) +#define TIMER_START_LO_STRT_LO_BIT 0 +#define TIMER_START_LO_STRT_LO_WIDTH 1 +#define TIMER_START_LO_STRT_LO_MASK 0x1 + +// Timer High start command bitfield. When executed, CFG_HI.ENABLE is set. (access: W) +#define TIMER_START_HI_STRT_HI_BIT 0 +#define TIMER_START_HI_STRT_HI_WIDTH 1 +#define TIMER_START_HI_STRT_HI_MASK 0x1 + +// Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set. (access: W) +#define TIMER_RESET_LO_RST_LO_BIT 0 +#define TIMER_RESET_LO_RST_LO_WIDTH 1 +#define TIMER_RESET_LO_RST_LO_MASK 0x1 + +// Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set. (access: W) +#define TIMER_RESET_HI_RST_HI_BIT 0 +#define TIMER_RESET_HI_RST_HI_WIDTH 1 +#define TIMER_RESET_HI_RST_HI_MASK 0x1 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int enable :1 ; // Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int reset :1 ; // Timer low counter reset command bitfield. Cleared after Timer Low reset execution. + unsigned int irqen :1 ; // Timer low compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int iem :1 ; // Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int mode :1 ; // Timer low continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer low counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with CMP_LO occurs. + unsigned int one_s :1 ; // Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low when compare match with CMP_LO occurs. + unsigned int pen :1 ; // Timer low prescaler enable configuration bitfield:- 1'b0: disabled - 1'b1: enabled + unsigned int ccfg :1 ; // Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz + unsigned int pval :8 ; // Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL) + unsigned int padding0:15; + unsigned int casc :1 ; // Timer low + Timer high 64bit cascaded mode configuration bitfield. + }; + unsigned int raw; +} __attribute__((packed)) timer_cfg_lo_t; + +typedef union { + struct { + unsigned int enable :1 ; // Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int reset :1 ; // Timer high counter reset command bitfield. Cleared after Timer high reset execution. + unsigned int irqen :1 ; // Timer high compare match interrupt enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int iem :1 ; // Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int mode :1 ; // Timer high continuous mode configuration bitfield: - 1'b0: Continue mode - continue incrementing Timer high counter when compare match with CMP_LO occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with CMP_LO occurs. + unsigned int one_s :1 ; // Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled counting when compare match with CMP_LO occurs. - 1'b1: disable Timer high when compare match with CMP_LO occurs. + unsigned int pen :1 ; // Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int clkcfg :1 ; // Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz + }; + unsigned int raw; +} __attribute__((packed)) timer_cfg_hi_t; + +typedef union { + struct { + unsigned int cnt_lo :32; // Timer Low counter value bitfield. + }; + unsigned int raw; +} __attribute__((packed)) timer_cnt_lo_t; + +typedef union { + struct { + unsigned int cnt_hi :32; // Timer High counter value bitfield. + }; + unsigned int raw; +} __attribute__((packed)) timer_cnt_hi_t; + +typedef union { + struct { + unsigned int cmp_lo :32; // Timer Low comparator value bitfield. + }; + unsigned int raw; +} __attribute__((packed)) timer_cmp_lo_t; + +typedef union { + struct { + unsigned int cmp_hi :32; // Timer High comparator value bitfield. + }; + unsigned int raw; +} __attribute__((packed)) timer_cmp_hi_t; + +typedef union { + struct { + unsigned int strt_lo :1 ; // Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set. + }; + unsigned int raw; +} __attribute__((packed)) timer_start_lo_t; + +typedef union { + struct { + unsigned int strt_hi :1 ; // Timer High start command bitfield. When executed, CFG_HI.ENABLE is set. + }; + unsigned int raw; +} __attribute__((packed)) timer_start_hi_t; + +typedef union { + struct { + unsigned int rst_lo :1 ; // Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set. + }; + unsigned int raw; +} __attribute__((packed)) timer_reset_lo_t; + +typedef union { + struct { + unsigned int rst_hi :1 ; // Timer High counter reset command bitfield. When executed, CFG_HI.RESET is set. + }; + unsigned int raw; +} __attribute__((packed)) timer_reset_hi_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_timer_cfg_lo : public vp::reg_32 +{ +public: + inline void enable_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_ENABLE_BIT, TIMER_CFG_LO_ENABLE_WIDTH); } + inline uint32_t enable_get() { return this->get_field(TIMER_CFG_LO_ENABLE_BIT, TIMER_CFG_LO_ENABLE_WIDTH); } + inline void reset_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_RESET_BIT, TIMER_CFG_LO_RESET_WIDTH); } + inline uint32_t reset_get() { return this->get_field(TIMER_CFG_LO_RESET_BIT, TIMER_CFG_LO_RESET_WIDTH); } + inline void irqen_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_IRQEN_BIT, TIMER_CFG_LO_IRQEN_WIDTH); } + inline uint32_t irqen_get() { return this->get_field(TIMER_CFG_LO_IRQEN_BIT, TIMER_CFG_LO_IRQEN_WIDTH); } + inline void iem_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_IEM_BIT, TIMER_CFG_LO_IEM_WIDTH); } + inline uint32_t iem_get() { return this->get_field(TIMER_CFG_LO_IEM_BIT, TIMER_CFG_LO_IEM_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_MODE_BIT, TIMER_CFG_LO_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(TIMER_CFG_LO_MODE_BIT, TIMER_CFG_LO_MODE_WIDTH); } + inline void one_s_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_ONE_S_BIT, TIMER_CFG_LO_ONE_S_WIDTH); } + inline uint32_t one_s_get() { return this->get_field(TIMER_CFG_LO_ONE_S_BIT, TIMER_CFG_LO_ONE_S_WIDTH); } + inline void pen_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_PEN_BIT, TIMER_CFG_LO_PEN_WIDTH); } + inline uint32_t pen_get() { return this->get_field(TIMER_CFG_LO_PEN_BIT, TIMER_CFG_LO_PEN_WIDTH); } + inline void ccfg_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_CCFG_BIT, TIMER_CFG_LO_CCFG_WIDTH); } + inline uint32_t ccfg_get() { return this->get_field(TIMER_CFG_LO_CCFG_BIT, TIMER_CFG_LO_CCFG_WIDTH); } + inline void pval_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_PVAL_BIT, TIMER_CFG_LO_PVAL_WIDTH); } + inline uint32_t pval_get() { return this->get_field(TIMER_CFG_LO_PVAL_BIT, TIMER_CFG_LO_PVAL_WIDTH); } + inline void casc_set(uint32_t value) { this->set_field(value, TIMER_CFG_LO_CASC_BIT, TIMER_CFG_LO_CASC_WIDTH); } + inline uint32_t casc_get() { return this->get_field(TIMER_CFG_LO_CASC_BIT, TIMER_CFG_LO_CASC_WIDTH); } +}; + +class vp_timer_cfg_hi : public vp::reg_32 +{ +public: + inline void enable_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_ENABLE_BIT, TIMER_CFG_HI_ENABLE_WIDTH); } + inline uint32_t enable_get() { return this->get_field(TIMER_CFG_HI_ENABLE_BIT, TIMER_CFG_HI_ENABLE_WIDTH); } + inline void reset_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_RESET_BIT, TIMER_CFG_HI_RESET_WIDTH); } + inline uint32_t reset_get() { return this->get_field(TIMER_CFG_HI_RESET_BIT, TIMER_CFG_HI_RESET_WIDTH); } + inline void irqen_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_IRQEN_BIT, TIMER_CFG_HI_IRQEN_WIDTH); } + inline uint32_t irqen_get() { return this->get_field(TIMER_CFG_HI_IRQEN_BIT, TIMER_CFG_HI_IRQEN_WIDTH); } + inline void iem_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_IEM_BIT, TIMER_CFG_HI_IEM_WIDTH); } + inline uint32_t iem_get() { return this->get_field(TIMER_CFG_HI_IEM_BIT, TIMER_CFG_HI_IEM_WIDTH); } + inline void mode_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_MODE_BIT, TIMER_CFG_HI_MODE_WIDTH); } + inline uint32_t mode_get() { return this->get_field(TIMER_CFG_HI_MODE_BIT, TIMER_CFG_HI_MODE_WIDTH); } + inline void one_s_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_ONE_S_BIT, TIMER_CFG_HI_ONE_S_WIDTH); } + inline uint32_t one_s_get() { return this->get_field(TIMER_CFG_HI_ONE_S_BIT, TIMER_CFG_HI_ONE_S_WIDTH); } + inline void pen_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_PEN_BIT, TIMER_CFG_HI_PEN_WIDTH); } + inline uint32_t pen_get() { return this->get_field(TIMER_CFG_HI_PEN_BIT, TIMER_CFG_HI_PEN_WIDTH); } + inline void clkcfg_set(uint32_t value) { this->set_field(value, TIMER_CFG_HI_CLKCFG_BIT, TIMER_CFG_HI_CLKCFG_WIDTH); } + inline uint32_t clkcfg_get() { return this->get_field(TIMER_CFG_HI_CLKCFG_BIT, TIMER_CFG_HI_CLKCFG_WIDTH); } +}; + +class vp_timer_cnt_lo : public vp::reg_32 +{ +public: + inline void cnt_lo_set(uint32_t value) { this->set_field(value, TIMER_CNT_LO_CNT_LO_BIT, TIMER_CNT_LO_CNT_LO_WIDTH); } + inline uint32_t cnt_lo_get() { return this->get_field(TIMER_CNT_LO_CNT_LO_BIT, TIMER_CNT_LO_CNT_LO_WIDTH); } +}; + +class vp_timer_cnt_hi : public vp::reg_32 +{ +public: + inline void cnt_hi_set(uint32_t value) { this->set_field(value, TIMER_CNT_HI_CNT_HI_BIT, TIMER_CNT_HI_CNT_HI_WIDTH); } + inline uint32_t cnt_hi_get() { return this->get_field(TIMER_CNT_HI_CNT_HI_BIT, TIMER_CNT_HI_CNT_HI_WIDTH); } +}; + +class vp_timer_cmp_lo : public vp::reg_32 +{ +public: + inline void cmp_lo_set(uint32_t value) { this->set_field(value, TIMER_CMP_LO_CMP_LO_BIT, TIMER_CMP_LO_CMP_LO_WIDTH); } + inline uint32_t cmp_lo_get() { return this->get_field(TIMER_CMP_LO_CMP_LO_BIT, TIMER_CMP_LO_CMP_LO_WIDTH); } +}; + +class vp_timer_cmp_hi : public vp::reg_32 +{ +public: + inline void cmp_hi_set(uint32_t value) { this->set_field(value, TIMER_CMP_HI_CMP_HI_BIT, TIMER_CMP_HI_CMP_HI_WIDTH); } + inline uint32_t cmp_hi_get() { return this->get_field(TIMER_CMP_HI_CMP_HI_BIT, TIMER_CMP_HI_CMP_HI_WIDTH); } +}; + +class vp_timer_start_lo : public vp::reg_32 +{ +public: + inline void strt_lo_set(uint32_t value) { this->set_field(value, TIMER_START_LO_STRT_LO_BIT, TIMER_START_LO_STRT_LO_WIDTH); } + inline uint32_t strt_lo_get() { return this->get_field(TIMER_START_LO_STRT_LO_BIT, TIMER_START_LO_STRT_LO_WIDTH); } +}; + +class vp_timer_start_hi : public vp::reg_32 +{ +public: + inline void strt_hi_set(uint32_t value) { this->set_field(value, TIMER_START_HI_STRT_HI_BIT, TIMER_START_HI_STRT_HI_WIDTH); } + inline uint32_t strt_hi_get() { return this->get_field(TIMER_START_HI_STRT_HI_BIT, TIMER_START_HI_STRT_HI_WIDTH); } +}; + +class vp_timer_reset_lo : public vp::reg_32 +{ +public: + inline void rst_lo_set(uint32_t value) { this->set_field(value, TIMER_RESET_LO_RST_LO_BIT, TIMER_RESET_LO_RST_LO_WIDTH); } + inline uint32_t rst_lo_get() { return this->get_field(TIMER_RESET_LO_RST_LO_BIT, TIMER_RESET_LO_RST_LO_WIDTH); } +}; + +class vp_timer_reset_hi : public vp::reg_32 +{ +public: + inline void rst_hi_set(uint32_t value) { this->set_field(value, TIMER_RESET_HI_RST_HI_BIT, TIMER_RESET_HI_RST_HI_WIDTH); } + inline uint32_t rst_hi_get() { return this->get_field(TIMER_RESET_HI_RST_HI_BIT, TIMER_RESET_HI_RST_HI_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int cfg_lo ; // Timer Low Configuration register. + unsigned int cfg_hi ; // Timer High Configuration register. + unsigned int cnt_lo ; // Timer Low counter value register. + unsigned int cnt_hi ; // Timer High counter value register. + unsigned int cmp_lo ; // Timer Low comparator value register. + unsigned int cmp_hi ; // Timer High comparator value register. + unsigned int start_lo ; // Start Timer Low counting register. + unsigned int start_hi ; // Start Timer High counting register. + unsigned int reset_lo ; // Reset Timer Low counter register. + unsigned int reset_hi ; // Reset Timer High counter register. +} __attribute__((packed)) timer_timer_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t timer_cfg_lo_get(uint32_t base) { return ARCHI_READ(base, TIMER_CFG_LO_OFFSET); } +static inline void timer_cfg_lo_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_CFG_LO_OFFSET, value); } + +static inline uint32_t timer_cfg_hi_get(uint32_t base) { return ARCHI_READ(base, TIMER_CFG_HI_OFFSET); } +static inline void timer_cfg_hi_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_CFG_HI_OFFSET, value); } + +static inline uint32_t timer_cnt_lo_get(uint32_t base) { return ARCHI_READ(base, TIMER_CNT_LO_OFFSET); } +static inline void timer_cnt_lo_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_CNT_LO_OFFSET, value); } + +static inline uint32_t timer_cnt_hi_get(uint32_t base) { return ARCHI_READ(base, TIMER_CNT_HI_OFFSET); } +static inline void timer_cnt_hi_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_CNT_HI_OFFSET, value); } + +static inline uint32_t timer_cmp_lo_get(uint32_t base) { return ARCHI_READ(base, TIMER_CMP_LO_OFFSET); } +static inline void timer_cmp_lo_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_CMP_LO_OFFSET, value); } + +static inline uint32_t timer_cmp_hi_get(uint32_t base) { return ARCHI_READ(base, TIMER_CMP_HI_OFFSET); } +static inline void timer_cmp_hi_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_CMP_HI_OFFSET, value); } + +static inline uint32_t timer_start_lo_get(uint32_t base) { return ARCHI_READ(base, TIMER_START_LO_OFFSET); } +static inline void timer_start_lo_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_START_LO_OFFSET, value); } + +static inline uint32_t timer_start_hi_get(uint32_t base) { return ARCHI_READ(base, TIMER_START_HI_OFFSET); } +static inline void timer_start_hi_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_START_HI_OFFSET, value); } + +static inline uint32_t timer_reset_lo_get(uint32_t base) { return ARCHI_READ(base, TIMER_RESET_LO_OFFSET); } +static inline void timer_reset_lo_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_RESET_LO_OFFSET, value); } + +static inline uint32_t timer_reset_hi_get(uint32_t base) { return ARCHI_READ(base, TIMER_RESET_HI_OFFSET); } +static inline void timer_reset_hi_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, TIMER_RESET_HI_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define TIMER_CFG_LO_ENABLE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define TIMER_CFG_LO_ENABLE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define TIMER_CFG_LO_ENABLE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define TIMER_CFG_LO_ENABLE(val) ((val) << 0) + +#define TIMER_CFG_LO_RESET_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define TIMER_CFG_LO_RESET_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define TIMER_CFG_LO_RESET_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define TIMER_CFG_LO_RESET(val) ((val) << 1) + +#define TIMER_CFG_LO_IRQEN_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define TIMER_CFG_LO_IRQEN_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define TIMER_CFG_LO_IRQEN_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define TIMER_CFG_LO_IRQEN(val) ((val) << 2) + +#define TIMER_CFG_LO_IEM_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define TIMER_CFG_LO_IEM_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define TIMER_CFG_LO_IEM_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define TIMER_CFG_LO_IEM(val) ((val) << 3) + +#define TIMER_CFG_LO_MODE_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define TIMER_CFG_LO_MODE_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define TIMER_CFG_LO_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define TIMER_CFG_LO_MODE(val) ((val) << 4) + +#define TIMER_CFG_LO_ONE_S_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define TIMER_CFG_LO_ONE_S_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define TIMER_CFG_LO_ONE_S_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define TIMER_CFG_LO_ONE_S(val) ((val) << 5) + +#define TIMER_CFG_LO_PEN_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define TIMER_CFG_LO_PEN_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define TIMER_CFG_LO_PEN_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define TIMER_CFG_LO_PEN(val) ((val) << 6) + +#define TIMER_CFG_LO_CCFG_GET(value) (ARCHI_BEXTRACTU((value),1,7)) +#define TIMER_CFG_LO_CCFG_GETS(value) (ARCHI_BEXTRACT((value),1,7)) +#define TIMER_CFG_LO_CCFG_SET(value,field) (ARCHI_BINSERT((value),(field),1,7)) +#define TIMER_CFG_LO_CCFG(val) ((val) << 7) + +#define TIMER_CFG_LO_PVAL_GET(value) (ARCHI_BEXTRACTU((value),8,8)) +#define TIMER_CFG_LO_PVAL_GETS(value) (ARCHI_BEXTRACT((value),8,8)) +#define TIMER_CFG_LO_PVAL_SET(value,field) (ARCHI_BINSERT((value),(field),8,8)) +#define TIMER_CFG_LO_PVAL(val) ((val) << 8) + +#define TIMER_CFG_LO_CASC_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define TIMER_CFG_LO_CASC_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define TIMER_CFG_LO_CASC_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define TIMER_CFG_LO_CASC(val) ((val) << 31) + +#define TIMER_CFG_HI_ENABLE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define TIMER_CFG_HI_ENABLE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define TIMER_CFG_HI_ENABLE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define TIMER_CFG_HI_ENABLE(val) ((val) << 0) + +#define TIMER_CFG_HI_RESET_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define TIMER_CFG_HI_RESET_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define TIMER_CFG_HI_RESET_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define TIMER_CFG_HI_RESET(val) ((val) << 1) + +#define TIMER_CFG_HI_IRQEN_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define TIMER_CFG_HI_IRQEN_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define TIMER_CFG_HI_IRQEN_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define TIMER_CFG_HI_IRQEN(val) ((val) << 2) + +#define TIMER_CFG_HI_IEM_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define TIMER_CFG_HI_IEM_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define TIMER_CFG_HI_IEM_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define TIMER_CFG_HI_IEM(val) ((val) << 3) + +#define TIMER_CFG_HI_MODE_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define TIMER_CFG_HI_MODE_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define TIMER_CFG_HI_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define TIMER_CFG_HI_MODE(val) ((val) << 4) + +#define TIMER_CFG_HI_ONE_S_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define TIMER_CFG_HI_ONE_S_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define TIMER_CFG_HI_ONE_S_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define TIMER_CFG_HI_ONE_S(val) ((val) << 5) + +#define TIMER_CFG_HI_PEN_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define TIMER_CFG_HI_PEN_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define TIMER_CFG_HI_PEN_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define TIMER_CFG_HI_PEN(val) ((val) << 6) + +#define TIMER_CFG_HI_CLKCFG_GET(value) (ARCHI_BEXTRACTU((value),1,7)) +#define TIMER_CFG_HI_CLKCFG_GETS(value) (ARCHI_BEXTRACT((value),1,7)) +#define TIMER_CFG_HI_CLKCFG_SET(value,field) (ARCHI_BINSERT((value),(field),1,7)) +#define TIMER_CFG_HI_CLKCFG(val) ((val) << 7) + +#define TIMER_CNT_LO_CNT_LO_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define TIMER_CNT_LO_CNT_LO_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define TIMER_CNT_LO_CNT_LO_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define TIMER_CNT_LO_CNT_LO(val) ((val) << 0) + +#define TIMER_CNT_HI_CNT_HI_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define TIMER_CNT_HI_CNT_HI_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define TIMER_CNT_HI_CNT_HI_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define TIMER_CNT_HI_CNT_HI(val) ((val) << 0) + +#define TIMER_CMP_LO_CMP_LO_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define TIMER_CMP_LO_CMP_LO_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define TIMER_CMP_LO_CMP_LO_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define TIMER_CMP_LO_CMP_LO(val) ((val) << 0) + +#define TIMER_CMP_HI_CMP_HI_GET(value) (ARCHI_BEXTRACTU((value),32,0)) +#define TIMER_CMP_HI_CMP_HI_GETS(value) (ARCHI_BEXTRACT((value),32,0)) +#define TIMER_CMP_HI_CMP_HI_SET(value,field) (ARCHI_BINSERT((value),(field),32,0)) +#define TIMER_CMP_HI_CMP_HI(val) ((val) << 0) + +#define TIMER_START_LO_STRT_LO_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define TIMER_START_LO_STRT_LO_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define TIMER_START_LO_STRT_LO_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define TIMER_START_LO_STRT_LO(val) ((val) << 0) + +#define TIMER_START_HI_STRT_HI_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define TIMER_START_HI_STRT_HI_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define TIMER_START_HI_STRT_HI_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define TIMER_START_HI_STRT_HI(val) ((val) << 0) + +#define TIMER_RESET_LO_RST_LO_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define TIMER_RESET_LO_RST_LO_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define TIMER_RESET_LO_RST_LO_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define TIMER_RESET_LO_RST_LO(val) ((val) << 0) + +#define TIMER_RESET_HI_RST_HI_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define TIMER_RESET_HI_RST_HI_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define TIMER_RESET_HI_RST_HI_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define TIMER_RESET_HI_RST_HI(val) ((val) << 0) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/cpi/udma_cpi_v1.h b/sw/pulp-sdk/archi/include/archi/udma/cpi/udma_cpi_v1.h new file mode 100644 index 0000000..be08c8a --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/cpi/udma_cpi_v1.h @@ -0,0 +1,614 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_CPI_UDMA_CPI_V1_H__ +#define __INCLUDE_ARCHI_UDMA_CPI_UDMA_CPI_V1_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// RX Camera uDMA transfer address of associated buffer register +#define UDMA_CPI_CAM_RX_SADDR_OFFSET 0x0 + +// RX Camera uDMA transfer size of buffer register +#define UDMA_CPI_CAM_RX_SIZE_OFFSET 0x4 + +// RX Camera uDMA transfer configuration register +#define UDMA_CPI_CAM_RX_CFG_OFFSET 0x8 + +// - +#define UDMA_CPI_CAM_RX_INITCFG_OFFSET 0xc + +// - +#define UDMA_CPI_CAM_TX_SADDR_OFFSET 0x10 + +// - +#define UDMA_CPI_CAM_TX_SIZE_OFFSET 0x14 + +// - +#define UDMA_CPI_CAM_TX_CFG_OFFSET 0x18 + +// - +#define UDMA_CPI_CAM_TX_INITCFG_OFFSET 0x1c + +// Global configuration register +#define UDMA_CPI_CAM_CFG_GLOB_OFFSET 0x20 + +// Lower Left corner configuration register +#define UDMA_CPI_CAM_CFG_LL_OFFSET 0x24 + +// Upper Right corner configuration register +#define UDMA_CPI_CAM_CFG_UR_OFFSET 0x28 + +// Horizontal Resolution configuration register +#define UDMA_CPI_CAM_CFG_SIZE_OFFSET 0x2c + +// RGB coefficients configuration register +#define UDMA_CPI_CAM_CFG_FILTER_OFFSET 0x30 + +// VSYNC Polarity register +#define UDMA_CPI_CAM_VSYNC_POLARITY_OFFSET 0x34 + + + +// +// REGISTERS FIELDS +// + +// Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address (access: R/W) +#define UDMA_CPI_CAM_RX_SADDR_RX_SADDR_BIT 0 +#define UDMA_CPI_CAM_RX_SADDR_RX_SADDR_WIDTH 16 +#define UDMA_CPI_CAM_RX_SADDR_RX_SADDR_MASK 0xffff + +// Buffer size in bytes. (128kBytes maximum) - Read: buffer size left - Write: set buffer size NOTE: Careful with size in byte. If you use uncompressed pixel data mapped on 16 bits, you have to declare buffer size in bytes even if buffer type is short. (access: R/W) +#define UDMA_CPI_CAM_RX_SIZE_RX_SIZE_BIT 0 +#define UDMA_CPI_CAM_RX_SIZE_RX_SIZE_WIDTH 17 +#define UDMA_CPI_CAM_RX_SIZE_RX_SIZE_MASK 0x1ffff + +// Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. (access: R/W) +#define UDMA_CPI_CAM_RX_CFG_CONTINOUS_BIT 0 +#define UDMA_CPI_CAM_RX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_CPI_CAM_RX_CFG_CONTINOUS_MASK 0x1 + +// Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 (access: R/W) +#define UDMA_CPI_CAM_RX_CFG_DATASIZE_BIT 1 +#define UDMA_CPI_CAM_RX_CFG_DATASIZE_WIDTH 2 +#define UDMA_CPI_CAM_RX_CFG_DATASIZE_MASK 0x6 + +// Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_CPI_CAM_RX_CFG_EN_BIT 4 +#define UDMA_CPI_CAM_RX_CFG_EN_WIDTH 1 +#define UDMA_CPI_CAM_RX_CFG_EN_MASK 0x10 + +// Transfer pending in queue status flag: -1'b0: free -1'b1: pending (access: R) +#define UDMA_CPI_CAM_RX_CFG_PENDING_BIT 5 +#define UDMA_CPI_CAM_RX_CFG_PENDING_WIDTH 1 +#define UDMA_CPI_CAM_RX_CFG_PENDING_MASK 0x20 + +// Channel clear and stop transfer: -1'b0: disable -1'b1: enable (access: W) +#define UDMA_CPI_CAM_RX_CFG_CLR_BIT 6 +#define UDMA_CPI_CAM_RX_CFG_CLR_WIDTH 1 +#define UDMA_CPI_CAM_RX_CFG_CLR_MASK 0x40 + +// Frame dropping: - 1'b0: disable - 1'b1: enable (access: R/W) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_BIT 0 +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_WIDTH 1 +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_MASK 0x1 + +// Sets how many frames should be dropped after each received. (access: R/W) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_BIT 1 +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_WIDTH 6 +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_MASK 0x7e + +// Input frame slicing: - 1'b0: disable - 1'b1: enable (access: R/W) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_BIT 7 +#define UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_WIDTH 1 +#define UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_MASK 0x80 + +// Input frame format: - 3'b000: RGB565 - 3'b001: RGB555 - 3'b010: RGB444 - 3'b100: BYPASS_LITEND - 3’b101: BYPASS_BIGEND (access: R/W) +#define UDMA_CPI_CAM_CFG_GLOB_FORMAT_BIT 8 +#define UDMA_CPI_CAM_CFG_GLOB_FORMAT_WIDTH 3 +#define UDMA_CPI_CAM_CFG_GLOB_FORMAT_MASK 0x700 + +// Right shift of final pixel value (DivFactor) NOTE: not used if FORMAT == BYPASS (access: R/W) +#define UDMA_CPI_CAM_CFG_GLOB_SHIFT_BIT 11 +#define UDMA_CPI_CAM_CFG_GLOB_SHIFT_WIDTH 4 +#define UDMA_CPI_CAM_CFG_GLOB_SHIFT_MASK 0x7800 + +// Enable data rx from camera interface. The enable/disable happens only at the start of a frame. - 1'b0: disable - 1'b1: enable (access: R/W) +#define UDMA_CPI_CAM_CFG_GLOB_EN_BIT 31 +#define UDMA_CPI_CAM_CFG_GLOB_EN_WIDTH 1 +#define UDMA_CPI_CAM_CFG_GLOB_EN_MASK 0x80000000 + +// X coordinate of lower left corner of slice (access: R/W) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_BIT 0 +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_WIDTH 16 +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_MASK 0xffff + +// Y coordinate of lower left corner of slice (access: R/W) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_BIT 16 +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_WIDTH 16 +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_MASK 0xffff0000 + +// X coordinate of upper right corner of slice (access: R/W) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_BIT 0 +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_WIDTH 16 +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_MASK 0xffff + +// Y coordinate of upper right corner of slice (access: R/W) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_BIT 16 +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_WIDTH 16 +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_MASK 0xffff0000 + +// Horizontal Resolution. It is used for slice mode. Value set into the bitfield must be equal to (rowlen-1). (access: R/W) +#define UDMA_CPI_CAM_CFG_SIZE_ROWLEN_BIT 16 +#define UDMA_CPI_CAM_CFG_SIZE_ROWLEN_WIDTH 16 +#define UDMA_CPI_CAM_CFG_SIZE_ROWLEN_MASK 0xffff0000 + +// Coefficient that multiplies the B component NOTE: not used if FORMAT == BYPASS (access: R/W) +#define UDMA_CPI_CAM_CFG_FILTER_B_COEFF_BIT 0 +#define UDMA_CPI_CAM_CFG_FILTER_B_COEFF_WIDTH 8 +#define UDMA_CPI_CAM_CFG_FILTER_B_COEFF_MASK 0xff + +// Coefficient that multiplies the G component NOTE: not used if FORMAT == BYPASS (access: R/W) +#define UDMA_CPI_CAM_CFG_FILTER_G_COEFF_BIT 8 +#define UDMA_CPI_CAM_CFG_FILTER_G_COEFF_WIDTH 8 +#define UDMA_CPI_CAM_CFG_FILTER_G_COEFF_MASK 0xff00 + +// Coefficient that multiplies the R component NOTE: not used if FORMAT == BYPASS (access: R/W) +#define UDMA_CPI_CAM_CFG_FILTER_R_COEFF_BIT 16 +#define UDMA_CPI_CAM_CFG_FILTER_R_COEFF_WIDTH 8 +#define UDMA_CPI_CAM_CFG_FILTER_R_COEFF_MASK 0xff0000 + +// Set vsync polarity of CPI. - 1'b0: Active 0 - 1'b1: Active 1 (access: R/W) +#define UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_BIT 0 +#define UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_WIDTH 1 +#define UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_MASK 0x1 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rx_saddr :16; // Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_rx_saddr_t; + +typedef union { + struct { + unsigned int rx_size :17; // Buffer size in bytes. (128kBytes maximum) - Read: buffer size left - Write: set buffer size NOTE: Careful with size in byte. If you use uncompressed pixel data mapped on 16 bits, you have to declare buffer size in bytes even if buffer type is short. + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_rx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. + unsigned int datasize :2 ; // Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 + unsigned int padding0:1 ; + unsigned int en :1 ; // Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. + unsigned int pending :1 ; // Transfer pending in queue status flag: -1'b0: free -1'b1: pending + unsigned int clr :1 ; // Channel clear and stop transfer: -1'b0: disable -1'b1: enable + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_rx_cfg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_rx_initcfg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_tx_saddr_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_tx_size_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_tx_cfg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_tx_initcfg_t; + +typedef union { + struct { + unsigned int framedrop_en :1 ; // Frame dropping: - 1'b0: disable - 1'b1: enable + unsigned int framedrop_val :6 ; // Sets how many frames should be dropped after each received. + unsigned int frameslice_en :1 ; // Input frame slicing: - 1'b0: disable - 1'b1: enable + unsigned int format :3 ; // Input frame format: - 3'b000: RGB565 - 3'b001: RGB555 - 3'b010: RGB444 - 3'b100: BYPASS_LITEND - 3’b101: BYPASS_BIGEND + unsigned int shift :4 ; // Right shift of final pixel value (DivFactor) NOTE: not used if FORMAT == BYPASS + unsigned int padding0:16; + unsigned int en :1 ; // Enable data rx from camera interface. The enable/disable happens only at the start of a frame. - 1'b0: disable - 1'b1: enable + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_cfg_glob_t; + +typedef union { + struct { + unsigned int frameslice_llx :16; // X coordinate of lower left corner of slice + unsigned int frameslice_lly :16; // Y coordinate of lower left corner of slice + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_cfg_ll_t; + +typedef union { + struct { + unsigned int frameslice_urx :16; // X coordinate of upper right corner of slice + unsigned int frameslice_ury :16; // Y coordinate of upper right corner of slice + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_cfg_ur_t; + +typedef union { + struct { + unsigned int padding0:16; + unsigned int rowlen :16; // Horizontal Resolution. It is used for slice mode. Value set into the bitfield must be equal to (rowlen-1). + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_cfg_size_t; + +typedef union { + struct { + unsigned int b_coeff :8 ; // Coefficient that multiplies the B component NOTE: not used if FORMAT == BYPASS + unsigned int g_coeff :8 ; // Coefficient that multiplies the G component NOTE: not used if FORMAT == BYPASS + unsigned int r_coeff :8 ; // Coefficient that multiplies the R component NOTE: not used if FORMAT == BYPASS + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_cfg_filter_t; + +typedef union { + struct { + unsigned int vsync_polarity :1 ; // Set vsync polarity of CPI. - 1'b0: Active 0 - 1'b1: Active 1 + }; + unsigned int raw; +} __attribute__((packed)) udma_cpi_cam_vsync_polarity_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_udma_cpi_cam_rx_saddr : public vp::reg_32 +{ +public: + inline void rx_saddr_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_RX_SADDR_RX_SADDR_BIT, UDMA_CPI_CAM_RX_SADDR_RX_SADDR_WIDTH); } + inline uint32_t rx_saddr_get() { return this->get_field(UDMA_CPI_CAM_RX_SADDR_RX_SADDR_BIT, UDMA_CPI_CAM_RX_SADDR_RX_SADDR_WIDTH); } +}; + +class vp_udma_cpi_cam_rx_size : public vp::reg_32 +{ +public: + inline void rx_size_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_RX_SIZE_RX_SIZE_BIT, UDMA_CPI_CAM_RX_SIZE_RX_SIZE_WIDTH); } + inline uint32_t rx_size_get() { return this->get_field(UDMA_CPI_CAM_RX_SIZE_RX_SIZE_BIT, UDMA_CPI_CAM_RX_SIZE_RX_SIZE_WIDTH); } +}; + +class vp_udma_cpi_cam_rx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_RX_CFG_CONTINOUS_BIT, UDMA_CPI_CAM_RX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_CPI_CAM_RX_CFG_CONTINOUS_BIT, UDMA_CPI_CAM_RX_CFG_CONTINOUS_WIDTH); } + inline void datasize_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_RX_CFG_DATASIZE_BIT, UDMA_CPI_CAM_RX_CFG_DATASIZE_WIDTH); } + inline uint32_t datasize_get() { return this->get_field(UDMA_CPI_CAM_RX_CFG_DATASIZE_BIT, UDMA_CPI_CAM_RX_CFG_DATASIZE_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_RX_CFG_EN_BIT, UDMA_CPI_CAM_RX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_CPI_CAM_RX_CFG_EN_BIT, UDMA_CPI_CAM_RX_CFG_EN_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_RX_CFG_PENDING_BIT, UDMA_CPI_CAM_RX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_CPI_CAM_RX_CFG_PENDING_BIT, UDMA_CPI_CAM_RX_CFG_PENDING_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_RX_CFG_CLR_BIT, UDMA_CPI_CAM_RX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_CPI_CAM_RX_CFG_CLR_BIT, UDMA_CPI_CAM_RX_CFG_CLR_WIDTH); } +}; + +class vp_udma_cpi_cam_cfg_glob : public vp::reg_32 +{ +public: + inline void framedrop_en_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_BIT, UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_WIDTH); } + inline uint32_t framedrop_en_get() { return this->get_field(UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_BIT, UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_WIDTH); } + inline void framedrop_val_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_BIT, UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_WIDTH); } + inline uint32_t framedrop_val_get() { return this->get_field(UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_BIT, UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_WIDTH); } + inline void frameslice_en_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_BIT, UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_WIDTH); } + inline uint32_t frameslice_en_get() { return this->get_field(UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_BIT, UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_WIDTH); } + inline void format_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_GLOB_FORMAT_BIT, UDMA_CPI_CAM_CFG_GLOB_FORMAT_WIDTH); } + inline uint32_t format_get() { return this->get_field(UDMA_CPI_CAM_CFG_GLOB_FORMAT_BIT, UDMA_CPI_CAM_CFG_GLOB_FORMAT_WIDTH); } + inline void shift_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_GLOB_SHIFT_BIT, UDMA_CPI_CAM_CFG_GLOB_SHIFT_WIDTH); } + inline uint32_t shift_get() { return this->get_field(UDMA_CPI_CAM_CFG_GLOB_SHIFT_BIT, UDMA_CPI_CAM_CFG_GLOB_SHIFT_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_GLOB_EN_BIT, UDMA_CPI_CAM_CFG_GLOB_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_CPI_CAM_CFG_GLOB_EN_BIT, UDMA_CPI_CAM_CFG_GLOB_EN_WIDTH); } +}; + +class vp_udma_cpi_cam_cfg_ll : public vp::reg_32 +{ +public: + inline void frameslice_llx_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_BIT, UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_WIDTH); } + inline uint32_t frameslice_llx_get() { return this->get_field(UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_BIT, UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_WIDTH); } + inline void frameslice_lly_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_BIT, UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_WIDTH); } + inline uint32_t frameslice_lly_get() { return this->get_field(UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_BIT, UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_WIDTH); } +}; + +class vp_udma_cpi_cam_cfg_ur : public vp::reg_32 +{ +public: + inline void frameslice_urx_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_BIT, UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_WIDTH); } + inline uint32_t frameslice_urx_get() { return this->get_field(UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_BIT, UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_WIDTH); } + inline void frameslice_ury_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_BIT, UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_WIDTH); } + inline uint32_t frameslice_ury_get() { return this->get_field(UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_BIT, UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_WIDTH); } +}; + +class vp_udma_cpi_cam_cfg_size : public vp::reg_32 +{ +public: + inline void rowlen_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_SIZE_ROWLEN_BIT, UDMA_CPI_CAM_CFG_SIZE_ROWLEN_WIDTH); } + inline uint32_t rowlen_get() { return this->get_field(UDMA_CPI_CAM_CFG_SIZE_ROWLEN_BIT, UDMA_CPI_CAM_CFG_SIZE_ROWLEN_WIDTH); } +}; + +class vp_udma_cpi_cam_cfg_filter : public vp::reg_32 +{ +public: + inline void b_coeff_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_FILTER_B_COEFF_BIT, UDMA_CPI_CAM_CFG_FILTER_B_COEFF_WIDTH); } + inline uint32_t b_coeff_get() { return this->get_field(UDMA_CPI_CAM_CFG_FILTER_B_COEFF_BIT, UDMA_CPI_CAM_CFG_FILTER_B_COEFF_WIDTH); } + inline void g_coeff_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_FILTER_G_COEFF_BIT, UDMA_CPI_CAM_CFG_FILTER_G_COEFF_WIDTH); } + inline uint32_t g_coeff_get() { return this->get_field(UDMA_CPI_CAM_CFG_FILTER_G_COEFF_BIT, UDMA_CPI_CAM_CFG_FILTER_G_COEFF_WIDTH); } + inline void r_coeff_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_CFG_FILTER_R_COEFF_BIT, UDMA_CPI_CAM_CFG_FILTER_R_COEFF_WIDTH); } + inline uint32_t r_coeff_get() { return this->get_field(UDMA_CPI_CAM_CFG_FILTER_R_COEFF_BIT, UDMA_CPI_CAM_CFG_FILTER_R_COEFF_WIDTH); } +}; + +class vp_udma_cpi_cam_vsync_polarity : public vp::reg_32 +{ +public: + inline void vsync_polarity_set(uint32_t value) { this->set_field(value, UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_BIT, UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_WIDTH); } + inline uint32_t vsync_polarity_get() { return this->get_field(UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_BIT, UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int cam_rx_saddr ; // RX Camera uDMA transfer address of associated buffer register + unsigned int cam_rx_size ; // RX Camera uDMA transfer size of buffer register + unsigned int cam_rx_cfg ; // RX Camera uDMA transfer configuration register + unsigned int cam_rx_initcfg ; // - + unsigned int cam_tx_saddr ; // - + unsigned int cam_tx_size ; // - + unsigned int cam_tx_cfg ; // - + unsigned int cam_tx_initcfg ; // - + unsigned int cam_cfg_glob ; // Global configuration register + unsigned int cam_cfg_ll ; // Lower Left corner configuration register + unsigned int cam_cfg_ur ; // Upper Right corner configuration register + unsigned int cam_cfg_size ; // Horizontal Resolution configuration register + unsigned int cam_cfg_filter ; // RGB coefficients configuration register + unsigned int cam_vsync_polarity; // VSYNC Polarity register +} __attribute__((packed)) udma_cpi_udma_cpi_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t udma_cpi_cam_rx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_RX_SADDR_OFFSET); } +static inline void udma_cpi_cam_rx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_RX_SADDR_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_rx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_RX_SIZE_OFFSET); } +static inline void udma_cpi_cam_rx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_RX_SIZE_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_rx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_RX_CFG_OFFSET); } +static inline void udma_cpi_cam_rx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_RX_CFG_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_rx_initcfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_RX_INITCFG_OFFSET); } +static inline void udma_cpi_cam_rx_initcfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_RX_INITCFG_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_tx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_TX_SADDR_OFFSET); } +static inline void udma_cpi_cam_tx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_TX_SADDR_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_tx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_TX_SIZE_OFFSET); } +static inline void udma_cpi_cam_tx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_TX_SIZE_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_tx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_TX_CFG_OFFSET); } +static inline void udma_cpi_cam_tx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_TX_CFG_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_tx_initcfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_TX_INITCFG_OFFSET); } +static inline void udma_cpi_cam_tx_initcfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_TX_INITCFG_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_cfg_glob_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_CFG_GLOB_OFFSET); } +static inline void udma_cpi_cam_cfg_glob_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_CFG_GLOB_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_cfg_ll_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_CFG_LL_OFFSET); } +static inline void udma_cpi_cam_cfg_ll_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_CFG_LL_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_cfg_ur_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_CFG_UR_OFFSET); } +static inline void udma_cpi_cam_cfg_ur_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_CFG_UR_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_cfg_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_CFG_SIZE_OFFSET); } +static inline void udma_cpi_cam_cfg_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_CFG_SIZE_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_cfg_filter_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_CFG_FILTER_OFFSET); } +static inline void udma_cpi_cam_cfg_filter_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_CFG_FILTER_OFFSET, value); } + +static inline uint32_t udma_cpi_cam_vsync_polarity_get(uint32_t base) { return ARCHI_READ(base, UDMA_CPI_CAM_VSYNC_POLARITY_OFFSET); } +static inline void udma_cpi_cam_vsync_polarity_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_CPI_CAM_VSYNC_POLARITY_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define UDMA_CPI_CAM_RX_SADDR_RX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_CPI_CAM_RX_SADDR_RX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_CPI_CAM_RX_SADDR_RX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_CPI_CAM_RX_SADDR_RX_SADDR(val) ((val) << 0) + +#define UDMA_CPI_CAM_RX_SIZE_RX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_CPI_CAM_RX_SIZE_RX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_CPI_CAM_RX_SIZE_RX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_CPI_CAM_RX_SIZE_RX_SIZE(val) ((val) << 0) + +#define UDMA_CPI_CAM_RX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_CPI_CAM_RX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_CPI_CAM_RX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_CPI_CAM_RX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_CPI_CAM_RX_CFG_DATASIZE_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define UDMA_CPI_CAM_RX_CFG_DATASIZE_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define UDMA_CPI_CAM_RX_CFG_DATASIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define UDMA_CPI_CAM_RX_CFG_DATASIZE(val) ((val) << 1) + +#define UDMA_CPI_CAM_RX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_CPI_CAM_RX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_CPI_CAM_RX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_CPI_CAM_RX_CFG_EN(val) ((val) << 4) + +#define UDMA_CPI_CAM_RX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_CPI_CAM_RX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_CPI_CAM_RX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_CPI_CAM_RX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_CPI_CAM_RX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define UDMA_CPI_CAM_RX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define UDMA_CPI_CAM_RX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define UDMA_CPI_CAM_RX_CFG_CLR(val) ((val) << 6) + +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_EN(val) ((val) << 0) + +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_GET(value) (ARCHI_BEXTRACTU((value),6,1)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_GETS(value) (ARCHI_BEXTRACT((value),6,1)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL_SET(value,field) (ARCHI_BINSERT((value),(field),6,1)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMEDROP_VAL(val) ((val) << 1) + +#define UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,7)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,7)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,7)) +#define UDMA_CPI_CAM_CFG_GLOB_FRAMESLICE_EN(val) ((val) << 7) + +#define UDMA_CPI_CAM_CFG_GLOB_FORMAT_GET(value) (ARCHI_BEXTRACTU((value),3,8)) +#define UDMA_CPI_CAM_CFG_GLOB_FORMAT_GETS(value) (ARCHI_BEXTRACT((value),3,8)) +#define UDMA_CPI_CAM_CFG_GLOB_FORMAT_SET(value,field) (ARCHI_BINSERT((value),(field),3,8)) +#define UDMA_CPI_CAM_CFG_GLOB_FORMAT(val) ((val) << 8) + +#define UDMA_CPI_CAM_CFG_GLOB_SHIFT_GET(value) (ARCHI_BEXTRACTU((value),4,11)) +#define UDMA_CPI_CAM_CFG_GLOB_SHIFT_GETS(value) (ARCHI_BEXTRACT((value),4,11)) +#define UDMA_CPI_CAM_CFG_GLOB_SHIFT_SET(value,field) (ARCHI_BINSERT((value),(field),4,11)) +#define UDMA_CPI_CAM_CFG_GLOB_SHIFT(val) ((val) << 11) + +#define UDMA_CPI_CAM_CFG_GLOB_EN_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_CPI_CAM_CFG_GLOB_EN_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_CPI_CAM_CFG_GLOB_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_CPI_CAM_CFG_GLOB_EN(val) ((val) << 31) + +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLX(val) ((val) << 0) + +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define UDMA_CPI_CAM_CFG_LL_FRAMESLICE_LLY(val) ((val) << 16) + +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URX(val) ((val) << 0) + +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define UDMA_CPI_CAM_CFG_UR_FRAMESLICE_URY(val) ((val) << 16) + +#define UDMA_CPI_CAM_CFG_SIZE_ROWLEN_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define UDMA_CPI_CAM_CFG_SIZE_ROWLEN_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define UDMA_CPI_CAM_CFG_SIZE_ROWLEN_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define UDMA_CPI_CAM_CFG_SIZE_ROWLEN(val) ((val) << 16) + +#define UDMA_CPI_CAM_CFG_FILTER_B_COEFF_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define UDMA_CPI_CAM_CFG_FILTER_B_COEFF_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define UDMA_CPI_CAM_CFG_FILTER_B_COEFF_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define UDMA_CPI_CAM_CFG_FILTER_B_COEFF(val) ((val) << 0) + +#define UDMA_CPI_CAM_CFG_FILTER_G_COEFF_GET(value) (ARCHI_BEXTRACTU((value),8,8)) +#define UDMA_CPI_CAM_CFG_FILTER_G_COEFF_GETS(value) (ARCHI_BEXTRACT((value),8,8)) +#define UDMA_CPI_CAM_CFG_FILTER_G_COEFF_SET(value,field) (ARCHI_BINSERT((value),(field),8,8)) +#define UDMA_CPI_CAM_CFG_FILTER_G_COEFF(val) ((val) << 8) + +#define UDMA_CPI_CAM_CFG_FILTER_R_COEFF_GET(value) (ARCHI_BEXTRACTU((value),8,16)) +#define UDMA_CPI_CAM_CFG_FILTER_R_COEFF_GETS(value) (ARCHI_BEXTRACT((value),8,16)) +#define UDMA_CPI_CAM_CFG_FILTER_R_COEFF_SET(value,field) (ARCHI_BINSERT((value),(field),8,16)) +#define UDMA_CPI_CAM_CFG_FILTER_R_COEFF(val) ((val) << 16) + +#define UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_CPI_CAM_VSYNC_POLARITY_VSYNC_POLARITY(val) ((val) << 0) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/cpi/udma_cpi_v1_old.h b/sw/pulp-sdk/archi/include/archi/udma/cpi/udma_cpi_v1_old.h new file mode 100644 index 0000000..b2817ec --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/cpi/udma_cpi_v1_old.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_CPI_V1_H__ +#define __ARCHI_UDMA_UDMA_CPI_V1_H__ + +// CAM custom registers offset definition +#define CAM_GLOB_OFFSET (0x00) +#define CAM_LL_OFFSET (0x04) +#define CAM_UR_OFFSET (0x08) +#define CAM_SIZE_OFFSET (0x0C) +#define CAM_FILTER_OFFSET (0x10) + +// CAM custom registers bitfields offset, mask, value definition +#define CAM_CFG_GLOB_FRAMEDROP_EN_OFFSET 0 +#define CAM_CFG_GLOB_FRAMEDROP_EN_WIDTH 1 +#define CAM_CFG_GLOB_FRAMEDROP_EN_MASK (0x1 << CAM_CFG_GLOB_FRAMEDROP_EN_OFFSET) +#define CAM_CFG_GLOB_FRAMEDROP_EN_ENA (1 << CAM_CFG_GLOB_FRAMEDROP_EN_OFFSET) +#define CAM_CFG_GLOB_FRAMEDROP_EN_DIS (0 << CAM_CFG_GLOB_FRAMEDROP_EN_OFFSET) + +#define CAM_CFG_GLOB_FRAMEDROP_VAL_OFFSET 1 +#define CAM_CFG_GLOB_FRAMEDROP_VAL_WIDTH 6 +#define CAM_CFG_GLOB_FRAMEDROP_VAL_MASK (0x3f << CAM_CFG_GLOB_FRAMEDROP_VAL_OFFSET) +#define CAM_CFG_GLOB_FRAMEDROP_VAL(val) (val << CAM_CFG_GLOB_FRAMEDROP_VAL_OFFSET) + +#define CAM_CFG_GLOB_FRAMESLICE_EN_OFFSET 7 +#define CAM_CFG_GLOB_FRAMESLICE_EN_WIDTH 1 +#define CAM_CFG_GLOB_FRAMESLICE_EN_MASK (0x1 << CAM_CFG_GLOB_FRAMESLICE_EN_OFFSET) +#define CAM_CFG_GLOB_FRAMESLICE_EN_ENA (1 << CAM_CFG_GLOB_FRAMESLICE_EN_OFFSET) +#define CAM_CFG_GLOB_FRAMESLICE_EN_DIS (0 << CAM_CFG_GLOB_FRAMESLICE_EN_OFFSET) + +#define CAM_CFG_GLOB_FORMAT_OFFSET 8 +#define CAM_CFG_GLOB_FORMAT_WIDTH 2 +#define CAM_CFG_GLOB_FORMAT_MASK (0x7 << CAM_CFG_GLOB_FORMAT_OFFSET) +#define CAM_CFG_GLOB_FORMAT_RGB565 (0 << CAM_CFG_GLOB_FORMAT_OFFSET) +#define CAM_CFG_GLOB_FORMAT_RGB555 (1 << CAM_CFG_GLOB_FORMAT_OFFSET) +#define CAM_CFG_GLOB_FORMAT_RGB444 (2 << CAM_CFG_GLOB_FORMAT_OFFSET) +#define CAM_CFG_GLOB_FORMAT_BYPASS_LITEND (4 << CAM_CFG_GLOB_FORMAT_OFFSET) +#define CAM_CFG_GLOB_FORMAT_BYPASS_BIGEND (5 << CAM_CFG_GLOB_FORMAT_OFFSET) + +#define ARCHI_CAM_CFG_GLOB_FORMAT_RGB565 0 +#define ARCHI_CAM_CFG_GLOB_FORMAT_RGB555 1 +#define ARCHI_CAM_CFG_GLOB_FORMAT_RGB444 2 +#define ARCHI_CAM_CFG_GLOB_FORMAT_BYPASS_LITEND 4 +#define ARCHI_CAM_CFG_GLOB_FORMAT_BYPASS_BIGEND 5 + +#define CAM_CFG_GLOB_SHIFT_OFFSET 11 +#define CAM_CFG_GLOB_SHIFT_WIDTH 4 +#define CAM_CFG_GLOB_SHIFT_MASK (0xf << CAM_CFG_GLOB_SHIFT_OFFSET) +#define CAM_CFG_GLOB_SHIFT(val) (val << CAM_CFG_GLOB_SHIFT_OFFSET) + +#define CAM_CFG_GLOB_EN_OFFSET 31 +#define CAM_CFG_GLOB_EN_WIDTH 1 +#define CAM_CFG_GLOB_EN_MASK (0x1 << CAM_CFG_GLOB_EN_OFFSET) +#define CAM_CFG_GLOB_EN_ENA (1 << CAM_CFG_GLOB_EN_OFFSET) +#define CAM_CFG_GLOB_EN_DIS (0 << CAM_CFG_GLOB_EN_OFFSET) + +#define CAM_CFG_LL_FRAMESLICE_LLX_OFFSET 0 +#define CAM_CFG_LL_FRAMESLICE_LLX_WIDTH 16 +#define CAM_CFG_LL_FRAMESLICE_LLX_MASK (0xffff << CAM_CFG_LL_FRAMESLICE_LLX_OFFSET) +#define CAM_CFG_LL_FRAMESLICE_LLX(val) (val << CAM_CFG_LL_FRAMESLICE_LLX_OFFSET) + +#define CAM_CFG_LL_FRAMESLICE_LLY_OFFSET 16 +#define CAM_CFG_LL_FRAMESLICE_LLY_WIDTH 16 +#define CAM_CFG_LL_FRAMESLICE_LLY_MASK (0xffff << CAM_CFG_LL_FRAMESLICE_LLY_OFFSET) +#define CAM_CFG_LL_FRAMESLICE_LLY(val) (val << CAM_CFG_LL_FRAMESLICE_LLY_OFFSET) + +#define CAM_CFG_UR_FRAMESLICE_URX_OFFSET 0 +#define CAM_CFG_UR_FRAMESLICE_URX_WIDTH 16 +#define CAM_CFG_UR_FRAMESLICE_URX_MASK (0xffff << CAM_CFG_UR_FRAMESLICE_URX_OFFSET) +#define CAM_CFG_UR_FRAMESLICE_URX(val) (val << CAM_CFG_UR_FRAMESLICE_URX_OFFSET) + +#define CAM_CFG_UR_FRAMESLICE_URY_OFFSET 16 +#define CAM_CFG_UR_FRAMESLICE_URY_WIDTH 16 +#define CAM_CFG_UR_FRAMESLICE_URY_MASK (0xffff << CAM_CFG_UR_FRAMESLICE_URY_OFFSET) +#define CAM_CFG_UR_FRAMESLICE_URY(val) (val << CAM_CFG_UR_FRAMESLICE_URY_OFFSET) + +#define CAM_CFG_SIZE_ROWLEN_OFFSET 16 +#define CAM_CFG_SIZE_ROWLEN_WIDTH 16 +#define CAM_CFG_SIZE_ROWLEN_MASK (0xffff << CAM_CFG_SIZE_ROWLEN_OFFSET) +#define CAM_CFG_SIZE_ROWLEN(val) ((val - 1) << CAM_CFG_SIZE_ROWLEN_OFFSET) + +#define CAM_CFG_FILTER_B_COEFF_OFFSET 0 +#define CAM_CFG_FILTER_B_COEFF_WIDTH 8 +#define CAM_CFG_FILTER_B_COEFF_MASK (0xff << CAM_CFG_FILTER_B_COEFF_OFFSET) +#define CAM_CFG_FILTER_B_COEFF(val) (val << CAM_CFG_FILTER_B_COEFF_OFFSET) + +#define CAM_CFG_FILTER_G_COEFF_OFFSET 8 +#define CAM_CFG_FILTER_G_COEFF_WIDTH 8 +#define CAM_CFG_FILTER_G_COEFF_MASK (0xff << CAM_CFG_FILTER_G_COEFF_OFFSET) +#define CAM_CFG_FILTER_G_COEFF(val) (val << CAM_CFG_FILTER_G_COEFF_OFFSET) + +#define CAM_CFG_FILTER_R_COEFF_OFFSET 16 +#define CAM_CFG_FILTER_R_COEFF_WIDTH 8 +#define CAM_CFG_FILTER_R_COEFF_MASK (0xff << CAM_CFG_FILTER_R_COEFF_OFFSET) +#define CAM_CFG_FILTER_R_COEFF(val) (val << CAM_CFG_FILTER_R_COEFF_OFFSET) + +// TODO Add enum definitions of CAM register bitfields + +/////////////////////////////////////////////////// +// TODO Obsolete : to be removed cause deprecated +#define CAM_CFG_GLOB_FRAMEDROP_EN_BIT 0 +#define CAM_CFG_GLOB_FRAMEDROP_VAL_BIT 1 +#define CAM_CFG_GLOB_FRAMEDROP_VAL_SIZE 6 +#define CAM_CFG_GLOB_FRAMESLICE_EN_BIT 7 +#define CAM_CFG_GLOB_FORMAT_BIT 8 +#define CAM_CFG_GLOB_FORMAT_SIZE 3 +#define CAM_CFG_GLOB_SHIFT_BIT 11 +#define CAM_CFG_GLOB_SHIFT_SIZE 4 +#define CAM_CFG_GLOB_EN_BIT 31 + +//+ #define CAM_CFG_GLOB_FORMAT_RGB565 0 +//+ #define CAM_CFG_GLOB_FORMAT_RGB555 1 +//+ #define CAM_CFG_GLOB_FORMAT_RGB444 2 +//+ #define CAM_CFG_GLOB_FORMAT_BYPASS 3 + +#define CAM_CFG_LL_FRAMESLICE_LLX_BIT 0 +#define CAM_CFG_LL_FRAMESLICE_LLX_SIZE 16 +#define CAM_CFG_LL_FRAMESLICE_LLY_BIT 16 +#define CAM_CFG_LL_FRAMESLICE_LLY_SIZE 16 + +#define CAM_CFG_UR_FRAMESLICE_URX_BIT 0 +#define CAM_CFG_UR_FRAMESLICE_URX_SIZE 16 +#define CAM_CFG_UR_FRAMESLICE_URY_BIT 16 +#define CAM_CFG_UR_FRAMESLICE_URY_SIZE 16 + +#define CAM_CFG_SIZE_ROWLEN_BIT 16 +#define CAM_CFG_SIZE_ROWLEN_SIZE 16 + +#define CAM_CFG_FILTER_B_COEFF_BIT 0 +#define CAM_CFG_FILTER_B_COEFF_SIZE 8 +#define CAM_CFG_FILTER_G_COEFF_BIT 8 +#define CAM_CFG_FILTER_G_COEFF_SIZE 8 +#define CAM_CFG_FILTER_R_COEFF_BIT 16 +#define CAM_CFG_FILTER_R_COEFF_SIZE 8 +/////////////////////////////////////////////////// + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/udma/csi2/udma_csi2_v1.h b/sw/pulp-sdk/archi/include/archi/udma/csi2/udma_csi2_v1.h new file mode 100644 index 0000000..e135f80 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/csi2/udma_csi2_v1.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_CSI2_V1_H__ +#define __ARCHI_UDMA_UDMA_CSI2_V1_H__ + +// CSI2 custom registers offset definition + +#define CSI2_CLK_CFG_OFFSET (0x00) + +// CSI2 custom registers bitfields offset, mask, value definition +#define CSI2_CLK_CFG_CCI_BIT 0 +#define CSI2_CLK_CFG_CCI_BITS 8 +#define CSI2_CLK_CFG_CCI_MASK ARCHI_REG_MASK(CSI2_CLK_CFG_CCI_BIT, CSI2_CLK_CFG_CCI_BITS) +#define CSI2_CLK_CFG_CCI(val) (val << CSI2_CLK_CFG_CCI_BIT) + +#define CSI2_CLK_CFG_PIXEL_BIT 8 +#define CSI2_CLK_CFG_PIXEL_BITS 8 +#define CSI2_CLK_CFG_PIXEL_MASK ARCHI_REG_MASK(CSI2_CLK_CFG_PIXEL_BIT, CSI2_CLK_CFG_PIXEL_BITS) +#define CSI2_CLK_CFG_PIXEL(val) (val << CSI2_CLK_CFG_PIXEL_BIT) + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/udma/hyper/udma_hyper_v1.h b/sw/pulp-sdk/archi/include/archi/udma/hyper/udma_hyper_v1.h new file mode 100644 index 0000000..a604937 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/hyper/udma_hyper_v1.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_HYPER_H__ +#define __ARCHI_HYPER_H__ + +#define REG_ACCESS 0x1 +#define MEM_ACCESS 0x0 + +// Memory base address +#define REG_MBR0 0 +// HYPER RAM 8 Mbytes / 2 = 4M address, here is 16M +#define REG_MBR1 0x01000000 + +#define REG_MBR_WIDTH 24 + +#define HYPER_EXT_ADDR_CHANNEL_OFFSET 0x00 +#define HYPER_EXT_CFG_CHANNEL_OFFSET 0x04 +#define HYPER_MEM_CFG0_CHANNEL_OFFSET 0x08 +#define HYPER_MEM_CFG1_CHANNEL_OFFSET 0x0C +#define HYPER_MEM_CFG2_CHANNEL_OFFSET 0x10 +#define HYPER_MEM_CFG3_CHANNEL_OFFSET 0x14 +#define HYPER_MEM_CFG4_CHANNEL_OFFSET 0x18 +#define HYPER_MEM_CFG5_CHANNEL_OFFSET 0x1C +#define HYPER_MEM_CFG6_CHANNEL_OFFSET 0x20 +#define HYPER_MEM_CFG7_CHANNEL_OFFSET 0x24 +#define HYPER_NB_REGS 10 + +#define HYPER_EXT_ADDR_CHANNEL_CUSTOM_OFFSET 0x20 +#define HYPER_EXT_CFG_CHANNEL_CUSTOM_OFFSET 0x24 +#define HYPER_MEM_CFG0_CHANNEL_CUSTOM_OFFSET 0x28 +#define HYPER_MEM_CFG1_CHANNEL_CUSTOM_OFFSET 0x2C +#define HYPER_MEM_CFG2_CHANNEL_CUSTOM_OFFSET 0x30 +#define HYPER_MEM_CFG3_CHANNEL_CUSTOM_OFFSET 0x34 +#define HYPER_MEM_CFG4_CHANNEL_CUSTOM_OFFSET 0x38 +#define HYPER_MEM_CFG5_CHANNEL_CUSTOM_OFFSET 0x3C +#define HYPER_MEM_CFG6_CHANNEL_CUSTOM_OFFSET 0x40 +#define HYPER_MEM_CFG7_CHANNEL_CUSTOM_OFFSET 0x44 + +#define HYPER_EXT_ADDR_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_EXT_ADDR_CHANNEL_CUSTOM_OFFSET) +#define HYPER_EXT_CFG_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_EXT_CFG_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG0_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG0_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG1_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG1_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG2_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG2_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG3_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG3_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG4_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG4_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG5_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG5_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG6_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG6_CHANNEL_CUSTOM_OFFSET) +#define HYPER_MEM_CFG7_OFFSET (UDMA_HYPER_OFFSET(0) + HYPER_MEM_CFG7_CHANNEL_CUSTOM_OFFSET) + +#define HYPER_EXT_ADDR (ARCHI_UDMA_ADDR + HYPER_EXT_ADDR_OFFSET) +#define HYPER_EXT_CFG (ARCHI_UDMA_ADDR + HYPER_EXT_CFG_OFFSET) +#define HYPER_MEM_CFG0 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG0_OFFSET) +#define HYPER_MEM_CFG1 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG1_OFFSET) +#define HYPER_MEM_CFG2 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG2_OFFSET) +#define HYPER_MEM_CFG3 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG3_OFFSET) +#define HYPER_MEM_CFG4 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG4_OFFSET) +#define HYPER_MEM_CFG5 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG5_OFFSET) +#define HYPER_MEM_CFG6 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG6_OFFSET) +#define HYPER_MEM_CFG7 (ARCHI_UDMA_ADDR + HYPER_MEM_CFG7_OFFSET) + +#define HYPER_EXT_ADDR_MASK 0xFFFFFFFF +#define HYPER_EXT_CFG_MASK 0x0000 // Not use +#define HYPER_MEM_CFG0_MASK 0x3FFF +#define HYPER_MEM_CFG1_MASK 0xFFFFFF +#define HYPER_MEM_CFG2_MASK 0x01FF01FF +#define HYPER_MEM_CFG3_MASK 0x73F +#define HYPER_MEM_CFG4_MASK 0x3FFF +#define HYPER_MEM_CFG5_MASK 0x00FFFFFF +#define HYPER_MEM_CFG6_MASK 0x01FF01FF +#define HYPER_MEM_CFG7_MASK 0x3F + +// HYPER RAM CONFIG +#define HYPER_MEM_CFG0_MBR0_OFFSET 0 // HyperRam base address, default = 0x0 +#define HYPER_MEM_CFG0_LATENCY0_OFFSET 8 +#define HYPER_MEM_CFG0_WRAP_SIZE0_OFFSET 12 + +#define HYPER_MEM_CFG1_RD_CSHI0_OFFSET 0 +#define HYPER_MEM_CFG1_RD_CSS0_OFFSET 4 +#define HYPER_MEM_CFG1_RD_CSH0_OFFSET 8 +#define HYPER_MEM_CFG1_WR_CSHI0_OFFSET 12 +#define HYPER_MEM_CFG1_WR_CSS0_OFFSET 16 +#define HYPER_MEM_CFG1_WR_CSH0_OFFSET 20 + +#define HYPER_MEM_CFG2_RD_MAX_LENGTH0_OFFSET 0 +#define HYPER_MEM_CFG2_WR_MAX_LENGTH0_OFFSET 16 + +#define HYPER_MEM_CFG3_ACS0_OFFSET 0 +#define HYPER_MEM_CFG3_TCO0_OFFSET 1 +#define HYPER_MEM_CFG3_DT0_OFFSET 2 +#define HYPER_MEM_CFG3_CRT0_OFFSET 3 // HyperRAM memory access 0, for register access 1 +#define HYPER_MEM_CFG3_RD_MAX_LEN_EN0_OFFSET 4 +#define HYPER_MEM_CFG3_WR_MAX_LEN_EN0_OFFSET 5 +#define HYPER_MEM_CFG3_RDS_DELAY_ADJ_OFFSET 8 + +// HYPER FLASH CONFIG +#define HYPER_MEM_CFG4_MBR1_OFFSET 0// Hyperflash base address, default = MBR0 + HYPERRAM SIZE +#define HYPER_MEM_CFG4_LATENCY1_OFFSET 8 +#define HYPER_MEM_CFG4_WRAP_SIZE1_OFFSET 12 + +#define HYPER_MEM_CFG5_RD_CSHI1_OFFSET 0 +#define HYPER_MEM_CFG5_RD_CSS1_OFFSET 4 +#define HYPER_MEM_CFG5_RD_CSH1_OFFSET 8 +#define HYPER_MEM_CFG5_WR_CSHI1_OFFSET 12 +#define HYPER_MEM_CFG5_WR_CSS1_OFFSET 16 +#define HYPER_MEM_CFG5_WR_CSH1_OFFSET 20 + +#define HYPER_MEM_CFG6_RD_MAX_LENGTH1_OFFSET 0 +#define HYPER_MEM_CFG6_WR_MAX_LENGTH1_OFFSET 16 + +#define HYPER_MEM_CFG7_ACS1_OFFSET 0 +#define HYPER_MEM_CFG7_TCO1_OFFSET 1 +#define HYPER_MEM_CFG7_DT1_OFFSET 2 +#define HYPER_MEM_CFG7_CRT1_OFFSET 3 // HyperFlash memory access 0, for register access 1 +#define HYPER_MEM_CFG7_RD_MAX_LEN_EN1_OFFSET 4 +#define HYPER_MEM_CFG7_WR_MAX_LEN_EN1_OFFSET 5 + +// BITS +#define HYPER_MEM_CFG3_MASK_GEN_B(offset) ((~(1 << offset)) & HYPER_MEM_CFG3_MASK) +#define HYPER_MEM_CFG7_MASK_GEN_B(offset) ((~(1 << offset)) & HYPER_MEM_CFG7_MASK) +// TWO BITS +#define HYPER_MEM_CFG0_MASK_GEN_TB(offset) ((~(0x3 << offset)) & HYPER_MEM_CFG0_MASK) +#define HYPER_MEM_CFG4_MASK_GEN_TB(offset) ((~(0x3 << offset)) & HYPER_MEM_CFG4_MASK) +// THREE BITS +#define HYPER_MEM_CFG3_MASK_GEN_THB(offset) ((~(0x7 << offset)) & HYPER_MEM_CFG3_MASK) +// HALF BYTES +#define HYPER_MEM_CFG0_MASK_GEN_HB(offset) ((~(0xF << offset)) & HYPER_MEM_CFG0_MASK) +#define HYPER_MEM_CFG1_MASK_GEN_HB(offset) ((~(0xF << offset)) & HYPER_MEM_CFG1_MASK) +#define HYPER_MEM_CFG4_MASK_GEN_HB(offset) ((~(0xF << offset)) & HYPER_MEM_CFG4_MASK) +#define HYPER_MEM_CFG5_MASK_GEN_HB(offset) ((~(0xF << offset)) & HYPER_MEM_CFG5_MASK) +// BYTES +#define HYPER_MEM_CFG0_MASK_GEN_BYTE(offset) ((~(0xFF << offset)) & HYPER_MEM_CFG0_MASK) +#define HYPER_MEM_CFG4_MASK_GEN_BYTE(offset) ((~(0xFF << offset)) & HYPER_MEM_CFG4_MASK) +// NINE BITS +#define HYPER_MEM_CFG2_MASK_GEN_NB(offset) ((~(0x1FF << offset)) & HYPER_MEM_CFG2_MASK) +#define HYPER_MEM_CFG6_MASK_GEN_NB(offset) ((~(0x1FF << offset)) & HYPER_MEM_CFG6_MASK) + +// MASK +#define HYPER_MEM_CFG0_MBR0_MASK_BYTE HYPER_MEM_CFG0_MASK_GEN_BYTE(HYPER_MEM_CFG0_MBR0_OFFSET) +#define HYPER_MEM_CFG0_LATENCY0_MASK_HB HYPER_MEM_CFG0_MASK_GEN_HB(HYPER_MEM_CFG0_LATENCY0_OFFSET) +#define HYPER_MEM_CFG0_WRAP_SIZE0_MASK_TB HYPER_MEM_CFG0_MASK_GEN_TB(HYPER_MEM_CFG0_WRAP_SIZE0_OFFSET) +#define HYPER_MEM_CFG1_RD_CSHI0_MASK_HB HYPER_MEM_CFG1_MASK_GEN_HB(HYPER_MEM_CFG1_RD_CSHI0_OFFSET) +#define HYPER_MEM_CFG1_RD_CSS0_MASK_HB HYPER_MEM_CFG1_MASK_GEN_HB(HYPER_MEM_CFG1_RD_CSS0_OFFSET) +#define HYPER_MEM_CFG1_RD_CSH0_MASK_HB HYPER_MEM_CFG1_MASK_GEN_HB(HYPER_MEM_CFG1_RD_CSH0_OFFSET) +#define HYPER_MEM_CFG1_WR_CSHI0_MASK_HB HYPER_MEM_CFG1_MASK_GEN_HB(HYPER_MEM_CFG1_WR_CSHI0_OFFSET) +#define HYPER_MEM_CFG1_WR_CSS0_MASK_HB HYPER_MEM_CFG1_MASK_GEN_HB(HYPER_MEM_CFG1_WR_CSS0_OFFSET) +#define HYPER_MEM_CFG1_WR_CSH0_MASK_HB HYPER_MEM_CFG1_MASK_GEN_HB(HYPER_MEM_CFG1_WR_CSH0_OFFSET) +#define HYPER_MEM_CFG2_RD_MAX_LENGTH0_MASK_NB HYPER_MEM_CFG2_MASK_GEN_NB(HYPER_MEM_CFG2_RD_MAX_LENGTH0_OFFSET) +#define HYPER_MEM_CFG2_WR_MAX_LENGTH0_MASK_NB HYPER_MEM_CFG2_MASK_GEN_NB(HYPER_MEM_CFG2_WR_MAX_LENGTH0_OFFSET) +#define HYPER_MEM_CFG3_ACS0_MASK_B HYPER_MEM_CFG3_MASK_GEN_B(HYPER_MEM_CFG3_ACS0_OFFSET) +#define HYPER_MEM_CFG3_TCO0_MASK_B HYPER_MEM_CFG3_MASK_GEN_B(HYPER_MEM_CFG3_TCO0_OFFSET) +#define HYPER_MEM_CFG3_DT0_MASK_B HYPER_MEM_CFG3_MASK_GEN_B(HYPER_MEM_CFG3_DT0_OFFSET) +#define HYPER_MEM_CFG3_CRT0_MASK_B HYPER_MEM_CFG3_MASK_GEN_B(HYPER_MEM_CFG3_CRT0_OFFSET) +#define HYPER_MEM_CFG3_RD_MAX_LEN_EN0_MASK_B HYPER_MEM_CFG3_MASK_GEN_B(HYPER_MEM_CFG3_RD_MAX_LEN_EN0_OFFSET) +#define HYPER_MEM_CFG3_WR_MAX_LEN_EN0_MASK_B HYPER_MEM_CFG3_MASK_GEN_B(HYPER_MEM_CFG3_WR_MAX_LEN_EN0_OFFSET) +#define HYPER_MEM_CFG3_RDS_DELAY_ADJ_MASK_THB HYPER_MEM_CFG3_MASK_GEN_THB(HYPER_MEM_CFG3_RDS_DELAY_ADJ_OFFSET) + +#define HYPER_MEM_CFG4_MBR1_MASK_BYTE HYPER_MEM_CFG4_MASK_GEN_BYTE(HYPER_MEM_CFG4_MBR1_OFFSET) +// This bit is ignored when the DEVTYPE = 1 is chosen to the HyperFlash memory. +//#define HYPER_MEM_CFG4_LATENCY1_MASK_HB HYPER_MEM_CFG4_MASK_GEN_HB(HYPER_MEM_CFG4_LATENCY1_OFFSET) +#define HYPER_MEM_CFG4_WRAP_SIZE1_MASK_TB HYPER_MEM_CFG4_MASK_GEN_TB(HYPER_MEM_CFG4_WRAP_SIZE1_OFFSET) +#define HYPER_MEM_CFG5_RD_CSHI1_MASK_HB HYPER_MEM_CFG5_MASK_GEN_HB(HYPER_MEM_CFG5_RD_CSHI1_OFFSET) +#define HYPER_MEM_CFG5_RD_CSS1_MASK_HB HYPER_MEM_CFG5_MASK_GEN_HB(HYPER_MEM_CFG5_RD_CSS1_OFFSET) +#define HYPER_MEM_CFG5_RD_CSH1_MASK_HB HYPER_MEM_CFG5_MASK_GEN_HB(HYPER_MEM_CFG5_RD_CSH1_OFFSET) +#define HYPER_MEM_CFG5_WR_CSHI1_MASK_HB HYPER_MEM_CFG5_MASK_GEN_HB(HYPER_MEM_CFG5_WR_CSHI1_OFFSET) +#define HYPER_MEM_CFG5_WR_CSS1_MASK_HB HYPER_MEM_CFG5_MASK_GEN_HB(HYPER_MEM_CFG5_WR_CSS1_OFFSET) +#define HYPER_MEM_CFG5_WR_CSH1_MASK_HB HYPER_MEM_CFG5_MASK_GEN_HB(HYPER_MEM_CFG5_WR_CSH1_OFFSET) +#define HYPER_MEM_CFG6_RD_MAX_LENGTH1_MASK_NB HYPER_MEM_CFG6_MASK_GEN_NB(HYPER_MEM_CFG6_RD_MAX_LENGTH1_OFFSET) +#define HYPER_MEM_CFG6_WR_MAX_LENGTH1_MASK_NB HYPER_MEM_CFG6_MASK_GEN_NB(HYPER_MEM_CFG6_WR_MAX_LENGTH1_OFFSET) +#define HYPER_MEM_CFG7_ACS1_MASK_B HYPER_MEM_CFG7_MASK_GEN_B(HYPER_MEM_CFG7_ACS1_OFFSET) +#define HYPER_MEM_CFG7_TCO1_MASK_B HYPER_MEM_CFG7_MASK_GEN_B(HYPER_MEM_CFG7_TCO1_OFFSET) +#define HYPER_MEM_CFG7_DT1_MASK_B HYPER_MEM_CFG7_MASK_GEN_B(HYPER_MEM_CFG7_DT1_OFFSET) +#define HYPER_MEM_CFG7_CRT1_MASK_B HYPER_MEM_CFG7_MASK_GEN_B(HYPER_MEM_CFG7_CRT1_OFFSET) +#define HYPER_MEM_CFG7_RD_MAX_LEN_EN1_MASK_B HYPER_MEM_CFG7_MASK_GEN_B(HYPER_MEM_CFG7_RD_MAX_LEN_EN1_OFFSET) +#define HYPER_MEM_CFG7_WR_MAX_LEN_EN1_MASK_B HYPER_MEM_CFG7_MASK_GEN_B(HYPER_MEM_CFG7_WR_MAX_LEN_EN1_OFFSET) + + +#define ARCHI_UDMA_HYPER_RX_EVT 0 +#define ARCHI_UDMA_HYPER_TX_EVT 1 + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/hyper/udma_hyper_v2.h b/sw/pulp-sdk/archi/include/archi/udma/hyper/udma_hyper_v2.h new file mode 100644 index 0000000..cccf3b5 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/hyper/udma_hyper_v2.h @@ -0,0 +1,999 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_HYPER_UDMA_HYPER_V2_H__ +#define __INCLUDE_ARCHI_UDMA_HYPER_UDMA_HYPER_V2_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// uDMA RX HYPERBUS buffer base address configuration register. +#define HYPER_RX_SADDR_OFFSET 0x0 + +// uDMA RX HYPERBUS buffer size configuration register. +#define HYPER_RX_SIZE_OFFSET 0x4 + +// uDMA RX HYPERBUS stream configuration register. +#define HYPER_RX_CFG_OFFSET 0x8 + +// uDMA TX HYPERBUS buffer base address configuration register. +#define HYPER_TX_SADDR_OFFSET 0x10 + +// uDMA TX HYPERBUS buffer size configuration register. +#define HYPER_TX_SIZE_OFFSET 0x14 + +// uDMA TX HYPERBUS stream configuration register. +#define HYPER_TX_CFG_OFFSET 0x18 + +// Memory access address register. +#define HYPER_EXT_ADDR_OFFSET 0x20 + +// HYPERBUS and Octo SPI Memory Timing configuration register. +#define HYPER_TIMING_CFG_OFFSET 0x24 + +// Device start address register. +#define HYPER_MBA0_OFFSET 0x28 + +// Device start address register. +#define HYPER_MBA1_OFFSET 0x2c + +// Device type register(RAM or FLASH). +#define HYPER_DEVICE_OFFSET 0x30 + +// OSPI command +#define HYPER_OSPI_CMD_OFFSET 0x34 + +// OSPI address +#define HYPER_OSPI_ADDR_OFFSET 0x38 + +// OSPI configuration +#define HYPER_OSPI_CFG_OFFSET 0x3c + +// OSPI chip select configuration +#define HYPER_OSPI_CSN_OFFSET 0x40 + +// - +#define HYPER__RESERVED0_OFFSET 0x44 + +// - +#define HYPER__RESERVED1_OFFSET 0x48 + +// OSPI interrupt enable register +#define HYPER_IRQ_EN_OFFSET 0x4c + +// Clock divide. +#define HYPER_CLK_DIV_OFFSET 0x50 + +// Transfer status for error. +#define HYPER_STATUS_OFFSET 0x54 + + + +// +// REGISTERS FIELDS +// + +// RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address (access: R/W) +#define HYPER_RX_SADDR_RX_SADDR_BIT 0 +#define HYPER_RX_SADDR_RX_SADDR_WIDTH 16 +#define HYPER_RX_SADDR_RX_SADDR_MASK 0xffff + +// RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define HYPER_RX_SIZE_RX_SIZE_BIT 0 +#define HYPER_RX_SIZE_RX_SIZE_WIDTH 17 +#define HYPER_RX_SIZE_RX_SIZE_MASK 0x1ffff + +// RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define HYPER_RX_CFG_CONTINOUS_BIT 0 +#define HYPER_RX_CFG_CONTINOUS_WIDTH 1 +#define HYPER_RX_CFG_CONTINOUS_MASK 0x1 + +// RX channel enable and start transfer bitfield: -1'b0: disable -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define HYPER_RX_CFG_EN_BIT 4 +#define HYPER_RX_CFG_EN_WIDTH 1 +#define HYPER_RX_CFG_EN_MASK 0x10 + +// RX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue (access: R) +#define HYPER_RX_CFG_PENDING_BIT 5 +#define HYPER_RX_CFG_PENDING_WIDTH 1 +#define HYPER_RX_CFG_PENDING_MASK 0x20 + +// RX channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear the on-going transfer (access: W) +#define HYPER_RX_CFG_CLR_BIT 6 +#define HYPER_RX_CFG_CLR_WIDTH 1 +#define HYPER_RX_CFG_CLR_MASK 0x40 + +// TX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets buffer base address (access: R/W) +#define HYPER_TX_SADDR_TX_SADDR_BIT 0 +#define HYPER_TX_SADDR_TX_SADDR_WIDTH 16 +#define HYPER_TX_SADDR_TX_SADDR_MASK 0xffff + +// TX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define HYPER_TX_SIZE_TX_SIZE_BIT 0 +#define HYPER_TX_SIZE_TX_SIZE_WIDTH 17 +#define HYPER_TX_SIZE_TX_SIZE_MASK 0x1ffff + +// TX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define HYPER_TX_CFG_CONTINOUS_BIT 0 +#define HYPER_TX_CFG_CONTINOUS_WIDTH 1 +#define HYPER_TX_CFG_CONTINOUS_MASK 0x1 + +// TX channel enable and start transfer bitfield: -1'b0: disabled -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define HYPER_TX_CFG_EN_BIT 4 +#define HYPER_TX_CFG_EN_WIDTH 1 +#define HYPER_TX_CFG_EN_MASK 0x10 + +// TX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue (access: R) +#define HYPER_TX_CFG_PENDING_BIT 5 +#define HYPER_TX_CFG_PENDING_WIDTH 1 +#define HYPER_TX_CFG_PENDING_MASK 0x20 + +// TX channel clear and stop transfer bitfield: -1'b0: disabled -1'b1: stop and clear the on-going transfer (access: W) +#define HYPER_TX_CFG_CLR_BIT 6 +#define HYPER_TX_CFG_CLR_WIDTH 1 +#define HYPER_TX_CFG_CLR_MASK 0x40 + +// Memory access address bitfield. (access: R/W) +#define HYPER_EXT_ADDR_SADDR_BIT 0 +#define HYPER_EXT_ADDR_SADDR_WIDTH 31 +#define HYPER_EXT_ADDR_SADDR_MASK 0x7fffffff + +// Register access flag bitfield. (access: R/W) +#define HYPER_EXT_ADDR_REG_ACCESS_BIT 31 +#define HYPER_EXT_ADDR_REG_ACCESS_WIDTH 1 +#define HYPER_EXT_ADDR_REG_ACCESS_MASK 0x80000000 + +// Latency Cycle value for both HyperRAM and HyperFLASH for chip select 0. When using HyperRAM memory, this bit should be set to the same value as the read latency in configuration register of HyperRAM memory the read latency in configuration register of HyperRAM memory. For SPI, is the dummy cycle after ADDRESS stage : - 4'b0000: 16 CK - 4'b0001: 1 CK - 4'b0001: 2 CK ... - 4'b1111: 15 CK (access: R/W) +#define HYPER_TIMING_CFG_LATENCY0_BIT 0 +#define HYPER_TIMING_CFG_LATENCY0_WIDTH 5 +#define HYPER_TIMING_CFG_LATENCY0_MASK 0x1f + +// Latency Cycle value for both HyperRAM and HyperFLASH for chip select 1. When using HyperRAM memory, this bit should be set to the same value as the read latency in configuration register of HyperRAM memory the read latency in configuration register of HyperRAM memory. For SPI, is the dummy cycle after ADDRESS stage : - 5'b00000: 0 CK - 5'b00001: 1 CK - 5'b000001: 2 CK ... - 5'b11111: 31 CK (access: R/W) +#define HYPER_TIMING_CFG_LATENCY1_BIT 5 +#define HYPER_TIMING_CFG_LATENCY1_WIDTH 5 +#define HYPER_TIMING_CFG_LATENCY1_MASK 0x3e0 + +// Some HyperBus devices may require a minimum time between the end of a prior transaction and the start of a new access. This time is referred to as Read-Write-Recovery time (tRWR). The master interface must start driving CS# Low only at a time when the CA1 transfer will complete after tRWR is satisfied. - 5'b00000: 0 CK - 5'b00001: 1 CK - 5'b000001: 2 CK ... - 5'b11111: 31 CK (access: R/W) +#define HYPER_TIMING_CFG_RW_RECOVERY_BIT 10 +#define HYPER_TIMING_CFG_RW_RECOVERY_WIDTH 4 +#define HYPER_TIMING_CFG_RW_RECOVERY_MASK 0x3c00 + +// Delay of RWDS for center aligned read: - 3'b000: 0 logic delay - 3'b001: 1 logic delay - 3'b010: 2 logic delay - 3'b111: 7 logic delay (access: R/W) +#define HYPER_TIMING_CFG_RWDS_DELAY_BIT 14 +#define HYPER_TIMING_CFG_RWDS_DELAY_WIDTH 3 +#define HYPER_TIMING_CFG_RWDS_DELAY_MASK 0x1c000 + +// Auto check for RWDS high or low for additional latency : - 1'b0: additional latency no autocheck - 1'b1: additional latency autocheck (access: R/W) +#define HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_BIT 17 +#define HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_WIDTH 1 +#define HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_MASK 0x20000 + +// Maximum chip select low time for self-refresh HYPERRAM to valid the data transfer : - 14'h0000: 1 CK - 14'h0001: 2 CK - 14'h0011: 3 CK - - 14'h3FFF: 16383 CK (access: R/W) +#define HYPER_TIMING_CFG_CS_MAX_BIT 18 +#define HYPER_TIMING_CFG_CS_MAX_WIDTH 16 +#define HYPER_TIMING_CFG_CS_MAX_MASK 0x3fffc0000 + +// Memory Base Address 0 for both RAM and FLASH bitfield. The base address of addressable region to each memory is set up. Since register can be set in 16M bytes boundary, lower 24 bit is fixed to 0. MBA0 can be greater than MBA1, the chip select which decided by the relationship among MBA0, MBA1, and EXT_ADDR. - MBA0 < MBA1, if (MBA1 <= EXT_ADDR) CS1 = 0; else CS0 = 0; - MBA0 > MBA1, if (MBA0 <= EXT_ADDR) CS0 = 0; else CS1 = 0; (access: R/W) +#define HYPER_MBA0_MBA0_BIT 24 +#define HYPER_MBA0_MBA0_WIDTH 7 +#define HYPER_MBA0_MBA0_MASK 0x7f000000 + +// Memory Base Address for both RAM and FLASH bitfield. The base address of addressable region to each memory is set up. Since register can be set in 16M bytes boundary, lower 24 bit is fixed to 0. MBA0 can be greater than MBA1, the chip select which decided by the relationship among MBA0, MBA1, and EXT_ADDR. - MBA0 < MBA1, if (MBA1 <= EXT_ADDR) CSn1 = 0; else CSn0 = 0; - MBA0 > MBA1, if (MBA0 <= EXT_ADDR) CSn0 = 0; else CSn1 = 0; (access: R/W) +#define HYPER_MBA1_MBA1_BIT 24 +#define HYPER_MBA1_MBA1_WIDTH 7 +#define HYPER_MBA1_MBA1_MASK 0x7f000000 + +// Device type : - 1'b00: Octo/ Single SPI - 1'b01: HYPERBUS (access: R/W) +#define HYPER_DEVICE_TYPE_BIT 0 +#define HYPER_DEVICE_TYPE_WIDTH 1 +#define HYPER_DEVICE_TYPE_MASK 0x1 + +// When in HYPERBUS mode : - 1'b0: HYPERRAM - 1'b1: HYPERLASH (access: R/W) +#define HYPER_DEVICE_DT0_BIT 1 +#define HYPER_DEVICE_DT0_WIDTH 1 +#define HYPER_DEVICE_DT0_MASK 0x2 + +// When in HYPERBUS mode : - 1'b0: HYPERRAM - 1'b1: HYPERLASH (access: R/W) +#define HYPER_DEVICE_DT1_BIT 2 +#define HYPER_DEVICE_DT1_WIDTH 1 +#define HYPER_DEVICE_DT1_MASK 0x4 + +// Octo SPI command size : - 2b0: 0 byte - 2'b1: 1 byte - 2'b2: 2 byte (access: R/W) +#define HYPER_OSPI_CFG_CMD_SIZE_BIT 0 +#define HYPER_OSPI_CFG_CMD_SIZE_WIDTH 2 +#define HYPER_OSPI_CFG_CMD_SIZE_MASK 0x3 + +// Octo SPI address size : - 3'b000: 0 byte (Jump ADDRESS stage) - 3'b001: 1 byte - 3'b010: 2 byte - 3'b011: 3 byte - 3'b100: 4 byte (access: R/W) +#define HYPER_OSPI_CFG_ADDR_SIZE_BIT 4 +#define HYPER_OSPI_CFG_ADDR_SIZE_WIDTH 3 +#define HYPER_OSPI_CFG_ADDR_SIZE_MASK 0x70 + +// Octo SPI line number for Single SPI or Octo SPI: - 1'b0: 8 line for Octo SPI - 1'b1: 1 line for Single SPI (SI : dq[0] SO: dq[1]) (access: R/W) +#define HYPER_OSPI_CFG_LINE_BIT 8 +#define HYPER_OSPI_CFG_LINE_WIDTH 1 +#define HYPER_OSPI_CFG_LINE_MASK 0x100 + +// Octo SPI command ddr mode or single mode : - 1'b0: DTR mode - 1'b1: STR mode (access: R/W) +#define HYPER_OSPI_CFG_CMD_DTR_STR_BIT 12 +#define HYPER_OSPI_CFG_CMD_DTR_STR_WIDTH 1 +#define HYPER_OSPI_CFG_CMD_DTR_STR_MASK 0x1000 + +// Octo SPI address ddr mode or single mode : - 1'b0: DTR mode - 1'b1: STR mode (access: R/W) +#define HYPER_OSPI_CFG_ADDR_DTR_STR_BIT 13 +#define HYPER_OSPI_CFG_ADDR_DTR_STR_WIDTH 1 +#define HYPER_OSPI_CFG_ADDR_DTR_STR_MASK 0x2000 + +// Octo SPI data ddr mode or single mode : - 1'b0: DTR mode - 1'b1: STR mode (access: R/W) +#define HYPER_OSPI_CFG_DATA_DTR_STR_BIT 14 +#define HYPER_OSPI_CFG_DATA_DTR_STR_WIDTH 1 +#define HYPER_OSPI_CFG_DATA_DTR_STR_MASK 0x4000 + +// Octo SPI data ddr mode data MSB: - 1'b0: LSB - 1'b1: MSB (access: R/W) +#define HYPER_OSPI_CFG_DATA_DTR_MSB_BIT 15 +#define HYPER_OSPI_CFG_DATA_DTR_MSB_WIDTH 1 +#define HYPER_OSPI_CFG_DATA_DTR_MSB_MASK 0x8000 + +// Octo SPI chip select index : - 1'b0: CSN0 - 1'b1: CSN1 (access: R/W) +#define HYPER_OSPI_CSN_INDEX_BIT 0 +#define HYPER_OSPI_CSN_INDEX_WIDTH 1 +#define HYPER_OSPI_CSN_INDEX_MASK 0x1 + +// Octo SPI chip select controlled by user : - 1'b0: IP control CSN - 1'b1: USER control CSN (access: R/W) +#define HYPER_OSPI_CSN_USER_CTRL_CSN_BIT 4 +#define HYPER_OSPI_CSN_USER_CTRL_CSN_WIDTH 1 +#define HYPER_OSPI_CSN_USER_CTRL_CSN_MASK 0x10 + +// Octo SPI chip select user control value : - 1'b0: CSN low - 1'b1: CSN high (access: R/W) +#define HYPER_OSPI_CSN_CSN_VAL_BIT 5 +#define HYPER_OSPI_CSN_CSN_VAL_WIDTH 1 +#define HYPER_OSPI_CSN_CSN_VAL_MASK 0x20 + +// Octo SPI interrupt enable control : - 1'b0: interrupt disable - 1'b1: Interrupt enable (access: R/W) +#define HYPER_IRQ_EN_EN_BIT 0 +#define HYPER_IRQ_EN_EN_WIDTH 1 +#define HYPER_IRQ_EN_EN_MASK 0x1 + +// Clock divide data, form 0 255, frequency divide table is : -8h0 IO_FREQUENCY / 1 -8h1 IO_FREQUENCY / 2 -8h2 IO_FREQUENCY / 4 (access: R/W) +#define HYPER_CLK_DIV_DATA_BIT 0 +#define HYPER_CLK_DIV_DATA_WIDTH 8 +#define HYPER_CLK_DIV_DATA_MASK 0xff + +// Clock divide valid, user can not control. Every time there is clock divide write access, set 1 by default, then when clock divide is finished, set 0. (access: W) +#define HYPER_CLK_DIV_VALID_BIT 8 +#define HYPER_CLK_DIV_VALID_WIDTH 1 +#define HYPER_CLK_DIV_VALID_MASK 0x100 + +// TX transfer error because of tcsm, write 1 to clear: - 1'b0: no error - 1'b1: error (access: R/W) +#define HYPER_STATUS_TX_ERROR_BIT 0 +#define HYPER_STATUS_TX_ERROR_WIDTH 1 +#define HYPER_STATUS_TX_ERROR_MASK 0x1 + +// RX transfer error because of tcsm, write 1 to clear: - 1'b0: no error - 1'b1: error (access: R/W) +#define HYPER_STATUS_RX_ERROR_BIT 1 +#define HYPER_STATUS_RX_ERROR_WIDTH 1 +#define HYPER_STATUS_RX_ERROR_MASK 0x2 + +// RX TX transfer end flag, can be polling by user, write 1 to clear: - 1'b0: not end - 1'b1: end (access: R/W) +#define HYPER_STATUS_RX_TX_END_BIT 2 +#define HYPER_STATUS_RX_TX_END_WIDTH 1 +#define HYPER_STATUS_RX_TX_END_MASK 0x4 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rx_saddr :16; // RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address + }; + unsigned int raw; +} __attribute__((packed)) hyper_rx_saddr_t; + +typedef union { + struct { + unsigned int rx_size :17; // RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) hyper_rx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int padding0:3 ; + unsigned int en :1 ; // RX channel enable and start transfer bitfield: -1'b0: disable -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int pending :1 ; // RX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue + unsigned int clr :1 ; // RX channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear the on-going transfer + }; + unsigned int raw; +} __attribute__((packed)) hyper_rx_cfg_t; + +typedef union { + struct { + unsigned int tx_saddr :16; // TX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets buffer base address + }; + unsigned int raw; +} __attribute__((packed)) hyper_tx_saddr_t; + +typedef union { + struct { + unsigned int tx_size :17; // TX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) hyper_tx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // TX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int padding0:3 ; + unsigned int en :1 ; // TX channel enable and start transfer bitfield: -1'b0: disabled -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int pending :1 ; // TX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue + unsigned int clr :1 ; // TX channel clear and stop transfer bitfield: -1'b0: disabled -1'b1: stop and clear the on-going transfer + }; + unsigned int raw; +} __attribute__((packed)) hyper_tx_cfg_t; + +typedef union { + struct { + unsigned int saddr :31; // Memory access address bitfield. + unsigned int reg_access :1 ; // Register access flag bitfield. + }; + unsigned int raw; +} __attribute__((packed)) hyper_ext_addr_t; + +typedef union { + struct { + unsigned int latency0 :5 ; // Latency Cycle value for both HyperRAM and HyperFLASH for chip select 0. When using HyperRAM memory, this bit should be set to the same value as the read latency in configuration register of HyperRAM memory the read latency in configuration register of HyperRAM memory. For SPI, is the dummy cycle after ADDRESS stage : - 4'b0000: 16 CK - 4'b0001: 1 CK - 4'b0001: 2 CK ... - 4'b1111: 15 CK + unsigned int latency1 :5 ; // Latency Cycle value for both HyperRAM and HyperFLASH for chip select 1. When using HyperRAM memory, this bit should be set to the same value as the read latency in configuration register of HyperRAM memory the read latency in configuration register of HyperRAM memory. For SPI, is the dummy cycle after ADDRESS stage : - 5'b00000: 0 CK - 5'b00001: 1 CK - 5'b000001: 2 CK ... - 5'b11111: 31 CK + unsigned int rw_recovery :4 ; // Some HyperBus devices may require a minimum time between the end of a prior transaction and the start of a new access. This time is referred to as Read-Write-Recovery time (tRWR). The master interface must start driving CS# Low only at a time when the CA1 transfer will complete after tRWR is satisfied. - 5'b00000: 0 CK - 5'b00001: 1 CK - 5'b000001: 2 CK ... - 5'b11111: 31 CK + unsigned int rwds_delay :3 ; // Delay of RWDS for center aligned read: - 3'b000: 0 logic delay - 3'b001: 1 logic delay - 3'b010: 2 logic delay - 3'b111: 7 logic delay + unsigned int additional_latency_autocheck_en:1 ; // Auto check for RWDS high or low for additional latency : - 1'b0: additional latency no autocheck - 1'b1: additional latency autocheck + unsigned int cs_max :16; // Maximum chip select low time for self-refresh HYPERRAM to valid the data transfer : - 14'h0000: 1 CK - 14'h0001: 2 CK - 14'h0011: 3 CK - - 14'h3FFF: 16383 CK + }; + unsigned int raw; +} __attribute__((packed)) hyper_timing_cfg_t; + +typedef union { + struct { + unsigned int padding0:24; + unsigned int mba0 :7 ; // Memory Base Address 0 for both RAM and FLASH bitfield. The base address of addressable region to each memory is set up. Since register can be set in 16M bytes boundary, lower 24 bit is fixed to 0. MBA0 can be greater than MBA1, the chip select which decided by the relationship among MBA0, MBA1, and EXT_ADDR. - MBA0 < MBA1, if (MBA1 <= EXT_ADDR) CS1 = 0; else CS0 = 0; - MBA0 > MBA1, if (MBA0 <= EXT_ADDR) CS0 = 0; else CS1 = 0; + }; + unsigned int raw; +} __attribute__((packed)) hyper_mba0_t; + +typedef union { + struct { + unsigned int padding0:24; + unsigned int mba1 :7 ; // Memory Base Address for both RAM and FLASH bitfield. The base address of addressable region to each memory is set up. Since register can be set in 16M bytes boundary, lower 24 bit is fixed to 0. MBA0 can be greater than MBA1, the chip select which decided by the relationship among MBA0, MBA1, and EXT_ADDR. - MBA0 < MBA1, if (MBA1 <= EXT_ADDR) CSn1 = 0; else CSn0 = 0; - MBA0 > MBA1, if (MBA0 <= EXT_ADDR) CSn0 = 0; else CSn1 = 0; + }; + unsigned int raw; +} __attribute__((packed)) hyper_mba1_t; + +typedef union { + struct { + unsigned int type :1 ; // Device type : - 1'b00: Octo/ Single SPI - 1'b01: HYPERBUS + unsigned int dt0 :1 ; // When in HYPERBUS mode : - 1'b0: HYPERRAM - 1'b1: HYPERLASH + unsigned int dt1 :1 ; // When in HYPERBUS mode : - 1'b0: HYPERRAM - 1'b1: HYPERLASH + }; + unsigned int raw; +} __attribute__((packed)) hyper_device_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hyper_ospi_cmd_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hyper_ospi_addr_t; + +typedef union { + struct { + unsigned int cmd_size :2 ; // Octo SPI command size : - 2b0: 0 byte - 2'b1: 1 byte - 2'b2: 2 byte + unsigned int padding0:2 ; + unsigned int addr_size :3 ; // Octo SPI address size : - 3'b000: 0 byte (Jump ADDRESS stage) - 3'b001: 1 byte - 3'b010: 2 byte - 3'b011: 3 byte - 3'b100: 4 byte + unsigned int padding1:1 ; + unsigned int line :1 ; // Octo SPI line number for Single SPI or Octo SPI: - 1'b0: 8 line for Octo SPI - 1'b1: 1 line for Single SPI (SI : dq[0] SO: dq[1]) + unsigned int padding2:3 ; + unsigned int cmd_dtr_str :1 ; // Octo SPI command ddr mode or single mode : - 1'b0: DTR mode - 1'b1: STR mode + unsigned int addr_dtr_str :1 ; // Octo SPI address ddr mode or single mode : - 1'b0: DTR mode - 1'b1: STR mode + unsigned int data_dtr_str :1 ; // Octo SPI data ddr mode or single mode : - 1'b0: DTR mode - 1'b1: STR mode + unsigned int data_dtr_msb :1 ; // Octo SPI data ddr mode data MSB: - 1'b0: LSB - 1'b1: MSB + }; + unsigned int raw; +} __attribute__((packed)) hyper_ospi_cfg_t; + +typedef union { + struct { + unsigned int index :1 ; // Octo SPI chip select index : - 1'b0: CSN0 - 1'b1: CSN1 + unsigned int padding0:3 ; + unsigned int user_ctrl_csn :1 ; // Octo SPI chip select controlled by user : - 1'b0: IP control CSN - 1'b1: USER control CSN + unsigned int csn_val :1 ; // Octo SPI chip select user control value : - 1'b0: CSN low - 1'b1: CSN high + }; + unsigned int raw; +} __attribute__((packed)) hyper_ospi_csn_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hyper__reserved0_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) hyper__reserved1_t; + +typedef union { + struct { + unsigned int en :1 ; // Octo SPI interrupt enable control : - 1'b0: interrupt disable - 1'b1: Interrupt enable + }; + unsigned int raw; +} __attribute__((packed)) hyper_irq_en_t; + +typedef union { + struct { + unsigned int data :8 ; // Clock divide data, form 0 255, frequency divide table is : -8h0 IO_FREQUENCY / 1 -8h1 IO_FREQUENCY / 2 -8h2 IO_FREQUENCY / 4 + unsigned int valid :1 ; // Clock divide valid, user can not control. Every time there is clock divide write access, set 1 by default, then when clock divide is finished, set 0. + }; + unsigned int raw; +} __attribute__((packed)) hyper_clk_div_t; + +typedef union { + struct { + unsigned int tx_error :1 ; // TX transfer error because of tcsm, write 1 to clear: - 1'b0: no error - 1'b1: error + unsigned int rx_error :1 ; // RX transfer error because of tcsm, write 1 to clear: - 1'b0: no error - 1'b1: error + unsigned int rx_tx_end :1 ; // RX TX transfer end flag, can be polling by user, write 1 to clear: - 1'b0: not end - 1'b1: end + }; + unsigned int raw; +} __attribute__((packed)) hyper_status_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_hyper_rx_saddr : public vp::reg_32 +{ +public: + inline void rx_saddr_set(uint32_t value) { this->set_field(value, HYPER_RX_SADDR_RX_SADDR_BIT, HYPER_RX_SADDR_RX_SADDR_WIDTH); } + inline uint32_t rx_saddr_get() { return this->get_field(HYPER_RX_SADDR_RX_SADDR_BIT, HYPER_RX_SADDR_RX_SADDR_WIDTH); } +}; + +class vp_hyper_rx_size : public vp::reg_32 +{ +public: + inline void rx_size_set(uint32_t value) { this->set_field(value, HYPER_RX_SIZE_RX_SIZE_BIT, HYPER_RX_SIZE_RX_SIZE_WIDTH); } + inline uint32_t rx_size_get() { return this->get_field(HYPER_RX_SIZE_RX_SIZE_BIT, HYPER_RX_SIZE_RX_SIZE_WIDTH); } +}; + +class vp_hyper_rx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, HYPER_RX_CFG_CONTINOUS_BIT, HYPER_RX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(HYPER_RX_CFG_CONTINOUS_BIT, HYPER_RX_CFG_CONTINOUS_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, HYPER_RX_CFG_EN_BIT, HYPER_RX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(HYPER_RX_CFG_EN_BIT, HYPER_RX_CFG_EN_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, HYPER_RX_CFG_PENDING_BIT, HYPER_RX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(HYPER_RX_CFG_PENDING_BIT, HYPER_RX_CFG_PENDING_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, HYPER_RX_CFG_CLR_BIT, HYPER_RX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(HYPER_RX_CFG_CLR_BIT, HYPER_RX_CFG_CLR_WIDTH); } +}; + +class vp_hyper_tx_saddr : public vp::reg_32 +{ +public: + inline void tx_saddr_set(uint32_t value) { this->set_field(value, HYPER_TX_SADDR_TX_SADDR_BIT, HYPER_TX_SADDR_TX_SADDR_WIDTH); } + inline uint32_t tx_saddr_get() { return this->get_field(HYPER_TX_SADDR_TX_SADDR_BIT, HYPER_TX_SADDR_TX_SADDR_WIDTH); } +}; + +class vp_hyper_tx_size : public vp::reg_32 +{ +public: + inline void tx_size_set(uint32_t value) { this->set_field(value, HYPER_TX_SIZE_TX_SIZE_BIT, HYPER_TX_SIZE_TX_SIZE_WIDTH); } + inline uint32_t tx_size_get() { return this->get_field(HYPER_TX_SIZE_TX_SIZE_BIT, HYPER_TX_SIZE_TX_SIZE_WIDTH); } +}; + +class vp_hyper_tx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, HYPER_TX_CFG_CONTINOUS_BIT, HYPER_TX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(HYPER_TX_CFG_CONTINOUS_BIT, HYPER_TX_CFG_CONTINOUS_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, HYPER_TX_CFG_EN_BIT, HYPER_TX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(HYPER_TX_CFG_EN_BIT, HYPER_TX_CFG_EN_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, HYPER_TX_CFG_PENDING_BIT, HYPER_TX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(HYPER_TX_CFG_PENDING_BIT, HYPER_TX_CFG_PENDING_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, HYPER_TX_CFG_CLR_BIT, HYPER_TX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(HYPER_TX_CFG_CLR_BIT, HYPER_TX_CFG_CLR_WIDTH); } +}; + +class vp_hyper_ext_addr : public vp::reg_32 +{ +public: + inline void saddr_set(uint32_t value) { this->set_field(value, HYPER_EXT_ADDR_SADDR_BIT, HYPER_EXT_ADDR_SADDR_WIDTH); } + inline uint32_t saddr_get() { return this->get_field(HYPER_EXT_ADDR_SADDR_BIT, HYPER_EXT_ADDR_SADDR_WIDTH); } + inline void reg_access_set(uint32_t value) { this->set_field(value, HYPER_EXT_ADDR_REG_ACCESS_BIT, HYPER_EXT_ADDR_REG_ACCESS_WIDTH); } + inline uint32_t reg_access_get() { return this->get_field(HYPER_EXT_ADDR_REG_ACCESS_BIT, HYPER_EXT_ADDR_REG_ACCESS_WIDTH); } +}; + +class vp_hyper_timing_cfg : public vp::reg_32 +{ +public: + inline void latency0_set(uint32_t value) { this->set_field(value, HYPER_TIMING_CFG_LATENCY0_BIT, HYPER_TIMING_CFG_LATENCY0_WIDTH); } + inline uint32_t latency0_get() { return this->get_field(HYPER_TIMING_CFG_LATENCY0_BIT, HYPER_TIMING_CFG_LATENCY0_WIDTH); } + inline void latency1_set(uint32_t value) { this->set_field(value, HYPER_TIMING_CFG_LATENCY1_BIT, HYPER_TIMING_CFG_LATENCY1_WIDTH); } + inline uint32_t latency1_get() { return this->get_field(HYPER_TIMING_CFG_LATENCY1_BIT, HYPER_TIMING_CFG_LATENCY1_WIDTH); } + inline void rw_recovery_set(uint32_t value) { this->set_field(value, HYPER_TIMING_CFG_RW_RECOVERY_BIT, HYPER_TIMING_CFG_RW_RECOVERY_WIDTH); } + inline uint32_t rw_recovery_get() { return this->get_field(HYPER_TIMING_CFG_RW_RECOVERY_BIT, HYPER_TIMING_CFG_RW_RECOVERY_WIDTH); } + inline void rwds_delay_set(uint32_t value) { this->set_field(value, HYPER_TIMING_CFG_RWDS_DELAY_BIT, HYPER_TIMING_CFG_RWDS_DELAY_WIDTH); } + inline uint32_t rwds_delay_get() { return this->get_field(HYPER_TIMING_CFG_RWDS_DELAY_BIT, HYPER_TIMING_CFG_RWDS_DELAY_WIDTH); } + inline void additional_latency_autocheck_en_set(uint32_t value) { this->set_field(value, HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_BIT, HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_WIDTH); } + inline uint32_t additional_latency_autocheck_en_get() { return this->get_field(HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_BIT, HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_WIDTH); } + inline void cs_max_set(uint32_t value) { this->set_field(value, HYPER_TIMING_CFG_CS_MAX_BIT, HYPER_TIMING_CFG_CS_MAX_WIDTH); } + inline uint32_t cs_max_get() { return this->get_field(HYPER_TIMING_CFG_CS_MAX_BIT, HYPER_TIMING_CFG_CS_MAX_WIDTH); } +}; + +class vp_hyper_mba0 : public vp::reg_32 +{ +public: + inline void mba0_set(uint32_t value) { this->set_field(value, HYPER_MBA0_MBA0_BIT, HYPER_MBA0_MBA0_WIDTH); } + inline uint32_t mba0_get() { return this->get_field(HYPER_MBA0_MBA0_BIT, HYPER_MBA0_MBA0_WIDTH); } +}; + +class vp_hyper_mba1 : public vp::reg_32 +{ +public: + inline void mba1_set(uint32_t value) { this->set_field(value, HYPER_MBA1_MBA1_BIT, HYPER_MBA1_MBA1_WIDTH); } + inline uint32_t mba1_get() { return this->get_field(HYPER_MBA1_MBA1_BIT, HYPER_MBA1_MBA1_WIDTH); } +}; + +class vp_hyper_device : public vp::reg_32 +{ +public: + inline void type_set(uint32_t value) { this->set_field(value, HYPER_DEVICE_TYPE_BIT, HYPER_DEVICE_TYPE_WIDTH); } + inline uint32_t type_get() { return this->get_field(HYPER_DEVICE_TYPE_BIT, HYPER_DEVICE_TYPE_WIDTH); } + inline void dt0_set(uint32_t value) { this->set_field(value, HYPER_DEVICE_DT0_BIT, HYPER_DEVICE_DT0_WIDTH); } + inline uint32_t dt0_get() { return this->get_field(HYPER_DEVICE_DT0_BIT, HYPER_DEVICE_DT0_WIDTH); } + inline void dt1_set(uint32_t value) { this->set_field(value, HYPER_DEVICE_DT1_BIT, HYPER_DEVICE_DT1_WIDTH); } + inline uint32_t dt1_get() { return this->get_field(HYPER_DEVICE_DT1_BIT, HYPER_DEVICE_DT1_WIDTH); } +}; + +class vp_hyper_ospi_cmd : public vp::reg_16 +{ +public: +}; + +class vp_hyper_ospi_addr : public vp::reg_32 +{ +public: +}; + +class vp_hyper_ospi_cfg : public vp::reg_32 +{ +public: + inline void cmd_size_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CFG_CMD_SIZE_BIT, HYPER_OSPI_CFG_CMD_SIZE_WIDTH); } + inline uint32_t cmd_size_get() { return this->get_field(HYPER_OSPI_CFG_CMD_SIZE_BIT, HYPER_OSPI_CFG_CMD_SIZE_WIDTH); } + inline void addr_size_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CFG_ADDR_SIZE_BIT, HYPER_OSPI_CFG_ADDR_SIZE_WIDTH); } + inline uint32_t addr_size_get() { return this->get_field(HYPER_OSPI_CFG_ADDR_SIZE_BIT, HYPER_OSPI_CFG_ADDR_SIZE_WIDTH); } + inline void line_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CFG_LINE_BIT, HYPER_OSPI_CFG_LINE_WIDTH); } + inline uint32_t line_get() { return this->get_field(HYPER_OSPI_CFG_LINE_BIT, HYPER_OSPI_CFG_LINE_WIDTH); } + inline void cmd_dtr_str_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CFG_CMD_DTR_STR_BIT, HYPER_OSPI_CFG_CMD_DTR_STR_WIDTH); } + inline uint32_t cmd_dtr_str_get() { return this->get_field(HYPER_OSPI_CFG_CMD_DTR_STR_BIT, HYPER_OSPI_CFG_CMD_DTR_STR_WIDTH); } + inline void addr_dtr_str_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CFG_ADDR_DTR_STR_BIT, HYPER_OSPI_CFG_ADDR_DTR_STR_WIDTH); } + inline uint32_t addr_dtr_str_get() { return this->get_field(HYPER_OSPI_CFG_ADDR_DTR_STR_BIT, HYPER_OSPI_CFG_ADDR_DTR_STR_WIDTH); } + inline void data_dtr_str_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CFG_DATA_DTR_STR_BIT, HYPER_OSPI_CFG_DATA_DTR_STR_WIDTH); } + inline uint32_t data_dtr_str_get() { return this->get_field(HYPER_OSPI_CFG_DATA_DTR_STR_BIT, HYPER_OSPI_CFG_DATA_DTR_STR_WIDTH); } + inline void data_dtr_msb_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CFG_DATA_DTR_MSB_BIT, HYPER_OSPI_CFG_DATA_DTR_MSB_WIDTH); } + inline uint32_t data_dtr_msb_get() { return this->get_field(HYPER_OSPI_CFG_DATA_DTR_MSB_BIT, HYPER_OSPI_CFG_DATA_DTR_MSB_WIDTH); } +}; + +class vp_hyper_ospi_csn : public vp::reg_32 +{ +public: + inline void index_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CSN_INDEX_BIT, HYPER_OSPI_CSN_INDEX_WIDTH); } + inline uint32_t index_get() { return this->get_field(HYPER_OSPI_CSN_INDEX_BIT, HYPER_OSPI_CSN_INDEX_WIDTH); } + inline void user_ctrl_csn_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CSN_USER_CTRL_CSN_BIT, HYPER_OSPI_CSN_USER_CTRL_CSN_WIDTH); } + inline uint32_t user_ctrl_csn_get() { return this->get_field(HYPER_OSPI_CSN_USER_CTRL_CSN_BIT, HYPER_OSPI_CSN_USER_CTRL_CSN_WIDTH); } + inline void csn_val_set(uint32_t value) { this->set_field(value, HYPER_OSPI_CSN_CSN_VAL_BIT, HYPER_OSPI_CSN_CSN_VAL_WIDTH); } + inline uint32_t csn_val_get() { return this->get_field(HYPER_OSPI_CSN_CSN_VAL_BIT, HYPER_OSPI_CSN_CSN_VAL_WIDTH); } +}; + +class vp_hyper__reserved0 : public vp::reg_32 +{ +public: +}; + +class vp_hyper__reserved1 : public vp::reg_32 +{ +public: +}; + +class vp_hyper_irq_en : public vp::reg_32 +{ +public: + inline void en_set(uint32_t value) { this->set_field(value, HYPER_IRQ_EN_EN_BIT, HYPER_IRQ_EN_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(HYPER_IRQ_EN_EN_BIT, HYPER_IRQ_EN_EN_WIDTH); } +}; + +class vp_hyper_clk_div : public vp::reg_32 +{ +public: + inline void data_set(uint32_t value) { this->set_field(value, HYPER_CLK_DIV_DATA_BIT, HYPER_CLK_DIV_DATA_WIDTH); } + inline uint32_t data_get() { return this->get_field(HYPER_CLK_DIV_DATA_BIT, HYPER_CLK_DIV_DATA_WIDTH); } + inline void valid_set(uint32_t value) { this->set_field(value, HYPER_CLK_DIV_VALID_BIT, HYPER_CLK_DIV_VALID_WIDTH); } + inline uint32_t valid_get() { return this->get_field(HYPER_CLK_DIV_VALID_BIT, HYPER_CLK_DIV_VALID_WIDTH); } +}; + +class vp_hyper_status : public vp::reg_32 +{ +public: + inline void tx_error_set(uint32_t value) { this->set_field(value, HYPER_STATUS_TX_ERROR_BIT, HYPER_STATUS_TX_ERROR_WIDTH); } + inline uint32_t tx_error_get() { return this->get_field(HYPER_STATUS_TX_ERROR_BIT, HYPER_STATUS_TX_ERROR_WIDTH); } + inline void rx_error_set(uint32_t value) { this->set_field(value, HYPER_STATUS_RX_ERROR_BIT, HYPER_STATUS_RX_ERROR_WIDTH); } + inline uint32_t rx_error_get() { return this->get_field(HYPER_STATUS_RX_ERROR_BIT, HYPER_STATUS_RX_ERROR_WIDTH); } + inline void rx_tx_end_set(uint32_t value) { this->set_field(value, HYPER_STATUS_RX_TX_END_BIT, HYPER_STATUS_RX_TX_END_WIDTH); } + inline uint32_t rx_tx_end_get() { return this->get_field(HYPER_STATUS_RX_TX_END_BIT, HYPER_STATUS_RX_TX_END_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int rx_saddr ; // uDMA RX HYPERBUS buffer base address configuration register. + unsigned int rx_size ; // uDMA RX HYPERBUS buffer size configuration register. + unsigned int rx_cfg ; // uDMA RX HYPERBUS stream configuration register. + unsigned int tx_saddr ; // uDMA TX HYPERBUS buffer base address configuration register. + unsigned int tx_size ; // uDMA TX HYPERBUS buffer size configuration register. + unsigned int tx_cfg ; // uDMA TX HYPERBUS stream configuration register. + unsigned int ext_addr ; // Memory access address register. + unsigned int timing_cfg ; // HYPERBUS and Octo SPI Memory Timing configuration register. + unsigned int mba0 ; // Device start address register. + unsigned int mba1 ; // Device start address register. + unsigned int device ; // Device type register(RAM or FLASH). + unsigned int ospi_cmd ; // OSPI command + unsigned int ospi_addr ; // OSPI address + unsigned int ospi_cfg ; // OSPI configuration + unsigned int ospi_csn ; // OSPI chip select configuration + unsigned int _reserved0 ; // - + unsigned int _reserved1 ; // - + unsigned int irq_en ; // OSPI interrupt enable register + unsigned int clk_div ; // Clock divide. + unsigned int status ; // Transfer status for error. +} __attribute__((packed)) hyper_hyper_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t hyper_rx_saddr_get(uint32_t base) { return ARCHI_READ(base, HYPER_RX_SADDR_OFFSET); } +static inline void hyper_rx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_RX_SADDR_OFFSET, value); } + +static inline uint32_t hyper_rx_size_get(uint32_t base) { return ARCHI_READ(base, HYPER_RX_SIZE_OFFSET); } +static inline void hyper_rx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_RX_SIZE_OFFSET, value); } + +static inline uint32_t hyper_rx_cfg_get(uint32_t base) { return ARCHI_READ(base, HYPER_RX_CFG_OFFSET); } +static inline void hyper_rx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_RX_CFG_OFFSET, value); } + +static inline uint32_t hyper_tx_saddr_get(uint32_t base) { return ARCHI_READ(base, HYPER_TX_SADDR_OFFSET); } +static inline void hyper_tx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_TX_SADDR_OFFSET, value); } + +static inline uint32_t hyper_tx_size_get(uint32_t base) { return ARCHI_READ(base, HYPER_TX_SIZE_OFFSET); } +static inline void hyper_tx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_TX_SIZE_OFFSET, value); } + +static inline uint32_t hyper_tx_cfg_get(uint32_t base) { return ARCHI_READ(base, HYPER_TX_CFG_OFFSET); } +static inline void hyper_tx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_TX_CFG_OFFSET, value); } + +static inline uint32_t hyper_ext_addr_get(uint32_t base) { return ARCHI_READ(base, HYPER_EXT_ADDR_OFFSET); } +static inline void hyper_ext_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_EXT_ADDR_OFFSET, value); } + +static inline uint32_t hyper_timing_cfg_get(uint32_t base) { return ARCHI_READ(base, HYPER_TIMING_CFG_OFFSET); } +static inline void hyper_timing_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_TIMING_CFG_OFFSET, value); } + +static inline uint32_t hyper_mba0_get(uint32_t base) { return ARCHI_READ(base, HYPER_MBA0_OFFSET); } +static inline void hyper_mba0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_MBA0_OFFSET, value); } + +static inline uint32_t hyper_mba1_get(uint32_t base) { return ARCHI_READ(base, HYPER_MBA1_OFFSET); } +static inline void hyper_mba1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_MBA1_OFFSET, value); } + +static inline uint32_t hyper_device_get(uint32_t base) { return ARCHI_READ(base, HYPER_DEVICE_OFFSET); } +static inline void hyper_device_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_DEVICE_OFFSET, value); } + +static inline uint32_t hyper_ospi_cmd_get(uint32_t base) { return ARCHI_READ(base, HYPER_OSPI_CMD_OFFSET); } +static inline void hyper_ospi_cmd_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_OSPI_CMD_OFFSET, value); } + +static inline uint32_t hyper_ospi_addr_get(uint32_t base) { return ARCHI_READ(base, HYPER_OSPI_ADDR_OFFSET); } +static inline void hyper_ospi_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_OSPI_ADDR_OFFSET, value); } + +static inline uint32_t hyper_ospi_cfg_get(uint32_t base) { return ARCHI_READ(base, HYPER_OSPI_CFG_OFFSET); } +static inline void hyper_ospi_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_OSPI_CFG_OFFSET, value); } + +static inline uint32_t hyper_ospi_csn_get(uint32_t base) { return ARCHI_READ(base, HYPER_OSPI_CSN_OFFSET); } +static inline void hyper_ospi_csn_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_OSPI_CSN_OFFSET, value); } + +static inline uint32_t hyper__reserved0_get(uint32_t base) { return ARCHI_READ(base, HYPER__RESERVED0_OFFSET); } +static inline void hyper__reserved0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER__RESERVED0_OFFSET, value); } + +static inline uint32_t hyper__reserved1_get(uint32_t base) { return ARCHI_READ(base, HYPER__RESERVED1_OFFSET); } +static inline void hyper__reserved1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER__RESERVED1_OFFSET, value); } + +static inline uint32_t hyper_irq_en_get(uint32_t base) { return ARCHI_READ(base, HYPER_IRQ_EN_OFFSET); } +static inline void hyper_irq_en_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_IRQ_EN_OFFSET, value); } + +static inline uint32_t hyper_clk_div_get(uint32_t base) { return ARCHI_READ(base, HYPER_CLK_DIV_OFFSET); } +static inline void hyper_clk_div_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_CLK_DIV_OFFSET, value); } + +static inline uint32_t hyper_status_get(uint32_t base) { return ARCHI_READ(base, HYPER_STATUS_OFFSET); } +static inline void hyper_status_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, HYPER_STATUS_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define HYPER_RX_SADDR_RX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define HYPER_RX_SADDR_RX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define HYPER_RX_SADDR_RX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define HYPER_RX_SADDR_RX_SADDR(val) ((val) << 0) + +#define HYPER_RX_SIZE_RX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define HYPER_RX_SIZE_RX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define HYPER_RX_SIZE_RX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define HYPER_RX_SIZE_RX_SIZE(val) ((val) << 0) + +#define HYPER_RX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define HYPER_RX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define HYPER_RX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define HYPER_RX_CFG_CONTINOUS(val) ((val) << 0) + +#define HYPER_RX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define HYPER_RX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define HYPER_RX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define HYPER_RX_CFG_EN(val) ((val) << 4) + +#define HYPER_RX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define HYPER_RX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define HYPER_RX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define HYPER_RX_CFG_PENDING(val) ((val) << 5) + +#define HYPER_RX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define HYPER_RX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define HYPER_RX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define HYPER_RX_CFG_CLR(val) ((val) << 6) + +#define HYPER_TX_SADDR_TX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define HYPER_TX_SADDR_TX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define HYPER_TX_SADDR_TX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define HYPER_TX_SADDR_TX_SADDR(val) ((val) << 0) + +#define HYPER_TX_SIZE_TX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define HYPER_TX_SIZE_TX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define HYPER_TX_SIZE_TX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define HYPER_TX_SIZE_TX_SIZE(val) ((val) << 0) + +#define HYPER_TX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define HYPER_TX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define HYPER_TX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define HYPER_TX_CFG_CONTINOUS(val) ((val) << 0) + +#define HYPER_TX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define HYPER_TX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define HYPER_TX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define HYPER_TX_CFG_EN(val) ((val) << 4) + +#define HYPER_TX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define HYPER_TX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define HYPER_TX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define HYPER_TX_CFG_PENDING(val) ((val) << 5) + +#define HYPER_TX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define HYPER_TX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define HYPER_TX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define HYPER_TX_CFG_CLR(val) ((val) << 6) + +#define HYPER_EXT_ADDR_SADDR_GET(value) (ARCHI_BEXTRACTU((value),31,0)) +#define HYPER_EXT_ADDR_SADDR_GETS(value) (ARCHI_BEXTRACT((value),31,0)) +#define HYPER_EXT_ADDR_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),31,0)) +#define HYPER_EXT_ADDR_SADDR(val) ((val) << 0) + +#define HYPER_EXT_ADDR_REG_ACCESS_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define HYPER_EXT_ADDR_REG_ACCESS_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define HYPER_EXT_ADDR_REG_ACCESS_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define HYPER_EXT_ADDR_REG_ACCESS(val) ((val) << 31) + +#define HYPER_TIMING_CFG_LATENCY0_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define HYPER_TIMING_CFG_LATENCY0_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define HYPER_TIMING_CFG_LATENCY0_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define HYPER_TIMING_CFG_LATENCY0(val) ((val) << 0) + +#define HYPER_TIMING_CFG_LATENCY1_GET(value) (ARCHI_BEXTRACTU((value),5,5)) +#define HYPER_TIMING_CFG_LATENCY1_GETS(value) (ARCHI_BEXTRACT((value),5,5)) +#define HYPER_TIMING_CFG_LATENCY1_SET(value,field) (ARCHI_BINSERT((value),(field),5,5)) +#define HYPER_TIMING_CFG_LATENCY1(val) ((val) << 5) + +#define HYPER_TIMING_CFG_RW_RECOVERY_GET(value) (ARCHI_BEXTRACTU((value),4,10)) +#define HYPER_TIMING_CFG_RW_RECOVERY_GETS(value) (ARCHI_BEXTRACT((value),4,10)) +#define HYPER_TIMING_CFG_RW_RECOVERY_SET(value,field) (ARCHI_BINSERT((value),(field),4,10)) +#define HYPER_TIMING_CFG_RW_RECOVERY(val) ((val) << 10) + +#define HYPER_TIMING_CFG_RWDS_DELAY_GET(value) (ARCHI_BEXTRACTU((value),3,14)) +#define HYPER_TIMING_CFG_RWDS_DELAY_GETS(value) (ARCHI_BEXTRACT((value),3,14)) +#define HYPER_TIMING_CFG_RWDS_DELAY_SET(value,field) (ARCHI_BINSERT((value),(field),3,14)) +#define HYPER_TIMING_CFG_RWDS_DELAY(val) ((val) << 14) + +#define HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN(val) ((val) << 17) + +#define HYPER_TIMING_CFG_CS_MAX_GET(value) (ARCHI_BEXTRACTU((value),16,18)) +#define HYPER_TIMING_CFG_CS_MAX_GETS(value) (ARCHI_BEXTRACT((value),16,18)) +#define HYPER_TIMING_CFG_CS_MAX_SET(value,field) (ARCHI_BINSERT((value),(field),16,18)) +#define HYPER_TIMING_CFG_CS_MAX(val) ((val) << 18) + +#define HYPER_MBA0_MBA0_GET(value) (ARCHI_BEXTRACTU((value),7,24)) +#define HYPER_MBA0_MBA0_GETS(value) (ARCHI_BEXTRACT((value),7,24)) +#define HYPER_MBA0_MBA0_SET(value,field) (ARCHI_BINSERT((value),(field),7,24)) +#define HYPER_MBA0_MBA0(val) ((val) << 24) + +#define HYPER_MBA1_MBA1_GET(value) (ARCHI_BEXTRACTU((value),7,24)) +#define HYPER_MBA1_MBA1_GETS(value) (ARCHI_BEXTRACT((value),7,24)) +#define HYPER_MBA1_MBA1_SET(value,field) (ARCHI_BINSERT((value),(field),7,24)) +#define HYPER_MBA1_MBA1(val) ((val) << 24) + +#define HYPER_DEVICE_TYPE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define HYPER_DEVICE_TYPE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define HYPER_DEVICE_TYPE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define HYPER_DEVICE_TYPE(val) ((val) << 0) + +#define HYPER_DEVICE_DT0_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define HYPER_DEVICE_DT0_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define HYPER_DEVICE_DT0_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define HYPER_DEVICE_DT0(val) ((val) << 1) + +#define HYPER_DEVICE_DT1_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define HYPER_DEVICE_DT1_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define HYPER_DEVICE_DT1_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define HYPER_DEVICE_DT1(val) ((val) << 2) + +#define HYPER_OSPI_CFG_CMD_SIZE_GET(value) (ARCHI_BEXTRACTU((value),2,0)) +#define HYPER_OSPI_CFG_CMD_SIZE_GETS(value) (ARCHI_BEXTRACT((value),2,0)) +#define HYPER_OSPI_CFG_CMD_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,0)) +#define HYPER_OSPI_CFG_CMD_SIZE(val) ((val) << 0) + +#define HYPER_OSPI_CFG_ADDR_SIZE_GET(value) (ARCHI_BEXTRACTU((value),3,4)) +#define HYPER_OSPI_CFG_ADDR_SIZE_GETS(value) (ARCHI_BEXTRACT((value),3,4)) +#define HYPER_OSPI_CFG_ADDR_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),3,4)) +#define HYPER_OSPI_CFG_ADDR_SIZE(val) ((val) << 4) + +#define HYPER_OSPI_CFG_LINE_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define HYPER_OSPI_CFG_LINE_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define HYPER_OSPI_CFG_LINE_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define HYPER_OSPI_CFG_LINE(val) ((val) << 8) + +#define HYPER_OSPI_CFG_CMD_DTR_STR_GET(value) (ARCHI_BEXTRACTU((value),1,12)) +#define HYPER_OSPI_CFG_CMD_DTR_STR_GETS(value) (ARCHI_BEXTRACT((value),1,12)) +#define HYPER_OSPI_CFG_CMD_DTR_STR_SET(value,field) (ARCHI_BINSERT((value),(field),1,12)) +#define HYPER_OSPI_CFG_CMD_DTR_STR(val) ((val) << 12) + +#define HYPER_OSPI_CFG_ADDR_DTR_STR_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define HYPER_OSPI_CFG_ADDR_DTR_STR_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define HYPER_OSPI_CFG_ADDR_DTR_STR_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define HYPER_OSPI_CFG_ADDR_DTR_STR(val) ((val) << 13) + +#define HYPER_OSPI_CFG_DATA_DTR_STR_GET(value) (ARCHI_BEXTRACTU((value),1,14)) +#define HYPER_OSPI_CFG_DATA_DTR_STR_GETS(value) (ARCHI_BEXTRACT((value),1,14)) +#define HYPER_OSPI_CFG_DATA_DTR_STR_SET(value,field) (ARCHI_BINSERT((value),(field),1,14)) +#define HYPER_OSPI_CFG_DATA_DTR_STR(val) ((val) << 14) + +#define HYPER_OSPI_CFG_DATA_DTR_MSB_GET(value) (ARCHI_BEXTRACTU((value),1,15)) +#define HYPER_OSPI_CFG_DATA_DTR_MSB_GETS(value) (ARCHI_BEXTRACT((value),1,15)) +#define HYPER_OSPI_CFG_DATA_DTR_MSB_SET(value,field) (ARCHI_BINSERT((value),(field),1,15)) +#define HYPER_OSPI_CFG_DATA_DTR_MSB(val) ((val) << 15) + +#define HYPER_OSPI_CSN_INDEX_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define HYPER_OSPI_CSN_INDEX_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define HYPER_OSPI_CSN_INDEX_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define HYPER_OSPI_CSN_INDEX(val) ((val) << 0) + +#define HYPER_OSPI_CSN_USER_CTRL_CSN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define HYPER_OSPI_CSN_USER_CTRL_CSN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define HYPER_OSPI_CSN_USER_CTRL_CSN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define HYPER_OSPI_CSN_USER_CTRL_CSN(val) ((val) << 4) + +#define HYPER_OSPI_CSN_CSN_VAL_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define HYPER_OSPI_CSN_CSN_VAL_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define HYPER_OSPI_CSN_CSN_VAL_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define HYPER_OSPI_CSN_CSN_VAL(val) ((val) << 5) + +#define HYPER_IRQ_EN_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define HYPER_IRQ_EN_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define HYPER_IRQ_EN_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define HYPER_IRQ_EN_EN(val) ((val) << 0) + +#define HYPER_CLK_DIV_DATA_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define HYPER_CLK_DIV_DATA_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define HYPER_CLK_DIV_DATA_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define HYPER_CLK_DIV_DATA(val) ((val) << 0) + +#define HYPER_CLK_DIV_VALID_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define HYPER_CLK_DIV_VALID_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define HYPER_CLK_DIV_VALID_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define HYPER_CLK_DIV_VALID(val) ((val) << 8) + +#define HYPER_STATUS_TX_ERROR_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define HYPER_STATUS_TX_ERROR_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define HYPER_STATUS_TX_ERROR_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define HYPER_STATUS_TX_ERROR(val) ((val) << 0) + +#define HYPER_STATUS_RX_ERROR_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define HYPER_STATUS_RX_ERROR_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define HYPER_STATUS_RX_ERROR_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define HYPER_STATUS_RX_ERROR(val) ((val) << 1) + +#define HYPER_STATUS_RX_TX_END_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define HYPER_STATUS_RX_TX_END_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define HYPER_STATUS_RX_TX_END_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define HYPER_STATUS_RX_TX_END(val) ((val) << 2) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2c/udma_i2c_v1.h b/sw/pulp-sdk/archi/include/archi/udma/i2c/udma_i2c_v1.h new file mode 100644 index 0000000..ac7b90f --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2c/udma_i2c_v1.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_I2C_V1_H__ +#define __ARCHI_UDMA_UDMA_I2C_V1_H__ + +#define ARCHI_I2C_SETUP_OFFSET 0x0 + +#define I2C_CMD_START 0x02 +#define I2C_CMD_STOP 0x04 +#define I2C_CMD_RD_ACK 0x08 +#define I2C_CMD_RD_NACK 0x10 +#define I2C_CMD_WR 0x20 +#define I2C_CMD_WAIT 0x40 +#define I2C_CMD_RPT 0x80 + +#define I2C_CMD_SETUP_ENABLE_BIT 8 +#define I2C_CMD_SETUP_DIV_BIT 16 + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2c/udma_i2c_v2.h b/sw/pulp-sdk/archi/include/archi/udma/i2c/udma_i2c_v2.h new file mode 100644 index 0000000..f148255 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2c/udma_i2c_v2.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_I2C_V2_H__ +#define __ARCHI_UDMA_UDMA_I2C_V2_H__ + +// I2C command IDS definition +#define I2C_CMD_OFFSET 4 +#define I2C_CMD_START (0x0 << I2C_CMD_OFFSET) +#define I2C_CMD_STOP (0x2 << I2C_CMD_OFFSET) +#define I2C_CMD_RD_ACK (0x4 << I2C_CMD_OFFSET) +#define I2C_CMD_RD_NACK (0x6 << I2C_CMD_OFFSET) +#define I2C_CMD_WR (0x8 << I2C_CMD_OFFSET) +#define I2C_CMD_WAIT (0xA << I2C_CMD_OFFSET) +#define I2C_CMD_RPT (0xC << I2C_CMD_OFFSET) +#define I2C_CMD_CFG (0xE << I2C_CMD_OFFSET) +#define I2C_CMD_WAIT_EV (0x1 << I2C_CMD_OFFSET) + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v1.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v1.h new file mode 100644 index 0000000..bbf18e0 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v1.h @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_I2S_V1_H__ +#define __ARCHI_UDMA_UDMA_I2S_V1_H__ + +#include "archi/udma/udma_v2.h" + +#define UDMA_I2S_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_I2S_OFFSET(id)) //FIXME shall be removed because deprecated +#define UDMA_I2S_RX0_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_I2S_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_I2S_RX1_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_I2S_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET) +#define UDMA_I2S_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_I2S_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) + + +#define UDMA_I2S_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_I2S_ID(id)) + +// I2S custom registers offset definition +#define I2S_EXT_OFFSET (0x00) +#define I2S_CFG_CLKGEN0_OFFSET (0x04) +#define I2S_CFG_CLKGEN1_OFFSET (0x08) +#define I2S_CFG_CLKGEN_OFFSET(clk) (I2S_CFG_CLKGEN0_OFFSET + (clk)*4) +#define I2S_CHMODE_OFFSET (0x0C) +#define I2S_FILT_CH0_OFFSET (0x10) +#define I2S_FILT_CH1_OFFSET (0x14) +#define I2S_FILT_CH_OFFSET(clk) (I2S_FILT_CH0_OFFSET + (clk)*4) + +// I2S custom registers bitfields offset, mask, value definition +#define I2S_EXT_BITS_WORD_OFFSET 0 +#define I2S_EXT_BITS_WORD_WIDTH 5 +#define I2S_EXT_BITS_WORD_MASK (0x1f << I2S_EXT_BITS_WORD_OFFSET) +#define I2S_EXT_BITS_WORD(val) ((val-1) << I2S_EXT_BITS_WORD_OFFSET) + + +#define I2S_CFG_CLKGEN_BITS_WORD_OFFSET 0 +#define I2S_CFG_CLKGEN_BITS_WORD_WIDTH 5 +#define I2S_CFG_CLKGEN_BITS_WORD_MASK (0x1f << I2S_CFG_CLKGEN_BITS_WORD_OFFSET) +#define I2S_CFG_CLKGEN_BITS_WORD(val) ((val-1) << I2S_CFG_CLKGEN_BITS_WORD_OFFSET) + +#define I2S_CFG_CLKGEN_CLK_EN_OFFSET 8 +#define I2S_CFG_CLKGEN_CLK_EN_WIDTH 1 +#define I2S_CFG_CLKGEN_CLK_EN_MASK (0x1 << I2S_CFG_CLKGEN_CLK_EN_OFFSET) +#define I2S_CFG_CLKGEN_CLK_EN (1 << I2S_CFG_CLKGEN_CLK_EN_OFFSET) +#define I2S_CFG_CLKGEN_CLK_DIS (0 << I2S_CFG_CLKGEN_CLK_EN_OFFSET) + +#define I2S_CFG_CLKGEN_CLKDIV_OFFSET 16 +#define I2S_CFG_CLKGEN_CLKDIV_WIDTH 16 +#define I2S_CFG_CLKGEN_CLKDIV_MASK (0xffff << I2S_CFG_CLKGEN_CLKDIV_OFFSET) +#define I2S_CFG_CLKGEN_CLKDIV(val) (val << I2S_CFG_CLKGEN_CLKDIV_OFFSET) + + +#define I2S_CFG_CLKGEN0_BITS_WORD_OFFSET 0 +#define I2S_CFG_CLKGEN0_BITS_WORD_WIDTH 5 +#define I2S_CFG_CLKGEN0_BITS_WORD_MASK (0x1f << I2S_CFG_CLKGEN0_BITS_WORD_OFFSET) +#define I2S_CFG_CLKGEN0_BITS_WORD(val) ((val-1) << I2S_CFG_CLKGEN0_BITS_WORD_OFFSET) + +#define I2S_CFG_CLKGEN0_CLK_EN_OFFSET 8 +#define I2S_CFG_CLKGEN0_CLK_EN_WIDTH 1 +#define I2S_CFG_CLKGEN0_CLK_EN_MASK (0x1 << I2S_CFG_CLKGEN0_CLK_EN_OFFSET) +#define I2S_CFG_CLKGEN0_CLK_EN (1 << I2S_CFG_CLKGEN0_CLK_EN_OFFSET) +#define I2S_CFG_CLKGEN0_CLK_DIS (0 << I2S_CFG_CLKGEN0_CLK_EN_OFFSET) + +#define I2S_CFG_CLKGEN0_CLKDIV_OFFSET 16 +#define I2S_CFG_CLKGEN0_CLKDIV_WIDTH 16 +#define I2S_CFG_CLKGEN0_CLKDIV_MASK (0xffff << I2S_CFG_CLKGEN0_CLKDIV_OFFSET) +#define I2S_CFG_CLKGEN0_CLKDIV(val) (val << I2S_CFG_CLKGEN0_CLKDIV_OFFSET) + +#define I2S_CFG_CLKGEN1_BITS_WORD_OFFSET 0 +#define I2S_CFG_CLKGEN1_BITS_WORD_WIDTH 5 +#define I2S_CFG_CLKGEN1_BITS_WORD_MASK (0x1f << I2S_CFG_CLKGEN1_BITS_WORD_OFFSET) +#define I2S_CFG_CLKGEN1_BITS_WORD(val) ((val-1) << I2S_CFG_CLKGEN1_BITS_WORD_OFFSET) + +#define I2S_CFG_CLKGEN1_CLK_EN_OFFSET 8 +#define I2S_CFG_CLKGEN1_CLK_EN_WIDTH 1 +#define I2S_CFG_CLKGEN1_CLK_EN_MASK (0x1 << I2S_CFG_CLKGEN1_CLK_EN_OFFSET) +#define I2S_CFG_CLKGEN1_CLK_EN (1 << I2S_CFG_CLKGEN1_CLK_EN_OFFSET) +#define I2S_CFG_CLKGEN1_CLK_DIS (0 << I2S_CFG_CLKGEN1_CLK_EN_OFFSET) + +#define I2S_CFG_CLKGEN1_CLKDIV_OFFSET 16 +#define I2S_CFG_CLKGEN1_CLKDIV_WIDTH 16 +#define I2S_CFG_CLKGEN1_CLKDIV_MASK (0xffff << I2S_CFG_CLKGEN1_CLKDIV_OFFSET) +#define I2S_CFG_CLKGEN1_CLKDIV(val) (val << I2S_CFG_CLKGEN1_CLKDIV_OFFSET) + + + +#define I2S_CHMODE_CH_SNAPCAM_OFFSET(x) (0 + (x)) +#define I2S_CHMODE_CH_SNAPCAM_WIDTH(x) (1) +#define I2S_CHMODE_CH_SNAPCAM_MASK(x) (0x1 << I2S_CHMODE_CH_SNAPCAM_OFFSET(x)) +#define I2S_CHMODE_CH_SNAPCAM_ENA(x) (0x1 << I2S_CHMODE_CH_SNAPCAM_OFFSET(x)) +#define I2S_CHMODE_CH_SNAPCAM_DIS(x) (0x0 << I2S_CHMODE_CH_SNAPCAM_OFFSET(x)) + +#define I2S_CHMODE_CH_LSBFIRST_OFFSET(x) (4 + (x)) +#define I2S_CHMODE_CH_LSBFIRST_WIDTH(x) (1) +#define I2S_CHMODE_CH_LSBFIRST_MASK(x) (0x1 << I2S_CHMODE_CH_LSBFIRST_OFFSET(x)) +#define I2S_CHMODE_CH_LSBFIRST_ENA(x) (1 << I2S_CHMODE_CH_LSBFIRST_OFFSET(x)) +#define I2S_CHMODE_CH_LSBFIRST_DIS(x) (0 << I2S_CHMODE_CH_LSBFIRST_OFFSET(x)) + +#define I2S_CHMODE_CH_PDM_USEFILTER_OFFSET(x) (8 + (x)) +#define I2S_CHMODE_CH_PDM_USEFILTER_WIDTH(x) (1) +#define I2S_CHMODE_CH_PDM_USEFILTER_MASK(x) (0x1 << I2S_CHMODE_CH_PDM_USEFILTER_OFFSET(x)) +#define I2S_CHMODE_CH_PDM_USEFILTER_ENA(x) (1 << I2S_CHMODE_CH_PDM_USEFILTER_OFFSET(x)) +#define I2S_CHMODE_CH_PDM_USEFILTER_DIS(x) (0 << I2S_CHMODE_CH_PDM_USEFILTER_OFFSET(x)) + +#define I2S_CHMODE_CH_PDM_EN_OFFSET(x) (12 + (x)) +#define I2S_CHMODE_CH_PDM_EN_WIDTH(x) (1) +#define I2S_CHMODE_CH_PDM_EN_MASK(x) (0x1 << I2S_CHMODE_CH_PDM_EN_OFFSET(x)) +#define I2S_CHMODE_CH_PDM_EN_ENA(x) (1 << I2S_CHMODE_CH_PDM_EN_OFFSET(x)) +#define I2S_CHMODE_CH_PDM_EN_DIS(x) (0 << I2S_CHMODE_CH_PDM_EN_OFFSET(x)) + +#define I2S_CHMODE_CH_USEDDR_OFFSET(x) (16 + (x)) +#define I2S_CHMODE_CH_USEDDR_WIDTH(x) (1) +#define I2S_CHMODE_CH_USEDDR_MASK(x) (0x1 << I2S_CHMODE_CH_USEDDR_OFFSET(x)) +#define I2S_CHMODE_CH_USEDDR_ENA(x) (1 << I2S_CHMODE_CH_USEDDR_OFFSET(x)) +#define I2S_CHMODE_CH_USEDDR_DIS(x) (0 << I2S_CHMODE_CH_USEDDR_OFFSET(x)) + +#define I2S_CHMODE_CH_MODE_OFFSET(x) (24 + (x*2)) +#define I2S_CHMODE_CH_MODE_WIDTH(x) (2) +#define I2S_CHMODE_CH_MODE_MASK(x) (0x3 << I2S_CHMODE_CH_MODE_OFFSET(x)) +#define I2S_CHMODE_CH_MODE_CLK(x,clk) (clk << I2S_CHMODE_CH_MODE_OFFSET(x)) +#define I2S_CHMODE_CH_MODE_EXTCLK_INTWS(x) (2 << I2S_CHMODE_CH_MODE_OFFSET(x)) +#define I2S_CHMODE_CH_MODE_EXTCLK_EXTWS(x) (2 << I2S_CHMODE_CH_MODE_OFFSET(x)) + + + +#define I2S_CHMODE_CH0_SNAPCAM_OFFSET 0 +#define I2S_CHMODE_CH0_SNAPCAM_WIDTH 1 +#define I2S_CHMODE_CH0_SNAPCAM_MASK (0x1 << I2S_CHMODE_CH0_SNAPCAM_OFFSET) +#define I2S_CHMODE_CH0_SNAPCAM_ENA (0x1 << I2S_CHMODE_CH0_SNAPCAM_OFFSET) +#define I2S_CHMODE_CH0_SNAPCAM_DIS (0x0 << I2S_CHMODE_CH0_SNAPCAM_OFFSET) + +#define I2S_CHMODE_CH0_LSBFIRST_OFFSET 4 +#define I2S_CHMODE_CH0_LSBFIRST_WIDTH 1 +#define I2S_CHMODE_CH0_LSBFIRST_MASK (0x1 << I2S_CHMODE_CH0_LSBFIRST_OFFSET) +#define I2S_CHMODE_CH0_LSBFIRST_ENA (1 << I2S_CHMODE_CH0_LSBFIRST_OFFSET) +#define I2S_CHMODE_CH0_LSBFIRST_DIS (0 << I2S_CHMODE_CH0_LSBFIRST_OFFSET) + +#define I2S_CHMODE_CH0_PDM_USEFILTER_OFFSET 8 +#define I2S_CHMODE_CH0_PDM_USEFILTER_WIDTH 1 +#define I2S_CHMODE_CH0_PDM_USEFILTER_MASK (0x1 << I2S_CHMODE_CH0_PDM_USEFILTER_OFFSET) +#define I2S_CHMODE_CH0_PDM_USEFILTER_ENA (1 << I2S_CHMODE_CH0_PDM_USEFILTER_OFFSET) +#define I2S_CHMODE_CH0_PDM_USEFILTER_DIS (0 << I2S_CHMODE_CH0_PDM_USEFILTER_OFFSET) + +#define I2S_CHMODE_CH0_PDM_EN_OFFSET 12 +#define I2S_CHMODE_CH0_PDM_EN_WIDTH 1 +#define I2S_CHMODE_CH0_PDM_EN_MASK (0x1 << I2S_CHMODE_CH0_PDM_EN_OFFSET) +#define I2S_CHMODE_CH0_PDM_EN_ENA (1 << I2S_CHMODE_CH0_PDM_EN_OFFSET) +#define I2S_CHMODE_CH0_PDM_EN_DIS (0 << I2S_CHMODE_CH0_PDM_EN_OFFSET) + +#define I2S_CHMODE_CH0_USEDDR_OFFSET 16 +#define I2S_CHMODE_CH0_USEDDR_WIDTH 1 +#define I2S_CHMODE_CH0_USEDDR_MASK (0x1 << I2S_CHMODE_CH0_USEDDR_OFFSET) +#define I2S_CHMODE_CH0_USEDDR_ENA (1 << I2S_CHMODE_CH0_USEDDR_OFFSET) +#define I2S_CHMODE_CH0_USEDDR_DIS (0 << I2S_CHMODE_CH0_USEDDR_OFFSET) + +#define I2S_CHMODE_CH0_MODE_OFFSET 24 +#define I2S_CHMODE_CH0_MODE_WIDTH 2 +#define I2S_CHMODE_CH0_MODE_MASK (0x3 << I2S_CHMODE_CH0_MODE_OFFSET) +#define I2S_CHMODE_CH0_MODE_CLK0 (0 << I2S_CHMODE_CH0_MODE_OFFSET) +#define I2S_CHMODE_CH0_MODE_CLK1 (1 << I2S_CHMODE_CH0_MODE_OFFSET) +#define I2S_CHMODE_CH0_MODE_EXTCLK_INTWS (2 << I2S_CHMODE_CH0_MODE_OFFSET) +#define I2S_CHMODE_CH0_MODE_EXTCLK_EXTWS (2 << I2S_CHMODE_CH0_MODE_OFFSET) + +#define I2S_CHMODE_CH1_SNAPCAM_OFFSET 1 +#define I2S_CHMODE_CH1_SNAPCAM_WIDTH 1 +#define I2S_CHMODE_CH1_SNAPCAM_MASK (0x1 << I2S_CHMODE_CH1_SNAPCAM_OFFSET) +#define I2S_CHMODE_CH1_SNAPCAM_ENA (0x1 << I2S_CHMODE_CH1_SNAPCAM_OFFSET) +#define I2S_CHMODE_CH1_SNAPCAM_DIS (0x0 << I2S_CHMODE_CH1_SNAPCAM_OFFSET) + +#define I2S_CHMODE_CH1_LSBFIRST_OFFSET 5 +#define I2S_CHMODE_CH1_LSBFIRST_WIDTH 1 +#define I2S_CHMODE_CH1_LSBFIRST_MASK (0x1 << I2S_CHMODE_CH1_LSBFIRST_OFFSET) +#define I2S_CHMODE_CH1_LSBFIRST_ENA (1 << I2S_CHMODE_CH1_LSBFIRST_OFFSET) +#define I2S_CHMODE_CH1_LSBFIRST_DIS (0 << I2S_CHMODE_CH1_LSBFIRST_OFFSET) + +#define I2S_CHMODE_CH1_PDM_USEFILTER_OFFSET 9 +#define I2S_CHMODE_CH1_PDM_USEFILTER_WIDTH 1 +#define I2S_CHMODE_CH1_PDM_USEFILTER_MASK (0x1 << I2S_CHMODE_CH1_PDM_USEFILTER_OFFSET) +#define I2S_CHMODE_CH1_PDM_USEFILTER_ENA (1 << I2S_CHMODE_CH1_PDM_USEFILTER_OFFSET) +#define I2S_CHMODE_CH1_PDM_USEFILTER_DIS (0 << I2S_CHMODE_CH1_PDM_USEFILTER_OFFSET) + +#define I2S_CHMODE_CH1_PDM_EN_OFFSET 13 +#define I2S_CHMODE_CH1_PDM_EN_WIDTH 1 +#define I2S_CHMODE_CH1_PDM_EN_MASK (0x1 << I2S_CHMODE_CH1_PDM_EN_OFFSET) +#define I2S_CHMODE_CH1_PDM_EN_ENA (1 << I2S_CHMODE_CH1_PDM_EN_OFFSET) +#define I2S_CHMODE_CH1_PDM_EN_DIS (0 << I2S_CHMODE_CH1_PDM_EN_OFFSET) + +#define I2S_CHMODE_CH1_USEDDR_OFFSET 17 +#define I2S_CHMODE_CH1_USEDDR_WIDTH 1 +#define I2S_CHMODE_CH1_USEDDR_MASK (0x1 << I2S_CHMODE_CH1_USEDDR_OFFSET) +#define I2S_CHMODE_CH1_USEDDR_ENA (1 << I2S_CHMODE_CH1_USEDDR_OFFSET) +#define I2S_CHMODE_CH1_USEDDR_DIS (0 << I2S_CHMODE_CH1_USEDDR_OFFSET) + +#define I2S_CHMODE_CH1_MODE_OFFSET 26 +#define I2S_CHMODE_CH1_MODE_WIDTH 2 +#define I2S_CHMODE_CH1_MODE_MASK (0x3 << I2S_CHMODE_CH1_MODE_OFFSET) +#define I2S_CHMODE_CH1_MODE_CLK0 (0 << I2S_CHMODE_CH1_MODE_OFFSET) +#define I2S_CHMODE_CH1_MODE_CLK1 (1 << I2S_CHMODE_CH1_MODE_OFFSET) +#define I2S_CHMODE_CH1_MODE_EXTCLK_INTWS (2 << I2S_CHMODE_CH1_MODE_OFFSET) +#define I2S_CHMODE_CH1_MODE_EXTCLK_EXTWS (2 << I2S_CHMODE_CH1_MODE_OFFSET) + +// Channel clock modes +// Write strobe is the clock for switching left/right channels +#define I2S_CHMODE_INT_CLOCK0 0 // Internal clock 0 +#define I2S_CHMODE_INT_CLOCK1 1 // Internal clock 1 +#define I2S_CHMODE_EXT_CLOCK_INT_WS 2 // External clock internal write strobe +#define I2S_CHMODE_EXT_CLOCK_EXT_WS 3 // External clock external write strobe + + +#define I2S_FILT_CH0_DECIMATION_OFFSET 0 +#define I2S_FILT_CH0_DECIMATION_WIDTH 10 +#define I2S_FILT_CH0_DECIMATION_MASK (0x3ff << I2S_FILT_CH0_DECIMATION_OFFSET) +#define I2S_FILT_CH0_DECIMATION(val) (val << I2S_FILT_CH0_DECIMATION_OFFSET) + +#define I2S_FILT_CH0_SHIFT_OFFSET 16 +#define I2S_FILT_CH0_SHIFT_WIDTH 3 +#define I2S_FILT_CH0_SHIFT_MASK (0x7 << I2S_FILT_CH0_SHIFT_OFFSET) +#define I2S_FILT_CH0_SHIFT(val) (val << I2S_FILT_CH0_SHIFT_OFFSET) + +#define I2S_FILT_CH1_DECIMATION_OFFSET 0 +#define I2S_FILT_CH1_DECIMATION_WIDTH 10 +#define I2S_FILT_CH1_DECIMATION_MASK (0x3ff << I2S_FILT_CH1_DECIMATION_OFFSET) +#define I2S_FILT_CH1_DECIMATION(val) (val << I2S_FILT_CH1_DECIMATION_OFFSET) + +#define I2S_FILT_CH1_SHIFT_OFFSET 16 +#define I2S_FILT_CH1_SHIFT_WIDTH 3 +#define I2S_FILT_CH1_SHIFT_MASK (0x7 << I2S_FILT_CH1_SHIFT_OFFSET) +#define I2S_FILT_CH1_SHIFT(val) (val << I2S_FILT_CH1_SHIFT_OFFSET) +/////////////////////////////////////////////////// + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v1_new.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v1_new.h new file mode 100644 index 0000000..1227baa --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v1_new.h @@ -0,0 +1,786 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_UDMA_I2S_V1_NEW_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_UDMA_I2S_V1_NEW_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// uDMA RX I2S channel 0 buffer base address configuration register. +#define UDMA_I2S_RX_SADDR_CH0_OFFSET 0x0 + +// uDMA RX I2S channel 0 buffer size configuration register. +#define UDMA_I2S_RX_SIZE_CH0_OFFSET 0x4 + +// uDMA RX I2S channel 0 stream configuration register. +#define UDMA_I2S_RX_CFG_CH0_OFFSET 0x8 + +// uDMA RX I2S channel 1 buffer base address configuration register. +#define UDMA_I2S_RX_SADDR_CH1_OFFSET 0x10 + +// uDMA RX I2S channel 1 buffer size configuration register. +#define UDMA_I2S_RX_SIZE_CH1_OFFSET 0x14 + +// uDMA RX I2S channel 1 stream configuration register. +#define UDMA_I2S_RX_CFG_CH1_OFFSET 0x18 + +// I2S external clock configuration register. +#define UDMA_I2S_CFG_EXT_OFFSET 0x20 + +// I2S clock and WS generator 0 configuration register. +#define UDMA_I2S_CFG_CLKGEN0_OFFSET 0x24 + +// I2S clock and WS generator 1 configuration register. +#define UDMA_I2S_CFG_CLKGEN1_OFFSET 0x28 + +// I2S channels mode configuration register. +#define UDMA_I2S_CHMODE_OFFSET 0x2c + +// I2S channel 0 filtering configuration register. +#define UDMA_I2S_FILT_CH0_OFFSET 0x30 + +// I2S channel 1 filtering configuration register. +#define UDMA_I2S_FILT_CH1_OFFSET 0x34 + + + +// +// REGISTERS FIELDS +// + +// I2S channel 0 RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address (access: R/W) +#define UDMA_I2S_RX_SADDR_CH0_RX_SADDR_BIT 0 +#define UDMA_I2S_RX_SADDR_CH0_RX_SADDR_WIDTH 16 +#define UDMA_I2S_RX_SADDR_CH0_RX_SADDR_MASK 0xffff + +// I2S channel 0 RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define UDMA_I2S_RX_SIZE_CH0_RX_SIZE_BIT 0 +#define UDMA_I2S_RX_SIZE_CH0_RX_SIZE_WIDTH 17 +#define UDMA_I2S_RX_SIZE_CH0_RX_SIZE_MASK 0x1ffff + +// I2S channel 0 RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define UDMA_I2S_RX_CFG_CH0_CONTINOUS_BIT 0 +#define UDMA_I2S_RX_CFG_CH0_CONTINOUS_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH0_CONTINOUS_MASK 0x1 + +// RX channel transfer size used to increment uDMA I2S channel 0 RX buffer address pointer: - 2'b00: plus 1 - +1 (8 bits) - 2'b01: plus 2 - +2 (16 bits) - 2'b10: plus 4 - +4 (32 bits) - 2'b11: plus 0 - +0 (access: R/W) +#define UDMA_I2S_RX_CFG_CH0_DATASIZE_BIT 1 +#define UDMA_I2S_RX_CFG_CH0_DATASIZE_WIDTH 2 +#define UDMA_I2S_RX_CFG_CH0_DATASIZE_MASK 0x6 + +// I2S channel 0 RX Channel enable and start transfer bitfield: -1'b0: disable -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_I2S_RX_CFG_CH0_EN_BIT 4 +#define UDMA_I2S_RX_CFG_CH0_EN_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH0_EN_MASK 0x10 + +// I2S channel 0 RX Channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear - stop and clear the on-going transfer (access: W) +#define UDMA_I2S_RX_CFG_CH0_CLR_BIT 5 +#define UDMA_I2S_RX_CFG_CH0_CLR_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH0_CLR_MASK 0x20 + +// I2S channel 0 RX Transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1:pending - pending transfer in the queue (access: R) +#define UDMA_I2S_RX_CFG_CH0_PENDING_BIT 5 +#define UDMA_I2S_RX_CFG_CH0_PENDING_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH0_PENDING_MASK 0x20 + +// I2S channel 1 RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address (access: R/W) +#define UDMA_I2S_RX_SADDR_CH1_TX_SADDR_BIT 0 +#define UDMA_I2S_RX_SADDR_CH1_TX_SADDR_WIDTH 16 +#define UDMA_I2S_RX_SADDR_CH1_TX_SADDR_MASK 0xffff + +// I2S channel 1 RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define UDMA_I2S_RX_SIZE_CH1_TX_SIZE_BIT 0 +#define UDMA_I2S_RX_SIZE_CH1_TX_SIZE_WIDTH 17 +#define UDMA_I2S_RX_SIZE_CH1_TX_SIZE_MASK 0x1ffff + +// I2S channel 1 RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define UDMA_I2S_RX_CFG_CH1_CONTINOUS_BIT 0 +#define UDMA_I2S_RX_CFG_CH1_CONTINOUS_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH1_CONTINOUS_MASK 0x1 + +// RX channel transfer size used to increment uDMA I2S channel 1 RX buffer address pointer: - 2'b00: plus 1 - +1 (8 bits) - 2'b01: plus 2 - +2 (16 bits) - 2'b10: plus 4 - +4 (32 bits) - 2'b11: plus 0 - +0 (access: R/W) +#define UDMA_I2S_RX_CFG_CH1_DATASIZE_BIT 1 +#define UDMA_I2S_RX_CFG_CH1_DATASIZE_WIDTH 2 +#define UDMA_I2S_RX_CFG_CH1_DATASIZE_MASK 0x6 + +// I2S channel 1 RX Channel enable and start transfer bitfield: -1'b0: disable -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_I2S_RX_CFG_CH1_EN_BIT 4 +#define UDMA_I2S_RX_CFG_CH1_EN_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH1_EN_MASK 0x10 + +// I2S channel 1 RX Channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear - stop and clear the on-going transfer (access: W) +#define UDMA_I2S_RX_CFG_CH1_CLR_BIT 5 +#define UDMA_I2S_RX_CFG_CH1_CLR_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH1_CLR_MASK 0x20 + +// I2S channel 1 RX Transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1: pending - pending transfer in the queue (access: R) +#define UDMA_I2S_RX_CFG_CH1_PENDING_BIT 5 +#define UDMA_I2S_RX_CFG_CH1_PENDING_WIDTH 1 +#define UDMA_I2S_RX_CFG_CH1_PENDING_MASK 0x20 + +// External clock word length in bits bitfield. The value is (num bits - 1). (access: R/W) +#define UDMA_I2S_CFG_EXT_EXT_BITS_WORD_BIT 0 +#define UDMA_I2S_CFG_EXT_EXT_BITS_WORD_WIDTH 5 +#define UDMA_I2S_CFG_EXT_EXT_BITS_WORD_MASK 0x1f + +// Clock generator 0 word length in bits bitfield. The value is (num bits - 1). (access: R/W) +#define UDMA_I2S_CFG_CLKGEN0_BITS_WORD_BIT 0 +#define UDMA_I2S_CFG_CLKGEN0_BITS_WORD_WIDTH 5 +#define UDMA_I2S_CFG_CLKGEN0_BITS_WORD_MASK 0x1f + +// Clock generator 0 enable bitfield: - 1'b0: disabled - 1'b1: enabled - enabled. Clock and WS signal are generated. (access: R/W) +#define UDMA_I2S_CFG_CLKGEN0_CLK_EN_BIT 8 +#define UDMA_I2S_CFG_CLKGEN0_CLK_EN_WIDTH 1 +#define UDMA_I2S_CFG_CLKGEN0_CLK_EN_MASK 0x100 + +// Clock generator 0 clock divider related to SoC clock frequency. (access: R/W) +#define UDMA_I2S_CFG_CLKGEN0_CLK_DIV_BIT 16 +#define UDMA_I2S_CFG_CLKGEN0_CLK_DIV_WIDTH 16 +#define UDMA_I2S_CFG_CLKGEN0_CLK_DIV_MASK 0xffff0000 + +// Clock generator 1 word length in bits bitfield. The value is (num bits - 1). (access: R/W) +#define UDMA_I2S_CFG_CLKGEN1_BITS_WORD_BIT 0 +#define UDMA_I2S_CFG_CLKGEN1_BITS_WORD_WIDTH 5 +#define UDMA_I2S_CFG_CLKGEN1_BITS_WORD_MASK 0x1f + +// Clock generator 1 enable bitfield: - 1'b0: disabled - 1'b1: enabled - enabled. Clock and WS signal are generated. (access: R/W) +#define UDMA_I2S_CFG_CLKGEN1_CLK_EN_BIT 8 +#define UDMA_I2S_CFG_CLKGEN1_CLK_EN_WIDTH 1 +#define UDMA_I2S_CFG_CLKGEN1_CLK_EN_MASK 0x100 + +// Clock generator 1 clock divider related to SoC clock frequency. (access: R/W) +#define UDMA_I2S_CFG_CLKGEN1_CLK_DIV_BIT 16 +#define UDMA_I2S_CFG_CLKGEN1_CLK_DIV_WIDTH 16 +#define UDMA_I2S_CFG_CLKGEN1_CLK_DIV_MASK 0xffff0000 + +// I2S channel 0 LSB first configuration for word serialization bitfield: - 1'b0: MSB first - 1'b1: LSB first (access: R/W) +#define UDMA_I2S_CHMODE_CH0_LSB_FIRST_BIT 4 +#define UDMA_I2S_CHMODE_CH0_LSB_FIRST_WIDTH 1 +#define UDMA_I2S_CHMODE_CH0_LSB_FIRST_MASK 0x10 + +// I2S channel 0 PDM filter activation bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_BIT 8 +#define UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_WIDTH 1 +#define UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_MASK 0x100 + +// I2S channel 0 PDM demodulation activation bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define UDMA_I2S_CHMODE_CH0_PDM_EN_BIT 12 +#define UDMA_I2S_CHMODE_CH0_PDM_EN_WIDTH 1 +#define UDMA_I2S_CHMODE_CH0_PDM_EN_MASK 0x1000 + +// I2S channel 0 DDR mode activation bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define UDMA_I2S_CHMODE_CH0_USEDDR_BIT 16 +#define UDMA_I2S_CHMODE_CH0_USEDDR_WIDTH 1 +#define UDMA_I2S_CHMODE_CH0_USEDDR_MASK 0x10000 + +// I2S channel 0 clock/WS mode configuration bitfield: - 2'b00: clock gen 0 - use clock generator 0 (clock and WS generated by clkgen) - 2'b01: clock gen 1 - use clock generator 1 (clock and WS generated by clkgen) - 2'b10: ext clock int ws - use external clock but internal generated WS by clock generator 0 - 2'b11: ext clock ext ws - use external clock and external WS (access: R/W) +#define UDMA_I2S_CHMODE_CH0_MODE_BIT 24 +#define UDMA_I2S_CHMODE_CH0_MODE_WIDTH 2 +#define UDMA_I2S_CHMODE_CH0_MODE_MASK 0x3000000 + +// I2S channel 1 LSB first configuration for word serialization bitfield: - 1'b0: MSB first - 1'b1: LSB first (access: R/W) +#define UDMA_I2S_CHMODE_CH1_LSB_FIRST_BIT 5 +#define UDMA_I2S_CHMODE_CH1_LSB_FIRST_WIDTH 1 +#define UDMA_I2S_CHMODE_CH1_LSB_FIRST_MASK 0x20 + +// I2S channel 1 PDM filter activation bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_BIT 9 +#define UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_WIDTH 1 +#define UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_MASK 0x200 + +// I2S channel 1 PDM demodulation activation bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define UDMA_I2S_CHMODE_CH1_PDM_EN_BIT 13 +#define UDMA_I2S_CHMODE_CH1_PDM_EN_WIDTH 1 +#define UDMA_I2S_CHMODE_CH1_PDM_EN_MASK 0x2000 + +// I2S channel 1 DDR mode activation bitfield: - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define UDMA_I2S_CHMODE_CH1_USEDDR_BIT 17 +#define UDMA_I2S_CHMODE_CH1_USEDDR_WIDTH 1 +#define UDMA_I2S_CHMODE_CH1_USEDDR_MASK 0x20000 + +// I2S channel 1 clock/WS mode configuration bitfield: - 2'b00: clock gen 0 - use clock generator 0 (clock and WS generated by clkgen) - 2'b01: clock gen 1 - use clock generator 1 (clock and WS generated by clkgen) - 2'b10: ext clock int ws - use external clock but internal generated WS by clock generator 0 - 2'b11: ext clock ext ws - use external clock and external WS (access: R/W) +#define UDMA_I2S_CHMODE_CH1_MODE_BIT 26 +#define UDMA_I2S_CHMODE_CH1_MODE_WIDTH 2 +#define UDMA_I2S_CHMODE_CH1_MODE_MASK 0xc000000 + +// I2S channel 0 PDM filter decimation value bitfield. (access: R/W) +#define UDMA_I2S_FILT_CH0_DECIMATION_BIT 0 +#define UDMA_I2S_FILT_CH0_DECIMATION_WIDTH 10 +#define UDMA_I2S_FILT_CH0_DECIMATION_MASK 0x3ff + +// I2S channel 0 PDM filter normalisation right shift value bitfield. (access: R/W) +#define UDMA_I2S_FILT_CH0_SHIFT_BIT 16 +#define UDMA_I2S_FILT_CH0_SHIFT_WIDTH 3 +#define UDMA_I2S_FILT_CH0_SHIFT_MASK 0x70000 + +// I2S channel 1 PDM filter decimation value bitfield. (access: R/W) +#define UDMA_I2S_FILT_CH1_DECIMATION_BIT 0 +#define UDMA_I2S_FILT_CH1_DECIMATION_WIDTH 10 +#define UDMA_I2S_FILT_CH1_DECIMATION_MASK 0x3ff + +// I2S channel 1 PDM filter normalisation right shift value bitfield. (access: R/W) +#define UDMA_I2S_FILT_CH1_SHIFT_BIT 16 +#define UDMA_I2S_FILT_CH1_SHIFT_WIDTH 3 +#define UDMA_I2S_FILT_CH1_SHIFT_MASK 0x70000 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rx_saddr :16; // I2S channel 0 RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_rx_saddr_ch0_t; + +typedef union { + struct { + unsigned int rx_size :17; // I2S channel 0 RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_rx_size_ch0_t; + +typedef union { + struct { + unsigned int continous :1 ; // I2S channel 0 RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int datasize :2 ; // RX channel transfer size used to increment uDMA I2S channel 0 RX buffer address pointer: - 2'b00: plus 1 - +1 (8 bits) - 2'b01: plus 2 - +2 (16 bits) - 2'b10: plus 4 - +4 (32 bits) - 2'b11: plus 0 - +0 + unsigned int padding0:1 ; + unsigned int en :1 ; // I2S channel 0 RX Channel enable and start transfer bitfield: -1'b0: disable -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // I2S channel 0 RX Channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear - stop and clear the on-going transfer + unsigned int pending :1 ; // I2S channel 0 RX Transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1:pending - pending transfer in the queue + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_rx_cfg_ch0_t; + +typedef union { + struct { + unsigned int tx_saddr :16; // I2S channel 1 RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_rx_saddr_ch1_t; + +typedef union { + struct { + unsigned int tx_size :17; // I2S channel 1 RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_rx_size_ch1_t; + +typedef union { + struct { + unsigned int continous :1 ; // I2S channel 1 RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int datasize :2 ; // RX channel transfer size used to increment uDMA I2S channel 1 RX buffer address pointer: - 2'b00: plus 1 - +1 (8 bits) - 2'b01: plus 2 - +2 (16 bits) - 2'b10: plus 4 - +4 (32 bits) - 2'b11: plus 0 - +0 + unsigned int padding0:1 ; + unsigned int en :1 ; // I2S channel 1 RX Channel enable and start transfer bitfield: -1'b0: disable -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // I2S channel 1 RX Channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear - stop and clear the on-going transfer + unsigned int pending :1 ; // I2S channel 1 RX Transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1: pending - pending transfer in the queue + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_rx_cfg_ch1_t; + +typedef union { + struct { + unsigned int ext_bits_word :5 ; // External clock word length in bits bitfield. The value is (num bits - 1). + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_cfg_ext_t; + +typedef union { + struct { + unsigned int bits_word :5 ; // Clock generator 0 word length in bits bitfield. The value is (num bits - 1). + unsigned int padding0:3 ; + unsigned int clk_en :1 ; // Clock generator 0 enable bitfield: - 1'b0: disabled - 1'b1: enabled - enabled. Clock and WS signal are generated. + unsigned int padding1:7 ; + unsigned int clk_div :16; // Clock generator 0 clock divider related to SoC clock frequency. + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_cfg_clkgen0_t; + +typedef union { + struct { + unsigned int bits_word :5 ; // Clock generator 1 word length in bits bitfield. The value is (num bits - 1). + unsigned int padding0:3 ; + unsigned int clk_en :1 ; // Clock generator 1 enable bitfield: - 1'b0: disabled - 1'b1: enabled - enabled. Clock and WS signal are generated. + unsigned int padding1:7 ; + unsigned int clk_div :16; // Clock generator 1 clock divider related to SoC clock frequency. + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_cfg_clkgen1_t; + +typedef union { + struct { + unsigned int padding0:4 ; + unsigned int ch0_lsb_first :1 ; // I2S channel 0 LSB first configuration for word serialization bitfield: - 1'b0: MSB first - 1'b1: LSB first + unsigned int padding1:3 ; + unsigned int ch0_pdm_usefilter:1 ; // I2S channel 0 PDM filter activation bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int padding2:3 ; + unsigned int ch0_pdm_en :1 ; // I2S channel 0 PDM demodulation activation bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int padding3:3 ; + unsigned int ch0_useddr :1 ; // I2S channel 0 DDR mode activation bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int padding4:7 ; + unsigned int ch0_mode :2 ; // I2S channel 0 clock/WS mode configuration bitfield: - 2'b00: clock gen 0 - use clock generator 0 (clock and WS generated by clkgen) - 2'b01: clock gen 1 - use clock generator 1 (clock and WS generated by clkgen) - 2'b10: ext clock int ws - use external clock but internal generated WS by clock generator 0 - 2'b11: ext clock ext ws - use external clock and external WS + unsigned int ch1_lsb_first :1 ; // I2S channel 1 LSB first configuration for word serialization bitfield: - 1'b0: MSB first - 1'b1: LSB first + unsigned int padding5:3 ; + unsigned int ch1_pdm_usefilter:1 ; // I2S channel 1 PDM filter activation bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int padding6:3 ; + unsigned int ch1_pdm_en :1 ; // I2S channel 1 PDM demodulation activation bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int padding7:3 ; + unsigned int ch1_useddr :1 ; // I2S channel 1 DDR mode activation bitfield: - 1'b0: disabled - 1'b1: enabled + unsigned int padding8:8 ; + unsigned int ch1_mode :2 ; // I2S channel 1 clock/WS mode configuration bitfield: - 2'b00: clock gen 0 - use clock generator 0 (clock and WS generated by clkgen) - 2'b01: clock gen 1 - use clock generator 1 (clock and WS generated by clkgen) - 2'b10: ext clock int ws - use external clock but internal generated WS by clock generator 0 - 2'b11: ext clock ext ws - use external clock and external WS + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_chmode_t; + +typedef union { + struct { + unsigned int decimation :10; // I2S channel 0 PDM filter decimation value bitfield. + unsigned int padding0:6 ; + unsigned int shift :3 ; // I2S channel 0 PDM filter normalisation right shift value bitfield. + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_filt_ch0_t; + +typedef union { + struct { + unsigned int decimation :10; // I2S channel 1 PDM filter decimation value bitfield. + unsigned int padding0:6 ; + unsigned int shift :3 ; // I2S channel 1 PDM filter normalisation right shift value bitfield. + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_filt_ch1_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_udma_i2s_rx_saddr_ch0 : public vp::reg_32 +{ +public: + inline void rx_saddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_SADDR_CH0_RX_SADDR_BIT, UDMA_I2S_RX_SADDR_CH0_RX_SADDR_WIDTH); } + inline uint32_t rx_saddr_get() { return this->get_field(UDMA_I2S_RX_SADDR_CH0_RX_SADDR_BIT, UDMA_I2S_RX_SADDR_CH0_RX_SADDR_WIDTH); } +}; + +class vp_udma_i2s_rx_size_ch0 : public vp::reg_32 +{ +public: + inline void rx_size_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_SIZE_CH0_RX_SIZE_BIT, UDMA_I2S_RX_SIZE_CH0_RX_SIZE_WIDTH); } + inline uint32_t rx_size_get() { return this->get_field(UDMA_I2S_RX_SIZE_CH0_RX_SIZE_BIT, UDMA_I2S_RX_SIZE_CH0_RX_SIZE_WIDTH); } +}; + +class vp_udma_i2s_rx_cfg_ch0 : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH0_CONTINOUS_BIT, UDMA_I2S_RX_CFG_CH0_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_I2S_RX_CFG_CH0_CONTINOUS_BIT, UDMA_I2S_RX_CFG_CH0_CONTINOUS_WIDTH); } + inline void datasize_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH0_DATASIZE_BIT, UDMA_I2S_RX_CFG_CH0_DATASIZE_WIDTH); } + inline uint32_t datasize_get() { return this->get_field(UDMA_I2S_RX_CFG_CH0_DATASIZE_BIT, UDMA_I2S_RX_CFG_CH0_DATASIZE_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH0_EN_BIT, UDMA_I2S_RX_CFG_CH0_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_I2S_RX_CFG_CH0_EN_BIT, UDMA_I2S_RX_CFG_CH0_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH0_CLR_BIT, UDMA_I2S_RX_CFG_CH0_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_I2S_RX_CFG_CH0_CLR_BIT, UDMA_I2S_RX_CFG_CH0_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH0_PENDING_BIT, UDMA_I2S_RX_CFG_CH0_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_I2S_RX_CFG_CH0_PENDING_BIT, UDMA_I2S_RX_CFG_CH0_PENDING_WIDTH); } +}; + +class vp_udma_i2s_rx_saddr_ch1 : public vp::reg_32 +{ +public: + inline void tx_saddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_SADDR_CH1_TX_SADDR_BIT, UDMA_I2S_RX_SADDR_CH1_TX_SADDR_WIDTH); } + inline uint32_t tx_saddr_get() { return this->get_field(UDMA_I2S_RX_SADDR_CH1_TX_SADDR_BIT, UDMA_I2S_RX_SADDR_CH1_TX_SADDR_WIDTH); } +}; + +class vp_udma_i2s_rx_size_ch1 : public vp::reg_32 +{ +public: + inline void tx_size_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_SIZE_CH1_TX_SIZE_BIT, UDMA_I2S_RX_SIZE_CH1_TX_SIZE_WIDTH); } + inline uint32_t tx_size_get() { return this->get_field(UDMA_I2S_RX_SIZE_CH1_TX_SIZE_BIT, UDMA_I2S_RX_SIZE_CH1_TX_SIZE_WIDTH); } +}; + +class vp_udma_i2s_rx_cfg_ch1 : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH1_CONTINOUS_BIT, UDMA_I2S_RX_CFG_CH1_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_I2S_RX_CFG_CH1_CONTINOUS_BIT, UDMA_I2S_RX_CFG_CH1_CONTINOUS_WIDTH); } + inline void datasize_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH1_DATASIZE_BIT, UDMA_I2S_RX_CFG_CH1_DATASIZE_WIDTH); } + inline uint32_t datasize_get() { return this->get_field(UDMA_I2S_RX_CFG_CH1_DATASIZE_BIT, UDMA_I2S_RX_CFG_CH1_DATASIZE_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH1_EN_BIT, UDMA_I2S_RX_CFG_CH1_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_I2S_RX_CFG_CH1_EN_BIT, UDMA_I2S_RX_CFG_CH1_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH1_CLR_BIT, UDMA_I2S_RX_CFG_CH1_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_I2S_RX_CFG_CH1_CLR_BIT, UDMA_I2S_RX_CFG_CH1_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_I2S_RX_CFG_CH1_PENDING_BIT, UDMA_I2S_RX_CFG_CH1_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_I2S_RX_CFG_CH1_PENDING_BIT, UDMA_I2S_RX_CFG_CH1_PENDING_WIDTH); } +}; + +class vp_udma_i2s_cfg_ext : public vp::reg_32 +{ +public: + inline void ext_bits_word_set(uint32_t value) { this->set_field(value, UDMA_I2S_CFG_EXT_EXT_BITS_WORD_BIT, UDMA_I2S_CFG_EXT_EXT_BITS_WORD_WIDTH); } + inline uint32_t ext_bits_word_get() { return this->get_field(UDMA_I2S_CFG_EXT_EXT_BITS_WORD_BIT, UDMA_I2S_CFG_EXT_EXT_BITS_WORD_WIDTH); } +}; + +class vp_udma_i2s_cfg_clkgen0 : public vp::reg_32 +{ +public: + inline void bits_word_set(uint32_t value) { this->set_field(value, UDMA_I2S_CFG_CLKGEN0_BITS_WORD_BIT, UDMA_I2S_CFG_CLKGEN0_BITS_WORD_WIDTH); } + inline uint32_t bits_word_get() { return this->get_field(UDMA_I2S_CFG_CLKGEN0_BITS_WORD_BIT, UDMA_I2S_CFG_CLKGEN0_BITS_WORD_WIDTH); } + inline void clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_CFG_CLKGEN0_CLK_EN_BIT, UDMA_I2S_CFG_CLKGEN0_CLK_EN_WIDTH); } + inline uint32_t clk_en_get() { return this->get_field(UDMA_I2S_CFG_CLKGEN0_CLK_EN_BIT, UDMA_I2S_CFG_CLKGEN0_CLK_EN_WIDTH); } + inline void clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_CFG_CLKGEN0_CLK_DIV_BIT, UDMA_I2S_CFG_CLKGEN0_CLK_DIV_WIDTH); } + inline uint32_t clk_div_get() { return this->get_field(UDMA_I2S_CFG_CLKGEN0_CLK_DIV_BIT, UDMA_I2S_CFG_CLKGEN0_CLK_DIV_WIDTH); } +}; + +class vp_udma_i2s_cfg_clkgen1 : public vp::reg_32 +{ +public: + inline void bits_word_set(uint32_t value) { this->set_field(value, UDMA_I2S_CFG_CLKGEN1_BITS_WORD_BIT, UDMA_I2S_CFG_CLKGEN1_BITS_WORD_WIDTH); } + inline uint32_t bits_word_get() { return this->get_field(UDMA_I2S_CFG_CLKGEN1_BITS_WORD_BIT, UDMA_I2S_CFG_CLKGEN1_BITS_WORD_WIDTH); } + inline void clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_CFG_CLKGEN1_CLK_EN_BIT, UDMA_I2S_CFG_CLKGEN1_CLK_EN_WIDTH); } + inline uint32_t clk_en_get() { return this->get_field(UDMA_I2S_CFG_CLKGEN1_CLK_EN_BIT, UDMA_I2S_CFG_CLKGEN1_CLK_EN_WIDTH); } + inline void clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_CFG_CLKGEN1_CLK_DIV_BIT, UDMA_I2S_CFG_CLKGEN1_CLK_DIV_WIDTH); } + inline uint32_t clk_div_get() { return this->get_field(UDMA_I2S_CFG_CLKGEN1_CLK_DIV_BIT, UDMA_I2S_CFG_CLKGEN1_CLK_DIV_WIDTH); } +}; + +class vp_udma_i2s_chmode : public vp::reg_32 +{ +public: + inline void ch0_lsb_first_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH0_LSB_FIRST_BIT, UDMA_I2S_CHMODE_CH0_LSB_FIRST_WIDTH); } + inline uint32_t ch0_lsb_first_get() { return this->get_field(UDMA_I2S_CHMODE_CH0_LSB_FIRST_BIT, UDMA_I2S_CHMODE_CH0_LSB_FIRST_WIDTH); } + inline void ch0_pdm_usefilter_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_BIT, UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_WIDTH); } + inline uint32_t ch0_pdm_usefilter_get() { return this->get_field(UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_BIT, UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_WIDTH); } + inline void ch0_pdm_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH0_PDM_EN_BIT, UDMA_I2S_CHMODE_CH0_PDM_EN_WIDTH); } + inline uint32_t ch0_pdm_en_get() { return this->get_field(UDMA_I2S_CHMODE_CH0_PDM_EN_BIT, UDMA_I2S_CHMODE_CH0_PDM_EN_WIDTH); } + inline void ch0_useddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH0_USEDDR_BIT, UDMA_I2S_CHMODE_CH0_USEDDR_WIDTH); } + inline uint32_t ch0_useddr_get() { return this->get_field(UDMA_I2S_CHMODE_CH0_USEDDR_BIT, UDMA_I2S_CHMODE_CH0_USEDDR_WIDTH); } + inline void ch0_mode_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH0_MODE_BIT, UDMA_I2S_CHMODE_CH0_MODE_WIDTH); } + inline uint32_t ch0_mode_get() { return this->get_field(UDMA_I2S_CHMODE_CH0_MODE_BIT, UDMA_I2S_CHMODE_CH0_MODE_WIDTH); } + inline void ch1_lsb_first_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH1_LSB_FIRST_BIT, UDMA_I2S_CHMODE_CH1_LSB_FIRST_WIDTH); } + inline uint32_t ch1_lsb_first_get() { return this->get_field(UDMA_I2S_CHMODE_CH1_LSB_FIRST_BIT, UDMA_I2S_CHMODE_CH1_LSB_FIRST_WIDTH); } + inline void ch1_pdm_usefilter_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_BIT, UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_WIDTH); } + inline uint32_t ch1_pdm_usefilter_get() { return this->get_field(UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_BIT, UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_WIDTH); } + inline void ch1_pdm_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH1_PDM_EN_BIT, UDMA_I2S_CHMODE_CH1_PDM_EN_WIDTH); } + inline uint32_t ch1_pdm_en_get() { return this->get_field(UDMA_I2S_CHMODE_CH1_PDM_EN_BIT, UDMA_I2S_CHMODE_CH1_PDM_EN_WIDTH); } + inline void ch1_useddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH1_USEDDR_BIT, UDMA_I2S_CHMODE_CH1_USEDDR_WIDTH); } + inline uint32_t ch1_useddr_get() { return this->get_field(UDMA_I2S_CHMODE_CH1_USEDDR_BIT, UDMA_I2S_CHMODE_CH1_USEDDR_WIDTH); } + inline void ch1_mode_set(uint32_t value) { this->set_field(value, UDMA_I2S_CHMODE_CH1_MODE_BIT, UDMA_I2S_CHMODE_CH1_MODE_WIDTH); } + inline uint32_t ch1_mode_get() { return this->get_field(UDMA_I2S_CHMODE_CH1_MODE_BIT, UDMA_I2S_CHMODE_CH1_MODE_WIDTH); } +}; + +class vp_udma_i2s_filt_ch0 : public vp::reg_32 +{ +public: + inline void decimation_set(uint32_t value) { this->set_field(value, UDMA_I2S_FILT_CH0_DECIMATION_BIT, UDMA_I2S_FILT_CH0_DECIMATION_WIDTH); } + inline uint32_t decimation_get() { return this->get_field(UDMA_I2S_FILT_CH0_DECIMATION_BIT, UDMA_I2S_FILT_CH0_DECIMATION_WIDTH); } + inline void shift_set(uint32_t value) { this->set_field(value, UDMA_I2S_FILT_CH0_SHIFT_BIT, UDMA_I2S_FILT_CH0_SHIFT_WIDTH); } + inline uint32_t shift_get() { return this->get_field(UDMA_I2S_FILT_CH0_SHIFT_BIT, UDMA_I2S_FILT_CH0_SHIFT_WIDTH); } +}; + +class vp_udma_i2s_filt_ch1 : public vp::reg_32 +{ +public: + inline void decimation_set(uint32_t value) { this->set_field(value, UDMA_I2S_FILT_CH1_DECIMATION_BIT, UDMA_I2S_FILT_CH1_DECIMATION_WIDTH); } + inline uint32_t decimation_get() { return this->get_field(UDMA_I2S_FILT_CH1_DECIMATION_BIT, UDMA_I2S_FILT_CH1_DECIMATION_WIDTH); } + inline void shift_set(uint32_t value) { this->set_field(value, UDMA_I2S_FILT_CH1_SHIFT_BIT, UDMA_I2S_FILT_CH1_SHIFT_WIDTH); } + inline uint32_t shift_get() { return this->get_field(UDMA_I2S_FILT_CH1_SHIFT_BIT, UDMA_I2S_FILT_CH1_SHIFT_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int rx_saddr_ch0 ; // uDMA RX I2S channel 0 buffer base address configuration register. + unsigned int rx_size_ch0 ; // uDMA RX I2S channel 0 buffer size configuration register. + unsigned int rx_cfg_ch0 ; // uDMA RX I2S channel 0 stream configuration register. + unsigned int rx_saddr_ch1 ; // uDMA RX I2S channel 1 buffer base address configuration register. + unsigned int rx_size_ch1 ; // uDMA RX I2S channel 1 buffer size configuration register. + unsigned int rx_cfg_ch1 ; // uDMA RX I2S channel 1 stream configuration register. + unsigned int cfg_ext ; // I2S external clock configuration register. + unsigned int cfg_clkgen0 ; // I2S clock and WS generator 0 configuration register. + unsigned int cfg_clkgen1 ; // I2S clock and WS generator 1 configuration register. + unsigned int chmode ; // I2S channels mode configuration register. + unsigned int filt_ch0 ; // I2S channel 0 filtering configuration register. + unsigned int filt_ch1 ; // I2S channel 1 filtering configuration register. +} __attribute__((packed)) udma_i2s_udma_i2s_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t udma_i2s_rx_saddr_ch0_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_RX_SADDR_CH0_OFFSET); } +static inline void udma_i2s_rx_saddr_ch0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_RX_SADDR_CH0_OFFSET, value); } + +static inline uint32_t udma_i2s_rx_size_ch0_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_RX_SIZE_CH0_OFFSET); } +static inline void udma_i2s_rx_size_ch0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_RX_SIZE_CH0_OFFSET, value); } + +static inline uint32_t udma_i2s_rx_cfg_ch0_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_RX_CFG_CH0_OFFSET); } +static inline void udma_i2s_rx_cfg_ch0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_RX_CFG_CH0_OFFSET, value); } + +static inline uint32_t udma_i2s_rx_saddr_ch1_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_RX_SADDR_CH1_OFFSET); } +static inline void udma_i2s_rx_saddr_ch1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_RX_SADDR_CH1_OFFSET, value); } + +static inline uint32_t udma_i2s_rx_size_ch1_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_RX_SIZE_CH1_OFFSET); } +static inline void udma_i2s_rx_size_ch1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_RX_SIZE_CH1_OFFSET, value); } + +static inline uint32_t udma_i2s_rx_cfg_ch1_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_RX_CFG_CH1_OFFSET); } +static inline void udma_i2s_rx_cfg_ch1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_RX_CFG_CH1_OFFSET, value); } + +static inline uint32_t udma_i2s_cfg_ext_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_CFG_EXT_OFFSET); } +static inline void udma_i2s_cfg_ext_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_CFG_EXT_OFFSET, value); } + +static inline uint32_t udma_i2s_cfg_clkgen0_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_CFG_CLKGEN0_OFFSET); } +static inline void udma_i2s_cfg_clkgen0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_CFG_CLKGEN0_OFFSET, value); } + +static inline uint32_t udma_i2s_cfg_clkgen1_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_CFG_CLKGEN1_OFFSET); } +static inline void udma_i2s_cfg_clkgen1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_CFG_CLKGEN1_OFFSET, value); } + +static inline uint32_t udma_i2s_chmode_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_CHMODE_OFFSET); } +static inline void udma_i2s_chmode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_CHMODE_OFFSET, value); } + +static inline uint32_t udma_i2s_filt_ch0_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_FILT_CH0_OFFSET); } +static inline void udma_i2s_filt_ch0_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_FILT_CH0_OFFSET, value); } + +static inline uint32_t udma_i2s_filt_ch1_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_FILT_CH1_OFFSET); } +static inline void udma_i2s_filt_ch1_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_FILT_CH1_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define UDMA_I2S_RX_SADDR_CH0_RX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_I2S_RX_SADDR_CH0_RX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_I2S_RX_SADDR_CH0_RX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_I2S_RX_SADDR_CH0_RX_SADDR(val) ((val) << 0) + +#define UDMA_I2S_RX_SIZE_CH0_RX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_I2S_RX_SIZE_CH0_RX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_I2S_RX_SIZE_CH0_RX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_I2S_RX_SIZE_CH0_RX_SIZE(val) ((val) << 0) + +#define UDMA_I2S_RX_CFG_CH0_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_I2S_RX_CFG_CH0_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_I2S_RX_CFG_CH0_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_I2S_RX_CFG_CH0_CONTINOUS(val) ((val) << 0) + +#define UDMA_I2S_RX_CFG_CH0_DATASIZE_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define UDMA_I2S_RX_CFG_CH0_DATASIZE_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define UDMA_I2S_RX_CFG_CH0_DATASIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define UDMA_I2S_RX_CFG_CH0_DATASIZE(val) ((val) << 1) + +#define UDMA_I2S_RX_CFG_CH0_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_I2S_RX_CFG_CH0_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_I2S_RX_CFG_CH0_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_I2S_RX_CFG_CH0_EN(val) ((val) << 4) + +#define UDMA_I2S_RX_CFG_CH0_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_RX_CFG_CH0_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_RX_CFG_CH0_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_RX_CFG_CH0_CLR(val) ((val) << 5) + +#define UDMA_I2S_RX_CFG_CH0_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_RX_CFG_CH0_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_RX_CFG_CH0_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_RX_CFG_CH0_PENDING(val) ((val) << 5) + +#define UDMA_I2S_RX_SADDR_CH1_TX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_I2S_RX_SADDR_CH1_TX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_I2S_RX_SADDR_CH1_TX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_I2S_RX_SADDR_CH1_TX_SADDR(val) ((val) << 0) + +#define UDMA_I2S_RX_SIZE_CH1_TX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_I2S_RX_SIZE_CH1_TX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_I2S_RX_SIZE_CH1_TX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_I2S_RX_SIZE_CH1_TX_SIZE(val) ((val) << 0) + +#define UDMA_I2S_RX_CFG_CH1_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_I2S_RX_CFG_CH1_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_I2S_RX_CFG_CH1_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_I2S_RX_CFG_CH1_CONTINOUS(val) ((val) << 0) + +#define UDMA_I2S_RX_CFG_CH1_DATASIZE_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define UDMA_I2S_RX_CFG_CH1_DATASIZE_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define UDMA_I2S_RX_CFG_CH1_DATASIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define UDMA_I2S_RX_CFG_CH1_DATASIZE(val) ((val) << 1) + +#define UDMA_I2S_RX_CFG_CH1_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_I2S_RX_CFG_CH1_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_I2S_RX_CFG_CH1_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_I2S_RX_CFG_CH1_EN(val) ((val) << 4) + +#define UDMA_I2S_RX_CFG_CH1_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_RX_CFG_CH1_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_RX_CFG_CH1_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_RX_CFG_CH1_CLR(val) ((val) << 5) + +#define UDMA_I2S_RX_CFG_CH1_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_RX_CFG_CH1_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_RX_CFG_CH1_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_RX_CFG_CH1_PENDING(val) ((val) << 5) + +#define UDMA_I2S_CFG_EXT_EXT_BITS_WORD_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define UDMA_I2S_CFG_EXT_EXT_BITS_WORD_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define UDMA_I2S_CFG_EXT_EXT_BITS_WORD_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define UDMA_I2S_CFG_EXT_EXT_BITS_WORD(val) ((val) << 0) + +#define UDMA_I2S_CFG_CLKGEN0_BITS_WORD_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define UDMA_I2S_CFG_CLKGEN0_BITS_WORD_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define UDMA_I2S_CFG_CLKGEN0_BITS_WORD_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define UDMA_I2S_CFG_CLKGEN0_BITS_WORD(val) ((val) << 0) + +#define UDMA_I2S_CFG_CLKGEN0_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define UDMA_I2S_CFG_CLKGEN0_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define UDMA_I2S_CFG_CLKGEN0_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define UDMA_I2S_CFG_CLKGEN0_CLK_EN(val) ((val) << 8) + +#define UDMA_I2S_CFG_CLKGEN0_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define UDMA_I2S_CFG_CLKGEN0_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define UDMA_I2S_CFG_CLKGEN0_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define UDMA_I2S_CFG_CLKGEN0_CLK_DIV(val) ((val) << 16) + +#define UDMA_I2S_CFG_CLKGEN1_BITS_WORD_GET(value) (ARCHI_BEXTRACTU((value),5,0)) +#define UDMA_I2S_CFG_CLKGEN1_BITS_WORD_GETS(value) (ARCHI_BEXTRACT((value),5,0)) +#define UDMA_I2S_CFG_CLKGEN1_BITS_WORD_SET(value,field) (ARCHI_BINSERT((value),(field),5,0)) +#define UDMA_I2S_CFG_CLKGEN1_BITS_WORD(val) ((val) << 0) + +#define UDMA_I2S_CFG_CLKGEN1_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define UDMA_I2S_CFG_CLKGEN1_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define UDMA_I2S_CFG_CLKGEN1_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define UDMA_I2S_CFG_CLKGEN1_CLK_EN(val) ((val) << 8) + +#define UDMA_I2S_CFG_CLKGEN1_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),16,16)) +#define UDMA_I2S_CFG_CLKGEN1_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),16,16)) +#define UDMA_I2S_CFG_CLKGEN1_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),16,16)) +#define UDMA_I2S_CFG_CLKGEN1_CLK_DIV(val) ((val) << 16) + +#define UDMA_I2S_CHMODE_CH0_LSB_FIRST_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_I2S_CHMODE_CH0_LSB_FIRST_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_I2S_CHMODE_CH0_LSB_FIRST_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_I2S_CHMODE_CH0_LSB_FIRST(val) ((val) << 4) + +#define UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define UDMA_I2S_CHMODE_CH0_PDM_USEFILTER_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define UDMA_I2S_CHMODE_CH0_PDM_USEFILTER(val) ((val) << 8) + +#define UDMA_I2S_CHMODE_CH0_PDM_EN_GET(value) (ARCHI_BEXTRACTU((value),1,12)) +#define UDMA_I2S_CHMODE_CH0_PDM_EN_GETS(value) (ARCHI_BEXTRACT((value),1,12)) +#define UDMA_I2S_CHMODE_CH0_PDM_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,12)) +#define UDMA_I2S_CHMODE_CH0_PDM_EN(val) ((val) << 12) + +#define UDMA_I2S_CHMODE_CH0_USEDDR_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define UDMA_I2S_CHMODE_CH0_USEDDR_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define UDMA_I2S_CHMODE_CH0_USEDDR_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define UDMA_I2S_CHMODE_CH0_USEDDR(val) ((val) << 16) + +#define UDMA_I2S_CHMODE_CH0_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,24)) +#define UDMA_I2S_CHMODE_CH0_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,24)) +#define UDMA_I2S_CHMODE_CH0_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,24)) +#define UDMA_I2S_CHMODE_CH0_MODE(val) ((val) << 24) + +#define UDMA_I2S_CHMODE_CH1_LSB_FIRST_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_CHMODE_CH1_LSB_FIRST_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_CHMODE_CH1_LSB_FIRST_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_CHMODE_CH1_LSB_FIRST(val) ((val) << 5) + +#define UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_GET(value) (ARCHI_BEXTRACTU((value),1,9)) +#define UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_GETS(value) (ARCHI_BEXTRACT((value),1,9)) +#define UDMA_I2S_CHMODE_CH1_PDM_USEFILTER_SET(value,field) (ARCHI_BINSERT((value),(field),1,9)) +#define UDMA_I2S_CHMODE_CH1_PDM_USEFILTER(val) ((val) << 9) + +#define UDMA_I2S_CHMODE_CH1_PDM_EN_GET(value) (ARCHI_BEXTRACTU((value),1,13)) +#define UDMA_I2S_CHMODE_CH1_PDM_EN_GETS(value) (ARCHI_BEXTRACT((value),1,13)) +#define UDMA_I2S_CHMODE_CH1_PDM_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,13)) +#define UDMA_I2S_CHMODE_CH1_PDM_EN(val) ((val) << 13) + +#define UDMA_I2S_CHMODE_CH1_USEDDR_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define UDMA_I2S_CHMODE_CH1_USEDDR_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define UDMA_I2S_CHMODE_CH1_USEDDR_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define UDMA_I2S_CHMODE_CH1_USEDDR(val) ((val) << 17) + +#define UDMA_I2S_CHMODE_CH1_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,26)) +#define UDMA_I2S_CHMODE_CH1_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,26)) +#define UDMA_I2S_CHMODE_CH1_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,26)) +#define UDMA_I2S_CHMODE_CH1_MODE(val) ((val) << 26) + +#define UDMA_I2S_FILT_CH0_DECIMATION_GET(value) (ARCHI_BEXTRACTU((value),10,0)) +#define UDMA_I2S_FILT_CH0_DECIMATION_GETS(value) (ARCHI_BEXTRACT((value),10,0)) +#define UDMA_I2S_FILT_CH0_DECIMATION_SET(value,field) (ARCHI_BINSERT((value),(field),10,0)) +#define UDMA_I2S_FILT_CH0_DECIMATION(val) ((val) << 0) + +#define UDMA_I2S_FILT_CH0_SHIFT_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define UDMA_I2S_FILT_CH0_SHIFT_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define UDMA_I2S_FILT_CH0_SHIFT_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define UDMA_I2S_FILT_CH0_SHIFT(val) ((val) << 16) + +#define UDMA_I2S_FILT_CH1_DECIMATION_GET(value) (ARCHI_BEXTRACTU((value),10,0)) +#define UDMA_I2S_FILT_CH1_DECIMATION_GETS(value) (ARCHI_BEXTRACT((value),10,0)) +#define UDMA_I2S_FILT_CH1_DECIMATION_SET(value,field) (ARCHI_BINSERT((value),(field),10,0)) +#define UDMA_I2S_FILT_CH1_DECIMATION(val) ((val) << 0) + +#define UDMA_I2S_FILT_CH1_SHIFT_GET(value) (ARCHI_BEXTRACTU((value),3,16)) +#define UDMA_I2S_FILT_CH1_SHIFT_GETS(value) (ARCHI_BEXTRACT((value),3,16)) +#define UDMA_I2S_FILT_CH1_SHIFT_SET(value,field) (ARCHI_BINSERT((value),(field),3,16)) +#define UDMA_I2S_FILT_CH1_SHIFT(val) ((val) << 16) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v2.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v2.h new file mode 100644 index 0000000..1ee0cef --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/udma_i2s_v2.h @@ -0,0 +1,808 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_UDMA_I2S_V2_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_UDMA_I2S_V2_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// RX Channel 0 I2S uDMA transfer address of associated buffer +#define UDMA_I2S_I2S_RX_SADDR_OFFSET 0x0 + +// RX Channel 0 I2S uDMA transfer size of buffer +#define UDMA_I2S_I2S_RX_SIZE_OFFSET 0x4 + +// RX Channel 0 I2S uDMA transfer configuration +#define UDMA_I2S_I2S_RX_CFG_OFFSET 0x8 + +// - +#define UDMA_I2S_I2S_RX_INITCFG_OFFSET 0xc + +// TX Channel I2S uDMA transfer address of associated buffer +#define UDMA_I2S_I2S_TX_SADDR_OFFSET 0x10 + +// TX Channel I2S uDMA transfer size of buffer +#define UDMA_I2S_I2S_TX_SIZE_OFFSET 0x14 + +// TX Channel I2S uDMA transfer configuration +#define UDMA_I2S_I2S_TX_CFG_OFFSET 0x18 + +// - +#define UDMA_I2S_I2S_TX_INITCFG_OFFSET 0x1c + +// Clock configuration for both master, slave and pdm +#define UDMA_I2S_I2S_CLKCFG_SETUP_OFFSET 0x20 + +// Configuration of I2S slave +#define UDMA_I2S_I2S_SLV_SETUP_OFFSET 0x24 + +// Configuration of I2S master +#define UDMA_I2S_I2S_MST_SETUP_OFFSET 0x28 + +// Configuration of PDM module +#define UDMA_I2S_I2S_PDM_SETUP_OFFSET 0x2c + + + +// +// REGISTERS FIELDS +// + +// Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address (access: R/W) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_BIT 0 +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_WIDTH 16 +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_MASK 0xffff + +// Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size (access: R/W) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_BIT 0 +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_WIDTH 17 +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_MASK 0x1ffff + +// Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. (access: R/W) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_BIT 0 +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_MASK 0x1 + +// Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 (access: R/W) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_BIT 1 +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_WIDTH 2 +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_MASK 0x6 + +// Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_I2S_I2S_RX_CFG_EN_BIT 4 +#define UDMA_I2S_I2S_RX_CFG_EN_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_EN_MASK 0x10 + +// Channel clear and stop transfer: -1'b0: disable -1'b1: enable (access: W) +#define UDMA_I2S_I2S_RX_CFG_CLR_BIT 5 +#define UDMA_I2S_I2S_RX_CFG_CLR_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_CLR_MASK 0x20 + +// Transfer pending in queue status flag: -1'b0: free -1'b1: pending (access: R) +#define UDMA_I2S_I2S_RX_CFG_PENDING_BIT 5 +#define UDMA_I2S_I2S_RX_CFG_PENDING_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_PENDING_MASK 0x20 + +// Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address (access: R/W) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_BIT 0 +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_WIDTH 16 +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_MASK 0xffff + +// Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size (access: R/W) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_BIT 0 +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_WIDTH 17 +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_MASK 0x1ffff + +// Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_BIT 0 +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_MASK 0x1 + +// Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_BIT 1 +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_WIDTH 2 +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_MASK 0x6 + +// Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_EN_BIT 4 +#define UDMA_I2S_I2S_TX_CFG_EN_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_EN_MASK 0x10 + +// Channel clear and stop transfer: -1'b0: disable -1'b1: enable (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_CLR_BIT 5 +#define UDMA_I2S_I2S_TX_CFG_CLR_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_CLR_MASK 0x20 + +// Transfer pending in queue status flag: -1'b0: free -1'b1: pending (access: R) +#define UDMA_I2S_I2S_TX_CFG_PENDING_BIT 5 +#define UDMA_I2S_I2S_TX_CFG_PENDING_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_PENDING_MASK 0x20 + +// LSB of master clock divider (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_BIT 0 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_WIDTH 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_MASK 0xff + +// LSB of slave clock divider (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_BIT 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_WIDTH 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_MASK 0xff00 + +// MSBs of both master and slave clock divider (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_BIT 16 +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_WIDTH 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_MASK 0xff0000 + +// Enables Slave clock (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_BIT 24 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_MASK 0x1000000 + +// Enables Master clock (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_BIT 25 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_MASK 0x2000000 + +// When enabled slave output clock is taken from PDM module (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_BIT 26 +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_MASK 0x4000000 + +// When set uses external clock for slave (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_BIT 28 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_MASK 0x10000000 + +// Selects slave clock source(either ext or generated): -1’b0:selects master -1’b1:selects slave (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_BIT 29 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_MASK 0x20000000 + +// When set uses external clock for master (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_BIT 30 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_MASK 0x40000000 + +// Selects master clock source(either ext or generated): -1’b0:selects master -1’b1:selects slave (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_BIT 31 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_MASK 0x80000000 + +// Sets how many words for each I2S phase (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_BIT 0 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_WIDTH 3 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_MASK 0x7 + +// Sets how many bits per word (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_BIT 8 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_WIDTH 5 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_MASK 0x1f00 + +// Enables LSB shifting (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_BIT 16 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_WIDTH 1 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_MASK 0x10000 + +// Enables both channels (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_BIT 17 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_WIDTH 1 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_MASK 0x20000 + +// Enables the Slave (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_BIT 31 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_WIDTH 1 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_MASK 0x80000000 + +// Sets how many words for each I2S phase (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_BIT 0 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_WIDTH 3 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_MASK 0x7 + +// Sets how many bits per word (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_BIT 8 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_WIDTH 5 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_MASK 0x1f00 + +// Enables LSB shifting (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_BIT 16 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_WIDTH 1 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_MASK 0x10000 + +// Enables both channels (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_BIT 17 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_WIDTH 1 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_MASK 0x20000 + +// Enables the Master (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_BIT 31 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_WIDTH 1 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_MASK 0x80000000 + +// Shifts the output of the filter (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_BIT 0 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_WIDTH 3 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_MASK 0x7 + +// Sets the decimation ratio of the filter (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_BIT 3 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_WIDTH 10 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_MASK 0x1ff8 + +// nan (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_BIT 13 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_WIDTH 2 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_MASK 0x6000 + +// nan (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_BIT 31 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_WIDTH 1 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_MASK 0x80000000 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rx_saddr :16; // Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_saddr_t; + +typedef union { + struct { + unsigned int rx_size :17; // Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. + unsigned int datasize :2 ; // Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 + unsigned int padding0:1 ; + unsigned int en :1 ; // Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // Channel clear and stop transfer: -1'b0: disable -1'b1: enable + unsigned int pending :1 ; // Transfer pending in queue status flag: -1'b0: free -1'b1: pending + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_cfg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_initcfg_t; + +typedef union { + struct { + unsigned int tx_saddr :16; // Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_saddr_t; + +typedef union { + struct { + unsigned int tx_size :17; // Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. + unsigned int datasize :2 ; // Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 + unsigned int padding0:1 ; + unsigned int en :1 ; // Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // Channel clear and stop transfer: -1'b0: disable -1'b1: enable + unsigned int pending :1 ; // Transfer pending in queue status flag: -1'b0: free -1'b1: pending + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_cfg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_initcfg_t; + +typedef union { + struct { + unsigned int master_clk_div :8 ; // LSB of master clock divider + unsigned int slave_clk_div :8 ; // LSB of slave clock divider + unsigned int common_clk_div :8 ; // MSBs of both master and slave clock divider + unsigned int slave_clk_en :1 ; // Enables Slave clock + unsigned int master_clk_en :1 ; // Enables Master clock + unsigned int pdm_clk_en :1 ; // When enabled slave output clock is taken from PDM module + unsigned int padding0:1 ; + unsigned int slave_ext :1 ; // When set uses external clock for slave + unsigned int slave_num :1 ; // Selects slave clock source(either ext or generated): -1’b0:selects master -1’b1:selects slave + unsigned int master_ext :1 ; // When set uses external clock for master + unsigned int master_num :1 ; // Selects master clock source(either ext or generated): -1’b0:selects master -1’b1:selects slave + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_clkcfg_setup_t; + +typedef union { + struct { + unsigned int slave_words :3 ; // Sets how many words for each I2S phase + unsigned int padding0:5 ; + unsigned int slave_bits :5 ; // Sets how many bits per word + unsigned int padding1:3 ; + unsigned int slave_lsb :1 ; // Enables LSB shifting + unsigned int slave_2ch :1 ; // Enables both channels + unsigned int padding2:13; + unsigned int slave_en :1 ; // Enables the Slave + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_slv_setup_t; + +typedef union { + struct { + unsigned int master_words :3 ; // Sets how many words for each I2S phase + unsigned int padding0:5 ; + unsigned int master_bits :5 ; // Sets how many bits per word + unsigned int padding1:3 ; + unsigned int master_lsb :1 ; // Enables LSB shifting + unsigned int master_2ch :1 ; // Enables both channels + unsigned int padding2:13; + unsigned int master_en :1 ; // Enables the Master + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_mst_setup_t; + +typedef union { + struct { + unsigned int pdm_shift :3 ; // Shifts the output of the filter + unsigned int pdm_decimation :10; // Sets the decimation ratio of the filter + unsigned int pdm_mode :2 ; // nan + unsigned int padding0:16; + unsigned int pdm_en :1 ; // nan + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_pdm_setup_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_udma_i2s_i2s_rx_saddr : public vp::reg_32 +{ +public: + inline void rx_saddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_SADDR_RX_SADDR_BIT, UDMA_I2S_I2S_RX_SADDR_RX_SADDR_WIDTH); } + inline uint32_t rx_saddr_get() { return this->get_field(UDMA_I2S_I2S_RX_SADDR_RX_SADDR_BIT, UDMA_I2S_I2S_RX_SADDR_RX_SADDR_WIDTH); } +}; + +class vp_udma_i2s_i2s_rx_size : public vp::reg_32 +{ +public: + inline void rx_size_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_SIZE_RX_SIZE_BIT, UDMA_I2S_I2S_RX_SIZE_RX_SIZE_WIDTH); } + inline uint32_t rx_size_get() { return this->get_field(UDMA_I2S_I2S_RX_SIZE_RX_SIZE_BIT, UDMA_I2S_I2S_RX_SIZE_RX_SIZE_WIDTH); } +}; + +class vp_udma_i2s_i2s_rx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_RX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_RX_CFG_CONTINOUS_WIDTH); } + inline void datasize_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_RX_CFG_DATASIZE_WIDTH); } + inline uint32_t datasize_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_RX_CFG_DATASIZE_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_EN_BIT, UDMA_I2S_I2S_RX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_EN_BIT, UDMA_I2S_I2S_RX_CFG_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_CLR_BIT, UDMA_I2S_I2S_RX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_CLR_BIT, UDMA_I2S_I2S_RX_CFG_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_PENDING_BIT, UDMA_I2S_I2S_RX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_PENDING_BIT, UDMA_I2S_I2S_RX_CFG_PENDING_WIDTH); } +}; + +class vp_udma_i2s_i2s_tx_saddr : public vp::reg_32 +{ +public: + inline void tx_saddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_SADDR_TX_SADDR_BIT, UDMA_I2S_I2S_TX_SADDR_TX_SADDR_WIDTH); } + inline uint32_t tx_saddr_get() { return this->get_field(UDMA_I2S_I2S_TX_SADDR_TX_SADDR_BIT, UDMA_I2S_I2S_TX_SADDR_TX_SADDR_WIDTH); } +}; + +class vp_udma_i2s_i2s_tx_size : public vp::reg_32 +{ +public: + inline void tx_size_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_SIZE_TX_SIZE_BIT, UDMA_I2S_I2S_TX_SIZE_TX_SIZE_WIDTH); } + inline uint32_t tx_size_get() { return this->get_field(UDMA_I2S_I2S_TX_SIZE_TX_SIZE_BIT, UDMA_I2S_I2S_TX_SIZE_TX_SIZE_WIDTH); } +}; + +class vp_udma_i2s_i2s_tx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_TX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_TX_CFG_CONTINOUS_WIDTH); } + inline void datasize_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_TX_CFG_DATASIZE_WIDTH); } + inline uint32_t datasize_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_TX_CFG_DATASIZE_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_EN_BIT, UDMA_I2S_I2S_TX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_EN_BIT, UDMA_I2S_I2S_TX_CFG_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_CLR_BIT, UDMA_I2S_I2S_TX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_CLR_BIT, UDMA_I2S_I2S_TX_CFG_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_PENDING_BIT, UDMA_I2S_I2S_TX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_PENDING_BIT, UDMA_I2S_I2S_TX_CFG_PENDING_WIDTH); } +}; + +class vp_udma_i2s_i2s_clkcfg_setup : public vp::reg_32 +{ +public: + inline void master_clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_WIDTH); } + inline uint32_t master_clk_div_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_WIDTH); } + inline void slave_clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_WIDTH); } + inline uint32_t slave_clk_div_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_WIDTH); } + inline void common_clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_WIDTH); } + inline uint32_t common_clk_div_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_WIDTH); } + inline void slave_clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_WIDTH); } + inline uint32_t slave_clk_en_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_WIDTH); } + inline void master_clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_WIDTH); } + inline uint32_t master_clk_en_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_WIDTH); } + inline void pdm_clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_WIDTH); } + inline uint32_t pdm_clk_en_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_WIDTH); } + inline void slave_ext_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_WIDTH); } + inline uint32_t slave_ext_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_WIDTH); } + inline void slave_num_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_WIDTH); } + inline uint32_t slave_num_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_WIDTH); } + inline void master_ext_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_WIDTH); } + inline uint32_t master_ext_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_WIDTH); } + inline void master_num_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_WIDTH); } + inline uint32_t master_num_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_WIDTH); } +}; + +class vp_udma_i2s_i2s_slv_setup : public vp::reg_32 +{ +public: + inline void slave_words_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_WIDTH); } + inline uint32_t slave_words_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_WIDTH); } + inline void slave_bits_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_WIDTH); } + inline uint32_t slave_bits_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_WIDTH); } + inline void slave_lsb_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_WIDTH); } + inline uint32_t slave_lsb_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_WIDTH); } + inline void slave_2ch_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_WIDTH); } + inline uint32_t slave_2ch_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_WIDTH); } + inline void slave_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_WIDTH); } + inline uint32_t slave_en_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_WIDTH); } +}; + +class vp_udma_i2s_i2s_mst_setup : public vp::reg_32 +{ +public: + inline void master_words_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_WIDTH); } + inline uint32_t master_words_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_WIDTH); } + inline void master_bits_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_WIDTH); } + inline uint32_t master_bits_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_WIDTH); } + inline void master_lsb_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_WIDTH); } + inline uint32_t master_lsb_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_WIDTH); } + inline void master_2ch_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_WIDTH); } + inline uint32_t master_2ch_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_WIDTH); } + inline void master_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_EN_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_EN_WIDTH); } + inline uint32_t master_en_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_EN_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_EN_WIDTH); } +}; + +class vp_udma_i2s_i2s_pdm_setup : public vp::reg_32 +{ +public: + inline void pdm_shift_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_WIDTH); } + inline uint32_t pdm_shift_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_WIDTH); } + inline void pdm_decimation_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_WIDTH); } + inline uint32_t pdm_decimation_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_WIDTH); } + inline void pdm_mode_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_WIDTH); } + inline uint32_t pdm_mode_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_WIDTH); } + inline void pdm_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_EN_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_EN_WIDTH); } + inline uint32_t pdm_en_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_EN_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_EN_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int i2s_rx_saddr ; // RX Channel 0 I2S uDMA transfer address of associated buffer + unsigned int i2s_rx_size ; // RX Channel 0 I2S uDMA transfer size of buffer + unsigned int i2s_rx_cfg ; // RX Channel 0 I2S uDMA transfer configuration + unsigned int i2s_rx_initcfg ; // - + unsigned int i2s_tx_saddr ; // TX Channel I2S uDMA transfer address of associated buffer + unsigned int i2s_tx_size ; // TX Channel I2S uDMA transfer size of buffer + unsigned int i2s_tx_cfg ; // TX Channel I2S uDMA transfer configuration + unsigned int i2s_tx_initcfg ; // - + unsigned int i2s_clkcfg_setup; // Clock configuration for both master, slave and pdm + unsigned int i2s_slv_setup ; // Configuration of I2S slave + unsigned int i2s_mst_setup ; // Configuration of I2S master + unsigned int i2s_pdm_setup ; // Configuration of PDM module +} __attribute__((packed)) udma_i2s_udma_i2s_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t udma_i2s_i2s_rx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_SADDR_OFFSET); } +static inline void udma_i2s_i2s_rx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_SADDR_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_rx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_SIZE_OFFSET); } +static inline void udma_i2s_i2s_rx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_SIZE_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_rx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_CFG_OFFSET); } +static inline void udma_i2s_i2s_rx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_CFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_rx_initcfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_INITCFG_OFFSET); } +static inline void udma_i2s_i2s_rx_initcfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_INITCFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_SADDR_OFFSET); } +static inline void udma_i2s_i2s_tx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_SADDR_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_SIZE_OFFSET); } +static inline void udma_i2s_i2s_tx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_SIZE_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_CFG_OFFSET); } +static inline void udma_i2s_i2s_tx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_CFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_initcfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_INITCFG_OFFSET); } +static inline void udma_i2s_i2s_tx_initcfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_INITCFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_clkcfg_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_CLKCFG_SETUP_OFFSET); } +static inline void udma_i2s_i2s_clkcfg_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_CLKCFG_SETUP_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_slv_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_SLV_SETUP_OFFSET); } +static inline void udma_i2s_i2s_slv_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_SLV_SETUP_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_mst_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_MST_SETUP_OFFSET); } +static inline void udma_i2s_i2s_mst_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_MST_SETUP_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_pdm_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_PDM_SETUP_OFFSET); } +static inline void udma_i2s_i2s_pdm_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_PDM_SETUP_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR(val) ((val) << 0) + +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE(val) ((val) << 0) + +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE(val) ((val) << 1) + +#define UDMA_I2S_I2S_RX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_I2S_I2S_RX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_I2S_I2S_RX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_I2S_I2S_RX_CFG_EN(val) ((val) << 4) + +#define UDMA_I2S_I2S_RX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_RX_CFG_CLR(val) ((val) << 5) + +#define UDMA_I2S_I2S_RX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_RX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR(val) ((val) << 0) + +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE(val) ((val) << 0) + +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE(val) ((val) << 1) + +#define UDMA_I2S_I2S_TX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_I2S_I2S_TX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_I2S_I2S_TX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_I2S_I2S_TX_CFG_EN(val) ((val) << 4) + +#define UDMA_I2S_I2S_TX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_TX_CFG_CLR(val) ((val) << 5) + +#define UDMA_I2S_I2S_TX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_TX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV(val) ((val) << 0) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),8,8)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),8,8)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),8,8)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV(val) ((val) << 8) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),8,16)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),8,16)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),8,16)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV(val) ((val) << 16) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN(val) ((val) << 24) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN(val) ((val) << 25) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,26)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,26)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,26)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN(val) ((val) << 26) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_GET(value) (ARCHI_BEXTRACTU((value),1,28)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_GETS(value) (ARCHI_BEXTRACT((value),1,28)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_SET(value,field) (ARCHI_BINSERT((value),(field),1,28)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT(val) ((val) << 28) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_GET(value) (ARCHI_BEXTRACTU((value),1,29)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_GETS(value) (ARCHI_BEXTRACT((value),1,29)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_SET(value,field) (ARCHI_BINSERT((value),(field),1,29)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM(val) ((val) << 29) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_GET(value) (ARCHI_BEXTRACTU((value),1,30)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_GETS(value) (ARCHI_BEXTRACT((value),1,30)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_SET(value,field) (ARCHI_BINSERT((value),(field),1,30)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT(val) ((val) << 30) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM(val) ((val) << 31) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS(val) ((val) << 0) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_GET(value) (ARCHI_BEXTRACTU((value),5,8)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_GETS(value) (ARCHI_BEXTRACT((value),5,8)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_SET(value,field) (ARCHI_BINSERT((value),(field),5,8)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS(val) ((val) << 8) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB(val) ((val) << 16) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH(val) ((val) << 17) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN(val) ((val) << 31) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS(val) ((val) << 0) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_GET(value) (ARCHI_BEXTRACTU((value),5,8)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_GETS(value) (ARCHI_BEXTRACT((value),5,8)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_SET(value,field) (ARCHI_BINSERT((value),(field),5,8)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS(val) ((val) << 8) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB(val) ((val) << 16) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH(val) ((val) << 17) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN(val) ((val) << 31) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT(val) ((val) << 0) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_GET(value) (ARCHI_BEXTRACTU((value),10,3)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_GETS(value) (ARCHI_BEXTRACT((value),10,3)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_SET(value,field) (ARCHI_BINSERT((value),(field),10,3)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION(val) ((val) << 3) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,13)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,13)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,13)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE(val) ((val) << 13) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN(val) ((val) << 31) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3.h new file mode 100644 index 0000000..f057ada --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3.h @@ -0,0 +1,41 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + +#include "udma_i2s_v3_regs.h" +#include "udma_i2s_v3_regfields.h" +#include "udma_i2s_v3_structs.h" +#include "udma_i2s_v3_regmap.h" +#include "udma_i2s_v3_accessors.h" +#include "udma_i2s_v3_macros.h" +#include "udma_i2s_v3_groups.h" +#include "udma_i2s_v3_constants.h" + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_accessors.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_accessors.h new file mode 100644 index 0000000..52f0c28 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_accessors.h @@ -0,0 +1,79 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_ACCESSORS_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_ACCESSORS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +static inline uint32_t udma_i2s_i2s_rx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_SADDR_OFFSET); } +static inline void udma_i2s_i2s_rx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_SADDR_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_rx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_SIZE_OFFSET); } +static inline void udma_i2s_i2s_rx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_SIZE_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_rx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_CFG_OFFSET); } +static inline void udma_i2s_i2s_rx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_CFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_rx_initcfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_RX_INITCFG_OFFSET); } +static inline void udma_i2s_i2s_rx_initcfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_RX_INITCFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_SADDR_OFFSET); } +static inline void udma_i2s_i2s_tx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_SADDR_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_SIZE_OFFSET); } +static inline void udma_i2s_i2s_tx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_SIZE_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_CFG_OFFSET); } +static inline void udma_i2s_i2s_tx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_CFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_tx_initcfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_TX_INITCFG_OFFSET); } +static inline void udma_i2s_i2s_tx_initcfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_TX_INITCFG_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_clkcfg_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_CLKCFG_SETUP_OFFSET); } +static inline void udma_i2s_i2s_clkcfg_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_CLKCFG_SETUP_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_slv_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_SLV_SETUP_OFFSET); } +static inline void udma_i2s_i2s_slv_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_SLV_SETUP_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_mst_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_MST_SETUP_OFFSET); } +static inline void udma_i2s_i2s_mst_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_MST_SETUP_OFFSET, value); } + +static inline uint32_t udma_i2s_i2s_pdm_setup_get(uint32_t base) { return ARCHI_READ(base, UDMA_I2S_I2S_PDM_SETUP_OFFSET); } +static inline void udma_i2s_i2s_pdm_setup_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_I2S_I2S_PDM_SETUP_OFFSET, value); } + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_constants.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_constants.h new file mode 100644 index 0000000..1757128 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_constants.h @@ -0,0 +1,33 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_CONSTANTS_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_CONSTANTS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_groups.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_groups.h new file mode 100644 index 0000000..44ea7c4 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_groups.h @@ -0,0 +1,33 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_GROUPS_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_GROUPS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_gvsoc.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_gvsoc.h new file mode 100644 index 0000000..b0b9920 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_gvsoc.h @@ -0,0 +1,169 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_GVSOC_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_GVSOC_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_udma_i2s_i2s_rx_saddr : public vp::reg_32 +{ +public: + inline void rx_saddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_SADDR_RX_SADDR_BIT, UDMA_I2S_I2S_RX_SADDR_RX_SADDR_WIDTH); } + inline uint32_t rx_saddr_get() { return this->get_field(UDMA_I2S_I2S_RX_SADDR_RX_SADDR_BIT, UDMA_I2S_I2S_RX_SADDR_RX_SADDR_WIDTH); } +}; + +class vp_udma_i2s_i2s_rx_size : public vp::reg_32 +{ +public: + inline void rx_size_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_SIZE_RX_SIZE_BIT, UDMA_I2S_I2S_RX_SIZE_RX_SIZE_WIDTH); } + inline uint32_t rx_size_get() { return this->get_field(UDMA_I2S_I2S_RX_SIZE_RX_SIZE_BIT, UDMA_I2S_I2S_RX_SIZE_RX_SIZE_WIDTH); } +}; + +class vp_udma_i2s_i2s_rx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_RX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_RX_CFG_CONTINOUS_WIDTH); } + inline void datasize_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_RX_CFG_DATASIZE_WIDTH); } + inline uint32_t datasize_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_RX_CFG_DATASIZE_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_EN_BIT, UDMA_I2S_I2S_RX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_EN_BIT, UDMA_I2S_I2S_RX_CFG_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_CLR_BIT, UDMA_I2S_I2S_RX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_CLR_BIT, UDMA_I2S_I2S_RX_CFG_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_RX_CFG_PENDING_BIT, UDMA_I2S_I2S_RX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_I2S_I2S_RX_CFG_PENDING_BIT, UDMA_I2S_I2S_RX_CFG_PENDING_WIDTH); } +}; + +class vp_udma_i2s_i2s_tx_saddr : public vp::reg_32 +{ +public: + inline void tx_saddr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_SADDR_TX_SADDR_BIT, UDMA_I2S_I2S_TX_SADDR_TX_SADDR_WIDTH); } + inline uint32_t tx_saddr_get() { return this->get_field(UDMA_I2S_I2S_TX_SADDR_TX_SADDR_BIT, UDMA_I2S_I2S_TX_SADDR_TX_SADDR_WIDTH); } +}; + +class vp_udma_i2s_i2s_tx_size : public vp::reg_32 +{ +public: + inline void tx_size_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_SIZE_TX_SIZE_BIT, UDMA_I2S_I2S_TX_SIZE_TX_SIZE_WIDTH); } + inline uint32_t tx_size_get() { return this->get_field(UDMA_I2S_I2S_TX_SIZE_TX_SIZE_BIT, UDMA_I2S_I2S_TX_SIZE_TX_SIZE_WIDTH); } +}; + +class vp_udma_i2s_i2s_tx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_TX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_CONTINOUS_BIT, UDMA_I2S_I2S_TX_CFG_CONTINOUS_WIDTH); } + inline void datasize_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_TX_CFG_DATASIZE_WIDTH); } + inline uint32_t datasize_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_DATASIZE_BIT, UDMA_I2S_I2S_TX_CFG_DATASIZE_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_EN_BIT, UDMA_I2S_I2S_TX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_EN_BIT, UDMA_I2S_I2S_TX_CFG_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_CLR_BIT, UDMA_I2S_I2S_TX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_CLR_BIT, UDMA_I2S_I2S_TX_CFG_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_TX_CFG_PENDING_BIT, UDMA_I2S_I2S_TX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_I2S_I2S_TX_CFG_PENDING_BIT, UDMA_I2S_I2S_TX_CFG_PENDING_WIDTH); } +}; + +class vp_udma_i2s_i2s_clkcfg_setup : public vp::reg_32 +{ +public: + inline void master_clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_WIDTH); } + inline uint32_t master_clk_div_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_WIDTH); } + inline void slave_clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_WIDTH); } + inline uint32_t slave_clk_div_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_WIDTH); } + inline void common_clk_div_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_WIDTH); } + inline uint32_t common_clk_div_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_WIDTH); } + inline void slave_clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_WIDTH); } + inline uint32_t slave_clk_en_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_WIDTH); } + inline void master_clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_WIDTH); } + inline uint32_t master_clk_en_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_WIDTH); } + inline void pdm_clk_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_WIDTH); } + inline uint32_t pdm_clk_en_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_WIDTH); } + inline void slave_ext_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_WIDTH); } + inline uint32_t slave_ext_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_WIDTH); } + inline void slave_num_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_WIDTH); } + inline uint32_t slave_num_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_WIDTH); } + inline void master_ext_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_WIDTH); } + inline uint32_t master_ext_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_WIDTH); } + inline void master_num_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_WIDTH); } + inline uint32_t master_num_get() { return this->get_field(UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_BIT, UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_WIDTH); } +}; + +class vp_udma_i2s_i2s_slv_setup : public vp::reg_32 +{ +public: + inline void slave_words_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_WIDTH); } + inline uint32_t slave_words_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_WIDTH); } + inline void slave_bits_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_WIDTH); } + inline uint32_t slave_bits_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_WIDTH); } + inline void slave_lsb_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_WIDTH); } + inline uint32_t slave_lsb_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_WIDTH); } + inline void slave_2ch_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_WIDTH); } + inline uint32_t slave_2ch_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_WIDTH); } + inline void slave_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_WIDTH); } + inline uint32_t slave_en_get() { return this->get_field(UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_BIT, UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_WIDTH); } +}; + +class vp_udma_i2s_i2s_mst_setup : public vp::reg_32 +{ +public: + inline void master_words_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_WIDTH); } + inline uint32_t master_words_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_WIDTH); } + inline void master_bits_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_WIDTH); } + inline uint32_t master_bits_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_WIDTH); } + inline void master_lsb_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_WIDTH); } + inline uint32_t master_lsb_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_WIDTH); } + inline void master_2ch_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_WIDTH); } + inline uint32_t master_2ch_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_WIDTH); } + inline void master_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_MST_SETUP_MASTER_EN_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_EN_WIDTH); } + inline uint32_t master_en_get() { return this->get_field(UDMA_I2S_I2S_MST_SETUP_MASTER_EN_BIT, UDMA_I2S_I2S_MST_SETUP_MASTER_EN_WIDTH); } +}; + +class vp_udma_i2s_i2s_pdm_setup : public vp::reg_32 +{ +public: + inline void pdm_shift_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_WIDTH); } + inline uint32_t pdm_shift_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_WIDTH); } + inline void pdm_decimation_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_WIDTH); } + inline uint32_t pdm_decimation_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_WIDTH); } + inline void pdm_mode_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_WIDTH); } + inline uint32_t pdm_mode_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_WIDTH); } + inline void pdm_en_set(uint32_t value) { this->set_field(value, UDMA_I2S_I2S_PDM_SETUP_PDM_EN_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_EN_WIDTH); } + inline uint32_t pdm_en_get() { return this->get_field(UDMA_I2S_I2S_PDM_SETUP_PDM_EN_BIT, UDMA_I2S_I2S_PDM_SETUP_PDM_EN_WIDTH); } +}; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_macros.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_macros.h new file mode 100644 index 0000000..3e94d22 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_macros.h @@ -0,0 +1,233 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_MACROS_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_MACROS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS FIELDS MACROS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR(val) ((val) << 0) + +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE(val) ((val) << 0) + +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE(val) ((val) << 1) + +#define UDMA_I2S_I2S_RX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_I2S_I2S_RX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_I2S_I2S_RX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_I2S_I2S_RX_CFG_EN(val) ((val) << 4) + +#define UDMA_I2S_I2S_RX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_RX_CFG_CLR(val) ((val) << 5) + +#define UDMA_I2S_I2S_RX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_RX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_RX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR(val) ((val) << 0) + +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE(val) ((val) << 0) + +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_GET(value) (ARCHI_BEXTRACTU((value),2,1)) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_GETS(value) (ARCHI_BEXTRACT((value),2,1)) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_SET(value,field) (ARCHI_BINSERT((value),(field),2,1)) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE(val) ((val) << 1) + +#define UDMA_I2S_I2S_TX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_I2S_I2S_TX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_I2S_I2S_TX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_I2S_I2S_TX_CFG_EN(val) ((val) << 4) + +#define UDMA_I2S_I2S_TX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_TX_CFG_CLR(val) ((val) << 5) + +#define UDMA_I2S_I2S_TX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_I2S_I2S_TX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_I2S_I2S_TX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV(val) ((val) << 0) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),8,8)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),8,8)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),8,8)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV(val) ((val) << 8) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_GET(value) (ARCHI_BEXTRACTU((value),8,16)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_GETS(value) (ARCHI_BEXTRACT((value),8,16)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_SET(value,field) (ARCHI_BINSERT((value),(field),8,16)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV(val) ((val) << 16) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,24)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,24)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,24)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN(val) ((val) << 24) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,25)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,25)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,25)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN(val) ((val) << 25) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_GET(value) (ARCHI_BEXTRACTU((value),1,26)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_GETS(value) (ARCHI_BEXTRACT((value),1,26)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,26)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN(val) ((val) << 26) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_GET(value) (ARCHI_BEXTRACTU((value),1,28)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_GETS(value) (ARCHI_BEXTRACT((value),1,28)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_SET(value,field) (ARCHI_BINSERT((value),(field),1,28)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT(val) ((val) << 28) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_GET(value) (ARCHI_BEXTRACTU((value),1,29)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_GETS(value) (ARCHI_BEXTRACT((value),1,29)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_SET(value,field) (ARCHI_BINSERT((value),(field),1,29)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM(val) ((val) << 29) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_GET(value) (ARCHI_BEXTRACTU((value),1,30)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_GETS(value) (ARCHI_BEXTRACT((value),1,30)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_SET(value,field) (ARCHI_BINSERT((value),(field),1,30)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT(val) ((val) << 30) + +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM(val) ((val) << 31) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS(val) ((val) << 0) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_GET(value) (ARCHI_BEXTRACTU((value),5,8)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_GETS(value) (ARCHI_BEXTRACT((value),5,8)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_SET(value,field) (ARCHI_BINSERT((value),(field),5,8)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS(val) ((val) << 8) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB(val) ((val) << 16) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH(val) ((val) << 17) + +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN(val) ((val) << 31) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS(val) ((val) << 0) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_GET(value) (ARCHI_BEXTRACTU((value),5,8)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_GETS(value) (ARCHI_BEXTRACT((value),5,8)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_SET(value,field) (ARCHI_BINSERT((value),(field),5,8)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS(val) ((val) << 8) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_GET(value) (ARCHI_BEXTRACTU((value),1,16)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_GETS(value) (ARCHI_BEXTRACT((value),1,16)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_SET(value,field) (ARCHI_BINSERT((value),(field),1,16)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB(val) ((val) << 16) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_GET(value) (ARCHI_BEXTRACTU((value),1,17)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_GETS(value) (ARCHI_BEXTRACT((value),1,17)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_SET(value,field) (ARCHI_BINSERT((value),(field),1,17)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH(val) ((val) << 17) + +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN(val) ((val) << 31) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_GET(value) (ARCHI_BEXTRACTU((value),3,0)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_GETS(value) (ARCHI_BEXTRACT((value),3,0)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_SET(value,field) (ARCHI_BINSERT((value),(field),3,0)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT(val) ((val) << 0) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_GET(value) (ARCHI_BEXTRACTU((value),10,3)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_GETS(value) (ARCHI_BEXTRACT((value),10,3)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_SET(value,field) (ARCHI_BINSERT((value),(field),10,3)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION(val) ((val) << 3) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_GET(value) (ARCHI_BEXTRACTU((value),2,13)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_GETS(value) (ARCHI_BEXTRACT((value),2,13)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_SET(value,field) (ARCHI_BINSERT((value),(field),2,13)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE(val) ((val) << 13) + +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_GET(value) (ARCHI_BEXTRACTU((value),1,31)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_GETS(value) (ARCHI_BEXTRACT((value),1,31)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,31)) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN(val) ((val) << 31) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regfields.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regfields.h new file mode 100644 index 0000000..678900c --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regfields.h @@ -0,0 +1,229 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_REGFIELDS_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_REGFIELDS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS FIELDS +// + +// Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address (access: R/W) +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_BIT 0 +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_WIDTH 16 +#define UDMA_I2S_I2S_RX_SADDR_RX_SADDR_MASK 0xffff + +// Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size (access: R/W) +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_BIT 0 +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_WIDTH 17 +#define UDMA_I2S_I2S_RX_SIZE_RX_SIZE_MASK 0x1ffff + +// Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. (access: R/W) +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_BIT 0 +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_CONTINOUS_MASK 0x1 + +// Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 (access: R/W) +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_BIT 1 +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_WIDTH 2 +#define UDMA_I2S_I2S_RX_CFG_DATASIZE_MASK 0x6 + +// Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_I2S_I2S_RX_CFG_EN_BIT 4 +#define UDMA_I2S_I2S_RX_CFG_EN_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_EN_MASK 0x10 + +// Channel clear and stop transfer: -1'b0: disable -1'b1: enable (access: W) +#define UDMA_I2S_I2S_RX_CFG_CLR_BIT 5 +#define UDMA_I2S_I2S_RX_CFG_CLR_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_CLR_MASK 0x20 + +// Transfer pending in queue status flag: -1'b0: free -1'b1: pending (access: R) +#define UDMA_I2S_I2S_RX_CFG_PENDING_BIT 5 +#define UDMA_I2S_I2S_RX_CFG_PENDING_WIDTH 1 +#define UDMA_I2S_I2S_RX_CFG_PENDING_MASK 0x20 + +// Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address (access: R/W) +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_BIT 0 +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_WIDTH 16 +#define UDMA_I2S_I2S_TX_SADDR_TX_SADDR_MASK 0xffff + +// Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size (access: R/W) +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_BIT 0 +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_WIDTH 17 +#define UDMA_I2S_I2S_TX_SIZE_TX_SIZE_MASK 0x1ffff + +// Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_BIT 0 +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_CONTINOUS_MASK 0x1 + +// Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_BIT 1 +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_WIDTH 2 +#define UDMA_I2S_I2S_TX_CFG_DATASIZE_MASK 0x6 + +// Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_EN_BIT 4 +#define UDMA_I2S_I2S_TX_CFG_EN_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_EN_MASK 0x10 + +// Channel clear and stop transfer: -1'b0: disable -1'b1: enable (access: R/W) +#define UDMA_I2S_I2S_TX_CFG_CLR_BIT 5 +#define UDMA_I2S_I2S_TX_CFG_CLR_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_CLR_MASK 0x20 + +// Transfer pending in queue status flag: -1'b0: free -1'b1: pending (access: R) +#define UDMA_I2S_I2S_TX_CFG_PENDING_BIT 5 +#define UDMA_I2S_I2S_TX_CFG_PENDING_WIDTH 1 +#define UDMA_I2S_I2S_TX_CFG_PENDING_MASK 0x20 + +// LSB of master clock divider (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_BIT 0 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_WIDTH 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_DIV_MASK 0xff + +// LSB of slave clock divider (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_BIT 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_WIDTH 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_DIV_MASK 0xff00 + +// MSBs of both master and slave clock divider (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_BIT 16 +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_WIDTH 8 +#define UDMA_I2S_I2S_CLKCFG_SETUP_COMMON_CLK_DIV_MASK 0xff0000 + +// Enables Slave clock (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_BIT 24 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_CLK_EN_MASK 0x1000000 + +// Enables Master clock (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_BIT 25 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_CLK_EN_MASK 0x2000000 + +// When enabled slave output clock is taken from PDM module (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_BIT 26 +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_PDM_CLK_EN_MASK 0x4000000 + +// When set uses external clock for slave (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_BIT 28 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_EXT_MASK 0x10000000 + +// Selects slave clock source(either ext or generated): -1b0:selects master -1b1:selects slave (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_BIT 29 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_SLAVE_NUM_MASK 0x20000000 + +// When set uses external clock for master (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_BIT 30 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_EXT_MASK 0x40000000 + +// Selects master clock source(either ext or generated): -1b0:selects master -1b1:selects slave (access: R/W) +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_BIT 31 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_WIDTH 1 +#define UDMA_I2S_I2S_CLKCFG_SETUP_MASTER_NUM_MASK 0x80000000 + +// Sets how many words for each I2S phase (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_BIT 0 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_WIDTH 3 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_WORDS_MASK 0x7 + +// Sets how many bits per word (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_BIT 8 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_WIDTH 5 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_BITS_MASK 0x1f00 + +// Enables LSB shifting (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_BIT 16 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_WIDTH 1 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_LSB_MASK 0x10000 + +// Enables both channels (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_BIT 17 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_WIDTH 1 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_2CH_MASK 0x20000 + +// Enables the Slave (access: R/W) +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_BIT 31 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_WIDTH 1 +#define UDMA_I2S_I2S_SLV_SETUP_SLAVE_EN_MASK 0x80000000 + +// Sets how many words for each I2S phase (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_BIT 0 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_WIDTH 3 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_WORDS_MASK 0x7 + +// Sets how many bits per word (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_BIT 8 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_WIDTH 5 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_BITS_MASK 0x1f00 + +// Enables LSB shifting (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_BIT 16 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_WIDTH 1 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_LSB_MASK 0x10000 + +// Enables both channels (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_BIT 17 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_WIDTH 1 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_2CH_MASK 0x20000 + +// Enables the Master (access: R/W) +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_BIT 31 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_WIDTH 1 +#define UDMA_I2S_I2S_MST_SETUP_MASTER_EN_MASK 0x80000000 + +// Shifts the output of the filter (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_BIT 0 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_WIDTH 3 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_SHIFT_MASK 0x7 + +// Sets the decimation ratio of the filter (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_BIT 3 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_WIDTH 10 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_DECIMATION_MASK 0x1ff8 + +// nan (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_BIT 13 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_WIDTH 2 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_MODE_MASK 0x6000 + +// nan (access: R/W) +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_BIT 31 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_WIDTH 1 +#define UDMA_I2S_I2S_PDM_SETUP_PDM_EN_MASK 0x80000000 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regmap.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regmap.h new file mode 100644 index 0000000..a68e8e8 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regmap.h @@ -0,0 +1,58 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_REGMAP_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_REGMAP_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS GLOBAL STRUCT +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef struct { + unsigned int i2s_rx_saddr ; // RX Channel 0 I2S uDMA transfer address of associated buffer + unsigned int i2s_rx_size ; // RX Channel 0 I2S uDMA transfer size of buffer + unsigned int i2s_rx_cfg ; // RX Channel 0 I2S uDMA transfer configuration + unsigned int i2s_rx_initcfg ; // - + unsigned int i2s_tx_saddr ; // TX Channel I2S uDMA transfer address of associated buffer + unsigned int i2s_tx_size ; // TX Channel I2S uDMA transfer size of buffer + unsigned int i2s_tx_cfg ; // TX Channel I2S uDMA transfer configuration + unsigned int i2s_tx_initcfg ; // - + unsigned int i2s_clkcfg_setup; // Clock configuration for both master, slave and pdm + unsigned int i2s_slv_setup ; // Configuration of I2S slave + unsigned int i2s_mst_setup ; // Configuration of I2S master + unsigned int i2s_pdm_setup ; // Configuration of PDM module +} __attribute__((packed)) udma_i2s_udma_i2s_t; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regs.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regs.h new file mode 100644 index 0000000..3964b54 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_regs.h @@ -0,0 +1,75 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_REGS_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_REGS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// RX Channel 0 I2S uDMA transfer address of associated buffer +#define UDMA_I2S_I2S_RX_SADDR_OFFSET 0x0 + +// RX Channel 0 I2S uDMA transfer size of buffer +#define UDMA_I2S_I2S_RX_SIZE_OFFSET 0x4 + +// RX Channel 0 I2S uDMA transfer configuration +#define UDMA_I2S_I2S_RX_CFG_OFFSET 0x8 + +// - +#define UDMA_I2S_I2S_RX_INITCFG_OFFSET 0xc + +// TX Channel I2S uDMA transfer address of associated buffer +#define UDMA_I2S_I2S_TX_SADDR_OFFSET 0x10 + +// TX Channel I2S uDMA transfer size of buffer +#define UDMA_I2S_I2S_TX_SIZE_OFFSET 0x14 + +// TX Channel I2S uDMA transfer configuration +#define UDMA_I2S_I2S_TX_CFG_OFFSET 0x18 + +// - +#define UDMA_I2S_I2S_TX_INITCFG_OFFSET 0x1c + +// Clock configuration for both master, slave and pdm +#define UDMA_I2S_I2S_CLKCFG_SETUP_OFFSET 0x20 + +// Configuration of I2S slave +#define UDMA_I2S_I2S_SLV_SETUP_OFFSET 0x24 + +// Configuration of I2S master +#define UDMA_I2S_I2S_MST_SETUP_OFFSET 0x28 + +// Configuration of PDM module +#define UDMA_I2S_I2S_PDM_SETUP_OFFSET 0x2c + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_structs.h b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_structs.h new file mode 100644 index 0000000..83f9d72 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/i2s/v3/udma_i2s_v3_structs.h @@ -0,0 +1,163 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_STRUCTS_H__ +#define __INCLUDE_ARCHI_UDMA_I2S_V3_UDMA_I2S_V3_STRUCTS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS STRUCTS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef union { + struct { + unsigned int rx_saddr :16; // Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_saddr_t; + +typedef union { + struct { + unsigned int rx_size :17; // Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. + unsigned int datasize :2 ; // Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 + unsigned int padding0:1 ; + unsigned int en :1 ; // Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // Channel clear and stop transfer: -1'b0: disable -1'b1: enable + unsigned int pending :1 ; // Transfer pending in queue status flag: -1'b0: free -1'b1: pending + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_cfg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_rx_initcfg_t; + +typedef union { + struct { + unsigned int tx_saddr :16; // Configure pointer to memory buffer: - Read: value of the pointer until transfer is over. Else returns 0 - Write: set Address Pointer to memory buffer start address + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_saddr_t; + +typedef union { + struct { + unsigned int tx_size :17; // Buffer size in byte. (128kBytes maximum) - Read: buffer size left - Write: set buffer size + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // Channel continuous mode: -1'b0: disable -1'b1: enable At the end of the buffer the uDMA reloads the address and size and starts a new transfer. + unsigned int datasize :2 ; // Channel transfer size used to increment uDMA buffer address pointer: - 2'b00: +1 (8 bits) - 2'b01: +2 (16 bits) - 2'b10: +4 (32 bits) - 2'b11: +0 + unsigned int padding0:1 ; + unsigned int en :1 ; // Channel enable and start transfer: -1'b0: disable -1'b1: enable This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // Channel clear and stop transfer: -1'b0: disable -1'b1: enable + unsigned int pending :1 ; // Transfer pending in queue status flag: -1'b0: free -1'b1: pending + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_cfg_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_tx_initcfg_t; + +typedef union { + struct { + unsigned int master_clk_div :8 ; // LSB of master clock divider + unsigned int slave_clk_div :8 ; // LSB of slave clock divider + unsigned int common_clk_div :8 ; // MSBs of both master and slave clock divider + unsigned int slave_clk_en :1 ; // Enables Slave clock + unsigned int master_clk_en :1 ; // Enables Master clock + unsigned int pdm_clk_en :1 ; // When enabled slave output clock is taken from PDM module + unsigned int padding0:1 ; + unsigned int slave_ext :1 ; // When set uses external clock for slave + unsigned int slave_num :1 ; // Selects slave clock source(either ext or generated): -1b0:selects master -1b1:selects slave + unsigned int master_ext :1 ; // When set uses external clock for master + unsigned int master_num :1 ; // Selects master clock source(either ext or generated): -1b0:selects master -1b1:selects slave + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_clkcfg_setup_t; + +typedef union { + struct { + unsigned int slave_words :3 ; // Sets how many words for each I2S phase + unsigned int padding0:5 ; + unsigned int slave_bits :5 ; // Sets how many bits per word + unsigned int padding1:3 ; + unsigned int slave_lsb :1 ; // Enables LSB shifting + unsigned int slave_2ch :1 ; // Enables both channels + unsigned int padding2:13; + unsigned int slave_en :1 ; // Enables the Slave + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_slv_setup_t; + +typedef union { + struct { + unsigned int master_words :3 ; // Sets how many words for each I2S phase + unsigned int padding0:5 ; + unsigned int master_bits :5 ; // Sets how many bits per word + unsigned int padding1:3 ; + unsigned int master_lsb :1 ; // Enables LSB shifting + unsigned int master_2ch :1 ; // Enables both channels + unsigned int padding2:13; + unsigned int master_en :1 ; // Enables the Master + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_mst_setup_t; + +typedef union { + struct { + unsigned int pdm_shift :3 ; // Shifts the output of the filter + unsigned int pdm_decimation :10; // Sets the decimation ratio of the filter + unsigned int pdm_mode :2 ; // nan + unsigned int padding0:16; + unsigned int pdm_en :1 ; // nan + }; + unsigned int raw; +} __attribute__((packed)) udma_i2s_i2s_pdm_setup_t; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1.h new file mode 100644 index 0000000..bae98d4 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1.h @@ -0,0 +1,41 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + +#include "udma_memcpy_v1_regs.h" +#include "udma_memcpy_v1_regfields.h" +#include "udma_memcpy_v1_structs.h" +#include "udma_memcpy_v1_regmap.h" +#include "udma_memcpy_v1_accessors.h" +#include "udma_memcpy_v1_macros.h" +#include "udma_memcpy_v1_groups.h" +#include "udma_memcpy_v1_constants.h" + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_accessors.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_accessors.h new file mode 100644 index 0000000..eccb24f --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_accessors.h @@ -0,0 +1,70 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_ACCESSORS_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_ACCESSORS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +static inline uint32_t udma_memcpy_rx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_RX_SADDR_OFFSET); } +static inline void udma_memcpy_rx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_RX_SADDR_OFFSET, value); } + +static inline uint32_t udma_memcpy_rx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_RX_SIZE_OFFSET); } +static inline void udma_memcpy_rx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_RX_SIZE_OFFSET, value); } + +static inline uint32_t udma_memcpy_rx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_RX_CFG_OFFSET); } +static inline void udma_memcpy_rx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_RX_CFG_OFFSET, value); } + +static inline uint32_t udma_memcpy_tx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_TX_SADDR_OFFSET); } +static inline void udma_memcpy_tx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_TX_SADDR_OFFSET, value); } + +static inline uint32_t udma_memcpy_tx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_TX_SIZE_OFFSET); } +static inline void udma_memcpy_tx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_TX_SIZE_OFFSET, value); } + +static inline uint32_t udma_memcpy_tx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_TX_CFG_OFFSET); } +static inline void udma_memcpy_tx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_TX_CFG_OFFSET, value); } + +static inline uint32_t udma_memcpy_dst_addr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_DST_ADDR_OFFSET); } +static inline void udma_memcpy_dst_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_DST_ADDR_OFFSET, value); } + +static inline uint32_t udma_memcpy_src_addr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_SRC_ADDR_OFFSET); } +static inline void udma_memcpy_src_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_SRC_ADDR_OFFSET, value); } + +static inline uint32_t udma_memcpy_mem_sel_get(uint32_t base) { return ARCHI_READ(base, UDMA_MEMCPY_MEM_SEL_OFFSET); } +static inline void udma_memcpy_mem_sel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MEMCPY_MEM_SEL_OFFSET, value); } + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_constants.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_constants.h new file mode 100644 index 0000000..a43db45 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_constants.h @@ -0,0 +1,33 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_CONSTANTS_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_CONSTANTS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_groups.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_groups.h new file mode 100644 index 0000000..aeb9c55 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_groups.h @@ -0,0 +1,33 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_GROUPS_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_GROUPS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_gvsoc.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_gvsoc.h new file mode 100644 index 0000000..a06f55e --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_gvsoc.h @@ -0,0 +1,118 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_GVSOC_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_GVSOC_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_udma_memcpy_rx_saddr : public vp::reg_32 +{ +public: + inline void rx_saddr_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_RX_SADDR_RX_SADDR_BIT, UDMA_MEMCPY_RX_SADDR_RX_SADDR_WIDTH); } + inline uint32_t rx_saddr_get() { return this->get_field(UDMA_MEMCPY_RX_SADDR_RX_SADDR_BIT, UDMA_MEMCPY_RX_SADDR_RX_SADDR_WIDTH); } +}; + +class vp_udma_memcpy_rx_size : public vp::reg_32 +{ +public: + inline void rx_size_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_RX_SIZE_RX_SIZE_BIT, UDMA_MEMCPY_RX_SIZE_RX_SIZE_WIDTH); } + inline uint32_t rx_size_get() { return this->get_field(UDMA_MEMCPY_RX_SIZE_RX_SIZE_BIT, UDMA_MEMCPY_RX_SIZE_RX_SIZE_WIDTH); } +}; + +class vp_udma_memcpy_rx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_RX_CFG_CONTINOUS_BIT, UDMA_MEMCPY_RX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_MEMCPY_RX_CFG_CONTINOUS_BIT, UDMA_MEMCPY_RX_CFG_CONTINOUS_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_RX_CFG_EN_BIT, UDMA_MEMCPY_RX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_MEMCPY_RX_CFG_EN_BIT, UDMA_MEMCPY_RX_CFG_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_RX_CFG_CLR_BIT, UDMA_MEMCPY_RX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_MEMCPY_RX_CFG_CLR_BIT, UDMA_MEMCPY_RX_CFG_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_RX_CFG_PENDING_BIT, UDMA_MEMCPY_RX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_MEMCPY_RX_CFG_PENDING_BIT, UDMA_MEMCPY_RX_CFG_PENDING_WIDTH); } +}; + +class vp_udma_memcpy_tx_saddr : public vp::reg_32 +{ +public: + inline void tx_saddr_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_TX_SADDR_TX_SADDR_BIT, UDMA_MEMCPY_TX_SADDR_TX_SADDR_WIDTH); } + inline uint32_t tx_saddr_get() { return this->get_field(UDMA_MEMCPY_TX_SADDR_TX_SADDR_BIT, UDMA_MEMCPY_TX_SADDR_TX_SADDR_WIDTH); } +}; + +class vp_udma_memcpy_tx_size : public vp::reg_32 +{ +public: + inline void tx_size_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_TX_SIZE_TX_SIZE_BIT, UDMA_MEMCPY_TX_SIZE_TX_SIZE_WIDTH); } + inline uint32_t tx_size_get() { return this->get_field(UDMA_MEMCPY_TX_SIZE_TX_SIZE_BIT, UDMA_MEMCPY_TX_SIZE_TX_SIZE_WIDTH); } +}; + +class vp_udma_memcpy_tx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_TX_CFG_CONTINOUS_BIT, UDMA_MEMCPY_TX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_MEMCPY_TX_CFG_CONTINOUS_BIT, UDMA_MEMCPY_TX_CFG_CONTINOUS_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_TX_CFG_EN_BIT, UDMA_MEMCPY_TX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_MEMCPY_TX_CFG_EN_BIT, UDMA_MEMCPY_TX_CFG_EN_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_TX_CFG_CLR_BIT, UDMA_MEMCPY_TX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_MEMCPY_TX_CFG_CLR_BIT, UDMA_MEMCPY_TX_CFG_CLR_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_TX_CFG_PENDING_BIT, UDMA_MEMCPY_TX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_MEMCPY_TX_CFG_PENDING_BIT, UDMA_MEMCPY_TX_CFG_PENDING_WIDTH); } +}; + +class vp_udma_memcpy_dst_addr : public vp::reg_32 +{ +public: + inline void dst_addr_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_DST_ADDR_DST_ADDR_BIT, UDMA_MEMCPY_DST_ADDR_DST_ADDR_WIDTH); } + inline uint32_t dst_addr_get() { return this->get_field(UDMA_MEMCPY_DST_ADDR_DST_ADDR_BIT, UDMA_MEMCPY_DST_ADDR_DST_ADDR_WIDTH); } +}; + +class vp_udma_memcpy_src_addr : public vp::reg_32 +{ +public: + inline void src_addr_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_BIT, UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_WIDTH); } + inline uint32_t src_addr_get() { return this->get_field(UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_BIT, UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_WIDTH); } +}; + +class vp_udma_memcpy_mem_sel : public vp::reg_32 +{ +public: + inline void mem_sel_set(uint32_t value) { this->set_field(value, UDMA_MEMCPY_MEM_SEL_MEM_SEL_BIT, UDMA_MEMCPY_MEM_SEL_MEM_SEL_WIDTH); } + inline uint32_t mem_sel_get() { return this->get_field(UDMA_MEMCPY_MEM_SEL_MEM_SEL_BIT, UDMA_MEMCPY_MEM_SEL_MEM_SEL_WIDTH); } +}; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_macros.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_macros.h new file mode 100644 index 0000000..90685c2 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_macros.h @@ -0,0 +1,118 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_MACROS_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_MACROS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS FIELDS MACROS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#define UDMA_MEMCPY_RX_SADDR_RX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_MEMCPY_RX_SADDR_RX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_MEMCPY_RX_SADDR_RX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_MEMCPY_RX_SADDR_RX_SADDR(val) ((val) << 0) + +#define UDMA_MEMCPY_RX_SIZE_RX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_MEMCPY_RX_SIZE_RX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_MEMCPY_RX_SIZE_RX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_MEMCPY_RX_SIZE_RX_SIZE(val) ((val) << 0) + +#define UDMA_MEMCPY_RX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MEMCPY_RX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MEMCPY_RX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MEMCPY_RX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_MEMCPY_RX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_MEMCPY_RX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_MEMCPY_RX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_MEMCPY_RX_CFG_EN(val) ((val) << 4) + +#define UDMA_MEMCPY_RX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_MEMCPY_RX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_MEMCPY_RX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_MEMCPY_RX_CFG_CLR(val) ((val) << 5) + +#define UDMA_MEMCPY_RX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_MEMCPY_RX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_MEMCPY_RX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_MEMCPY_RX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_MEMCPY_TX_SADDR_TX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_MEMCPY_TX_SADDR_TX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_MEMCPY_TX_SADDR_TX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_MEMCPY_TX_SADDR_TX_SADDR(val) ((val) << 0) + +#define UDMA_MEMCPY_TX_SIZE_TX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_MEMCPY_TX_SIZE_TX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_MEMCPY_TX_SIZE_TX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_MEMCPY_TX_SIZE_TX_SIZE(val) ((val) << 0) + +#define UDMA_MEMCPY_TX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MEMCPY_TX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MEMCPY_TX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MEMCPY_TX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_MEMCPY_TX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_MEMCPY_TX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_MEMCPY_TX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_MEMCPY_TX_CFG_EN(val) ((val) << 4) + +#define UDMA_MEMCPY_TX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_MEMCPY_TX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_MEMCPY_TX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_MEMCPY_TX_CFG_CLR(val) ((val) << 5) + +#define UDMA_MEMCPY_TX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_MEMCPY_TX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_MEMCPY_TX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_MEMCPY_TX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_MEMCPY_DST_ADDR_DST_ADDR_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_MEMCPY_DST_ADDR_DST_ADDR_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_MEMCPY_DST_ADDR_DST_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_MEMCPY_DST_ADDR_DST_ADDR(val) ((val) << 0) + +#define UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_MEMCPY_SRC_ADDR_SRC_ADDR(val) ((val) << 0) + +#define UDMA_MEMCPY_MEM_SEL_MEM_SEL_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MEMCPY_MEM_SEL_MEM_SEL_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MEMCPY_MEM_SEL_MEM_SEL_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MEMCPY_MEM_SEL_MEM_SEL(val) ((val) << 0) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regfields.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regfields.h new file mode 100644 index 0000000..701a6e0 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regfields.h @@ -0,0 +1,114 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_REGFIELDS_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_REGFIELDS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS FIELDS +// + +// RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address (access: R/W) +#define UDMA_MEMCPY_RX_SADDR_RX_SADDR_BIT 0 +#define UDMA_MEMCPY_RX_SADDR_RX_SADDR_WIDTH 16 +#define UDMA_MEMCPY_RX_SADDR_RX_SADDR_MASK 0xffff + +// RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define UDMA_MEMCPY_RX_SIZE_RX_SIZE_BIT 0 +#define UDMA_MEMCPY_RX_SIZE_RX_SIZE_WIDTH 17 +#define UDMA_MEMCPY_RX_SIZE_RX_SIZE_MASK 0x1ffff + +// RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define UDMA_MEMCPY_RX_CFG_CONTINOUS_BIT 0 +#define UDMA_MEMCPY_RX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_MEMCPY_RX_CFG_CONTINOUS_MASK 0x1 + +// RX channel enable and start transfer bitfield: -1'b0: disable -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_MEMCPY_RX_CFG_EN_BIT 4 +#define UDMA_MEMCPY_RX_CFG_EN_WIDTH 1 +#define UDMA_MEMCPY_RX_CFG_EN_MASK 0x10 + +// RX channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear - stop and clear the on-going transfer (access: W) +#define UDMA_MEMCPY_RX_CFG_CLR_BIT 5 +#define UDMA_MEMCPY_RX_CFG_CLR_WIDTH 1 +#define UDMA_MEMCPY_RX_CFG_CLR_MASK 0x20 + +// RX transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1: pending - pending transfer in the queue (access: R) +#define UDMA_MEMCPY_RX_CFG_PENDING_BIT 5 +#define UDMA_MEMCPY_RX_CFG_PENDING_WIDTH 1 +#define UDMA_MEMCPY_RX_CFG_PENDING_MASK 0x20 + +// TX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets buffer base address (access: R/W) +#define UDMA_MEMCPY_TX_SADDR_TX_SADDR_BIT 0 +#define UDMA_MEMCPY_TX_SADDR_TX_SADDR_WIDTH 16 +#define UDMA_MEMCPY_TX_SADDR_TX_SADDR_MASK 0xffff + +// TX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define UDMA_MEMCPY_TX_SIZE_TX_SIZE_BIT 0 +#define UDMA_MEMCPY_TX_SIZE_TX_SIZE_WIDTH 17 +#define UDMA_MEMCPY_TX_SIZE_TX_SIZE_MASK 0x1ffff + +// TX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define UDMA_MEMCPY_TX_CFG_CONTINOUS_BIT 0 +#define UDMA_MEMCPY_TX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_MEMCPY_TX_CFG_CONTINOUS_MASK 0x1 + +// TX channel enable and start transfer bitfield: -1'b0: disabled -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_MEMCPY_TX_CFG_EN_BIT 4 +#define UDMA_MEMCPY_TX_CFG_EN_WIDTH 1 +#define UDMA_MEMCPY_TX_CFG_EN_MASK 0x10 + +// TX channel clear and stop transfer bitfield: -1'b0: disabled -1'b1: stop and clear - stop and clear the on-going transfer (access: W) +#define UDMA_MEMCPY_TX_CFG_CLR_BIT 5 +#define UDMA_MEMCPY_TX_CFG_CLR_WIDTH 1 +#define UDMA_MEMCPY_TX_CFG_CLR_MASK 0x20 + +// TX transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1: pending - pending transfer in the queue (access: R) +#define UDMA_MEMCPY_TX_CFG_PENDING_BIT 5 +#define UDMA_MEMCPY_TX_CFG_PENDING_WIDTH 1 +#define UDMA_MEMCPY_TX_CFG_PENDING_MASK 0x20 + +// TX destination start address configuration bitfield. MEMCPY TX transfer copy data from L2 TX_CFG.TX_SADDR address to FC_TCDM or L2 memories DST_ADDR address. (access: R/W) +#define UDMA_MEMCPY_DST_ADDR_DST_ADDR_BIT 0 +#define UDMA_MEMCPY_DST_ADDR_DST_ADDR_WIDTH 17 +#define UDMA_MEMCPY_DST_ADDR_DST_ADDR_MASK 0x1ffff + +// RX source start address configuration bitfield. MEMCPY RX transfer copy data from FC_TCDM or L2 memories SRC_ADDR address to L2 RX_CFG.RX_SADDR address. (access: R/W) +#define UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_BIT 0 +#define UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_WIDTH 17 +#define UDMA_MEMCPY_SRC_ADDR_SRC_ADDR_MASK 0x1ffff + +// Memory selection configuration bitfield: - 1'b0: L2 from/to FC_TCDM - 1'b1: L2 from/to L2 (access: R/W) +#define UDMA_MEMCPY_MEM_SEL_MEM_SEL_BIT 0 +#define UDMA_MEMCPY_MEM_SEL_MEM_SEL_WIDTH 1 +#define UDMA_MEMCPY_MEM_SEL_MEM_SEL_MASK 0x1 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regmap.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regmap.h new file mode 100644 index 0000000..6c907e4 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regmap.h @@ -0,0 +1,55 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_REGMAP_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_REGMAP_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS GLOBAL STRUCT +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef struct { + unsigned int rx_saddr ; // uDMA RX MEMCPY buffer base address configuration register. + unsigned int rx_size ; // uDMA RX MEMCPY buffer size configuration register. + unsigned int rx_cfg ; // uDMA RX MEMCPY stream configuration register. + unsigned int tx_saddr ; // uDMA TX MEMCPY buffer base address configuration register. + unsigned int tx_size ; // uDMA TX MEMCPY buffer size configuration register. + unsigned int tx_cfg ; // uDMA TX MEMCPY stream configuration register. + unsigned int dst_addr ; // MEMCPY TX destination address configuration register. + unsigned int src_addr ; // MEMCPY RX source address configuration register. + unsigned int mem_sel ; // MEMCPY memory source/destination select configuration register. +} __attribute__((packed)) udma_memcpy_udma_memcpy_t; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regs.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regs.h new file mode 100644 index 0000000..e946e56 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_regs.h @@ -0,0 +1,66 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_REGS_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_REGS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// uDMA RX MEMCPY buffer base address configuration register. +#define UDMA_MEMCPY_RX_SADDR_OFFSET 0x0 + +// uDMA RX MEMCPY buffer size configuration register. +#define UDMA_MEMCPY_RX_SIZE_OFFSET 0x4 + +// uDMA RX MEMCPY stream configuration register. +#define UDMA_MEMCPY_RX_CFG_OFFSET 0x8 + +// uDMA TX MEMCPY buffer base address configuration register. +#define UDMA_MEMCPY_TX_SADDR_OFFSET 0x10 + +// uDMA TX MEMCPY buffer size configuration register. +#define UDMA_MEMCPY_TX_SIZE_OFFSET 0x14 + +// uDMA TX MEMCPY stream configuration register. +#define UDMA_MEMCPY_TX_CFG_OFFSET 0x18 + +// MEMCPY TX destination address configuration register. +#define UDMA_MEMCPY_DST_ADDR_OFFSET 0x20 + +// MEMCPY RX source address configuration register. +#define UDMA_MEMCPY_SRC_ADDR_OFFSET 0x24 + +// MEMCPY memory source/destination select configuration register. +#define UDMA_MEMCPY_MEM_SEL_OFFSET 0x28 + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_structs.h b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_structs.h new file mode 100644 index 0000000..aaf7004 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/memcpy/v1/udma_memcpy_v1_structs.h @@ -0,0 +1,114 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_STRUCTS_H__ +#define __INCLUDE_ARCHI_UDMA_MEMCPY_V1_UDMA_MEMCPY_V1_STRUCTS_H__ + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS STRUCTS +// + +#if !defined(LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLER__) + +typedef union { + struct { + unsigned int rx_saddr :16; // RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_rx_saddr_t; + +typedef union { + struct { + unsigned int rx_size :17; // RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_rx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int padding0:3 ; + unsigned int en :1 ; // RX channel enable and start transfer bitfield: -1'b0: disable -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // RX channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear - stop and clear the on-going transfer + unsigned int pending :1 ; // RX transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1: pending - pending transfer in the queue + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_rx_cfg_t; + +typedef union { + struct { + unsigned int tx_saddr :16; // TX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets buffer base address + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_tx_saddr_t; + +typedef union { + struct { + unsigned int tx_size :17; // TX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_tx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // TX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int padding0:3 ; + unsigned int en :1 ; // TX channel enable and start transfer bitfield: -1'b0: disabled -1'b1: start - enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int clr :1 ; // TX channel clear and stop transfer bitfield: -1'b0: disabled -1'b1: stop and clear - stop and clear the on-going transfer + unsigned int pending :1 ; // TX transfer pending in queue status flag: -1'b0: no pending - no pending transfer in the queue -1'b1: pending - pending transfer in the queue + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_tx_cfg_t; + +typedef union { + struct { + unsigned int dst_addr :17; // TX destination start address configuration bitfield. MEMCPY TX transfer copy data from L2 TX_CFG.TX_SADDR address to FC_TCDM or L2 memories DST_ADDR address. + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_dst_addr_t; + +typedef union { + struct { + unsigned int src_addr :17; // RX source start address configuration bitfield. MEMCPY RX transfer copy data from FC_TCDM or L2 memories SRC_ADDR address to L2 RX_CFG.RX_SADDR address. + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_src_addr_t; + +typedef union { + struct { + unsigned int mem_sel :1 ; // Memory selection configuration bitfield: - 1'b0: L2 from/to FC_TCDM - 1'b1: L2 from/to L2 + }; + unsigned int raw; +} __attribute__((packed)) udma_memcpy_mem_sel_t; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/mram/udma_mram_v1.h b/sw/pulp-sdk/archi/include/archi/udma/mram/udma_mram_v1.h new file mode 100644 index 0000000..742ab94 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/mram/udma_mram_v1.h @@ -0,0 +1,965 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * and GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_UDMA_MRAM_UDMA_MRAM_V1_H__ +#define __INCLUDE_ARCHI_UDMA_MRAM_UDMA_MRAM_V1_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// uDMA RX UART buffer base address configuration register. +#define UDMA_MRAM_RX_SADDR_OFFSET 0x0 + +// uDMA RX UART buffer size configuration register. +#define UDMA_MRAM_RX_SIZE_OFFSET 0x4 + +// uDMA RX UART stream configuration register. +#define UDMA_MRAM_RX_CFG_OFFSET 0x8 + +// uDMA TX UART buffer base address configuration register. +#define UDMA_MRAM_TX_SADDR_OFFSET 0x10 + +// uDMA TX UART buffer size configuration register. +#define UDMA_MRAM_TX_SIZE_OFFSET 0x14 + +// uDMA TX UART stream configuration register. +#define UDMA_MRAM_TX_CFG_OFFSET 0x18 + +// Destination Address register for programing. +#define UDMA_MRAM_TX_DADDR_OFFSET 0x20 + +// Destination Address register for reading. +#define UDMA_MRAM_RX_DADDR_OFFSET 0x24 + +// MRAM status for pending operation +#define UDMA_MRAM_STATUS_OFFSET 0x28 + +// MRAM MODE: READ - ERASE - PROG - TRIM_CFG +#define UDMA_MRAM_MRAM_MODE_OFFSET 0x2c + +// Erase Address for word or Sector Erase +#define UDMA_MRAM_ERASE_ADDR_OFFSET 0x30 + +// Size of Words or Sector to erase +#define UDMA_MRAM_ERASE_SIZE_OFFSET 0x34 + +// Set Clock div Enable and Div factor. +#define UDMA_MRAM_CLOCK_DIV_OFFSET 0x38 + +// Trigger ERASE and REF_LINE INIT. +#define UDMA_MRAM_TRIGGER_OFFSET 0x3c + +// Interrupt status register. +#define UDMA_MRAM_ISR_OFFSET 0x40 + +// Interrupt enable register. +#define UDMA_MRAM_IER_OFFSET 0x44 + +// Interrupt clean register. +#define UDMA_MRAM_ICR_OFFSET 0x48 + + + +// +// REGISTERS FIELDS +// + +// RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address (access: R/W) +#define UDMA_MRAM_RX_SADDR_RX_SADDR_BIT 0 +#define UDMA_MRAM_RX_SADDR_RX_SADDR_WIDTH 16 +#define UDMA_MRAM_RX_SADDR_RX_SADDR_MASK 0xffff + +// RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define UDMA_MRAM_RX_SIZE_RX_SIZE_BIT 0 +#define UDMA_MRAM_RX_SIZE_RX_SIZE_WIDTH 17 +#define UDMA_MRAM_RX_SIZE_RX_SIZE_MASK 0x1ffff + +// RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define UDMA_MRAM_RX_CFG_CONTINOUS_BIT 0 +#define UDMA_MRAM_RX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_MRAM_RX_CFG_CONTINOUS_MASK 0x1 + +// RX channel enable and start transfer bitfield: -1'b0: disable -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_MRAM_RX_CFG_EN_BIT 4 +#define UDMA_MRAM_RX_CFG_EN_WIDTH 1 +#define UDMA_MRAM_RX_CFG_EN_MASK 0x10 + +// RX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue (access: R) +#define UDMA_MRAM_RX_CFG_PENDING_BIT 5 +#define UDMA_MRAM_RX_CFG_PENDING_WIDTH 1 +#define UDMA_MRAM_RX_CFG_PENDING_MASK 0x20 + +// RX channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear the on-going transfer (access: W) +#define UDMA_MRAM_RX_CFG_CLR_BIT 6 +#define UDMA_MRAM_RX_CFG_CLR_WIDTH 1 +#define UDMA_MRAM_RX_CFG_CLR_MASK 0x40 + +// TX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets buffer base address (access: R/W) +#define UDMA_MRAM_TX_SADDR_TX_SADDR_BIT 0 +#define UDMA_MRAM_TX_SADDR_TX_SADDR_WIDTH 16 +#define UDMA_MRAM_TX_SADDR_TX_SADDR_MASK 0xffff + +// TX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. (access: R/W) +#define UDMA_MRAM_TX_SIZE_TX_SIZE_BIT 0 +#define UDMA_MRAM_TX_SIZE_TX_SIZE_WIDTH 17 +#define UDMA_MRAM_TX_SIZE_TX_SIZE_MASK 0x1ffff + +// TX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. (access: R/W) +#define UDMA_MRAM_TX_CFG_CONTINOUS_BIT 0 +#define UDMA_MRAM_TX_CFG_CONTINOUS_WIDTH 1 +#define UDMA_MRAM_TX_CFG_CONTINOUS_MASK 0x1 + +// TX channel enable and start transfer bitfield: -1'b0: disabled -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. (access: R/W) +#define UDMA_MRAM_TX_CFG_EN_BIT 4 +#define UDMA_MRAM_TX_CFG_EN_WIDTH 1 +#define UDMA_MRAM_TX_CFG_EN_MASK 0x10 + +// TX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue (access: R) +#define UDMA_MRAM_TX_CFG_PENDING_BIT 5 +#define UDMA_MRAM_TX_CFG_PENDING_WIDTH 1 +#define UDMA_MRAM_TX_CFG_PENDING_MASK 0x20 + +// TX channel clear and stop transfer bitfield: -1'b0: disabled -1'b1: stop and clear the on-going transfer (access: W) +#define UDMA_MRAM_TX_CFG_CLR_BIT 6 +#define UDMA_MRAM_TX_CFG_CLR_WIDTH 1 +#define UDMA_MRAM_TX_CFG_CLR_MASK 0x40 + +// TX destination address (access: R/W) +#define UDMA_MRAM_TX_DADDR_TX_DST_ADDR_BIT 0 +#define UDMA_MRAM_TX_DADDR_TX_DST_ADDR_WIDTH 19 +#define UDMA_MRAM_TX_DADDR_TX_DST_ADDR_MASK 0x7ffff + +// RX destination address (access: R/W) +#define UDMA_MRAM_RX_DADDR_RX_DST_ADDR_BIT 0 +#define UDMA_MRAM_RX_DADDR_RX_DST_ADDR_WIDTH 19 +#define UDMA_MRAM_RX_DADDR_RX_DST_ADDR_MASK 0x7ffff + +// Erase pending bit: - 1'b0: not pending - 1'b1: pending (access: R) +#define UDMA_MRAM_STATUS_ERASE_PENDING_BIT 0 +#define UDMA_MRAM_STATUS_ERASE_PENDING_WIDTH 1 +#define UDMA_MRAM_STATUS_ERASE_PENDING_MASK 0x1 + +// Program busy bit: - 1'b0: not busy - 1'b1: busy (access: R) +#define UDMA_MRAM_STATUS_TX_BUSY_BIT 1 +#define UDMA_MRAM_STATUS_TX_BUSY_WIDTH 1 +#define UDMA_MRAM_STATUS_TX_BUSY_MASK 0x2 + +// Read busy bit: - 1'b0: not busy - 1'b1: busy (access: R) +#define UDMA_MRAM_STATUS_RX_BUSY_BIT 2 +#define UDMA_MRAM_STATUS_RX_BUSY_WIDTH 1 +#define UDMA_MRAM_STATUS_RX_BUSY_MASK 0x4 + +// Reference line pending bit: - 1'b0: not pending - 1'b1: pending (access: R) +#define UDMA_MRAM_STATUS_REF_LINE_PENDING_BIT 3 +#define UDMA_MRAM_STATUS_REF_LINE_PENDING_WIDTH 1 +#define UDMA_MRAM_STATUS_REF_LINE_PENDING_MASK 0x8 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_ECC_BYPS_BIT 0 +#define UDMA_MRAM_MRAM_MODE_ECC_BYPS_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_ECC_BYPS_MASK 0x1 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_DPD_BIT 1 +#define UDMA_MRAM_MRAM_MODE_DPD_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_DPD_MASK 0x2 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_AREF_BIT 2 +#define UDMA_MRAM_MRAM_MODE_AREF_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_AREF_MASK 0x4 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_TMEN_BIT 3 +#define UDMA_MRAM_MRAM_MODE_TMEN_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_TMEN_MASK 0x8 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_NVR_BIT 4 +#define UDMA_MRAM_MRAM_MODE_NVR_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_NVR_MASK 0x10 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_RST_B_BIT 5 +#define UDMA_MRAM_MRAM_MODE_RST_B_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_RST_B_MASK 0x20 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_RET_B_BIT 6 +#define UDMA_MRAM_MRAM_MODE_RET_B_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_RET_B_MASK 0x40 + +// nan (access: R/W) +#define UDMA_MRAM_MRAM_MODE_POR_B_BIT 7 +#define UDMA_MRAM_MRAM_MODE_POR_B_WIDTH 1 +#define UDMA_MRAM_MRAM_MODE_POR_B_MASK 0x80 + +// MRAM command: - 8’h1: TRIM_CFG - 8’h2: NORMAL_TX - 8’h4: ERASE_CHIP - 8’h8: ERASE_SECT - 8’h10: ERASE_WORD - 8’h20: PWDN - 8’h40: READ_RX - 8’h80: REF_LINE_P - 8’hC0: REF_LINE_AP (access: R/W) +#define UDMA_MRAM_MRAM_MODE_CMD_BIT 8 +#define UDMA_MRAM_MRAM_MODE_CMD_WIDTH 8 +#define UDMA_MRAM_MRAM_MODE_CMD_MASK 0xff00 + +// Erase address (access: R/W) +#define UDMA_MRAM_ERASE_ADDR_ADDR_BIT 0 +#define UDMA_MRAM_ERASE_ADDR_ADDR_WIDTH 19 +#define UDMA_MRAM_ERASE_ADDR_ADDR_MASK 0x7ffff + +// Clock divide data, form 0 - 255, frequency divide table is : -8’h0 - IO_FREQUENCY / 1 -8’h1 - IO_FREQUENCY / 2 -8’h2 - IO_FREQUENCY / 4 … (access: R/W) +#define UDMA_MRAM_CLOCK_DIV_DATA_BIT 0 +#define UDMA_MRAM_CLOCK_DIV_DATA_WIDTH 8 +#define UDMA_MRAM_CLOCK_DIV_DATA_MASK 0xff + +// Clock divider enable : - 1'b0: disabled - 1'b1: enabled (access: R/W) +#define UDMA_MRAM_CLOCK_DIV_EN_BIT 8 +#define UDMA_MRAM_CLOCK_DIV_EN_WIDTH 1 +#define UDMA_MRAM_CLOCK_DIV_EN_MASK 0x100 + +// Trigger enable bit: - 1'b0: disabled - 1'b1: enabled (access: W) +#define UDMA_MRAM_TRIGGER_EN_BIT 0 +#define UDMA_MRAM_TRIGGER_EN_WIDTH 1 +#define UDMA_MRAM_TRIGGER_EN_MASK 0x1 + +// Erase done bit: - 1'b0: not done - 1'b1: done (access: R) +#define UDMA_MRAM_ISR_ERASE_DONE_BIT 0 +#define UDMA_MRAM_ISR_ERASE_DONE_WIDTH 1 +#define UDMA_MRAM_ISR_ERASE_DONE_MASK 0x1 + +// Program done bit: - 1'b0: not done - 1'b1: done (access: R) +#define UDMA_MRAM_ISR_PROGRAM_DONE_BIT 1 +#define UDMA_MRAM_ISR_PROGRAM_DONE_WIDTH 1 +#define UDMA_MRAM_ISR_PROGRAM_DONE_MASK 0x2 + +// TRIM configuration done bit: - 1'b0: not done - 1'b1: done (access: R) +#define UDMA_MRAM_ISR_TRIM_CFG_DONE_BIT 2 +#define UDMA_MRAM_ISR_TRIM_CFG_DONE_WIDTH 1 +#define UDMA_MRAM_ISR_TRIM_CFG_DONE_MASK 0x4 + +// Reference line done bit: - 1'b0: not done - 1'b1: done (access: R) +#define UDMA_MRAM_ISR_REF_LINE_DONE_BIT 3 +#define UDMA_MRAM_ISR_REF_LINE_DONE_WIDTH 1 +#define UDMA_MRAM_ISR_REF_LINE_DONE_MASK 0x8 + +// Erase IRQ enable bit: - 1'b0: not enable - 1'b1: enable (access: R) +#define UDMA_MRAM_IER_ERASE_EN_BIT 0 +#define UDMA_MRAM_IER_ERASE_EN_WIDTH 1 +#define UDMA_MRAM_IER_ERASE_EN_MASK 0x1 + +// Program IRQ enable bit: - 1'b0: not enable - 1'b1: enable (access: R) +#define UDMA_MRAM_IER_PROGRAM_EN_BIT 1 +#define UDMA_MRAM_IER_PROGRAM_EN_WIDTH 1 +#define UDMA_MRAM_IER_PROGRAM_EN_MASK 0x2 + +// TRIM configuration IRQ enable bit: - 1'b0: not enable - 1'b1: enable (access: R) +#define UDMA_MRAM_IER_TRIM_CFG_EN_BIT 2 +#define UDMA_MRAM_IER_TRIM_CFG_EN_WIDTH 1 +#define UDMA_MRAM_IER_TRIM_CFG_EN_MASK 0x4 + +// Reference line IRQ enable bit: - 1'b0: not enable - 1'b1: enable (access: R) +#define UDMA_MRAM_IER_REF_LINE_EN_BIT 3 +#define UDMA_MRAM_IER_REF_LINE_EN_WIDTH 1 +#define UDMA_MRAM_IER_REF_LINE_EN_MASK 0x8 + +// Erase clean IRQ bit: - 1'b0: not clean - 1'b1: clean (access: R) +#define UDMA_MRAM_ICR_ERASE_DONE_BIT 0 +#define UDMA_MRAM_ICR_ERASE_DONE_WIDTH 1 +#define UDMA_MRAM_ICR_ERASE_DONE_MASK 0x1 + +// Program clean IRQ bit: - 1'b0: not clean - 1'b1: clean (access: R) +#define UDMA_MRAM_ICR_PROGRAM_DONE_BIT 1 +#define UDMA_MRAM_ICR_PROGRAM_DONE_WIDTH 1 +#define UDMA_MRAM_ICR_PROGRAM_DONE_MASK 0x2 + +// TRIM configuration clean IRQ bit: - 1'b0: not clean - 1'b1: clean (access: R) +#define UDMA_MRAM_ICR_TRIM_CFG_DONE_BIT 2 +#define UDMA_MRAM_ICR_TRIM_CFG_DONE_WIDTH 1 +#define UDMA_MRAM_ICR_TRIM_CFG_DONE_MASK 0x4 + +// Reference line clean IRQ bit: - 1'b0: not clean - 1'b1: clean (access: R) +#define UDMA_MRAM_ICR_REF_LINE_DONE_BIT 3 +#define UDMA_MRAM_ICR_REF_LINE_DONE_WIDTH 1 +#define UDMA_MRAM_ICR_REF_LINE_DONE_MASK 0x8 + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + unsigned int rx_saddr :16; // RX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets RX buffer base address + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_rx_saddr_t; + +typedef union { + struct { + unsigned int rx_size :17; // RX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_rx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // RX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int padding0:3 ; + unsigned int en :1 ; // RX channel enable and start transfer bitfield: -1'b0: disable -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int pending :1 ; // RX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue + unsigned int clr :1 ; // RX channel clear and stop transfer: -1'b0: disable -1'b1: stop and clear the on-going transfer + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_rx_cfg_t; + +typedef union { + struct { + unsigned int tx_saddr :16; // TX buffer base address bitfield: - Read: returns value of the buffer pointer until transfer is finished. Else returns 0. - Write: sets buffer base address + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_tx_saddr_t; + +typedef union { + struct { + unsigned int tx_size :17; // TX buffer size bitfield in bytes. (128kBytes maximum) - Read: returns remaining buffer size to transfer. - Write: sets buffer size. + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_tx_size_t; + +typedef union { + struct { + unsigned int continous :1 ; // TX channel continuous mode bitfield: -1'b0: disabled -1'b1: enabled At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer. + unsigned int padding0:3 ; + unsigned int en :1 ; // TX channel enable and start transfer bitfield: -1'b0: disabled -1'b1: enable and start the transfer This signal is used also to queue a transfer if one is already ongoing. + unsigned int pending :1 ; // TX transfer pending in queue status flag: -1'b0: no pending transfer in the queue -1'b1: pending transfer in the queue + unsigned int clr :1 ; // TX channel clear and stop transfer bitfield: -1'b0: disabled -1'b1: stop and clear the on-going transfer + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_tx_cfg_t; + +typedef union { + struct { + unsigned int tx_dst_addr :19; // TX destination address + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_tx_daddr_t; + +typedef union { + struct { + unsigned int rx_dst_addr :19; // RX destination address + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_rx_daddr_t; + +typedef union { + struct { + unsigned int erase_pending :1 ; // Erase pending bit: - 1'b0: not pending - 1'b1: pending + unsigned int tx_busy :1 ; // Program busy bit: - 1'b0: not busy - 1'b1: busy + unsigned int rx_busy :1 ; // Read busy bit: - 1'b0: not busy - 1'b1: busy + unsigned int ref_line_pending:1 ; // Reference line pending bit: - 1'b0: not pending - 1'b1: pending + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_status_t; + +typedef union { + struct { + unsigned int ecc_byps :1 ; // nan + unsigned int dpd :1 ; // nan + unsigned int aref :1 ; // nan + unsigned int tmen :1 ; // nan + unsigned int nvr :1 ; // nan + unsigned int rst_b :1 ; // nan + unsigned int ret_b :1 ; // nan + unsigned int por_b :1 ; // nan + unsigned int cmd :8 ; // MRAM command: - 8’h1: TRIM_CFG - 8’h2: NORMAL_TX - 8’h4: ERASE_CHIP - 8’h8: ERASE_SECT - 8’h10: ERASE_WORD - 8’h20: PWDN - 8’h40: READ_RX - 8’h80: REF_LINE_P - 8’hC0: REF_LINE_AP + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_mram_mode_t; + +typedef union { + struct { + unsigned int addr :19; // Erase address + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_erase_addr_t; + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_erase_size_t; + +typedef union { + struct { + unsigned int data :8 ; // Clock divide data, form 0 - 255, frequency divide table is : -8’h0 - IO_FREQUENCY / 1 -8’h1 - IO_FREQUENCY / 2 -8’h2 - IO_FREQUENCY / 4 … + unsigned int en :1 ; // Clock divider enable : - 1'b0: disabled - 1'b1: enabled + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_clock_div_t; + +typedef union { + struct { + unsigned int en :1 ; // Trigger enable bit: - 1'b0: disabled - 1'b1: enabled + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_trigger_t; + +typedef union { + struct { + unsigned int erase_done :1 ; // Erase done bit: - 1'b0: not done - 1'b1: done + unsigned int program_done :1 ; // Program done bit: - 1'b0: not done - 1'b1: done + unsigned int trim_cfg_done :1 ; // TRIM configuration done bit: - 1'b0: not done - 1'b1: done + unsigned int ref_line_done :1 ; // Reference line done bit: - 1'b0: not done - 1'b1: done + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_isr_t; + +typedef union { + struct { + unsigned int erase_en :1 ; // Erase IRQ enable bit: - 1'b0: not enable - 1'b1: enable + unsigned int program_en :1 ; // Program IRQ enable bit: - 1'b0: not enable - 1'b1: enable + unsigned int trim_cfg_en :1 ; // TRIM configuration IRQ enable bit: - 1'b0: not enable - 1'b1: enable + unsigned int ref_line_en :1 ; // Reference line IRQ enable bit: - 1'b0: not enable - 1'b1: enable + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_ier_t; + +typedef union { + struct { + unsigned int erase_done :1 ; // Erase clean IRQ bit: - 1'b0: not clean - 1'b1: clean + unsigned int program_done :1 ; // Program clean IRQ bit: - 1'b0: not clean - 1'b1: clean + unsigned int trim_cfg_done :1 ; // TRIM configuration clean IRQ bit: - 1'b0: not clean - 1'b1: clean + unsigned int ref_line_done :1 ; // Reference line clean IRQ bit: - 1'b0: not clean - 1'b1: clean + }; + unsigned int raw; +} __attribute__((packed)) udma_mram_icr_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_udma_mram_rx_saddr : public vp::reg_32 +{ +public: + inline void rx_saddr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_RX_SADDR_RX_SADDR_BIT, UDMA_MRAM_RX_SADDR_RX_SADDR_WIDTH); } + inline uint32_t rx_saddr_get() { return this->get_field(UDMA_MRAM_RX_SADDR_RX_SADDR_BIT, UDMA_MRAM_RX_SADDR_RX_SADDR_WIDTH); } +}; + +class vp_udma_mram_rx_size : public vp::reg_32 +{ +public: + inline void rx_size_set(uint32_t value) { this->set_field(value, UDMA_MRAM_RX_SIZE_RX_SIZE_BIT, UDMA_MRAM_RX_SIZE_RX_SIZE_WIDTH); } + inline uint32_t rx_size_get() { return this->get_field(UDMA_MRAM_RX_SIZE_RX_SIZE_BIT, UDMA_MRAM_RX_SIZE_RX_SIZE_WIDTH); } +}; + +class vp_udma_mram_rx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_MRAM_RX_CFG_CONTINOUS_BIT, UDMA_MRAM_RX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_MRAM_RX_CFG_CONTINOUS_BIT, UDMA_MRAM_RX_CFG_CONTINOUS_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_RX_CFG_EN_BIT, UDMA_MRAM_RX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_MRAM_RX_CFG_EN_BIT, UDMA_MRAM_RX_CFG_EN_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_MRAM_RX_CFG_PENDING_BIT, UDMA_MRAM_RX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_MRAM_RX_CFG_PENDING_BIT, UDMA_MRAM_RX_CFG_PENDING_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_RX_CFG_CLR_BIT, UDMA_MRAM_RX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_MRAM_RX_CFG_CLR_BIT, UDMA_MRAM_RX_CFG_CLR_WIDTH); } +}; + +class vp_udma_mram_tx_saddr : public vp::reg_32 +{ +public: + inline void tx_saddr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TX_SADDR_TX_SADDR_BIT, UDMA_MRAM_TX_SADDR_TX_SADDR_WIDTH); } + inline uint32_t tx_saddr_get() { return this->get_field(UDMA_MRAM_TX_SADDR_TX_SADDR_BIT, UDMA_MRAM_TX_SADDR_TX_SADDR_WIDTH); } +}; + +class vp_udma_mram_tx_size : public vp::reg_32 +{ +public: + inline void tx_size_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TX_SIZE_TX_SIZE_BIT, UDMA_MRAM_TX_SIZE_TX_SIZE_WIDTH); } + inline uint32_t tx_size_get() { return this->get_field(UDMA_MRAM_TX_SIZE_TX_SIZE_BIT, UDMA_MRAM_TX_SIZE_TX_SIZE_WIDTH); } +}; + +class vp_udma_mram_tx_cfg : public vp::reg_32 +{ +public: + inline void continous_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TX_CFG_CONTINOUS_BIT, UDMA_MRAM_TX_CFG_CONTINOUS_WIDTH); } + inline uint32_t continous_get() { return this->get_field(UDMA_MRAM_TX_CFG_CONTINOUS_BIT, UDMA_MRAM_TX_CFG_CONTINOUS_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TX_CFG_EN_BIT, UDMA_MRAM_TX_CFG_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_MRAM_TX_CFG_EN_BIT, UDMA_MRAM_TX_CFG_EN_WIDTH); } + inline void pending_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TX_CFG_PENDING_BIT, UDMA_MRAM_TX_CFG_PENDING_WIDTH); } + inline uint32_t pending_get() { return this->get_field(UDMA_MRAM_TX_CFG_PENDING_BIT, UDMA_MRAM_TX_CFG_PENDING_WIDTH); } + inline void clr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TX_CFG_CLR_BIT, UDMA_MRAM_TX_CFG_CLR_WIDTH); } + inline uint32_t clr_get() { return this->get_field(UDMA_MRAM_TX_CFG_CLR_BIT, UDMA_MRAM_TX_CFG_CLR_WIDTH); } +}; + +class vp_udma_mram_tx_daddr : public vp::reg_32 +{ +public: + inline void tx_dst_addr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TX_DADDR_TX_DST_ADDR_BIT, UDMA_MRAM_TX_DADDR_TX_DST_ADDR_WIDTH); } + inline uint32_t tx_dst_addr_get() { return this->get_field(UDMA_MRAM_TX_DADDR_TX_DST_ADDR_BIT, UDMA_MRAM_TX_DADDR_TX_DST_ADDR_WIDTH); } +}; + +class vp_udma_mram_rx_daddr : public vp::reg_32 +{ +public: + inline void rx_dst_addr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_RX_DADDR_RX_DST_ADDR_BIT, UDMA_MRAM_RX_DADDR_RX_DST_ADDR_WIDTH); } + inline uint32_t rx_dst_addr_get() { return this->get_field(UDMA_MRAM_RX_DADDR_RX_DST_ADDR_BIT, UDMA_MRAM_RX_DADDR_RX_DST_ADDR_WIDTH); } +}; + +class vp_udma_mram_status : public vp::reg_32 +{ +public: + inline void erase_pending_set(uint32_t value) { this->set_field(value, UDMA_MRAM_STATUS_ERASE_PENDING_BIT, UDMA_MRAM_STATUS_ERASE_PENDING_WIDTH); } + inline uint32_t erase_pending_get() { return this->get_field(UDMA_MRAM_STATUS_ERASE_PENDING_BIT, UDMA_MRAM_STATUS_ERASE_PENDING_WIDTH); } + inline void tx_busy_set(uint32_t value) { this->set_field(value, UDMA_MRAM_STATUS_TX_BUSY_BIT, UDMA_MRAM_STATUS_TX_BUSY_WIDTH); } + inline uint32_t tx_busy_get() { return this->get_field(UDMA_MRAM_STATUS_TX_BUSY_BIT, UDMA_MRAM_STATUS_TX_BUSY_WIDTH); } + inline void rx_busy_set(uint32_t value) { this->set_field(value, UDMA_MRAM_STATUS_RX_BUSY_BIT, UDMA_MRAM_STATUS_RX_BUSY_WIDTH); } + inline uint32_t rx_busy_get() { return this->get_field(UDMA_MRAM_STATUS_RX_BUSY_BIT, UDMA_MRAM_STATUS_RX_BUSY_WIDTH); } + inline void ref_line_pending_set(uint32_t value) { this->set_field(value, UDMA_MRAM_STATUS_REF_LINE_PENDING_BIT, UDMA_MRAM_STATUS_REF_LINE_PENDING_WIDTH); } + inline uint32_t ref_line_pending_get() { return this->get_field(UDMA_MRAM_STATUS_REF_LINE_PENDING_BIT, UDMA_MRAM_STATUS_REF_LINE_PENDING_WIDTH); } +}; + +class vp_udma_mram_mram_mode : public vp::reg_32 +{ +public: + inline void ecc_byps_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_ECC_BYPS_BIT, UDMA_MRAM_MRAM_MODE_ECC_BYPS_WIDTH); } + inline uint32_t ecc_byps_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_ECC_BYPS_BIT, UDMA_MRAM_MRAM_MODE_ECC_BYPS_WIDTH); } + inline void dpd_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_DPD_BIT, UDMA_MRAM_MRAM_MODE_DPD_WIDTH); } + inline uint32_t dpd_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_DPD_BIT, UDMA_MRAM_MRAM_MODE_DPD_WIDTH); } + inline void aref_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_AREF_BIT, UDMA_MRAM_MRAM_MODE_AREF_WIDTH); } + inline uint32_t aref_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_AREF_BIT, UDMA_MRAM_MRAM_MODE_AREF_WIDTH); } + inline void tmen_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_TMEN_BIT, UDMA_MRAM_MRAM_MODE_TMEN_WIDTH); } + inline uint32_t tmen_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_TMEN_BIT, UDMA_MRAM_MRAM_MODE_TMEN_WIDTH); } + inline void nvr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_NVR_BIT, UDMA_MRAM_MRAM_MODE_NVR_WIDTH); } + inline uint32_t nvr_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_NVR_BIT, UDMA_MRAM_MRAM_MODE_NVR_WIDTH); } + inline void rst_b_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_RST_B_BIT, UDMA_MRAM_MRAM_MODE_RST_B_WIDTH); } + inline uint32_t rst_b_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_RST_B_BIT, UDMA_MRAM_MRAM_MODE_RST_B_WIDTH); } + inline void ret_b_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_RET_B_BIT, UDMA_MRAM_MRAM_MODE_RET_B_WIDTH); } + inline uint32_t ret_b_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_RET_B_BIT, UDMA_MRAM_MRAM_MODE_RET_B_WIDTH); } + inline void por_b_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_POR_B_BIT, UDMA_MRAM_MRAM_MODE_POR_B_WIDTH); } + inline uint32_t por_b_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_POR_B_BIT, UDMA_MRAM_MRAM_MODE_POR_B_WIDTH); } + inline void cmd_set(uint32_t value) { this->set_field(value, UDMA_MRAM_MRAM_MODE_CMD_BIT, UDMA_MRAM_MRAM_MODE_CMD_WIDTH); } + inline uint32_t cmd_get() { return this->get_field(UDMA_MRAM_MRAM_MODE_CMD_BIT, UDMA_MRAM_MRAM_MODE_CMD_WIDTH); } +}; + +class vp_udma_mram_erase_addr : public vp::reg_32 +{ +public: + inline void addr_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ERASE_ADDR_ADDR_BIT, UDMA_MRAM_ERASE_ADDR_ADDR_WIDTH); } + inline uint32_t addr_get() { return this->get_field(UDMA_MRAM_ERASE_ADDR_ADDR_BIT, UDMA_MRAM_ERASE_ADDR_ADDR_WIDTH); } +}; + +class vp_udma_mram_erase_size : public vp::reg_32 +{ +public: +}; + +class vp_udma_mram_clock_div : public vp::reg_32 +{ +public: + inline void data_set(uint32_t value) { this->set_field(value, UDMA_MRAM_CLOCK_DIV_DATA_BIT, UDMA_MRAM_CLOCK_DIV_DATA_WIDTH); } + inline uint32_t data_get() { return this->get_field(UDMA_MRAM_CLOCK_DIV_DATA_BIT, UDMA_MRAM_CLOCK_DIV_DATA_WIDTH); } + inline void en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_CLOCK_DIV_EN_BIT, UDMA_MRAM_CLOCK_DIV_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_MRAM_CLOCK_DIV_EN_BIT, UDMA_MRAM_CLOCK_DIV_EN_WIDTH); } +}; + +class vp_udma_mram_trigger : public vp::reg_32 +{ +public: + inline void en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_TRIGGER_EN_BIT, UDMA_MRAM_TRIGGER_EN_WIDTH); } + inline uint32_t en_get() { return this->get_field(UDMA_MRAM_TRIGGER_EN_BIT, UDMA_MRAM_TRIGGER_EN_WIDTH); } +}; + +class vp_udma_mram_isr : public vp::reg_32 +{ +public: + inline void erase_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ISR_ERASE_DONE_BIT, UDMA_MRAM_ISR_ERASE_DONE_WIDTH); } + inline uint32_t erase_done_get() { return this->get_field(UDMA_MRAM_ISR_ERASE_DONE_BIT, UDMA_MRAM_ISR_ERASE_DONE_WIDTH); } + inline void program_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ISR_PROGRAM_DONE_BIT, UDMA_MRAM_ISR_PROGRAM_DONE_WIDTH); } + inline uint32_t program_done_get() { return this->get_field(UDMA_MRAM_ISR_PROGRAM_DONE_BIT, UDMA_MRAM_ISR_PROGRAM_DONE_WIDTH); } + inline void trim_cfg_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ISR_TRIM_CFG_DONE_BIT, UDMA_MRAM_ISR_TRIM_CFG_DONE_WIDTH); } + inline uint32_t trim_cfg_done_get() { return this->get_field(UDMA_MRAM_ISR_TRIM_CFG_DONE_BIT, UDMA_MRAM_ISR_TRIM_CFG_DONE_WIDTH); } + inline void ref_line_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ISR_REF_LINE_DONE_BIT, UDMA_MRAM_ISR_REF_LINE_DONE_WIDTH); } + inline uint32_t ref_line_done_get() { return this->get_field(UDMA_MRAM_ISR_REF_LINE_DONE_BIT, UDMA_MRAM_ISR_REF_LINE_DONE_WIDTH); } +}; + +class vp_udma_mram_ier : public vp::reg_32 +{ +public: + inline void erase_en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_IER_ERASE_EN_BIT, UDMA_MRAM_IER_ERASE_EN_WIDTH); } + inline uint32_t erase_en_get() { return this->get_field(UDMA_MRAM_IER_ERASE_EN_BIT, UDMA_MRAM_IER_ERASE_EN_WIDTH); } + inline void program_en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_IER_PROGRAM_EN_BIT, UDMA_MRAM_IER_PROGRAM_EN_WIDTH); } + inline uint32_t program_en_get() { return this->get_field(UDMA_MRAM_IER_PROGRAM_EN_BIT, UDMA_MRAM_IER_PROGRAM_EN_WIDTH); } + inline void trim_cfg_en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_IER_TRIM_CFG_EN_BIT, UDMA_MRAM_IER_TRIM_CFG_EN_WIDTH); } + inline uint32_t trim_cfg_en_get() { return this->get_field(UDMA_MRAM_IER_TRIM_CFG_EN_BIT, UDMA_MRAM_IER_TRIM_CFG_EN_WIDTH); } + inline void ref_line_en_set(uint32_t value) { this->set_field(value, UDMA_MRAM_IER_REF_LINE_EN_BIT, UDMA_MRAM_IER_REF_LINE_EN_WIDTH); } + inline uint32_t ref_line_en_get() { return this->get_field(UDMA_MRAM_IER_REF_LINE_EN_BIT, UDMA_MRAM_IER_REF_LINE_EN_WIDTH); } +}; + +class vp_udma_mram_icr : public vp::reg_32 +{ +public: + inline void erase_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ICR_ERASE_DONE_BIT, UDMA_MRAM_ICR_ERASE_DONE_WIDTH); } + inline uint32_t erase_done_get() { return this->get_field(UDMA_MRAM_ICR_ERASE_DONE_BIT, UDMA_MRAM_ICR_ERASE_DONE_WIDTH); } + inline void program_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ICR_PROGRAM_DONE_BIT, UDMA_MRAM_ICR_PROGRAM_DONE_WIDTH); } + inline uint32_t program_done_get() { return this->get_field(UDMA_MRAM_ICR_PROGRAM_DONE_BIT, UDMA_MRAM_ICR_PROGRAM_DONE_WIDTH); } + inline void trim_cfg_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ICR_TRIM_CFG_DONE_BIT, UDMA_MRAM_ICR_TRIM_CFG_DONE_WIDTH); } + inline uint32_t trim_cfg_done_get() { return this->get_field(UDMA_MRAM_ICR_TRIM_CFG_DONE_BIT, UDMA_MRAM_ICR_TRIM_CFG_DONE_WIDTH); } + inline void ref_line_done_set(uint32_t value) { this->set_field(value, UDMA_MRAM_ICR_REF_LINE_DONE_BIT, UDMA_MRAM_ICR_REF_LINE_DONE_WIDTH); } + inline uint32_t ref_line_done_get() { return this->get_field(UDMA_MRAM_ICR_REF_LINE_DONE_BIT, UDMA_MRAM_ICR_REF_LINE_DONE_WIDTH); } +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int rx_saddr ; // uDMA RX UART buffer base address configuration register. + unsigned int rx_size ; // uDMA RX UART buffer size configuration register. + unsigned int rx_cfg ; // uDMA RX UART stream configuration register. + unsigned int tx_saddr ; // uDMA TX UART buffer base address configuration register. + unsigned int tx_size ; // uDMA TX UART buffer size configuration register. + unsigned int tx_cfg ; // uDMA TX UART stream configuration register. + unsigned int tx_daddr ; // Destination Address register for programing. + unsigned int rx_daddr ; // Destination Address register for reading. + unsigned int status ; // MRAM status for pending operation + unsigned int mram_mode ; // MRAM MODE: READ - ERASE - PROG - TRIM_CFG + unsigned int erase_addr ; // Erase Address for word or Sector Erase + unsigned int erase_size ; // Size of Words or Sector to erase + unsigned int clock_div ; // Set Clock div Enable and Div factor. + unsigned int trigger ; // Trigger ERASE and REF_LINE INIT. + unsigned int isr ; // Interrupt status register. + unsigned int ier ; // Interrupt enable register. + unsigned int icr ; // Interrupt clean register. +} __attribute__((packed)) udma_mram_udma_mram_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t udma_mram_rx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_RX_SADDR_OFFSET); } +static inline void udma_mram_rx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_RX_SADDR_OFFSET, value); } + +static inline uint32_t udma_mram_rx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_RX_SIZE_OFFSET); } +static inline void udma_mram_rx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_RX_SIZE_OFFSET, value); } + +static inline uint32_t udma_mram_rx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_RX_CFG_OFFSET); } +static inline void udma_mram_rx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_RX_CFG_OFFSET, value); } + +static inline uint32_t udma_mram_tx_saddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_TX_SADDR_OFFSET); } +static inline void udma_mram_tx_saddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_TX_SADDR_OFFSET, value); } + +static inline uint32_t udma_mram_tx_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_TX_SIZE_OFFSET); } +static inline void udma_mram_tx_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_TX_SIZE_OFFSET, value); } + +static inline uint32_t udma_mram_tx_cfg_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_TX_CFG_OFFSET); } +static inline void udma_mram_tx_cfg_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_TX_CFG_OFFSET, value); } + +static inline uint32_t udma_mram_tx_daddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_TX_DADDR_OFFSET); } +static inline void udma_mram_tx_daddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_TX_DADDR_OFFSET, value); } + +static inline uint32_t udma_mram_rx_daddr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_RX_DADDR_OFFSET); } +static inline void udma_mram_rx_daddr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_RX_DADDR_OFFSET, value); } + +static inline uint32_t udma_mram_status_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_STATUS_OFFSET); } +static inline void udma_mram_status_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_STATUS_OFFSET, value); } + +static inline uint32_t udma_mram_mram_mode_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_MRAM_MODE_OFFSET); } +static inline void udma_mram_mram_mode_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_MRAM_MODE_OFFSET, value); } + +static inline uint32_t udma_mram_erase_addr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_ERASE_ADDR_OFFSET); } +static inline void udma_mram_erase_addr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_ERASE_ADDR_OFFSET, value); } + +static inline uint32_t udma_mram_erase_size_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_ERASE_SIZE_OFFSET); } +static inline void udma_mram_erase_size_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_ERASE_SIZE_OFFSET, value); } + +static inline uint32_t udma_mram_clock_div_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_CLOCK_DIV_OFFSET); } +static inline void udma_mram_clock_div_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_CLOCK_DIV_OFFSET, value); } + +static inline uint32_t udma_mram_trigger_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_TRIGGER_OFFSET); } +static inline void udma_mram_trigger_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_TRIGGER_OFFSET, value); } + +static inline uint32_t udma_mram_isr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_ISR_OFFSET); } +static inline void udma_mram_isr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_ISR_OFFSET, value); } + +static inline uint32_t udma_mram_ier_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_IER_OFFSET); } +static inline void udma_mram_ier_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_IER_OFFSET, value); } + +static inline uint32_t udma_mram_icr_get(uint32_t base) { return ARCHI_READ(base, UDMA_MRAM_ICR_OFFSET); } +static inline void udma_mram_icr_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, UDMA_MRAM_ICR_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#define UDMA_MRAM_RX_SADDR_RX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_MRAM_RX_SADDR_RX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_MRAM_RX_SADDR_RX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_MRAM_RX_SADDR_RX_SADDR(val) ((val) << 0) + +#define UDMA_MRAM_RX_SIZE_RX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_MRAM_RX_SIZE_RX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_MRAM_RX_SIZE_RX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_MRAM_RX_SIZE_RX_SIZE(val) ((val) << 0) + +#define UDMA_MRAM_RX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_RX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_RX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_RX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_MRAM_RX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_MRAM_RX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_MRAM_RX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_MRAM_RX_CFG_EN(val) ((val) << 4) + +#define UDMA_MRAM_RX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_MRAM_RX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_MRAM_RX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_MRAM_RX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_MRAM_RX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define UDMA_MRAM_RX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define UDMA_MRAM_RX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define UDMA_MRAM_RX_CFG_CLR(val) ((val) << 6) + +#define UDMA_MRAM_TX_SADDR_TX_SADDR_GET(value) (ARCHI_BEXTRACTU((value),16,0)) +#define UDMA_MRAM_TX_SADDR_TX_SADDR_GETS(value) (ARCHI_BEXTRACT((value),16,0)) +#define UDMA_MRAM_TX_SADDR_TX_SADDR_SET(value,field) (ARCHI_BINSERT((value),(field),16,0)) +#define UDMA_MRAM_TX_SADDR_TX_SADDR(val) ((val) << 0) + +#define UDMA_MRAM_TX_SIZE_TX_SIZE_GET(value) (ARCHI_BEXTRACTU((value),17,0)) +#define UDMA_MRAM_TX_SIZE_TX_SIZE_GETS(value) (ARCHI_BEXTRACT((value),17,0)) +#define UDMA_MRAM_TX_SIZE_TX_SIZE_SET(value,field) (ARCHI_BINSERT((value),(field),17,0)) +#define UDMA_MRAM_TX_SIZE_TX_SIZE(val) ((val) << 0) + +#define UDMA_MRAM_TX_CFG_CONTINOUS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_TX_CFG_CONTINOUS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_TX_CFG_CONTINOUS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_TX_CFG_CONTINOUS(val) ((val) << 0) + +#define UDMA_MRAM_TX_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_MRAM_TX_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_MRAM_TX_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_MRAM_TX_CFG_EN(val) ((val) << 4) + +#define UDMA_MRAM_TX_CFG_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_MRAM_TX_CFG_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_MRAM_TX_CFG_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_MRAM_TX_CFG_PENDING(val) ((val) << 5) + +#define UDMA_MRAM_TX_CFG_CLR_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define UDMA_MRAM_TX_CFG_CLR_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define UDMA_MRAM_TX_CFG_CLR_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define UDMA_MRAM_TX_CFG_CLR(val) ((val) << 6) + +#define UDMA_MRAM_TX_DADDR_TX_DST_ADDR_GET(value) (ARCHI_BEXTRACTU((value),19,0)) +#define UDMA_MRAM_TX_DADDR_TX_DST_ADDR_GETS(value) (ARCHI_BEXTRACT((value),19,0)) +#define UDMA_MRAM_TX_DADDR_TX_DST_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),19,0)) +#define UDMA_MRAM_TX_DADDR_TX_DST_ADDR(val) ((val) << 0) + +#define UDMA_MRAM_RX_DADDR_RX_DST_ADDR_GET(value) (ARCHI_BEXTRACTU((value),19,0)) +#define UDMA_MRAM_RX_DADDR_RX_DST_ADDR_GETS(value) (ARCHI_BEXTRACT((value),19,0)) +#define UDMA_MRAM_RX_DADDR_RX_DST_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),19,0)) +#define UDMA_MRAM_RX_DADDR_RX_DST_ADDR(val) ((val) << 0) + +#define UDMA_MRAM_STATUS_ERASE_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_STATUS_ERASE_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_STATUS_ERASE_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_STATUS_ERASE_PENDING(val) ((val) << 0) + +#define UDMA_MRAM_STATUS_TX_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define UDMA_MRAM_STATUS_TX_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define UDMA_MRAM_STATUS_TX_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define UDMA_MRAM_STATUS_TX_BUSY(val) ((val) << 1) + +#define UDMA_MRAM_STATUS_RX_BUSY_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define UDMA_MRAM_STATUS_RX_BUSY_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define UDMA_MRAM_STATUS_RX_BUSY_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define UDMA_MRAM_STATUS_RX_BUSY(val) ((val) << 2) + +#define UDMA_MRAM_STATUS_REF_LINE_PENDING_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define UDMA_MRAM_STATUS_REF_LINE_PENDING_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define UDMA_MRAM_STATUS_REF_LINE_PENDING_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define UDMA_MRAM_STATUS_REF_LINE_PENDING(val) ((val) << 3) + +#define UDMA_MRAM_MRAM_MODE_ECC_BYPS_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_MRAM_MODE_ECC_BYPS_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_MRAM_MODE_ECC_BYPS_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_MRAM_MODE_ECC_BYPS(val) ((val) << 0) + +#define UDMA_MRAM_MRAM_MODE_DPD_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define UDMA_MRAM_MRAM_MODE_DPD_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define UDMA_MRAM_MRAM_MODE_DPD_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define UDMA_MRAM_MRAM_MODE_DPD(val) ((val) << 1) + +#define UDMA_MRAM_MRAM_MODE_AREF_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define UDMA_MRAM_MRAM_MODE_AREF_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define UDMA_MRAM_MRAM_MODE_AREF_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define UDMA_MRAM_MRAM_MODE_AREF(val) ((val) << 2) + +#define UDMA_MRAM_MRAM_MODE_TMEN_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define UDMA_MRAM_MRAM_MODE_TMEN_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define UDMA_MRAM_MRAM_MODE_TMEN_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define UDMA_MRAM_MRAM_MODE_TMEN(val) ((val) << 3) + +#define UDMA_MRAM_MRAM_MODE_NVR_GET(value) (ARCHI_BEXTRACTU((value),1,4)) +#define UDMA_MRAM_MRAM_MODE_NVR_GETS(value) (ARCHI_BEXTRACT((value),1,4)) +#define UDMA_MRAM_MRAM_MODE_NVR_SET(value,field) (ARCHI_BINSERT((value),(field),1,4)) +#define UDMA_MRAM_MRAM_MODE_NVR(val) ((val) << 4) + +#define UDMA_MRAM_MRAM_MODE_RST_B_GET(value) (ARCHI_BEXTRACTU((value),1,5)) +#define UDMA_MRAM_MRAM_MODE_RST_B_GETS(value) (ARCHI_BEXTRACT((value),1,5)) +#define UDMA_MRAM_MRAM_MODE_RST_B_SET(value,field) (ARCHI_BINSERT((value),(field),1,5)) +#define UDMA_MRAM_MRAM_MODE_RST_B(val) ((val) << 5) + +#define UDMA_MRAM_MRAM_MODE_RET_B_GET(value) (ARCHI_BEXTRACTU((value),1,6)) +#define UDMA_MRAM_MRAM_MODE_RET_B_GETS(value) (ARCHI_BEXTRACT((value),1,6)) +#define UDMA_MRAM_MRAM_MODE_RET_B_SET(value,field) (ARCHI_BINSERT((value),(field),1,6)) +#define UDMA_MRAM_MRAM_MODE_RET_B(val) ((val) << 6) + +#define UDMA_MRAM_MRAM_MODE_POR_B_GET(value) (ARCHI_BEXTRACTU((value),1,7)) +#define UDMA_MRAM_MRAM_MODE_POR_B_GETS(value) (ARCHI_BEXTRACT((value),1,7)) +#define UDMA_MRAM_MRAM_MODE_POR_B_SET(value,field) (ARCHI_BINSERT((value),(field),1,7)) +#define UDMA_MRAM_MRAM_MODE_POR_B(val) ((val) << 7) + +#define UDMA_MRAM_MRAM_MODE_CMD_GET(value) (ARCHI_BEXTRACTU((value),8,8)) +#define UDMA_MRAM_MRAM_MODE_CMD_GETS(value) (ARCHI_BEXTRACT((value),8,8)) +#define UDMA_MRAM_MRAM_MODE_CMD_SET(value,field) (ARCHI_BINSERT((value),(field),8,8)) +#define UDMA_MRAM_MRAM_MODE_CMD(val) ((val) << 8) + +#define UDMA_MRAM_ERASE_ADDR_ADDR_GET(value) (ARCHI_BEXTRACTU((value),19,0)) +#define UDMA_MRAM_ERASE_ADDR_ADDR_GETS(value) (ARCHI_BEXTRACT((value),19,0)) +#define UDMA_MRAM_ERASE_ADDR_ADDR_SET(value,field) (ARCHI_BINSERT((value),(field),19,0)) +#define UDMA_MRAM_ERASE_ADDR_ADDR(val) ((val) << 0) + +#define UDMA_MRAM_CLOCK_DIV_DATA_GET(value) (ARCHI_BEXTRACTU((value),8,0)) +#define UDMA_MRAM_CLOCK_DIV_DATA_GETS(value) (ARCHI_BEXTRACT((value),8,0)) +#define UDMA_MRAM_CLOCK_DIV_DATA_SET(value,field) (ARCHI_BINSERT((value),(field),8,0)) +#define UDMA_MRAM_CLOCK_DIV_DATA(val) ((val) << 0) + +#define UDMA_MRAM_CLOCK_DIV_EN_GET(value) (ARCHI_BEXTRACTU((value),1,8)) +#define UDMA_MRAM_CLOCK_DIV_EN_GETS(value) (ARCHI_BEXTRACT((value),1,8)) +#define UDMA_MRAM_CLOCK_DIV_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,8)) +#define UDMA_MRAM_CLOCK_DIV_EN(val) ((val) << 8) + +#define UDMA_MRAM_TRIGGER_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_TRIGGER_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_TRIGGER_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_TRIGGER_EN(val) ((val) << 0) + +#define UDMA_MRAM_ISR_ERASE_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_ISR_ERASE_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_ISR_ERASE_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_ISR_ERASE_DONE(val) ((val) << 0) + +#define UDMA_MRAM_ISR_PROGRAM_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define UDMA_MRAM_ISR_PROGRAM_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define UDMA_MRAM_ISR_PROGRAM_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define UDMA_MRAM_ISR_PROGRAM_DONE(val) ((val) << 1) + +#define UDMA_MRAM_ISR_TRIM_CFG_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define UDMA_MRAM_ISR_TRIM_CFG_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define UDMA_MRAM_ISR_TRIM_CFG_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define UDMA_MRAM_ISR_TRIM_CFG_DONE(val) ((val) << 2) + +#define UDMA_MRAM_ISR_REF_LINE_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define UDMA_MRAM_ISR_REF_LINE_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define UDMA_MRAM_ISR_REF_LINE_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define UDMA_MRAM_ISR_REF_LINE_DONE(val) ((val) << 3) + +#define UDMA_MRAM_IER_ERASE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_IER_ERASE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_IER_ERASE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_IER_ERASE_EN(val) ((val) << 0) + +#define UDMA_MRAM_IER_PROGRAM_EN_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define UDMA_MRAM_IER_PROGRAM_EN_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define UDMA_MRAM_IER_PROGRAM_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define UDMA_MRAM_IER_PROGRAM_EN(val) ((val) << 1) + +#define UDMA_MRAM_IER_TRIM_CFG_EN_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define UDMA_MRAM_IER_TRIM_CFG_EN_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define UDMA_MRAM_IER_TRIM_CFG_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define UDMA_MRAM_IER_TRIM_CFG_EN(val) ((val) << 2) + +#define UDMA_MRAM_IER_REF_LINE_EN_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define UDMA_MRAM_IER_REF_LINE_EN_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define UDMA_MRAM_IER_REF_LINE_EN_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define UDMA_MRAM_IER_REF_LINE_EN(val) ((val) << 3) + +#define UDMA_MRAM_ICR_ERASE_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,0)) +#define UDMA_MRAM_ICR_ERASE_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,0)) +#define UDMA_MRAM_ICR_ERASE_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,0)) +#define UDMA_MRAM_ICR_ERASE_DONE(val) ((val) << 0) + +#define UDMA_MRAM_ICR_PROGRAM_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,1)) +#define UDMA_MRAM_ICR_PROGRAM_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,1)) +#define UDMA_MRAM_ICR_PROGRAM_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,1)) +#define UDMA_MRAM_ICR_PROGRAM_DONE(val) ((val) << 1) + +#define UDMA_MRAM_ICR_TRIM_CFG_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,2)) +#define UDMA_MRAM_ICR_TRIM_CFG_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,2)) +#define UDMA_MRAM_ICR_TRIM_CFG_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,2)) +#define UDMA_MRAM_ICR_TRIM_CFG_DONE(val) ((val) << 2) + +#define UDMA_MRAM_ICR_REF_LINE_DONE_GET(value) (ARCHI_BEXTRACTU((value),1,3)) +#define UDMA_MRAM_ICR_REF_LINE_DONE_GETS(value) (ARCHI_BEXTRACT((value),1,3)) +#define UDMA_MRAM_ICR_REF_LINE_DONE_SET(value,field) (ARCHI_BINSERT((value),(field),1,3)) +#define UDMA_MRAM_ICR_REF_LINE_DONE(val) ((val) << 3) + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/spim/udma_spim_v1.h b/sw/pulp-sdk/archi/include/archi/udma/spim/udma_spim_v1.h new file mode 100644 index 0000000..9035f60 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/spim/udma_spim_v1.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_SPIM_V1_H__ +#define __ARCHI_UDMA_UDMA_SPIM_V1_H__ + +#define SPIM_RX_SADDR_OFFSET 0x000 +#define SPIM_RX_SIZE_OFFSET 0x004 +#define SPIM_RX_CFG_OFFSET 0x008 +#define SPIM_RX_INTCFG_OFFSET 0x00C + +#define SPIM_TX_SADDR_OFFSET 0x010 +#define SPIM_TX_SIZE_OFFSET 0x014 +#define SPIM_TX_CFG_OFFSET 0x018 +#define SPIM_TX_INTCFG_OFFSET 0x01C + +#define SPIM_STATUS_OFFSET 0x000 +#define SPIM_CLKDIV_OFFSET 0x004 +#define SPIM_SPICMD_OFFSET 0x008 +#define SPIM_SPIADR_OFFSET 0x00C +#define SPIM_SPILEN_OFFSET 0x010 +#define SPIM_SPIDUM_OFFSET 0x014 +#define SPIM_TXFIFO_OFFSET 0x018 +#define SPIM_RXFIFO_OFFSET 0x01C + + +#define ARCHI_SPIM_WSTATUS_QWRITE 8 +#define ARCHI_SPIM_WSTATUS_QREAD 4 +#define ARCHI_SPIM_WSTATUS_WRITE 2 +#define ARCHI_SPIM_WSTATUS_READ 1 + +#define ARCHI_SPIM_WSTATUS_CSKEEP_BIT 16 +#define ARCHI_SPIM_WSTATUS_CS_BIT 8 +#define ARCHI_SPIM_WSTATUS_RESET_BIT 4 +#define ARCHI_SPIM_WSTATUS_CMD_BIT 0 + +#define ARCHI_SPIM_RSTATUS_DATA_RX_BIT 6 +#define ARCHI_SPIM_RSTATUS_DATA_TX_BIT 5 +#define ARCHI_SPIM_RSTATUS_DUMMY_BIT 4 +#define ARCHI_SPIM_RSTATUS_MODE_BIT 3 +#define ARCHI_SPIM_RSTATUS_ADDR_BIT 2 +#define ARCHI_SPIM_RSTATUS_CMD_BIT 1 +#define ARCHI_SPIM_RSTATUS_IDLE_BIT 0 + +#define ARCHI_SPIM_CLKDIV_DATASIZE_TX_BIT 18 +#define ARCHI_SPIM_CLKDIV_DATASIZE_RX_BIT 16 +#define ARCHI_SPIM_CLKDIV_CPHA_BIT 9 +#define ARCHI_SPIM_CLKDIV_CPOL_BIT 8 +#define ARCHI_SPIM_CLKDIV_CLKDIV_BIT 0 + +#define SPIM_CMD_RD 0 +#define SPIM_CMD_WR 1 +#define SPIM_CMD_QRD 2 +#define SPIM_CMD_QWR 3 + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/udma/spim/udma_spim_v2.h b/sw/pulp-sdk/archi/include/archi/udma/spim/udma_spim_v2.h new file mode 100644 index 0000000..0d5dd87 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/spim/udma_spim_v2.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_SPIM_V2_H__ +#define __ARCHI_UDMA_UDMA_SPIM_V2_H__ + +// SPI commands IDS definition +#define SPI_CMD_CFG_ID 0 +#define SPI_CMD_SOT_ID 1 +#define SPI_CMD_SEND_CMD_ID 2 +#define SPI_CMD_SEND_ADDR_ID 3 +#define SPI_CMD_DUMMY_ID 4 +#define SPI_CMD_WAIT_ID 5 +#define SPI_CMD_TX_DATA_ID 6 +#define SPI_CMD_RX_DATA_ID 7 +#define SPI_CMD_RPT_ID 8 +#define SPI_CMD_EOT_ID 9 +#define SPI_CMD_RPT_END_ID 10 +#define SPI_CMD_RX_CHECK_ID 11 +#define SPI_CMD_FUL_ID 12 + +// SPI command fields offset, mask, value definition +// SPI commands fields offsets +#define SPI_CMD_ID_OFFSET 28 +#define SPI_CMD_ID_WIDTH 4 + +// COMMON definitions +#define SPI_CMD_QPI_ENA 1 +#define SPI_CMD_QPI_DIS 0 +#define SPI_CMD_BYTE_ALIGN_DIS 1 +#define SPI_CMD_BYTE_ALIGN_ENA 0 +#define SPI_CMD_DATA_WITDH(val) (val) +#define SPI_CMD_CMD_SIZE(val) (val) + +// CFG +#define SPI_CMD_CFG_CLK_DIV_OFFSET 0 +#define SPI_CMD_CFG_CLK_DIV_WIDTH 8 +#define SPI_CMD_CFG_CPHA_OFFSET 8 +#define SPI_CMD_CFG_CPOL_OFFSET 9 + +#define SPI_CMD_CFG_CLKDIV(val) (val) +#define SPI_CMD_CFG_CPOL_POS 1 +#define SPI_CMD_CFG_CPOL_NEG 0 +#define SPI_CMD_CFG_CPHA_STD 1 +#define SPI_CMD_CFG_CPHA_OPP 0 + +// SOT +#define SPI_CMD_SOT_CS_OFFSET 0 +#define SPI_CMD_SOT_CS_WIDTH 2 + +#define SPI_CMD_SOT_CS0 0 +#define SPI_CMD_SOT_CS1 1 +#define SPI_CMD_SOT_CS2 2 +#define SPI_CMD_SOT_CS3 3 + +// SEND_CMD +#define SPI_CMD_SEND_CMD_CMD_OFFSET 0 +#define SPI_CMD_SEND_CMD_CMD_WIDTH 16 +#define SPI_CMD_SEND_CMD_SIZE_OFFSET 16 +#define SPI_CMD_SEND_CMD_SIZE_WIDTH 4 +#define SPI_CMD_SEND_CMD_QPI_OFFSET 27 + +// SEND_ADDR +#define SPI_CMD_SEND_ADDR_SIZE_OFFSET 16 +#define SPI_CMD_SEND_ADDR_SIZE_WIDTH 5 +#define SPI_CMD_SEND_ADDR_QPI_OFFSET 27 + +//#define SPI_CMD_SEND_ADDR_VALUE(value) ((((value) & 0xff000000) >> 24) | (((value) & 0xff0000) >> 8) | (((value) & 0xff00) << 8) | (((value) & 0xff) << 24)) +#define SPI_CMD_SEND_ADDR_VALUE(value) (value) + + +// SEND_DUMMY +#define SPI_CMD_DUMMY_CYCLE_OFFSET 16 +#define SPI_CMD_DUMMY_CYCLE_WIDTH 5 + +// TX_DATA +#define SPI_CMD_TX_DATA_SIZE_OFFSET 0 +#define SPI_CMD_TX_DATA_SIZE_WIDTH 16 +#define SPI_CMD_TX_DATA_BYTE_ALIGN_OFFSET 26 +#define SPI_CMD_TX_DATA_QPI_OFFSET 27 + +// RX_DATA +#define SPI_CMD_RX_DATA_SIZE_OFFSET 0 +#define SPI_CMD_RX_DATA_SIZE_WIDTH 16 +#define SPI_CMD_RX_DATA_BYTE_ALIGN_OFFSET 26 +#define SPI_CMD_RX_DATA_BYTE_ALIGN_WIDTH 1 +#define SPI_CMD_RX_DATA_QPI_OFFSET 27 +#define SPI_CMD_RX_DATA_QPI_WIDTH 1 + +// RPT +#define SPI_CMD_RPT_NB_OFFSET 0 +#define SPI_CMD_RPT_NB_WIDTH 16 + +// EOT +#define SPI_CMD_EOT_GEN_EVT_OFFSET 0 + +#define SPI_CMD_EOT_EVENT_ENA 1 +#define SPI_CMD_EOT_EVENT_DIS 0 + +// WAIT +#define SPI_CMD_WAIT_EVENT_OFFSET 0 +#define SPI_CMD_WAIT_EVENT_WIDTH 2 + +// RX_CHECK +#define SPI_CMD_RX_CHECK_VALUE_OFFSET 0 +#define SPI_CMD_RX_CHECK_VALUE_WIDTH 16 + +#define SPI_CMD_RX_CHECK_SIZE_OFFSET 16 +#define SPI_CMD_RX_CHECK_SIZE_WIDTH 4 + +#define SPI_CMD_RX_CHECK_MODE_OFFSET 24 +#define SPI_CMD_RX_CHECK_MODE_WIDTH 2 + +#define SPI_CMD_RX_CHECK_BYTE_ALIGN_OFFSET 26 + +#define SPI_CMD_RX_CHECK_QPI_OFFSET 27 + +#define SPI_CMD_RX_CHECK_MODE_MATCH 0 +#define SPI_CMD_RX_CHECK_MODE_ONES 1 +#define SPI_CMD_RX_CHECK_MODE_ZEROS 2 +#define SPI_CMD_RX_CHECK_MODE_MASK 3 + +// FULL DUPLEX +#define SPI_CMD_FUL_SIZE_OFFSET 0 +#define SPI_CMD_FUL_SIZE_WIDTH 16 +#define SPI_CMD_FUL_BYTE_ALIGN_OFFSET 26 +#define SPI_CMD_FUL_BYTE_ALIGN_WIDTH 1 + +// SPI CMD encoding +#define SPI_CMD_CFG(clockDiv,cpol,cpha) ((SPI_CMD_CFG_ID<>8)<> 24) | (((value) & 0xff0000) >> 8) | (((value) & 0xff00) << 8) | (((value) & 0xff) << 24)) +#define SPI_CMD_SEND_ADDR_VALUE(value) (value) + + +// SEND_DUMMY +#define SPI_CMD_DUMMY_CYCLE_OFFSET 16 +#define SPI_CMD_DUMMY_CYCLE_WIDTH 5 + +// TX_DATA +#define SPI_CMD_TX_DATA_SIZE_OFFSET 0 +#define SPI_CMD_TX_DATA_SIZE_WIDTH 16 +#define SPI_CMD_TX_DATA_QPI_OFFSET 27 +#define SPI_CMD_TX_DATA_WORDTRANS_OFFSET 21 +#define SPI_CMD_TX_DATA_WORDTRANS_WIDTH 2 +#define SPI_CMD_TX_DATA_LSBFIRST_OFFSET 26 +#define SPI_CMD_TX_DATA_BITSWORD_OFFSET 16 +#define SPI_CMD_TX_DATA_BITSWORD_WIDTH 5 + + +// RX_DATA +#define SPI_CMD_RX_DATA_SIZE_OFFSET 0 +#define SPI_CMD_RX_DATA_SIZE_WIDTH 16 +#define SPI_CMD_RX_DATA_QPI_OFFSET 27 +#define SPI_CMD_RX_DATA_WORDTRANS_OFFSET 21 +#define SPI_CMD_RX_DATA_WORDTRANS_WIDTH 2 +#define SPI_CMD_RX_DATA_LSBFIRST_OFFSET 26 +#define SPI_CMD_RX_DATA_BITSWORD_OFFSET 16 +#define SPI_CMD_RX_DATA_BITSWORD_WIDTH 5 + + +// RPT +#define SPI_CMD_RPT_NB_OFFSET 0 +#define SPI_CMD_RPT_NB_WIDTH 16 + +// EOT +#define SPI_CMD_EOT_GEN_EVT_OFFSET 0 +#define SPI_CMD_EOT_CS_KEEP_OFFSET 1 + +#define SPI_CMD_EOT_EVENT_ENA 1 +#define SPI_CMD_EOT_EVENT_DIS 0 + +// WAIT +#define SPI_CMD_WAIT_EVENT_OFFSET 0 +#define SPI_CMD_WAIT_EVENT_WIDTH 2 + +// RX_CHECK +#define SPI_CMD_RX_CHECK_VALUE_OFFSET 0 +#define SPI_CMD_RX_CHECK_VALUE_WIDTH 16 + +#define SPI_CMD_RX_CHECK_SIZE_OFFSET 16 +#define SPI_CMD_RX_CHECK_SIZE_WIDTH 4 + +#define SPI_CMD_RX_CHECK_MODE_OFFSET 24 +#define SPI_CMD_RX_CHECK_MODE_WIDTH 2 + +#define SPI_CMD_RX_CHECK_BYTE_ALIGN_OFFSET 26 + +#define SPI_CMD_RX_CHECK_QPI_OFFSET 27 + +#define SPI_CMD_RX_CHECK_MODE_MATCH 0 +#define SPI_CMD_RX_CHECK_MODE_ONES 1 +#define SPI_CMD_RX_CHECK_MODE_ZEROS 2 +#define SPI_CMD_RX_CHECK_MODE_MASK 3 + +// FULL DUPLEX +#define SPI_CMD_FUL_SIZE_OFFSET 0 +#define SPI_CMD_FUL_SIZE_WIDTH 16 +#define SPI_CMD_FUL_WORDTRANS_OFFSET 21 +#define SPI_CMD_FUL_WORDTRANS_WIDTH 2 +#define SPI_CMD_FUL_LSBFIRST_OFFSET 26 +#define SPI_CMD_FUL_BITSWORD_OFFSET 16 +#define SPI_CMD_FUL_BITSWORD_WIDTH 5 + +#define SPI_CMD_SETUP_UC_TXRXEN_OFFSET 27 +#define SPI_CMD_SETUP_UC_DS_OFFSET 25 + +// SPI CMD encoding +#define SPI_CMD_CFG(clockDiv,cpol,cpha) ((SPI_CMD_CFG_ID<>UDMA_PERIPH_AREA_SIZE_LOG2) + +// Return the offset of a channel from its identifier +#define UDMA_CHANNEL_OFFSET(id) ((id)*UDMA_CHANNEL_SIZE) + +// Returns the identifier of a channel from its offset +#define UDMA_CHANNEL_GET(offset) ((offset)>>UDMA_CHANNEL_SIZE_LOG2) + + + + + + + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/udma/udma_v2.h b/sw/pulp-sdk/archi/include/archi/udma/udma_v2.h new file mode 100644 index 0000000..7633a0d --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/udma/udma_v2.h @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_UDMA_UDMA_V2_H__ +#define __ARCHI_UDMA_UDMA_V2_H__ + +/* + * Global register map + */ + +// The UDMA register map is made of several channels, each channel area size is defined just below + +// Periph area size in log2 +#define UDMA_PERIPH_AREA_SIZE_LOG2 7 + +// Periph area size +#define UDMA_PERIPH_AREA_SIZE (1<>UDMA_PERIPH_AREA_SIZE_LOG2) + +// Return the offset of a channel from its identifier +#define UDMA_CHANNEL_OFFSET(id) ((id)<>UDMA_CHANNEL_SIZE_LOG2) + +// Return the id of a channel from the peripheral id +#define UDMA_CHANNEL_ID(id) ((id)*2) + +// Return the number of events per peripheral +#define UDMA_NB_PERIPH_EVENTS_LOG2 1 +#define UDMA_NB_PERIPH_EVENTS (1<>UDMA_PERIPH_AREA_SIZE_LOG2) + +// Return the offset of a channel from its identifier +#define UDMA_CHANNEL_OFFSET(id) ((id)<>UDMA_CHANNEL_SIZE_LOG2) + +// Return the id of a channel from the peripheral id +#define UDMA_CHANNEL_ID(id) ((id)*2) + +// Return the number of events per peripheral +#define UDMA_NB_PERIPH_EVENTS_LOG2 2 +#define UDMA_NB_PERIPH_EVENTS (1<> (offset)) + + +#ifndef LANGUAGE_ASSEMBLY + +#define archi_write8(add, val_) (*(volatile unsigned char *)(long)(add) = val_) +#define archi_write16(add, val_) (*(volatile unsigned short *)(long)(add) = val_) +#define archi_write32(add, val_) (*(volatile unsigned int *)(long)(add) = val_) +#define archi_write(add, val_) (*(volatile unsigned int *)(long)(add) = val_) + +#define archi_read8(add) (*(volatile unsigned char *)(long)(add)) +#define archi_read16(add) (*(volatile unsigned short *)(long)(add)) +#define archi_read32(add) (*(volatile unsigned int *)(long)(add)) +#define archi_read(add) (*(volatile unsigned int *)(long)(add)) + + +#if defined(__riscv__) && !defined(__LLVM__) && !defined(RV_ISA_RV32) +#define ARCHI_WRITE_VOL(base, offset, value) __builtin_pulp_write_base_off_v((value), (base), (offset)) +#define ARCHI_WRITE(base, offset, value) __builtin_pulp_OffsetedWrite((value), (int *)(base), (offset)) +#define ARCHI_READ(base, offset) __builtin_pulp_OffsetedRead((int *)(base), (offset)) +#else +#define ARCHI_WRITE_VOL(base, offset, value) archi_write32((base) + (offset), (value)) +#define ARCHI_WRITE(base, offset, value) archi_write32((base) + (offset), (value)) +#define ARCHI_READ(base, offset) archi_read32((base) + (offset)) +#endif + + +#include "archi/riscv/builtins_v2.h" +#include "archi/riscv/builtins_v2_emu.h" + +#define ARCHI_BINSERT(dst,src,size,off) __BITINSERT(dst,src,size,off) +#define ARCHI_BINSERT_R(dst,src,size,off) __BITINSERT_R(dst,src,size,off) +#define ARCHI_BEXTRACTU(src,size,off) __BITEXTRACTU(src,size,off) +#define ARCHI_BEXTRACT(src,size,off) __BITEXTRACT(src,size,off) + +#endif + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/archi/include/archi/vendors/dolphin/rtc.h b/sw/pulp-sdk/archi/include/archi/vendors/dolphin/rtc.h new file mode 100644 index 0000000..de53751 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/vendors/dolphin/rtc.h @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_RTC_H__ +#define __ARCHI_RTC_H__ + +/* + * The RTC should be used through the APB interface. In this header file, there are: + * - APB registers which are direct access registers, with ADDR: ( SOC_PERIPHERALS_BASE_ADDR + 0x7000 + APB_RTC_**_OFFSET) + * - RTC registers which are indirect access registers. These regs should be R/W via the APB registers. + * + * For distinguishing these two types of registers: + * - APB registers: All the defines are named in UPPER_CASE + * - RTC registers: All the difines are named in Initial_Capitalization + * + * ARCHI_RTC_ADDR = ( SOC_PERIPHERALS_BASE_ADDR + 0x8000 ) + */ + + +#define RTC_RTC_INT_EVENT ARCHI_SOC_EVENT_RTC_IRQ +#define RTC_RTC_APB_EVENT ARCHI_SOC_EVENT_RTC_APB_IRQ + +// Address of APB registers +#define APB_RTC_STAT_OFFSET 0x00 +#define APB_RTC_CTRL_OFFSET 0x04 +#define APB_RTC_DATA_OFFSET 0x08 +#define APB_RTC_IRQ_CTRL_OFFSET 0x10 +#define APB_RTC_IRQ_MASK_OFFSET 0x14 +#define APB_RTC_IRQ_FLAG_OFFSET 0x18 + +#define APB_RTC_STAT_REG_ADDR (ARCHI_RTC_ADDR + APB_RTC_STAT_OFFSET) +#define APB_RTC_CTRL_REG_ADDR (ARCHI_RTC_ADDR + APB_RTC_CTRL_OFFSET) +#define APB_RTC_DATA_REG_ADDR (ARCHI_RTC_ADDR + APB_RTC_DATA_OFFSET) +#define APB_RTC_IRQ_CTRL_REG_ADDR (ARCHI_RTC_ADDR + APB_RTC_IRQ_CTRL_OFFSET) +#define APB_RTC_IRQ_MASK_REG_ADDR (ARCHI_RTC_ADDR + APB_RTC_IRQ_MASK_OFFSET) +#define APB_RTC_IRQ_FLAG_REG_ADDR (ARCHI_RTC_ADDR + APB_RTC_IRQ_FLAG_OFFSET) + +// Bit field of APB registers +#define APB_RTC_NOIRQ_REQ 0x00 // APB_RTC_Status [0:1] +#define APB_RTC_IRQ_REQ 0x01 // APB_RTC_Status [0:1] +#define APB_RTC_READ 0x00 +#define APB_RTC_WRITE 0x01 +#define APB_IRQ_HIGH_LEVEL 0x00 // The generated INT_APB is a high level +#define APB_IRQ_LOW_LEVEL 0x01 // The generated INT_APB is a low level +#define APB_IRQ_HIGH_LEVEL_PULSE 0x02 // The generated INT_APB is a high level pulse with a duration of 1 CKIN cycle +#define APB_IRQ_LOW_LEVEL_PULSE 0x03 // The generated INT_APB is a low level pulse with a duration of 1 CKIN cycle +#define APB_WRITE_IRQ_MASKED 0x01 // 0x0 APB Write Operation Irq Enabled +#define APB_READ_IRQ_MASKED 0x01 // 0x0 APB Read Operation Irq Enabled +#define APB_W_Flag 0x02 // b'1 of APB_RTC_IRQ_FLAG_REG_ADDR +#define APB_R_Flag 0x01 // b'0 of APB_RTC_IRQ_FLAG_REG_ADDR +#define APB_SR_MASK 0x03 + +//***************************************************** +// Address of Indirect Access Register +//***************************************************** +#define RTC_Status_Addr 0x00 +#define RTC_Ctrl_Addr 0x01 +#define RTC_Clk_Ctrl_Addr 0x02 +#define RTC_IRQ_Ctrl_Addr 0x08 +#define RTC_IRQ_Mask_Addr 0x09 +#define RTC_IRQ_Flag_Addr 0x0A +#define RTC_Calendar_Ctrl_Addr 0x10 +#define RTC_Calendar_TIME_Addr 0x12 +#define RTC_Calendar_DATE_Addr 0x13 +#define RTC_Alarm_Ctrl_Addr 0x18 +#define RTC_Alarm1_TIME_Addr 0x1A +#define RTC_Alarm1_DATE_Addr 0x1B +#define RTC_CntDown_Ctrl_Addr 0x20 +#define RTC_CntDown1_Init_Addr 0x21 +#define RTC_CntDown1_Timer_Addr 0x22 +#define RTC_CKIN_DIV1_Addr 0x28 +#define RTC_Ref_Clk_Conf_Addr 0x2A +#define RTC_Test_Addr 0x30 + +// Bit field of RTC indirect Access Register +#define RTC_IRQ_REQ 0x01 // RTC_Status [0:1] +#define RTC_Soft_Reset 0x01 // 0x00: No soft reset +#define RTC_Calibration_Enable 0x01 // 0x00: Calibration disable +#define RTC_Active_Mode 0x00 +#define RTC_Standby_Mode 0x01 +#define RTC_CKOUT_Auto_Calibrated 0x01 // 0x00: CKOUT not auto calibrated +#define RTC_CKOUT_Not_Generated 0x01 // 0x00: CKOUT is generated +#define RTC_Irq_High_Level 0x00 // The generated INT_RTC is a high level +#define RTC_Irq_Low_Level 0x01 // The generated INT_RTC is a low level +#define RTC_Irq_High_Level_Pulse 0x02 // The generated INT_RTC is a high level pulse with a duration of 1 CKIN cycle +#define RTC_Irq_Low_Level_Pulse 0x03 // The generated INT_RTC is a low level pulse with a duration of 1 CKIN cycle +#define RTC_Calibration_Irq_Masked 0x01 // Calibration Irq Enabled +#define RTC_Timer1_Irq_Enable 0x00 // Countdown timer 1 irq enabled +#define RTC_Timer1_Irq_Masked 0x01 // Countdown timer 1 irq masked; +#define RTC_Alarm1_Irq_Enable 0x00 // Alarm 1 irq masked; When 0 Alarm 1 irq enabled +#define RTC_Alarm1_Irq_Masked 0x01 // Alarm 1 irq masked; When 0 Alarm 1 irq enabled +#define RTC_Calendar_Inactive 0x01 // 0x0: Calendar is active +#define RTC_Alarm_Rpt_Mode 0x01 // 0x0: Single Mode +#define RTC_Alarm_ON 0x00 // 0x0: Alarm1 is active +#define RTC_Alarm_OFF 0x01 // 0x0: Alarm1 is active +#define RTC_CountDown1_Rpt_Mode 0x01 // 0x0: Single Mode +#define RTC_CountDown1_Active 0x00 // 0x0: Countdown 1 is active +#define RTC_CountDown1_Inactive 0x01 + +#define RTC_Irq_Alarm1_Flag 0x01 +#define RTC_Irq_Timer1_Flag 0x10 +#define RTC_Irq_Calibration_Flag 0x1000 + +#ifndef LANGUAGE_ASSEMBLY + +/* Structure for APB RTC registers */ +typedef union { + struct { + unsigned int apb_addr:6; // Indirect access address, address range [0:3F] + unsigned int pad:10; + unsigned int apb_load:1; /* Indirect access load bit: + 0: APB read operation + 1: APB write operation + */ + unsigned int pad1:15; + }; + unsigned int raw; +}Apb_rtc_ctrlT; + +typedef union { + struct { + unsigned int irq_form:2; + unsigned int pad:30; + }; + unsigned int raw; +}Apb_irq_ctrlT; + +typedef union { + struct { + unsigned int readMask:1; + unsigned int writeMask:1; + unsigned int pad:30; + }; + unsigned int raw; +}Apb_irq_maskT; + +typedef union{ + Apb_rtc_ctrlT rtcCtrl; + Apb_irq_ctrlT irqCtrl; + Apb_irq_maskT irqMask; + unsigned int Raw; +}Apb_rtcT; + +//============================================================= +/* Structure for indirect access registers */ + +typedef union { + struct{ + unsigned int rtc_sb:1; + unsigned int pad:3; + unsigned int cal_En:1; + unsigned int pad1:3; + unsigned int soft_rst:1; + unsigned int pad2:23; + }; + unsigned int raw; +}Rtc_ctrlT; + +typedef union{ + struct{ + unsigned int clkOut_sb:1; + unsigned int pad:11; + unsigned int div1_autoCal:1; + unsigned int pad1:3; + unsigned int div1_comp:5; + unsigned int pad2:11; + }; + unsigned int raw; +}Rtc_clk_ctrlT; + +typedef union{ + struct{ + unsigned int irq_form:2; + unsigned int pad:30; + }; + unsigned int raw; +}Rtc_irq_ctrlT; + +typedef union{ + struct{ + unsigned int alarm1_masked:1; + unsigned int pad:3; + unsigned int timer1_masked:1; + unsigned int pad1:7; + unsigned int cal_masked:1; + unsigned int pad2:19; + }; + unsigned int raw; +}Rtc_irq_maskT; + +typedef union{ + struct{ + unsigned int calend_En:1; + unsigned int pad:31; + }; + unsigned int raw; +}Rtc_calend_ctrlT; + +typedef union{ + struct{ + unsigned int second_0:4; + unsigned int second_1:4; + unsigned int minute_0:4; + unsigned int minute_1:4; + unsigned int hour_0:4; + unsigned int hour_1:4; + }; + unsigned int raw; +}Rtc_calend_timeT; + +typedef union{ + struct{ + unsigned int day_0:4; + unsigned int day_1:4; + unsigned int month_0:4; + unsigned int month_1:4; + unsigned int year_0:4; + unsigned int year_1:4; + }; + unsigned int raw; +}Rtc_calend_dateT; + +typedef union{ + struct{ + unsigned int alarm1_En:1; + unsigned int pad:3; + unsigned int alarm1_mode:1; + unsigned int pad1:11; + unsigned int alarm1_conf:4; + unsigned int pad2:12; + }; + unsigned int raw; +}Rtc_alarm_ctrlT; + +typedef union{ + struct{ + unsigned int cntDwn1_En:1; + unsigned int pad:3; + unsigned int cntDwn1_mode:1; + unsigned int pad1:27; + }; + unsigned int raw; +}Rtc_cntDwn_ctrlT; + +typedef union { + struct{ + unsigned int divVal:16; + unsigned int pad:16; + }; + unsigned int raw; +}Rtc_CKIN_divT; + +typedef union{ + struct{ + unsigned int refClkVal:22; + unsigned int pad:10; + }; + unsigned int raw; +}Rtc_ref_clkT; + +typedef union{ +// unsigned int status; + Rtc_ctrlT conf; + Rtc_clk_ctrlT clkConf; + Rtc_irq_ctrlT irqConf; + Rtc_irq_maskT irqMask; +// unsigned int irqFlag; + Rtc_calend_ctrlT calendConf; +// unsigned int calendTime; +// unsigned int calendDate; + Rtc_alarm_ctrlT alarmCtrl; +// unsigned int alarmTime; +// unsigned int alarmDate; + Rtc_cntDwn_ctrlT cntDwnCtrl; +// unsigned int cntDwn1InitVal; +// unsigned int cntDwn1Val; + Rtc_CKIN_divT ckinDiv; + Rtc_ref_clkT refClk; + unsigned int Raw; +}RtcT; + +#endif + +#endif diff --git a/sw/pulp-sdk/archi/include/archi/vendors/iid/quiddikey_v1.h b/sw/pulp-sdk/archi/include/archi/vendors/iid/quiddikey_v1.h new file mode 100644 index 0000000..5337910 --- /dev/null +++ b/sw/pulp-sdk/archi/include/archi/vendors/iid/quiddikey_v1.h @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_IID_QUIDDIKEY_V1_H__ +#define __ARCHI_IID_QUIDDIKEY_V1_H__ + +// Registers offset definition +#define APB_QK_CR_OFFSET (0x00) +#define APB_QK_SR_OFFSET (0x08) +#define APB_QK_AR_OFFSET (0x0C) +#define APB_QK_IER_OFFSET (0x10) +#define APB_QK_IMR_OFFSET (0x14) +#define APB_QK_ISR_OFFSET (0x18) +#define APB_QK_KEY_DEST_OFFSET (0x20) +#define APB_QK_DIR_OFFSET (0xA0) +#define APB_QK_DOR_OFFSET (0xA8) +#define APB_QK_MISC_OFFSET (0xC0) +#define APB_QK_IF_SR_OFFSET (0xD0) +#define APB_QK_TEST_OFFSET (0xD8) +#define APB_QK_HW_RUC0_OFFSET (0xE0) +#define APB_QK_HW_RUC1_OFFSET (0xE4) +#define APB_QK_HW_SET_OFFSET (0xF0) +#define APB_QK_HW_INFO_OFFSET (0xF4) +#define APB_QK_HW_ID_OFFSET (0xF8) +#define APB_QK_HW_VER_OFFSET (0xFC) + +// Registers bitfields offset, mask, value definition +// Configuration Register +#define APB_QK_CR_ZEROISE_BIT (0) +#define APB_QK_CR_ZEROISE_BITS (1) +#define APB_QK_CR_ZEROISE_MASK ARCHI_REG_MASK(APB_QK_CR_ZEROISE_BIT, APB_QK_CR_ZEROISE_BITS) +#define APB_QK_CR_ZEROISE_ENA (1< + * + * Copyright (C) 2014-2017 ETH Zurich, University of Bologna + * All rights reserved. + */ + +#ifndef __ARCHI_XNE_V1_H__ +#define __ARCHI_XNE_V1_H__ + +/* + * Control and generic configuration register layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0000 | 31: 0 | 0xffffffff || TRIGGER + * 1 | 0x0004 | 31: 0 | 0xffffffff || ACQUIRE + * 2 | 0x0008 | 31: 0 | 0xffffffff || EVT_ENABLE + * 3 | 0x000c | 31: 0 | 0xffffffff || STATUS + * 4 | 0x0010 | 31: 0 | 0xffffffff || RUNNING_JOB + * 5 | 0x0014 | 31: 0 | 0xffffffff || SOFT_CLEAR + * 6-7 | | | || Reserved + * 8 | 0x0020 | 31: 0 | 0xffffffff || BYTECODE0 [31:0] + * 9 | 0x0024 | 31: 0 | 0xffffffff || BYTECODE1 [63:32] + * 10 | 0x0028 | 31: 0 | 0xffffffff || BYTECODE2 [95:64] + * 11 | 0x002c | 31: 0 | 0xffffffff || BYTECODE3 [127:96] + * 12 | 0x0030 | 31: 0 | 0xffffffff || BYTECODE4 [159:128] + * 13 | 0x0034 | 31:16 | 0xffff0000 || LOOPS0 [15:0] + * | | 15: 0 | 0x0000ffff || BYTECODE5 [175:160] + * 14 | 0x0038 | 31: 0 | 0xffffffff || LOOPS1 [47:16] + * 15 | | 31: 0 | 0xffffffff || Reserved + * ================================================================================ + * + * Job-dependent registers layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0040 | 31: 0 | 0xffffffff || X_ADDR + * 1 | 0x0044 | 31: 0 | 0xffffffff || W_ADDR + * 2 | 0x0048 | 31: 0 | 0xffffffff || Y_ADDR + * 3 | 0x004c | 31:24 | 0xff000000 || UCODE_STATIC0.w + * | | 23:16 | 0x00ff0000 || UCODE_STATIC0.h + * | | 15: 8 | 0x0000ff00 || UCODE_STATIC0.ow + * | | 7: 0 | 0x000000ff || UCODE_STATIC0.oh + * 4 | 0x0050 | 31:24 | 0xff000000 || UCODE_STATIC1.fs0 + * | | 23:16 | 0x00ff0000 || UCODE_STATIC1.fs1 + * | | 7: 0 | 0x000000ff || UCODE_STATIC1.acc + * 5 | 0x0054 | 27:16 | 0x0fff0000 || UCODE_STATIC2.nif + * | | 11: 0 | 0x00000fff || UCODE_STATIC2.nof + * 6 | 0x0058 | 31: 0 | 0xffffffff || TAU_ADDR + * 7 | 0x005c | 3: 0 | 0x0000000f || TAU_SHIFT + * ================================================================================ + * + */ + +#define XNE_TRIGGER 0x00 +#define XNE_ACQUIRE 0x04 +#define XNE_FINISHED 0x08 +#define XNE_STATUS 0x0c +#define XNE_RUNNING_JOB 0x10 +#define XNE_SOFT_CLEAR 0x14 + +#define XNE_BYTECODE 0x20 +#define XNE_BYTECODE0_OFFS 0x00 +#define XNE_BYTECODE1_OFFS 0x04 +#define XNE_BYTECODE2_OFFS 0x08 +#define XNE_BYTECODE3_OFFS 0x0c +#define XNE_BYTECODE4_OFFS 0x10 +#define XNE_BYTECODE5_LOOPS0_OFFS 0x14 +#define XNE_LOOPS1_OFFS 0x18 + +#define XNE_X_ADDR 0x40 +#define XNE_W_ADDR 0x44 +#define XNE_Y_ADDR 0x48 +#define XNE_UCODE_STATIC0 0x4c +#define XNE_UCODE_STATIC1 0x50 +#define XNE_UCODE_STATIC2 0x54 +#define XNE_TAU_ADDR 0x58 +#define XNE_TAU_SHIFT 0x5c + +#endif diff --git a/sw/pulp-sdk/bin/rename_l2.py b/sw/pulp-sdk/bin/rename_l2.py new file mode 100644 index 0000000..cbde37d --- /dev/null +++ b/sw/pulp-sdk/bin/rename_l2.py @@ -0,0 +1,11 @@ +import glob +import os +from shutil import copyfile +import sys + +for file in glob.glob("./*.slm"): + if "l2" not in file and "tcdm" not in file and "prog_mem" not in file: + dir = os.path.dirname(file) + target = os.path.join(dir, "l2_{}_{}".format(sys.argv[1], os.path.basename(file))) + copyfile(file, target) + diff --git a/sw/pulp-sdk/bin/slm_conv b/sw/pulp-sdk/bin/slm_conv new file mode 100755 index 0000000..a342f5d Binary files /dev/null and b/sw/pulp-sdk/bin/slm_conv differ diff --git a/sw/pulp-sdk/hal/.gitignore b/sw/pulp-sdk/hal/.gitignore new file mode 100644 index 0000000..92608f4 --- /dev/null +++ b/sw/pulp-sdk/hal/.gitignore @@ -0,0 +1,3 @@ +/build/ +*~ +.sconsign.dblite diff --git a/sw/pulp-sdk/hal/LICENSE b/sw/pulp-sdk/hal/LICENSE new file mode 100644 index 0000000..f433b1a --- /dev/null +++ b/sw/pulp-sdk/hal/LICENSE @@ -0,0 +1,177 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS diff --git a/sw/pulp-sdk/hal/Makefile b/sw/pulp-sdk/hal/Makefile new file mode 100644 index 0000000..5f7a225 --- /dev/null +++ b/sw/pulp-sdk/hal/Makefile @@ -0,0 +1,8 @@ +build: + scons + +clean: + rm -f .sconsign.dblite + scons -c + +.PHONY: build clean \ No newline at end of file diff --git a/sw/pulp-sdk/hal/SConstruct b/sw/pulp-sdk/hal/SConstruct new file mode 100644 index 0000000..cef66e8 --- /dev/null +++ b/sw/pulp-sdk/hal/SConstruct @@ -0,0 +1,125 @@ +import os +import subprocess +import shlex +import pulp_config as plpconfig +import SCons.Util + +install_dir = os.environ.get('INSTALL_DIR') +target_install_dir = os.environ.get('TARGET_INSTALL_DIR') + +if install_dir is None: + install_dir = 'install' + +if target_install_dir is None: + target_install_dir = 'install' + +files = [ 'hal/pulp.h', 'hal/utils.h', 'hal/pulp_io.h', 'hal/debug_bridge/debug_bridge.h' ] +files.append('hal/gvsoc/gvsoc.h') +files.append('hal/tb/tb.h') + +try: + files += subprocess.check_output(shlex.split('plpfiles copy --item=hal_files')).decode('UTF-8').split() +except subprocess.CalledProcessError as e: + print (e.output) + raise + +try: + src_files = subprocess.check_output(shlex.split('plpfiles copy --item=hal_src_files')).decode('UTF-8').split() +except subprocess.CalledProcessError as e: + print (e.output) + raise + + +configs = plpconfig.get_configs_from_env() + +def append_file(file): + global files + if not file in files: + files.append(file) + + +for config in configs: + + # The old system is storing the path to archi files in the json file + # This has to be migrated so that only IP information is stored in the + # json file and this build system is them copying the archi files according + # to the IP information found in the json file. + + chip = config.get('**/chip/pulp_chip_family').get() + + + append_file('hal/chips/%s/pulp.h' % chip) + + udma_hyper = config.get_child_int('**/udma/hyper/version') + if udma_hyper is not None: + append_file('hal/udma/hyper/udma_hyper_v%d.h' % udma_hyper) + + # RTC + rtc = config.get('**/soc/rtc') + if rtc is None: + rtc = config.get('**/chip/rtc') + if rtc is not None: + rtc_version = config.get_child_int('**/rtc/version') + if rtc_version == 1 or rtc_version is None: + append_file('hal/vendors/dolphin/rtc.h') + else: + append_file('hal/rtc/rtc_v%d.h' % (rtc_version)) + + # PMU + pmu = config.get_child_int('**/soc/pmu/version') + if pmu is None: + pmu = config.get_child_int('**/chip/pmu/version') + + if pmu is not None: + append_file('hal/maestro/pmu_v%d.h' % pmu) + + # ITC + itc = config.get_child_int('**/soc/fc_itc/version') + if itc is not None: + append_file('hal/itc/itc_v%d.h' % itc) + + # GPIO + gpio = config.get_child_int('**/gpio/version') + if gpio is not None: + append_file('hal/gpio/gpio_v%d.h' % gpio) + + + # Chip specific files can be included here + if chip == 'vega': + append_file('hal/pwm/pwm_v1.h') + append_file('hal/chips/vega/efuse.h') + append_file('hal/chips/vega/pulp.h') + elif chip == 'gap9': + append_file('hal/pwm/pwm_v1.h') + append_file('hal/chips/gap9/efuse.h') + append_file('hal/chips/gap9/pulp.h') + elif chip == 'gap': + append_file('hal/pwm/pwm_v1.h') + elif chip == 'wolfe': + append_file('hal/pwm/pwm_v1.h') + elif chip == 'vivosoc3': + append_file('hal/chips/vivosoc3/fll.h') + append_file('hal/chips/vivosoc3/freq.h') + elif chip == 'vivosoc3_5': + append_file('hal/chips/vivosoc3_5/fll.h') + append_file('hal/chips/vivosoc3_5/freq.h') + elif chip == 'vivosoc3_1': + append_file('hal/chips/vivosoc3_1/fll.h') + append_file('hal/chips/vivosoc3_1/freq.h') + elif chip == 'vivosoc4': + append_file('hal/chips/vivosoc4/fll.h') + append_file('hal/chips/vivosoc4/freq.h') + + +targets = [] + +for file in files: + file_path = os.path.join('include', file) + targets.append(InstallAs(os.path.join(target_install_dir, file_path), file_path)) + +for file in src_files: + file_path = os.path.join('src', file) + targets.append(InstallAs(os.path.join(target_install_dir, file_path), file_path)) + + +Default(targets) diff --git a/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v1.h b/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v1.h new file mode 100644 index 0000000..79f48a6 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v1.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_APB_SOC_APB_SOC_V1_H__ +#define __HAL_APB_SOC_APB_SOC_V1_H__ + +#include "hal/pulp_io.h" + +static inline unsigned int apb_soc_nbCores() { + return pulp_read16(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_INFO_CORES_OFFSET); +} + +static inline unsigned int apb_soc_nbClusters() { + return pulp_read16(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_INFO_CLUSTERS_OFFSET); +} + +static inline void apb_soc_set_pin_function(int pinnumber, int function) { + int old_function; + int addr; + old_function = pulp_read32(SOC_CTRL_PADFUN0); + old_function = old_function & (~(1 << pinnumber)); + old_function = old_function | (function << pinnumber); + pulp_write32(SOC_CTRL_PADFUN0, old_function); +} + +static inline int apb_soc_get_pin_function(int pinnumber) { + int old_function; + old_function = pulp_read32(SOC_CTRL_PADFUN0); + old_function = (old_function >> pinnumber & 0x01); + return old_function; +} + +static inline void hal_apb_soc_padfun_set(unsigned int id, unsigned int value) { +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v2.h b/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v2.h new file mode 100644 index 0000000..050830f --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v2.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_APB_SOC_APB_SOC_V2_H__ +#define __HAL_APB_SOC_APB_SOC_V2_H__ + +#include "archi/pulp.h" + +static inline void apb_soc_bootaddr_set(unsigned int value) { + pulp_write32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_BOOTADDR_OFFSET, value); +} + +static inline void apb_soc_status_set(unsigned int value) { + pulp_write32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_CORESTATUS_OFFSET, value | (1<> APB_SOC_PADS_CONFIG_BOOTSEL_BIT) & 1; +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v4.h b/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v4.h new file mode 100644 index 0000000..c8dc12d --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/apb_soc/apb_soc_v4.h @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_APB_SOC_APB_SOC_V4_H__ +#define __HAL_APB_SOC_APB_SOC_V4_H__ + +#include "archi/pulp.h" +#include "hal/pulp_io.h" + +static inline void apb_soc_bootaddr_set(unsigned int value) { + pulp_write32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_BOOTADDR_OFFSET, value); +} + +static inline unsigned int apb_soc_bootaddr_get() { + return pulp_read32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_BOOTADDR_OFFSET); +} + +static inline int apb_soc_busy_get() { + return pulp_read32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_BUSY_OFFSET); +} + +static inline void apb_soc_cluster_isolate_set(int isolate) { + pulp_write32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_CLUSTER_ISOLATE_OFFSET, isolate); +} + +static inline void apb_soc_status_set(unsigned int value) { + pulp_write32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_CORESTATUS_OFFSET, value | (1<> APB_SOC_PADS_CONFIG_BOOTSEL_BIT) & 1; +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/chips/arnold/pulp.h b/sw/pulp-sdk/hal/include/hal/chips/arnold/pulp.h new file mode 100644 index 0000000..b924dbc --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/chips/arnold/pulp.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_CHIPS_ARNOLD_PULP_H__ +#define __HAL_CHIPS_ARNOLD_PULP_H__ + +#include "hal/riscv/riscv_v5.h" +#include "hal/itc/itc_v1.h" +#include "hal/timer/timer_v2.h" +#include "hal/soc_eu/soc_eu_v2.h" +#include "hal/udma/udma_v3.h" +#include "hal/apb_soc/apb_soc_v3.h" +#include "hal/rom/rom_v2.h" +#include "hal/fll/fll_v1.h" +#include "archi/stdout/stdout_v3.h" +#include "hal/gpio/gpio_v3.h" + +#include "hal/udma/cpi/udma_cpi_v1.h" +#include "hal/udma/i2c/udma_i2c_v2.h" +#include "hal/udma/spim/udma_spim_v3.h" +#include "hal/udma/uart/udma_uart_v1.h" + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/chips/bigpulp/pulp.h b/sw/pulp-sdk/hal/include/hal/chips/bigpulp/pulp.h new file mode 100644 index 0000000..d559a71 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/chips/bigpulp/pulp.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_CHIPS_BIGPULP_PULP_H__ +#define __HAL_CHIPS_BIGPULP_PULP_H__ + +#include "hal/riscv/riscv_v4.h" +#include "hal/eu/eu_v3.h" +#include "hal/dma/mchan_v6.h" +#include "hal/timer/timer_v2.h" +#include "hal/cluster_ctrl/cluster_ctrl_v2.h" +#include "hal/icache/icache_ctrl_v2.h" +#include "hal/apb_soc/apb_soc_v3.h" +#if PULP_CHIP != CHIP_BIGPULP_STANDALONE +#include "hal/mailbox/mailbox_v0.h" +#include "hal/tryx/tryx_v1.h" +#endif + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/chips/devchip/pulp.h b/sw/pulp-sdk/hal/include/hal/chips/devchip/pulp.h new file mode 100644 index 0000000..cda05c7 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/chips/devchip/pulp.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 ETH Zurich and University of Bologna + * All rights reserved. + * + * This software may be modified and distributed under the terms + * of the BSD license. See the LICENSE file for details. + * + */ + +#ifndef __HAL_DEVCHIP_PULP_H__ +#define __HAL_DEVCHIP_PULP_H__ + +#include "hal/riscv/riscv_v4.h" +#include "hal/eu/eu_v3.h" +#include "hal/itc/itc_v1.h" +#include "hal/dma/mchan_v6.h" +#include "hal/timer/timer_v2.h" +#include "hal/soc_eu/soc_eu_v1.h" +#include "hal/udma/udma_v2.h" +#include "hal/cluster_ctrl/cluster_ctrl_v2.h" +#include "hal/icache/icache_ctrl_v2.h" +#include "hal/apb_soc/apb_soc_v3.h" +#include "hal/maestro/pmu_v2.h" +#include "hal/rom/rom_v2.h" +#include "hal/fll/fll_v1.h" +#include "hal/gpio/gpio_v2.h" +#include "hal/hwce/hwce_v5.h" + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/chips/fulmine/pulp.h b/sw/pulp-sdk/hal/include/hal/chips/fulmine/pulp.h new file mode 100644 index 0000000..49d601a --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/chips/fulmine/pulp.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_CHIPS_FULMINE_PULP_H__ +#define __HAL_CHIPS_FULMINE_PULP_H__ + +#include "hal/or1k/or1k_v5.h" +#include "hal/dma/mchan_v5.h" +#include "hal/eu/eu_v1.h" +#include "hal/timer/timer_v1.h" +#include "hal/icache/icache_ctrl_v1.h" +#include "hal/udma/udma_v1.h" +#include "hal/apb_soc/apb_soc_v1.h" + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/chips/gap/apb_soc.h b/sw/pulp-sdk/hal/include/hal/chips/gap/apb_soc.h new file mode 100644 index 0000000..2d63bb5 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/chips/gap/apb_soc.h @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_CHIPS_GAP_APB_SOC_H__ +#define __HAL_CHIPS_GAP_APB_SOC_H__ + +#include "archi/pulp.h" + +#define APB_SOC_PADFUN_OFFSET(g) (APB_SOC_SAFE_PADFUN0_OFFSET+(g)*4) //sets the mux for pins g*16+0 (bits [1:0]) to g*16+15 (bits [31:30]) +#define APB_SOC_PADFUN_NO(pad) ((pad) >> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 3 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_SAFE_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_SAFE_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) + +#define APB_SOC_STATUS_EOC_BIT 31 + +#define APB_SOC_BYPASS_USER1_BIT 15 +#define APB_SOC_BYPASS_USER0_BIT 14 + +static inline void apb_soc_status_set(unsigned int value) { + pulp_write32(ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_CORESTATUS_OFFSET, value | (1< +#include "debug_bridge/debug_bridge.h" + +#define HAL_DEBUG_STRUCT_NAME __hal_debug_struct +#define HAL_DEBUG_STRUCT_NAME_STR "__hal_debug_struct" + +typedef hal_debug_struct_t hal_bridge_t; + +extern hal_debug_struct_t HAL_DEBUG_STRUCT_NAME; + +static inline hal_debug_struct_t *hal_debug_struct_get() +{ + return &HAL_DEBUG_STRUCT_NAME; +} + + +static inline hal_bridge_t *hal_bridge_get() +{ + return hal_debug_struct_get(); +} + + +#define HAL_DEBUG_STRUCT_INIT { PROTOCOL_VERSION_4, {0}, {0}, 0, 1, 0 ,0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0, 0, 0, 0, 0} + + +static inline int hal_bridge_is_connected(hal_bridge_t *bridge) { + return *(volatile uint32_t *)&bridge->bridge.connected; +} + +static inline void hal_bridge_connect(hal_bridge_req_t *req) +{ + req->type = HAL_BRIDGE_REQ_CONNECT; +} + +static inline void hal_bridge_reply(hal_bridge_req_t *req) +{ + req->type = HAL_BRIDGE_REQ_REPLY; +} + +static inline void hal_bridge_disconnect(hal_bridge_req_t *req) +{ + req->type = HAL_BRIDGE_REQ_DISCONNECT; +} + +static inline void hal_bridge_open(hal_bridge_req_t *req, int name_len, const char* name, int flags, int mode) +{ + req->type = HAL_BRIDGE_REQ_OPEN; + req->open.name_len = name_len; + req->open.name = (uint32_t)(long)name; + req->open.flags = flags; + req->open.mode = mode; +} + +static inline void hal_bridge_close(hal_bridge_req_t *req, int file) +{ + req->type = HAL_BRIDGE_REQ_CLOSE; + req->close.file = file; +} + +static inline void hal_bridge_read(hal_bridge_req_t *req, int file, void* ptr, int len) +{ + req->type = HAL_BRIDGE_REQ_READ; + req->read.file = file; + req->read.ptr = (uint32_t)(long)ptr; + req->read.len = len; +} + +static inline void hal_bridge_write(hal_bridge_req_t *req, int file, void* ptr, int len) +{ + req->type = HAL_BRIDGE_REQ_WRITE; + req->write.file = file; + req->write.ptr = (uint32_t)(long)ptr; + req->write.len = len; +} + +static inline void hal_bridge_fb_open(hal_bridge_req_t *req, int name_len, const char* name, int width, int height, int format) +{ + req->type = HAL_BRIDGE_REQ_FB_OPEN; + req->fb_open.name_len = name_len; + req->fb_open.name = (uint32_t)(long)name; + req->fb_open.width = width; + req->fb_open.height = height; + req->fb_open.format = format; +} + +static inline void hal_bridge_fb_update(hal_bridge_req_t *req, uint64_t fb, unsigned int addr, int posx, int posy, int width, int height) +{ + req->type = HAL_BRIDGE_REQ_FB_UPDATE; + req->fb_update.screen = fb; + req->fb_update.addr = addr; + req->fb_update.posx = posx; + req->fb_update.posy = posy; + req->fb_update.width = width; + req->fb_update.height = height; +} + +static inline void hal_bridge_target_status_sync(hal_bridge_req_t *req) +{ + req->type = HAL_BRIDGE_REQ_TARGET_STATUS_SYNC; +} + + +static inline void hal_debug_flush_printf(hal_debug_struct_t *debug_struct) { + while(*(volatile uint32_t *)&debug_struct->pending_putchar); +} + +static inline void hal_debug_exit(hal_debug_struct_t *debug_struct, int status) { + *(volatile uint32_t *)&debug_struct->exit_status = 0x80000000 | status; +} + +static inline int hal_debug_is_empty(hal_debug_struct_t *debug_struct) +{ + return *(volatile uint32_t *)&debug_struct->putc_current == 0; +} + +static inline int hal_debug_is_busy(hal_debug_struct_t *debug_struct) +{ + return *(volatile uint32_t *)&debug_struct->pending_putchar; +} + +static inline void hal_debug_send_printf(hal_debug_struct_t *debug_struct) { + if (debug_struct->putc_current) + { + *(volatile uint32_t *)&debug_struct->pending_putchar = debug_struct->putc_current; + *(volatile uint32_t *)&debug_struct->putc_current = 0; + } +} + +static inline void hal_debug_putchar(hal_debug_struct_t *debug_struct, char c) { + hal_debug_flush_printf(debug_struct); + *(volatile uint8_t *)&(debug_struct->putc_buffer[debug_struct->putc_current++]) = c; + if (*(volatile uint32_t *)&debug_struct->putc_current == HAL_PRINTF_BUF_SIZE || c == '\n') { + hal_debug_send_printf(debug_struct); + } +} + +static inline int hal_debug_putchar_nopoll(hal_debug_struct_t *debug_struct, char c) { + if (*(volatile uint32_t *)&debug_struct->pending_putchar) + return -1; + *(volatile uint8_t *)&(debug_struct->putc_buffer[debug_struct->putc_current++]) = c; + if (*(volatile uint32_t *)&debug_struct->putc_current == HAL_PRINTF_BUF_SIZE || c == '\n') { + hal_debug_send_printf(debug_struct); + } + return 0; +} + +static inline void hal_debug_step(hal_debug_struct_t *debug_struct, unsigned int value) { + *(volatile uint32_t *)&debug_struct->debug_step = value; + *(volatile uint32_t *)&debug_struct->debug_step_pending = 1; + while (*(volatile uint32_t *)&debug_struct->debug_step_pending); +} + +static inline void hal_debug_reset(hal_debug_struct_t *debug_struct) { + *(volatile uint32_t *)&debug_struct->exit_status = 0x80000000 | 0x40000000; // 0xC0000000: reset +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/dma/mchan_v4.h b/sw/pulp-sdk/hal/include/hal/dma/mchan_v4.h new file mode 100644 index 0000000..5f069b6 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/dma/mchan_v4.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_DMA_MCHAN_V4H__ +#define __HAL_DMA_MCHAN_V4H__ + +#include + +#define TCDM_ADDR_REG ( MCHAN_BASE_ADDR + TCDM_ADDR_REG_OFFSET ) +#define EXT_ADDR_REG ( MCHAN_BASE_ADDR + EXT_ADDR_REG_OFFSET ) +#define CMD_QUEUE ( MCHAN_BASE_ADDR + CMD_QUEUE_OFFSET ) +#define CMD_QUEUE_BUSY_REG ( MCHAN_BASE_ADDR + CMD_QUEUE_BUSY_REG_OFFSET ) + +#define set_ext_addr(addr) \ + *(volatile int*)EXT_ADDR_REG = addr; + +#define set_tcdm_addr(addr) \ + *(volatile int*)TCDM_ADDR_REG = addr; + +#define push_cmd(cmd) \ + *(volatile int*)CMD_QUEUE = cmd; + +#define dma_barrier() \ + while(*(volatile int*)CMD_QUEUE_BUSY_REG); + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/dma/mchan_v5.h b/sw/pulp-sdk/hal/include/hal/dma/mchan_v5.h new file mode 100644 index 0000000..d7fd9b4 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/dma/mchan_v5.h @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_DMA_MCHAN_V5_H__ +#define __HAL_DMA_MCHAN_V5_H__ + +#include "archi/dma/mchan_v5.h" +#include "hal/eu/eu_v1.h" + +#include "hal/pulp.h" + +#define MCHAN_COMMAND_QUEUE (ARCHI_MCHAN_ADDR + MCHAN_COMMAND_QUEUE_OFFSET) +#define MCHAN_STATUS_REGISTER (ARCHI_MCHAN_ADDR + MCHAN_STATUS_REGISTER_OFFSET) + +static inline int mchan_transfer(unsigned int len, char type, char incr, char twd, unsigned int ext_addr, unsigned int tcdm_addr, unsigned short int count, unsigned short int stride){ + + int id = *(volatile int*) MCHAN_COMMAND_QUEUE; + + *(volatile int*) MCHAN_COMMAND_QUEUE = (1<<19) | len | (type << MCHAN_LEN_WIDTH) | ( incr << (MCHAN_LEN_WIDTH + 1) ) | ( twd << (MCHAN_LEN_WIDTH + 2) ); + *(volatile int*) MCHAN_COMMAND_QUEUE = tcdm_addr; + *(volatile int*) MCHAN_COMMAND_QUEUE = ext_addr; + + if (twd == 1) + *(volatile int*) MCHAN_COMMAND_QUEUE = count | (stride << 16); + + return id; + +} + +static inline void mchan_barrier(int id) { + while(((*(volatile int*)(MCHAN_STATUS_REGISTER)) >> id ) & 0x1 ) { + eu_evt_maskWaitAndClr(1<<8); + } +} + + + + + + + +// FOR OPENVX + +static inline unsigned int pulp_dma_base() { + return ARCHI_MCHAN_ADDR; +} + +static inline unsigned int pulp_dmaext_base() { + return ARCHI_MCHAN_ADDR; +} + +static inline void pulp_dma_cmd_push(unsigned int dmaBase, unsigned int locAddr, unsigned int extAddr, unsigned int cmd) { + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, cmd); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, locAddr); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, extAddr); +} + +static inline void pulp_dma_memcpy_fromId(unsigned int dmaBase, unsigned int ext, unsigned int loc, int loc2ext, unsigned int size, unsigned int counter) { + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, ((!loc2ext) << MCHAN_TYPE_OFFSET) | (MCHAN_INC_MODE << MCHAN_INCR_OFFSET) | (MCHAN_LIN_MODE << MCHAN_TWD_OFFSET) | (size << MCHAN_SIZE_OFFSET)); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, loc); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, ext); +} + +static inline unsigned int pulp_dma_memcpy(unsigned int dmaBase, unsigned int ext, unsigned int loc, int loc2ext, unsigned int size) { + unsigned int counter = pulp_read32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET); + pulp_dma_memcpy_fromId(dmaBase, ext, loc, loc2ext, size, counter); + return counter; +} + +static inline unsigned int pulp_dma_memcpy_2d(unsigned int dmaBase, unsigned int ext, unsigned int loc, int loc2ext, unsigned int size, unsigned int stride, unsigned int length) { + unsigned int counter = pulp_read32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, ((!loc2ext) << MCHAN_TYPE_OFFSET) | (MCHAN_INC_MODE << MCHAN_INCR_OFFSET) | (MCHAN_TWD_MODE << MCHAN_TWD_OFFSET) | (size << MCHAN_SIZE_OFFSET)); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, loc); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, ext); + pulp_write32(dmaBase + MCHAN_COMMAND_QUEUE_OFFSET, (stride << MCHAN_2D_STRIDE_OFFSET) | (length << MCHAN_2D_LEN_OFFSET)); + return counter; +} + +static inline void pulp_dma_barrier() { + unsigned int addr = ARCHI_MCHAN_ADDR + MCHAN_STATUS_REGISTER_OFFSET; + while(pulp_read32(addr)) { + eu_evt_maskWaitAndClr(1< +#include "hal/pulp.h" + +#if defined(ARCHI_HAS_MCHAN_64) && ARCHI_HAS_MCHAN_64 == 1 +typedef unsigned long long mchan_ext_t; +#else +typedef unsigned int mchan_ext_t; +#endif + +/** @name High-level DMA memory copy functions + * The following functions can be used to trigger DMA transfers to copy data between the cluster memory (L1) and another memory outside the cluster (another cluster L1 or L2). + * Note that they cannot be used from L2 to L2 or from a cluster memory to the same cluster memory. The DMA supports the following features: + * - Transfers can be either event-based or irq-based. With event-based transfers the core can call a wait function to block execution until the transfer is done. With irq-based transfers, the completion of the transfer will trigger the DMA interrupt. This interrupt cannot be managed with this HAL, but must be managed as any other IRQ. + * - The DMA supports 2D transfers which allows transfering a 2D tile in one command. Additional information must then be given to specify the width of the tile and the number of bytes between 2 lines of the tile. + * - The event or irq sent at the end of the transfer can be either sent to the core which enqueued the transfer or broadcasted to all cluster cores. + * - To identify specific transfers, the DMA provides a counter allocator. All transfers enqueued with the same counter are gathered into a group, on which the core can be stalled until the whole group of transfers is finished. + * - All transfers are enqueued into a global FIFO which can stall the core enqueueing the transfer in case it is full. The size of the FIFO depends on the chip but is typically 16 commands. + */ +/**@{*/ + +/** Memory transfer with event-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc); + +/** Cluster memory to external memory transfer with event-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt(mchan_ext_t ext, unsigned int loc, unsigned short size); + +/** External memory to cluster memory transfer with event-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_extToL1(unsigned int loc, mchan_ext_t ext, unsigned short size); + +/** Memory transfer with irq-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc); + +/** Cluster memory to external memory transfer with irq-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt_irq(mchan_ext_t ext, unsigned int loc, unsigned short size); + +/** External memory to cluster memory transfer with irq-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_extToL1_irq(unsigned int loc, mchan_ext_t ext, unsigned short size); + +/** 2-dimensional memory transfer with event-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc); + +/** Cluster memory to external memory 2-dimensional transfer with event-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length); + +/** External memory to cluster memory 2-dimensional transfer with event-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer + */ +static inline int plp_dma_extToL1_2d(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length); + +/** 2-dimensional memory transfer with irq-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc); + +/** Cluster memory to external memory 2-dimensional transfer with irq-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length); + +/** External memory to cluster memory 2-dimensional transfer with irq-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer + */ +static inline int plp_dma_extToL1_2d_irq(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length); + +//!@} + +/** @name DMA wait functions + */ + +/** DMA barrier. + * This blocks the core until no transfer is on-going in the DMA. + */ +static inline void plp_dma_barrier(); + +/** DMA wait. + * This blocks the core until the specified transfer is finished. + * + \param counter The counter ID identifying the transfer. This has either been allocated explicitly or returned from an enqueued transfer (e.g. plp_dma_extToL1_2d_irq) + */ +static inline void plp_dma_wait(unsigned int counter); + +//!@} + + +/** @name DMA low-level functions. + * This can be used instead of the high-level ones in order to have more control over the DMA features. + */ + +/** DMA counter allocation. + * This allocates a counter and activate it for all the next transfers until another one is allocated. This means during this period, all transfers will be accounted on this counter and thus waiting + * on this counter will wait for all these transfers. + * + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_counter_alloc(); + +/** DMA counter release. + * This makes the counter available for another transfer through the DMA counter allocator + * + \param counter The counter number to be released + */ +static inline void plp_dma_counter_free(int counter); + +/** DMA command generation. + * Can be used to generate the 32 bits command to be pushed to the DMA, depending on the required mode. + * + \param ext2loc If 1, the data is loaded from external memory, and stored to the cluster memory, otherwise it is the contrary + \param size Size in bytes of the transfer. In case it is a 2D transfer, this is the total number of bytes to be transfered, whatever the stride. Must fit 16 bits, i.e. must be inferior to 65536. + \param is2D If 1, the transfer is a 2-dimensional transfer (tile) otherwise it is a classic one. + \param trigEvt If 1, an event is sent to 1 or all cores at the end of the transfer. + \param trigIrq If 1, an interrupt is sent to 1 or all cores at the end of the transfer. + \param broadcast If 1 the event or irq generated when the transfer is finished is sent to all cores, otherwise it is only sent to the core enqueueing the transfer. + \return The generated command. + */ +static inline unsigned int plp_dma_getCmd(int ext2loc, unsigned int size, int is2D, int trigEvt, int trigIrq, int broadcast); + +/** Generate the stride command for 2D transfers. + * + \param stride The stride of the 2D transfer, i.e. the number of bytes between the beginning of 2 lines of the tile. Must fit 16 bits, i.e. must be inferior to 65536. + \param len The length of the 2D transfer, i.e. the number of bytes transfered after which the DMA should switch to the new line. Must fit 16 bits, i.e. must be inferior to 65536. + \return The generated command. + */ +static inline unsigned int plp_dma_getStrides(unsigned short stride, unsigned short len); + +/** Push a transfer to the DMA + * + \param locAddr The address of the transfer for the cluster memory + \param extAddr The address of the transfer for the external memory + \param cmd The command that specifies the type of the transfer. This can be generated using plp_dma_getCmd. + */ +static inline void plp_dma_cmd_push(unsigned int cmd, unsigned int locAddr, mchan_ext_t extAddr); + +/** Push a 2D transfer to the DMA + * + \param locAddr The address of the transfer for the cluster memory + \param extAddr The address of the transfer for the external memory + \param cmd The command that specifies the type of the transfer. This can be generated using plp_dma_getStrides. + \param strides The command that specifies the 2D transfer (stride and len). This can be generated using plp_dma_getStrides. + */ +static inline void plp_dma_cmd_push_2d(unsigned int cmd, unsigned int locAddr, mchan_ext_t extAddr, unsigned stride, unsigned int length); + +/** Return the counter status. + * + \return Counter status. There is one bit per counter. 1 means there are still on-going transfers for this counter, 0 means nothing is on-going. + */ +static inline unsigned int plp_dma_status(); + +//!@} + +/// @cond IMPLEM + +#if defined(__riscv__) && !defined(RV_ISA_RV32) && !defined(__LLVM__) +#define DMA_WRITE(value, offset) __builtin_pulp_OffsetedWrite((value), (int *)ARCHI_DEMUX_PERIPHERALS_ADDR, ARCHI_MCHAN_DEMUX_OFFSET + (offset)) +#define DMA_READ(offset) __builtin_pulp_OffsetedRead((int *)ARCHI_DEMUX_PERIPHERALS_ADDR, ARCHI_MCHAN_DEMUX_OFFSET + (offset)) +#else +#define DMA_WRITE(value, offset) pulp_write32(ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET + (offset), (value)) +#define DMA_READ(offset) pulp_read32(ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET + (offset)) +#endif + +static inline int plp_dma_counter_alloc() { + return DMA_READ(PLP_DMA_QUEUE_OFFSET); +} + +static inline void plp_dma_counter_free(int counter) { + DMA_WRITE(1<>32), PLP_DMA_QUEUE_OFFSET); +#else + DMA_WRITE(extAddr, PLP_DMA_QUEUE_OFFSET); +#endif +} + +static inline void plp_dma_cmd_push_2d(unsigned int cmd, unsigned int locAddr, mchan_ext_t extAddr, unsigned int stride, unsigned int length) { + plp_dma_cmd_push(cmd, locAddr, extAddr); + DMA_WRITE(plp_dma_getStrides(stride, length), PLP_DMA_QUEUE_OFFSET); +} + +static inline int plp_dma_memcpy(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_memcpy_merge(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc, int merge) { + unsigned int counter = -1; + if (!merge) + counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_memcpy_priv(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_PRIV); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_l1ToExt(mchan_ext_t ext, unsigned int loc, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_extToL1(unsigned int loc, mchan_ext_t ext, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_memcpy_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_1D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_l1ToExt_irq(mchan_ext_t ext, unsigned int loc, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_1D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_extToL1_irq(unsigned int loc, mchan_ext_t ext, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_1D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline void plp_dma_memcpy_2d_keepCounter(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc) { + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_2D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); +} + +static inline int plp_dma_memcpy_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_memcpy_2d_keepCounter(ext, loc, size, stride, length, ext2loc); + return counter; +} + +static inline int plp_dma_l1ToExt_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_2D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_extToL1_2d(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_2D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_memcpy_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_2D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_l1ToExt_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_2D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_extToL1_2d_irq(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_2D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + __asm__ __volatile__ ("" : : : "memory"); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline void plp_dma_barrier() { + while(DMA_READ(PLP_DMA_STATUS_OFFSET) & 0xFFFF) { + eu_evt_maskWaitAndClr(1< +#include "hal/pulp.h" + +#define PLP_DMA_LOC2EXT 0 +#define PLP_DMA_EXT2LOC 1 + +#define PLP_DMA_1D 0 +#define PLP_DMA_2D 1 + +#define PLP_DMA_NO_TRIG_EVT 0 +#define PLP_DMA_TRIG_EVT 1 + +#define PLP_DMA_NO_TRIG_IRQ 0 +#define PLP_DMA_TRIG_IRQ 1 + +#define PLP_DMA_PRIV 0 +#define PLP_DMA_SHARED 1 + +#define PLP_DMA_FIX 0 +#define PLP_DMA_INC 1 + +#if defined(ARCHI_HAS_MCHAN_64) && ARCHI_HAS_MCHAN_64 == 1 +typedef unsigned long long mchan_ext_t; +#else +typedef unsigned int mchan_ext_t; +#endif + +/** @name High-level DMA memory copy functions + * The following functions can be used to trigger DMA transfers to copy data between the cluster memory (L1) and another memory outside the cluster (another cluster L1 or L2). + * Note that they cannot be used from L2 to L2 or from a cluster memory to the same cluster memory. The DMA supports the following features: + * - Transfers can be either event-based or irq-based. With event-based transfers the core can call a wait function to block execution until the transfer is done. With irq-based transfers, the completion of the transfer will trigger the DMA interrupt. This interrupt cannot be managed with this HAL, but must be managed as any other IRQ. + * - The DMA supports 2D transfers which allows transfering a 2D tile in one command. Additional information must then be given to specify the width of the tile and the number of bytes between 2 lines of the tile. + * - The event or irq sent at the end of the transfer can be either sent to the core which enqueued the transfer or broadcasted to all cluster cores. + * - To identify specific transfers, the DMA provides a counter allocator. All transfers enqueued with the same counter are gathered into a group, on which the core can be stalled until the whole group of transfers is finished. + * - All transfers are enqueued into a global FIFO which can stall the core enqueueing the transfer in case it is full. The size of the FIFO depends on the chip but is typically 16 commands. + */ +/**@{*/ + +/** Memory transfer with event-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc); + +/** Cluster memory to external memory transfer with event-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt(mchan_ext_t ext, unsigned int loc, unsigned short size); + +/** External memory to cluster memory transfer with event-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_extToL1(unsigned int loc, mchan_ext_t ext, unsigned short size); + +/** Memory transfer with irq-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc); + +/** Cluster memory to external memory transfer with irq-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt_irq(mchan_ext_t ext, unsigned int loc, unsigned short size); + +/** External memory to cluster memory transfer with irq-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_extToL1_irq(unsigned int loc, mchan_ext_t ext, unsigned short size); + +/** 2-dimensional memory transfer with event-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc); + +/** Cluster memory to external memory 2-dimensional transfer with event-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length); + +/** External memory to cluster memory 2-dimensional transfer with event-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer + */ +static inline int plp_dma_extToL1_2d(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length); + +/** 2-dimensional memory transfer with irq-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_memcpy_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc); + +/** Cluster memory to external memory 2-dimensional transfer with irq-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. + \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_l1ToExt_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length); + +/** External memory to cluster memory 2-dimensional transfer with irq-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. + \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. + \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. + \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer + */ +static inline int plp_dma_extToL1_2d_irq(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length); + +//!@} + +/** @name DMA wait functions + */ + +/** DMA barrier. + * This blocks the core until no transfer is on-going in the DMA. + */ +static inline void plp_dma_barrier(); + +/** DMA wait. + * This blocks the core until the specified transfer is finished. + * + \param counter The counter ID identifying the transfer. This has either been allocated explicitly or returned from an enqueued transfer (e.g. plp_dma_extToL1_2d_irq) + */ +static inline void plp_dma_wait(unsigned int counter); + +//!@} + + +/** @name DMA low-level functions. + * This can be used instead of the high-level ones in order to have more control over the DMA features. + */ + +/** DMA counter allocation. + * This allocates a counter and activate it for all the next transfers until another one is allocated. This means during this period, all transfers will be accounted on this counter and thus waiting + * on this counter will wait for all these transfers. + * + \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. + */ +static inline int plp_dma_counter_alloc(); + +/** DMA counter release. + * This makes the counter available for another transfer through the DMA counter allocator + * + \param counter The counter number to be released + */ +static inline void plp_dma_counter_free(int counter); + +/** DMA command generation. + * Can be used to generate the 32 bits command to be pushed to the DMA, depending on the required mode. + * + \param ext2loc If 1, the data is loaded from external memory, and stored to the cluster memory, otherwise it is the contrary + \param size Size in bytes of the transfer. In case it is a 2D transfer, this is the total number of bytes to be transfered, whatever the stride. Must fit 16 bits, i.e. must be inferior to 65536. + \param is2D If 1, the transfer is a 2-dimensional transfer (tile) otherwise it is a classic one. + \param trigEvt If 1, an event is sent to 1 or all cores at the end of the transfer. + \param trigIrq If 1, an interrupt is sent to 1 or all cores at the end of the transfer. + \param broadcast If 1 the event or irq generated when the transfer is finished is sent to all cores, otherwise it is only sent to the core enqueueing the transfer. + \return The generated command. + */ +static inline unsigned int plp_dma_getCmd(int ext2loc, unsigned int size, int is2D, int trigEvt, int trigIrq, int broadcast); + +/** Generate the stride command for 2D transfers. + * + \param stride The stride of the 2D transfer, i.e. the number of bytes between the beginning of 2 lines of the tile. Must fit 16 bits, i.e. must be inferior to 65536. + \param len The length of the 2D transfer, i.e. the number of bytes transfered after which the DMA should switch to the new line. Must fit 16 bits, i.e. must be inferior to 65536. + \return The generated command. + */ +static inline unsigned int plp_dma_getStrides(unsigned short stride, unsigned short len); + +/** Push a transfer to the DMA + * + \param locAddr The address of the transfer for the cluster memory + \param extAddr The address of the transfer for the external memory + \param cmd The command that specifies the type of the transfer. This can be generated using plp_dma_getCmd. + */ +static inline void plp_dma_cmd_push(unsigned int cmd, unsigned int locAddr, mchan_ext_t extAddr); + +/** Push a 2D transfer to the DMA + * + \param locAddr The address of the transfer for the cluster memory + \param extAddr The address of the transfer for the external memory + \param cmd The command that specifies the type of the transfer. This can be generated using plp_dma_getStrides. + \param strides The command that specifies the 2D transfer (stride and len). This can be generated using plp_dma_getStrides. + */ +static inline void plp_dma_cmd_push_2d(unsigned int cmd, unsigned int locAddr, mchan_ext_t extAddr, unsigned int stride, unsigned int length); + +/** Return the counter status. + * + \return Counter status. There is one bit per counter. 1 means there are still on-going transfers for this counter, 0 means nothing is on-going. + */ +static inline unsigned int plp_dma_status(); + +//!@} + +/// @cond IMPLEM + +#if defined(__riscv__) && !defined(RV_ISA_RV32) && !defined(__LLVM__) +#define DMA_WRITE(value, offset) __builtin_pulp_OffsetedWrite((value), (int *)ARCHI_MCHAN_EXT_ADDR, (offset)) +#define DMA_READ(offset) __builtin_pulp_OffsetedRead((int *)ARCHI_MCHAN_EXT_ADDR, (offset)) +#else +#define DMA_WRITE(value, offset) pulp_write32(ARCHI_MCHAN_EXT_ADDR + (offset), (value)) +#define DMA_READ(offset) pulp_read32(ARCHI_MCHAN_EXT_ADDR + (offset)) +#endif + +static inline int plp_dma_counter_alloc() { + return DMA_READ(MCHAN_CMD_OFFSET); +} + +static inline void plp_dma_counter_free(int counter) { + DMA_WRITE(1<>32), MCHAN_CMD_OFFSET); +#else + DMA_WRITE(extAddr, MCHAN_CMD_OFFSET); +#endif +} + +static inline void plp_dma_cmd_push_2d(unsigned int cmd, unsigned int locAddr, mchan_ext_t extAddr, unsigned int stride, unsigned int length) { + plp_dma_cmd_push(cmd, locAddr, extAddr); + DMA_WRITE(length, MCHAN_CMD_OFFSET); + DMA_WRITE(stride, MCHAN_CMD_OFFSET); +} + +static inline int plp_dma_memcpy(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_l1ToExt(mchan_ext_t ext, unsigned int loc, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_extToL1(unsigned int loc, mchan_ext_t ext, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_1D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_memcpy_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_1D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_l1ToExt_irq(mchan_ext_t ext, unsigned int loc, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_1D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline int plp_dma_extToL1_irq(unsigned int loc, mchan_ext_t ext, unsigned short size) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_1D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push(cmd, loc, ext); + return counter; +} + +static inline void plp_dma_memcpy_2d_keepCounter(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc) { + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_2D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); +} + +static inline int plp_dma_memcpy_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + plp_dma_memcpy_2d_keepCounter(ext, loc, size, stride, length, ext2loc); + return counter; +} + +static inline int plp_dma_l1ToExt_2d(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_2D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_extToL1_2d(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_2D, PLP_DMA_TRIG_EVT, PLP_DMA_NO_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_memcpy_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length, int ext2loc) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(ext2loc, size, PLP_DMA_2D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_l1ToExt_2d_irq(mchan_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_LOC2EXT, size, PLP_DMA_2D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline int plp_dma_extToL1_2d_irq(unsigned int loc, mchan_ext_t ext, unsigned short size, unsigned short stride, unsigned short length) { + unsigned int counter = plp_dma_counter_alloc(); + unsigned int cmd = plp_dma_getCmd(PLP_DMA_EXT2LOC, size, PLP_DMA_2D, PLP_DMA_NO_TRIG_EVT, PLP_DMA_TRIG_IRQ, PLP_DMA_SHARED); + plp_dma_cmd_push_2d(cmd, loc, ext, stride, length); + return counter; +} + +static inline void plp_dma_barrier() { + while(DMA_READ(MCHAN_STATUS_OFFSET) & 0xFFFF) { + eu_evt_maskWaitAndClr(1<>= 1; + } +} + +// sets the values for the 3 diffrent timing intervals that are used by the IP +// bits[ 9: 0] sets the short interval default 5 cycles +// bits[19:10] sets the medium interval default 50 cycles +// bits[29:20] sets the long interval default 400 cycles +static inline void plp_efuse_configTimings(unsigned int timervalues) { + pulp_write32(ARCHI_EFUSE_ADDR + EFUSE_CFG_OFFSET, timervalues); +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/eu/eu_v1.h b/sw/pulp-sdk/hal/include/hal/eu/eu_v1.h new file mode 100644 index 0000000..66a7e9e --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/eu/eu_v1.h @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_EU_EU_V1_H__ +#define __HAL_EU_EU_V1_H__ + +#include "hal/eu/eu_v1_ids.h" +#include "hal/pulp_io.h" +#include "hal/pulp.h" +#include "archi/eu/eu_v1.h" + +static inline void pulp_evt_wait() { + pulp_write32(ARCHI_DEMUX_ADDR + PULP_DEMUX_CORE_CLKGATE_OFFSET, 1); +#ifdef __riscv__ +#if PULP_CORE == CORE_RISCV_V4 + asm volatile ("nop;nop;wfi"); +#else + asm volatile ("nop;nop;"); + asm volatile (".word 0x10200073;"); + #endif +#else + __asm volatile("l.psync"); +#endif +} + +static inline void pulp_evt_activate(unsigned int event) { + unsigned int addr = ARCHI_EU_ADDR + PULP_EV_MASK_LOW + hal_core_id() * 4; + unsigned int mask = pulp_read32(addr); + pulp_write32(addr, mask | (1 << event)); +} + +static inline void pulp_evtmask_wait_base(unsigned int base, unsigned int eventMask) { + unsigned int oldMask = pulp_read32(base + ARCHI_EU_OFFSET + PULP_EV_MASK_LOW + hal_core_id() * 4); + pulp_write32(base + ARCHI_EU_OFFSET + PULP_EV_MASK_LOW + hal_core_id() * 4, eventMask); + pulp_write32(base + ARCHI_EU_OFFSET + PULP_CORE_CLKGATE, hal_core_id()); +#ifdef __riscv__ + asm volatile ("nop;nop;wfi"); +#else + __asm volatile("l.psync"); +#endif + pulp_write32(base + ARCHI_EU_OFFSET + PULP_EV_MASK_LOW + hal_core_id() * 4, oldMask); +} + +static inline void pulp_evtMask_set_base(int base, unsigned int eventMask) { + pulp_write32(base + PULP_EV_MASK_LOW, eventMask); +} + +static inline void pulp_evtMask_set(unsigned int eventMask) { + pulp_write32(ARCHI_EU_ADDR + PULP_EV_MASK_LOW + hal_core_id() * 4, eventMask); +} + +static inline void pulp_evtMask_coreSet(int core, unsigned int eventMask) { + pulp_write32(ARCHI_EU_ADDR + PULP_EV_MASK_LOW + core * 4, eventMask); +} + +static inline unsigned pulp_evtMask_get() { + return pulp_read32(ARCHI_EU_ADDR + PULP_EV_MASK_LOW + hal_core_id() * 4); +} + +static inline void pulp_evtmask_wait(unsigned int eventMask) { + unsigned int oldMask = pulp_evtMask_get(); + pulp_evtMask_set(eventMask); + pulp_evt_wait(); + pulp_evtMask_set(oldMask); +} + +static inline void pulp_gpevt_wait(unsigned int event) { + pulp_evtmask_wait(1 << event); +} + +static inline void pulp_gpevt_trigger_remote(unsigned int event) { + pulp_write32(ARCHI_CLUSTER_GLOBAL_ADDR(0) + ARCHI_EU_OFFSET + PULP_EVNT_GEN, 1 << event); +} + +static inline void pulp_gpevt_trigger_cluster(unsigned int cid, unsigned int event) { + pulp_write32(ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_EU_OFFSET + PULP_EVNT_GEN, 1 << event); +} + +static inline void pulp_gpevt_triggerCoreSet(unsigned int event, unsigned int coreSet) { + pulp_write32(ARCHI_EU_ADDR + PULP_EVNT_GEN_GP0 + ((event - 1) << 2), coreSet); +} + +static inline void pulp_gpevt_clear_base(unsigned int base, unsigned int event) { + // On pulp 3 we can clear all events specified in the mask in one shot + pulp_write32(base + ARCHI_EU_OFFSET + PULP_EV_BUFFER_LOW + hal_core_id()*4, 1 << event); +} + +static inline void pulp_gpevt_clear(unsigned int event) { + pulp_write32(ARCHI_DEMUX_ADDR + PULP_DEMUX_EV_BUFFER_CLEAR_OFFSET, 1 << event); +} + +static inline void pulp_gpevtmask_clear(unsigned int event) { + pulp_write32(ARCHI_DEMUX_ADDR + PULP_DEMUX_EV_BUFFER_CLEAR_OFFSET, event); +} + +static inline void eu_evt_maskWaitAndClr(int mask) +{ + pulp_evtmask_wait(mask); + pulp_gpevtmask_clear(mask); +} + +static inline void pulp_fc_gpevt_clear(unsigned int event) { + pulp_gpevt_clear_base(0x50200000, event); +} + +static inline unsigned int pulp_gpevt_status_base(unsigned int base) { + return pulp_read32(ARCHI_EU_ADDR + PULP_EV_BUFFER_LOW + hal_core_id()*4); +} + +static inline unsigned int pulp_gpevt_status() { + return pulp_gpevt_status_base(ARCHI_CLUSTER_ADDR); +} + +static inline unsigned int pulp_fc_gpevt_status() { + return pulp_gpevt_status_base(0x50200000); +} + + +/** @name SW event trigger. + * Functions for triggering SW events which can be used to wake-up cluster cores from SW. + */ +/**@{*/ + +static inline unsigned int eu_evt_trig_cluster_addr(int cluster, int event) +{ + return ARCHI_CLUSTER_GLOBAL_ADDR(cluster) + ARCHI_EU_OFFSET + PULP_EVNT_GEN_GP0 + ((event - 1) << 2); +} + +static inline unsigned int eu_evt_trig_remote_addr(int event) +{ + return eu_evt_trig_cluster_addr(0, event); +} + +static inline unsigned int eu_evt_trig_addr(int event) +{ + return ARCHI_EU_ADDR + PULP_EVNT_GEN_GP0 + ((event - 1) << 2); +} + +static inline void eu_evt_trig(unsigned int evtAddr, unsigned int coreSet) +{ + pulp_write32(evtAddr, coreSet); +} + +//!@} + +/* + * Interrupt + */ +static inline unsigned int pulp_irq_id_read(int coreid){ + return pulp_read32(ARCHI_EU_ADDR + PULP_READ_IRQ_ID_BASE + 4*coreid); +} + + +static inline unsigned int pulp_irq_buff_low_read(int coreid){ + return pulp_read32(ARCHI_EU_ADDR + PULP_IRQ_BUFFER_LOW_BASE + 4*coreid); +} + +static inline unsigned int pulpe_irq_buff_high_read(int coreid){ + return pulp_read32(ARCHI_EU_ADDR + PULP_IRQ_BUFFER_HIGH_BASE + 4*coreid); +} + +static inline void pulp_irq_buff_low_clear( unsigned int mask ) { + pulp_write32(ARCHI_DEMUX_ADDR + PULP_DEMUX_IRQ_BUFFER_CLEAR_OFFSET, mask); +} + +static inline unsigned int pulp_irq_mask_low_read( int coreid ) { + return pulp_read32(ARCHI_EU_ADDR + PULP_IRQ_MASK_LOW_BASE + 4*coreid) ; +} + +static inline unsigned int pulp_irq_mask_high_read( int coreid ) { + return pulp_read32(ARCHI_EU_ADDR + PULP_IRQ_MASK_HIGH_BASE+ 4*coreid ); +} + +static inline void pulp_irq_mask_low_set( int coreid , unsigned int mask ) { + pulp_write32(ARCHI_EU_ADDR + PULP_IRQ_MASK_LOW_BASE + 4*coreid, mask); +} + +static inline void pulp_irq_mask_high_set( int coreid , unsigned int mask ) { + pulp_write32(ARCHI_EU_ADDR + PULP_IRQ_MASK_HIGH_BASE + 4*coreid, mask); +} + +static inline void eu_irq_maskSet(unsigned int irqMask) +{ + int coreId = hal_core_id(); + pulp_irq_mask_low_set(coreId, pulp_irq_mask_low_read(coreId) | irqMask); +} + +static inline void eu_irq_maskClr(unsigned int irqMask) +{ + int coreId = hal_core_id(); + pulp_irq_mask_low_set(coreId, pulp_irq_mask_low_read(coreId) & ~irqMask); +} + + + + +/* + * BARRIERS + */ + +static inline void pulp_barrier_notify(unsigned int barrier_id) { + pulp_write32(ARCHI_EU_ADDR + PULP_CLKGATE_WAIT_BARRIER, barrier_id); +} + +static inline unsigned int pulp_barrier_read(unsigned int barrier_id){ + return pulp_read32(ARCHI_EU_ADDR + PULP_CLKGATE_SET_BARRIER+4*barrier_id); +} + + +static inline void pulp_barrier_setup(unsigned int barrier_id, unsigned int num_threads, unsigned int mask_to_trigg) { + pulp_write32(ARCHI_EU_ADDR + PULP_CLKGATE_SET_BARRIER+4*barrier_id, (num_threads<<16)+mask_to_trigg); +} + + + + + + +static inline void eu_evt_maskSet_base(unsigned int base, unsigned int evtMask) { + pulp_evtMask_set_base(base, evtMask); +} + +static inline void eu_evt_maskSet(unsigned int evtMask) +{ + pulp_evtMask_set(pulp_evtMask_get() | evtMask); +} + +static inline void eu_evt_maskClr(unsigned int evtMask) +{ + pulp_evtMask_set(pulp_evtMask_get() & ~evtMask); +} + + +static inline unsigned int eu_evt_wait() +{ + pulp_evt_wait(); + return pulp_gpevt_status() & pulp_evtMask_get(); +} + + +static inline unsigned int eu_evt_getClusterBase(unsigned int coreId) +{ + return ARCHI_EU_ADDR + coreId * 4; +} + + + + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/eu/eu_v1_ids.h b/sw/pulp-sdk/hal/include/hal/eu/eu_v1_ids.h new file mode 100644 index 0000000..33eebea --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/eu/eu_v1_ids.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_EU_EU_V1_IDS_H__ +#define __HAL_EU_EU_V1_IDS_H__ + +// Highest priority is 0 +#define BARRIER 0 +#define GP0 1 +#define GP1 2 +#define GP2 3 + +#define TMR0 4 +#define TMR1 5 +#define TMR2 6 +#define TMR3 7 + +#define DMA 8 + +#define EVENT_GPIO 9 +#define EVENT_SPIM0 10 +#define EVENT_SPIM1 11 +#define EVENT_UART 12 +#define EVENT_I2C 13 +#define EVENT_I2S 14 +#define EVENT_I2S_CAM 15 + +#define EVENT_HWCE 17 + +#define EVTMASK_BARRIER (1 << 0) +#define EVTMASK_GP0 (1 << 1) +#define EVTMASK_GP1 (1 << 2) +#define EVTMASK_GP2 (1 << 3) +#define EVTMASK_TMR0 (1 << 4) +#define EVTMASK_TMR1 (1 << 5) +#define EVTMASK_TMR2 (1 << 6) +#define EVTMASK_TMR3 (1 << 7) +#define EVTMASK_DMA (1 << 8) +#define EVTMASK_GPIO (1 << 9) +#define EVTMASK_SPIM0 (1 << 10) +#define EVTMASK_SPIM1 (1 << 11) +#define EVTMASK_UART (1 << 12) +#define EVTMASK_I2C (1 << 13) +#define EVTMASK_I2S (1 << 14) +#define EVTMASK_I2S_CAM (1 << 15) +#define EVTMASK_HWCE (1 << 17) + +#endif + diff --git a/sw/pulp-sdk/hal/include/hal/eu/eu_v3.h b/sw/pulp-sdk/hal/include/hal/eu/eu_v3.h new file mode 100644 index 0000000..4479ac3 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/eu/eu_v3.h @@ -0,0 +1,609 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_EU_EU_V3_H__ +#define __HAL_EU_EU_V3_H__ + +#include "archi/eu/eu_v3.h" +#include "archi/pulp.h" +#include "hal/pulp_io.h" + + + +/** @name Event management + * The following function can be used for selecting which events can wake-up the core, put the core the sleep, clear events and so on. + */ +/**@{*/ + +/** Clock-gated load. + * On architectures that support it, this executes the special p.elw instruction which is used to put the core in idle mode until it receives an event. + On other architectures, it executes a classic read which has the same effect but does not handle correctly interrupts while the core is sleeping. + \param base The base address of the event unit. + \param offset The offset in the event unit where to load from. Depending on this offset, this will trigger different behaviors (barrier, wait, wait&clear, etc). + \return The loaded value, after the core has been waken-up. This value depends on the feature which is accessed. + */ +#if defined(__OPTIMIZE__) +static inline unsigned int evt_read32(unsigned int base, unsigned int offset) +{ + unsigned int value; + #if !defined(__LLVM__) && ((defined(OR1K_VERSION) && OR1K_VERSION >= 5) || (defined(RISCV_VERSION) && RISCV_VERSION >= 4)) + value = __builtin_pulp_event_unit_read((int *)base, offset); + #else + __asm__ __volatile__ ("" : : : "memory"); + value = pulp_read32(base + offset); + __asm__ __volatile__ ("" : : : "memory"); + #endif + return value; +} +#else +#define evt_read32(base,offset) \ + ({ \ + __builtin_pulp_event_unit_read((int *)base, offset); \ + }) +#endif + +/** Get event status. + Return the value of the event status register. This register contains one bit per event, 1 means the event is set. Note that this register is actually used + as a status register for both events and interrupts, so clearing one will clear the other. This register is a buffer, which means if an event is received + while its bit is already at 1, the event is somehow lost as the bit stays at 1. Thus events should be used as Linux signals. + \return The content of the status register. + */ +static inline unsigned int eu_evt_status() +{ + return pulp_read32(ARCHI_EU_DEMUX_ADDR + EU_CORE_BUFFER); +} + +/** Get active events. + Same as eu_evt_status, but the content of the status register is ANDed with the content of the event mask register so that + only relevant events (that can wake-up the core) are shown. It can for example be used to know which events must be handled + after a core wake-up as the core has been waken-up due to one of them. + \return The content of the status register ANDed with the event mask register. + */ +static inline unsigned int eu_evt_statusMasked() +{ + return pulp_read32(ARCHI_EU_DEMUX_ADDR + EU_CORE_BUFFER_MASKED); +} + +/** Clear some bits of the event status register. + This allows clearing events after they have been received so that they do not prevent the core from sleeping anymore. + \param evtMask Bits to be cleared. 1 means the bit must be cleared, 0 it should remain the same. + */ +static inline void eu_evt_clr(unsigned int evtMask) +{ + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_CORE_BUFFER_CLEAR, evtMask); +} + +/** Modify the event mask. + The event mask tells the event unit which events can wake-up the core. When the core executes the p.elw instruction it goes to sleep unless + there is one bit which is set in both the event mask and the event status register. If the event is received while the core is already sleeping + and the corresponding bit is set in the event mask, the core is waken-up and cannot go back to sleep until either the event mask or the event status + register is modified (usually the bit is cleared using eu_evt_clr) + \param evtMask Value to write to the event mask. There is 1 bit per event, 1 means it can wake-up the core, 0 it cannot + */ +static inline void eu_evt_mask(unsigned int evtMask) +{ + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_CORE_MASK, evtMask); +} + +/** Set part of the event mask to 1. + See eu_evt_maskSet + \param base The address of the register + \param evtMask Bit mask used to update the event mask. There is 1 bit per event, 1 means the corresponding bit is set in the event mask. + */ +static inline void eu_evt_maskSet_base(unsigned int base, unsigned int evtMask) +{ +#if defined(__riscv__) && !defined(__LLVM__) + // TODO riscv compiler is not able to factorize the event unit base if we use classic C code + __asm volatile ("sw %0,%1(%2)" : : "r" (evtMask), "I" (EU_CORE_MASK_OR), "r" (base) ); +#else + pulp_write32(base + EU_CORE_MASK_OR, evtMask); +#endif +} + +/** Set part of the event mask to 1. + This is similar to eu_evt_mask but for each bit at 1 in the new value, the corresponding bit is set in the event mask and the others remain the same. + This is useful when the mask must be updated before waiting for a specific event without modifying the other events (this saves a few instructions) + \param evtMask Bit mask used to update the event mask. There is 1 bit per event, 1 means the corresponding bit is set in the event mask. + */ +static inline void eu_evt_maskSet(unsigned int evtMask) +{ + eu_evt_maskSet_base(ARCHI_EU_DEMUX_ADDR, evtMask); +} + +/** Set part of the event mask to 0. + This is the opposite of eu_evt_maskSet. For each bit at 1 in the new value, the corresponding bit is set to 0 in the event mask and the others remain the same. + \param evtMask Bit mask used to update the event mask. There is 1 bit per event, 1 means the corresponding bit is cleared in the event mask. + */ +static inline void eu_evt_maskClr(unsigned int evtMask) +{ +#if defined(__riscv__) && !defined(__LLVM__) + // TODO riscv compiler is not able to factorize the event unit base if we use classic C code + __asm volatile ("sw %0,%1(%2)" : : "r" (evtMask), "I" (EU_CORE_MASK_AND), "r" (ARCHI_EU_DEMUX_ADDR) ); +#else + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_CORE_MASK_AND, evtMask); +#endif +} + +/** Put the core to sleep mode until it receives an event + The core goes to sleep until there is one bit at 1 in both the event status register and the event mask register. If it is already the case, when this function is called, + the core does not go to sleep and this function returns immediately. + */ +static inline unsigned int eu_evt_wait() +{ + return evt_read32(ARCHI_EU_DEMUX_ADDR, EU_CORE_EVENT_WAIT); +} + +static inline unsigned int eu_evt_wait_noreplay() +{ + return pulp_read32(ARCHI_EU_DEMUX_ADDR + EU_CORE_EVENT_WAIT); +} + +static inline unsigned int eu_wait_for_interrupt() +{ + return pulp_read32(ARCHI_EU_DEMUX_ADDR + EU_CORE_EVENT_WAIT); +} + +/** Put the core to sleep mode until it receives an event and clears the active events + This is similar to eu_evt_wait but when the core is waken-up, the active events are cleared in the status register. An event is active if its bit is at 1 in both + the event status register and the event mask register. + */ +static inline unsigned int eu_evt_waitAndClr() +{ + return evt_read32(ARCHI_EU_DEMUX_ADDR, EU_CORE_EVENT_WAIT_CLEAR); +} + +/** Modify the event mask, put the core to sleep mode until it receives an event, clears the active events and restore the mask. + This is similar to eu_evt_waitAndClr but the events whose bit is set to 1 in the given mask, are activated in the event mask before going to sleep, and are cleared + when the core is waken-up. + Not that this function is using 3 instructions instead of 1 for most of other primitives, as it needs 2 instruction to set and clear the mask. + \param evtMask Event mask used for activating and deactivating events. Each bit to 1 means the corresponding event is activated before sleeping and deactivated after. + */ +static inline unsigned int eu_evt_maskWaitAndClr(unsigned evtMask) +{ + eu_evt_maskSet(evtMask); + unsigned int result = eu_evt_waitAndClr(); + eu_evt_maskClr(evtMask); + return result; +} + +static inline unsigned int eu_fc_evt_maskWaitAndClr(unsigned evtMask) +{ + eu_evt_maskSet(evtMask); + unsigned int result; + do { + result = eu_evt_waitAndClr(); + } while (result == 0); + eu_evt_maskClr(evtMask); + return result; +} + +//!@} + + + + +/** @name Interrupt management + * Functions for setting-up which IRQ can trigger an interrupt handler, clear interrupts and so on + */ +/**@{*/ + +static inline unsigned int eu_evt_statusIrqMasked() +{ + return pulp_read32(ARCHI_EU_DEMUX_ADDR + EU_CORE_BUFFER_IRQ_MASKED); +} + +static inline void eu_irq_mask(unsigned int irqMask) +{ + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_CORE_MASK_IRQ, irqMask); +} + +static inline void eu_irq_secMask(unsigned int irqMask) +{ + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_CORE_MASK_SEC_IRQ, irqMask); +} + +static inline void eu_irq_maskSet_base(unsigned int base, unsigned int irqMask) +{ + pulp_write32(base + EU_CORE_MASK_IRQ_OR, irqMask); +} + +static inline void eu_irq_maskSet(unsigned int irqMask) +{ + eu_irq_maskSet_base(ARCHI_EU_DEMUX_ADDR, irqMask); +} + +static inline void eu_irq_maskClr(unsigned int irqMask) +{ + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_CORE_MASK_IRQ_AND, irqMask); +} + +static inline void eu_irq_secMaskSet(unsigned int irqMask) +{ + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_SEC_DEMUX_OFFSET + EU_SEC_MASK_OR, irqMask); +} + +static inline void eu_irq_secMaskClr(unsigned int irqMask) +{ + pulp_write32(ARCHI_EU_DEMUX_ADDR + EU_SEC_DEMUX_OFFSET + EU_SEC_MASK_AND, irqMask); +} + +static inline unsigned int eu_irq_status() +{ + return pulp_read32(ARCHI_EU_DEMUX_ADDR + EU_CORE_BUFFER_IRQ_MASKED); +} + +//!@} + + + + +/** @name SW event trigger. + * Functions for triggering SW events which can be used to wake-up cluster cores from SW. + */ +/**@{*/ + +static inline unsigned int eu_evt_trig_remote_addr(int event) +{ + return ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET + EU_SW_EVENTS_AREA_BASE + EU_CORE_TRIGG_SW_EVENT + (event << 2); +} + +static inline unsigned int eu_evt_trig_cluster_addr(int cluster, int event) +{ + return ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cluster) + ARCHI_EU_OFFSET + EU_SW_EVENTS_AREA_BASE + EU_CORE_TRIGG_SW_EVENT + (event << 2); +} + +#ifdef ARCHI_HAS_FC +static inline unsigned int eu_evt_trig_fc_addr(int event) +{ +#ifdef ITC_VERSION + return ARCHI_FC_ITC_ADDR + EU_SW_EVENTS_AREA_BASE + EU_CORE_TRIGG_SW_EVENT + (event << 2); +#else + return ARCHI_FC_GLOBAL_ADDR + ARCHI_FC_PERIPHERALS_OFFSET + ARCHI_FC_EU_OFFSET + EU_SW_EVENTS_AREA_BASE + EU_CORE_TRIGG_SW_EVENT + (event << 2); +#endif +} +#endif + +static inline unsigned int eu_evt_trig_addr(int event) +{ + return ARCHI_EU_DEMUX_ADDR + EU_SW_EVENTS_DEMUX_OFFSET + EU_CORE_TRIGG_SW_EVENT + (event << 2); +} + +static inline void eu_evt_trig(unsigned int evtAddr, unsigned int coreSet) +{ + pulp_write32(evtAddr, coreSet); +} + +static inline void eu_evt_trig_from_id(unsigned int event, unsigned int coreSet) +{ + IP_WRITE(ARCHI_EU_DEMUX_ADDR, EU_SW_EVENTS_DEMUX_OFFSET + EU_CORE_TRIGG_SW_EVENT + (event << 2), coreSet); +} + +//!@} + + + +/** @name Hardware barriers. + * Functions for managing the hardware barriers which can be used to implement a rendez-vous + */ + +// Convert barrier ID into barrier address, that can be used more efficiently by +// subsequent operations (usually leads to only 1 lw or sw) +static inline unsigned int eu_bar_addr(int barId) +{ + return ARCHI_EU_DEMUX_ADDR + EU_BARRIER_DEMUX_OFFSET + EU_BARRIER_AREA_OFFSET_GET(barId); +} + +static inline unsigned int eu_bar_id(int barAddr) +{ + return EU_BARRIER_AREA_BARRIERID_GET(barAddr); +} + +// All-in-one barrier: Trigger barrier notif, wait for barrier and clear the event +// This also return the pending active events. +// Barrier event must be active for this to work +static inline unsigned int eu_bar_trig_wait_clr(unsigned int barAddr) +{ + return evt_read32(barAddr, EU_HW_BARR_TRIGGER_WAIT_CLEAR); +} + +static inline void eu_bar_setup_mask(unsigned int barAddr, unsigned int coreMask, unsigned int targetMask) +{ + IP_WRITE(barAddr, EU_HW_BARR_TRIGGER_MASK, coreMask); + IP_WRITE(barAddr, EU_HW_BARR_TARGET_MASK, targetMask); +} + +static inline void eu_bar_setup(unsigned int barAddr, unsigned int coreMask) +{ + eu_bar_setup_mask(barAddr, coreMask, coreMask); +} + +static inline void eu_bar_trigger(unsigned int barAddr, unsigned int mask) +{ + pulp_write32(barAddr + EU_HW_BARR_TRIGGER, mask); +} + +//!@} + + + +/** @name SoC events FIFO. + * Functions for managing SoC events coming from outside the cluster and pushed by the HW to the SoC event FIFO. + */ +/**@{*/ + +static inline unsigned int eu_soc_events_pop() +{ + return pulp_read32(ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET + EU_SOC_EVENTS_AREA_OFFSET + EU_SOC_EVENTS_CURRENT_EVENT); +} + +#ifdef ARCHI_HAS_FC +static inline unsigned int fc_eu_soc_events_pop() +{ +#ifdef ARCHI_FC_PERIPHERALS_ADDR + return pulp_read32(ARCHI_FC_PERIPHERALS_ADDR + ARCHI_EU_OFFSET + EU_SOC_EVENTS_AREA_OFFSET + EU_SOC_EVENTS_CURRENT_EVENT); +#else + return pulp_read32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_EU_OFFSET + EU_SOC_EVENTS_AREA_OFFSET + EU_SOC_EVENTS_CURRENT_EVENT); +#endif +} +#endif + +static inline int eu_soc_events_is_valid(unsigned int word) +{ + return (word >> EU_SOC_EVENTS_VALID_BIT) & 1; +} + +static inline unsigned int eu_soc_events_get_event(unsigned int word) +{ + return word & EU_SOC_EVENTS_EVENT_MASK; +} + +//!@} + + + +/** @name Hardware mutexes. + * Functions for managing, locking and unlocking hardware mutexes + */ +/**@{*/ + +// Convert mutex ID into mutex address, that can be used more efficiently by +// subsequent operations (usually leads to only 1 lw or sw) +static inline unsigned int eu_mutex_addr(int mutexId) +{ + return ARCHI_EU_DEMUX_ADDR + EU_MUTEX_DEMUX_OFFSET + (mutexId << 2); +} + +static inline void eu_mutex_lock(unsigned int mutexAddr) +{ + evt_read32(mutexAddr, 0); +} + +static inline void eu_mutex_lock_from_id(unsigned int id) +{ + evt_read32(ARCHI_EU_DEMUX_ADDR, EU_MUTEX_DEMUX_OFFSET + (id << 2)); +} + +static inline void eu_mutex_unlock(unsigned int mutexAddr) +{ + __asm__ __volatile__ ("" : : : "memory"); + pulp_write32(mutexAddr, 0); + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void eu_mutex_unlock_from_id(int id) +{ + __asm__ __volatile__ ("" : : : "memory"); + IP_WRITE(ARCHI_EU_DEMUX_ADDR, EU_MUTEX_DEMUX_OFFSET + (id<<2), 0); + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void eu_mutex_init(unsigned int mutexAddr) +{ + pulp_write32(mutexAddr, 0); +} + +//!@} + + + +/** @name Hardware dispatcher. + * Functions for managing the hardware dispatcher, which can be used to dispatch entry points to sleeping slave cores. + */ +static inline unsigned int eu_dispatch_pop() +{ + eu_evt_maskSet(1<> 4) +#define ARCHI_GPIO_INTTYPE_GPIO(inttype) ((inttype)*16) +#define ARCHI_GPIO_INTTYPE_SIZE 2 +#define ARCHI_GPIO_INTTYPE_BIT(pad) (((pad) & 0xF) << 1) +#define ARCHI_GPIO_INTTYPE_GET(gpio,value) (((value) >> ARCHI_GPIO_INTTYPE_BIT(gpio)) & ((1<> (32-c)) << d)) +#endif + +/* LOW-LEVEL HAL */ +#define HWCE_ADDR_BASE ARCHI_HWCE_ADDR + +// For all the following functions we use __builtin_pulp_OffsetedWrite and __builtin_pulp_OffsetedRead +// instead of classic load/store because otherwise the compiler is not able to correctly factorize +// the HWCE base in case several accesses are done, ending up with twice more code + +#if defined(__riscv__) && !defined(RV_ISA_RV32) +#define HWCE_WRITE(value, offset) __builtin_pulp_OffsetedWrite(value, (int *)HWCE_ADDR_BASE, offset) +#define HWCE_READ(offset) __builtin_pulp_OffsetedRead((int *)HWCE_ADDR_BASE, offset) +#else +#define HWCE_WRITE(value, offset) pulp_write32(HWCE_ADDR_BASE + (offset), value) +#define HWCE_READ(offset) pulp_read32(HWCE_ADDR_BASE + (offset)) +#endif + +static inline void hwce_y_trans_size_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_TRANS_SIZE); +} + +static inline void hwce_y_line_stride_length_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_LINE_STRIDE_LENGTH); +} + +static inline void hwce_y_feat_stride_length_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_FEAT_STRIDE_LENGTH); +} + +static inline void hwce_y_out_3_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_OUT_3_BASE_ADDR); +} + +static inline void hwce_y_out_2_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_OUT_2_BASE_ADDR); +} + +static inline void hwce_y_out_1_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_OUT_1_BASE_ADDR); +} + +static inline void hwce_y_out_0_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_OUT_0_BASE_ADDR); +} + +static inline void hwce_y_in_3_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_IN_3_BASE_ADDR); +} + +static inline void hwce_y_in_2_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_IN_2_BASE_ADDR); +} + +static inline void hwce_y_in_1_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_IN_1_BASE_ADDR); +} + +static inline void hwce_y_in_0_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_Y_IN_0_BASE_ADDR); +} + +static inline void hwce_x_trans_size_set(unsigned int value) { + HWCE_WRITE(value, HWCE_X_TRANS_SIZE); +} + +static inline void hwce_x_line_stride_length_set(unsigned int value) { + HWCE_WRITE(value, HWCE_X_LINE_STRIDE_LENGTH); +} + +static inline void hwce_x_feat_stride_length_set(unsigned int value) { + HWCE_WRITE(value, HWCE_X_FEAT_STRIDE_LENGTH); +} + +static inline void hwce_x_in_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_X_IN_BASE_ADDR); +} + +static inline void hwce_w_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_W_BASE_ADDR); +} + +static inline void hwce_gen_config0_set(unsigned int value) { + HWCE_WRITE(value, HWCE_GEN_CONFIG0); +} + +static inline unsigned int hwce_gen_config0_get() { + return HWCE_READ(HWCE_GEN_CONFIG0); +} + +static inline void hwce_gen_config1_set(unsigned int value) { + HWCE_WRITE(value, HWCE_GEN_CONFIG1); +} + +static inline unsigned int hwce_gen_config1_get() { + return HWCE_READ(HWCE_GEN_CONFIG1); +} + +static inline void hwce_gen_config2_set(unsigned int value) { + HWCE_WRITE(value, HWCE_GEN_CONFIG2); +} + +static inline unsigned int hwce_gen_config2_get() { + return HWCE_READ(HWCE_GEN_CONFIG2); +} + +static inline void hwce_job_config0_set(unsigned int value) { + HWCE_WRITE(value, HWCE_JOB_CONFIG0); +} + +static inline void hwce_job_config1_set(unsigned int value) { + HWCE_WRITE(value, HWCE_JOB_CONFIG1); +} + +static inline void hwce_job_config2_set(unsigned int value) { + HWCE_WRITE(value, HWCE_JOB_CONFIG2); +} + +static inline void hwce_th_base_addr_set(unsigned int value) { + HWCE_WRITE(value, HWCE_TH_BASE_ADDR); +} + +static inline void hwce_lbufxtranssize_set(unsigned int value) { + HWCE_WRITE(value, HWCE_LBUFXTRANSSIZE_ADDR); +} + +static inline unsigned int hwce_stride_length_value(unsigned int stride, unsigned int length) { + unsigned int res = 0; + res = __hwce_bitinsert(0, stride, 16, 16); + res = __hwce_bitinsert(res, length, 16, 0 ); + return res; +} + +static inline unsigned int hwce_gen_config0_value(unsigned int wstride, unsigned int ncp, unsigned int conv, unsigned vect, unsigned int uns, unsigned int ny, unsigned int nf, unsigned int qf, unsigned int rnd) { + unsigned int res; + res = __hwce_bitinsert(0, wstride, 16, 16); + // res = __hwce_bitinsert(0, norm_bias, 1, 15); + res = __hwce_bitinsert(res, rnd , 1 , 14); + res = __hwce_bitinsert(res, ncp , 1 , 13); + res = __hwce_bitinsert(res, conv , 2 , 11); + res = __hwce_bitinsert(res, vect , 2 , 9); + res = __hwce_bitinsert(res, 0 , 1 , 8); + res = __hwce_bitinsert(res, ny , 1 , 7); + res = __hwce_bitinsert(res, nf , 1 , 6); + res = __hwce_bitinsert(res, qf , 6 , 0); + return res; +} + +static inline unsigned int hwce_gen_config1_value(unsigned int qmodex, unsigned int qshiftx, unsigned int qmodey, unsigned int qshifty, unsigned int thstride) { + unsigned int res = 0; + res = __hwce_bitinsert(res, qmodex, 3, 29); + res = __hwce_bitinsert(res, qshiftx, 5, 24); + res = __hwce_bitinsert(res, qmodey, 3, 21); + res = __hwce_bitinsert(res, qshifty, 5, 16); + res = __hwce_bitinsert(res, thstride, 16, 0); + return res; +} + +static inline unsigned int hwce_gen_config2_value(unsigned int qmodew, unsigned int qshiftw, unsigned int wait_nfeat) { + unsigned int res = 0; + res = __builtin_bitinsert(res, qmodew, 3, 29); + res = __builtin_bitinsert(res, qshiftw, 5, 24); + res = __builtin_bitinsert(res, wait_nfeat, 8, 16); + return res; +} + +static inline unsigned int hwce_job_config0_value(unsigned int noyconst, unsigned int lbuflen, unsigned int lbufskiphi, unsigned int lbufskiplo) { + unsigned int res = 0; + res = __hwce_bitinsert(res, noyconst, 16, 16); + res = __hwce_bitinsert(res, lbufskiphi, 4, 12); + res = __hwce_bitinsert(res, lbufskiplo, 4, 8); + res = __hwce_bitinsert(res, lbuflen, 8, 0); + return res; +} + +static inline unsigned int hwce_job_config1_value(unsigned int lo, unsigned int wif, unsigned int wof, unsigned int vect_disable_mask, unsigned int rect, unsigned int noutfeat) { + unsigned int res = 0; + res = __hwce_bitinsert(res, noutfeat , 8 , 24); + res = __hwce_bitinsert(res, lo , 1 , 23); + res = __hwce_bitinsert(res, rect , 1 , 22); + res = __hwce_bitinsert(res, wif , 6 , 16); + res = __hwce_bitinsert(res, wof , 6 , 8); + res = __hwce_bitinsert(res, vect_disable_mask, 4 , 0); + return res; +} + +static inline unsigned int hwce_job_config2_value(unsigned int bynfeat, unsigned int bye, unsigned int s2, unsigned int lbufprecnt, unsigned int xlrem, unsigned int ylrem, unsigned int ylen) { + unsigned int res; + res = __hwce_bitinsert(0, bynfeat , 8 , 24); + res = __hwce_bitinsert(res, bye , 1 , 23); + res = __hwce_bitinsert(res, s2 , 1 , 22); + res = __hwce_bitinsert(res, xlrem , 2 , 20); + res = __hwce_bitinsert(res, ylrem , 2 , 18); + res = __hwce_bitinsert(res, ylen , 8 , 8); + res = __hwce_bitinsert(res, lbufprecnt , 8 , 0); + return res; +} + +static inline void hwce_wait_event() { + eu_evt_maskWaitAndClr(1 << EVENT_HWCE); +} + +static inline void hwce_trigger_job() { + HWCE_WRITE(0, HWCE_TRIGGER); +} + +static inline void hwce_sw_evt() { + HWCE_WRITE(0, HWCE_SW_EVT); +} + +static inline int hwce_acquire_job() { + return HWCE_READ(HWCE_ACQUIRE); +} + +static inline void hwce_soft_clear() { + volatile int i; + HWCE_WRITE(1, HWCE_SOFT_CLEAR); + for(i=0; i<3; i++); + HWCE_WRITE(0, HWCE_SOFT_CLEAR); +} + +static inline void hwce_cg_enable() { + *(volatile int*) (ARCHI_CLUSTER_CTRL_ADDR + (3 << 3)) |= 0xc00; +} + +static inline void hwce_cg_disable() { + *(volatile int*) (ARCHI_CLUSTER_CTRL_ADDR + (3 << 3)) &= ~0xc00; +} + +#endif /* __HWCE_HAL_H__ */ + diff --git a/sw/pulp-sdk/hal/include/hal/hwme/hwme_v1.h b/sw/pulp-sdk/hal/include/hal/hwme/hwme_v1.h new file mode 100644 index 0000000..c27c3a2 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/hwme/hwme_v1.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Authors: Francesco Conti + */ + +#ifndef __HAL_HWME_V1_H__ +#define __HAL_HWME_V1_H__ + +#include "hal/pulp.h" + +#if HWME_VERSION != 1 + #error This file must be included only with XNE version 1. +#endif + +/* + * Control and generic configuration register layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0000 | 31: 0 | 0xffffffff || TRIGGER + * 1 | 0x0004 | 31: 0 | 0xffffffff || ACQUIRE + * 2 | 0x0008 | 31: 0 | 0xffffffff || EVT_ENABLE + * 3 | 0x000c | 31: 0 | 0xffffffff || STATUS + * 4 | 0x0010 | 31: 0 | 0xffffffff || RUNNING_JOB + * 5 | 0x0014 | 31: 0 | 0xffffffff || SOFT_CLEAR + * 6-7 | | | || Reserved + * 8 | 0x0020 | 31: 0 | 0xffffffff || BYTECODE0 [31:0] + * 9 | 0x0024 | 31: 0 | 0xffffffff || BYTECODE1 [63:32] + * 10 | 0x0028 | 31: 0 | 0xffffffff || BYTECODE2 [95:64] + * 11 | 0x002c | 31: 0 | 0xffffffff || BYTECODE3 [127:96] + * 12 | 0x0030 | 31: 0 | 0xffffffff || BYTECODE4 [159:128] + * 13 | 0x0034 | 31:16 | 0xffff0000 || LOOPS0 [15:0] + * | | 15: 0 | 0x0000ffff || BYTECODE5 [175:160] + * 14 | 0x0038 | 31: 0 | 0xffffffff || LOOPS1 [47:16] + * 15 | | 31: 0 | 0xffffffff || Reserved + * ================================================================================ + * + * Job-dependent registers layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0040 | 31: 0 | 0xffffffff || A_ADDR + * 1 | 0x0044 | 31: 0 | 0xffffffff || B_ADDR + * 2 | 0x0048 | 31: 0 | 0xffffffff || C_ADDR + * 3 | 0x004c | 31: 0 | 0xffffffff || D_ADDR + * 4 | 0x0050 | 31: 0 | 0xffffffff || NB_ITER + * 5 | 0x0054 | 31: 0 | 0xffffffff || LEN_ITER + * 6 | 0x0058 | 31:16 | 0xffff0000 || SHIFT + * | | 0: 0 | 0x00000001 || SIMPLEMUL + * 7 | 0x005c | 31: 0 | 0xffffffff || VECTSTRIDE + * 8 | 0x0060 | 31: 0 | 0xffffffff || VECTSTRIDE2 + * ================================================================================ + * + */ + +/* LOW-LEVEL HAL */ +#define HWME_ADDR_BASE ARCHI_FC_HWPE_ADDR +#define HWME_ADDR_SPACE 0x00000100 + +// For all the following functions we use __builtin_pulp_OffsetedWrite and __builtin_pulp_OffsetedRead +// instead of classic load/store because otherwise the compiler is not able to correctly factorize +// the HWME base in case several accesses are done, ending up with twice more code + +#if defined(__riscv__) && !defined(RV_ISA_RV32) +#define HWME_WRITE(value, offset) __builtin_pulp_OffsetedWrite(value, (int *)HWME_ADDR_BASE, offset) +#define HWME_READ(offset) __builtin_pulp_OffsetedRead((int *)HWME_ADDR_BASE, offset) +#else +#define HWME_WRITE(value, offset) pulp_write32(HWME_ADDR_BASE + (offset), value) +#define HWME_READ(offset) pulp_read32(HWME_ADDR_BASE + (offset)) +#endif + +static inline void hwme_bytecode_set(unsigned int offs, unsigned int value) { + HWME_WRITE(value, HWME_BYTECODE+offs); +} + +static inline void hwme_a_addr_set(unsigned int value) { + HWME_WRITE(value, HWME_A_ADDR); +} + +static inline void hwme_b_addr_set(unsigned int value) { + HWME_WRITE(value, HWME_B_ADDR); +} + +static inline void hwme_c_addr_set(unsigned int value) { + HWME_WRITE(value, HWME_C_ADDR); +} + +static inline void hwme_d_addr_set(unsigned int value) { + HWME_WRITE(value, HWME_D_ADDR); +} + +static inline void hwme_nb_iter_set(unsigned int value) { + HWME_WRITE(value, HWME_NB_ITER); +} + +static inline void hwme_len_iter_set(unsigned int value) { + HWME_WRITE(value, HWME_LEN_ITER); +} + +static inline void hwme_shift_simplemul_set(unsigned int value) { + HWME_WRITE(value, HWME_SHIFT_SIMPLEMUL); +} + +static inline void hwme_vectstride_set(unsigned int value) { + HWME_WRITE(value, HWME_VECTSTRIDE); +} + +static inline void hwme_vectstride2_set(unsigned int value) { + HWME_WRITE(value, HWME_VECTSTRIDE2); +} + +static inline unsigned int hwme_shift_simplemul_value( + unsigned short shift, + unsigned simplemul +) { + unsigned int res = 0; +#if defined(__riscv__) && !defined(RV_ISA_RV32) + res = __builtin_bitinsert(0, shift, 16, 16); + res = __builtin_bitinsert(res, simplemul, 8, 0); +#else + res |= ((shift & 0xffff) << 16) | + ((simplemul & 0xff)); +#endif + return res; +} + +static inline void hwme_trigger_job() { + HWME_WRITE(0, HWME_TRIGGER); +} + +static inline int hwme_acquire_job() { + return HWME_READ(HWME_ACQUIRE); +} + +static inline unsigned int hwme_get_status() { + return HWME_READ(HWME_STATUS); +} + +static inline void hwme_soft_clear() { + volatile int i; + HWME_WRITE(0, HWME_SOFT_CLEAR); +} + +static inline void plp_hwme_enable() { + *(volatile int*) (ARCHI_SOC_EU_ADDR + (3 << 3)) |= 0xc00; +} + +static inline void plp_hwme_disable() { + *(volatile int*) (ARCHI_SOC_EU_ADDR + (3 << 3)) &= ~0xc00; +} + +#endif /* __HAL_HWME_V1_H__ */ + diff --git a/sw/pulp-sdk/hal/include/hal/icache/icache_ctrl_v1.h b/sw/pulp-sdk/hal/include/hal/icache/icache_ctrl_v1.h new file mode 100644 index 0000000..8ae06b9 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/icache/icache_ctrl_v1.h @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_ICACHE_ICACHE_CTRL_V1_H__ +#define __HAL_ICACHE_ICACHE_CTRL_V1_H__ + +#include "archi/pulp.h" + +// Flush the L0 buffers, each bit of conf identifies a L0 Buffer Block +static inline void flush_L0_buffers(int conf){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x0CU) = conf; + return; +} + +// Enable All Icache Banks api +static inline void enable_all_icache_banks(void){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = 0xFFFFFFFF; + return; +} + +static inline void hal_icache_cluster_enable(int cid) +{ + pulp_write32(ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_ICACHE_CTRL_OFFSET, 0xFFFFFFFF); +} + +static inline void icache_enable(unsigned int base) +{ + pulp_write32(base, 0xFFFFFFFF); +} + +// Disable all icache banks routine +static inline void disable_all_icache_banks(void){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = 0x00000000; + return; +} + +// Reset the statistic counters in each icache banks +static inline void reset_all_icache_stat_regs(void){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x10U) = 0xFFFFFFFF; + return; +} + +// Enable all the statistic counters in all icache banks available +static inline void start_all_icache_stat_regs(void){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x14U) = 0xFFFFFFFF; + return; +} + +// Disable all the statistic counters in all icache banks available +static inline void stop_all_icache_stat_regs(void){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x14U) = 0x00000000; + return; +} + +// Read Hit counter reg in a specified icache bank +static inline unsigned int read_hit_icache_reg(unsigned int bank){ + volatile unsigned int reg_status; + reg_status = *(volatile unsigned int *) (ARCHI_ICACHE_CTRL_ADDR+0x18U+bank*0x04U); + return reg_status; +} + +// Read Total transaction counter reg in a specified icache bank +static inline unsigned int read_trans_icache_reg(unsigned int bank){ + volatile unsigned int reg_status; + reg_status = *(volatile unsigned int *) (ARCHI_ICACHE_CTRL_ADDR+0x28U+bank*0x04U); + return reg_status; +} + +// Read Total transaction counter reg in a specified icache bank +static inline unsigned int read_stall_icache_reg(unsigned int bank){ + return 0x0U; +} + +static inline void flush_all_icache_banks(void){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x04U) = -1;// write 4'b1111 in the flush reg + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = 0x0;// disable the icache banks + + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = -1;// enable the icache banks + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x04U) = 0x0;// write 4'b000 in the flush reg + return; +} + +static inline int read_enable_icache_reg(void){ + volatile int reg_status; + reg_status = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR); + return reg_status; +} + +static inline int read_status_icache_reg(void){ + volatile int reg_status; + reg_status = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x08U); + return reg_status; +} + +static inline void flush_some_icache_banks(int conf){ + volatile int current_conf = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x08U); + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = conf ^ current_conf; + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = current_conf; + return; +} + +static inline void set_icache_banks_conf(int conf){ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = conf; + return; +} + +static inline void set_icache_private(void){ + + //Disable all icache banks + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x04U) = -1;// write 4'b1111 in the flush reg + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = 0x0;// disable the icache banks + + //Drive the icache_is_private signal + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0xF0U) = 0x1; + + //Enable all icache banks + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = -1;// enable the icache banks + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x04U) = 0x0;// write 4'b000 in the flush reg + return; +} + +static inline void set_icache_shared(void){ + + //Disable all icache banks + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x04U) = -1;// write 4'b1111 in the flush reg + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = 0x0;// disable the icache banks + + //Drive the icache_is_private signal + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0xF0U) = 0x0; + + //Enable all icache banks + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = -1;// enable the icache banks + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x04U) = 0x0; // write 4'b000 in the flush reg + return; +} + +static inline int read_icache_pri_sh_reg(void){ + volatile int reg_status; + reg_status = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0xF0U); + return reg_status; +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/icache/icache_ctrl_v2.h b/sw/pulp-sdk/hal/include/hal/icache/icache_ctrl_v2.h new file mode 100644 index 0000000..d8b17fb --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/icache/icache_ctrl_v2.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_ICACHE_ICACHE_CTRL_V2_H__ +#define __HAL_ICACHE_ICACHE_CTRL_V2_H__ + +#include "hal/pulp.h" + +static inline unsigned int plp_icache_cluster_remote_base(int cid) { return ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_ICACHE_CTRL_OFFSET; } + +static inline unsigned int plp_icache_cluster_base(int cid) { return ARCHI_ICACHE_CTRL_ADDR; } + +static inline unsigned int plp_icache_fc_base() { return ARCHI_ICACHE_CTRL_ADDR; } + +// Enable All Icache Banks api +static inline void enable_all_icache_banks ( ) +{ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = 0xFFFFFFFF; +} + +static inline void hal_icache_cluster_enable(int cid) +{ + pulp_write32(ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_ICACHE_CTRL_OFFSET, 0xFFFFFFFF); +} + +static inline void icache_enable(unsigned int base) +{ + pulp_write32(base, 0xFFFFFFFF); +} + +static inline void icache_disable(unsigned int base) +{ + pulp_write32(base, 0); +} + +// Disable all icache banks routine +static inline void disable_all_icache_banks ( ) +{ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR) = 0x00000000; +} + + + +// Reset the statistic counters in each icache banks +static inline void reset_all_icache_stat_regs() +{ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x10) = 0xFFFFFFFF; +} + + +// Enable all the statisctic counters in all icache banks availabe +static inline void start_all_icache_stat_regs() +{ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x14) = 0xFFFFFFFF; +} + +// Disable all the statisctic counters in all icache banks availabe +static inline void stop_all_icache_stat_regs() +{ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x14) = 0x00000000; +} + + +static inline int read_hit_icache_reg( ) +{ + volatile int reg_status; + reg_status = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x40); + return reg_status; +} + + +static inline int read_trans_icache_reg( ) +{ + volatile int reg_status; + //FIXME we need to know how many banks are used + reg_status = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR +0x44); + return reg_status; +} + + + +static inline void flush_all_icache_banks_common ( unsigned int base ) +{ + *(volatile int*) (base+0x4) = 1; +} + + + + + +static inline void flush_all_icache_banks ( ) +{ + flush_all_icache_banks_common(ARCHI_ICACHE_CTRL_ADDR); +} + +static inline void selective_flush_icache_addr (unsigned int address ) +{ + *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x8) = address; // write 4'b1111 in the flush reg +} + + +static inline int read_enable_icache_reg( ) +{ + volatile int reg_status; + reg_status = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR + 0x0C); + return reg_status; +} + + + + + + +static inline int read_status_icache_reg( ) +{ + volatile int reg_status; + + reg_status = *(volatile int*) (ARCHI_ICACHE_CTRL_ADDR+0x08); + + return reg_status; +} +#endif diff --git a/sw/pulp-sdk/hal/include/hal/itc/itc_v1.h b/sw/pulp-sdk/hal/include/hal/itc/itc_v1.h new file mode 100644 index 0000000..802ed10 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/itc/itc_v1.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_ITC_ITC_V1_H__ +#define __HAL_ITC_ITC_V1_H__ + +#include "hal/pulp.h" +#include "hal/pulp_io.h" +#include "archi/itc/itc_v1.h" + + +static inline void hal_itc_enable_value_set(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_MASK_OFFSET, mask); +} + +static inline unsigned int hal_itc_enable_value_get() { + return pulp_read32(ARCHI_FC_ITC_ADDR + ITC_MASK_OFFSET); +} + +static inline void hal_itc_enable_set(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_MASK_SET_OFFSET, mask); +} + +static inline void hal_itc_enable_clr(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_MASK_CLR_OFFSET, mask); +} + + +static inline void hal_itc_ack_value_set(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_ACK_OFFSET, mask); +} + +static inline unsigned int hal_itc_ack_value_get() { + return pulp_read32(ARCHI_FC_ITC_ADDR + ITC_ACK_OFFSET); +} + +static inline void hal_itc_ack_set(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_ACK_SET_OFFSET, mask); +} + +static inline void hal_itc_ack_clr(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_ACK_CLR_OFFSET, mask); +} + + + +static inline void hal_itc_status_value_set(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_STATUS_OFFSET, mask); +} + +static inline void hal_itc_status_value_set_remote(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_STATUS_OFFSET, mask); +} + +static inline unsigned int hal_itc_status_value_get() { + return pulp_read32(ARCHI_FC_ITC_ADDR + ITC_STATUS_OFFSET); +} + +static inline void hal_itc_status_set(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_STATUS_SET_OFFSET, mask); +} + +static inline void hal_itc_status_clr(unsigned int mask) { + pulp_write32(ARCHI_FC_ITC_ADDR + ITC_STATUS_CLR_OFFSET, mask); +} + + +static inline unsigned int hal_itc_fifo_pop() { + return pulp_read32(ARCHI_FC_ITC_ADDR + ITC_FIFO_OFFSET); +} + + +static inline void hal_itc_wait_for_interrupt() { + asm volatile ("wfi"); +} + + +static inline void hal_itc_wait_for_event_noirq(unsigned int mask) { + + int end = 0; + do { + + unsigned int state = hal_irq_disable(); + if ((hal_itc_status_value_get() & mask) == 0) { + hal_itc_enable_set(mask); + asm volatile ("wfi"); + hal_itc_enable_clr(mask); + } else { + hal_itc_status_clr(mask); + end = 1; + } + hal_irq_restore(state); + } while (!end); +} + + +static inline void hal_itc_wait_for_event(unsigned int mask) { + hal_itc_wait_for_event_noirq(mask); +} + + + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/maestro/pmu_v1.h b/sw/pulp-sdk/hal/include/hal/maestro/pmu_v1.h new file mode 100644 index 0000000..9026951 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/maestro/pmu_v1.h @@ -0,0 +1,337 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_MAESTRO_PMU_V1_H__ +#define __HAL_MAESTRO_PMU_V1_H__ + +#include "hal/pulp.h" +#include "archi/maestro/maestro_v1.h" + +/* APB Interface */ +#define PCTRL 0x0 +#define PRDATA 0x4 +#define DLC_SR 0x8 +#define DLC_IMR 0xC +#define DLC_IFR 0x10 +#define DLC_IOIFR 0x14 +#define DLC_IDIFR 0x18 +#define DLC_IMCIFR 0x1C + +#define PMU_Read(reg) __builtin_pulp_OffsetedRead((void *) PMU_DLC_BASE_ADDRESS, (reg)) +#define PMU_Write(reg, value) IP_WRITE(PMU_DLC_BASE_ADDRESS, (reg), (value)) + +// #define SOC_PERIPHERALS_BASE_ADDR (0x1A100000) +// #define APB_SOC_CTRL_ADDR (SOC_PERIPHERALS_BASE_ADDR+0x3000) + +/* Base address for programming interface of PMU: 0x1A106000 */ +// #define PMU_DLC_OFFSET 0x6000 +#define PMU_DLC_OFFSET ARCHI_PMU_OFFSET +#define PMU_DLC_BASE_ADDRESS (ARCHI_SOC_PERIPHERALS_ADDR + PMU_DLC_OFFSET) + +/* Cluster Reset and transaction isolation */ +#define PMU_CLUSTER_RESET_OFFSET 0x8 +#define PMU_CLUSTER_RESET_REG (ARCHI_APB_SOC_CTRL_ADDR + PMU_CLUSTER_RESET_OFFSET) + +#define PMU_CLUSTER_TRANSAC_ISOLATE_OFFSET 0xC +#define PMU_CLUSTER_TRANSAC_ISOLATE_REG (ARCHI_APB_SOC_CTRL_ADDR + PMU_CLUSTER_TRANSAC_ISOLATE_OFFSET) + +/* Voltage definition, 0x1A103100 */ +#define PMU_DCDC_CONFIG_OFFSET 0x100 +#define PMU_DCDC_CONFIG_REG (ARCHI_APB_SOC_CTRL_ADDR + PMU_DCDC_CONFIG_OFFSET) + +/* PMU bypass for cluster ON/OFF control */ +#define APB_SOC_CL_BYPASS_OFFSET 0x70 +#define PMU_BYPASS_REG (ARCHI_APB_SOC_CTRL_ADDR + APB_SOC_CL_BYPASS_OFFSET) + +/* Retention control, 0x1A103104. Aliased at 0x1A10007C */ +#define PMU_RETENTION_CONFIG_OFFSET 0x104 +#define PMU_RETENTION_CONFIG_ALIAS_OFFSET 0x7C +#define PMU_RETENTION_CONFIG_REG (ARCHI_APB_SOC_CTRL_ADDR + PMU_RETENTION_CONFIG_OFFSET) +#define PMU_RETENTION_CONFIG_ALIAS_REG (ARCHI_APB_SOC_CTRL_ADDR + PMU_RETENTION_CONFIG_ALIAS_OFFSET) + +/* Retention forcing, 0x1A103108 */ +#define PMU_RETENTION_FORCE_CONFIG_OFFSET 0x108 +#define PMU_RETENTION_FORCE_CONFIG_REG (ARCHI_APB_SOC_CTRL_ADDR + PMU_RETENTION_FORCE_CONFIG_OFFSET) + +#define GAP8_MAX_LV_FREQUENCY 150000000 +#define GAP8_MAX_NV_FREQUENCY 250000000 + +/* Voltage regulator and power states */ + +#define DCDC_OPER_POINTS 4 + +#define DCDC_DEFAULT_NV 1200 +#define DCDC_DEFAULT_MV 1200 +#define DCDC_DEFAULT_LV 1000 +#define DCDC_DEFAULT_RET 800 + +#define DCDC_RANGE 5 +#define DCDC_BASE_VALUE 550 +#define DCDC_STEP 50 + +#define mVtoDCDCSetting(mV) ((unsigned int) (((mV) - DCDC_BASE_VALUE)/DCDC_STEP)) +#define DCDCSettingtomV(Dc) ((unsigned int) ((Dc)*DCDC_STEP + DCDC_BASE_VALUE)) + +#define MAX_DCDC_VARIATION (int) (0.1*32767) + +typedef enum { + REGU_NV = 0, + REGU_LV = 1, + REGU_RET = 2, + REGU_OFF = 3 +} PMU_RegulatorStateT; + +typedef enum { + CLUSTER_OFF = 0, + CLUSTER_ON = 1 +} PMU_ClusterStateT; + +#define PMU_STATES 6 +#define PMU_LAST_STATE 6 +#define PMU_LN2_STATES 3 +#define REGU_STATE_SIZE 2 +#define REGU_STATE_OFFSET 1 +#define CLUSTER_STATE_SIZE 1 +#define CLUSTER_STATE_OFFSET 0 + +typedef enum { + SOC_CLUSTER_HP = ((REGU_NV<<1) | CLUSTER_ON), /* 001 = 1 */ + SOC_CLUSTER_LP = ((REGU_LV<<1) | CLUSTER_ON), /* 011 = 3 */ + SOC_HP = ((REGU_NV<<1) | CLUSTER_OFF), /* 000 = 0 */ + SOC_LP = ((REGU_LV<<1) | CLUSTER_OFF), /* 010 = 2 */ + RETENTIVE = ((REGU_RET<<1) | CLUSTER_OFF), /* 100 = 4 */ + DEEP_SLEEP = ((REGU_OFF<<1) | CLUSTER_OFF) /* 110 = 6 */ +} PMU_SystemStateT; + +#define POWER_SYSTEM_STATE(ReguState, ClusterState) ((PMU_SystemStateT) (((ReguState)<<1)|(ClusterState))) +#define REGULATOR_STATE(State) ((PMU_RegulatorStateT) (__builtin_bitextractu((State), REGU_STATE_SIZE, REGU_STATE_OFFSET))) +#define CLUSTER_STATE(State) ((PMU_ClusterStateT) (__builtin_bitextractu((State), CLUSTER_STATE_SIZE, CLUSTER_STATE_OFFSET))) + +typedef enum { + PMU_CHANGE_OK = 0, + PMU_CHANGE_ERROR = 1 +} PMU_StatusT; + +#define LN2_DCDC_OPER_POINTS 2 +typedef enum { + DCDC_Nominal = 0, + DCDC_Medium = 1, + DCDC_Low = 2, + DCDC_Retentive = 3, +} PMU_DCDC_HW_OperatingPointT; + + +typedef enum { + SCU_DEEP_SLEEP = 0, + SCU_RETENTIVE = 1, + SCU_SOC_HP = 2, + SCU_SOC_LP = 3, + SCU_SOC_CLUSTER_HP = 4, + SCU_SOC_CLUSTER_LP = 5, +} PMU_SCU_Seq; + +typedef enum { /* Enum encoding follows the definition of the boot_type field of PMU_RetentionStateT */ + COLD_BOOT=0, /* SoC cold boot, from Flash usually */ + DEEP_SLEEP_BOOT=1, /* Reboot from deep sleep state, state has been lost, somehow equivalent to COLD_BOOT */ + RETENTIVE_BOOT=2, /* Reboot from Retentive state, state has been retained, should bypass flash reload */ + FAST_DEEP_SLEEP_BOOT=3 +} PMU_WakeupStateT; + +typedef enum { + BOOT_FROM_ROM=0, + BOOT_FROM_L2=1, +} PMU_BootMode_T; + +typedef enum { + EXT_WAKEUP_RAISING_EDGE = 0, + EXT_WAKEUP_FALLING_EDGE = 1, + EXT_WAKEUP_HIGH = 2, + EXT_WAKEUP_LOW = 3, +} WakeupMode_T; + +/* PMU Events */ +#define PMU_EVENT_CLUSTER_ON_OFF (ARCHI_SOC_EVENT_CLUSTER_ON_OFF) +#define PMU_EVENT_MSP (ARCHI_SOC_EVENT_MSP) +#define PMU_EVENT_ICU_MODE_CHANGED (ARCHI_SOC_EVENT_ICU_MODE_CHANGED) +#define PMU_EVENT_ICU_OK (ARCHI_SOC_EVENT_ICU_OK) +#define PMU_EVENT_CLUSTER_CLOCK_GATE (ARCHI_SOC_EVENT_ICU_DELAYED) +#define PMU_EVENT_PICL_OK (ARCHI_SOC_EVENT_PICL_OK) +#define PMU_EVENT_SCU_OK (ARCHI_SOC_EVENT_SCU_OK) +#define PMU_EVENT_SCU_PENDING (ARCHI_SOC_EVENT_PMU_NB_EVENTS) + +/* Retention state */ +#define L2_RETENTIVE_REGION 4 +#define N_GPIO 32 +#define LN2_N_GPIO 5 + +typedef union { + struct { +#if PULP_CHIP_FAMILY == CHIP_GAP + unsigned int L2Retention:L2_RETENTIVE_REGION; /* 1 enable bit per area */ + unsigned int FllSoCRetention:1; /* 1: Soc Fll is state retentive */ + unsigned int FllClusterRetention:1; /* 1: Cluster Fll is state retentive */ +#else + unsigned int FllSoCRetention:1; /* 1: Soc Fll is state retentive */ + unsigned int FllClusterRetention:1; /* 1: Cluster Fll is state retentive */ + unsigned int L2Retention:L2_RETENTIVE_REGION; /* 1 enable bit per area */ +#endif + unsigned int ExternalWakeUpSource:LN2_N_GPIO; /* 00000: GPIO0, 00001: GPIO1, ..., 11111: GPIO31 */ + unsigned int ExternalWakeUpMode: 2; /* 00: raise, 01: fall, 10: high, 11: low */ + unsigned int ExternalWakeupEnable:1; /* 0: disable ext wake up, 1: enable ext wake up */ + unsigned int WakeupState:2; /* 00: SOC_HP, 01: SOC_LP, 10: SOC_CLUSTER_HP, 11: SOC_CLUSTER_LP */ + unsigned int BootMode:1; /* 0: boot from rom, 1: boot from L2 */ + unsigned int WakeupCause:1; /* Wake up it status, read clears, 0: RTC, 1: External event */ + unsigned int BootType:2; /* 00: cold boot, 01: deep sleep, 10: retentive deep sleep */ + unsigned int ClusterWakeUpState:1; /* Cluster State we want at wake up, to be used if we wanmt bypass mode at wake up */ + } Fields; + unsigned int Raw; +} PMU_RetentionStateT; + +typedef union { + struct { + unsigned int L2_Area_Retentive:4; /* L2 Area 0, 1, 2, 3 is forced to retentive state */ + unsigned int L2_Area_Down:4; /* L2 Area 0, 1, 2, 3 is forced to shutdown */ + unsigned int Fll_Cluster_Retentive:1; /* Cluster Fll is forced to retentive */ + unsigned int Fll_Cluster_Down:1; /* Cluster Fll is forced to shutdown */ + } Fields; + unsigned int Raw; +} PMU_ForcedRetentionStateT; + +#if PULP_CHIP_FAMILY == CHIP_GAP +/* PMU bypass control for fast Cluster ON/OFF sequences */ +typedef union { + struct { + unsigned int Bypass:1; /* b0 1: Bypass maestro */ + unsigned int BypassConfig:1; /* b1 0: Use default config, 1: Use user config, fields are bellow */ + unsigned int Pad0:1; /* b2 */ + unsigned int ClusterState:1; /* b3 0: Cluster Off, 1: Cluster On */ + unsigned int TRCMaxCurrent:3; /* b4..6 When in BypassConfig and On state, max current allowed on the TRC */ + unsigned int TRCDelay:2; /* b7..8 When in BypassConfig and On state number of 32K cycles after pwr ok to release isolation */ + unsigned int BypassClock:1; /* b9 1: Bypass clock and reset control by Maestro */ + unsigned int ClusterClockGate:1; /* b10 1: Clock gate the cluster, should always be used before shutdown or retention */ + unsigned int ClockDown:1; /* b11 1: Set Cluster FLL to off state */ + unsigned int ClockRetentive:1; /* b12 1: Set Cluster FLL to retentive state */ + unsigned int ClusterReset:1; /* b13 1: If in Bypass Clock controls the cluster reset */ + unsigned int Pad1:2; /* b14..15 Padding */ + unsigned int TRCPowerOk:1; /* b16 Power ok coming from TRC */ + unsigned int PMUPowerDown:1; /* b17 Power down as reported from maestro */ + } Fields; + unsigned int Raw; +} PMU_BypassT; +#else +/* PMU bypass control for fast Cluster ON/OFF sequences */ +typedef union { + struct { + unsigned int Bypass:1; /* b0 1: Enabled bypass*/ + unsigned int ClusterState:1; /* b1 0: Cluster Off, 1: Cluster On */ + unsigned int ClusterClockGate:1; /* b2 1: Clock gate the cluster, should always be used before shutdown or retention */ + unsigned int ClockRetentive:1; /* b3 1: Set Cluster FLL to retentive state */ + unsigned int ClockDown:1; /* b4 1: Set Cluster FLL to off state */ + unsigned int ClusterReset:1; /* b5 1: If in Bypass Clock controls the cluster reset */ + unsigned int Isolate:1; /* b6 Isolate */ + unsigned int ClusterRetentive:1; /* b7 1: Set cluster to retentive state */ + unsigned int TRCPowerOk:1; /* b8 Power ok coming from TRC */ + unsigned int PMUClockEnableAck:1; /* b9 Cluster clock gate acknowledge */ + unsigned int PMUPowerDown:1; /* b10 Power down as reported from maestro */ + } Fields; + unsigned int Raw; +} PMU_BypassT; +#endif + + +extern PMU_RetentionStateT PMURetentionState; + +static inline void PMU_ResetCluster(unsigned int Value) { + unsigned int Val = IP_READ(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_CL_BYPASS_OFFSET); + PMU_BypassT ByPass; + ByPass.Raw = Val; + ByPass.Fields.ClusterReset = Value; + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_CL_BYPASS_OFFSET, ByPass.Raw); + // __builtin_pulp_OffsetedWrite(Value, (int *) APB_SOC_CTRL_ADDR, PMU_CLUSTER_RESET_OFFSET); +} + +static inline void PMU_IsolateCluster(unsigned int Value) { + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, PMU_CLUSTER_TRANSAC_ISOLATE_OFFSET, Value); +} + +static inline unsigned int GetPMUBypass() { + return IP_READ(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_CL_BYPASS_OFFSET); +} + +static inline void SetPMUBypass(unsigned int Value) { + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_CL_BYPASS_OFFSET, Value); +} + +static inline unsigned int GetRetentiveState() { + return IP_READ(ARCHI_APB_SOC_CTRL_ADDR, PMU_RETENTION_CONFIG_OFFSET); +} + +static inline void SetRetentiveState(unsigned Value) { + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, PMU_RETENTION_CONFIG_OFFSET, Value); +} + +static inline unsigned int GetForcedRetentiveState() { + return IP_READ(ARCHI_APB_SOC_CTRL_ADDR, PMU_RETENTION_FORCE_CONFIG_OFFSET); +} + +static inline void SetForcedRetentiveState(unsigned Value) { + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, PMU_RETENTION_FORCE_CONFIG_OFFSET, Value); +} + +static inline unsigned int GetDCDCSetting() { + return IP_READ(ARCHI_APB_SOC_CTRL_ADDR, PMU_DCDC_CONFIG_OFFSET); +} + +static inline void SetDCDCSetting(unsigned int Value) { + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, PMU_DCDC_CONFIG_OFFSET, Value); +} + + +static inline void hal_pmu_bypass_set(unsigned int Value) { + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_CL_BYPASS_OFFSET, Value); +} + +static inline unsigned int hal_pmu_bypass_get() { + return IP_READ(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_CL_BYPASS_OFFSET); +} + +static inline PMU_WakeupStateT SoC_WakeupState() + +{ +/* + PMU_RetentionStateT State; + State.Raw = GetRetentiveState(); +*/ + return ((PMU_WakeupStateT) PMURetentionState.Fields.BootType); +} + +static inline void ConfigureExternalWup(unsigned int Gpio, WakeupMode_T WupMode, unsigned Enable) + +{ + PMURetentionState.Fields.ExternalWakeUpSource = Gpio; + PMURetentionState.Fields.ExternalWakeUpMode = WupMode; + PMURetentionState.Fields.ExternalWakeupEnable = Enable; + SetRetentiveState(PMURetentionState.Raw); +} + +static inline void EnableExternalWakeup(unsigned int Enable) + +{ + PMURetentionState.Fields.ExternalWakeupEnable = Enable; + SetRetentiveState(PMURetentionState.Raw); +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/maestro/pmu_v2.h b/sw/pulp-sdk/hal/include/hal/maestro/pmu_v2.h new file mode 100644 index 0000000..d3db7bd --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/maestro/pmu_v2.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_MAESTRO_PMU_V2_H__ +#define __HAL_MAESTRO_PMU_V2_H__ + +#include "hal/pulp.h" +#include "archi/maestro/maestro_v2.h" + +static inline void hal_pmu_bypass_set(unsigned int Value) { + IP_WRITE(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_BYPASS_OFFSET, Value); +} + +static inline unsigned int hal_pmu_bypass_get() { + return IP_READ(ARCHI_APB_SOC_CTRL_ADDR, APB_SOC_BYPASS_OFFSET); +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/maestro/pmu_v3.h b/sw/pulp-sdk/hal/include/hal/maestro/pmu_v3.h new file mode 100644 index 0000000..516cb0d --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/maestro/pmu_v3.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_MAESTRO_PMU_V3_H__ +#define __HAL_MAESTRO_PMU_V3_H__ + +#include "hal/pulp.h" +#include "archi/maestro/maestro_v3.h" + + +#define PMU_PICL_PACK(chipsel,addr) (((chipsel) << 5) | (addr)) +#define PMU_DLC_PACK(state,picl) (((state) << 16) | ((picl) << 1) | 0x1); //write 0x2 at picl_reg + + + +#define PMU_WRITE(offset, value) IP_WRITE(ARCHI_PMU_ADDR, offset, value) +#define PMU_READ(offset) IP_READ(ARCHI_PMU_ADDR, offset) + + + +static inline void maestro_picl_write(unsigned int island, unsigned int addr, unsigned int value) +{ + unsigned int picl_reg = PMU_PICL_PACK(island, addr); + unsigned int dlc_reg = PMU_DLC_PACK(value, picl_reg); + PMU_WRITE(MAESTRO_DLC_PCTRL_OFFSET, dlc_reg); +} + + +static inline __attribute__((always_inline)) void maestro_trigger_sequence(unsigned int seq) +{ + // Compute the right register ID / bit shift as each WIU IFR register is 8 bits wide + int reg_id = MAESTRO_WIU_IFR_0_OFFSET + (seq >> 3); + int seq_id = seq & 0x7; + + maestro_picl_write(MAESTRO_WIU_OFFSET, reg_id, 1< + +#define __CHIP_INC(x) #x +#define _CHIP_INC(x) __CHIP_INC(hal/chips/x/pulp.h) +#define CHIP_INC(x) _CHIP_INC(x) + +#if defined(PULP_CHIP_FAMILY) +#include CHIP_INC(PULP_CHIP_FAMILY_STR) +#else +#include CHIP_INC(PULP_CHIP_STR) +#endif + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/pulp_io.h b/sw/pulp-sdk/hal/include/hal/pulp_io.h new file mode 100644 index 0000000..bae7ab2 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/pulp_io.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_PULP_IO__ +#define __HAL_PULP_IO__ + +#include + +#define pulp_write8(add, val_) (*(volatile unsigned char *)(long)(add) = val_) +#define pulp_write16(add, val_) (*(volatile unsigned short *)(long)(add) = val_) +#define pulp_write32(add, val_) (*(volatile unsigned int *)(long)(add) = val_) +#define pulp_write(add, val_) (*(volatile unsigned int *)(long)(add) = val_) + +#if 1 + +#define pulp_read8(add) (*(volatile unsigned char *)(long)(add)) +#define pulp_read16(add) (*(volatile unsigned short *)(long)(add)) +#define pulp_read32(add) (*(volatile unsigned int *)(long)(add)) +#define pulp_read(add) (*(volatile unsigned int *)(long)(add)) + +#else + +static inline uint8_t pulp_read8(uint32_t add) +{ + __asm__ __volatile__ ("" : : : "memory"); + uint8_t result = *(volatile uint8_t *)add; + asm volatile("l.nop;"); + __asm__ __volatile__ ("" : : : "memory"); + return result; +} + +static inline uint16_t pulp_read16(uint32_t add) +{ + __asm__ __volatile__ ("" : : : "memory"); + uint16_t result = *(volatile uint16_t *)add; + asm volatile("nop;"); + __asm__ __volatile__ ("" : : : "memory"); + return result; +} + +static inline uint32_t pulp_read32(uint32_t add) +{ + __asm__ __volatile__ ("" : : : "memory"); + uint32_t result = *(volatile uint32_t *)add; + asm volatile("nop;"); + __asm__ __volatile__ ("" : : : "memory"); + return result; +} + +static inline uint32_t pulp_read(uint32_t add) +{ + __asm__ __volatile__ ("" : : : "memory"); + uint32_t result = *(volatile uint32_t *)add; + asm volatile("nop;"); + __asm__ __volatile__ ("" : : : "memory"); + return result; +} + +#endif + +#if defined(__riscv__) && !defined(RV_ISA_RV32) && !defined(__LLVM__) +#define IP_WRITE_VOL(base, offset, value) __builtin_pulp_write_base_off_v((value), (base), (offset)) +#define IP_WRITE(base, offset, value) __builtin_pulp_OffsetedWrite((value), (int *)(base), (offset)) +#define IP_READ(base, offset) __builtin_pulp_OffsetedRead((int *)(base), (offset)) +#else +#define IP_WRITE_VOL(base, offset, value) pulp_write32((base) + (offset), (value)) +#define IP_WRITE(base, offset, value) pulp_write32((base) + (offset), (value)) +#define IP_READ(base, offset) pulp_read32((base) + (offset)) +#endif + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/pwm/pwm_v1.h b/sw/pulp-sdk/hal/include/hal/pwm/pwm_v1.h new file mode 100644 index 0000000..aae6c6a --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/pwm/pwm_v1.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna and + * GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_PWM_PWM_V1_H__ +#define __HAL_PWM_PWM_V1_H__ + +#include +#include + +/* Timer Base: PWM_BASE_ADDR + Timer*PWM_TIMER_TO_TIMER_OFFSET + Config: + PWM_TIMER_CONFIG_OFFSET + Threhsold: + PWM_TIMER_THRESHOLD_OFFSET + Channel Thresh + PWM_TIMER_TH_CHANNEL_OFFSET + Channel*PWM_CHANNEL_TO_CHANNEL_OFFSET + Channel LUT + PWM_TIMER_LUT_CHANNEL_OFFSET + Channel*PWM_CHANNEL_TO_CHANNEL_OFFSET +*/ + +typedef enum { + PWM_TIMER0=0, + PWM_TIMER1=1, + PWM_TIMER2=2, + PWM_TIMER3=3, +} numPwmTimerT; + +typedef enum { + PWM_TIMER_TH_CHANNEL0=0, + PWM_TIMER_TH_CHANNEL1=1, + PWM_TIMER_TH_CHANNEL2=2, + PWM_TIMER_TH_CHANNEL3=3, +} PwmTimerThChannelT; + +typedef enum { + PWM_TIMER_LUT_CHANNEL0=0, + PWM_TIMER_LUT_CHANNEL1=1, + PWM_TIMER_LUT_CHANNEL2=2, + PWM_TIMER_LUT_CHANNEL3=3, +} PwmTimerLutChannelT; + +enum{ + pwm_timer_event0 = 0, + pwm_timer_event1 , + pwm_timer_event2 , + pwm_timer_event3 , +}; + +typedef enum { + PWM_TIMER_CMD_START = 0x01, /* Start counting */ + PWM_TIMER_CMD_STOP = 0x02, /* Stop counting */ + PWM_TIMER_CMD_UPD = 0x04, /* Update timer params */ + PWM_TIMER_CMD_RST = 0x08, /* Reset counter value */ +} PwmCounterCmdT; + +typedef struct { + unsigned int SelectInputSource:8; /* Select counting condition */ + unsigned int InputEnableIn:3; /* Define enable rules: + 000, always count (use clock) + 001 count when external input is 0 + 010 count when external input is 1 + 011 count on rising edge of external + 100 count on falling edge of external + 101 count on falling and on rising edge of external + */ + unsigned int FllOrRTC:1; /* Clock input of counter is Fll or RTC */ + unsigned int IncThenDec:1; /* When counter reaches threshold count down if IncThenDec else return to 0 and ocunt up again */ + unsigned int Pad:3; + unsigned int PreScaler:8; /* */ + unsigned int Pad2:8; +} PwmCounterConfigT; + +typedef struct { + unsigned int chThreshold:16; /* Threshold value for the channel of a counter */ + unsigned int chAction:3; + /* When counter reaches threshold: + 000: Set + 001: Toggle then next is Clear + 010: Set then Clear + 011: Toggle + 100: Clear + 101: Toggle then next is Set + 110: Clear then Set + */ + unsigned int Pad:13; +} PwmChannelThConfigT; + +typedef struct { + unsigned int Lut:16; + unsigned int Flt:2; + unsigned int Pad:14; +} PwmChannelLutConfigT; + +typedef struct{ + unsigned int evt0_sel:4; + unsigned int evt1_sel:4; + unsigned int evt2_sel:4; + unsigned int evt3_sel:4; + unsigned int evt_en:4; + unsigned int pad:12; +} PwmTimerEvtT; + +// TODO: maybe we do not need the functions: _get below, +// because all the get could be replaced by reading the value of struct objects. +// Except: maybe we need to reset the values in structs after a "RESET"!! +// And for debugging usages. +static inline void gap_pwm_timer_cmd(numPwmTimerT timer, PwmCounterCmdT CMD){ + pulp_write32( PWM_TIMER_CMD_ADDR(timer), CMD); +} + +static inline void gap_pwm_timer_config(numPwmTimerT timer, unsigned int conf){ + pulp_write32( PWM_TIMER_CONFIG_ADDR(timer), conf); +} + +static inline unsigned int gap_pwm_timer_config_get(numPwmTimerT timer){ + return pulp_read32( PWM_TIMER_CONFIG_ADDR(timer)); +} + +static inline void gap_pwm_timer_threshold_set(numPwmTimerT timer, unsigned int value){ + pulp_write32(PWM_TIMER_THRESHOLD_ADDR(timer), value); +} + +static inline unsigned int gap_pwm_timer_threshold_get(numPwmTimerT timer){ + return pulp_read32(PWM_TIMER_THRESHOLD_ADDR(timer)); +} + +static inline void gap_pwm_timer_th_channel_set(numPwmTimerT timer, PwmTimerThChannelT channel, unsigned int value){ + pulp_write32(PWM_TIMER_TH_CHANNEL_ADDR(timer, channel), value); +} + +static inline unsigned int gap_pwm_timer_th_channel_get(numPwmTimerT timer, PwmTimerThChannelT channel){ + return pulp_read32(PWM_TIMER_TH_CHANNEL_ADDR(timer, channel)); +} + +static inline void gap_pwm_timer_lut_channel_set(numPwmTimerT timer, PwmTimerThChannelT channel, unsigned int value){ + pulp_write32(PWM_TIMER_LUT_CHANNEL_ADDR(timer, channel), value); +} + +static inline unsigned int gap_pwm_timer_lut_channel_get(numPwmTimerT timer, PwmTimerThChannelT channel){ + return pulp_read32(PWM_TIMER_LUT_CHANNEL_ADDR(timer, channel)); +} + +static inline unsigned int gap_pwm_timer_read_counter(numPwmTimerT nTimer) { + return pulp_read32( PWM_TIMER_COUNTER_ADDR(nTimer) ); +} + +static inline void gap_pwm_timer_evt_reg_cfg (unsigned int CMD){ + pulp_write32(REG_EVENT_CFG, CMD); +} + +static inline unsigned int gap_pwm_timer_evt_reg_read() { + return pulp_read32( REG_EVENT_CFG ); +} + +static inline unsigned int gap_pwm_timer_status(){ + return pulp_read32(REG_PWM_TIMER_EN); +} + +static inline void gap_pwm_timer_en_reg(unsigned int timer_en_val){ + pulp_write32(REG_PWM_TIMER_EN, timer_en_val); +} +/*************************************************************************/ + +typedef union{ + PwmCounterConfigT timerConf; + unsigned int timerTh; /* Threshold value for the counter */ + PwmChannelThConfigT ch_ThConfig; + PwmChannelLutConfigT ch_LutConfig; + PwmTimerEvtT timerEvt; + unsigned int Raw; +} gap_pwm_timer_t; + + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/rab/rab_v1.h b/sw/pulp-sdk/hal/include/hal/rab/rab_v1.h new file mode 100644 index 0000000..916e722 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/rab/rab_v1.h @@ -0,0 +1,381 @@ +/* + * Copyright (C) 2017 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_RAB_V1_H__ +#define __HAL_RAB_V1_H__ + +#include "archi-host/phys_addr.h" +#include "archi-host/virt_addr.h" + +#include "archi/rab/rab_v1.h" + +#include "hal/pulp.h" // ARCHI_RAB_CFG_ADDR +#include "hal/utils.h" // BIT_* functions + +#include // ENOENT +#include // for uint8_t + +//#ifndef LOG_LVL_RAB_CFG +// #define LOG_LVL_RAB_CFG LOG_ERR +//#endif + +// This struct represents the L1 TLB entry information for PULP. +typedef struct { + virt_addr_t va_start, va_end; + phys_addr_t offset; + uint8_t flags; +} rab_cfg_val_t; + +typedef uint8_t rab_l2_set_t; + +// This struct represents the L2 TLB entry information for PULP. +typedef struct { + virt_pfn_t virt_pfn; + phys_pfn_t phys_pfn; + uint8_t flags; + rab_l2_set_t set; +} rab_cfg_l2_val_t; + +// This struct represents a miss in the RAB Miss Hardware FIFO. +typedef struct rab_miss_t { + virt_addr_t virt_addr; + int core_id; + int cluster_id; + int intra_cluster_id; + uint8_t is_prefetch; +} rab_miss_t; + +/** @name Main RAB TLB entry configuration functions + * + * @{ + */ + +/** Configure a RAB L1 TLB slice. + + \param begin First virtual address to be mapped. + \param end Address of the next byte after the last virtual address to be mapped. + \param phys_addr Pointer to the physical address to which the RAB slice shall map. + \param rab_slice Pointer to the RAB slice to be configured. + \param rdonly Defines memory accesses through the new slice as read-only (if not 0) or + as read-write (if 0). + \param cache_coherent Defines memory accesses through the new slice as coherent with the + caches of the host (if not 0) or as not necessarily coherent (if 0). + + \return 0 if the RAB slice has been configured successfully; negative value with an errno on + errors. +*/ +static inline int config_rab_slice(const virt_addr_t begin, const virt_addr_t end, + const phys_addr_t* const phys_addr, rab_cfg_t* const rab_slice, + const unsigned char rdonly, const unsigned char cache_coherent); + +/** Configure a RAB L2 TLB entry. + + \param virt_pfn Virtual page frame number to be mapped. + \param phys_addr Physical page frame number to which the L2 TLB entry shall map. + \param l2_set Index of the set in which the L2 TLB entry shall be configured. + \param l2_set_off Offset of the L2 TLB entry within the set to be configured. + \param rdonly Defines memory accesses through the new slice as read-only (if not 0) or + as read-write (if 0). + \param cache_coherent Defines memory accesses through the new slice as coherent with the + caches of the host (if not 0) or as not necessarily coherent (if 0). + + \return 0 if the RAB L2 TLB entry has been configured successfully; negative value with an errno + on errors. +*/ +static inline int config_rab_l2_entry(const virt_pfn_t virt_pfn, + const phys_pfn_t phys_pfn, const rab_l2_set_t set, const unsigned char entry, + const unsigned char rdonly, const unsigned char cache_coherent); + +//!@} + +/** @name RAB TLB entry inspection functions + * + * @{ + */ + +/** Print a RAB L1 TLB configuration value to standard output. + + \param cfg_val Pointer to the struct on PULP containing the configuration. + + \return 0 if printing was successful; negative value with an errno on errors. +*/ +int print_rab_cfg_val(const rab_cfg_val_t* const cfg_val); + +/** Print the current RAB L1 TLB configuration. + + \param begin Pointer to the first RAB slice to be printed. + \param end Pointer to the RAB slice after the last to be printed. + \param only_valid If 0, all RAB slices are printed; otherwise, only valid slices are printed. + + \return 0 if the RAB configuration was printed successfully; negative value with an errno on + errors. +*/ +int print_rab_cfg(const rab_cfg_t* const begin, const rab_cfg_t* const end, + const unsigned only_valid); + +/** Print a RAB L2 TLB configuration value to standard output. + + \param varam_ptr Pointer to the virtual address RAM of the L2 TLB entry to be configured. + \param param_ptr Pointer to the physical address RAM of the L2 TLB entry to be configured. + \param cfg_val Pointer to the struct on PULP containing the configuration. + + \return 0 if printing was successful; negative value with an errno on errors. +*/ +int print_rab_cfg_l2_val(const rab_cfg_l2_varam_t* const varam_ptr, + const rab_cfg_l2_param_t* const param_ptr, const rab_cfg_l2_val_t* const cfg_val, + const unsigned char entry); + +//!@} + +/** @name Low-level RAB L1 and L2 TLB entry inspection and manipulation functions + * + * @{ + */ + +/** Read a RAB L1 TLB configuration value to PULP. + + \param dst Pointer to the PULP struct in which the configuration shall be stored. + \param src Pointer to the RAB configuration entry. + + \return 0 if the RAB configuration value has been read successfully; negative value with an + errno on errors. +*/ +static inline int read_rab_cfg_val(rab_cfg_val_t* const dst, const rab_cfg_t* const src); + +/** Write a RAB L1 TLB configuration value from PULP. + + \param dst Pointer to the RAB configuration entry. + \param src Pointer to the PULP struct from which the configuration shall be read. + + \return 0 if the RAB configuration value has been written successfully; negative value with an + errno on errors. +*/ +static inline int write_rab_cfg_val(rab_cfg_t* const dst, const rab_cfg_val_t* const src); + +/** Disable a RAB L1 TLB slice. + + \param rab_slice Pointer to the RAB slice to be disabled. + + \return 0 if the RAB slice has been disabled successfully; negative value with an errno on + errors. +*/ +static inline int disable_rab_slice(rab_cfg_t* const rab_slice); + +/** Determine if a RAB L1 TLB slice is enabled. + + \param cfg_val Pointer to the PULP representation of the RAB slice to be examined. + + \return 0 if the RAB slice is disabled; 1 if the RAB slice is enabled; negative value with an + errno on errors. +*/ +static inline int rab_slice_is_enabled(const rab_cfg_val_t* const cfg_val); + +/** Determine if a virtual address is in the address range of a RAB L1 TLB slice. + + \param cfg_val Pointer to the PULP representation of the RAB slice to be examined. + \param virt_addr Virtual address to check for inclusion. + + \return 0 if the virtual address is not in the address range of the RAB slice; 1 if it is; + negative value with an errno on errors. +*/ +static inline int rab_slice_contains_virt_addr(const rab_cfg_val_t* const cfg_val, + const virt_addr_t virt_addr); + +/** Determine the L2 TLB set index of a virtual page frame number. + + \param virt_pfn Virtual page frame number to determine the set index of. + + \return The L2 set index. +*/ +static inline rab_l2_set_t page_set(const virt_pfn_t virt_pfn); + +/** Write a RAB L2 TLB entry from PULP. + + \param varam_ptr Pointer to the virtual address RAM of the L2 TLB entry to be configured. + \param param_ptr Pointer to the physical address RAM of the L2 TLB entry to be configured. + \param src Pointer to the PULP struct from which the configuration shall be read. + + \return 0 if the RAB configuration value has been written successfully; negative value with an + errno on errors. +*/ +static inline int write_rab_cfg_l2_val(rab_cfg_l2_varam_t* const varam_ptr, + rab_cfg_l2_param_t* const param_ptr, rab_cfg_l2_val_t * const src); + +//!@} + +/** @name RAB Miss Hardware FIFO interface functions + * + * @{ + */ + +/** Get miss from RAB Miss FIFO. + + \param rab_miss Pointer through which the RAB miss shall be returned. + + \return 0 on success; negative value with an errno on errors. -ENOENT is returned in case the + FIFO is empty; in this case, `rab_miss` is not changed. +*/ +static inline int get_rab_miss(rab_miss_t* const rab_miss); + +//!@} + +/// @cond IMPLEM + +int read_rab_cfg_val(rab_cfg_val_t* const dst, const rab_cfg_t* const src) +{ + dst->va_start = src->word[0]; + dst->va_end = src->word[2]; + copy_phys_addr((phys_addr_t*)&(dst->offset), (phys_addr_t*)&(src->word[4])); + dst->flags = (uint8_t)(src->word[6] & 0xFF); + + return 0; +} + +int write_rab_cfg_val(rab_cfg_t* const dst, const rab_cfg_val_t* const src) +{ + // Disable slice before writing the new configuration. + dst->word[6] = 0; + + dst->word[0] = src->va_start; + dst->word[2] = src->va_end; + copy_phys_addr((phys_addr_t*)&(dst->word[4]), (phys_addr_t*)&(src->offset)); + dst->word[6] = (0x000000FF) & (uint32_t)(src->flags); + + return 0; +} + +int config_rab_slice(const virt_addr_t begin, const virt_addr_t end, + const phys_addr_t* const phys_addr, rab_cfg_t* const rab_slice, + const unsigned char rdonly, const unsigned char cache_coherent) +{ + int ret = 0; + + rab_cfg_val_t cfg = { + .va_start = begin, + .va_end = end-1, + .flags = RAB_CFG_FLAG_EN + | RAB_CFG_FLAG_RDEN + | (rdonly ? 0 : RAB_CFG_FLAG_WREN) + | (cache_coherent ? RAB_CFG_FLAG_COHERENT : 0) + }; + ret = copy_phys_addr(&(cfg.offset), phys_addr); + if (ret < 0) + return ret; + + ret = write_rab_cfg_val(rab_slice, &cfg); + if (ret < 0) + return ret; + + //#if LOG_LVL_RAB_CFG >= LOG_DEBUG + // printf("[DD] Configured RAB slice:\n"); + // print_rab_cfg_val(&cfg); + // printf("\n"); + //#endif + + return 0; +} + +int disable_rab_slice(rab_cfg_t* const rab_slice) +{ + rab_slice->word[6] = 0; + return 0; +} + +int rab_slice_is_enabled(const rab_cfg_val_t* const cfg_val) +{ + return (cfg_val->flags & RAB_CFG_FLAG_EN) == RAB_CFG_FLAG_EN; +} + +int rab_slice_contains_virt_addr(const rab_cfg_val_t* const cfg_val, + const virt_addr_t virt_addr) +{ + return (virt_addr >= cfg_val->va_start) && (virt_addr <= cfg_val->va_end); +} + +rab_l2_set_t page_set(const virt_pfn_t virt_pfn) +{ + return (rab_l2_set_t)(virt_pfn & RAB_CFG_L2_SET_PFN_MASK); +} + +int write_rab_cfg_l2_val(rab_cfg_l2_varam_t* const varam_ptr, + rab_cfg_l2_param_t* const param_ptr, rab_cfg_l2_val_t * const src) +{ + // Disable slice before writing the new configuration. + *varam_ptr = 0; + + *param_ptr = src->phys_pfn; + *varam_ptr = (src->virt_pfn << 4) | (uint32_t)(src->flags); + + return 0; +} + +int config_rab_l2_entry(const virt_pfn_t virt_pfn, + const phys_pfn_t phys_pfn, const rab_l2_set_t set, const unsigned char entry, + const unsigned char rdonly, const unsigned char cache_coherent) +{ + int ret = 0; + + rab_cfg_l2_val_t cfg = { + .virt_pfn = virt_pfn, + .phys_pfn = phys_pfn, + .flags = RAB_CFG_FLAG_EN + | RAB_CFG_FLAG_RDEN + | (rdonly ? 0 : RAB_CFG_FLAG_WREN) + | (cache_coherent ? RAB_CFG_FLAG_COHERENT : 0), + .set = set + }; + + rab_cfg_l2_varam_t* const varam_ptr = RAB_CFG_L2_VARAM_PTR(set, entry); + rab_cfg_l2_param_t* const param_ptr = RAB_CFG_L2_PARAM_PTR(set, entry); + + ret = write_rab_cfg_l2_val(varam_ptr, param_ptr, &cfg); + if (ret < 0) + return ret; + + //#if ( (LOG_LVL_RAB_CFG >= LOG_DEBUG) || (LOG_LVL_VMM >= LOG_TRACE) ) + // printf("[DD] Configured RAB L2 TLB entry:\n"); + // print_rab_cfg_l2_val(varam_ptr, param_ptr, &cfg, entry); + // printf("\n"); + //#endif + + return 0; +} + +int get_rab_miss(rab_miss_t* const rab_miss) +{ + int ret = 0; + + const uint32_t meta_fifo_val = *(volatile uint32_t*)((unsigned)ARCHI_RAB_CFG_ADDR + 8); + if (BIT_GET(meta_fifo_val, 31, 1) != 0) + return -ENOENT; // FIFO is empty. + + rab_miss->virt_addr = *(volatile virt_addr_t*)(ARCHI_RAB_CFG_ADDR); + + rab_miss->core_id = BIT_GET(meta_fifo_val, 0, AXI_ID_WIDTH_CORE); + rab_miss->intra_cluster_id = BIT_GET(meta_fifo_val, AXI_ID_WIDTH_CORE, AXI_ID_WIDTH_CLUSTER); + rab_miss->cluster_id + = BIT_GET(meta_fifo_val, AXI_ID_WIDTH_CLUSTER + AXI_ID_WIDTH_CORE, AXI_ID_WIDTH_SOC); + + const uint32_t axi_user + = BIT_GET(meta_fifo_val, AXI_ID_WIDTH + RAB_PORT_ID_WIDTH, AXI_USER_WIDTH); + rab_miss->is_prefetch = (axi_user == BIT_MASK_LSBS(AXI_USER_WIDTH) ? 1 : 0); + + return 0; +} + +/// @endcond + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/riscv/builtins_v2.h b/sw/pulp-sdk/hal/include/hal/riscv/builtins_v2.h new file mode 100644 index 0000000..b7b4434 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/riscv/builtins_v2.h @@ -0,0 +1,324 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_RISCV_BUILTINS_V2_H__ +#define __HAL_RISCV_BUILTINS_V2_H__ +#ifdef ARCHI_CORE_HAS_PULPV2 +/* ARITHMETIC SECTION */ +typedef signed short v2s __attribute__((vector_size (4))); +typedef unsigned short v2u __attribute__((vector_size (4))); + +typedef signed char v4s __attribute__((vector_size (4))); +typedef unsigned char v4u __attribute__((vector_size (4))); + +#ifdef __EMUL__ +typedef void * rt_pointerT; +#else +typedef unsigned int rt_pointerT; +#endif +/* Packing of scalars into vectors */ +#define __PACK2(x, y) __builtin_pulp_pack2((signed short) (x), (signed short) (y)) +#define __PACKU2(x, y) __builtin_pulp_pack2((unsigned short) (x), (unsigned short) (y)) + +#define __PACK4(x, y, z, t) __builtin_pulp_pack4((signed char) (x), (signed char) (y), (signed char) (z), (signed char) (t)) +#define __PACKU4(x, y, z, t) __builtin_pulp_pack4((unsigned char) (x), (unsigned char) (y), (unsigned char) (z), (unsigned char) (t)) + +/* Max */ +#define __MAX(a, b) __builtin_pulp_maxsi((a), (b)) + +#define __MAX2(x, y) __builtin_pulp_max2((x), (y)) +#define __MAX4(x, y) __builtin_pulp_max4((x), (y)) + +#define __MAXU2(x, y) __builtin_pulp_maxu2((x), (y)) +#define __MAXU4(x, y) __builtin_pulp_maxu4((x), (y)) + +/* Min */ +#define __MIN2(x, y) __builtin_pulp_min2((x), (y)) +#define __MIN4(x, y) __builtin_pulp_min4((x), (y)) + +#define __MINU2(x, y) __builtin_pulp_minu2((x), (y)) +#define __MINU4(x, y) __builtin_pulp_minu4((x), (y)) + +/* Clip */ +#define __CLIP(x, precision) __builtin_pulp_clip((x), -(1<<(precision)), (1<(y)?(x):(y)) +#define __MAX2(x, y) ((v2s) {((signed short)(x)[0]>(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]>(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __MAX4(x, y) ((v4s) {((signed char)(x)[0]>(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]>(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]>(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]>(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __MAXU2(x, y) ((v2u) {((unsigned short)(x)[0]>(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]>(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __MAXU4(x, y) ((v4u) {((unsigned char)(x)[0]>(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]>(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]>(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]>(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Min */ +#define __MIN2(x, y) ((v2s) {((signed short)(x)[0]<(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]<(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __MIN4(x, y) ((v4s) {((signed char)(x)[0]<(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]<(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]<(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]<(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __MINU2(x, y) ((v2u) {((unsigned short)(x)[0]<(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]<(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __MINU4(x, y) ((v4u) {((unsigned char)(x)[0]<(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]<(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]<(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]<(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Clip */ +#define __CLIP(x, precision) ((x)<(-(1<<(precision)))?(-(1<<(precision))):(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x))) +#define __CLIP_R(x, bound) (((x)<=-((bound)+1))?(-((bound)+1)):(((x)>=(bound))?(bound):(x))) + +#define __CLIPU(x, precision) ((x)<0)?0:(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x)) +#define __CLIPU_R(x, bound) (((x)<=0)?(0):(((x)>=(bound))?(bound):(x))) + +/* Abs */ +#define __ABS2(x) ((v2u) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1]}) +#define __ABS4(x) ((v4u) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1], \ + ((x)[2]<0)?-(x)[2]:(x)[2], ((x)[3]<0)?-(x)[3]:(x)[3]}) + +/* Unary minus */ +#define __NEG2(x) ((v2s) {-(x)[0], -(x)[1]} +#define __NEG4(x) ((v4s) {-(x)[0], -(x)[1], -(x)[2], -(x)[3]} + +/* Addition */ +#define __ADD2(x, y) ((v2s) {(x)[0]+(y)[0], (x)[1]+(y)[1]} +#define __ADD4(x, y) ((v4s) {(x)[0]+(y)[0], (x)[1]+(y)[1], (x)[2]+(y)[2], (x)[3]+(y)[3]} + +/* Substraction */ +#define __SUB2(x, y) ((v2s) {(x)[0]-(y)[0], (x)[1]-(y)[1]} +#define __SUB4(x, y) ((v4s) {(x)[0]-(y)[0], (x)[1]-(y)[1], (x)[2]-(y)[2], (x)[3]-(y)[3]} + +/* Average */ +#define __AVG2(x, y) ((v2s) {((x)[0]+(y)[0])>>1, ((x)[1]+(y)[1])>>1} +#define __AVG4(x, y) ((v4s) {((x)[0]+(y)[0])>>1, ((x)[1]+(y)[1])>>1, ((x)[2]+(y)[2])>>1, ((x)[3]+(y)[3])>>1} + +/* Average unsigned */ +#define __AVGU2(x, y) ((v2u) {((unsigned short)(x)[0]+(unsigned short)(y)[0])>>1, ((unsigned short)(x)[1]+(unsigned short)(y)[1])>>1} +#define __AVGU4(x, y) ((v4u) {((unsigned char)(x)[0]+(unsigned char)(y)[0])>>1, ((unsigned char)(x)[1]+(unsigned char)(y)[1])>>1, \ + ((unsigned char)(x)[2]+(unsigned char)(y)[2])>>1, ((unsigned char)(x)[3]+(unsigned char)(y)[3])>>1} + +/* Bitwise and */ +#define __AND2(x, y) ((v2s) {(x)[0]&(y)[0], (x)[1]&(y)[1]} +#define __AND4(x, y) ((v4s) {(x)[0]&(y)[0], (x)[1]&(y)[1], (x)[2]&(y)[2], (x)[3]&(y)[3]} + +/* Bitwise or */ +#define __OR2(x, y) ((v2s) {(x)[0]|(y)[0], (x)[1]|(y)[1]} +#define __OR4(x, y) ((v4s) {(x)[0]|(y)[0], (x)[1]|(y)[1], (x)[2]|(y)[2], (x)[3]|(y)[3]} + +/* Bitwise exor */ +#define __EXOR2(x, y) ((v2s) {(x)[0]^(y)[0], (x)[1]^(y)[1]} +#define __EXOR4(x, y) ((v4s) {(x)[0]^(y)[0], (x)[1]^(y)[1], (x)[2]^(y)[2], (x)[3]^(y)[3]} + +/* Logical shift right */ +#define __SRL2(x, y) ((v2u) {((unsigned short)(x)[0]>>(unsigned short)(y)[0]), ((unsigned short)(x)[1]>>(unsigned short)(y)[1])} +#define __SRL4(x, y) ((v4u) {((unsigned char)(x)[0]>>(unsigned char)(y)[0]), ((unsigned char)(x)[1]>>(unsigned char)(y)[1]), \ + ((unsigned char)(x)[2]>>(unsigned char)(y)[2]), ((unsigned char)(x)[3]>>(unsigned char)(y)[3])} + +/* Arithmetic shift right */ +#define __SRA2(x, y) ((v2s) {((signed short)(x)[0]>>(signed short)(y)[0]), ((signed short)(x)[1]>>(signed short)(y)[1])} +#define __SRA4(x, y) ((v4s) {((signed char)(x)[0]>>(signed char)(y)[0]), ((signed char)(x)[1]>>(signed char)(y)[1]), \ + ((signed char)(x)[2]>>(signed char)(y)[2]), ((signed char)(x)[3]>>(signed char)(y)[3])} + +/* Logical shift left */ +#define __SLL2(x, y) ((v2s) {(x)[0]<<(y)[0], (x)[1]<<(y)[1]} +#define __SLL4(x, y) ((v4s) {(x)[0]<<(y)[0], (x)[1]<<(y)[1], (x)[2]<<(y)[2], (x)[3]<<(y)[3]} + +/* Mac */ +#define __MAC(Acc, x, y) ((Acc) + ((x) * (y))) +#define __MSU(Acc, x, y) ((Acc) - ((x) * (y))) + +#define __MACS(Acc, x, y) ((Acc) + ((short int) (x) * (short int) (y))) +#define __MACHHS(Acc, x, y) ((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) +#define __MACU(Acc, x, y) ((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) +#define __MACHHU(Acc, x, y) ((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + +#define __MACSN(Acc, x, y, n) (((Acc) + ((short int) (x) * (short int) (y)))>>(n)) +#define __MACUN(Acc, x, y, n) (((Acc) + ((unsigned short int) (x) * (unsigned short int) (y)))>>(n)) +#define __MACSRN(Acc, x, y, n) ((((Acc) + ((short int) (x) * (short int) (y))) + (1<<((n)-1))) >> (n)) +#define __MACURN(Acc, x, y, n) ((((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) + (1<<((n)-1))) >> (n)) + +#define __MACHHSN(Acc, x, y, n) (((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) >> (n)) +#define __MACHHUN(Acc, x, y, n) (((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) >> (n)) +#define __MACHHSRN(Acc, x, y, n) ((((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) + (1<<((n)-1))) >> (n)) +#define __MACHHURN(Acc, x, y, n) ((((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + (n))) + +/* Multiplications */ +#define __MULS(x, y) (((short int) (x) * (short int) (y))) +#define __MULU(x, y) (((unsigned short int) (x) * (unsigned short int) (y))) +#define __MULHHS(x, y) (((short int) ((x)>>16) * (short int) ((y)>>16))) +#define __MULHHU(x, y) (((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + +#define __MULSN(x, y, n) (((short int) (x) * (short int) (y))>>(n)) +#define __MULSRN(x, y, n) ((((short int) (x) * (short int) (y)) + (1<<((n)-1)))>>(n)) +#define __MULUN(x, y, n) (((unsigned short int) (x) * (unsigned short int) (y))>>(n)) +#define __MULURN(x, y, n) ((((unsigned short int) (x) * (unsigned short int) (y)) + (1<<((n)-1)))>>(n)) + +#define __MULHHSN(x, y, n) ((((short int) ((x)>>16) * (short int) ((y)>>16)))>>(n)) +#define __MULHHSRN(x, y, n) (((((short int) ((x)>>16) * (short int) ((y)>>16)))+(1<<((n)-1)))>>(n)) +#define __MULHHUN(x, y, n) ((((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16)))>>(n)) +#define __MULHHURN(x, y, n) (((((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16)))+(1<<((n)-1)))>>(n)) + +/* Vectorial product and sum of products */ +#define __DOTP2(x, y) ( (short)(x)[0]*(short)(y)[0] + (short)(x)[1]*(short)(y)[1]) +#define __DOTPU2(x, y) ( (unsigned short)(x)[0]*(unsigned short)(y)[0] + (unsigned short)(x)[1]*(unsigned short)(y)[1]) +#define __DOTPUS2(x, y) ( (unsigned short)(x)[0]*(short)(y)[0] + (unsigned short)(x)[1]*(short)(y)[1]) + +#define __DOTPSC2(x, y) ( (short)(x)[0]*(short)(y) + (short)(x)[1]*(short)(y)) +#define __DOTPUSC2(x, y) ( (unsigned short)(x)[0]*(unsigned short)(y) + (unsigned short)(x)[1]*(unsigned short)(y)) +#define __DOTPUSSC2(x, y) ( (unsigned short)(x)[0]*(short)(y) + (unsigned short)(x)[1]*(short)(y)) + +#define __SUMDOTP2(x, y, z) ((z)+(short)(x)[0]*(short)(y)[0] + (short)(x)[1]*(short)(y)[1]) +#define __SUMDOTPU2(x, y, z) ((z)+(unsigned short)(x)[0]*(unsigned short)(y)[0] + (unsigned short)(x)[1]*(unsigned short)(y)[1]) +#define __SUMDOTPUS2(x, y, z) ((z)+(unsigned short)(x)[0]*(short)(y)[0] + (unsigned short)(x)[1]*(short)(y)[1]) + +#define __SUMDOTPSC2(x, y, z) ((z)+(short)(x)[0]*(short)(y) + (short)(x)[1]*(short)(y)) +#define __SUMDOTPUSC2(x, y, z) ((z)+(unsigned short)(x)[0]*(unsigned short)(y) + (unsigned short)(x)[1]*(unsigned short)(y)) +#define __SUMDOTPUSSC2(x, y, z) ((z)+(unsigned short)(x)[0]*(short)(y) + (unsigned short)(x)[1]*(short)(y)) + +#define __DOTP4(x, y) ( (char)(x)[0]*(char)(y)[0] + (char)(x)[1]*(char)(y)[1] + (char)(x)[2]*(char)(y)[2] + (char)(x)[3]*(char)(y)[3]) +#define __DOTPU4(x, y) ( (unsigned char)(x)[0]*(unsigned char)(y)[0] + (unsigned char)(x)[1]*(unsigned char)(y)[1] + \ + (unsigned char)(x)[2]*(unsigned char)(y)[2] + (unsigned char)(x)[3]*(unsigned char)(y)[3]) +#define __DOTPUS4(x, y) ( (unsigned char)(x)[0]*(char)(y)[0] + (unsigned char)(x)[1]*(char)(y)[1] + \ + (unsigned char)(x)[2]*(char)(y)[2] + (unsigned char)(x)[3]*(char)(y)[3]) + +#define __DOTPSC4(x, y) ( (char)(x)[0]*(char)(y) + (char)(x)[1]*(char)(y) + (char)(x)[2]*(char)(y) + (char)(x)[3]*(char)(y)) +#define __DOTPUSC4(x, y) ( (unsigned char)(x)[0]*(unsigned char)(y) + (unsigned char)(x)[1]*(unsigned char)(y) + \ + (unsigned char)(x)[2]*(unsigned char)(y) + (unsigned char)(x)[3]*(unsigned char)(y)) +#define __DOTPUSSC4(x, y) ( (unsigned char)(x)[0]*(char)(y) + (unsigned char)(x)[1]*(char)(y) + \ + (unsigned char)(x)[2]*(char)(y) + (unsigned char)(x)[3]*(char)(y)) + +#define __SUMDOTP4(x, y, z) ((z)+(char)(x)[0]*(char)(y)[0] + (char)(x)[1]*(char)(y)[1] + (char)(x)[2]*(char)(y)[2] + (char)(x)[3]*(char)(y)[3]) +#define __SUMDOTPU4(x, y, z) ((z)+(unsigned char)(x)[0]*(unsigned char)(y)[0] + (unsigned char)(x)[1]*(unsigned char)(y)[1] + \ + (unsigned char)(x)[2]*(unsigned char)(y)[2] + (unsigned char)(x)[3]*(unsigned char)(y)[3]) +#define __SUMDOTPUS4(x, y, z) ((z)+(unsigned char)(x)[0]*(char)(y)[0] + (unsigned char)(x)[1]*(char)(y)[1] + \ + (unsigned char)(x)[2]*(char)(y)[2] + (unsigned char)(x)[3]*(char)(y)[3]) + +#define __SUMDOTPSC4(x, y, z) ((z)+(char)(x)[0]*(char)(y) + (char)(x)[1]*(char)(y) + (char)(x)[2]*(char)(y) + (char)(x)[3]*(char)(y)) +#define __SUMDOTPUSC4(x, y, z) ((z)+(unsigned char)(x)[0]*(unsigned char)(y) + (unsigned char)(x)[1]*(unsigned char)(y) + \ + (unsigned char)(x)[2]*(unsigned char)(y) + (unsigned char)(x)[3]*(unsigned char)(y)) +#define __SUMDOTPUSSC4(x, y, z) ((z)+(unsigned char)(x)[0]*(char)(y) + (unsigned char)(x)[1]*(char)(y) + \ + (unsigned char)(x)[2]*(char)(y) + (unsigned char)(x)[3]*(char)(y)) + +#ifdef ARCHI_CORE_HAS_CPLX + +/* Complex Multiplication, Q15x15 into Q15, with optional post scaling by 1 or 2 */ +#define __CPLXMULS(x, y) ((v2s) {(signed short) ((((long long) (x)[0]*(long long) (y)[0]) - ((long long) (x)[1]*(long long) (y)[1]))>>15), \ + (signed short) ((((long long) (x)[0]*(long long) (y)[1]) + ((long long) (x)[1]*(long long) (y)[0]))>>15)}) +#define __CPLXMULSDIV2(x, y) (__CPLXMULS(x, y)>>(v2s){1,1}) +#define __CPLXMULSDIV4(x, y) (__CPLXMULS(x, y)>>(v2s){2,2}) + +/* Complex conjugate */ +#define __CPLXCONJ(x) ((v2s) {(x)[0], -(x)[1]}) + +/* Complex substration, result rotated by -pi/2 */ +#define __SUB2ROTMJ(x, y) ((v2s) {(x)[1]-(y)[1], (y)[0]-(x)[0]}) + +/* Complex addition with post scaling by 1 or 2 */ +#define __ADD2DIV2(x, y) (((x)+(y))>>(v2s) {1, 1}) +#define __ADD2DIV4(x, y) (((x)+(y))>>(v2s) {2, 2}) + +#define __ADD4DIV2(x, y) (((x)+(y))>>(v4s) {1, 1, 1, 1}) +#define __ADD4DIV4(x, y) (((x)+(y))>>(v4s) {2, 2, 2, 2}) + +/* Complex substraction with post scaling by 1 or 2 */ +#define __SUB2DIV2(x, y) (((x)-(y))>>(v2s) {1, 1}) +#define __SUB2DIV4(x, y) (((x)-(y))>>(v2s) {2, 2}) + +#define __SUB4DIV2(x, y) (((x)-(y))>>(v4s) {1, 1, 1, 1}) +#define __SUB4DIV4(x, y) (((x)-(y))>>(v4s) {2, 2, 2, 2}) + +/* Complex subtraction with post scaling by 1 or 2 */ +#define __SUB2DIV2(x, y) (((x)-(y))>>(v2s) {1, 1}) +#define __SUB2DIV4(x, y) (((x)-(y))>>(v2s) {2, 2}) + +/* Viterbi Max and Viterbi Select, pair of Q15 */ +#define __VITMAX(x, y) (_VitT1_Flag=((x)[1]<=(y)[1])?1:0, _VitT0_Flag=((x)[0]<=(y)[0])?1:0,\ + (v2s) {((x)[0]>(y)[0])?(x)[0]:(y)[0], ((x)[1]>(y)[1])?(x)[1]:(y)[1]}) +#define __VITSEL(x, y) (v2s) {(_VitT0_Flag?(y)[0]:(x)[0])<<1|_VitT0_Flag, (_VitT1_Flag?(y)[1]:(x)[1])<<1|_VitT1_Flag} + +#endif + +/* Position of the most significant bit of x */ +#define __FL1(x) (31 - __builtin_clz((x))) + +/* Number of sign bits */ +#define __CLB(x) (__builtin_clrsb((x))) + +/* Bit set */ +#define __BITSET(x, size, off) ((x) | (((1<<(size))-1)<<(off))) +#define __BITSET_R(x, size, off) ((x) | (((1<<(size))-1)<<(off))) +#define __BITSET_R_SAFE(x, size, off) ((x) | (((1<<((size)&0x1F))-1)<<((off)&0x1F))) + +/* Bit clr */ +#define __BITCLR(x, size, off) ((x) & ~(((1<<(size))-1)<<(off))) +#define __BITCLR_R(x, size, off) ((x) & ~(((1<<(size))-1)<<(off))) +#define __BITCLR_R_SAFE(x, size, off) ((x) & ~(((1<<((size)&0x1F))-1)<<((off)&0x1F))) + +/* Bit Extraction */ +#define __BITEXTRACT(x, size, off) (((((x)>>(off))&((unsigned int)(1<<(size))-1))<<(32-(size)))>>(32-(size))) +#define __BITEXTRACTU(x, size, off) (((x)>>(off))&((unsigned int)(1<<(size))-1)) + +#define __BITEXTRACT_R(x, size, off) (((((x)>>(off))&((unsigned int)(1<<(size))-1))<<(32-(size)))>>(32-(size))) +#define __BITEXTRACTU_R(x, size, off) (((x)>>(off))&((unsigned int)(1<<(size))-1)) + +#define __BITEXTRACT_R_SAFE(x, size, off) (((((x)>>((off)&0x1F))&((unsigned int)(1<<((((size)>32)?32:(size))))-1))<<(32-((((size)>32)?32:(size)))))>>(32-((((size)>32)?32:(size))))) +#define __BITEXTRACTU_R_SAFE(x, size, off) (((x)>>((off)&0x1F))&((unsigned int)(1<<((((size)>32)?32:(size))))-1)) + +/* Bit insertion */ +#define __BITINSERT(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) +#define __BITINSERT_R(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) +#define __BITINSERT_R_SAFE(dst, src, size, off) (((dst) & ~(((1<<(((size)>32)?32:(size)))-1)<<((off)&0x1F))) | (((src) & ((1<<(((size)>32)?32:(size)))-1))<<((off)&0x1F))) + +/* 1 bit rotation to the right, 32 bits input */ +#define __ROTR(x) ((((x)>>1)&0x7FFFFFFF) | ((x)<<31)) + +/* Add with normalization */ +#define __ADDNORMU(x, y, scale) ((unsigned int)((x) + (y))>>(scale)) +#define __ADDNORMU_REG(x, y, scale) ((unsigned int)((x) + (y))>>(scale)) +#define __ADDNORM(x, y, scale) ((int)((x) + (y))>>(scale)) +#define __ADDNORM_REG(x, y, scale) ((int)((x) + (y))>>(scale)) + +/* Add with normalization and rounding */ +#define __ADDROUNDNORMU(x, y, scale) ((unsigned int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __ADDROUNDNORMU_REG(x, y, scale) ((unsigned int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __ADDROUNDNORM(x, y, scale) ((int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __ADDROUNDNORM_REG(x, y, scale) ((int)((x) + (y) + (1<<((scale)-1)))>>(scale)) + +/* Sub with normalization */ +#define __SUBNORMU(x, y, scale) ((unsigned int)((x) - (y))>>(scale)) +#define __SUBNORMU_REG(x, y, scale) ((unsigned int)((x) - (y))>>(scale)) +#define __SUBNORM(x, y, scale) ((int)((x) - (y))>>(scale)) +#define __SUBNORM_REG(x, y, scale) ((int)((x) - (y))>>(scale)) + +/* Sub with normalization and rounding */ +#define __SUBROUNDNORMU(x, y, scale) ((unsigned int)((x) - (y) + (1<<((scale)-1)))>>(scale)) +#define __SUBROUNDNORMU_REG(x, y, scale) ((unsigned int)((x) - (y) + (1<<((scale)-1)))>>(scale)) +#define __SUBROUNDNORM(x, y, scale) ((int)((x) - (y) + (1<<((scale)-1)))>>(scale)) +#define __SUBROUNDNORM_REG(x, y, scale) ((int)((x) - (y) + (1<<((scale)-1)))>>(scale)) + +/* Normalization and rounding */ +#define __ROUNDNORMU(x, scale) ((unsigned int)((x) + (1<<((scale)-1)))>>(scale)) +#define __ROUNDNORMU_REG(x, scale) ((unsigned int)((x) + (1<<((scale)-1)))>>(scale)) +#define __ROUNDNORM(x, scale) ((int)((x) + (1<<((scale)-1)))>>(scale)) +#define __ROUNDNORM_REG(x, scale) ((int)((x) + (1<<((scale)-1)))>>(scale)) +#define __COREID() 0 +#define __CLUSTERID() 0 +#define __NCORE() 1 + +#define __SPRWRITE(x, y) +#define __SPRREAD(x) ((int) 0) +#define __SPRREAD_VOL(x) ((int) 0) + +#define __READ_BASE_OFF(base, off) ((int) 0) +#define __WRITE_BASE_OFF(base, off, val) + +#define __READ_BASE_OFF_VOL(base, off) ((int) 0) +#define __READ_BASE_OFF_HALF_VOL(base, off) ((int) 0) +#define __READ_BASE_OFF_BYTE_VOL(base, off) ((int) 0) + +#define __WRITE_BASE_OFF_VOL(x, base, off) +#define __WRITE_BASE_OFF_HALF_VOL(x, base, off) +#define __WRITE_BASE_OFF_BYTE_VOL(x, base, off) +/* Utilities, Target independant */ +#define FIX2FP(Val, Precision) ((float) (Val) / (float) (1<<(Precision))) +#define FP2FIXR(Val, Precision) ((int)((Val)*((1 << (Precision))-1) + 0.5)) +#define FP2FIX(Val, Precision) ((int)((Val)*((1 << (Precision))-1))) +#endif +#endif diff --git a/sw/pulp-sdk/hal/include/hal/riscv/riscv_v3.h b/sw/pulp-sdk/hal/include/hal/riscv/riscv_v3.h new file mode 100644 index 0000000..b87ee1a --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/riscv/riscv_v3.h @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_RISCV_RISCV_V3_H__ +#define __HAL_RISCV_RISCV_V3_H__ + +#include "archi/pulp.h" +#include "hal/riscv/builtins_v2_emu.h" + +#define CSR_PCMR_ACTIVE 0x1 + +static inline unsigned int hal_mepc_read() { + int retval; + asm volatile ("csrr %0, 0x341" : "=r" (retval)); + return retval; +} + +static inline unsigned int core_id() { + int hart_id; + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); + // in PULP the hart id is {22'b0, cluster_id, core_id} + return hart_id & 0x01f; +} + +static inline unsigned int cluster_id() { int hart_id; + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); + // in PULP the hart id is {22'b0, cluster_id, core_id} + return hart_id & 0x3e0; +} + +static inline unsigned int hal_core_id() { + int hart_id; + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); + // in PULP the hart id is {22'b0, cluster_id, core_id} + return hart_id & 0x01f; +} + +static inline unsigned int hal_cluster_id() { + int hart_id; + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); + // in PULP the hart id is {22'b0, cluster_id, core_id} + return (hart_id >> 5) & 0x3f; +} + +static inline unsigned int hal_has_fc() { +#ifdef PLP_HAS_FC + return 1; +#else + return 0; +#endif +} + +static inline unsigned int hal_is_fc() { + if (hal_has_fc()) return hal_cluster_id() == 32; + else return 0; +} + +static inline int hal_irq_disable() +{ + int result; + asm volatile ("csrrc %0, 0x300, %1" : "=r" (result) : "I" (0) ); + return result; +} + +static inline void hal_irq_restore(int state) +{ + int result; + asm volatile ("csrrc %0, 0x300, %1" : "=r" (result) : "r" (state) ); +} + +static inline void hal_irq_enable() +{ + int result; + asm volatile ("csrrc %0, 0x300, %1" : "=r" (result) : "I" (0x1<<1) ); +} + +/* + * PERFORMANCE COUNTERS + * + * API for accessing performance counters registers. + * Have a look at file spr-defs.h to speficy registers through defines + * SPR_PCER_* and SPR_PCMR_* + */ + +#define PCER_NB_EVENTS CSR_PCER_NB_EVENTS +#define PCER_ALL_EVENTS_MASK CSR_PCER_ALL_EVENTS_MASK +#define PCMR_ACTIVE CSR_PCMR_ACTIVE +#define PCMR_SATURATE CSR_PCMR_SATURATE + +/* Configure the active events. eventMask is an OR of events got through SPR_PCER_EVENT_MASK */ +static inline void cpu_perf_conf_events(unsigned int eventMask) +{ + asm volatile ("csrw 0x7A0, %0" : "+r" (eventMask)); +} + +/* Return events configuration */ +static inline unsigned int cpu_perf_conf_events_get() +{ + unsigned int result; + asm volatile ("csrr %0, 0x7A0" : "=r" (result)); + return result; +} + +/* Configure the mode. confMask is an OR of all SPR_PCMR_* macros */ +static inline void cpu_perf_conf(unsigned int confMask) +{ + asm volatile ("csrw 0x7A1, %0" :: "r" (confMask)); +} + +/* Starts counting in all counters. As this is using the mode register, + * the rest of the config can be given through conf parameter */ +static inline void cpu_perf_start(unsigned int conf) { + cpu_perf_conf(conf | CSR_PCMR_ACTIVE); // TODO +} + +/* Stops counting in all counters. As this is using the mode register, + * the rest of the config can be given through conf parameter */ +static inline void cpu_perf_stop(unsigned int conf) { + cpu_perf_conf(conf); // TODO +} + +/* Set the specified counter to the specified value */ +static inline void cpu_perf_set(unsigned int counterId, unsigned int value); + +/* Set all counters to the specified value */ +static inline void cpu_perf_setall(unsigned int value) { + asm volatile ("csrw 0x79F, %0" :: "r" (value)); +} + +/* Return the value of the specified counter */ +static inline unsigned int cpu_perf_get(const unsigned int counterId) { + unsigned int value = 0; + + // This is stupid! But I really don't know how else we could do that + switch(counterId) { + case 0: asm volatile ("csrr %0, 0x780" : "=r" (value)); break; + case 1: asm volatile ("csrr %0, 0x781" : "=r" (value)); break; + case 2: asm volatile ("csrr %0, 0x782" : "=r" (value)); break; + case 3: asm volatile ("csrr %0, 0x783" : "=r" (value)); break; + case 4: asm volatile ("csrr %0, 0x784" : "=r" (value)); break; + case 5: asm volatile ("csrr %0, 0x785" : "=r" (value)); break; + case 6: asm volatile ("csrr %0, 0x786" : "=r" (value)); break; + case 7: asm volatile ("csrr %0, 0x787" : "=r" (value)); break; + case 8: asm volatile ("csrr %0, 0x788" : "=r" (value)); break; + case 9: asm volatile ("csrr %0, 0x789" : "=r" (value)); break; + case 10: asm volatile ("csrr %0, 0x78A" : "=r" (value)); break; + case 11: asm volatile ("csrr %0, 0x78B" : "=r" (value)); break; + case 12: asm volatile ("csrr %0, 0x78C" : "=r" (value)); break; + case 13: asm volatile ("csrr %0, 0x78D" : "=r" (value)); break; + case 14: asm volatile ("csrr %0, 0x78E" : "=r" (value)); break; + case 15: asm volatile ("csrr %0, 0x78F" : "=r" (value)); break; + case 16: asm volatile ("csrr %0, 0x790" : "=r" (value)); break; + case 17: asm volatile ("csrr %0, 0x791" : "=r" (value)); break; + case 18: asm volatile ("csrr %0, 0x792" : "=r" (value)); break; + case 19: asm volatile ("csrr %0, 0x793" : "=r" (value)); break; + case 20: asm volatile ("csrr %0, 0x794" : "=r" (value)); break; + case 21: asm volatile ("csrr %0, 0x795" : "=r" (value)); break; + case 22: asm volatile ("csrr %0, 0x796" : "=r" (value)); break; + case 23: asm volatile ("csrr %0, 0x797" : "=r" (value)); break; + case 24: asm volatile ("csrr %0, 0x798" : "=r" (value)); break; + case 25: asm volatile ("csrr %0, 0x799" : "=r" (value)); break; + case 26: asm volatile ("csrr %0, 0x79A" : "=r" (value)); break; + case 27: asm volatile ("csrr %0, 0x79B" : "=r" (value)); break; + case 28: asm volatile ("csrr %0, 0x79C" : "=r" (value)); break; + case 29: asm volatile ("csrr %0, 0x79D" : "=r" (value)); break; + case 30: asm volatile ("csrr %0, 0x79E" : "=r" (value)); break; + } + return value; +} + +static inline char *cpu_perf_name(int event) { + switch (event) + { + case 0: return "CYCLES"; + case 1: return "INSTR"; + case 2: return "LD_STALL"; + case 3: return "JMP_STALL"; + case 4: return "IMISS"; + case 5: return "LD"; + case 6: return "ST"; + case 7: return "JUMP"; + case 8: return "BRANCH"; + case 9: return "TAKEN_BRANCH"; + case 10: return "RVC"; + case 11: return "LD_EXT"; + case 12: return "ST_EXT"; + case 13: return "LD_EXT_CYC"; + case 14: return "ST_EXT_CYC"; + case 15: return "TCDM_CONT"; + } + return (char *)0; +} + + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/riscv/riscv_v4.h b/sw/pulp-sdk/hal/include/hal/riscv/riscv_v4.h new file mode 100644 index 0000000..2d00fde --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/riscv/riscv_v4.h @@ -0,0 +1,648 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_RISCV_RISCV_V4_H__ +#define __HAL_RISCV_RISCV_V4_H__ + +#include "archi/pulp.h" + +#include "hal/riscv/types.h" +#include "archi/riscv/builtins_v2.h" +#include "archi/riscv/builtins_v2_emu.h" + +#define CSR_PCMR_ACTIVE 0x1 + +#define SR_MTVEC 0x305 + + + + + + +#if defined(__OPTIMIZE__) && defined(CORE_PULP_BUILTINS) && !defined(__LLVM__) + +static inline unsigned int hal_spr_read_then_clr(unsigned int reg, unsigned int val) +{ + return __builtin_pulp_read_then_spr_bit_clr(reg, val); +} + +static inline unsigned int hal_spr_read_then_set(unsigned int reg, unsigned int val) +{ + return __builtin_pulp_read_then_spr_bit_set(reg, val); +} + +static inline void hal_spr_write(unsigned int reg, unsigned int val) +{ + __builtin_pulp_spr_write(reg, val); +} + +static inline unsigned int hal_spr_read(unsigned int reg) +{ + return __builtin_pulp_spr_read(reg); +} + +#else + +#if defined(__LLVM__) + +#else + +#define hal_spr_read_then_clr(reg,val) \ + ({ \ + int state; \ + asm volatile ("csrrc %0, %1, %2" : "=r" (state) : "I" (reg), "I" (val) ); \ + state; \ + }) + +#define hal_spr_read_then_set(reg,val) \ + ({ \ + int state; \ + asm volatile ("csrrs %0, %1, %2" : "=r" (state) : "I" (reg), "I" (val) ); \ + state; \ + }) + +#define hal_spr_write(reg,val) \ +do { \ + asm volatile ("csrw %0, %1" : : "I" (reg), "r" (val) ); \ +} while(0) + +#define hal_spr_read(reg) \ +({ \ + int result; \ + asm volatile ("csrr %0, %1" : "=r" (result) : "I" (reg) ); \ + result; \ +}) + +#endif + +#endif + + + + + +#if defined(__LLVM__) + +#define csr_read(csr) \ +({ \ + register unsigned int __v; \ + __asm__ __volatile__ ("csrr %0, " #csr \ + : "=r" (__v)); \ + __v; \ +}) + +#define hal_mepc_read() csr_read(0x341) + +#else +#define hal_mepc_read() hal_spr_read(RV_CSR_MEPC) +#endif + +static inline unsigned int core_id() { + int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return hart_id & 0x01f; +} + +static inline unsigned int cluster_id() { int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return (hart_id >> 5) & 0x3f; +} + +#ifndef PLP_NO_BUILTIN + +static inline unsigned int hal_core_id() { + return core_id(); + //return __builtin_pulp_CoreId(); +} + +static inline unsigned int hal_cluster_id() { + return cluster_id(); + //return __builtin_pulp_ClusterId(); +} + +// TODO replace by compiler builtin +static inline __attribute__((always_inline)) unsigned int hal_has_fc() { +#ifdef ARCHI_HAS_FC + return 1; +#else + return 0; +#endif +} + +static inline __attribute__((always_inline)) unsigned int hal_is_fc() { +#ifndef ARCHI_HAS_FC + return 0; +#else + if (hal_has_fc()) return hal_cluster_id() == ARCHI_FC_CID; + else return 0; +#endif +} + +#else + +static inline __attribute__((always_inline)) unsigned int hal_core_id() { + int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return hart_id & 0x01f; +} + +static inline __attribute__((always_inline)) unsigned int hal_cluster_id() { + int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return (hart_id >> 5) & 0x3f; +} + +static inline __attribute__((always_inline)) unsigned int hal_has_fc() { +#ifdef ARCHI_HAS_FC + return 1; +#else + return 0; +#endif +} + +static inline __attribute__((always_inline)) unsigned int hal_is_fc() { +#ifndef ARCHI_HAS_FC + return 0; +#else + if (hal_has_fc()) return hal_cluster_id() == ARCHI_FC_CID; + else return 0; +#endif +} + +#endif + + + +#if defined(__LLVM__) + +static inline int hal_irq_disable() +{ + return 0; +} + +static inline void hal_irq_restore(int state) +{ +} + +static inline void hal_irq_enable() +{ +} + +#else + +static inline int hal_irq_disable() +{ + int irq = hal_spr_read_then_clr(0x300, 0x1<<3); + // This memory barrier is needed to prevent the compiler to cross the irq barrier + __asm__ __volatile__ ("" : : : "memory"); + return irq; +} + +static inline void hal_irq_restore(int state) +{ + // This memory barrier is needed to prevent the compiler to cross the irq barrier + __asm__ __volatile__ ("" : : : "memory"); + hal_spr_write(0x300, state); +} + +static inline void hal_irq_enable() +{ + // This memory barrier is needed to prevent the compiler to cross the irq barrier + __asm__ __volatile__ ("" : : : "memory"); + hal_spr_read_then_set(0x300, 0x1<<3); +} + +#endif + +/* + * PERFORMANCE COUNTERS + * + * API for accessing performance counters registers. + * Have a look at file spr-defs.h to speficy registers through defines + * SPR_PCER_* and SPR_PCMR_* + */ + +#define PCER_NB_EVENTS CSR_PCER_NB_EVENTS +#define PCER_ALL_EVENTS_MASK CSR_PCER_ALL_EVENTS_MASK +#define PCMR_ACTIVE CSR_PCMR_ACTIVE +#define PCMR_SATURATE CSR_PCMR_SATURATE + +/* Configure the active events. eventMask is an OR of events got through SPR_PCER_EVENT_MASK */ +static inline void cpu_perf_conf_events(unsigned int eventMask) +{ +#ifndef PLP_NO_PERF_COUNTERS + asm volatile ("csrw 0x7A0, %0" : "+r" (eventMask)); +#endif +} + +/* Return events configuration */ +static inline unsigned int cpu_perf_conf_events_get() +{ +#ifndef PLP_NO_PERF_COUNTERS + unsigned int result; + asm volatile ("csrr %0, 0x7A0" : "=r" (result)); + return result; +#else + return 0; +#endif +} + +/* Configure the mode. confMask is an OR of all SPR_PCMR_* macros */ +static inline void cpu_perf_conf(unsigned int confMask) +{ +#ifndef PLP_NO_PERF_COUNTERS + asm volatile ("csrw 0x7A1, %0" :: "r" (confMask)); +#endif +} + +/* Starts counting in all counters. As this is using the mode register, + * the rest of the config can be given through conf parameter */ +static inline void cpu_perf_start(unsigned int conf) { +#ifndef PLP_NO_PERF_COUNTERS + cpu_perf_conf(conf | CSR_PCMR_ACTIVE); // TODO +#endif +} + +/* Stops counting in all counters. As this is using the mode register, + * the rest of the config can be given through conf parameter */ +static inline void cpu_perf_stop(unsigned int conf) { +#ifndef PLP_NO_PERF_COUNTERS + cpu_perf_conf(conf); // TODO +#endif +} + +/* Set the specified counter to the specified value */ +static inline void cpu_perf_set(unsigned int counterId, unsigned int value) { + +} + +/* Set all counters to the specified value */ +static inline void cpu_perf_setall(unsigned int value) { +#ifndef PLP_NO_PERF_COUNTERS + asm volatile ("csrw 0x79F, %0" :: "r" (value)); +#endif +} + +/* Return the value of the specified counter */ +static inline unsigned int cpu_perf_get(const unsigned int counterId) { +#ifndef PLP_NO_PERF_COUNTERS + unsigned int value = 0; + + // This is stupid! But I really don't know how else we could do that + switch(counterId) { + case 0: asm volatile ("csrr %0, 0x780" : "=r" (value)); break; + case 1: asm volatile ("csrr %0, 0x781" : "=r" (value)); break; + case 2: asm volatile ("csrr %0, 0x782" : "=r" (value)); break; + case 3: asm volatile ("csrr %0, 0x783" : "=r" (value)); break; + case 4: asm volatile ("csrr %0, 0x784" : "=r" (value)); break; + case 5: asm volatile ("csrr %0, 0x785" : "=r" (value)); break; + case 6: asm volatile ("csrr %0, 0x786" : "=r" (value)); break; + case 7: asm volatile ("csrr %0, 0x787" : "=r" (value)); break; + case 8: asm volatile ("csrr %0, 0x788" : "=r" (value)); break; + case 9: asm volatile ("csrr %0, 0x789" : "=r" (value)); break; + case 10: asm volatile ("csrr %0, 0x78A" : "=r" (value)); break; + case 11: asm volatile ("csrr %0, 0x78B" : "=r" (value)); break; + case 12: asm volatile ("csrr %0, 0x78C" : "=r" (value)); break; + case 13: asm volatile ("csrr %0, 0x78D" : "=r" (value)); break; + case 14: asm volatile ("csrr %0, 0x78E" : "=r" (value)); break; + case 15: asm volatile ("csrr %0, 0x78F" : "=r" (value)); break; + case 16: asm volatile ("csrr %0, 0x790" : "=r" (value)); break; + case 17: asm volatile ("csrr %0, 0x791" : "=r" (value)); break; + case 18: asm volatile ("csrr %0, 0x792" : "=r" (value)); break; + case 19: asm volatile ("csrr %0, 0x793" : "=r" (value)); break; + case 20: asm volatile ("csrr %0, 0x794" : "=r" (value)); break; + case 21: asm volatile ("csrr %0, 0x795" : "=r" (value)); break; + case 22: asm volatile ("csrr %0, 0x796" : "=r" (value)); break; + case 23: asm volatile ("csrr %0, 0x797" : "=r" (value)); break; + case 24: asm volatile ("csrr %0, 0x798" : "=r" (value)); break; + case 25: asm volatile ("csrr %0, 0x799" : "=r" (value)); break; + case 26: asm volatile ("csrr %0, 0x79A" : "=r" (value)); break; + case 27: asm volatile ("csrr %0, 0x79B" : "=r" (value)); break; + case 28: asm volatile ("csrr %0, 0x79C" : "=r" (value)); break; + case 29: asm volatile ("csrr %0, 0x79D" : "=r" (value)); break; + case 30: asm volatile ("csrr %0, 0x79E" : "=r" (value)); break; + } + return value; +#else + return 0; +#endif +} + +static inline const char *cpu_perf_name(int event) { + switch (event) + { + case 0: return "CYCLES"; + case 1: return "INSTR"; + case 2: return "LD_STALL"; + case 3: return "JMP_STALL"; + case 4: return "IMISS"; + case 5: return "LD"; + case 6: return "ST"; + case 7: return "JUMP"; + case 8: return "BRANCH"; + case 9: return "TAKEN_BRANCH"; + case 10: return "RVC"; + case 11: return "LD_EXT"; + case 12: return "ST_EXT"; + case 13: return "LD_EXT_CYC"; + case 14: return "ST_EXT_CYC"; + case 15: return "TCDM_CONT"; + } + return (char *)0; +} + + + +/* + * Stack checking + */ + +static inline void cpu_stack_check_enable(unsigned int base, unsigned int end) +{ + asm volatile ("csrwi 0x7D0, 0" :: ); + asm volatile ("csrw 0x7D1, %0" :: "r" (base)); + asm volatile ("csrw 0x7D2, %0" :: "r" (end)); + asm volatile ("csrwi 0x7D0, 1" :: ); +} + +static inline void cpu_stack_check_disable() +{ + asm volatile ("csrwi 0x7D0, 0" :: ); +} + + + +#if !defined(RV_ISA_RV32) + +/* Packing of scalars into vectors */ +#define __builtin_pack2(x, y) __builtin_pulp_pack2((signed short) (x), (signed short) (y)) +#define __builtin_packu2(x, y) __builtin_pulp_pack2((unsigned short) (x), (unsigned short) (y)) + +#define __builtin_pack4(x, y, z, t) __builtin_pulp_pack4((signed char) (x), (signed char) (y), (signed char) (z), (signed char) (t)) +#define __builtin_packu4(x, y, z, t) __builtin_pulp_pack4((unsigned char) (x), (unsigned char) (y), (unsigned char) (z), (unsigned char) (t)) + +#define __builtin_max2(x, y) __builtin_pulp_max2((x), (y)) +#define __builtin_max4(x, y) __builtin_pulp_max4((x), (y)) + +#define __builtin_maxu2(x, y) __builtin_pulp_maxu2((x), (y)) +#define __builtin_maxu4(x, y) __builtin_pulp_maxu4((x), (y)) + +/* Min */ +#define __builtin_min2(x, y) __builtin_pulp_min2((x), (y)) +#define __builtin_min4(x, y) __builtin_pulp_min4((x), (y)) + +#define __builtin_minu2(x, y) __builtin_pulp_minu2((x), (y)) +#define __builtin_minu4(x, y) __builtin_pulp_minu4((x), (y)) + +/* Clip */ +#define __builtin_clip(x, precision) __builtin_pulp_clip((x), -(1<<(precision)), (1<(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]>(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __builtin_max4(x, y) ((v4s) {((signed char)(x)[0]>(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]>(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]>(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]>(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __builtin_maxu2(x, y) ((v2u) {((unsigned short)(x)[0]>(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]>(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __builtin_maxu4(x, y) ((v4u) {((unsigned char)(x)[0]>(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]>(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]>(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]>(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Min */ +#define __builtin_min2(x, y) ((v2s) {((signed short)(x)[0]<(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]<(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __builtin_min4(x, y) ((v4s) {((signed char)(x)[0]<(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]<(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]<(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]<(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __builtin_minu2(x, y) ((v2u) {((unsigned short)(x)[0]<(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]<(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __builtin_minu4(x, y) ((v4u) {((unsigned char)(x)[0]<(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]<(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]<(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]<(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Clip */ +#define __builtin_clip(x, precision) ((x)<(-(1<<(precision)))?(-(1<<(precision))):(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x))) +#define __builtin_clipu(x, precision) ((x)<0)?0:(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x)) + +/* Abs */ +#define __builtin_abs2(x) ((v2s) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1]}) +#define __builtin_abs4(x) ((v4s) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1], \ + ((x)[2]<0)?-(x)[2]:(x)[2], ((x)[3]<0)?-(x)[3]:(x)[3]}) + +/* Mac */ +#define __builtin_macs(Acc, x, y) ((Acc) + ((short int) (x) * (short int) (y))) +#define __builtin_machhs(Acc, x, y) ((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) +#define __builtin_macu(Acc, x, y) ((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) +#define __builtin_machhu(Acc, x, y) ((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + +#define __builtin_macsN(Acc, x, y, n) (((Acc) + ((short int) (x) * (short int) (y)))>>(n)) +#define __builtin_macuN(Acc, x, y, n) (((Acc) + ((unsigned short int) (x) * (unsigned short int) (y)))>>(n)) +#define __builtin_macsRN(Acc, x, y, n) ((((Acc) + ((short int) (x) * (short int) (y))) + (1<<((n)-1))) >> (n)) +#define __builtin_macuRN(Acc, x, y, n) ((((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) + (1<<((n)-1))) >> (n)) + +#define __builtin_machhsN(Acc, x, y, n) (((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) >> (n)) +#define __builtin_machhuN(Acc, x, y, n) (((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) >> (n)) +#define __builtin_machhsRN(Acc, x, y, n) ((((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) + (1<<((n)-1))) >> (n)) +#define __builtin_machhuRN(Acc, x, y, n) ((((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + (n))) + +/* Multiplications */ +#define __builtin_mulsN(x, y, n) (((short int) (x) * (short int) (y))>>(n)) +#define __builtin_mulsRN(x, y, n) ((((short int) (x) * (short int) (y)) + (1<<((n)-1)))>>(n)) +#define __builtin_muluN(x, y, n) (((unsigned short int) (x) * (unsigned short int) (y))>>(n)) +#define __builtin_muluRN(x, y, n) ((((unsigned short int) (x) * (unsigned short int) (y)) + (1<<((n)-1)))>>(n)) + +/* Vectorial product and sum of products */ +#define __builtin_dotp2(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_dotpu2(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_dotpus2(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1]) + +#define __builtin_sumdotp2(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_sumdotpu2(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_sumdotpus2(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1]) + +#define __builtin_dotp4(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_dotpu4(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_dotpus4(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) + +#define __builtin_sumdotp4(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_sumdotpu4(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_sumdotpus4(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) + + +/* Position of the most significant bit of x */ +#define __FL1(x) (31 - __builtin_clz((x))) + +/* Number of sign bits */ +static inline unsigned int __builtin_clb(unsigned int x) { + int result = 0; + while (x) { + if (x & 1) result++; + x >>= 1; + } + return result; +} + +/* Bit Extraction */ +#define __builtin_bitextract(x, size, off) (((((x)>>(off))&((unsigned int)(1<<(size))-1))<<(32-(size)))>>(32-(size))) +#define __builtin_bitextractu(x, size, off) (((x)>>(off))&((unsigned int)(1<<(size))-1)) + +/* Bit insertion */ +#define __builtin_bitinsert(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) +#define __builtin_bitinsert_r(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) + +/* 1 bit rotation to the right, 32 bits input */ +#define __builtin_rotr(x) ((((x)>>1)&0x7FFFFFFF) | ((x)<<31)) + +/* Add with normalization and rounding */ +#define __builtin_addroundnormu(x, y, scale) ((unsigned int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __builtin_addroundnorm(x, y, scale) ((int)((x) + (y) + (1<<((scale)-1)))>>(scale)) + +/* Normalization and rounding */ +#define __builtin_roundnormu(x, scale) ((unsigned int)((x) + (1<<((scale)-1)))>>(scale)) +#define __builtin_roundnorm(x, scale) ((int)((x) + (1<<((scale)-1)))>>(scale)) + +#endif + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/riscv/riscv_v5.h b/sw/pulp-sdk/hal/include/hal/riscv/riscv_v5.h new file mode 100644 index 0000000..23da57a --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/riscv/riscv_v5.h @@ -0,0 +1,669 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_RISCV_RISCV_V5_H__ +#define __HAL_RISCV_RISCV_V5_H__ + +#include "archi/pulp.h" + +#include "hal/riscv/types.h" +#include "archi/riscv/builtins_v2.h" +#include "archi/riscv/builtins_v2_emu.h" + +#define CSR_PCMR_ACTIVE 0x1 + +#define SR_MTVEC 0x305 + + + + + + +#if defined(__OPTIMIZE__) && defined(CORE_PULP_BUILTINS) && !defined(__LLVM__) + +static inline unsigned int hal_spr_read_then_clr(unsigned int reg, unsigned int val) +{ + return __builtin_pulp_read_then_spr_bit_clr(reg, val); +} + +static inline unsigned int hal_spr_read_then_set(unsigned int reg, unsigned int val) +{ + return __builtin_pulp_read_then_spr_bit_set(reg, val); +} + +static inline void hal_spr_write(unsigned int reg, unsigned int val) +{ + __builtin_pulp_spr_write(reg, val); +} + +static inline unsigned int hal_spr_read(unsigned int reg) +{ + return __builtin_pulp_spr_read(reg); +} + +#else + +#if defined(__LLVM__) + +#else + +#define hal_spr_read_then_clr(reg,val) \ + ({ \ + int state; \ + asm volatile ("csrrc %0, %1, %2" : "=r" (state) : "I" (reg), "I" (val) ); \ + state; \ + }) + +#define hal_spr_read_then_set(reg,val) \ + ({ \ + int state; \ + asm volatile ("csrrs %0, %1, %2" : "=r" (state) : "I" (reg), "I" (val) ); \ + state; \ + }) + +#define hal_spr_read_then_clr_from_reg(reg,val) \ + ({ \ + int state; \ + asm volatile ("csrrc %0, %1, %2" : "=r" (state) : "I" (reg), "r" (val) ); \ + state; \ + }) + +#define hal_spr_read_then_set(reg,val) \ + ({ \ + int state; \ + asm volatile ("csrrs %0, %1, %2" : "=r" (state) : "I" (reg), "I" (val) ); \ + state; \ + }) + +#define hal_spr_read_then_set_from_reg(reg,val) \ + ({ \ + int state; \ + asm volatile ("csrrs %0, %1, %2" : "=r" (state) : "I" (reg), "r" (val) ); \ + state; \ + }) + +#define hal_spr_write(reg,val) \ +do { \ + asm volatile ("csrw %0, %1" : : "I" (reg), "r" (val) ); \ +} while(0) + +#define hal_spr_read(reg) \ +({ \ + int result; \ + asm volatile ("csrr %0, %1" : "=r" (result) : "I" (reg) ); \ + result; \ +}) + +#endif + +#endif + + + + + +#if defined(__LLVM__) + +#define csr_read(csr) \ +({ \ + register unsigned int __v; \ + __asm__ __volatile__ ("csrr %0, " #csr \ + : "=r" (__v)); \ + __v; \ +}) + +#define hal_mepc_read() csr_read(0x341) + +#else +#define hal_mepc_read() hal_spr_read(RV_CSR_MEPC) +#endif + +static inline unsigned int core_id() { + int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return hart_id & 0x01f; +} + +static inline unsigned int cluster_id() { int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return (hart_id >> 5) & 0x3f; +} + +#ifndef PLP_NO_BUILTIN + +static inline unsigned int hal_core_id() { + return core_id(); + //return __builtin_pulp_CoreId(); +} + +static inline unsigned int hal_cluster_id() { + return cluster_id(); + //return __builtin_pulp_ClusterId(); +} + +// TODO replace by compiler builtin +static inline __attribute__((always_inline)) unsigned int hal_has_fc() { +#ifdef ARCHI_HAS_FC + return 1; +#else + return 0; +#endif +} + +static inline __attribute__((always_inline)) unsigned int hal_is_fc() { +#ifndef ARCHI_HAS_FC + return 0; +#else + if (hal_has_fc()) return hal_cluster_id() == ARCHI_FC_CID; + else return 0; +#endif +} + +#else + +static inline __attribute__((always_inline)) unsigned int hal_core_id() { + int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return hart_id & 0x01f; +} + +static inline __attribute__((always_inline)) unsigned int hal_cluster_id() { + int hart_id; +#if RISCV_VERSION >= 4 && !defined(RISCV_1_7) +#if PULP_CHIP_FAMILY == CHIP_GAP + asm("csrr %0, 0x014" : "=r" (hart_id) : ); +#else + asm("csrr %0, 0xF14" : "=r" (hart_id) : ); +#endif +#else + asm("csrr %0, 0xF10" : "=r" (hart_id) : ); +#endif + // in PULP the hart id is {22'b0, cluster_id, core_id} + return (hart_id >> 5) & 0x3f; +} + +static inline __attribute__((always_inline)) unsigned int hal_has_fc() { +#ifdef ARCHI_HAS_FC + return 1; +#else + return 0; +#endif +} + +static inline __attribute__((always_inline)) unsigned int hal_is_fc() { +#ifndef ARCHI_HAS_FC + return 0; +#else + if (hal_has_fc()) return hal_cluster_id() == ARCHI_FC_CID; + else return 0; +#endif +} + +#endif + + + +#if defined(__LLVM__) + +static inline int hal_irq_disable() +{ + return 0; +} + +static inline void hal_irq_restore(int state) +{ +} + +static inline void hal_irq_enable() +{ +} + +#else + +static inline int hal_irq_disable() +{ + int irq = hal_spr_read_then_clr(0x300, 0x1<<3); + // This memory barrier is needed to prevent the compiler to cross the irq barrier + __asm__ __volatile__ ("" : : : "memory"); + return irq; +} + +static inline void hal_irq_restore(int state) +{ + // This memory barrier is needed to prevent the compiler to cross the irq barrier + __asm__ __volatile__ ("" : : : "memory"); + hal_spr_write(0x300, state); +} + +static inline void hal_irq_enable() +{ + // This memory barrier is needed to prevent the compiler to cross the irq barrier + __asm__ __volatile__ ("" : : : "memory"); + hal_spr_read_then_set(0x300, 0x1<<3); +} + +#endif + +/* + * PERFORMANCE COUNTERS + * + * API for accessing performance counters registers. + * Have a look at file spr-defs.h to speficy registers through defines + * SPR_PCER_* and SPR_PCMR_* + */ + +#define PCER_NB_EVENTS CSR_PCER_NB_EVENTS +#define PCER_ALL_EVENTS_MASK CSR_PCER_ALL_EVENTS_MASK +#define PCMR_ACTIVE CSR_PCMR_ACTIVE +#define PCMR_SATURATE CSR_PCMR_SATURATE + +/* Configure the active events. eventMask is an OR of events got through SPR_PCER_EVENT_MASK */ +static inline void cpu_perf_conf_events(unsigned int eventMask) +{ +#ifndef PLP_NO_PERF_COUNTERS + asm volatile ("csrw 0xCC0, %0" : "+r" (eventMask)); +#endif +} + +/* Return events configuration */ +static inline unsigned int cpu_perf_conf_events_get() +{ +#ifndef PLP_NO_PERF_COUNTERS + unsigned int result; + asm volatile ("csrr %0, 0xCC0" : "=r" (result)); + return result; +#else + return 0; +#endif +} + +/* Configure the mode. confMask is an OR of all SPR_PCMR_* macros */ +static inline void cpu_perf_conf(unsigned int confMask) +{ +#ifndef PLP_NO_PERF_COUNTERS + asm volatile ("csrw 0xCC1, %0" :: "r" (confMask)); +#endif +} + +/* Starts counting in all counters. As this is using the mode register, + * the rest of the config can be given through conf parameter */ +static inline void cpu_perf_start(unsigned int conf) { +#ifndef PLP_NO_PERF_COUNTERS + cpu_perf_conf(conf | CSR_PCMR_ACTIVE); // TODO +#endif +} + +/* Stops counting in all counters. As this is using the mode register, + * the rest of the config can be given through conf parameter */ +static inline void cpu_perf_stop(unsigned int conf) { +#ifndef PLP_NO_PERF_COUNTERS + cpu_perf_conf(conf); // TODO +#endif +} + +/* Set the specified counter to the specified value */ +static inline void cpu_perf_set(unsigned int counterId, unsigned int value) { + +} + +/* Set all counters to the specified value */ +static inline void cpu_perf_setall(unsigned int value) { +#ifndef PLP_NO_PERF_COUNTERS + asm volatile ("csrw 0x79F, %0" :: "r" (value)); +#endif +} + +/* Return the value of the specified counter */ +static inline unsigned int cpu_perf_get(const unsigned int counterId) { +#ifndef PLP_NO_PERF_COUNTERS + unsigned int value = 0; + + // This is stupid! But I really don't know how else we could do that + switch(counterId) { + case 0: asm volatile ("csrr %0, 0x780" : "=r" (value)); break; + case 1: asm volatile ("csrr %0, 0x781" : "=r" (value)); break; + case 2: asm volatile ("csrr %0, 0x782" : "=r" (value)); break; + case 3: asm volatile ("csrr %0, 0x783" : "=r" (value)); break; + case 4: asm volatile ("csrr %0, 0x784" : "=r" (value)); break; + case 5: asm volatile ("csrr %0, 0x785" : "=r" (value)); break; + case 6: asm volatile ("csrr %0, 0x786" : "=r" (value)); break; + case 7: asm volatile ("csrr %0, 0x787" : "=r" (value)); break; + case 8: asm volatile ("csrr %0, 0x788" : "=r" (value)); break; + case 9: asm volatile ("csrr %0, 0x789" : "=r" (value)); break; + case 10: asm volatile ("csrr %0, 0x78A" : "=r" (value)); break; + case 11: asm volatile ("csrr %0, 0x78B" : "=r" (value)); break; + case 12: asm volatile ("csrr %0, 0x78C" : "=r" (value)); break; + case 13: asm volatile ("csrr %0, 0x78D" : "=r" (value)); break; + case 14: asm volatile ("csrr %0, 0x78E" : "=r" (value)); break; + case 15: asm volatile ("csrr %0, 0x78F" : "=r" (value)); break; + case 16: asm volatile ("csrr %0, 0x790" : "=r" (value)); break; + case 17: asm volatile ("csrr %0, 0x791" : "=r" (value)); break; + case 18: asm volatile ("csrr %0, 0x792" : "=r" (value)); break; + case 19: asm volatile ("csrr %0, 0x793" : "=r" (value)); break; + case 20: asm volatile ("csrr %0, 0x794" : "=r" (value)); break; + case 21: asm volatile ("csrr %0, 0x795" : "=r" (value)); break; + case 22: asm volatile ("csrr %0, 0x796" : "=r" (value)); break; + case 23: asm volatile ("csrr %0, 0x797" : "=r" (value)); break; + case 24: asm volatile ("csrr %0, 0x798" : "=r" (value)); break; + case 25: asm volatile ("csrr %0, 0x799" : "=r" (value)); break; + case 26: asm volatile ("csrr %0, 0x79A" : "=r" (value)); break; + case 27: asm volatile ("csrr %0, 0x79B" : "=r" (value)); break; + case 28: asm volatile ("csrr %0, 0x79C" : "=r" (value)); break; + case 29: asm volatile ("csrr %0, 0x79D" : "=r" (value)); break; + case 30: asm volatile ("csrr %0, 0x79E" : "=r" (value)); break; + } + return value; +#else + return 0; +#endif +} + +static inline const char *cpu_perf_name(int event) { + switch (event) + { + case 0: return "CYCLES"; + case 1: return "INSTR"; + case 2: return "LD_STALL"; + case 3: return "JMP_STALL"; + case 4: return "IMISS"; + case 5: return "LD"; + case 6: return "ST"; + case 7: return "JUMP"; + case 8: return "BRANCH"; + case 9: return "TAKEN_BRANCH"; + case 10: return "RVC"; + case 11: return "LD_EXT"; + case 12: return "ST_EXT"; + case 13: return "LD_EXT_CYC"; + case 14: return "ST_EXT_CYC"; + case 15: return "TCDM_CONT"; + } + return (char *)0; +} + + + +/* + * Stack checking + */ + +static inline void cpu_stack_check_enable(unsigned int base, unsigned int end) +{ + asm volatile ("csrwi 0x7D0, 0" :: ); + asm volatile ("csrw 0x7D1, %0" :: "r" (base)); + asm volatile ("csrw 0x7D2, %0" :: "r" (end)); + asm volatile ("csrwi 0x7D0, 1" :: ); +} + +static inline void cpu_stack_check_disable() +{ + asm volatile ("csrwi 0x7D0, 0" :: ); +} + + + +#if !defined(RV_ISA_RV32) + +/* Packing of scalars into vectors */ +#define __builtin_pack2(x, y) __builtin_pulp_pack2((signed short) (x), (signed short) (y)) +#define __builtin_packu2(x, y) __builtin_pulp_pack2((unsigned short) (x), (unsigned short) (y)) + +#define __builtin_pack4(x, y, z, t) __builtin_pulp_pack4((signed char) (x), (signed char) (y), (signed char) (z), (signed char) (t)) +#define __builtin_packu4(x, y, z, t) __builtin_pulp_pack4((unsigned char) (x), (unsigned char) (y), (unsigned char) (z), (unsigned char) (t)) + +#define __builtin_max2(x, y) __builtin_pulp_max2((x), (y)) +#define __builtin_max4(x, y) __builtin_pulp_max4((x), (y)) + +#define __builtin_maxu2(x, y) __builtin_pulp_maxu2((x), (y)) +#define __builtin_maxu4(x, y) __builtin_pulp_maxu4((x), (y)) + +/* Min */ +#define __builtin_min2(x, y) __builtin_pulp_min2((x), (y)) +#define __builtin_min4(x, y) __builtin_pulp_min4((x), (y)) + +#define __builtin_minu2(x, y) __builtin_pulp_minu2((x), (y)) +#define __builtin_minu4(x, y) __builtin_pulp_minu4((x), (y)) + +/* Clip */ +#define __builtin_clip(x, precision) __builtin_pulp_clip((x), -(1<<(precision)), (1<(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]>(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __builtin_max4(x, y) ((v4s) {((signed char)(x)[0]>(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]>(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]>(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]>(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __builtin_maxu2(x, y) ((v2u) {((unsigned short)(x)[0]>(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]>(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __builtin_maxu4(x, y) ((v4u) {((unsigned char)(x)[0]>(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]>(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]>(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]>(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Min */ +#define __builtin_min2(x, y) ((v2s) {((signed short)(x)[0]<(signed short)(y)[0])?((signed short)(x)[0]):((signed short)(y)[0]), \ + ((signed short)(x)[1]<(signed short)(y)[1])?((signed short)(x)[1]):((signed short)(y)[1])}) +#define __builtin_min4(x, y) ((v4s) {((signed char)(x)[0]<(signed char)(y)[0])?(signed char)(x)[0]:(signed char)(y)[0], \ + ((signed char)(x)[1]<(signed char)(y)[1])?(signed char)(x)[1]:(signed char)(y)[1], \ + ((signed char)(x)[2]<(signed char)(y)[2])?(signed char)(x)[2]:(signed char)(y)[2], \ + ((signed char)(x)[3]<(signed char)(y)[3])?(signed char)(x)[3]:(signed char)(y)[3]}) + +#define __builtin_minu2(x, y) ((v2u) {((unsigned short)(x)[0]<(unsigned short)(y)[0])?(unsigned short)(x)[0]:(unsigned short)(y)[0], \ + ((unsigned short)(x)[1]<(unsigned short)(y)[1])?(unsigned short)(x)[1]:(unsigned short)(y)[1]}) +#define __builtin_minu4(x, y) ((v4u) {((unsigned char)(x)[0]<(unsigned char)(y)[0])?(unsigned char)(x)[0]:(unsigned char)(y)[0], \ + ((unsigned char)(x)[1]<(unsigned char)(y)[1])?(unsigned char)(x)[1]:(unsigned char)(y)[1], \ + ((unsigned char)(x)[2]<(unsigned char)(y)[2])?(unsigned char)(x)[2]:(unsigned char)(y)[2], \ + ((unsigned char)(x)[3]<(unsigned char)(y)[3])?(unsigned char)(x)[3]:(unsigned char)(y)[3]}) + +/* Clip */ +#define __builtin_clip(x, precision) ((x)<(-(1<<(precision)))?(-(1<<(precision))):(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x))) +#define __builtin_clipu(x, precision) ((x)<0)?0:(((x)>((1<<(precision))-1))?((1<<(precision))-1):(x)) + +/* Abs */ +#define __builtin_abs2(x) ((v2s) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1]}) +#define __builtin_abs4(x) ((v4s) {((x)[0]<0)?-(x)[0]:(x)[0], ((x)[1]<0)?-(x)[1]:(x)[1], \ + ((x)[2]<0)?-(x)[2]:(x)[2], ((x)[3]<0)?-(x)[3]:(x)[3]}) + +/* Mac */ +#define __builtin_macs(Acc, x, y) ((Acc) + ((short int) (x) * (short int) (y))) +#define __builtin_machhs(Acc, x, y) ((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) +#define __builtin_macu(Acc, x, y) ((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) +#define __builtin_machhu(Acc, x, y) ((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + +#define __builtin_macsN(Acc, x, y, n) (((Acc) + ((short int) (x) * (short int) (y)))>>(n)) +#define __builtin_macuN(Acc, x, y, n) (((Acc) + ((unsigned short int) (x) * (unsigned short int) (y)))>>(n)) +#define __builtin_macsRN(Acc, x, y, n) ((((Acc) + ((short int) (x) * (short int) (y))) + (1<<((n)-1))) >> (n)) +#define __builtin_macuRN(Acc, x, y, n) ((((Acc) + ((unsigned short int) (x) * (unsigned short int) (y))) + (1<<((n)-1))) >> (n)) + +#define __builtin_machhsN(Acc, x, y, n) (((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) >> (n)) +#define __builtin_machhuN(Acc, x, y, n) (((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) >> (n)) +#define __builtin_machhsRN(Acc, x, y, n) ((((Acc) + ((short int) ((x)>>16) * (short int) ((y)>>16))) + (1<<((n)-1))) >> (n)) +#define __builtin_machhuRN(Acc, x, y, n) ((((Acc) + ((unsigned short int) ((x)>>16) * (unsigned short int) ((y)>>16))) + (n))) + +/* Multiplications */ +#define __builtin_mulsN(x, y, n) (((short int) (x) * (short int) (y))>>(n)) +#define __builtin_mulsRN(x, y, n) ((((short int) (x) * (short int) (y)) + (1<<((n)-1)))>>(n)) +#define __builtin_muluN(x, y, n) (((unsigned short int) (x) * (unsigned short int) (y))>>(n)) +#define __builtin_muluRN(x, y, n) ((((unsigned short int) (x) * (unsigned short int) (y)) + (1<<((n)-1)))>>(n)) + +/* Vectorial product and sum of products */ +#define __builtin_dotp2(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_dotpu2(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_dotpus2(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1]) + +#define __builtin_sumdotp2(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_sumdotpu2(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1]) +#define __builtin_sumdotpus2(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1]) + +#define __builtin_dotp4(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_dotpu4(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_dotpus4(x, y) ( (x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) + +#define __builtin_sumdotp4(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_sumdotpu4(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) +#define __builtin_sumdotpus4(x, y, z) ((z)+(x)[0]*(y)[0] + (x)[1]*(y)[1] + (x)[2]*(y)[2] + (x)[3]*(y)[3]) + + +/* Position of the most significant bit of x */ +#define __FL1(x) (31 - __builtin_clz((x))) + +/* Number of sign bits */ +static inline unsigned int __builtin_clb(unsigned int x) { + int result = 0; + while (x) { + if (x & 1) result++; + x >>= 1; + } + return result; +} + +/* Bit Extraction */ +#define __builtin_bitextract(x, size, off) (((((x)>>(off))&((unsigned int)(1<<(size))-1))<<(32-(size)))>>(32-(size))) +#define __builtin_bitextractu(x, size, off) (((x)>>(off))&((unsigned int)(1<<(size))-1)) + +/* Bit insertion */ +#define __builtin_bitinsert(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) +#define __builtin_bitinsert_r(dst, src, size, off) (((dst) & ~(((1<<(size))-1)<<(off))) | (((src) & ((1<<(size))-1))<<(off))) + +/* 1 bit rotation to the right, 32 bits input */ +#define __builtin_rotr(x) ((((x)>>1)&0x7FFFFFFF) | ((x)<<31)) + +/* Add with normalization and rounding */ +#define __builtin_addroundnormu(x, y, scale) ((unsigned int)((x) + (y) + (1<<((scale)-1)))>>(scale)) +#define __builtin_addroundnorm(x, y, scale) ((int)((x) + (y) + (1<<((scale)-1)))>>(scale)) + +/* Normalization and rounding */ +#define __builtin_roundnormu(x, scale) ((unsigned int)((x) + (1<<((scale)-1)))>>(scale)) +#define __builtin_roundnorm(x, scale) ((int)((x) + (1<<((scale)-1)))>>(scale)) + +#endif + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/riscv/types.h b/sw/pulp-sdk/hal/include/hal/riscv/types.h new file mode 100644 index 0000000..aa93e32 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/riscv/types.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_TYPES_H__ +#define __HAL_TYPES_H__ + + +typedef signed short v2s __attribute__((vector_size (4))); +typedef unsigned short v2u __attribute__((vector_size (4))); + +typedef signed char v4s __attribute__((vector_size (4))); +typedef unsigned char v4u __attribute__((vector_size (4))); + +typedef signed char v4qi __attribute__((vector_size (4))); +typedef unsigned char v4qu __attribute__((vector_size (4))); + +typedef signed short v2hi __attribute__((vector_size (4))); +typedef unsigned short v2hu __attribute__((vector_size (4))); + + + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/rom/rom_v2.h b/sw/pulp-sdk/hal/include/hal/rom/rom_v2.h new file mode 100644 index 0000000..e56806b --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/rom/rom_v2.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_ROM_ROM_V2_H__ +#define __HAL_ROM_ROM_V2_H__ + +#include + +typedef struct { + uint32_t start; + uint32_t ptr; + uint32_t size; + uint32_t blocks; +} flash_v2_mem_area_t; + +typedef struct { + uint32_t nextDesc; + uint32_t nbAreas; + uint32_t entry; + uint32_t bootaddr; +} flash_v2_header_t; + +typedef struct { + uint32_t chipID; + uint32_t nbBinaries; + uint32_t ptrBinaries[6]; +} flash_v3_header_t; + +typedef struct { + uint32_t checksum; + uint32_t nbAreas; + uint32_t entry; + uint32_t bootaddr; + flash_v2_mem_area_t memArea[16]; +} binary_v3_desc_t; + +typedef struct { + flash_v2_header_t header; + flash_v2_mem_area_t area; +} flash_v2_header_single_t; + +#define FLASH_BLOCK_SIZE_LOG2 12 +#define FLASH_BLOCK_SIZE (1<= 32) { + reg = msbReg; + evt -= 32; + } else { + reg = lsbReg; + } + soc_eu_eventMask_set(reg, soc_eu_eventMask_get(reg) & ~(1 << evt)); +} + +static inline void soc_eu_eventMask_clearEvent(int evt, unsigned int lsbReg, unsigned int msbReg) { + unsigned int reg; + if (evt >= 32) { + reg = msbReg; + evt -= 32; + } else { + reg = lsbReg; + } + soc_eu_eventMask_set(reg, soc_eu_eventMask_get(reg) | (1 << evt)); +} + +static inline void soc_eu_fcEventMask_setEvent(int evt) { + soc_eu_eventMask_setEvent(evt, SOC_FC_MASK_LSB, SOC_FC_MASK_MSB); +} + +static inline void soc_eu_prEventMask_setEvent(int evt) { + soc_eu_eventMask_setEvent(evt, SOC_PR_MASK_LSB, SOC_PR_MASK_MSB); +} + +static inline void soc_eu_clEventMask_setEvent(int clusterId, int evt) { + soc_eu_eventMask_setEvent(evt, SOC_CL_MASK_LSB, SOC_CL_MASK_MSB); +} + +static inline void soc_eu_fcEventMask_clearEvent(int evt) { + soc_eu_eventMask_clearEvent(evt, SOC_FC_MASK_LSB, SOC_FC_MASK_MSB); +} + +static inline void soc_eu_prEventMask_clearEvent(int evt) { + soc_eu_eventMask_clearEvent(evt, SOC_PR_MASK_LSB, SOC_PR_MASK_MSB); +} + +static inline void soc_eu_clEventMask_clearEvent(int clusterId, int evt) { + soc_eu_eventMask_clearEvent(evt, SOC_CL_MASK_LSB, SOC_CL_MASK_MSB); +} + + + +static inline void soc_eu_genEventMask(unsigned int mask) { + pulp_write32(ARCHI_SOC_EU_ADDR + SOC_EU_EVENT, mask); +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/soc_eu/soc_eu_v2.h b/sw/pulp-sdk/hal/include/hal/soc_eu/soc_eu_v2.h new file mode 100644 index 0000000..67974fc --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/soc_eu/soc_eu_v2.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_SOC_EU_SOC_EU_V2_H__ +#define __HAL_SOC_EU_SOC_EU_V2_H__ + +#include "archi/pulp.h" +#include "archi/soc_eu/soc_eu_v2.h" + +static inline unsigned int hal_soc_eu_addr(void) +{ + return ARCHI_SOC_EU_ADDR; +} + + +static inline void soc_eu_eventMask_set(unsigned int reg, unsigned int value) { + pulp_write32(ARCHI_SOC_EU_ADDR + reg, value); +} + +static inline unsigned int soc_eu_eventMask_get(unsigned int reg) { + return pulp_read32(ARCHI_SOC_EU_ADDR + reg); +} + +static inline void soc_eu_eventMask_reset(unsigned int first_reg) { + for (int i=0; ipower_domains[domain] = state; +} + +static void tb_checker_send_assert(tb_checker_t *checker, uint32_t delay) +{ + checker->delay = delay; + hal_compiler_barrier(); + checker->request = TB_CHECKER_REQ_POWER_DOMAIN_STATE_ASSERT; + hal_compiler_barrier(); + + apb_soc_jtag_reg_write(3<<1); +} + +static int tb_checker_wait_reply(tb_checker_t *checker) +{ + // Wait until we get the reply + while(*(volatile uint32_t *)&checker->request != TB_CHECKER_REQ_NONE); + + apb_soc_jtag_reg_write(1<<1); + while((apb_soc_jtag_reg_ext(apb_soc_jtag_reg_read()) >> 1) != 3); + + // And propagate the request result + return checker->result; +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/timer/timer_v1.h b/sw/pulp-sdk/hal/include/hal/timer/timer_v1.h new file mode 100644 index 0000000..9f8ec00 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/timer/timer_v1.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_TIMER_TIMER_V1_H__ +#define __HAL_TIMER_TIMER_V1_H__ + +#include "archi/pulp.h" + +#define START_TIME_ADDR (ARCHI_TIMER_ADDR + 0x0) +#define STOP_TIME_ADDR (ARCHI_TIMER_ADDR + 0x04) +#define RESET_TIME_ADDR (ARCHI_TIMER_ADDR + 0x08) +#define GET_TIME_LO_ADDR (ARCHI_TIMER_ADDR + 0x0C) +#define GET_TIME_HI_ADDR (ARCHI_TIMER_ADDR + 0x10) + +#define START_TIME_T0_ADDR (ARCHI_TIMER_ADDR + 0x40) +#define STOP_TIME_T0_ADDR (ARCHI_TIMER_ADDR + 0x44) +#define RESET_TIME_T0_ADDR (ARCHI_TIMER_ADDR + 0x48) +#define GET_TIME_T0_ADDR (ARCHI_TIMER_ADDR + 0x4C) +#define START_TIME_T1_ADDR (ARCHI_TIMER_ADDR + 0x80) +#define STOP_TIME_T1_ADDR (ARCHI_TIMER_ADDR + 0x84) +#define RESET_TIME_T1_ADDR (ARCHI_TIMER_ADDR + 0x88) +#define GET_TIME_T1_ADDR (ARCHI_TIMER_ADDR + 0x8C) +#define START_TIME_T2_ADDR (ARCHI_TIMER_ADDR + 0xC0) +#define STOP_TIME_T2_ADDR (ARCHI_TIMER_ADDR + 0xC4) +#define RESET_TIME_T2_ADDR (ARCHI_TIMER_ADDR + 0xC8) +#define GET_TIME_T2_ADDR (ARCHI_TIMER_ADDR + 0xCC) +#define START_TIME_T3_ADDR (ARCHI_TIMER_ADDR + 0x100) +#define STOP_TIME_T3_ADDR (ARCHI_TIMER_ADDR + 0x104) +#define RESET_TIME_T3_ADDR (ARCHI_TIMER_ADDR + 0x108) +#define GET_TIME_T3_ADDR (ARCHI_TIMER_ADDR + 0x10C) + +#define GET_TIMER_ADDR(t) (ARCHI_TIMER_ADDR + ((t)+1)*0x40) + +static inline void start_core_timer(int timernum) { + *(volatile int*)(GET_TIMER_ADDR(timernum) + 0x0) = 1; +} + +static inline void stop_core_timer(int timernum) { + *(volatile int*)(GET_TIMER_ADDR(timernum) + 0x4) = 1; +} + +static inline void reset_core_timer(int timernum) { + *(volatile int*)(GET_TIMER_ADDR(timernum) + 0x8) = 1; +} + +static inline int get_core_time(int timernum) { + return *(volatile int*)(GET_TIMER_ADDR(timernum) + 0xc); +} + +static inline void set_core_time(int timernum,int timerval) { + *(volatile int*)(GET_TIMER_ADDR(timernum) + 0xc) = timerval; +} + +static inline void plp_timer_fire(int timer) +{ + start_core_timer(timer); + reset_core_timer(timer); +} + +static inline void plp_timer_compare_set(int timer, int cmpVal) +{ + set_core_time(timer, cmpVal); +} + +static inline void plp_timer_compare_unset(int timer) +{ + set_core_time(timer, 0); +} + +static inline void plp_timer_update(int timer, int cmpVal) +{ + set_core_time(timer, cmpVal); +} + +static inline void plp_timer_cancel(int timer) +{ + stop_core_timer(timer); +} + +static inline unsigned int plp_timer_cycles(int timer) +{ + return get_core_time(timer); +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/timer/timer_v2.h b/sw/pulp-sdk/hal/include/hal/timer/timer_v2.h new file mode 100644 index 0000000..d3defae --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/timer/timer_v2.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna and + * GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_TIMER_TIMER_V2_H__ +#define __HAL_TIMER_TIMER_V2_H__ + +#include "hal/pulp.h" +#include "archi/timer/timer_v2.h" + + +#ifdef ARCHI_HAS_FC + +static inline unsigned int timer_base_fc(int id, int sub_id) +{ + return ARCHI_FC_TIMER_ADDR + id * ARCHI_FC_TIMER_SIZE + sub_id * 4; +} + +#else + +#define timer_base_fc(id,sub_id) timer_base_cl(0,id,sub_id) + +#endif + + +#ifdef ARCHI_HAS_CLUSTER + +static inline unsigned int timer_base_cl(int cid, int id, int sub_id) +{ + return ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_TIMER_OFFSET + id * ARCHI_TIMER_SIZE + sub_id * 4; +} + +#endif + + +static inline unsigned int timer_conf_get(unsigned int addr) +{ + return timer_cfg_lo_get(addr); +} + + +static inline void timer_conf_set(unsigned int addr, unsigned int value) +{ + timer_cfg_lo_set(addr, value); +} + + +static inline unsigned int timer_count_get(unsigned int addr) +{ + return timer_cnt_lo_get(addr); +} + + +static inline void timer_count_set(unsigned int addr, unsigned int value) +{ + timer_cnt_lo_set(addr, value); +} + + +static inline unsigned int timer_cmp_get(unsigned int addr) +{ + return timer_cmp_lo_get(addr); +} + + +static inline void timer_cmp_set(unsigned int addr, unsigned int cmp) +{ + timer_cmp_lo_set(addr, cmp); +} + + +static inline void timer_reset(unsigned int addr) +{ + timer_reset_lo_set(addr, 1); +} + + +static inline void timer_start(unsigned int addr) +{ + timer_start_lo_set(addr, 1); +} + + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/tryx/tryx_v1.h b/sw/pulp-sdk/hal/include/hal/tryx/tryx_v1.h new file mode 100644 index 0000000..b50134b --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/tryx/tryx_v1.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_TRYX_V1_H__ +#define __HAL_TRYX_V1_H__ + +#include "archi/pulp.h" + +#define DEBUG_TRYX 0 +#define EVTMASK_RAB_WAKEUP ( (unsigned)(1 << ARCHI_EVT_RAB_WAKEUP) ) + +/** Check if the TRYX register contains a slave error. + + \return 0 if there is no slave error; 1 if there is a slave error. + */ +static inline int pulp_tryx_has_slverr() +{ + return (*(const volatile unsigned int*)ARCHI_TRYX_ADDR & 0x1) == 0x1; +} + +/** Set the TRYX register such that (1) the next memory access does not go from RAB further down + the memory hierarchy, and (2) a (possible) RAB miss caused by the next memory access is + flagged as prefetch in the RAB miss FIFO. + */ +static inline void pulp_tryx_set_prefetch() +{ + *(volatile unsigned int*)ARCHI_TRYX_ADDR = 0xFFFFFFFF; +} + +/** Try to read from a memory address without blocking in case it produces a slave error. + + \param addr The address that shall be read. + \param val The value in which the result shall be stored if the read is successful. + + \return 0 if the read was successful; 1 if the read caused a slave error. + */ +static inline int pulp_tryread_noblock(const unsigned int* const addr, unsigned int* const val) +{ + *val = *(const volatile unsigned*)addr; + return pulp_tryx_has_slverr(); +} + +/** Try to write to a memory address without blocking in case it produces a slave error. + + \param addr The address to which data shall be written. + \param val The value that shall be written. + + \return 0 if the write was successful; 1 if the write caused a slave error. + */ +static inline int pulp_trywrite_noblock(unsigned int* const addr, const unsigned int val) +{ + *addr = val; + return pulp_tryx_has_slverr(); +} + +/** Go to sleep and wait for wake-up event. + */ +void pulp_tryx_slowpath(); + +/** Read from an address and block until the read completes. + + \param addr The address that shall be read. + + \return The data stored at that address. + */ +static inline unsigned int pulp_tryread(const unsigned int* const addr) +{ + unsigned int val; + + int miss = pulp_tryread_noblock(addr, &val); + while (miss) { + pulp_tryx_slowpath(); + miss = pulp_tryread_noblock(addr, &val); + } + + return val; +} + +/** Try to read from a memory address without blocking in case it misses in the RAB and without + causing a memory transaction. This function can be used to trigger the setup of a RAB slice + in advance of a read. + + \param addr The address that shall be read-prefetched. + + \return 0 if the read would succeed (i.e., a slice in the RAB exists for this address); 1 if + the read resulted in a RAB miss; negative value with an errno on errors. + */ +static inline int pulp_tryread_prefetch(const unsigned int* const addr) +{ + #if DEBUG_TRYX == 1 + printf("read-prefetch of address 0x%X\n",(unsigned)addr); + #endif + + pulp_tryx_set_prefetch(); + + // Issue a read through RAB. + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wunused-but-set-variable" + const volatile unsigned int dummy = *(volatile unsigned int*)addr; + #pragma GCC diagnostic pop + + if (pulp_tryx_has_slverr()) { + #if DEBUG_TRYX == 1 + printf("miss on address 0x%X\n",(unsigned)addr); + #endif + return 1; + } + + return 0; +} + +/** Write to an address and block until the write completes. + + \param addr The address to which data shall be written. + \param val The value that shall be written. + */ +static inline void pulp_trywrite(unsigned int* const addr, const unsigned int val) +{ + int miss = pulp_trywrite_noblock(addr, val); + while (miss) { + pulp_tryx_slowpath(); + miss = pulp_trywrite_noblock(addr, val); + } + + return; +} + +/** Try to write to a memory address without blocking in case it misses in the RAB and without + causing a memory transaction. This function can be used to trigger the setup of a RAB slice + in advance of a write. + + \param addr The address that shall be write-prefetched. + + \return 0 if the write would succeed (i.e., a slice in the RAB exists for this address); 1 if + the write resulted in a RAB miss; negative value with an errno on errors. + */ +static inline int pulp_trywrite_prefetch(unsigned int* const addr) +{ + #if DEBUG_TRYX == 1 + printf("write-prefetch of address 0x%X\n",(unsigned)addr); + #endif + + pulp_tryx_set_prefetch(); + + // Issue a write through RAB (to be discarded). + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wunused-but-set-variable" + *(volatile unsigned int*)addr = 0x5000BAD1; + #pragma GCC diagnostic pop + + if (pulp_tryx_has_slverr()) { + #if DEBUG_TRYX == 1 + printf("miss on address 0x%X\n",(unsigned)addr); + #endif + return 1; + } + + return 0; +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/udma/cpi/udma_cpi_v1.h b/sw/pulp-sdk/hal/include/hal/udma/cpi/udma_cpi_v1.h new file mode 100644 index 0000000..ce8e107 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/cpi/udma_cpi_v1.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_CPI_V1_H__ +#define __HAL_UDMA_UDMA_CPI_V1_H__ + +#include "archi/udma/cpi/udma_cpi_v1_old.h" + +#define UDMA_CAM_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_CAM_ID(id)) + +#define UDMA_CAM_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_CAM_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_CAM_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_CAM_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) +#define ARCHI_SOC_EVENT_CAM_RX(id) ARCHI_SOC_EVENT_UDMA_RX(ARCHI_UDMA_CAM_ID(id)) + + +// UDMA RX/TX Channels HAL Registers Structure +typedef struct { + uint32_t rx_ch_saddr; + uint32_t rx_ch_size; + uint32_t rx_ch_cfg; + uint32_t rx_ch_initcfg_unused; + uint32_t tx_ch_saddr; + uint32_t tx_ch_size; + uint32_t tx_ch_cfg; + uint32_t tx_ch_initcfg_unused; +} plpUdmaRxTxChHandle2_t; + +// CAM HAL Registers Structure +typedef struct { + plpUdmaRxTxChHandle2_t udma_rxtx_ch_handle; + uint32_t cfg_glob; + uint32_t cfg_ll; + uint32_t cfg_ur; + uint32_t cfg_size; + uint32_t cfg_filter; +} plpUdmaCameraHandle_t; + +// CAM HAL Register Fields Structure +typedef struct { + uint32_t framedrop_enable:1; + uint32_t framedrop_value:6; + uint32_t frameslice_enable:1; + uint32_t format:3; + uint32_t shift:4; + uint32_t unused:16; + uint32_t enable:1; +} __attribute__ ((packed)) plpUdmaCamCfgGlob_t; + +typedef struct { + uint32_t frameslice_llx:16; + uint32_t frameslice_lly:16; +} __attribute__ ((packed)) plpUdmaCamCfgLl_t; + +typedef struct { + uint32_t frameslice_urx:16; + uint32_t frameslice_ury:16; +} __attribute__ ((packed)) plpUdmaCamCfgUr_t; + +typedef struct { + uint32_t unused:16; + uint32_t row_length:16; +} __attribute__ ((packed)) plpUdmaCamCfgSize_t; + +typedef struct { + uint32_t b_coeff:8; + uint32_t g_coeff:8; + uint32_t r_coeff:8; + uint32_t unused:8; +} __attribute__ ((packed)) plpUdmaCamCfgFilter_t; + +// CAM HAL Register Union definition +typedef union { + plpUdmaCamCfgGlob_t cfg_glob; + plpUdmaCamCfgLl_t cfg_ll; + plpUdmaCamCfgUr_t cfg_ur; + plpUdmaCamCfgSize_t cfg_size; + plpUdmaCamCfgFilter_t cfg_filter; + uint32_t raw; +} __attribute__ ((packed)) plpUdmaCamCustom_u; + +static inline void hal_cpi_ll_set(int cpi, unsigned int value){ + pulp_write32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_LL_OFFSET, value); +} +static inline unsigned int hal_cpi_ll_read(int cpi){ + return pulp_read32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_LL_OFFSET); +} +static inline void hal_cpi_ur_set(int cpi, unsigned int value){ + pulp_write32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_UR_OFFSET, value); +} +static inline unsigned int hal_cpi_ur_read(int cpi){ + return pulp_read32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_UR_OFFSET); +} +static inline void hal_cpi_size_set(int cpi, unsigned int value){ + pulp_write32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_SIZE_OFFSET, value); +} +static inline unsigned int hal_cpi_size_read(int cpi){ + return pulp_read32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_SIZE_OFFSET); +} +static inline void hal_cpi_glob_set(int cpi, unsigned int value){ + pulp_write32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_GLOB_OFFSET, value); +} +static inline unsigned int hal_cpi_glob_read(int cpi){ + return pulp_read32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_GLOB_OFFSET); +} +static inline void hal_cpi_filter_set(int cpi, unsigned int value){ + pulp_write32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_FILTER_OFFSET, value); +} +static inline unsigned int hal_cpi_filter_read(int cpi){ + return pulp_read32(UDMA_CAM_CUSTOM_ADDR(cpi) + CAM_FILTER_OFFSET); +} + +/////////////////////////////////////////////////// +// TODO Obsolete : to be removed cause deprecated +static inline void plp_cam_glob_set(int enabled, int frameDropEn, int nbFrameDrop, int frameSliceEn, int format, int shift) +{ + unsigned int value = (enabled << CAM_CFG_GLOB_EN_BIT) | (frameDropEn << CAM_CFG_GLOB_FRAMEDROP_EN_BIT) | (nbFrameDrop << CAM_CFG_GLOB_FRAMEDROP_VAL_BIT) | (format << CAM_CFG_GLOB_FORMAT_BIT) | (shift << CAM_CFG_GLOB_SHIFT_BIT); + pulp_write32(ARCHI_UDMA_ADDR + UDMA_CAM_OFFSET(0) + UDMA_CHANNEL_CUSTOM_OFFSET + CAM_GLOB_OFFSET, value); +} + +// CAM HAL Handle +#define CAM_HANDLE(id) ((plpUdmaCameraHandle_t *)(ARCHI_UDMA_ADDR + UDMA_CAM_OFFSET(id))) + +// CAM HAL functions prototype +static inline void plpUdmaCamGlobSet (plpUdmaCameraHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaCamGlobGet (plpUdmaCameraHandle_t * const handle); +static inline void plpUdmaCamLlSet (plpUdmaCameraHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaCamLlGet (plpUdmaCameraHandle_t * const handle); +static inline void plpUdmaCamUrSet (plpUdmaCameraHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaCamUrGet (plpUdmaCameraHandle_t * const handle); +static inline void plpUdmaCamSizeSet (plpUdmaCameraHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaCamSizeGet (plpUdmaCameraHandle_t * const handle); +static inline void plpUdmaCamFilterSet (plpUdmaCameraHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaCamFilterGet (plpUdmaCameraHandle_t * const handle); + +// CAM HAL functions definition +static inline void plpUdmaCamGlobSet (plpUdmaCameraHandle_t * const handle, uint32_t data) { + handle->cfg_glob = data; +} + +static inline uint32_t plpUdmaCamGlobGet (plpUdmaCameraHandle_t * const handle) { + return handle->cfg_glob; +} + +static inline void plpUdmaCamLlSet (plpUdmaCameraHandle_t * const handle, uint32_t data) { + handle->cfg_ll = data; +} + +static inline uint32_t plpUdmaCamLlGet (plpUdmaCameraHandle_t * const handle) { + return handle->cfg_ll; +} + +static inline void plpUdmaCamUrSet (plpUdmaCameraHandle_t * const handle, uint32_t data) { + handle->cfg_ur = data; +} + +static inline uint32_t plpUdmaCamUrGet (plpUdmaCameraHandle_t * const handle) { + return handle->cfg_ur; +} + +static inline void plpUdmaCamSizeSet (plpUdmaCameraHandle_t * const handle, uint32_t data) { + handle->cfg_size = data; +} + +static inline uint32_t plpUdmaCamSizeGet (plpUdmaCameraHandle_t * const handle) { + return handle->cfg_size; +} + +static inline void plpUdmaCamFilterSet (plpUdmaCameraHandle_t * const handle, uint32_t data) { + handle->cfg_filter = data; +} + +static inline uint32_t plpUdmaCamFilterGet (plpUdmaCameraHandle_t * const handle) { + return handle->cfg_filter; +} + +/////////////////////////////////////////////////// + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/csi2/udma_csi2_v1.h b/sw/pulp-sdk/hal/include/hal/udma/csi2/udma_csi2_v1.h new file mode 100644 index 0000000..274cc24 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/csi2/udma_csi2_v1.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_CSI2_V1_H__ +#define __HAL_UDMA_UDMA_CSI2_V1_H__ + +#include "archi/udma/csi2/udma_csi2_v1.h" + +#define UDMA_CSI2_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_CSI2_ID(id)) + +#define UDMA_CSI2_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_CSI2_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_CSI2_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_CSI2_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) +// NOTE defined in archi/vega/properties.h +// #define ARCHI_SOC_EVENT_CSI2_RX(id) ARCHI_SOC_EVENT_UDMA_RX(ARCHI_UDMA_CSI2_ID(id)) + +// CSI2 HAL Registers Structure +struct plpUdmaCsi2_struct_t { + plpUdmaRxTxChHandle_t udma_rxtx_ch_handle; + uint32_t unused; + uint32_t cfg_clk; +}; +typedef volatile struct plpUdmaCsi2_struct_t plpUdmaCsi2Handle_t; + +// CSI2 HAL Handle +// located in "archi/chip/vega/memory_map.h" + +// CSI2 HAL functions prototype +static inline void plpUdmaCsi2ClkCfgSet (plpUdmaCsi2Handle_t * handle, uint32_t data); +static inline uint32_t plpUdmaCsi2ClkCfgGet (plpUdmaCsi2Handle_t * handle); + +// CSI2 HAL functions definition +static inline void plpUdmaCsi2ClkCfgSet (plpUdmaCsi2Handle_t * handle, uint32_t data) { + handle->cfg_clk = data; +} + +static inline uint32_t plpUdmaCsi2ClkCfgGet (plpUdmaCsi2Handle_t * handle) { + return handle->cfg_clk; +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/hyper/udma_hyper_v1.h b/sw/pulp-sdk/hal/include/hal/udma/hyper/udma_hyper_v1.h new file mode 100644 index 0000000..b7374fb --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/hyper/udma_hyper_v1.h @@ -0,0 +1,589 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_PERIPH_HYPER_V1_H__ +#define __HAL_UDMA_UDMA_PERIPH_HYPER_V1_H__ + +#include + +#define UDMA_HYPER_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_HYPER_ID(id)) +#define UDMA_HYPER_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_HYPER_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET) +#define UDMA_HYPER_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) +#define ARCHI_SOC_EVENT_HYPER_RX(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_HYPER_ID(id)) + ARCHI_UDMA_HYPER_RX_EVT) +#define ARCHI_SOC_EVENT_HYPER_TX(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_HYPER_ID(id)) + ARCHI_UDMA_HYPER_TX_EVT) + +#include "archi/udma/hyper/udma_hyper_v1.h" +/* + * set Hyper IP ext_addr configuration with value + */ +static inline void hal_hyper_udma_ext_addr_set(unsigned int value) +{ + pulp_write32(HYPER_EXT_ADDR, value & HYPER_EXT_ADDR_MASK); +} + +/* + * get Hyper IP configuration ext_addr value + */ +static inline unsigned int hal_hyper_udma_ext_addr_get() +{ + return (unsigned int)pulp_read32(HYPER_EXT_ADDR); +} + +/* + * set Hyper IP configuration mem_cfg0 + */ +static inline void hal_hyper_udma_mem_cfg0_set(unsigned short value) +{ + pulp_write32(HYPER_MEM_CFG0, value & HYPER_MEM_CFG0_MASK); +} + +/* + * get Hyper IP configuration mem_cfg0 value + */ +static inline unsigned short hal_hyper_udma_mem_cfg0_get() +{ + return (unsigned short) (pulp_read32(HYPER_MEM_CFG0) & HYPER_MEM_CFG0_MASK); +} + +/* + * set Hyper IP configuration mem_cfg1 + */ +static inline void hal_hyper_udma_mem_cfg1_set(unsigned int value) +{ + pulp_write32(HYPER_MEM_CFG1, value & HYPER_MEM_CFG1_MASK); +} + +/* + * get Hyper IP configuration mem_cfg1 value + */ +static inline unsigned int hal_hyper_udma_mem_cfg1_get() +{ + return (unsigned int) (pulp_read32(HYPER_MEM_CFG1) & HYPER_MEM_CFG1_MASK); +} + +/* + * set Hyper IP configuration mem_cfg2 with value + */ +static inline void hal_hyper_udma_mem_cfg2_set(unsigned int value) +{ + pulp_write32(HYPER_MEM_CFG2, value & HYPER_MEM_CFG2_MASK); +} + +/* + * get Hyper IP configuration mem_cfg2 value + */ +static inline unsigned int hal_hyper_udma_mem_cfg2_get() +{ + return (unsigned int) (pulp_read32(HYPER_MEM_CFG2) & HYPER_MEM_CFG2_MASK); +} + +/* + * set Hyper IP configuration mem_cfg3 with value + */ +static inline void hal_hyper_udma_mem_cfg3_set(unsigned short value) +{ + pulp_write32(HYPER_MEM_CFG3, value & HYPER_MEM_CFG3_MASK); +} + +/* + * get Hyper IP configuration mem_cfg3 value + */ +static inline unsigned short hal_hyper_udma_mem_cfg3_get() +{ + return (unsigned short) (pulp_read32(HYPER_MEM_CFG3) & HYPER_MEM_CFG3_MASK); +} + +/* + * set Hyper IP configuration mem_cfg4 with value + */ +static inline void hal_hyper_udma_mem_cfg4_set(unsigned short value) +{ + pulp_write32(HYPER_MEM_CFG4, value & HYPER_MEM_CFG4_MASK); +} + +/* + * get Hyper IP configuration mem_cfg4 value + */ +static inline unsigned short hal_hyper_udma_mem_cfg4_get() +{ + return (unsigned short) (pulp_read32(HYPER_MEM_CFG4) & HYPER_MEM_CFG4_MASK); +} + +/* + * set Hyper IP configuration mem_cfg5 with value + */ +static inline void hal_hyper_udma_mem_cfg5_set(unsigned int value) +{ + pulp_write32(HYPER_MEM_CFG5, value & HYPER_MEM_CFG5_MASK); +} + +/* + * get Hyper IP configuration mem_cfg5 value + */ +static inline unsigned int hal_hyper_udma_mem_cfg5_get() +{ + return (unsigned int) (pulp_read32(HYPER_MEM_CFG5) & HYPER_MEM_CFG5_MASK); +} + +/* + * set Hyper IP configuration mem_cfg6 with value + */ +static inline void hal_hyper_udma_mem_cfg6_set(unsigned int value) +{ + pulp_write32(HYPER_MEM_CFG6, value & HYPER_MEM_CFG6_MASK); +} + +/* + * get Hyper IP configuration mem_cfg6 value + */ +static inline unsigned int hal_hyper_udma_mem_cfg6_get() +{ + return (unsigned int) (pulp_read32(HYPER_MEM_CFG6) & HYPER_MEM_CFG6_MASK); +} + +/* + * set Hyper IP configuration mem_cfg7 with value + */ +static inline void hal_hyper_udma_mem_cfg7_set(unsigned char value) +{ + pulp_write32(HYPER_MEM_CFG7, value & HYPER_MEM_CFG7_MASK); +} + +/* + * get Hyper IP configuration mem_cfg7 value + */ +static inline unsigned char hal_hyper_udma_mem_cfg7_get() +{ + return (unsigned char) (pulp_read32(HYPER_MEM_CFG7) & HYPER_MEM_CFG7_MASK); +} + +/* + * set write read address for both ram and flash + * address[31:24] + * mbr1 <= mbr0, always select csn0 + * mbr0 <= addr < mbr1, chip select csn0 + * mbr1 <= addr, chip select csn1 + */ +static inline void hal_hyper_udma_addr_set(unsigned int addr) +{ + hal_hyper_udma_ext_addr_set(addr); +} + +/* + * set hyper0 base address + */ +static inline void hal_hyper_udma_mbr0_set(unsigned char mbr0) +{ + hal_hyper_udma_mem_cfg0_set((hal_hyper_udma_mem_cfg0_get() + & HYPER_MEM_CFG0_MBR0_MASK_BYTE) + | (mbr0 << HYPER_MEM_CFG0_MBR0_OFFSET)); +} + +/* + * set hyper0 latency + */ +static inline void hal_hyper_udma_latency0_set(unsigned char latency0) +{ + hal_hyper_udma_mem_cfg0_set((hal_hyper_udma_mem_cfg0_get() + & HYPER_MEM_CFG0_LATENCY0_MASK_HB) + | (latency0 << HYPER_MEM_CFG0_LATENCY0_OFFSET)); +} + +/* + * set hyper0 wrap size + */ +static inline void hal_hyper_udma_wrap_size0_set(unsigned char wrapsize) +{ + hal_hyper_udma_mem_cfg0_set((hal_hyper_udma_mem_cfg0_get() + & HYPER_MEM_CFG0_WRAP_SIZE0_MASK_TB) + | (wrapsize << HYPER_MEM_CFG0_WRAP_SIZE0_OFFSET)); +} + +/* + * set hyper0 rd cshi + */ +static inline void hal_hyper_udma_rd_cshi0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg1_set((hal_hyper_udma_mem_cfg1_get() + & HYPER_MEM_CFG1_RD_CSHI0_MASK_HB) + | (value << HYPER_MEM_CFG1_RD_CSHI0_OFFSET)); +} + +/* + * set hyper0 rd css + */ +static inline void hal_hyper_udma_rd_css0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg1_set((hal_hyper_udma_mem_cfg1_get() + & HYPER_MEM_CFG1_RD_CSS0_MASK_HB) + | (value << HYPER_MEM_CFG1_RD_CSS0_OFFSET)); +} + +/* + * set hyper0 rd csh + */ +static inline void hal_hyper_udma_rd_csh0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg1_set((hal_hyper_udma_mem_cfg1_get() + & HYPER_MEM_CFG1_RD_CSH0_MASK_HB) + | (value << HYPER_MEM_CFG1_RD_CSH0_OFFSET)); +} + + +/* + * set hyper0 wr cshi + */ +static inline void hal_hyper_udma_wr_cshi0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg1_set((hal_hyper_udma_mem_cfg1_get() + & HYPER_MEM_CFG1_WR_CSHI0_MASK_HB) + | (value << HYPER_MEM_CFG1_WR_CSHI0_OFFSET)); +} + +/* + * set hyper0 wr css + */ +static inline void hal_hyper_udma_wr_css0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg1_set((hal_hyper_udma_mem_cfg1_get() + & HYPER_MEM_CFG1_WR_CSS0_MASK_HB) + | (value << HYPER_MEM_CFG1_WR_CSS0_OFFSET)); +} + +/* + * set hyper0 wr csh + */ +static inline void hal_hyper_udma_wr_csh0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg1_set((hal_hyper_udma_mem_cfg1_get() + & HYPER_MEM_CFG1_WR_CSH0_MASK_HB) + | (value << HYPER_MEM_CFG1_WR_CSH0_OFFSET)); +} + +/* + * set hyper0 rd max length + */ +static inline void hal_hyper_udma_rd_max_length0_set(unsigned short value) +{ + hal_hyper_udma_mem_cfg2_set((hal_hyper_udma_mem_cfg2_get() + & HYPER_MEM_CFG2_RD_MAX_LENGTH0_MASK_NB) + | (value << HYPER_MEM_CFG2_RD_MAX_LENGTH0_OFFSET)); +} + +/* + * set hyper0 wr max length + */ +static inline void hal_hyper_udma_wr_max_length0_set(unsigned short value) +{ + hal_hyper_udma_mem_cfg2_set((hal_hyper_udma_mem_cfg2_get() + & HYPER_MEM_CFG2_WR_MAX_LENGTH0_MASK_NB) + | (value << HYPER_MEM_CFG2_WR_MAX_LENGTH0_OFFSET)); +} + +/* + * set hyper0 acs0 + */ +static inline void hal_hyper_udma_acs0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg3_set((hal_hyper_udma_mem_cfg3_get() + & HYPER_MEM_CFG3_ACS0_MASK_B) + | (value << HYPER_MEM_CFG3_ACS0_OFFSET)); +} + +/* + * set hyper0 tco0 + */ +static inline void hal_hyper_udma_tco0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg3_set((hal_hyper_udma_mem_cfg3_get() + & HYPER_MEM_CFG3_TCO0_MASK_B) + | (value << HYPER_MEM_CFG3_TCO0_OFFSET)); +} + +/* + * set hyper0 dt0 + */ +static inline void hal_hyper_udma_dt0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg3_set((hal_hyper_udma_mem_cfg3_get() + & HYPER_MEM_CFG3_DT0_MASK_B) + | (value << HYPER_MEM_CFG3_DT0_OFFSET)); +} + +/* + * set hyper0 crt + */ +static inline void hal_hyper_udma_crt0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg3_set((hal_hyper_udma_mem_cfg3_get() + & HYPER_MEM_CFG3_CRT0_MASK_B) + | (value << HYPER_MEM_CFG3_CRT0_OFFSET)); +} + + +/* + * set hyper0 rd max len en + */ +static inline void hal_hyper_udma_rd_maxlen_en0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg3_set((hal_hyper_udma_mem_cfg3_get() + & HYPER_MEM_CFG3_RD_MAX_LEN_EN0_MASK_B) + | (value << HYPER_MEM_CFG3_RD_MAX_LEN_EN0_OFFSET)); +} + + +/* + * set hyper0 wr max len en + */ +static inline void hal_hyper_udma_wr_maxlen_en0_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg3_set((hal_hyper_udma_mem_cfg3_get() + & HYPER_MEM_CFG3_WR_MAX_LEN_EN0_MASK_B) + | (value << HYPER_MEM_CFG3_WR_MAX_LEN_EN0_OFFSET)); +} + +/* + * set hyper0 rds delay adj + */ +static inline void hal_hyper_udma_rds_delay_adj_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg3_set((hal_hyper_udma_mem_cfg3_get() + & HYPER_MEM_CFG3_RDS_DELAY_ADJ_MASK_THB) + | (value << HYPER_MEM_CFG3_RDS_DELAY_ADJ_OFFSET)); +} + +/* + * set hyper1 base address + */ +static inline void hal_hyper_udma_mbr1_set(unsigned char mbr1) +{ + hal_hyper_udma_mem_cfg4_set((hal_hyper_udma_mem_cfg4_get() + & HYPER_MEM_CFG4_MBR1_MASK_BYTE) + | (mbr1 << HYPER_MEM_CFG4_MBR1_OFFSET)); +} + +/* + * set hyper1 wrap size + */ +static inline void hal_hyper_udma_wrap_size1_set(unsigned char wrapsize) +{ + hal_hyper_udma_mem_cfg4_set((hal_hyper_udma_mem_cfg4_get() + & HYPER_MEM_CFG4_WRAP_SIZE1_MASK_TB) + | (wrapsize << HYPER_MEM_CFG4_WRAP_SIZE1_OFFSET)); +} + +/* + * set hyper1 rd cshi + */ +static inline void hal_hyper_udma_rd_cshi1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg5_set((hal_hyper_udma_mem_cfg5_get() + & HYPER_MEM_CFG5_RD_CSHI1_MASK_HB) + | (value << HYPER_MEM_CFG5_RD_CSHI1_OFFSET)); +} + +/* + * set hyper1 rd css + */ +static inline void hal_hyper_udma_rd_css1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg5_set((hal_hyper_udma_mem_cfg5_get() + & HYPER_MEM_CFG5_RD_CSS1_MASK_HB) + | (value << HYPER_MEM_CFG5_RD_CSS1_OFFSET)); +} + +/* + * set hyper1 rd csh + */ +static inline void hal_hyper_udma_rd_csh1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg5_set((hal_hyper_udma_mem_cfg5_get() + & HYPER_MEM_CFG5_RD_CSH1_MASK_HB) + | (value << HYPER_MEM_CFG5_RD_CSH1_OFFSET)); +} + + +/* + * set hyper1 wr cshi + */ +static inline void hal_hyper_udma_wr_cshi1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg5_set((hal_hyper_udma_mem_cfg5_get() + & HYPER_MEM_CFG5_WR_CSHI1_MASK_HB) + | (value << HYPER_MEM_CFG5_WR_CSHI1_OFFSET)); +} + +/* + * set hyper1 wr css + */ +static inline void hal_hyper_udma_wr_css1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg5_set((hal_hyper_udma_mem_cfg5_get() + & HYPER_MEM_CFG5_WR_CSS1_MASK_HB) + | (value << HYPER_MEM_CFG5_WR_CSS1_OFFSET)); +} + +/* + * set hyper1 wr csh + */ +static inline void hal_hyper_udma_wr_csh1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg5_set((hal_hyper_udma_mem_cfg5_get() + & HYPER_MEM_CFG5_WR_CSH1_MASK_HB) + | (value << HYPER_MEM_CFG5_WR_CSH1_OFFSET)); +} + + +/* + * set hyper1 rd max length + */ +static inline void hal_hyper_udma_rd_max_length1_set(unsigned short value) +{ + hal_hyper_udma_mem_cfg6_set((hal_hyper_udma_mem_cfg6_get() + & HYPER_MEM_CFG6_RD_MAX_LENGTH1_MASK_NB) + | (value << HYPER_MEM_CFG6_RD_MAX_LENGTH1_OFFSET)); +} + +/* + * set hyper1 wr max length + */ +static inline void hal_hyper_udma_wr_max_length1_set(unsigned short value) +{ + hal_hyper_udma_mem_cfg6_set((hal_hyper_udma_mem_cfg6_get() + & HYPER_MEM_CFG6_WR_MAX_LENGTH1_MASK_NB) + | (value << HYPER_MEM_CFG6_WR_MAX_LENGTH1_OFFSET)); +} + + +/* + * set hyper1 acs1 + */ +static inline void hal_hyper_udma_acs1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg7_set((hal_hyper_udma_mem_cfg7_get() + & HYPER_MEM_CFG7_ACS1_MASK_B) + | (value << HYPER_MEM_CFG7_ACS1_OFFSET)); +} + +/* + * set hyper1 tco1 + */ +static inline void hal_hyper_udma_tco1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg7_set((hal_hyper_udma_mem_cfg7_get() + & HYPER_MEM_CFG7_TCO1_MASK_B) + | (value << HYPER_MEM_CFG7_TCO1_OFFSET)); +} + +/* + * set hyper1 dt1 + */ +static inline void hal_hyper_udma_dt1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg7_set((hal_hyper_udma_mem_cfg7_get() + & HYPER_MEM_CFG7_DT1_MASK_B) + | (value << HYPER_MEM_CFG7_DT1_OFFSET)); +} + +/* + * set hyper1 crt + */ +static inline void hal_hyper_udma_crt1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg7_set((hal_hyper_udma_mem_cfg7_get() + & HYPER_MEM_CFG7_CRT1_MASK_B) + | (value << HYPER_MEM_CFG7_CRT1_OFFSET)); +} + + +/* + * set hyper1 rd max len en + */ +static inline void hal_hyper_udma_rd_maxlen_en1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg7_set((hal_hyper_udma_mem_cfg7_get() + & HYPER_MEM_CFG7_RD_MAX_LEN_EN1_MASK_B) + | (value << HYPER_MEM_CFG7_RD_MAX_LEN_EN1_OFFSET)); +} + + +/* + * set hyper1 wr max len en + */ +static inline void hal_hyper_udma_wr_maxlen_en1_set(unsigned char value) +{ + hal_hyper_udma_mem_cfg7_set((hal_hyper_udma_mem_cfg7_get() + & HYPER_MEM_CFG7_WR_MAX_LEN_EN1_MASK_B) + | (value << HYPER_MEM_CFG7_WR_MAX_LEN_EN1_OFFSET)); +} + +/* + * Enable the clock to the whole hyper IP + * Needed prior to all other configuration of this IP + */ +static inline void hal_hyper_start_ip() +{ + plp_udma_cg_set(plp_udma_cg_get() | (1< + +#define ARCHI_UDMA_HYPER_RX_EVT 0 +#define ARCHI_UDMA_HYPER_TX_EVT 1 + +#define UDMA_HYPER_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id)) + +#define UDMA_HYPER_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_HYPER_ID(id)) +#define UDMA_HYPER_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_HYPER_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET) +#define UDMA_HYPER_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) +#define ARCHI_SOC_EVENT_HYPER_RX(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_HYPER_ID(id)) + ARCHI_UDMA_HYPER_RX_EVT) +#define ARCHI_SOC_EVENT_HYPER_TX(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_HYPER_ID(id)) + ARCHI_UDMA_HYPER_TX_EVT) + +#include "archi/udma/hyper/udma_hyper_v2.h" + +#define REG_MBR0 0 +#define REG_MBR1 0x01000000 + +static inline void hal_hyper_udma_ext_addr_set(unsigned int value) +{ + pulp_write32(UDMA_HYPER_ADDR(0) + HYPER_EXT_ADDR_OFFSET, value); +} + +static inline unsigned int hal_hyper_udma_ext_addr_get() +{ + return (unsigned int)pulp_read32(UDMA_HYPER_ADDR(0) + HYPER_EXT_ADDR_OFFSET); +} + +static inline void hal_hyper_udma_addr_set(unsigned int addr) +{ + hal_hyper_udma_ext_addr_set(addr); +} + +static inline void hal_hyper_enqueue(unsigned channelBase, unsigned int l2Addr, unsigned int ext_addr, unsigned int size, unsigned int cfg) +{ + hal_hyper_udma_ext_addr_set(ext_addr); + plp_udma_enqueue(channelBase, l2Addr, size, cfg); +} + +static inline void hal_hyper_ram_ext_addr_set(unsigned int value) +{ + return hal_hyper_udma_addr_set(REG_MBR0 | value); +} + +static inline void hal_hyper_flash_ext_addr_set(unsigned int value) +{ + return hal_hyper_udma_addr_set(REG_MBR1 | value); +} + +/* + * Hyper IP boot initialization + */ +/* + PLP_BOOT_CODE __attribute__((constructor)) void plp_hyper_ip_init() + { + plp_trace(RT_TRACE_INIT, "Hyper IP driver initialization\n"); + + plp_trace(RT_TRACE_INIT, "Hyper driver initialization done\n"); + } +*/ + +#if 0 +static inline void hal_hyper_ext_addr_set(unsigned int value) +{ + pulp_write32(ARCHI_UDMA_ADDR + HYPER_EXT_ADDR_OFFSET, value); +} + +static inline void hal_hyper_ram_ext_addr_set(unsigned int value) {return hal_hyper_ext_addr_set(REG_MBR0 | value);} + +static inline void hal_hyper_flash_ext_addr_set(unsigned int value) {return hal_hyper_ext_addr_set(REG_MBR1 | value);} + +static inline void hal_hyper_enqueue(unsigned channelBase, unsigned int l2Addr, unsigned int ext_addr, unsigned int size, unsigned int cfg) { + hal_hyper_ext_addr_set(ext_addr); + plp_udma_enqueue(channelBase, l2Addr, size, cfg); +} + +static inline void hal_hyper_ram_enqueue(unsigned channelBase, unsigned int l2Addr, unsigned int ext_addr, unsigned int size, unsigned int cfg) { + hal_hyper_ram_ext_addr_set(ext_addr); + plp_udma_enqueue(channelBase, l2Addr, size, cfg); +} + +static inline void hal_hyper_flash_enqueue(unsigned channelBase, unsigned int l2Addr, unsigned int ext_addr, unsigned int size, unsigned int cfg) { + hal_hyper_flash_ext_addr_set(ext_addr); + plp_udma_enqueue(channelBase, l2Addr, size, cfg); +} +#endif + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/udma/i2c/udma_i2c_v1.h b/sw/pulp-sdk/hal/include/hal/udma/i2c/udma_i2c_v1.h new file mode 100644 index 0000000..a2db655 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/i2c/udma_i2c_v1.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_I2C_V1_H__ +#define __HAL_UDMA_UDMA_I2C_V1_H__ + +#include "archi/udma/i2c/udma_i2c_v1.h" + +static inline uint32_t hal_udma_i2c_setup_compute(int en, int div) +{ + return (en << I2C_CMD_SETUP_ENABLE_BIT) | ( div << I2C_CMD_SETUP_DIV_BIT); +} + +static inline void hal_udma_i2c_setup_set(uint32_t periph_base, uint32_t value) +{ + pulp_write32(periph_base + UDMA_CHANNEL_CUSTOM_OFFSET + ARCHI_I2C_SETUP_OFFSET, value); +} + +static inline uint32_t hal_udma_i2c_setup_get(uint32_t periph_base) +{ + return pulp_read32(periph_base + UDMA_CHANNEL_CUSTOM_OFFSET + ARCHI_I2C_SETUP_OFFSET); +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/i2c/udma_i2c_v2.h b/sw/pulp-sdk/hal/include/hal/udma/i2c/udma_i2c_v2.h new file mode 100644 index 0000000..eb4fed0 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/i2c/udma_i2c_v2.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_I2C_V2_H__ +#define __HAL_UDMA_UDMA_I2C_V2_H__ + +#include "archi/udma/i2c/udma_i2c_v2.h" + +#define UDMA_I2C_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_I2C_ID(id)) + +#define UDMA_I2C_DATA_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_I2C_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_I2C_CMD_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_I2C_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET) +#define UDMA_I2C_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_I2C_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) +#define ARCHI_SOC_EVENT_I2C_DATA(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_I2C_ID(id)) + 0) +#define ARCHI_SOC_EVENT_I2C_CMD(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_I2C_ID(id)) + 1) + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/i2s/udma_i2s_v1.h b/sw/pulp-sdk/hal/include/hal/udma/i2s/udma_i2s_v1.h new file mode 100644 index 0000000..18ae725 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/i2s/udma_i2s_v1.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_PERIPH_I2S_V1_H__ +#define __HAL_UDMA_UDMA_PERIPH_I2S_V1_H__ + +#include "archi/udma/i2s/udma_i2s_v1.h" +#include "archi/utils.h" + +static inline void hal_i2s_ext_clk_set(int i2s, unsigned int value); + +static inline unsigned int hal_i2s_ext_clk_get(int i2s); + +static inline void hal_i2s_cfg_clkgen_set(int i2s, int clk, unsigned int value); + +static inline unsigned int hal_i2s_cfg_clkgen_get(int i2s, int clk); + +static inline void hal_i2s_chmode_set(int i2s, unsigned int value); + +static inline unsigned int hal_i2s_chmode_get(int i2s); + +static inline void hal_i2s_filt_ch_set(int i2s, int ch, unsigned int value); + +static inline unsigned int hal_i2s_filt_ch_get(int i2s, int ch); + + + + +/// @cond IMPLEM + +static inline void hal_i2s_ext_clk_set(int i2s, unsigned int value) +{ + pulp_write32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_EXT_OFFSET, value); +} + +static inline unsigned int hal_i2s_ext_clk_get(int i2s) +{ + return pulp_read32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_EXT_OFFSET); +} + +static inline void hal_i2s_cfg_clkgen_set(int i2s, int clk, unsigned int value) +{ + pulp_write32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_CFG_CLKGEN_OFFSET(clk), value); +} + +static inline unsigned int hal_i2s_cfg_clkgen_get(int i2s, int clk) +{ + return pulp_read32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_CFG_CLKGEN_OFFSET(clk)); +} + +static inline void hal_i2s_chmode_set(int i2s, unsigned int value) +{ + pulp_write32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_CHMODE_OFFSET, value); +} + +static inline unsigned int hal_i2s_chmode_get(int i2s) +{ + return pulp_read32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_CHMODE_OFFSET); +} + +static inline void hal_i2s_filt_ch_set(int i2s, int ch, unsigned int value) +{ + pulp_write32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_FILT_CH_OFFSET(ch), value); +} + +static inline unsigned int hal_i2s_filt_ch_get(int i2s, int ch) +{ + return pulp_read32(UDMA_I2S_CUSTOM_ADDR(i2s) + I2S_FILT_CH_OFFSET(ch)); +} + + + +static inline unsigned int hal_i2s_clkgen_en_update(unsigned int reg_value, unsigned int field_value) +{ + return ARCHI_BINSERT(reg_value, field_value, I2S_CFG_CLKGEN_CLK_EN_WIDTH, I2S_CFG_CLKGEN_CLK_EN_OFFSET); +} + + + +/// @endcond + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v1.h b/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v1.h new file mode 100644 index 0000000..360a798 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v1.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_SPIM_V1_H__ +#define __HAL_UDMA_UDMA_SPIM_V1_H__ + +#include "archi/udma/spim/udma_spim_v1.h" + + +static inline void plp_spi_disable(unsigned channelBase) +{ + pulp_write32(channelBase + UDMA_CHANNEL_CFG_OFFSET, 0); +} + +static inline void hal_udma_spim_enqueue(unsigned int periphBase, unsigned channelBase, unsigned int spi_status, unsigned int l2Addr, unsigned int size, unsigned int cfg, unsigned int spi_len) +{ + pulp_write32(periphBase + UDMA_CHANNEL_CUSTOM_OFFSET + SPIM_SPILEN_OFFSET, spi_len << 16); + pulp_write32(channelBase + UDMA_CHANNEL_SADDR_OFFSET, l2Addr); + pulp_write32(channelBase + UDMA_CHANNEL_SIZE_OFFSET, size); + pulp_write32(channelBase + UDMA_CHANNEL_CFG_OFFSET, cfg); + pulp_write32(periphBase + UDMA_CHANNEL_CUSTOM_OFFSET + SPIM_STATUS_OFFSET, spi_status); +} + +static inline uint32_t hal_udma_spim_status_compute( + unsigned int cskeep, unsigned int cs, unsigned int reset, unsigned int command +) +{ + return (cskeep << ARCHI_SPIM_WSTATUS_CSKEEP_BIT) | + (cs << ARCHI_SPIM_WSTATUS_CS_BIT) | + (reset << ARCHI_SPIM_WSTATUS_RESET_BIT) | + (command << ARCHI_SPIM_WSTATUS_CMD_BIT); +} + +static inline uint32_t hal_udma_spim_status_get(uint32_t periph_base) +{ + return pulp_read32(periph_base + UDMA_CHANNEL_CUSTOM_OFFSET + SPIM_STATUS_OFFSET); +} + +static inline void hal_udma_spim_status_set(uint32_t periph_base, uint32_t value) +{ + pulp_write32(periph_base + UDMA_CHANNEL_CUSTOM_OFFSET + SPIM_STATUS_OFFSET, value); +} + +static inline uint32_t hal_udma_spim_clkdiv_compute( + int datasize_tx, int datasize_rx, int cpha, int cpol, int clkdiv +) +{ + return (datasize_tx << ARCHI_SPIM_CLKDIV_DATASIZE_TX_BIT) | + (datasize_rx << ARCHI_SPIM_CLKDIV_DATASIZE_RX_BIT) | + (cpha << ARCHI_SPIM_CLKDIV_CPHA_BIT) | + (cpol << ARCHI_SPIM_CLKDIV_CPOL_BIT) | + (clkdiv << ARCHI_SPIM_CLKDIV_CLKDIV_BIT); +} + +static inline uint32_t hal_udma_spim_clkdiv_get(uint32_t periph_base) +{ + return pulp_read32(periph_base + UDMA_CHANNEL_CUSTOM_OFFSET + SPIM_CLKDIV_OFFSET); +} + +static inline void hal_udma_spim_clkdiv_set(uint32_t periph_base, uint32_t value) +{ + pulp_write32(periph_base + UDMA_CHANNEL_CUSTOM_OFFSET + SPIM_CLKDIV_OFFSET, value); +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v2.h b/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v2.h new file mode 100644 index 0000000..c939ddc --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v2.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_SPIM_V2_H__ +#define __HAL_UDMA_UDMA_SPIM_V2_H__ + +#include "archi/udma/spim/udma_spim_v2.h" + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v3.h b/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v3.h new file mode 100644 index 0000000..2fc2185 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/spim/udma_spim_v3.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_SPIM_V3_H__ +#define __HAL_UDMA_UDMA_SPIM_V3_H__ + +#include "archi/udma/spim/udma_spim_v3.h" + +#define UDMA_SPIM_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_SPIM_ID(id)) +#define UDMA_SPIM_CMD_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x20) +#define UDMA_SPIM_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x00) +#define UDMA_SPIM_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + 0x10) +#define UDMA_SPIM_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SPIM_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/udma/tcdm/udma_tcdm_v1.h b/sw/pulp-sdk/hal/include/hal/udma/tcdm/udma_tcdm_v1.h new file mode 100644 index 0000000..46dba86 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/tcdm/udma_tcdm_v1.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_TCDM_V1_H__ +#define __HAL_UDMA_UDMA_TCDM_V1_H__ + +#include "archi/udma/tcdm/udma_tcdm_v1.h" + +#define UDMA_TCDM_OFFSET UDMA_PERIPH_OFFSET(ARCHI_UDMA_TCDM_ID(id)) + +#define UDMA_TCDM_RX_ADDR (ARCHI_UDMA_ADDR + UDMA_TCDM_OFFSET + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_TCDM_TX_ADDR (ARCHI_UDMA_ADDR + UDMA_TCDM_OFFSET + UDMA_CHANNEL_TX_OFFSET) +#define UDMA_TCDM_CUSTOM_ADDR (ARCHI_UDMA_ADDR + UDMA_TCDM_OFFSET + UDMA_CHANNEL_CUSTOM_OFFSET) + +static inline void plp_tcdm_setDst(unsigned int addr) +{ + pulp_write32(ARCHI_UDMA_ADDR + UDMA_TCDM_OFFSET + UDMA_CHANNEL_CUSTOM_OFFSET + TCDM_T_DST_SADDR, addr); +} + +static inline void plp_tcdm_setSrc(unsigned int addr) +{ + pulp_write32(ARCHI_UDMA_ADDR + UDMA_TCDM_OFFSET + UDMA_CHANNEL_CUSTOM_OFFSET + TCDM_T_SRC_SADDR, addr); +} + +static inline void plp_udma_enqueue_toTcdm(unsigned int l2Addr, unsigned int fcTcdmAddr, unsigned int size, unsigned int cfg) +{ + plp_tcdm_setDst(fcTcdmAddr); + plp_udma_enqueue(UDMA_TCDM_TX_ADDR, l2Addr, size, cfg); +} + +static inline void plp_udma_enqueue_fromTcdm(unsigned int l2Addr, unsigned int fcTcdmAddr, unsigned int size, unsigned int cfg) +{ + plp_tcdm_setSrc(fcTcdmAddr); + plp_udma_enqueue(UDMA_TCDM_RX_ADDR, l2Addr, size, cfg); +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/uart/udma_uart_v1.h b/sw/pulp-sdk/hal/include/hal/udma/uart/udma_uart_v1.h new file mode 100644 index 0000000..7b9c4a3 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/uart/udma_uart_v1.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_UART_V1_H__ +#define __HAL_UDMA_UDMA_UART_V1_H__ + +#include "archi/udma/uart/udma_uart_v1.h" + +#define UDMA_UART_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_UART_ID(id)) +#define UDMA_UART_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET) +#define UDMA_UART_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET) +#define UDMA_UART_CUSTOM_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET) +#define ARCHI_SOC_EVENT_UART_RX(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_UART_ID(id)) + ARCHI_UDMA_UART_RX_EVT) +#define ARCHI_SOC_EVENT_UART_TX(id) (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_UART_ID(id)) + ARCHI_UDMA_UART_TX_EVT) + +// UDMA RX/TX Channels HAL Registers Structure +typedef struct { + uint32_t rx_ch_saddr; + uint32_t rx_ch_size; + uint32_t rx_ch_cfg; + uint32_t rx_ch_initcfg_unused; + uint32_t tx_ch_saddr; + uint32_t tx_ch_size; + uint32_t tx_ch_cfg; + uint32_t tx_ch_initcfg_unused; +} plpUdmaRxTxChHandle3_t; + +// UART HAL Registers Structure +typedef struct { + plpUdmaRxTxChHandle3_t udma_rxtx_ch_handle; + uint32_t status; + uint32_t setup; +} plpUdmaUartHandle_t; + +// UART HAL Register Fields Structure +typedef struct { + uint32_t tx_oe:1; + uint32_t rx_oe:1; + uint32_t rx_pe:1; + uint32_t unused:29; +} __attribute__ ((packed)) plpUdmaUartStatus_t; + +typedef struct { + uint32_t parity_en:1; + uint32_t char_length:2; + uint32_t stop_bit_length:1; + uint32_t unused0:4; + uint32_t tx_en:1; + uint32_t rx_en:1; + uint32_t unused1:6; + uint32_t clkdiv:16; +} __attribute__ ((packed)) plpUdmaUartSetup_t; + +// UART HAL Register Union definition +typedef union { + plpUdmaUartStatus_t status; + plpUdmaUartSetup_t setup; + uint32_t raw; +} __attribute__ ((packed)) plpUdmaUartCustom_u; + +// UART HAL Handle +#define UART_HANDLE(id) ((plpUdmaUartHandle_t *)(ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(id))) + +// UART HAL functions prototype +static inline void plpUdmaUartSetupSet (plpUdmaUartHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaUartSetupGet (plpUdmaUartHandle_t * const handle); +static inline uint32_t plpUdmaUartStatusGet (plpUdmaUartHandle_t * const handle); + +// UART HAL functions definition +static inline void plpUdmaUartSetupSet (plpUdmaUartHandle_t * const handle, uint32_t data) { + handle->setup = data; +} + +static inline uint32_t plpUdmaUartSetupGet (plpUdmaUartHandle_t * const handle) { + return handle->setup; +} + +static inline uint32_t plpUdmaUartStatusGet (plpUdmaUartHandle_t * const handle) { + return handle->status; +} + +/////////////////////////////////////////////////// +// TODO Obsolete : to be removed cause deprecated +/** + * Setup UART. The UART defaults to 8 bit character mode with 1 stop bit. + * + * parity Enable/disable parity mode + * clk_counter Clock counter value that is used to derive the UART clock. + * There is a prescaler in place that already divides the SoC + * clock by 16. Since this is a counter, a value of 0 means that + * the SoC clock divided by 16 is used. A value of 31 would mean + * that we use the SoC clock divided by 16*32 = 512. + */ + +static inline void plp_uart_setup(int channel, int parity, uint16_t clk_counter) +{ + + // [31:16]: clock divider (from SoC clock) + // [9]: RX enable + // [8]: TX enable + // [3]: stop bits 0 = 1 stop bit + // 1 = 2 stop bits + // [2:1]: bits 00 = 5 bits + // 01 = 6 bits + // 10 = 7 bits + // 11 = 8 bits + // [0]: parity + + unsigned int val = 0x0306 | parity; // both tx and rx enabled; 8N1 configuration; 1 stop bits + + val |= ((clk_counter) << 16); + + pulp_write32(ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(channel) + UDMA_CHANNEL_CUSTOM_OFFSET + UART_SETUP_OFFSET, val); +} + +static inline void plp_uart_disable(int channel) { + pulp_write32(ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(channel) + UDMA_CHANNEL_CUSTOM_OFFSET + UART_SETUP_OFFSET, 0x00500006); +} + +static inline int plp_uart_tx_busy(int channel) { + return pulp_read32(ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(channel) + UDMA_CHANNEL_CUSTOM_OFFSET + UART_STATUS_OFFSET) & 1; +} + +static inline int plp_uart_rx_busy(int channel) { + return (pulp_read32(ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(channel) + UDMA_CHANNEL_CUSTOM_OFFSET + UART_STATUS_OFFSET) >> 1) & 1; +} + +static inline unsigned int plp_uart_reg_read(int channel, unsigned int addr) +{ //adr is an offset, expected UART_STATUS_OFFSET or UART_SETUP_OFFSET + return pulp_read32(ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(channel) + UDMA_CHANNEL_CUSTOM_OFFSET + addr); +} + +static inline void plp_uart_reg_write(int channel, unsigned int addr, unsigned int cfg) +{ //adr is an offset, expected UART_STATUS_OFFSET or UART_SETUP_OFFSET + pulp_write32(ARCHI_UDMA_ADDR + UDMA_UART_OFFSET(channel) + UDMA_CHANNEL_CUSTOM_OFFSET + addr, cfg); +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/udma_v1.h b/sw/pulp-sdk/hal/include/hal/udma/udma_v1.h new file mode 100644 index 0000000..d9b8f0c --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/udma_v1.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2015 ETH Zurich and University of Bologna + * All rights reserved. + * + * This software may be modified and distributed under the terms + * of the BSD license. See the LICENSE file for details. + * + */ + +#ifndef __HAL_UDMA_V1_H__ +#define __HAL_UDMA_V1_H__ + +#include +#include "hal/udma/udma_periph_v1.h" + +static inline void plp_udma_enqueue(unsigned channelBase, unsigned int l2Addr, unsigned int size, unsigned int cfg) +{ + pulp_write32(channelBase + UDMA_CHANNEL_SADDR_OFFSET, l2Addr); + pulp_write32(channelBase + UDMA_CHANNEL_SIZE_OFFSET, size); + pulp_write32(channelBase + UDMA_CHANNEL_CFG_OFFSET, cfg); +} + +/** Tell if a channel is busy, i.e. if it already contains at least one on-going transfer + * + \param channelOffset Offset of the channel + \return 1 if the channel is busy, 0 otherwise + */ +static inline int plp_udma_busy(unsigned channelOffset); + +static inline void udma_mapAllEvents(unsigned int inEvent0, unsigned int inEvent1, unsigned int inEvent2, unsigned int inEvent3, unsigned int inEvent4, unsigned int inEvent5, unsigned int inEvent6, unsigned int inEvent7) +{ + pulp_write32(ARCHI_UDMA_ADDR + UDMA_CONF_OFFSET + UDMA_EVENTS_SETUP0_OFFSET, (inEvent0 << 0) | (inEvent1 << 4) | (inEvent2 << 8) | (inEvent3 << 12) | (inEvent4 << 16) | (inEvent5 << 20) | (inEvent6 << 24) | (inEvent7 << 28)); +} + +static inline void udma_mapAllEvents1(unsigned int inEvent0, unsigned int inEvent1, unsigned int inEvent2, unsigned int inEvent3, unsigned int inEvent4, unsigned int inEvent5, unsigned int inEvent6, unsigned int inEvent7) +{ + pulp_write32(ARCHI_UDMA_ADDR + UDMA_CONF_OFFSET + UDMA_EVENTS_SETUP1_OFFSET, (inEvent0 << 0) | (inEvent1 << 4) | (inEvent2 << 8) | (inEvent3 << 12) | (inEvent4 << 16) | (inEvent5 << 20) | (inEvent6 << 24) | (inEvent7 << 28)); +} + +/// @cond IMPLEM + +static inline int plp_udma_busy(unsigned channelOffset) +{ + return (pulp_read32(channelOffset + UDMA_CHANNEL_CFG_OFFSET) & UDMA_CHANNEL_CFG_EN); +} + +static inline unsigned int hal_udma_channel_base(int id) { + return ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_PERIPH_OFFSET(id>>1) + UDMA_CHANNEL_OFFSET(id&1); +} + +static inline unsigned int hal_udma_periph_base(int id) { + return ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_PERIPH_OFFSET(id); +} + +/// @endcond + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/udma/udma_v2.h b/sw/pulp-sdk/hal/include/hal/udma/udma_v2.h new file mode 100644 index 0000000..1590a54 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/udma_v2.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_V2_H__ +#define __HAL_UDMA_UDMA_V2_H__ + +#include "hal/pulp_io.h" +#include +#include "archi/udma/udma_v2.h" + +/** @name UDMA HAL + * The following API can be used to manage the generic part of the UDMA, i.e. for global configuration and channel enqueueing. Other HALs are available for peripheral specific parts. + * The UDMA is in charge of moving data between peripherals and L2 memory. In order to better pipeline transfers and not loose any data between 2 transfers, 2 transfers at the same time + * can be enqueued in the UDMA. Once the first one is finished, the UDMA starts the second, while the application should enqueue another one to always have 2 pending. + * By default, all peripherals are clock-gated and must be explicitly activated before being used. + * The UDMA can use input events to automatically trigger other actions like enqueuing a new transfer. + */ +/**@{*/ + +/** Tell if a new transfer canbe enqueued to a UDMA channel. + * + \param channelOffset Offset of the channel + \return 1 if another transfer can be enqueued, 0 otherwise + */ +static inline int plp_udma_canEnqueue(unsigned int channelOffset); + +/** Enqueue a new transfer to a UDMA channel. + * + \param channelOffset Offset of the channel + \param l2Addr Address in L2 memory where the data must be accessed (either stored or loaded) + \param size Size in bytes of the transfer + \param cfg Configuration of the transfer. Can be UDMA_CHANNEL_CFG_SIZE_8, UDMA_CHANNEL_CFG_SIZE_16 or UDMA_CHANNEL_CFG_SIZE_32 + */ +static inline void plp_udma_enqueue(unsigned channelOffset, unsigned int l2Addr, unsigned int size, unsigned int cfg); + +/** Tell if a channel is busy, i.e. if it already contains at least one on-going transfer + * + \param channelOffset Offset of the channel + \return 1 if the channel is busy, 0 otherwise + */ +static inline int plp_udma_busy(unsigned channelOffset); + +/** Configures peripheral clock-gating. + * + \param value New configuration. There is 1 bit per peripheral, 0 means the peripheral is clock-gated. The bit number corresponds to the channel ID of the peripheral. + */ +static inline void plp_udma_cg_set(unsigned int value); + +/** Returns peripheral clock-gating. + * + \return The current clock-gating configuration. + */ +static inline unsigned int plp_udma_cg_get(); + +/** Configures input events + * 4 input events can be configured. Each input event is made of 8 bits specifying which global event this local event refers to. This can then be used in some UDMA commands to refer to the global event. + * + \param value The new configuration. Each event is encoded on 8 bits so that it can contain a global event ID between 0 and 255. + */ +static inline void plp_udma_evtin_set(unsigned int value); + +/** Returns input events configuration. + * + \return The current input events configuration. + */ +static inline unsigned int plp_udma_evtin_get(); + + +/** Channel base + * Returns the channel base from the channel identifier + \param id The channel identifier + \return Channel base + */ +static inline unsigned int hal_udma_channel_base(int id); + +/** Channel type (TX or RX) + * Tells if the channel is a TX channel + \param id The channel base address + \return 1 if it is a TX channel + */ +static inline unsigned int hal_udma_channel_isTx(unsigned int addr); + + + +// UDMA RX/TX Channels HAL Registers Structure +typedef struct { + uint32_t rx_ch_saddr; + uint32_t rx_ch_size; + uint32_t rx_ch_cfg; + uint32_t rx_ch_initcfg_unused; + uint32_t tx_ch_saddr; + uint32_t tx_ch_size; + uint32_t tx_ch_cfg; + uint32_t tx_ch_initcfg_unused; +} plpUdmaRxTxChHandle_t; + +// UDMA RX/TX Channels HAL Register Fields Structure +typedef struct { + uint32_t saddr:16; + uint32_t unused:16; +} plpUdmaRxTxChSaddr_t; + +typedef struct { + uint32_t size:17; + uint32_t unused:15; +} plpUdmaRxTxChSize_t; + +typedef struct { + uint32_t continuous:1; + uint32_t datasize:2; + uint32_t unused0:1; + uint32_t enable:1; // used to check also if a transfer is under going + uint32_t clear_pending:1; // clear transfer OR check pending transfer in queue + uint32_t unused1:26; +} plpUdmaRxTxChCfg_t; + +typedef struct { + uint32_t unused:32; +} plpUdmaRxTxChInitCfg_t; + +typedef union { + plpUdmaRxTxChSaddr_t saddr; + plpUdmaRxTxChSize_t size; + plpUdmaRxTxChCfg_t cfg; + uint32_t raw; +} plpUdmaRxTxCh_u; + +// UDMA RX/TX Channels HAL functions prototype +static inline void plpUdmaRxChStartAddrSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaRxChStartAddrGet (plpUdmaRxTxChHandle_t * const handle); +static inline void plpUdmaRxChSizeSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaRxChSizeGet (plpUdmaRxTxChHandle_t * const handle); +static inline void plpUdmaRxChCfgSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaRxChCfgGet (plpUdmaRxTxChHandle_t * const handle); +static inline void plpUdmaTxChStartAddrSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaTxChStartAddrGet (plpUdmaRxTxChHandle_t * const handle); +static inline void plpUdmaTxChSizeSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaTxChSizeGet (plpUdmaRxTxChHandle_t * const handle); +static inline void plpUdmaTxChCfgSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data); +static inline uint32_t plpUdmaTxChCfgGet (plpUdmaRxTxChHandle_t * const handle); + + + + + + + + +//!@} + +/// @cond IMPLEM + +static inline unsigned int hal_udma_channel_isTx(unsigned int addr) +{ + return (addr >> UDMA_CHANNEL_SIZE_LOG2) & 1; +} + +static inline int plp_udma_canEnqueue(unsigned int channelBase) +{ + return !(pulp_read32(channelBase + UDMA_CHANNEL_CFG_OFFSET) & UDMA_CHANNEL_CFG_SHADOW); +} + +static inline void plp_udma_enqueue(unsigned channelBase, unsigned int l2Addr, unsigned int size, unsigned int cfg) +{ + ARCHI_WRITE(channelBase, UDMA_CHANNEL_SADDR_OFFSET, l2Addr); + ARCHI_WRITE(channelBase, UDMA_CHANNEL_SIZE_OFFSET, size); + ARCHI_WRITE(channelBase, UDMA_CHANNEL_CFG_OFFSET, cfg | UDMA_CHANNEL_CFG_EN); +} + +static inline void plp_udma_clr(unsigned channelBase) +{ + ARCHI_WRITE(channelBase, UDMA_CHANNEL_CFG_OFFSET, UDMA_CHANNEL_CFG_CLEAR); +} + +static inline int plp_udma_busy(unsigned channelOffset) +{ + return (pulp_read32(channelOffset + UDMA_CHANNEL_CFG_OFFSET) & UDMA_CHANNEL_CFG_EN); +} + +static inline void plp_udma_cg_set(unsigned int value) { + pulp_write32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_CG_OFFSET, value); +} + + static inline unsigned int plp_udma_cg_get() { + return pulp_read32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_CG_OFFSET); +} + +static inline void plp_udma_evtin_set(unsigned int value) { + pulp_write32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_EVTIN_OFFSET, value); +} + +static inline unsigned int plp_udma_evtin_get() { + return pulp_read32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_EVTIN_OFFSET); +} + +static inline unsigned int hal_udma_periph_base(int id) { + return ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_PERIPH_OFFSET(id); +} + +static inline __attribute__((always_inline)) unsigned int hal_udma_channel_base(int id) { + return ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_PERIPH_OFFSET(id>>1) + UDMA_CHANNEL_OFFSET(id&1); +} + +// UDMA RX/TX Channels HAL functions definition +static inline void plpUdmaRxChStartAddrSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data) { + handle->rx_ch_saddr = data; +}; + +static inline uint32_t plpUdmaRxChStartAddrGet (plpUdmaRxTxChHandle_t * const handle) { + return handle->rx_ch_saddr; +}; + +static inline void plpUdmaRxChSizeSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data) { + handle->rx_ch_size = data; +}; + +static inline uint32_t plpUdmaRxChSizeGet (plpUdmaRxTxChHandle_t * const handle) { + return handle->rx_ch_size; +}; + +static inline void plpUdmaRxChCfgSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data) { + handle->rx_ch_cfg = data; +}; + +static inline uint32_t plpUdmaRxChCfgGet (plpUdmaRxTxChHandle_t * const handle) { + return handle->rx_ch_cfg; +}; + +static inline void plpUdmaTxChStartAddrSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data) { + handle->tx_ch_saddr = data; +}; + +static inline uint32_t plpUdmaTxChStartAddrGet (plpUdmaRxTxChHandle_t * const handle) { + return handle->tx_ch_saddr; +}; + +static inline void plpUdmaTxChSizeSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data) { + handle->tx_ch_size = data; +}; + +static inline uint32_t plpUdmaTxChSizeGet (plpUdmaRxTxChHandle_t * const handle) { + return handle->tx_ch_size; +}; + +static inline void plpUdmaTxChCfgSet (plpUdmaRxTxChHandle_t * const handle, uint32_t data) { + handle->tx_ch_cfg = data; +}; + +static inline uint32_t plpUdmaTxChCfgGet (plpUdmaRxTxChHandle_t * const handle) { + return handle->tx_ch_cfg; +}; + +/// @endcond + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/udma/udma_v3.h b/sw/pulp-sdk/hal/include/hal/udma/udma_v3.h new file mode 100644 index 0000000..29d2bd4 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/udma/udma_v3.h @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UDMA_UDMA_V3_H__ +#define __HAL_UDMA_UDMA_V3_H__ + +#include "hal/pulp.h" +#include +#include "archi/udma/udma_v3.h" + +/** @name UDMA HAL + * The following API can be used to manage the generic part of the UDMA, i.e. for global configuration and channel enqueueing. Other HALs are available for peripheral specific parts. + * The UDMA is in charge of moving data between peripherals and L2 memory. In order to better pipeline transfers and not loose any data between 2 transfers, 2 transfers at the same time + * can be enqueued in the UDMA. Once the first one is finished, the UDMA starts the second, while the application should enqueue another one to always have 2 pending. + * By default, all peripherals are clock-gated and must be explicitly activated before being used. + * The UDMA can use input events to automatically trigger other actions like enqueuing a new transfer. + */ +/**@{*/ + +/** Tell if a new transfer canbe enqueued to a UDMA channel. + * + \param channelOffset Offset of the channel + \return 1 if another transfer can be enqueued, 0 otherwise + */ +static inline int plp_udma_canEnqueue(unsigned int channelOffset); + +/** Enqueue a new transfer to a UDMA channel. + * + \param channelOffset Offset of the channel + \param l2Addr Address in L2 memory where the data must be accessed (either stored or loaded) + \param size Size in bytes of the transfer + \param cfg Configuration of the transfer. Can be UDMA_CHANNEL_CFG_SIZE_8, UDMA_CHANNEL_CFG_SIZE_16 or UDMA_CHANNEL_CFG_SIZE_32 + */ +static inline void plp_udma_enqueue(unsigned channelOffset, unsigned int l2Addr, unsigned int size, unsigned int cfg); + +/** Tell if a channel is busy, i.e. if it already contains at least one on-going transfer + * + \param channelOffset Offset of the channel + \return 1 if the channel is busy, 0 otherwise + */ +static inline int plp_udma_busy(unsigned channelOffset); + +/** Configures peripheral clock-gating. + * + \param value New configuration. There is 1 bit per peripheral, 0 means the peripheral is clock-gated. The bit number corresponds to the channel ID of the peripheral. + */ +static inline void plp_udma_cg_set(unsigned int value); + +/** Returns peripheral clock-gating. + * + \return The current clock-gating configuration. + */ +static inline unsigned int plp_udma_cg_get(); + +/** Configures input events + * 4 input events can be configured. Each input event is made of 8 bits specifying which global event this local event refers to. This can then be used in some UDMA commands to refer to the global event. + * + \param value The new configuration. Each event is encoded on 8 bits so that it can contain a global event ID between 0 and 255. + */ +static inline void plp_udma_evtin_set(unsigned int value); + +/** Returns input events configuration. + * + \return The current input events configuration. + */ +static inline unsigned int plp_udma_evtin_get(); + + +/** Channel base + * Returns the channel base from the channel identifier + \param id The channel identifier + \return Channel base + */ +static inline unsigned int hal_udma_channel_base(int id); + +/** Channel type (TX or RX) + * Tells if the channel is a TX channel + \param id The channel base address + \return 1 if it is a TX channel + */ +static inline unsigned int hal_udma_channel_isTx(unsigned int addr); + + + + + + +// UDMA RX/TX Channels HAL Registers Structure +struct plpUdmaRxTxCh_struct_t{ + uint32_t rx_ch_saddr; + uint32_t rx_ch_size; + uint32_t rx_ch_cfg; + uint32_t rx_ch_initcfg_unused; + uint32_t tx_ch_saddr; + uint32_t tx_ch_size; + uint32_t tx_ch_cfg; + uint32_t tx_ch_initcfg_unused; +}; +typedef volatile struct plpUdmaRxTxCh_struct_t plpUdmaRxTxChHandle_t; + +// UDMA RX/TX Channels HAL Register Fields Structure +typedef struct { + uint32_t saddr:16; + uint32_t unused:16; +} plpUdmaRxTxChSaddr_t; + +typedef struct { + uint32_t size:17; + uint32_t unused:15; +} plpUdmaRxTxChSize_t; + +typedef struct { + uint32_t continuous:1; + uint32_t datasize:2; + uint32_t unused0:1; + uint32_t enable:1; // used to check also if a transfer is under going + uint32_t clear_pending:1; // clear transfer OR check pending transfer in queue + uint32_t unused1:26; +} plpUdmaRxTxChCfg_t; + +typedef struct { + uint32_t unused:32; +} plpUdmaRxTxChInitCfg_t; + +typedef union { + plpUdmaRxTxChSaddr_t saddr; + plpUdmaRxTxChSize_t size; + plpUdmaRxTxChCfg_t cfg; + uint32_t raw; +} plpUdmaRxTxCh_u; + +// UDMA RX/TX Channels HAL functions prototype +static inline void plpUdmaRxChStartAddrSet (plpUdmaRxTxChHandle_t * handle, uint32_t data); +static inline uint32_t plpUdmaRxChStartAddrGet (plpUdmaRxTxChHandle_t * handle); +static inline void plpUdmaRxChSizeSet (plpUdmaRxTxChHandle_t * handle, uint32_t data); +static inline uint32_t plpUdmaRxChSizeGet (plpUdmaRxTxChHandle_t * handle); +static inline void plpUdmaRxChCfgSet (plpUdmaRxTxChHandle_t * handle, uint32_t data); +static inline uint32_t plpUdmaRxChCfgGet (plpUdmaRxTxChHandle_t * handle); +static inline void plpUdmaTxChStartAddrSet (plpUdmaRxTxChHandle_t * handle, uint32_t data); +static inline uint32_t plpUdmaTxChStartAddrGet (plpUdmaRxTxChHandle_t * handle); +static inline void plpUdmaTxChSizeSet (plpUdmaRxTxChHandle_t * handle, uint32_t data); +static inline uint32_t plpUdmaTxChSizeGet (plpUdmaRxTxChHandle_t * handle); +static inline void plpUdmaTxChCfgSet (plpUdmaRxTxChHandle_t * handle, uint32_t data); +static inline uint32_t plpUdmaTxChCfgGet (plpUdmaRxTxChHandle_t * handle); + +//!@} + +/// @cond IMPLEM + +// UDMA RX/TX Channels HAL functions definition +static inline void plpUdmaRxChStartAddrSet (plpUdmaRxTxChHandle_t * handle, uint32_t data) { + handle->rx_ch_saddr = data; +}; + +static inline uint32_t plpUdmaRxChStartAddrGet (plpUdmaRxTxChHandle_t * handle) { + return handle->rx_ch_saddr; +}; + +static inline void plpUdmaRxChSizeSet (plpUdmaRxTxChHandle_t * handle, uint32_t data) { + handle->rx_ch_size = data; +}; + +static inline uint32_t plpUdmaRxChSizeGet (plpUdmaRxTxChHandle_t * handle) { + return handle->rx_ch_size; +}; + +static inline void plpUdmaRxChCfgSet (plpUdmaRxTxChHandle_t * handle, uint32_t data) { + handle->rx_ch_cfg = data; +}; + +static inline uint32_t plpUdmaRxChCfgGet (plpUdmaRxTxChHandle_t * handle) { + return handle->rx_ch_cfg; +}; + +static inline void plpUdmaTxChStartAddrSet (plpUdmaRxTxChHandle_t * handle, uint32_t data) { + handle->tx_ch_saddr = data; +}; + +static inline uint32_t plpUdmaTxChStartAddrGet (plpUdmaRxTxChHandle_t * handle) { + return handle->tx_ch_saddr; +}; + +static inline void plpUdmaTxChSizeSet (plpUdmaRxTxChHandle_t * handle, uint32_t data) { + handle->tx_ch_size = data; +}; + +static inline uint32_t plpUdmaTxChSizeGet (plpUdmaRxTxChHandle_t * handle) { + return handle->tx_ch_size; +}; + +static inline void plpUdmaTxChCfgSet (plpUdmaRxTxChHandle_t * handle, uint32_t data) { + handle->tx_ch_cfg = data; +}; + +static inline uint32_t plpUdmaTxChCfgGet (plpUdmaRxTxChHandle_t * handle) { + return handle->tx_ch_cfg; +}; + + + + +/////////////////////////////////////////////////// +// TODO Obsolete : to be removed cause deprecated +static inline unsigned int hal_udma_channel_isTx(unsigned int addr) +{ + return (addr >> UDMA_CHANNEL_SIZE_LOG2) & 1; +} + +static inline int plp_udma_canEnqueue(unsigned int channelBase) +{ + return !(pulp_read32(channelBase + UDMA_CHANNEL_CFG_OFFSET) & UDMA_CHANNEL_CFG_SHADOW); +} + +static inline void plp_udma_enqueue(unsigned channelBase, unsigned int l2Addr, unsigned int size, unsigned int cfg) +{ + pulp_write32(channelBase + UDMA_CHANNEL_SADDR_OFFSET, l2Addr); + pulp_write32(channelBase + UDMA_CHANNEL_SIZE_OFFSET, size); + pulp_write32(channelBase + UDMA_CHANNEL_CFG_OFFSET, cfg | UDMA_CHANNEL_CFG_EN); +} + +static inline int plp_udma_busy(unsigned channelOffset) +{ + return (pulp_read32(channelOffset + UDMA_CHANNEL_CFG_OFFSET) & UDMA_CHANNEL_CFG_EN); +} + +static inline void plp_udma_cg_set(unsigned int value) { + pulp_write32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_CG_OFFSET, value); +} + + static inline unsigned int plp_udma_cg_get() { + return pulp_read32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_CG_OFFSET); +} + +static inline void plp_udma_evtin_set(unsigned int value) { + pulp_write32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_EVTIN_OFFSET, value); +} + +static inline unsigned int plp_udma_evtin_get() { + return pulp_read32(ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + UDMA_CONF_EVTIN_OFFSET); +} + +static inline unsigned int hal_udma_periph_base(int id) { + return ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_PERIPH_OFFSET(id); +} + +static inline unsigned int hal_udma_channel_base(int id) { + return ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_PERIPH_OFFSET(id>>1) + UDMA_CHANNEL_OFFSET(id&1); +} +/////////////////////////////////////////////////// + +/// @endcond + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/utils.h b/sw/pulp-sdk/hal/include/hal/utils.h new file mode 100644 index 0000000..41f8df3 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/utils.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2017 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_UTILS_H__ +#define __HAL_UTILS_H__ + +/** @name Bitmask Generation Macros + * + * @{ + */ + +/** Create a bitmask with one bit set. + + \param n The index of the bit to set. The LSB has index 0. + + \return Bitmask with the `n`-th bit set. +*/ +#define BIT_MASK_ONE(n) (1UL << (n)) + +/** Create a bitmask with the lowest bits set. + + \param n The number of LSBs to set. + + \return Bitmask with the `n` LSBs set. +*/ +#define BIT_MASK_LSBS(n) (BIT_MASK_ONE(n) - 1) + +/** Create a bitmask with a number of intermediary bits set. + + \param start The index of the lowest bit to set. The LSB has index 0. + \param n The number of bits to set. + + \return Bitmask with `n` bits set starting at `start`. +*/ +#define BIT_MASK_IMEDS(start, n) (BIT_MASK_LSBS(n) << (start)) + +//!@} + +/** @name Bitfield Manipulation Macros + * + * @{ + */ + +/** Set the masked bits. + + \param y The bitfield to manipulate. + \param mask The bitmask that defines which bits to set. + + \return A bitfield where all bits that are set in `mask` are set and all other bits are taken + from `y`. +*/ +#define BIT_SET(y, mask) ((y) |= (mask)) + +/** Clear the masked bits. + + \param y The bitfield to manipulate. + \param mask The bitmask that defines which bits to clear. + + \return A bitfield where all bits that are set in `mask` are cleared and all other bits are + taken from `y`. +*/ +#define BIT_CLEAR(y, mask) ((y) &= ~(mask)) + +/** Flip the masked bits. + + \param y The bitfield to manipulate. + \param mask The bitmask that defines which bits to flip. + + \return A bitfield where all bits that are set in `mask` are flipped and all other bits are + taken from `y`. +*/ +#define BIT_FLIP(y, mask) ((y) ^= (mask)) + +/// @cond IMPLEM + +// Prepare a bitmask for insertion or combining. +#define __BIT_MASK_PREP(x, start, n) (((x) & BIT_MASK_LSBS(n)) << (start)) + +/// @endcond + +/** Get a part of a bitfield. + + \param y The bitfield to extract a part from. + \param start The index of the least-significant bit of the part to extract. + \param n The number of bits to extract. + + \return The `n` bits starting at `start` from `y` in the LSBs. +*/ +#define BIT_GET(y, start, n) (((y) >> (start)) & BIT_MASK_LSBS(n)) + +/** Insert one bitfield into another. + + \param y The target bitfield to insert into. + \param x The bitfield to insert. + \param start The index at which `x` shall be inserted into `y`. + \param n The number of bits to insert from `x`. + + \return `y` with `n` bits from `x` inserted starting at `start`. +*/ +#define BIT_INSERT(y, x, start, n) \ + (y = ((y) & ~BIT_MASK_IMEDS(start, n)) | __BIT_MASK_PREP(x, start, n)) + +//!@} + + +static inline void hal_compiler_barrier() { + __asm__ __volatile__ ("" : : : "memory"); +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/vendors/dolphin/rtc.h b/sw/pulp-sdk/hal/include/hal/vendors/dolphin/rtc.h new file mode 100644 index 0000000..03b0818 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/vendors/dolphin/rtc.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_RTC_H__ +#define __HAL_RTC_H__ + +#include +#include "archi/vendors/dolphin/rtc.h" + +//============================================================= +/* + * For Configuring the RTC, we use the APB interface: + * Write a Register: + 1) Write the data (the value of this indirect Access Register) to APB_RTC_DATA_REG_ADDR + 2) Write the register address in APB_RTC_CTRL_REG_ADDR[0:5] + 3) Set the write bit APB_RTC_CTRL_REG_ADDR[16] to 1 + + * Read a Register: + 1) Write the register address in APB_RTC_CTRL_REG_ADDR[0:5] + 2) Set the write bit APB_RTC_CTRL_REG_ADDR[16] to 0 + 3) Read the value of the register from APB_RTC_DATA_REG_ADDR + */ + +static inline unsigned int rt_apb_rtc_reg_read (unsigned int addr){ + return pulp_read32(addr); +} + +static inline void rt_apb_rtc_reg_write(unsigned int addr, unsigned int conf){ + pulp_write32(addr, conf); +} + +#endif diff --git a/sw/pulp-sdk/hal/include/hal/vendors/iid/quiddikey_v1.h b/sw/pulp-sdk/hal/include/hal/vendors/iid/quiddikey_v1.h new file mode 100644 index 0000000..e980485 --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/vendors/iid/quiddikey_v1.h @@ -0,0 +1,372 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_IID_QUIDDIKEY_V1_H__ +#define __HAL_IID_QUIDDIKEY_V1_H__ + +#include +#include +#include "archi/vendors/iid/quiddikey_v1.h" + +#if QUIDDIKEY_VERSION != 1 +#error This file must be included only with quiddikey version 1 +#endif + +// QUIDDIKEY HAL Registers Structure +typedef struct { + uint32_t cfg; + uint32_t status; + uint32_t allow; + uint32_t ier; + uint32_t imr; + uint32_t isr; + uint32_t key_dest; + uint32_t dir; + uint32_t dor; + uint32_t misc; + uint32_t if_sr; + uint32_t test; + uint32_t hw_ruc0; + uint32_t hw_ruc1; + uint32_t hw_settings; + uint32_t hw_info; + uint32_t hw_id; + uint32_t hw_ver; +} halQuiddikeyHandle_t; + + +// QUIDDIKEY HAL Register Fields Structure +typedef struct { + uint32_t zeroize : 1; + uint32_t enroll : 1; + uint32_t start : 1; + uint32_t unused : 2; + uint32_t stop : 1; + uint32_t get_key : 1; + uint32_t unwrap : 1; + uint32_t wrap_gen_rand : 1; + uint32_t wrap : 1; + uint32_t unused1 : 5; + uint32_t gen_rand : 1; + uint32_t unused2 : 16; +} __attribute__ ((packed)) halQuiddikeyCfg_t; + +typedef struct { + uint32_t busy : 1; + uint32_t last_op_pass : 1; + uint32_t last_op_error : 1; + uint32_t zeroized : 1; + uint32_t rejected : 1; + uint32_t di_req : 1; + uint32_t do_req : 1; + uint32_t unused : 25; +} __attribute__ ((packed)) halQuiddikeyStatus_t; + +typedef struct { + uint32_t unused : 1; + uint32_t enroll : 1; + uint32_t start : 1; + uint32_t unused1 : 2; + uint32_t stop : 1; + uint32_t get_key : 1; + uint32_t unwrap : 1; + uint32_t wrap_gen_rand : 1; + uint32_t wrap : 1; + uint32_t unused2 : 5; + uint32_t gen_rand : 1; + uint32_t unused3 : 16; +} __attribute__ ((packed)) halQuiddikeyAllow_t; + +typedef struct { + uint32_t ier : 1; + uint32_t unused : 31; +} __attribute__ ((packed)) halQuiddikeyInterruptEnable_t; + +typedef struct { + uint32_t busy : 1; + uint32_t ok : 1; + uint32_t error : 1; + uint32_t zeroized : 1; + uint32_t rejected : 1; + uint32_t di_req : 1; + uint32_t do_req : 1; + uint32_t unused : 25; +} __attribute__ ((packed)) halQuiddikeyInterruptMask_t; + +typedef struct { + uint32_t busy : 1; + uint32_t ok : 1; + uint32_t error : 1; + uint32_t zeroized : 1; + uint32_t rejected : 1; + uint32_t di_req : 1; + uint32_t do_req : 1; + uint32_t unused : 25; +} __attribute__ ((packed)) halQuiddikeyInterruptStatus_t; + +typedef struct { + uint32_t dor_reg : 1; + uint32_t ko_itf : 1; + uint32_t unused : 30; +} __attribute__ ((packed)) halQuiddikeyKeyDest_t; + +typedef struct { + uint32_t data:32; +} __attribute__ ((packed)) halQuiddikeyDataInput_t; + +typedef struct { + uint32_t data:32; +} __attribute__ ((packed)) halQuiddikeyDataOutput_t; + +typedef struct { + uint32_t endianness : 1; + uint32_t unused : 31; +} __attribute__ ((packed)) halQuiddikeyEndianness_t; + +typedef struct { + uint32_t apb_error : 1; + uint32_t unused : 31; +} __attribute__ ((packed)) halQuiddikeyInterfaceStatus_t; + +typedef struct { + uint32_t bist_sel : 1; + uint32_t unused : 3; + uint32_t bist_running : 1; + uint32_t bist_active : 1; + uint32_t bist_ok : 1; + uint32_t bist_fail : 1; + uint32_t unused1 : 23; + uint32_t bist_allow : 1; +} __attribute__ ((packed)) halQuiddikeyTest_t; + +typedef struct { + uint32_t hw_ruc0:32; +} __attribute__ ((packed)) halQuiddikeyHwRUC0_t; + +typedef struct { + uint32_t hw_ruc1:32; +} __attribute__ ((packed)) halQuiddikeyHwRUC1_t; + +typedef struct { + uint32_t unused : 1; + uint32_t disable_enroll : 1; + uint32_t disable_start : 1; + uint32_t unused1 : 2; + uint32_t disable_stop : 1; + uint32_t disable_get_key : 1; + uint32_t disable_unwrap : 1; + uint32_t disable_wrap_gen_rand : 1; + uint32_t disable_wrap : 1; + uint32_t unused2 : 5; + uint32_t disable_gen_rand : 1; + uint32_t unused3 : 16; +} __attribute__ ((packed)) halQuiddikeyHwSettings_t; + +typedef struct { + uint32_t unused : 22; + uint32_t cfg_bist : 1; + uint32_t unused1 : 5; + uint32_t cfg_type : 1; + uint32_t unused3 : 3; +} __attribute__ ((packed)) halQuiddikeyInfo_t; + +typedef struct { + uint32_t id:32; +} __attribute__ ((packed)) halQuiddikeyID_t; + +typedef struct { + uint32_t rev : 8; + uint32_t minor : 8; + uint32_t major : 8; + uint32_t unused : 8; +} __attribute__ ((packed)) halQuiddikeyVersion_t; + +// QUIDDIKEY HAL Register Union definition +typedef union { + halQuiddikeyCfg_t config; + halQuiddikeyStatus_t status; + halQuiddikeyAllow_t allow; + halQuiddikeyInterruptEnable_t int_enable; + halQuiddikeyInterruptMask_t int_mask; + halQuiddikeyInterruptStatus_t int_status; + halQuiddikeyKeyDest_t key_dest; + halQuiddikeyDataInput_t data_in; + halQuiddikeyDataOutput_t data_out; + halQuiddikeyEndianness_t endianness; + halQuiddikeyInterfaceStatus_t apb_itf_status; + halQuiddikeyTest_t test_cfg; + halQuiddikeyHwRUC0_t hw_ruc0; + halQuiddikeyHwRUC1_t hw_ruc1; + halQuiddikeyHwSettings_t hw_settings; + halQuiddikeyInfo_t info; + halQuiddikeyID_t id; + halQuiddikeyVersion_t version; + uint32_t raw; +} __attribute__ ((packed)) halQuiddikey_u; + + +// QUIDDIKEY HAL Handle +// located in "archi/chip/x/memory_map.h" + + +// QUIDDIKEY HAL functions prototype +static inline uint32_t halQuiddikeyBaseAddrGet (halQuiddikeyHandle_t * const handle); + +static inline void halQuiddikeyCfgSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyCfgGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyStatusSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyStatusGet (halQuiddikeyHandle_t * const handle); +static inline uint32_t halQuiddikeyAllowGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyInterruptEnableSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyInterruptEnableGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyInterruptMaskSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyInterruptMaskGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyInterruptStatusSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyInterruptStatusGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyKeyDestSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyKeyDestGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyDataInputSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyDataOutputGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyEndiannessSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyEndiannessGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyApbInterfaceStatusSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyApbInterfaceStatusGet (halQuiddikeyHandle_t * const handle); +static inline void halQuiddikeyTestSet (halQuiddikeyHandle_t * const handle, uint32_t data); +static inline uint32_t halQuiddikeyTestGet (halQuiddikeyHandle_t * const handle); +static inline uint32_t halQuiddikeyHwRUC0Get (halQuiddikeyHandle_t * const handle); +static inline uint32_t halQuiddikeyHwRUC1Get (halQuiddikeyHandle_t * const handle); +static inline uint32_t halQuiddikeyHwSettingsGet (halQuiddikeyHandle_t * const handle); +static inline uint32_t halQuiddikeyHwInfoGet (halQuiddikeyHandle_t * const handle); +static inline uint32_t halQuiddikeyHwIDGet (halQuiddikeyHandle_t * const handle); +static inline uint32_t halQuiddikeyHwVersionGet (halQuiddikeyHandle_t * const handle); + + + + +// QUIDDIKEY HAL functions definition +static inline uint32_t halQuiddikeyBaseAddrGet (halQuiddikeyHandle_t * const handle) { + return (uint32_t) (handle); +} + +static inline void halQuiddikeyCfgSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->cfg = data; +} + +static inline uint32_t halQuiddikeyCfgGet (halQuiddikeyHandle_t * const handle) { + return handle->cfg; +} + +static inline void halQuiddikeyStatusSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->status = data; +} + +static inline uint32_t halQuiddikeyStatusGet (halQuiddikeyHandle_t * const handle) { + return handle->status; +} + +static inline uint32_t halQuiddikeyAllowGet (halQuiddikeyHandle_t * const handle) { + return handle->allow; +} + +static inline void halQuiddikeyInterruptEnableSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->ier = data; +} + +static inline uint32_t halQuiddikeyInterruptEnableGet (halQuiddikeyHandle_t * const handle) { + return handle->ier; +} + +static inline void halQuiddikeyInterruptMaskSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->imr = data; +} + +static inline uint32_t halQuiddikeyInterruptMaskGet (halQuiddikeyHandle_t * const handle) { + return handle->imr; +} + +static inline void halQuiddikeyInterruptStatusSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->isr = data; +} + +static inline uint32_t halQuiddikeyInterruptStatusGet (halQuiddikeyHandle_t * const handle) { + return handle->isr; +} + +static inline void halQuiddikeyKeyDestSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->key_dest = data; +} + +static inline uint32_t halQuiddikeyKeyDestGet (halQuiddikeyHandle_t * const handle) { + return handle->key_dest; +} + +static inline void halQuiddikeyDataInputSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->dir = data; +} + +static inline uint32_t halQuiddikeyDataOuputGet (halQuiddikeyHandle_t * const handle) { + return handle->dor; +} + +static inline void halQuiddikeyEndiannessSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->misc = data; +} + +static inline uint32_t halQuiddikeyEndiannessGet (halQuiddikeyHandle_t * const handle) { + return handle->misc; +} + +static inline void halQuiddikeyApbInterfaceStatusSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->if_sr = data; +} + +static inline uint32_t halQuiddikeyApbInterfaceStatusGet (halQuiddikeyHandle_t * const handle) { + return handle->if_sr; +} + +static inline void halQuiddikeyTestSet (halQuiddikeyHandle_t * const handle, uint32_t data) { + handle->test = data; +} + +static inline uint32_t halQuiddikeyTestGet (halQuiddikeyHandle_t * const handle) { + return handle->test; +} + +static inline uint32_t halQuiddikeyHwRUC0Get (halQuiddikeyHandle_t * const handle) { + return handle->hw_ruc0; +} + +static inline uint32_t halQuiddikeyHwRUC1Get (halQuiddikeyHandle_t * const handle) { + return handle->hw_ruc1; +} + +static inline uint32_t halQuiddikeyHwSettingsGet (halQuiddikeyHandle_t * const handle) { + return handle->hw_settings; +} + +static inline uint32_t halQuiddikeyHwInfoGet (halQuiddikeyHandle_t * const handle) { + return handle->hw_info; +} + +static inline uint32_t halQuiddikeyHwIDGet (halQuiddikeyHandle_t * const handle) { + return handle->hw_id; +} + +static inline uint32_t halQuiddikeyHwVersionGet (halQuiddikeyHandle_t * const handle) { + return handle->hw_ver; +} + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/vendors/lnt/csi2_v1.h b/sw/pulp-sdk/hal/include/hal/vendors/lnt/csi2_v1.h new file mode 100644 index 0000000..051aeaa --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/vendors/lnt/csi2_v1.h @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2018 GreenWaves Technologies + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_LNT_CSI2_V1_H__ +#define __HAL_LNT_CSI2_V1_H__ + +#include +#include +#include "archi/vendors/lnt/csi2_v1.h" + +#if CSI2_VERSION != 1 +#error This file must be included only with quiddikey version 1 +#endif + +// CSI2 HAL Registers Structure +struct halCsi2_struct_t { + uint32_t unused[96]; // offset to start reg access @ 0x60<<2 + uint32_t cfg; // default value 0x0 + uint32_t err_msb1; // default value 0x0 + uint32_t err_msb; // default value 0x0 + uint32_t err_lsb; // default value 0x0 + uint32_t hs_rx_timeout_msb2; // default value 0xff + uint32_t hs_rx_timeout_msb1; // default value 0xff + uint32_t hs_rx_timeout_lsb; // default value 0xff + uint32_t vccfg; // default value 0x1 + uint32_t polarity; // default value 0x0 + uint32_t cci_addr; // default value 0x0 + uint32_t cci_wr_data; // default value 0x0 + uint32_t cci_rd_data; // default value 0x0 + uint32_t cci_read_write; // default value 0x0 + uint32_t cci_status; // default value 0x0 + uint32_t cci_device_addr; // default value 0x3c + uint32_t ulps_status; // default value 0x0 +}; +typedef volatile struct halCsi2_struct_t halCsi2Handle_t; + +// DPHY HAL Registers Structure +struct halDphy_struct_t { + uint32_t lane_enable; // default value 0x1 + uint32_t unused[31]; + //TODO add missing new registers visible in v1.6 + uint32_t reset_dig_logic; // default value 0x1f + uint32_t unused1[41]; + uint32_t lane_ck_cont_mode; // default value 0x0f + uint32_t unused2[13]; + uint32_t lane_ck_hs_countdown; // default value 0x1b + uint32_t unused3[1]; + uint32_t lane_ck_rx_calib_enable; // default value 0x7f + uint32_t unused4[29]; + uint32_t lane_0_hs_countdown; // default value 0x1b + uint32_t unused5[1]; + uint32_t lane_0_rx_calib_enable; // default value 0x7f + uint32_t unused6[29]; + uint32_t lane_1_hs_countdown; // default value 0x1b + uint32_t unused7[1]; + uint32_t lane_1_rx_calib_enable; // default value 0x7f +}; +typedef volatile struct halDphy_struct_t halDphyHandle_t; + +// TODO CSI2 HAL Register Fields Structure +// typedef struct { +// uint32_t zeroize : 1; +// uint32_t unused2 : 16; +// } __attribute__ ((packed)) halQuiddikeyCfg_t; + +// TODO CSI2 HAL Register Union definition +// typedef union { +// halQuiddikeyCfg_t config; +// halQuiddikeyStatus_t status; +// uint32_t raw; +// } __attribute__ ((packed)) halQuiddikey_u; + + + + +// CSI2 HAL Handle +// located in "archi/chip/x/memory_map.h" + +// DPHY HAL Handle +// located in "archi/chip/x/memory_map.h" + + +// CSI2 HAL functions prototype +static inline uint32_t halCsi2BaseAddrGet (halCsi2Handle_t * handle); +static inline void halCsi2CfgSet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2CfgGet (halCsi2Handle_t * handle); +static inline uint32_t halCsi2ErrMsb1Get (halCsi2Handle_t * handle); +static inline uint32_t halCsi2ErrMsbGet (halCsi2Handle_t * handle); +static inline uint32_t halCsi2ErrLsbGet (halCsi2Handle_t * handle); +static inline void halCsi2HsRxTimeoutMsb2Set (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2HsRxTimeoutMsb2Get (halCsi2Handle_t * handle); +static inline void halCsi2HsRxTimeoutMsb1Set (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2HsRxTimeoutMsb1Get (halCsi2Handle_t * handle); +static inline void halCsi2HsRxTimeoutLsbSet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2HsRxTimeoutLsbGet (halCsi2Handle_t * handle); +static inline void halCsi2VcCfgSet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2VcCfgGet (halCsi2Handle_t * handle); +static inline void halCsi2PolaritySet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2PolarityGet (halCsi2Handle_t * handle); +static inline void halCsi2CciAddressSet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2CciAddressGet (halCsi2Handle_t * handle); +static inline void halCsi2CciWriteDataSet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2CciWriteDataGet (halCsi2Handle_t * handle); +static inline uint32_t halCsi2CciReadDataGet (halCsi2Handle_t * handle); +static inline void halCsi2CciReadWriteSet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2CciReadWriteGet (halCsi2Handle_t * handle); +static inline uint32_t halCsi2CciStatusGet (halCsi2Handle_t * handle); +static inline void halCsi2CciDeviceAddressSet (halCsi2Handle_t * handle, uint32_t data); +static inline uint32_t halCsi2CciDeviceAddressGet (halCsi2Handle_t * handle); +static inline uint32_t halCsi2UlpsStatusGet (halCsi2Handle_t * handle); + +// DPHY HAL functions prototype +static inline uint32_t halDphyBaseAddrGet (halDphyHandle_t * handle); +static inline void halDphyLaneEnableSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLaneEnableGet (halDphyHandle_t * handle); +static inline void halDphyResetDigLogicSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyResetDigLogicGet (halDphyHandle_t * handle); +static inline void halDphyLaneClkHsCountdownSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLaneClkHsCountdownGet (halDphyHandle_t * handle); +static inline void halDphyLaneClkContModeSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLaneClkContModeGet (halDphyHandle_t * handle); +static inline void halDphyLaneClkRxCalibSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLaneClkRxCalibGet (halDphyHandle_t * handle); +static inline void halDphyLane0HsCountdownSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLane0HsCountdownGet (halDphyHandle_t * handle); +static inline void halDphyLane0RxCalibSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLane0RxCalibGet (halDphyHandle_t * handle); +static inline void halDphyLane1HsCountdownSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLane1HsCountdownGet (halDphyHandle_t * handle); +static inline void halDphyLane1RxCalibSet (halDphyHandle_t * handle, uint32_t data); +static inline uint32_t halDphyLane1RxCalibGet (halDphyHandle_t * handle); + +// TODO + +// CSI2 HAL functions definition +static inline uint32_t halCsi2BaseAddrGet (halCsi2Handle_t * handle) { + return (uint32_t) (handle); +} + +static inline void halCsi2CfgSet (halCsi2Handle_t * handle, uint32_t data) { + handle->cfg = data; +} + +static inline uint32_t halCsi2CfgGet (halCsi2Handle_t * handle) { + return handle->cfg; +} + +static inline uint32_t halCsi2ErrMsb1Get (halCsi2Handle_t * handle) { + return handle->err_msb1; +} + +static inline uint32_t halCsi2ErrMsbGet (halCsi2Handle_t * handle) { + return handle->err_msb; +} + +static inline uint32_t halCsi2ErrLsbGet (halCsi2Handle_t * handle) { + return handle->err_lsb; +} + +static inline void halCsi2HsRxTimeoutMsb2Set (halCsi2Handle_t * handle, uint32_t data) { + handle->hs_rx_timeout_msb2 = data; +} + +static inline uint32_t halCsi2HsRxTimeoutMsb2Get (halCsi2Handle_t * handle) { + return handle->hs_rx_timeout_msb2; +} + +static inline void halCsi2HsRxTimeoutMsb1Set (halCsi2Handle_t * handle, uint32_t data) { + handle->hs_rx_timeout_msb1 = data; +} + +static inline uint32_t halCsi2HsRxTimeoutMsb1Get (halCsi2Handle_t * handle) { + return handle->hs_rx_timeout_msb1; +} + +static inline void halCsi2HsRxTimeoutLsbSet (halCsi2Handle_t * handle, uint32_t data) { + handle->hs_rx_timeout_lsb = data; +} + +static inline uint32_t halCsi2HsRxTimeoutLsbGet (halCsi2Handle_t * handle) { + return handle->hs_rx_timeout_lsb; +} + +static inline void halCsi2VcCfgSet (halCsi2Handle_t * handle, uint32_t data) { + handle->vccfg = data; +} + +static inline uint32_t halCsi2VcCfgGet (halCsi2Handle_t * handle) { + return handle->vccfg; +} + +static inline void halCsi2PolaritySet (halCsi2Handle_t * handle, uint32_t data) { + handle->polarity = data; +} + +static inline uint32_t halCsi2PolarityGet (halCsi2Handle_t * handle) { + return handle->polarity; +} + +static inline void halCsi2CciAddressSet (halCsi2Handle_t * handle, uint32_t data) { + handle->cci_addr = data; +} + +static inline uint32_t halCsi2CciAddressGet (halCsi2Handle_t * handle) { + return handle->cci_addr; +} + +static inline void halCsi2CciWriteDataSet (halCsi2Handle_t * handle, uint32_t data) { + handle->cci_wr_data = data; +} + +static inline uint32_t halCsi2CciWriteDataGet (halCsi2Handle_t * handle) { + return handle->cci_wr_data; +} + +static inline uint32_t halCsi2CciReadDataGet (halCsi2Handle_t * handle) { + return handle->cci_rd_data; +} + +static inline void halCsi2CciReadWriteSet (halCsi2Handle_t * handle, uint32_t data) { + handle->cci_read_write = data; +} + +static inline uint32_t halCsi2CciReadWriteGet (halCsi2Handle_t * handle) { + return handle->cci_read_write; +} + +static inline uint32_t halCsi2CciStatusGet (halCsi2Handle_t * handle) { + return handle->cci_status; +} + +static inline void halCsi2CciDeviceAddressSet (halCsi2Handle_t * handle, uint32_t data) { + handle->cci_device_addr = data; +} + +static inline uint32_t halCsi2CciDeviceAddressGet (halCsi2Handle_t * handle) { + return handle->cci_device_addr; +} + +static inline uint32_t halCsi2UlpsStatusGet (halCsi2Handle_t * handle) { + return handle->ulps_status; +} + + + + +// DPHY HAL functions definition +static inline uint32_t halDphyBaseAddrGet (halDphyHandle_t * handle) { + return (uint32_t) (handle); +} + +static inline void halDphyLaneEnableSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_enable = data; +} + +static inline uint32_t halDphyLaneEnableGet (halDphyHandle_t * handle) { + return handle->lane_enable; +} + +static inline void halDphyResetDigLogicSet (halDphyHandle_t * handle, uint32_t data) { + handle->reset_dig_logic = data; +} + +static inline uint32_t halDphyResetDigLogicGet (halDphyHandle_t * handle) { + return handle->reset_dig_logic; +} + +static inline void halDphyLaneClkHsCountdownSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_ck_hs_countdown = data; +} + +static inline uint32_t halDphyLaneClkHsCountdownGet (halDphyHandle_t * handle) { + return handle->lane_ck_hs_countdown; +} + +static inline void halDphyLaneClkContModeSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_ck_cont_mode = data; +} + +static inline uint32_t halDphyLaneClkContModeGet (halDphyHandle_t * handle) { + return handle->lane_ck_cont_mode; +} + +static inline void halDphyLaneClkRxCalibSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_ck_rx_calib_enable = data; +} + +static inline uint32_t halDphyLaneClkRxCalibGet (halDphyHandle_t * handle) { + return handle->lane_ck_rx_calib_enable; +} + +static inline void halDphyLane0HsCountdownSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_0_hs_countdown = data; +} + +static inline uint32_t halDphyLane0HsCountdownGet (halDphyHandle_t * handle) { + return handle->lane_0_hs_countdown; +} + +static inline void halDphyLane0RxCalibSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_0_rx_calib_enable = data; +} + +static inline uint32_t halDphyLane0RxCalibGet (halDphyHandle_t * handle) { + return handle->lane_0_rx_calib_enable; +} + +static inline void halDphyLane1HsCountdownSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_1_hs_countdown = data; +} + +static inline uint32_t halDphyLane1HsCountdownGet (halDphyHandle_t * handle) { + return handle->lane_1_hs_countdown; +} + +static inline void halDphyLane1RxCalibSet (halDphyHandle_t * handle, uint32_t data) { + handle->lane_1_rx_calib_enable = data; +} + +static inline uint32_t halDphyLane1RxCalibGet (halDphyHandle_t * handle) { + return handle->lane_1_rx_calib_enable; +} + + +#endif \ No newline at end of file diff --git a/sw/pulp-sdk/hal/include/hal/xne/xne_v1.h b/sw/pulp-sdk/hal/include/hal/xne/xne_v1.h new file mode 100644 index 0000000..80a685e --- /dev/null +++ b/sw/pulp-sdk/hal/include/hal/xne/xne_v1.h @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_XNE_XNE_V1_H__ +#define __HAL_XNE_XNE_V1_H__ + +#include "hal/pulp.h" +#include "archi/xne/xne_v1.h" + +#if XNE_VERSION != 1 + #error This file must be included only with XNE version 1. +#endif + +/* + * Control and generic configuration register layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0000 | 31: 0 | 0xffffffff || TRIGGER + * 1 | 0x0004 | 31: 0 | 0xffffffff || ACQUIRE + * 2 | 0x0008 | 31: 0 | 0xffffffff || EVT_ENABLE + * 3 | 0x000c | 31: 0 | 0xffffffff || STATUS + * 4 | 0x0010 | 31: 0 | 0xffffffff || RUNNING_JOB + * 5 | 0x0014 | 31: 0 | 0xffffffff || SOFT_CLEAR + * 6-7 | | | || Reserved + * 8 | 0x0020 | 31: 0 | 0xffffffff || BYTECODE[31:0] + * 9 | 0x0024 | 31: 0 | 0xffffffff || BYTECODE[63:32] + * 10 | 0x0028 | 31: 0 | 0xffffffff || BYTECODE[95:64] + * 11 | 0x002c | 31: 0 | 0xffffffff || BYTECODE[127:96] + * 12 | 0x0030 | 31: 0 | 0xffffffff || BYTECODE[159:128] + * 13 | 0x0034 | 31:16 | 0xffff0000 || LOOPS[15:0] + * | | 15: 0 | 0x0000ffff || BYTECODE[175:160] + * 14 | 0x0038 | 31: 0 | 0xffffffff || LOOPS[47:16] + * 15 | 0x003c | 31: 0 | 0xffffffff || Reserved + * ================================================================================ + * + * Job-dependent registers layout + * ================================================================================ + * # reg | offset | bits | bitmask || content + * -------+----------+---------+--------------++----------------------------------- + * 0 | 0x0040 | 31: 0 | 0xffffffff || X_ADDR + * 1 | 0x0044 | 31: 0 | 0xffffffff || W_ADDR + * 2 | 0x0048 | 31: 0 | 0xffffffff || Y_ADDR + * 3 | 0x004c | 31:24 | 0xff000000 || UCODE_STATIC0.w + * | | 23:16 | 0x00ff0000 || UCODE_STATIC0.h + * | | 15: 8 | 0x0000ff00 || UCODE_STATIC0.ow + * | | 7: 0 | 0x000000ff || UCODE_STATIC0.oh + * 4 | 0x0050 | 31:24 | 0xff000000 || UCODE_STATIC1.fs0 + * | | 23:16 | 0x00ff0000 || UCODE_STATIC1.fs1 + * | | 7: 0 | 0x000000ff || UCODE_STATIC1.acc + * 5 | 0x0054 | 27:16 | 0x0fff0000 || UCODE_STATIC2.nif + * | | 11: 0 | 0x00000fff || UCODE_STATIC2.nof + * 6 | 0x0058 | 31: 0 | 0xffffffff || TAU_ADDR + * 7 | 0x005c | 3: 0 | 0x0000000f || TAU_SHIFT + * ================================================================================ + * + */ + +/* LOW-LEVEL HAL */ +#if PULP_CHIP == CHIP_QUENTIN + #define XNE_ADDR_BASE ARCHI_FC_HWPE_ADDR +#else + #define XNE_ADDR_BASE HWCE_BASE_ADDR +#endif +#define XNE_ADDR_SPACE 0x00000100 + +// For all the following functions we use __builtin_pulp_OffsetedWrite and __builtin_pulp_OffsetedRead +// instead of classic load/store because otherwise the compiler is not able to correctly factorize +// the XNE base in case several accesses are done, ending up with twice more code + +#if defined(__riscv__) && !defined(RV_ISA_RV32) +#define XNE_WRITE(value, offset) __builtin_pulp_OffsetedWrite(value, (int *)XNE_ADDR_BASE, offset) +#define XNE_READ(offset) __builtin_pulp_OffsetedRead((int *)XNE_ADDR_BASE, offset) +#else +#define XNE_WRITE(value, offset) pulp_write32(XNE_ADDR_BASE + (offset), value) +#define XNE_READ(offset) pulp_read32(XNE_ADDR_BASE + (offset)) +#endif + +static inline void xne_bytecode_set(unsigned int offs, unsigned int value) { + XNE_WRITE(value, XNE_BYTECODE+offs); +} + +static inline void xne_x_addr_set(unsigned int value) { + XNE_WRITE(value, XNE_X_ADDR); +} + +static inline void xne_w_addr_set(unsigned int value) { + XNE_WRITE(value, XNE_W_ADDR); +} + +static inline void xne_y_addr_set(unsigned int value) { + XNE_WRITE(value, XNE_Y_ADDR); +} + +static inline void xne_ucode_static0_set(unsigned int value) { + XNE_WRITE(value, XNE_UCODE_STATIC0); +} + +static inline void xne_ucode_static1_set(unsigned int value) { + XNE_WRITE(value, XNE_UCODE_STATIC1); +} + +static inline void xne_ucode_static2_set(unsigned int value) { + XNE_WRITE(value, XNE_UCODE_STATIC2); +} + +static inline void xne_tau_addr_set(unsigned int value) { + XNE_WRITE(value, XNE_TAU_ADDR); +} + +static inline void xne_tau_shift_set(unsigned int value) { + XNE_WRITE(value, XNE_TAU_SHIFT); +} + +static inline unsigned int xne_ucode_static0_value( + unsigned char h, + unsigned char w, + unsigned char oh, + unsigned char ow +) { + unsigned int res = 0; +#if defined(__riscv__) && !defined(RV_ISA_RV32) + res = __builtin_bitinsert(0, w, 8, 24); + res = __builtin_bitinsert(res, h, 8, 16); + res = __builtin_bitinsert(res, ow, 8, 8); + res = __builtin_bitinsert(res, oh, 8, 0); +#else + res |= ((w & 0xff) << 24) | + ((h & 0xff) << 16) | + ((ow & 0xff) << 8) | + ((oh & 0xff)); +#endif + return res; +} + +static inline unsigned int xne_ucode_static1_value( + unsigned char fs0, + unsigned char fs1, + unsigned char acc +) { + unsigned int res = 0; +#if defined(__riscv__) && !defined(RV_ISA_RV32) + res = __builtin_bitinsert(0, fs0, 8, 24); + res = __builtin_bitinsert(res, fs1, 8, 16); + res = __builtin_bitinsert(res, acc, 8, 0); +#else + res |= ((fs0 & 0xff) << 24) | + ((fs1 & 0xff) << 16) | + ((acc & 0xff)); +#endif + return res; +} + +static inline unsigned int xne_ucode_static2_value( + unsigned short nif, + unsigned short nof +) { + unsigned int res = 0; +#if defined(__riscv__) && !defined(RV_ISA_RV32) + res = __builtin_bitinsert(0, nif, 16, 16); + res = __builtin_bitinsert(res, nof, 16, 0); +#else + res |= ((nif & 0xffff) << 16) | + ((nof & 0xffff)); +#endif + return res; +} + +static inline unsigned int xne_tau_shift_value( + unsigned char shift +) { + unsigned int res = 0; +#if defined(__riscv__) && !defined(RV_ISA_RV32) + res = __builtin_bitinsert(0, shift, 4, 0); +#else + res |= shift << 4; +#endif + return res; +} + +static inline void xne_wait_event() { +#if PULP_CHIP != CHIP_QUENTIN + eu_evt_maskWaitAndClr(1 << PLP_EVT_ACC0); +#endif +} + +static inline void xne_trigger_job() { + XNE_WRITE(0, XNE_TRIGGER); +} + +static inline int xne_acquire_job() { + return XNE_READ(XNE_ACQUIRE); +} + +static inline unsigned int xne_get_status() { + return XNE_READ(XNE_STATUS); +} + +static inline void xne_soft_clear() { + volatile int i; + XNE_WRITE(0, XNE_SOFT_CLEAR); +} + +static inline void plp_xne_enable() { +#ifdef ARCHI_HAS_CLUSTER + *(volatile int*) (EOC_UNIT_BASE_ADDR + (3 << 3)) |= 0xc00; +#endif +} + +static inline void plp_xne_disable() { +#ifdef ARCHI_HAS_CLUSTER + *(volatile int*) (EOC_UNIT_BASE_ADDR + (3 << 3)) &= ~0xc00; +#endif +} + +#endif /* __HAL_XNE_V1_H__ */ + diff --git a/sw/pulp-sdk/hal/src/hal/mailbox/mailbox_v0.c b/sw/pulp-sdk/hal/src/hal/mailbox/mailbox_v0.c new file mode 100644 index 0000000..eabcc4c --- /dev/null +++ b/sw/pulp-sdk/hal/src/hal/mailbox/mailbox_v0.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/mailbox/mailbox_v0.h" +#include "rt/rt_time.h" // rt_time_wait_cycles() + +int mailbox_read(unsigned int* const ptr) +{ + uint32_t status; + + if ( mailbox_status_read() & 0x1 ) + { + status = 1; + // wait for not empty + while ( status ) + { + rt_time_wait_cycles(500); + status = mailbox_status_read() & 0x1; + } + } + + *ptr = mailbox_data_read(); + return MAILBOX_VALID; +} + +int mailbox_read_timed(unsigned int* const ptr, const unsigned int t) +{ + uint32_t status; + + if ( mailbox_status_read() & 0x1 ) + { + volatile uint32_t timeout = t; + status = 1; + // wait for not empty or timeout + while ( status && (timeout > 0) ) + { + rt_time_wait_cycles(500); + timeout--; + status = mailbox_status_read() & 0x1; + } + if ( status ) + return MAILBOX_FAIL; + } + + *ptr = mailbox_data_read(); + return MAILBOX_VALID; +} + +int mailbox_write(const unsigned int value) +{ + uint32_t status; + + if ( mailbox_status_read() & 0x2 ) + { + status = 1; + // wait for not full + while ( status ) { + rt_time_wait_cycles(500); + status = mailbox_status_read() & 0x2; + } + if ( status ) + return MAILBOX_FAIL; + } + + mailbox_data_write(value); + return MAILBOX_VALID; +} diff --git a/sw/pulp-sdk/hal/src/hal/rab/rab_v1.c b/sw/pulp-sdk/hal/src/hal/rab/rab_v1.c new file mode 100644 index 0000000..055e320 --- /dev/null +++ b/sw/pulp-sdk/hal/src/hal/rab/rab_v1.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2017 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/rab/rab_v1.h" +#include "archi-host/pgtable_hwdef.h" // virt_pfn2addr() +#include // printf() identifiers +#include "stdio.h" // printf() + +int print_rab_cfg_val(const rab_cfg_val_t* const cfg_val) +{ + printf("va_start: "); + print_virt_addr(&(cfg_val->va_start)); + printf(", va_end: "); + print_virt_addr(&(cfg_val->va_end)); + printf(", offset: "); + print_phys_addr(&(cfg_val->offset)); + printf(", flags: 0x%" PRIx8, cfg_val->flags); + return 0; +} + +int print_rab_cfg(const rab_cfg_t* const begin, const rab_cfg_t* const end, + const unsigned only_valid) +{ + unsigned i = 0; + for (const rab_cfg_t* cfg_rptr = begin; cfg_rptr < end; ++cfg_rptr, ++i) { + rab_cfg_val_t cfg_val; + read_rab_cfg_val(&cfg_val, cfg_rptr); + if (!only_valid || cfg_val.flags != 0) { + printf("[%02u]: ", i); + print_rab_cfg_val(&cfg_val); + printf("\n"); + } + } + + return 0; +} + +int print_rab_cfg_l2_val(const rab_cfg_l2_varam_t* const varam_ptr, + const rab_cfg_l2_param_t* const param_ptr, const rab_cfg_l2_val_t* const cfg_val, + const unsigned char entry) +{ + const virt_addr_t virt_addr = virt_pfn2addr(cfg_val->virt_pfn); + phys_addr_t phys_addr; + phys_pfn2addr(&phys_addr, cfg_val->phys_pfn); + + printf("va: "); + print_virt_addr(&virt_addr); + printf(", set %d, entry %d", (int)cfg_val->set, (int)entry); + printf(" @ varam: 0x%" PRIx32, (unsigned long)varam_ptr); + printf(", pa: "); + print_phys_addr(&phys_addr); + printf(" @ param: 0x%" PRIx32, (unsigned long)param_ptr); + printf(", flags: 0x%" PRIx8, cfg_val->flags); + return 0; +} diff --git a/sw/pulp-sdk/hal/src/hal/tryx/tryx_v1.c b/sw/pulp-sdk/hal/src/hal/tryx/tryx_v1.c new file mode 100644 index 0000000..feb1c7c --- /dev/null +++ b/sw/pulp-sdk/hal/src/hal/tryx/tryx_v1.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/tryx/tryx_v1.h" + +#include "pulp.h" // pulp_read32(), eu_evt_mask() +#include "stdio.h" // printf() + +void pulp_tryx_slowpath() +{ + int coreid = get_core_id(); + unsigned int mask; + + // save event mask + mask = pulp_read32(ARCHI_EU_DEMUX_ADDR + EU_CORE_MASK); + + // only listen to wake-up event + eu_evt_mask(EVTMASK_RAB_WAKEUP); + + // go to sleep, wait and clear + evt_read32(ARCHI_EU_DEMUX_ADDR, EU_CORE_EVENT_WAIT_CLEAR); + + // restore the event mask + eu_evt_mask(mask); + + return; +} diff --git a/sw/pulp-sdk/kernel/riscv/rt/crt0.S b/sw/pulp-sdk/kernel/riscv/rt/crt0.S new file mode 100644 index 0000000..6319140 --- /dev/null +++ b/sw/pulp-sdk/kernel/riscv/rt/crt0.S @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Authors: + * Germain Haugou, ETH (germain.haugou@iis.ee.ethz.ch) + * Salvatore Di Girolamo, ETH (digirols@inf.ethz.ch) + */ + +#include "archi/pulp.h" +#include "archi/eu/eu_v3.h" + + .section .text + +_entry: + # activate dispatch event + li t0, (1< prog_mem + + .text : + { + . = ALIGN(4); + _stext = .; + *(.text) + *(.text.*) + _etext = .; + *(.lit) + *(.shdata) + _endtext = .; + . = ALIGN(4); + } > prog_mem + + .text.cluster : + { + __cluster_text_start = .; + *(.cluster.text) + *(.cluster.text.*) + __cluster_text_end = .; + . = ALIGN(4); + } > prog_mem + + + .rodata : { + . = ALIGN(4); + *(.rodata); + *(.rodata.*) + *(.srodata); + *(.srodata.*) + *(.eh_frame*) + } > L2 + + .data : { + . = ALIGN(4); + sdata = .; + _sdata = .; + *(.data); + *(.data.*) + *(.sdata); + *(.sdata.*) + *(.heapl2ram) + . = ALIGN(4); + edata = .; + _edata = .; + } > L2 + + .bss : { + . = ALIGN(8); + _bss_start = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > L2 + + .l2_data : { + . = ALIGN(4); + *(.l2_data) + *(.l2_data.*) + *(.data_fc_shared) + *(.data_fc_shared.*) + . = ALIGN(4); + } > L2 + + __l2_data_end = ALIGN(8); + + __cluster_text_size = __cluster_text_end - __cluster_text_start; + + __l2_heap_start = ALIGN(4); + + __l2_heap_size = LENGTH(L2) - __l2_heap_start + ORIGIN(L2); + + + /* Following sections are keeping the cluster data + * in L2 until the cluster is powered up */ + + _l1_preload_start_inL2 = ALIGN(4); + + .data_tiny_l1 : + { + . = ALIGN(4); + _l1_preload_start = .; + *(.data_tiny_l1) + *(.data_tiny_l1.*) + *(.data_alias_l1) + *(.data_alias_l1.*) + } > L1_aliased + + .stack : { + . = ALIGN(4); + . = ALIGN(16); + . = . + 0x400; + stack = .; + } > L1 + + + _l1_preload_size = SIZEOF(.data_tiny_l1); + + .l2_handler_data : { + . = ALIGN(4); + KEEP(*(.l2_handler_data)) + } > L2_handler_data + + .l2_queue : { + . = ALIGN(4); + } > L2_queue +} + diff --git a/sw/pulp-sdk/runtime/libs/io/io.c b/sw/pulp-sdk/runtime/libs/io/io.c new file mode 100644 index 0000000..b38485a --- /dev/null +++ b/sw/pulp-sdk/runtime/libs/io/io.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Authors: Germain Haugou, ETH (germain.haugou@iis.ee.ethz.ch) + */ + +#include "tinyprintf.h" +#include +#include "hal/pulp.h" +#include + +static int errno; +int *__errno() { return &errno; } + +int strcmp(const char *s1, const char *s2) +{ + while (*s1 != '\0' && *s1 == *s2) + { + s1++; + s2++; + } + + return (*(unsigned char *) s1) - (*(unsigned char *) s2); +} + +int strncmp(const char *s1, const char *s2, size_t n) +{ + if (n == 0) + return 0; + + while (n-- != 0 && *s1 == *s2) + { + if (n == 0 || *s1 == '\0') + break; + s1++; + s2++; + } + + return (*(unsigned char *) s1) - (*(unsigned char *) s2); +} + +size_t strlen(const char *str) +{ + const char *start = str; + + while (*str) + str++; + return str - start; +} + +int memcmp(const void *m1, const void *m2, size_t n) +{ + unsigned char *s1 = (unsigned char *) m1; + unsigned char *s2 = (unsigned char *) m2; + + while (n--) + { + if (*s1 != *s2) + { + return *s1 - *s2; + } + s1++; + s2++; + } + return 0; +} + +void *memset(void *m, int c, size_t n) +{ + char *s = (char *)m; + while (n--) + *s++ = (char) c; + + return m; +} + +void *memcpy(void *dst0, const void *src0, size_t len0) +{ + char *dst = (char *) dst0; + char *src = (char *) src0; + + void *save = dst0; + + while (len0--) + { + *dst++ = *src++; + } + + return save; +} + +static void __rt_putc_stdout(char c) +{ + //*(uint32_t*)(long)(0x1A104000 + (hal_core_id() << 3) + (hal_cluster_id() << 7)) = c; + *(uint32_t*)(long)(0x1A104000) = c; + // Poll while microblaze debug module's FIFo is full + //while (pulp_read8(ARCHI_STDOUT_ADDR + 0x8) & 0x8); + //*(uint32_t *)(long)(ARCHI_STDOUT_ADDR + STDOUT_PUTC_OFFSET + 0x4) = c; +} + +static void tfp_putc(void *data, char c) { + __rt_putc_stdout(c); +} + +int printf(const char *fmt, ...) { + + va_list va; + va_start(va, fmt); + tfp_format(NULL, tfp_putc, fmt, va); + va_end(va); + + return 0; +} + +int puts(const char *s) { + + char c; + do { + c = *s; + if (c == 0) { + tfp_putc(NULL, '\n'); + break; + } + tfp_putc(NULL, c); + s++; + } while(1); + + return 0; +} + +int putchar(int c) { + + tfp_putc(NULL, c); + + return c; +} + diff --git a/sw/pulp-sdk/runtime/libs/io/tinyprintf.c b/sw/pulp-sdk/runtime/libs/io/tinyprintf.c new file mode 100644 index 0000000..66e574b --- /dev/null +++ b/sw/pulp-sdk/runtime/libs/io/tinyprintf.c @@ -0,0 +1,539 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +File: tinyprintf.c + +Copyright (C) 2004 Kustaa Nyholm + +This library is free software; you can redistribute it and/or +modify it under the terms of the GNU Lesser General Public +License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public +License along with this library; if not, write to the Free Software +Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +*/ + +#include "tinyprintf.h" + + +/* + * Configuration + */ + +/* Enable long int support */ +#define PRINTF_LONG_SUPPORT + +/* Enable long long int support (implies long int support) */ +#define PRINTF_LONG_LONG_SUPPORT + +/* Enable %z (size_t) support */ +#define PRINTF_SIZE_T_SUPPORT + +/* + * Configuration adjustments + */ +#ifdef PRINTF_SIZE_T_SUPPORT +#include +#endif + +#ifdef PRINTF_LONG_LONG_SUPPORT +# define PRINTF_LONG_SUPPORT +#endif + +/* __SIZEOF___ defined at least by gcc */ +#ifdef __SIZEOF_POINTER__ +# define SIZEOF_POINTER __SIZEOF_POINTER__ +#endif +#ifdef __SIZEOF_LONG_LONG__ +# define SIZEOF_LONG_LONG __SIZEOF_LONG_LONG__ +#endif +#ifdef __SIZEOF_LONG__ +# define SIZEOF_LONG __SIZEOF_LONG__ +#endif +#ifdef __SIZEOF_INT__ +# define SIZEOF_INT __SIZEOF_INT__ +#endif + +#ifdef __GNUC__ +# define _TFP_GCC_NO_INLINE_ __attribute__ ((noinline)) +#else +# define _TFP_GCC_NO_INLINE_ +#endif + +/* + * Implementation + */ +struct param { + char lz:1; /**< Leading zeros */ + char alt:1; /**< alternate form */ + char uc:1; /**< Upper case (for base16 only) */ + char align_left:1; /**< 0 == align right (default), 1 == align left */ + unsigned int width; /**< field width */ + char sign; /**< The sign to display (if any) */ + unsigned int base; /**< number base (e.g.: 8, 10, 16) */ + char *bf; /**< Buffer to output */ +}; + + +#ifdef PRINTF_LONG_LONG_SUPPORT +static void _TFP_GCC_NO_INLINE_ ulli2a( + unsigned long long int num, struct param *p) +{ + int n = 0; + unsigned long long int d = 1; + char *bf = p->bf; + while (num / d >= p->base) + d *= p->base; + while (d != 0) { + int dgt = num / d; + num %= d; + d /= p->base; + if (n || dgt > 0 || d == 0) { + *bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10); + ++n; + } + } + *bf = 0; +} + +static void lli2a(long long int num, struct param *p) +{ + if (num < 0) { + num = -num; + p->sign = '-'; + } + ulli2a(num, p); +} +#endif + +#ifdef PRINTF_LONG_SUPPORT +static void uli2a(unsigned long int num, struct param *p) +{ + int n = 0; + unsigned long int d = 1; + char *bf = p->bf; + while (num / d >= p->base) + d *= p->base; + while (d != 0) { + int dgt = num / d; + num %= d; + d /= p->base; + if (n || dgt > 0 || d == 0) { + *bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10); + ++n; + } + } + *bf = 0; +} + +static void li2a(long num, struct param *p) +{ + if (num < 0) { + num = -num; + p->sign = '-'; + } + uli2a(num, p); +} +#endif + +static void ui2a(unsigned int num, struct param *p) +{ + int n = 0; + unsigned int d = 1; + char *bf = p->bf; + while (num / d >= p->base) + d *= p->base; + while (d != 0) { + int dgt = num / d; + num %= d; + d /= p->base; + if (n || dgt > 0 || d == 0) { + *bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10); + ++n; + } + } + *bf = 0; +} + +static void i2a(int num, struct param *p) +{ + if (num < 0) { + num = -num; + p->sign = '-'; + } + ui2a(num, p); +} + +static int a2d(char ch) +{ + if (ch >= '0' && ch <= '9') + return ch - '0'; + else if (ch >= 'a' && ch <= 'f') + return ch - 'a' + 10; + else if (ch >= 'A' && ch <= 'F') + return ch - 'A' + 10; + else + return -1; +} + +static char a2u(char ch, const char **src, int base, unsigned int *nump) +{ + const char *p = *src; + unsigned int num = 0; + int digit; + while ((digit = a2d(ch)) >= 0) { + if (digit > base) + break; + num = num * base + digit; + ch = *p++; + } + *src = p; + *nump = num; + return ch; +} + +static void putchw(void *putp, putcf putf, struct param *p) +{ + char ch; + int n = p->width; + char *bf = p->bf; + + /* Number of filling characters */ + while (*bf++ && n > 0) + n--; + if (p->sign) + n--; + if (p->alt && p->base == 16) + n -= 2; + else if (p->alt && p->base == 8) + n--; + + /* Fill with space to align to the right, before alternate or sign */ + if (!p->lz && !p->align_left) { + while (n-- > 0) + putf(putp, ' '); + } + + /* print sign */ + if (p->sign) + putf(putp, p->sign); + + /* Alternate */ + if (p->alt && p->base == 16) { + putf(putp, '0'); + putf(putp, (p->uc ? 'X' : 'x')); + } else if (p->alt && p->base == 8) { + putf(putp, '0'); + } + + /* Fill with zeros, after alternate or sign */ + if (p->lz) { + while (n-- > 0) + putf(putp, '0'); + } + + /* Put actual buffer */ + bf = p->bf; + while ((ch = *bf++)) + putf(putp, ch); + + /* Fill with space to align to the left, after string */ + if (!p->lz && p->align_left) { + while (n-- > 0) + putf(putp, ' '); + } +} + +void tfp_format(void *putp, putcf putf, const char *fmt, va_list va) +{ + struct param p; +#ifdef PRINTF_LONG_SUPPORT + char bf[23]; /* long = 64b on some architectures */ +#else + char bf[12]; /* int = 32b on some architectures */ +#endif + char ch; + p.bf = bf; + + while ((ch = *(fmt++))) { + if (ch != '%') { + putf(putp, ch); + } else { +#ifdef PRINTF_LONG_SUPPORT + char lng = 0; /* 1 for long, 2 for long long */ +#endif + /* Init parameter struct */ + p.lz = 0; + p.alt = 0; + p.width = 0; + p.align_left = 0; + p.sign = 0; + + /* Flags */ + while ((ch = *(fmt++))) { + switch (ch) { + case '-': + p.align_left = 1; + continue; + case '0': + p.lz = 1; + continue; + case '#': + p.alt = 1; + continue; + default: + break; + } + break; + } + + /* Width */ + if (ch >= '0' && ch <= '9') { + ch = a2u(ch, &fmt, 10, &(p.width)); + } + + /* We accept 'x.y' format but don't support it completely: + * we ignore the 'y' digit => this ignores 0-fill + * size and makes it == width (ie. 'x') */ + if (ch == '.') { + p.lz = 1; /* zero-padding */ + /* ignore actual 0-fill size: */ + do { + ch = *(fmt++); + } while ((ch >= '0') && (ch <= '9')); + } + +#ifdef PRINTF_SIZE_T_SUPPORT +# ifdef PRINTF_LONG_SUPPORT + if (ch == 'z') { + ch = *(fmt++); + if (sizeof(size_t) == sizeof(unsigned long int)) + lng = 1; +# ifdef PRINTF_LONG_LONG_SUPPORT + else if (sizeof(size_t) == sizeof(unsigned long long int)) + lng = 2; +# endif + } else +# endif +#endif + +#ifdef PRINTF_LONG_SUPPORT + if (ch == 'l') { + ch = *(fmt++); + lng = 1; +#ifdef PRINTF_LONG_LONG_SUPPORT + if (ch == 'l') { + ch = *(fmt++); + lng = 2; + } +#endif + } +#endif + switch (ch) { + case 0: + goto abort; + case 'u': + p.base = 10; +#ifdef PRINTF_LONG_SUPPORT +#ifdef PRINTF_LONG_LONG_SUPPORT + if (2 == lng) + ulli2a(va_arg(va, unsigned long long int), &p); + else +#endif + if (1 == lng) + uli2a(va_arg(va, unsigned long int), &p); + else +#endif + ui2a(va_arg(va, unsigned int), &p); + putchw(putp, putf, &p); + break; + case 'd': + case 'i': + p.base = 10; +#ifdef PRINTF_LONG_SUPPORT +#ifdef PRINTF_LONG_LONG_SUPPORT + if (2 == lng) + lli2a(va_arg(va, long long int), &p); + else +#endif + if (1 == lng) + li2a(va_arg(va, long int), &p); + else +#endif + i2a(va_arg(va, int), &p); + putchw(putp, putf, &p); + break; +#ifdef SIZEOF_POINTER + case 'p': + p.alt = 1; +# if defined(SIZEOF_INT) && SIZEOF_POINTER <= SIZEOF_INT + lng = 0; +# elif defined(SIZEOF_LONG) && SIZEOF_POINTER <= SIZEOF_LONG + lng = 1; +# elif defined(SIZEOF_LONG_LONG) && SIZEOF_POINTER <= SIZEOF_LONG_LONG + lng = 2; +# endif +#endif +#if defined(__GNUC__) && __GNUC__ >= 7 + __attribute__ ((fallthrough)); +#endif + case 'x': + case 'X': + p.base = 16; + p.uc = (ch == 'X')?1:0; +#ifdef PRINTF_LONG_SUPPORT +#ifdef PRINTF_LONG_LONG_SUPPORT + if (2 == lng) + ulli2a(va_arg(va, unsigned long long int), &p); + else +#endif + if (1 == lng) + uli2a(va_arg(va, unsigned long int), &p); + else +#endif + ui2a(va_arg(va, unsigned int), &p); + putchw(putp, putf, &p); + break; + case 'o': + p.base = 8; + ui2a(va_arg(va, unsigned int), &p); + putchw(putp, putf, &p); + break; + case 'c': + putf(putp, (char)(va_arg(va, int))); + break; + case 's': + p.bf = va_arg(va, char *); + putchw(putp, putf, &p); + p.bf = bf; + break; + case '%': + putf(putp, ch); + default: + break; + } + } + } + abort:; +} + +#if TINYPRINTF_DEFINE_TFP_PRINTF +static putcf stdout_putf; +static void *stdout_putp; + +void init_printf(void *putp, putcf putf) +{ + stdout_putf = putf; + stdout_putp = putp; +} + +void tfp_printf(char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + tfp_format(stdout_putp, stdout_putf, fmt, va); + va_end(va); +} +#endif + +#if TINYPRINTF_DEFINE_TFP_SPRINTF +struct _vsnprintf_putcf_data +{ + size_t dest_capacity; + char *dest; + size_t num_chars; +}; + +static void _vsnprintf_putcf(void *p, char c) +{ + struct _vsnprintf_putcf_data *data = (struct _vsnprintf_putcf_data*)p; + if (data->num_chars < data->dest_capacity) + data->dest[data->num_chars] = c; + data->num_chars ++; +} + +int tfp_vsnprintf(char *str, size_t size, const char *format, va_list ap) +{ + struct _vsnprintf_putcf_data data; + + if (size < 1) + return 0; + + data.dest = str; + data.dest_capacity = size-1; + data.num_chars = 0; + tfp_format(&data, _vsnprintf_putcf, format, ap); + + if (data.num_chars < data.dest_capacity) + data.dest[data.num_chars] = '\0'; + else + data.dest[data.dest_capacity] = '\0'; + + return data.num_chars; +} + +int tfp_snprintf(char *str, size_t size, const char *format, ...) +{ + va_list ap; + int retval; + + va_start(ap, format); + retval = tfp_vsnprintf(str, size, format, ap); + va_end(ap); + return retval; +} + +struct _vsprintf_putcf_data +{ + char *dest; + size_t num_chars; +}; + +static void _vsprintf_putcf(void *p, char c) +{ + struct _vsprintf_putcf_data *data = (struct _vsprintf_putcf_data*)p; + data->dest[data->num_chars++] = c; +} + +int tfp_vsprintf(char *str, const char *format, va_list ap) +{ + struct _vsprintf_putcf_data data; + data.dest = str; + data.num_chars = 0; + tfp_format(&data, _vsprintf_putcf, format, ap); + data.dest[data.num_chars] = '\0'; + return data.num_chars; +} +int sprintf(char *str, const char *format, ...) +{ + va_list ap; + int retval; + va_start(ap, format); + retval = tfp_vsprintf(str, format, ap); + va_end(ap); + return retval; +} + +#endif diff --git a/sw/pulp-sdk/runtime/libs/io/tinyprintf.h b/sw/pulp-sdk/runtime/libs/io/tinyprintf.h new file mode 100644 index 0000000..ab6c070 --- /dev/null +++ b/sw/pulp-sdk/runtime/libs/io/tinyprintf.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* +File: tinyprintf.h + +Copyright (C) 2004 Kustaa Nyholm + +This library is free software; you can redistribute it and/or +modify it under the terms of the GNU Lesser General Public +License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public +License along with this library; if not, write to the Free Software +Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +This library is really just two files: 'tinyprintf.h' and 'tinyprintf.c'. + +They provide a simple and small (+400 loc) printf functionality to +be used in embedded systems. + +I've found them so useful in debugging that I do not bother with a +debugger at all. + +They are distributed in source form, so to use them, just compile them +into your project. + +Two printf variants are provided: printf and the 'sprintf' family of +functions ('snprintf', 'sprintf', 'vsnprintf', 'vsprintf'). + +The formats supported by this implementation are: +'c' 'd' 'i' 'o' 'p' 'u' 's' 'x' 'X'. + +Zero padding and field width are also supported. + +If the library is compiled with 'PRINTF_SUPPORT_LONG' defined, then +the long specifier is also supported. Note that this will pull in some +long math routines (pun intended!) and thus make your executable +noticeably longer. Likewise with 'PRINTF_LONG_LONG_SUPPORT' for the +long long specifier, and with 'PRINTF_SIZE_T_SUPPORT' for the size_t +specifier. + +The memory footprint of course depends on the target CPU, compiler and +compiler options, but a rough guesstimate (based on a H8S target) is about +1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space. +Not too bad. Your mileage may vary. By hacking the source code you can +get rid of some hundred bytes, I'm sure, but personally I feel the balance of +functionality and flexibility versus code size is close to optimal for +many embedded systems. + +To use the printf, you need to supply your own character output function, +something like : + +void putc ( void* p, char c) +{ + while (!SERIAL_PORT_EMPTY) ; + SERIAL_PORT_TX_REGISTER = c; +} + +Before you can call printf, you need to initialize it to use your +character output function with something like: + +init_printf(NULL,putc); + +Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc', +the NULL (or any pointer) you pass into the 'init_printf' will eventually be +passed to your 'putc' routine. This allows you to pass some storage space (or +anything really) to the character output function, if necessary. +This is not often needed but it was implemented like that because it made +implementing the sprintf function so neat (look at the source code). + +The code is re-entrant, except for the 'init_printf' function, so it is safe +to call it from interrupts too, although this may result in mixed output. +If you rely on re-entrancy, take care that your 'putc' function is re-entrant! + +The printf and sprintf functions are actually macros that translate to +'tfp_printf' and 'tfp_sprintf' when 'TINYPRINTF_OVERRIDE_LIBC' is set +(default). Setting it to 0 makes it possible to use them along with +'stdio.h' printf's in a single source file. When +'TINYPRINTF_OVERRIDE_LIBC' is set, please note that printf/sprintf are +not function-like macros, so if you have variables or struct members +with these names, things will explode in your face. Without variadic +macros this is the best we can do to wrap these function. If it is a +problem, just give up the macros and use the functions directly, or +rename them. + +It is also possible to avoid defining tfp_printf and/or tfp_sprintf by +clearing 'TINYPRINTF_DEFINE_TFP_PRINTF' and/or +'TINYPRINTF_DEFINE_TFP_SPRINTF' to 0. This allows for example to +export only tfp_format, which is at the core of all the other +functions. + +For further details see source code. + +regs Kusti, 23.10.2004 +*/ + +#ifndef __TFP_PRINTF__ +#define __TFP_PRINTF__ + +#include + +/* Global configuration */ + +#define TINYPRINTF_OVERRIDE_LIBC 0 + +/* Set this to 0 if you do not want to provide tfp_printf */ +#ifndef TINYPRINTF_DEFINE_TFP_PRINTF +# define TINYPRINTF_DEFINE_TFP_PRINTF 1 +#endif + +/* Set this to 0 if you do not want to provide + tfp_sprintf/snprintf/vsprintf/vsnprintf */ +#ifndef TINYPRINTF_DEFINE_TFP_SPRINTF +# define TINYPRINTF_DEFINE_TFP_SPRINTF 1 +#endif + +/* Set this to 0 if you do not want tfp_printf and + tfp_{vsn,sn,vs,s}printf to be also available as + printf/{vsn,sn,vs,s}printf */ +#ifndef TINYPRINTF_OVERRIDE_LIBC +# define TINYPRINTF_OVERRIDE_LIBC 1 +#endif + +/* Optional external types dependencies */ + +#if TINYPRINTF_DEFINE_TFP_SPRINTF +# include /* size_t */ +#endif + +/* Declarations */ + +#ifdef __GNUC__ +# define _TFP_SPECIFY_PRINTF_FMT(fmt_idx,arg1_idx) \ + __attribute__((format (printf, fmt_idx, arg1_idx))) +#else +# define _TFP_SPECIFY_PRINTF_FMT(fmt_idx,arg1_idx) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*putcf) (void *, char); + +/* + 'tfp_format' really is the central function for all tinyprintf. For + each output character after formatting, the 'putf' callback is + called with 2 args: + - an arbitrary void* 'putp' param defined by the user and + passed unmodified from 'tfp_format', + - the character. + The 'tfp_printf' and 'tfp_sprintf' functions simply define their own + callback and pass to it the right 'putp' it is expecting. +*/ +void tfp_format(void *putp, putcf putf, const char *fmt, va_list va); + +#if TINYPRINTF_DEFINE_TFP_SPRINTF +int tfp_vsnprintf(char *str, size_t size, const char *fmt, va_list ap); +int tfp_snprintf(char *str, size_t size, const char *fmt, ...) \ + _TFP_SPECIFY_PRINTF_FMT(3, 4); +int tfp_vsprintf(char *str, const char *fmt, va_list ap); +int tfp_sprintf(char *str, const char *fmt, ...) \ + _TFP_SPECIFY_PRINTF_FMT(2, 3); +# if TINYPRINTF_OVERRIDE_LIBC +# define vsnprintf tfp_vsnprintf +# define snprintf tfp_snprintf +# define vsprintf tfp_vsprintf +# define sprintf tfp_sprintf +# endif +#endif + +#if TINYPRINTF_DEFINE_TFP_PRINTF +void init_printf(void *putp, putcf putf); +void tfp_printf(char *fmt, ...) _TFP_SPECIFY_PRINTF_FMT(1, 2); +# if TINYPRINTF_OVERRIDE_LIBC +# define printf tfp_printf +# endif +#endif + + //void tfp_putc(void *data, char c); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/sw/pulp-sdk/scripts/s19toslm.py b/sw/pulp-sdk/scripts/s19toslm.py new file mode 100755 index 0000000..9b81cf6 --- /dev/null +++ b/sw/pulp-sdk/scripts/s19toslm.py @@ -0,0 +1,209 @@ +#!/usr/bin/python2 + +# //////////////////////////////////////////////////////////////////////////////// +# // Company: Multitherman Laboratory @ DEIS - University of Bologna // +# // Viale Risorgimento 2 40136 // +# // Bologna - fax 0512093785 - // +# // // +# // Engineer: Davide Rossi - davide.rossi@unibo.it // +# // // +# // Additional contributions by: // +# // Andreas Traber - atraber@student.ethz.ch // +# // // +# // Create Date: 05/04/2013 // +# // Design Name: ULPSoC // +# // Project Name: ULPSoC // +# // Language: tcl, now python // +# // // +# // Description: s19 to slm conversion tool for stxp70 cluster compilation // +# // // +# // Revision: // +# // Revision v0.1 - File Created // +# // Revision v0.2 - Modification: Compiler does now generate little endian // +# // directly. revert bytes! // +# // Revision v0.3 - Moved from 128 bit s19 to 8 bit s19 file. This solves our // +# // problems with misaligned addresses in s19 files. // +# // Revision v0.4 - Added TCDM memory initialization // +# // Revision v0.5 - Rewrote the whole thing in python as tcl cannot handle // +# // long file names properly +# //////////////////////////////////////////////////////////////////////////////// + +import sys +import math + + +############################################################################### +# Function to dump single bytes of a string to a file +############################################################################### +def dump_bytes( filetoprint, addr, data_s): + for i in range(0,4,1): + filetoprint.write("@%08X %s\n" % ( addr+i, data_s[i*2:(i+1)*2] )) + + +############################################################################### +# Start of file +############################################################################### +if(len(sys.argv) < 2): + print("Usage s19toslm.py FILENAME") + quit() + +l2_hnd_start = 0x1C000000 +l2_hnd_end = l2_hnd_start + 4*1024*1024 - 1 +l2_pkt_start = l2_hnd_end + 1 +l2_pkt_end = l2_pkt_start + 4*1024*1024 - 1 +l2_hnd_width = 32 +l2_pkt_width = 32 + +prog_mem_start = 0x1D000000 +prog_mem_end = prog_mem_start + 32*1024 - 1 +prog_mem_width = 64 + +#tcdm_banks = 32 +#tcdm_bank_size = 8192 # in words (32 bit) +tcdm_banks = 64 +tcdm_bank_size = 4096 # in words (32 bit) +tcdm_start = 0x10000000 +tcdm_end = tcdm_start + tcdm_banks * tcdm_bank_size * 4 - 1 +tcdm_bank_bits = int(math.log(tcdm_banks, 2)) +tcdm_width = 32 + +############################################################################### +# Parse s19 file +############################################################################### +s19_file = open(sys.argv[1], 'r') +s19_dict = {} + +for line in s19_file: + rec_field = line[:2] + prefix = line[:4] + + if rec_field == "S0" or prefix == "S009" or prefix == "S505" or prefix == "S705" or prefix == "S017" or line == "": + continue + + addr = int("0x%s" % line[4:12], 0) + data = line[12:14] + + s19_dict[addr] = data + +s19_file.close() + +def bytes_to_words(word_width, start_addr, end_addr): + word_dict = {} + num_bytes = word_width / 8 + shamt = int(math.log(num_bytes, 2)) + for addr in s19_dict: + if addr < start_addr or addr > end_addr: + continue + + word_addr = addr >> shamt + if word_addr in word_dict: + data = word_dict[word_addr] + else: + data = '00' * num_bytes + + byte_num = addr % num_bytes + data = list(data) + upper = 2 * (num_bytes - byte_num) + lower = upper - 2 + data[lower:upper] = list(s19_dict[addr]) + data = ''.join(data) + word_dict[word_addr] = data + return word_dict + +slm_dict = {} +for addr in s19_dict: + wordaddr = addr >> 2 + data = "00000000" + + if wordaddr in slm_dict: + data = slm_dict[wordaddr] + + byte = addr % 4 + byte0 = data[0:2] + byte1 = data[2:4] + byte2 = data[4:6] + byte3 = data[6:8] + new = s19_dict[addr] + + if byte == 0: + data = "%s%s%s%s" % (byte0, byte1, byte2, new) + elif byte == 1: + data = "%s%s%s%s" % (byte0, byte1, new, byte3) + elif byte == 2: + data = "%s%s%s%s" % (byte0, new, byte2, byte3) + elif byte == 3: + data = "%s%s%s%s" % (new, byte1, byte2, byte3) + + slm_dict[wordaddr] = data + +# word align all addresses +#l2_start = l2_start >> 2 +#l2_end = l2_end >> 2 +#prog_mem_start = prog_mem_start >> 2 +#prog_mem_end = prog_mem_end >> 2 +tcdm_start = tcdm_start >> 2 +tcdm_end = tcdm_end >> 2 + + +l2_hnd_dict = bytes_to_words(l2_hnd_width, l2_hnd_start, l2_hnd_end) +l2_pkt_dict = bytes_to_words(l2_pkt_width, l2_pkt_start, l2_pkt_end) +prog_mem_dict = bytes_to_words(prog_mem_width, prog_mem_start, prog_mem_end) + + +############################################################################### +# open files +############################################################################### +tcdm_files = {} +for i in range(0, tcdm_banks): + tcdm_files[i] = open("tcdm_bank%d.slm" % i, 'w') +l2_hnd_stim = open("l2_hnd_stim.slm", 'w') +l2_pkt_stim = open("l2_pkt_stim.slm", 'w') +prog_mem_stim = open("prog_mem_stim.slm", 'w') + +############################################################################### +# write the stimuli +############################################################################### +def write_file(f, entries, start_addr, word_width): + num_bytes = word_width / 8 + start_word_addr = start_addr >> int(math.log(num_bytes, 2)) + for word_addr in sorted(entries.keys()): + word = entries[word_addr] + entry_addr = word_addr - start_word_addr + f.write("@%08X %s\n" % (entry_addr, word)) + +for addr in sorted(slm_dict.keys()): + data = slm_dict[addr] + + ## l2 address range + #if(addr >= l2_start and addr <= l2_end): + # l2_base = addr - l2_start + # l2_stim.write("@%08X %s\n" % (l2_base, data)) + + ## program memory address range + #if(addr >= prog_mem_start and addr <= prog_mem_end): + # prog_mem_base = addr - prog_mem_start + # prog_mem_stim.write("@%08X %s\n" % (prog_mem_base, data)) + + # tcdm address range + if(addr >= tcdm_start and addr <= tcdm_end): + tcdm_addr = (addr - tcdm_start) >> tcdm_bank_bits + bank = addr % tcdm_banks + tcdm_files[bank].write("@%08X %s\n" % (tcdm_addr, data)) + #tcdm_size += 1 + +write_file(l2_hnd_stim, l2_hnd_dict, l2_hnd_start, l2_hnd_width) +write_file(l2_pkt_stim, l2_pkt_dict, l2_pkt_start, l2_pkt_width) + +write_file(prog_mem_stim, prog_mem_dict, prog_mem_start, prog_mem_width) + +############################################################################### +# close all files +############################################################################### + +for i in tcdm_files: + tcdm_files[i].close() + +prog_mem_stim.close() +l2_hnd_stim.close() +l2_pkt_stim.close() + diff --git a/sw/rules/spin-handlers.mk b/sw/rules/spin-handlers.mk new file mode 100644 index 0000000..572eb8c --- /dev/null +++ b/sw/rules/spin-handlers.mk @@ -0,0 +1,92 @@ +TARGET_SLM ?= ${PSPIN_HW}/sim_files/slm_files +TARGET_VSIM ?= ${PSPIN_HW}/${PSPIN_SIM} +SPIN_APP_NAME ?= "" +TELEMETRY_KEY ?= "" +INFO_KEY ?= "" +DMA_KEY ?= "" +HANDLERS_PREFIX ?= ${SPIN_APP_NAME} +PKT_SIZE ?= 1024 +PKT_DELAY ?= 78 +MSG_DELAY ?= 78 + +include $(PSPIN_RT)/spin-rt.mk + +#0: only header; 1: transfer full packet; 2: custom transfer +FULL_PKT ?= 0 +CUSTOM_HDR_SIZE ?= 0 + +PKT_SEED ?= 0 +HAS_HH ?= 1 +HAS_TH ?= 1 +MSG_COUNT ?= 1 +PKTGEN_CUSTOM_PARAMS ?= "" +APP_CFLAGS ?= "" + +PKTGEN ?= ${PSPIN_RT}/packet_generator/bin/generic + +# Default rule +all:: + +build:: + $(MAKE) conf io=uart CONFIG_OPT="uart/baudrate=115200" + +packets:: + $(PSPIN_RT)/scripts/make_packets.sh ${NUM_PACKETS} ${SPIN_APP_NAME} ${HANDLERS_PREFIX} ${PKT_SIZE} ${PKT_DELAY} ${MSG_DELAY} ${FULL_PKT} ${MSG_COUNT} ${PKTGEN} ${PKTGEN_CUSTOM_PARAMS} ${HAS_HH} ${HAS_TH} ${PKT_SEED} ${CUSTOM_HDR_SIZE} + +#TODO: trace, trace-chrome should go to stdout, not to a file! +trace:: + perl $(PSPIN_RT)/scripts/tracevis/parse.pl -t build/$(SPIN_APP_NAME) $(TRACE_DIR)trace_core_* > $(SPIN_APP_NAME).trace.txt + +transcript:: + cat $(TARGET_VSIM)/transcript + +trace-chrome:: + perl $(PSPIN_RT)/scripts/tracevis/parse.pl build/$(SPIN_APP_NAME) $(TRACE_DIR)trace_core_* > $(SPIN_APP_NAME).trace.json + +trace-stdout:: + @perl $(PSPIN_RT)/scripts/tracevis/parse.pl -t build/$(SPIN_APP_NAME) $(TARGET_VSIM)/trace_core_* + +trace-chrome-stdout:: + @perl $(PSPIN_RT)/scripts/tracevis/parse.pl build/$(SPIN_APP_NAME) $(TARGET_VSIM)/trace_core_* + +#telemetry:: +# $(PSPIN_RT)/scripts/telemetry_time_tracevis.sh $(SPIN_APP_NAME).trace.txt $(TELEMETRY_KEY) "$(PSPIN_RT)/src/*.c ${SPIN_APP_SRCS}" > $(SPIN_APP_NAME).time.telemetry + +#telemetry-instr:: +# $(PSPIN_RT)/scripts/telemetry_instructions_tracevis.sh $(SPIN_APP_NAME).trace.txt $(TELEMETRY_KEY) "$(PSPIN_RT)/src/*.c ${SPIN_APP_SRCS}" > $(SPIN_APP_NAME).instructions.telemetry + +#info:: +# $(PSPIN_RT)/scripts/extract_info.sh $(INFO_KEY) $(TARGET_VSIM)/transcript +# + +info:: + make trace; + $(PSPIN_RT)/scripts/handlers_data.sh $(INFO_KEY) $(SPIN_APP_NAME).trace.txt + +dma:: + $(PSPIN_RT)/scripts/extract_dma.sh $(DMA_KEY) $(TARGET_VSIM) + +patch: + @for file in ${PATCH_INTERNAL} ${PATCH_EXTERNAL}; do \ + $(PSPIN_RT)/scripts/patch_bsw.sh $${file} build/bigpulp-juno/${SPIN_APP_NAME}/cl/${PSPIN_RT}/src/ "${PULP_CFLAGS}" ; \ + done + +simulate:: + $(PSPIN_RT)/bin/spin_run 0 | tee transcript + cp $(PSPIN_HW)/verilator_model/trace_* . + +simulate-debug:: + $(PSPIN_RT)/bin/spin_run 1 | tee transcript + cp $(PSPIN_HW)/verilator_model/trace_* . + cp $(PSPIN_HW)/verilator_model/waves.vcd . + +stats:: + $(PSPIN_RT)/scripts/handlers_duration.sh transcript + +makenrun:: + make patch + make deploy + make packets + make simulate + + diff --git a/sw/rules/spin-rt.mk b/sw/rules/spin-rt.mk new file mode 100644 index 0000000..472bb6b --- /dev/null +++ b/sw/rules/spin-rt.mk @@ -0,0 +1,52 @@ +TARGET_SLM ?= ${PSPIN_HW}/sim_files/slm_files +CC=${RISCV_GCC}/riscv32-unknown-elf-gcc +OBJCOPY=${RISCV_GCC}/riscv32-unknown-elf-objcopy +OBJDUMP=${RISCV_GCC}/riscv32-unknown-elf-objdump +PULP_SDK=${PSPIN_RT}/pulp-sdk/ + +TARGET_BIN=build/$(SPIN_APP_NAME) + +.PHONY: install deploy + +CFLAGS=-DPULP_CHIP_STR=bigpulp -DPULP_CHIP_FAMILY_STR=bigpulp -DPULP_CHIP=40 -DPULP_CHIP_FAMILY=7 -march=rv32imacxpulpv2 -D__riscv__ -MMD -MP $(SPIN_CFLAGS) +LDFLAGS=-nostartfiles -nostdlib -Wl,--gc-sections -T $(PULP_SDK)/linker/config.ld -T $(PULP_SDK)/linker/link.ld $(SPIN_LDFLAGS) +INCLUDE_FILES=-I$(PULP_SDK)/archi/include -I$(PULP_SDK)/hal/include -I${PSPIN_HW}/deps/axi/src/dma/frontends/pulp_cluster_frontend/lib/ -I${PSPIN_RT}/include/ + +PULP_SRCS=$(PULP_SDK)/runtime/libs/io/io.c $(PULP_SDK)/runtime/libs/io/tinyprintf.c +PULP_INC=-I$(PULP_SDK)/runtime/libs/io/ + +#SRC_FILES=$(PSPIN_RT)/src/hpu.c $(PSPIN_RT)/src/handler.c ${SPIN_APP_SRCS} +SRC_FILES=$(PSPIN_RT)/src/hpu.c ${SPIN_APP_SRCS} + + +runtime-debug: + mkdir -p build/ + $(CC) $(CFLAGS) -DLANGUAGE_ASSEMBLY $(INCLUDE_FILES) -c $(PULP_SDK)/kernel/riscv/rt/crt0.S -o build/crt0.o + $(CC) $(CFLAGS) ${SPIN_CFLAGS} $(PULP_INC) $(INCLUDE_FILES) $(PULP_SRCS) $(SRC_FILES) build/crt0.o -o $(TARGET_BIN) $(LDFLAGS) + +runtime: + mkdir -p build/ + $(CC) $(CFLAGS) -DLANGUAGE_ASSEMBLY -O3 -flto $(INCLUDE_FILES) -c $(PULP_SDK)/kernel/riscv/rt/crt0.S -o build/crt0.o + $(CC) $(CFLAGS) ${SPIN_CFLAGS} $(PULP_INC) $(INCLUDE_FILES) $(PULP_SRCS) $(SRC_FILES) build/crt0.o -o $(TARGET_BIN) $(LDFLAGS) + +deploy:: + $(MAKE) runtime + mkdir -p build/slm_files/ + $(OBJCOPY) --srec-len 1 --output-target=srec $(TARGET_BIN) build/$(SPIN_APP_NAME).s19 + cd build/slm_files && \ + $(PULP_SDK)/scripts/s19toslm.py ../$(SPIN_APP_NAME).s19 && \ + $(PULP_SDK)/bin/slm_conv -n 16384 -f l2_hnd_stim.slm -S 1 -P 32 && \ + python $(PULP_SDK)/bin/rename_l2.py hnd && \ + mkdir -p ${TARGET_SLM} && \ + cp *.slm ${TARGET_SLM} + $(OBJDUMP) -S build/$(SPIN_APP_NAME) > build/$(SPIN_APP_NAME).disasm + +install: + mkdir -p build/ + mkdir -p build/lib/ + mkdir -p build/include/ + (cd packet_generator; make lib ) + cp packet_generator/libpktgen.so build/lib/ + cp packet_generator/*.h build/include/ + + diff --git a/sw/runtime/include/handler.h b/sw/runtime/include/handler.h new file mode 100644 index 0000000..b7c2bbc --- /dev/null +++ b/sw/runtime/include/handler.h @@ -0,0 +1,286 @@ +#pragma once + +//#include "pulp.h" +#include "pspin.h" +#include "util.h" +#include "spin_conf.h" +#include "spin_dma.h" +#include "hwsched.h" + +#define __handler__ __attribute__((used)) + +#define SPIN_DMA_EXT2LOC PLP_DMA_EXT2LOC +#define SPIN_DMA_LOC2EXT PLP_DMA_LOC2EXT +#define SPIN_OK 0x0 +#define SPIN_FAIL 0x1 + + +#define GET_IP_UDP_PLD(pkt_ptr, pkt_pld_ptr, pkt_pld_len) \ +{ \ + ip_hdr_t *ip_hdr = (ip_hdr_t*) (pkt_ptr); \ + pkt_pld_len = ip_hdr->length - sizeof(ip_hdr_t) - sizeof(udp_hdr_t); \ + pkt_pld_ptr = ((uint8_t *) pkt_ptr) + (ip_hdr->ihl * 4) + sizeof(udp_hdr_t); \ +} + +typedef futex_t spin_lock_t; + +typedef struct task +{ + //handler memory (L2) + void* handler_mem; + size_t handler_mem_size; + + //packet memory (L1) + void* pkt_mem; + size_t pkt_mem_size; + + //per-message scratchpad (L1) + void* scratchpad[NB_CLUSTERS]; + size_t scratchpad_size[NB_CLUSTERS]; + + //host memory region + uint32_t host_mem_high; + uint32_t host_mem_low; + size_t host_mem_size; + + //l2 pkt addr + void* l2_pkt_mem; + + //home cluster id + uint32_t home_cluster_id; + + //flow id + uint32_t flow_id; + +}__attribute__((__packed__)) task_t; + +typedef struct handler_args +{ + task_t *task; + uint32_t hpu_gid; + uint32_t cluster_id; + uint32_t hpu_id; +} handler_args_t; + +typedef void (*handler_fn)(handler_args_t*); + +typedef dma_t spin_dma_t; + +typedef struct spin_rw_lock { + spin_lock_t glock; + volatile int32_t num_readers; +} spin_rw_lock_t; + + +static inline int spin_dma(void* source, void* dest, size_t size, int direction, int options, spin_dma_t* xfer) +{ + *xfer = spin__memcpy_nonblk(source, dest, (uint32_t)size); + return SPIN_OK; +} + +static inline int spin_dma_wait(spin_dma_t xfer) +{ + spin__wait_for_tf_completion(xfer); + return SPIN_OK; +} + +static inline int spin_dma_test(spin_dma_t xfer, uint32_t *completed) +{ + *completed = spin__tf_completed(xfer); + return SPIN_OK; +} + + +/** Locks **/ + +static inline int spin_lock_init(spin_lock_t* lock) +{ + futex_init(lock); + return SPIN_OK; +} + +static inline int spin_lock_try_lock(spin_lock_t* lock) +{ + return futex_try_lock(lock); +} + +static inline int spin_lock_lock(spin_lock_t* lock) +{ + futex_lock_s(lock); + return SPIN_OK; +} + +static inline int spin_lock_unlock(spin_lock_t* lock) +{ + futex_unlock(lock); + return SPIN_OK; +} + +static inline int spin_rw_lock_r_lock(spin_rw_lock_t *rwlock) +{ + int32_t num_readers = amo_add(&(rwlock->num_readers), 1) + 1; + if (num_readers == 1) + { + spin_lock_lock(&(rwlock->glock)); + } + return SPIN_OK; +} + +static inline int spin_rw_lock_r_unlock(spin_rw_lock_t *rwlock) +{ + int32_t num_readers = amo_add(&(rwlock->num_readers), -1) - 1; + if (num_readers == 0) + { + spin_lock_unlock(&(rwlock->glock)); + } + return SPIN_OK; +} + +static inline int spin_rw_lock_w_lock(spin_rw_lock_t *rwlock) +{ + spin_lock_lock(&(rwlock->glock)); + return SPIN_OK; +} + +static inline int spin_rw_lock_w_unlock(spin_rw_lock_t *rwlock) +{ + spin_lock_unlock(&(rwlock->glock)); + return SPIN_OK; +} + + +typedef uint32_t spin_cmd_t; +static inline int spin_cmd_wait(spin_cmd_t handle) +{ + MMIO_WRITE(CMD_WAIT, handle); + return SPIN_OK; +} + +static inline int spin_cmd_test(spin_cmd_t handle, bool *completed) +{ + MMIO_WRITE(CMD_TEST, handle); + *completed = MMIO_READ(CMD_TEST) == 1; + return SPIN_OK; +} + +static inline int spin_rdma_put(uint32_t dest, void *data, uint32_t length, spin_cmd_t *handle) +{ + uint32_t fid = 1 /* >1 is RDMA */; + uint32_t src_addr_high = 0; + uint32_t cmd_info = 2; + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 144(%1); \ + sw %3, 148(%1); \ + sw %5, 152(%1); \ + sw %4, 156(%1); \ + sw %6, 160(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(dest), "r"(fid), "r"(src_addr_high), "r"((uint32_t)data), "r"(length), "r"(cmd_info)); + + *handle = res; + return SPIN_OK; +} + +static inline int spin_send_packet(void *data, uint32_t length, spin_cmd_t *handle) +{ + uint32_t dest = 0; + uint32_t fid = 0 /* fid is used as QP ID. fid=0 -> no QP, it's raw data */; + uint32_t src_addr_high = 0; + uint32_t cmd_info = 2; + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 144(%1); \ + sw %3, 148(%1); \ + sw %5, 152(%1); \ + sw %4, 156(%1); \ + sw %6, 160(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(dest), "r"(fid), "r"(src_addr_high), "r"((uint32_t)data), "r"(length), "r"(cmd_info)); + + *handle = res; + return SPIN_OK; +} + +static inline int spin_dma_to_host(uint64_t host_addr, uint32_t nic_addr, uint32_t length, bool generate_event, spin_cmd_t *xfer) +{ + uint32_t host_address_high = (uint32_t) (host_addr >> 32); + uint32_t host_address_low = (uint32_t) host_addr; + uint32_t direction = 1; //NIC -> host + uint32_t cmd_info = (uint8_t) generate_event; + + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 148(%1); \ + sw %3, 144(%1); \ + sw %4, 152(%1); \ + sw %5, 156(%1); \ + sw %6, 160(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(host_address_high), "r"(host_address_low), "r"(nic_addr), "r"(length), "r"(direction), "r"(cmd_info)); + + *xfer = res; + return SPIN_OK; +} + +static inline int spin_dma_from_host(uint64_t host_addr, uint32_t nic_addr, uint32_t length, bool generate_event, spin_cmd_t *xfer) +{ + uint32_t host_address_high = (uint32_t) (host_addr >> 32); + uint32_t host_address_low = (uint32_t) host_addr; + uint32_t direction = 0; //host -> NIC + uint32_t cmd_info = (uint8_t) generate_event; + + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 148(%1); \ + sw %3, 144(%1); \ + sw %4, 152(%1); \ + sw %5, 156(%1); \ + sw %6, 160(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(host_address_high), "r"(host_address_low), "r"(nic_addr), "r"(length), "r"(direction), "r"(cmd_info)); + + *xfer = res; + return SPIN_OK; +} + +// spin_host_write is deprecated. Use spin_write_to_host instead! +#define spin_host_write spin_write_to_host + +static inline int spin_write_to_host(uint64_t host_addr, uint64_t user_data, spin_cmd_t *xfer) +{ + uint32_t host_address_high = (uint32_t) (host_addr >> 32); + uint32_t host_address_low = (uint32_t) host_addr; + + uint32_t data_high = (uint32_t) (user_data >> 32); + uint32_t data_low = (uint32_t) user_data; + + uint32_t size_and_direction = (0x8 << 1) | 0x1; // 8 bytes NIC -> host + uint32_t cmd_info = (uint8_t) 4; + + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 148(%1); \ + sw %3, 144(%1); \ + sw %4, 152(%1); \ + sw %6, 156(%1); \ + sw %5, 160(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(host_address_high), "r"(host_address_low), "r"(size_and_direction), "r"(data_high), "r"(data_low), "r"(cmd_info)); + + *xfer = res; + return SPIN_OK; +} + +//this function is only needed to avoid the compiler stripping away the handler functions (we don't reference them +//from the code but have pointers to them in the ME) +void init_handlers(handler_fn * hh, handler_fn *ph, handler_fn *th, void **handler_mem_ptr); diff --git a/sw/runtime/include/hwsched.h b/sw/runtime/include/hwsched.h new file mode 100644 index 0000000..107b670 --- /dev/null +++ b/sw/runtime/include/hwsched.h @@ -0,0 +1,39 @@ +#pragma once + +#define HWSCHED_HANDLER_FUN_ADDR 0x1B205000 +#define HWSCHED_HANDLER_FUN_SIZE 0x1B205004 +#define HWSCHED_HANDLER_MEM_ADDR 0x1B205008 +#define HWSCHED_HANDLER_MEM_SIZE 0x1B20500c +#define HWSCHED_PKT_ADDR 0x1B205010 +#define HWSCHED_PKT_SIZE 0x1B205014 +#define HWSCHED_SCRATCHPAD_0_ADDR 0x1B205018 +#define HWSCHED_SCRATCHPAD_1_ADDR 0x1B20501c +#define HWSCHED_SCRATCHPAD_2_ADDR 0x1B205020 +#define HWSCHED_SCRATCHPAD_3_ADDR 0x1B205024 +#define HWSCHED_SCRATCHPAD_0_SIZE 0x1B205028 +#define HWSCHED_SCRATCHPAD_1_SIZE 0x1B20502c +#define HWSCHED_SCRATCHPAD_2_SIZE 0x1B205030 +#define HWSCHED_SCRATCHPAD_3_SIZE 0x1B205034 +#define HWSCHED_HOST_MEM_ADDR_HIGH 0x1B205038 +#define HWSCHED_HOST_MEM_ADDR_LOW 0x1B20503c +#define HWSCHED_HOST_MEM_SIZE 0x1B205040 +#define HWSCHED_HOST_L2_PKT_ADDR 0x1B205044 +#define HWSCHED_HOME_CLUSTER_ID 0x1B205048 +#define HWSCHED_FLOW_ID 0x1B20504c +#define HWSCHED_DOORBELL 0x1B205050 +#define HWSCHED_ERROR 0x1B205054 + +#define CMD_ISSUE 0x1B205080 +#define CMD_WAIT 0x1B205084 +#define CMD_TEST 0x1B205088 +#define CMD_INFO 0x1B20508C +#define CMD_WORD0 0x1B205090 +#define CMD_WORD1 0x1B205094 +#define CMD_WORD2 0x1B205098 +#define CMD_WORD3 0x1B20509C +#define CMD_WORD4 0x1B2050A0 +#define CMD_WORD5 0x1B2050A4 +#define CMD_WORD6 0x1B2050A8 + +#define MMIO_READ(X) (*((uint32_t volatile*) (X))) +#define MMIO_WRITE(X, V) (*((uint32_t volatile*) (X)) = V) \ No newline at end of file diff --git a/sw/runtime/include/libaxidma.h b/sw/runtime/include/libaxidma.h new file mode 100644 index 0000000..2fbeb43 --- /dev/null +++ b/sw/runtime/include/libaxidma.h @@ -0,0 +1,155 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// AXI DMA library for the pulp cluster frontend + +#include + + +// base address of the dma +typedef struct { + uint32_t src_addr_low; + uint32_t src_addr_high; + uint32_t dst_addr_low; + uint32_t dst_addr_high; + uint32_t num_bytes; + volatile uint32_t tf_id __attribute__((aligned(8))); + volatile uint32_t done_id __attribute__((aligned(8))); + volatile uint32_t config __attribute__((aligned(8))); +} axidma__dma_conf_t; + +// launch simple 1D transfer (supporting 64 bit addresses) +static inline uint32_t axidma__launch_oned_64( + axidma__dma_conf_t* axidma__dma_conf, + void* src_addr_low, + void* src_addr_high, + void* dst_addr_low, + void* dst_addr_high, + uint32_t num_bytes +) { + + // configure the dma + axidma__dma_conf->src_addr_low = (uint32_t)src_addr_low; + axidma__dma_conf->src_addr_high = (uint32_t)src_addr_high; + axidma__dma_conf->dst_addr_low = (uint32_t)dst_addr_low; + axidma__dma_conf->dst_addr_high = (uint32_t)dst_addr_high; + axidma__dma_conf->num_bytes = (uint32_t)num_bytes; + + __asm__ __volatile__ ("" : : : "memory"); + + // launch the transfer + return axidma__dma_conf->tf_id; +} + + +// launch simple 1D transfer +// make sure the high address registers are correctly set! +static inline uint32_t axidma__launch_oned( + axidma__dma_conf_t* axidma__dma_conf, + void* src_addr, + void* dst_addr, + uint32_t num_bytes +) { + + // configure the dma + axidma__dma_conf->src_addr_low = (uint32_t)src_addr; + axidma__dma_conf->dst_addr_low = (uint32_t)dst_addr; + axidma__dma_conf->num_bytes = (uint32_t)num_bytes; + + __asm__ __volatile__ ("" : : : "memory"); + + // launch the transfer + return axidma__dma_conf->tf_id; +} + + +// use to set the the segment address in a segmented system +static inline void axidma__set_seg_addr( + axidma__dma_conf_t* axidma__dma_conf, + void* src_seg_addr, + void* dsc_seg_addr +) { + + // configure the upper 64 bit addresses + axidma__dma_conf->src_addr_high = (uint32_t)src_seg_addr; + axidma__dma_conf->dst_addr_high = (uint32_t)dsc_seg_addr; + +} + + +// clear upper address registers +static inline void axidma__clear_seg_addr( + axidma__dma_conf_t* axidma__dma_conf +) { + + // clear both upper address registers + axidma__set_seg_addr(axidma__dma_conf, 0, 0); +} + + +// read the id of the last transaction that has been completed +static inline uint32_t axidma__read_completed_id( + axidma__dma_conf_t* axidma__dma_conf +) { + + return axidma__dma_conf->done_id; +} + + +// wait for a given transaction to complete +static inline void axidma__wait_for_tf_completion( + axidma__dma_conf_t* axidma__dma_conf, + uint32_t tf_id +) { + + // spin until transfer is completed + while (tf_id > axidma__read_completed_id(axidma__dma_conf)) { + asm volatile ("nop"); + } +} + + +// test if a given transaction has been completed +static inline char axidma__tf_completed( + axidma__dma_conf_t* axidma__dma_conf, + uint32_t tf_id +) { + + return (tf_id <= axidma__read_completed_id(axidma__dma_conf)); +} + + +// non-blocking transfer +static inline uint32_t axidma__memcpy_nonblk( + axidma__dma_conf_t* axidma__dma_conf, + void* src_addr, + void* dst_addr, + uint32_t num_bytes +) { + + return axidma__launch_oned(axidma__dma_conf, src_addr, dst_addr, num_bytes); +} + + +// blocking transfer +static inline void axidma__memcpy( + axidma__dma_conf_t* axidma__dma_conf, + void* src_addr, + void* dst_addr, + uint32_t num_bytes +) { + + volatile uint32_t tf_id = axidma__launch_oned(axidma__dma_conf, src_addr, dst_addr, num_bytes); + // spin until transfer is completed + while (tf_id > axidma__read_completed_id(axidma__dma_conf)) { + asm volatile ("nop"); + } +} diff --git a/sw/runtime/include/packets.h b/sw/runtime/include/packets.h new file mode 100755 index 0000000..2ba84c7 --- /dev/null +++ b/sw/runtime/include/packets.h @@ -0,0 +1,49 @@ +#ifndef PACKETS_H +#define PACKETS_H + +#include + +typedef struct ip_hdr +{ + //ip-like + uint8_t version:4; + uint8_t ihl:4; + uint8_t tos; + uint16_t length; + + uint16_t identification; + uint16_t offset; + + uint8_t ttl; + uint8_t protocol; + uint16_t checksum; + + uint32_t source_id; // 4 + uint32_t dest_id; // 4 + +} __attribute__((__packed__)) ip_hdr_t; + +typedef struct udp_hdr +{ + uint16_t src_port; + uint16_t dst_port; + uint16_t length; + uint16_t checksum; +} __attribute__((__packed__)) udp_hdr_t; + + +typedef struct app_hdr +{ //QUIC-like + uint64_t connection_id; + uint16_t packet_num; + uint16_t frame_type; //frame_type 1: connection closing +} __attribute__((__packed__)) app_hdr_t; + +typedef struct pkt_hdr +{ + ip_hdr_t ip_hdr; + udp_hdr_t udp_hdr; + app_hdr_t app_hdr; +} __attribute__((__packed__)) pkt_hdr_t; + +#endif /* PACKETS_H */ diff --git a/sw/runtime/include/pspin.h b/sw/runtime/include/pspin.h new file mode 100644 index 0000000..2b03cea --- /dev/null +++ b/sw/runtime/include/pspin.h @@ -0,0 +1,258 @@ +#pragma once + +#include +#include +#include +#include +#include + +#define MEM_ALIGNMENT 4 +#define ALIGN_UP(NUM, ALIGN) ((((uint32_t)(NUM)) + ((ALIGN)-1)) & ~((ALIGN)-1)) +#define DMA_MAX_XFER_SIZE 32768 +#define DMA_NULL 0 + +typedef uint32_t dma_t; +typedef volatile uint32_t futex_t; + +#ifndef NO_PULP + +static inline void rt_time_wait_cycles(const unsigned cycles) +{ + /** + * Each iteration of the loop below will take four cycles on RI5CY (one for + * `addi` and three for the taken `bnez`; if the instructions hit in the + * I$). Thus, we let `i` count the number of remaining loop iterations and + * initialize it to a fourth of the number of clock cyles. With this + * initialization, we must not enter the loop if the number of clock cycles + * is less than four, because this will cause an underflow on the first + * subtraction. + */ + register unsigned threshold; + asm volatile("li %[threshold], 4" + : [ threshold ] "=r"(threshold)); + asm volatile goto("ble %[cycles], %[threshold], %l2" + : /* no output */ + : [ cycles ] "r"(cycles), [ threshold ] "r"(threshold) + : /* no clobbers */ + : __wait_cycles_end); + register unsigned i = cycles >> 2; +__wait_cycles_start: + // Decrement `i` and loop if it is not yet zero. + asm volatile("addi %0, %0, -1" + : "+r"(i)); + asm volatile goto("bnez %0, %l1" + : /* no output */ + : "r"(i) + : /* no clobbers */ + : __wait_cycles_start); +__wait_cycles_end: + return; +} + + +static inline void asm_mem_fence() +{ + __asm__ __volatile__("" + : + : + : "memory"); +} + +static inline uint32_t load_reserved(volatile const uint32_t *const addr) +{ + uint32_t val; + asm_mem_fence(); + asm volatile("lr.w %0, (%1)" + : "=r"(val) + : "r"(addr)); + asm_mem_fence(); + return val; +} + +/** + * Expose the store-conditional instruction. Only stores a value if a previously made reservation + * has not been broken. + * + * @param addr A pointer to L2 memory at which to store the value. + * @param val Value to store. + * + * @return 0: Store was successful (the reservation was still valid). + * 1: Reservation was broken, no store happened. + * 2: Slave error; the slave does not support LR/SC. + * 3: The address does not exist. + */ +static inline unsigned store_conditional(volatile uint32_t *const addr, const uint32_t val) +{ + unsigned res; + asm_mem_fence(); + asm volatile("sc.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +/** + * Swap a value atomically if the old memory value matches. + * + * @param addr A pointer to L2 memory at which to swap the value. + * @param old The value expected in memory. + * @param new The new value to be stored if `old` matches the memory content. + * + * @return 0: Swap was successful. + * -1: No swap because old value did not match. + * >0: No swap because atomic access failed. + */ +static inline int compare_and_swap( + volatile uint32_t *const addr, const uint32_t old, const uint32_t new) +{ + uint32_t tmp = load_reserved(addr); + if (tmp == old) + return store_conditional(addr, new); + else + return -1; +} + +static inline uint32_t amo_swap(volatile uint32_t *const addr, const uint32_t val) +{ + uint32_t res; + asm_mem_fence(); + asm volatile("amoswap.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline void amo_store(volatile uint32_t *const addr, const uint32_t val) +{ + asm_mem_fence(); + asm volatile("amoswap.w x0, %0, (%1)" + : + : "r"(val), "r"(addr)); + asm_mem_fence(); +} + +static inline int32_t amo_add(volatile int32_t *const addr, const int32_t val) +{ + int32_t res; + asm_mem_fence(); + asm volatile("amoadd.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline uint32_t amo_and(volatile uint32_t *const addr, const uint32_t val) +{ + uint32_t res; + asm_mem_fence(); + asm volatile("amoand.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline uint32_t amo_or(volatile uint32_t *const addr, const uint32_t val) +{ + uint32_t res; + asm_mem_fence(); + asm volatile("amoor.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline uint32_t amo_xor(volatile uint32_t *const addr, const uint32_t val) +{ + uint32_t res; + asm_mem_fence(); + asm volatile("amoxor.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline uint32_t amo_maxu(volatile uint32_t *const addr, const uint32_t val) +{ + uint32_t res; + asm_mem_fence(); + asm volatile("amomaxu.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline int32_t amo_max(volatile int32_t *const addr, const int32_t val) +{ + int32_t res; + asm_mem_fence(); + asm volatile("amomax.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline uint32_t amo_minu(volatile uint32_t *const addr, const uint32_t val) +{ + uint32_t res; + asm_mem_fence(); + asm volatile("amominu.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static inline int32_t amo_min(volatile int32_t *const addr, const int32_t val) +{ + int32_t res; + asm_mem_fence(); + asm volatile("amomin.w %0, %1, (%2)" + : "=r"(res) + : "r"(val), "r"(addr)); + asm_mem_fence(); + return res; +} + +static void futex_init(futex_t *futex) +{ + //*futex = 0; + amo_store(futex, 0); +} + +static inline int futex_try_lock(futex_t *futex) +{ + return amo_or(futex, 1) == 0; +} + +static inline int futex_lock(futex_t *futex) +{ + while (amo_or(futex, 1)) + { + ; + } + return 1; +} + +static inline int futex_lock_s(futex_t *futex) +{ + while (amo_or(futex, 1)) + { + rt_time_wait_cycles(32); + } + return 1; +} + +static inline void futex_unlock(futex_t *futex) +{ + futex_init(futex); +} + +#endif diff --git a/sw/runtime/include/pspin_rt.h b/sw/runtime/include/pspin_rt.h new file mode 100644 index 0000000..c1ca5fa --- /dev/null +++ b/sw/runtime/include/pspin_rt.h @@ -0,0 +1,48 @@ +#pragma once + +#include +#include +#include +#include +#include + +#define ECALL_PSPIN_HANDLER_EXIT 0xa + +#define PULP_CSR_MSTATUS 0x300 +#define PULP_CSR_MTVEC 0x305 +#define PULP_CSR_MEPC 0x341 +#define PULP_CSR_MCAUSE 0x342 +#define PULP_CSR_PRIVLV 0xc10 + +#define PULP_CSR_PMPCFG0 0x3a0 +#define PULP_CSR_PMPCFG1 0x3a1 +#define PULP_CSR_PMPCFG2 0x3a2 +#define PULP_CSR_PMPCFG3 0x3a3 +#define PULP_CSR_PMPADDR0 0x3b0 +#define PULP_CSR_PMPADDR1 0x3b1 +#define PULP_CSR_PMPADDR2 0x3b2 +#define PULP_CSR_PMPADDR3 0x3b3 +#define PULP_CSR_PMPADDR4 0x3b4 +#define PULP_CSR_PMPADDR5 0x3b5 +#define PULP_CSR_PMPADDR6 0x3b6 +#define PULP_CSR_PMPADDR7 0x3b7 +#define PULP_CSR_PMPADDR8 0x3b8 +#define PULP_CSR_PMPADDR9 0x3b9 +#define PULP_CSR_PMPADDR10 0x3ba +#define PULP_CSR_PMPADDR11 0x3bb +#define PULP_CSR_PMPADDR12 0x3bc +#define PULP_CSR_PMPADDR13 0x3bd +#define PULP_CSR_PMPADDR14 0x3be +#define PULP_CSR_PMPADDR15 0x3bf + +#ifndef NO_PULP +static inline uint32_t rt_core_id() +{ + return hal_core_id(); +} + +static inline uint32_t rt_cluster_id() +{ + return hal_cluster_id(); +} +#endif diff --git a/sw/runtime/include/spin_conf.h b/sw/runtime/include/spin_conf.h new file mode 100644 index 0000000..aebbc1a --- /dev/null +++ b/sw/runtime/include/spin_conf.h @@ -0,0 +1,27 @@ +#pragma once + +/* PULP settings */ +// number of cores per cluster +#ifndef NB_CORES + #define NB_CORES 8 +#endif + +// number of clusters +#ifndef NB_CLUSTERS + #define NB_CLUSTERS 4 +#endif +#define CORE_COUNT (NB_CORES * NB_CLUSTERS) + +/* Packet settings */ +// length of the input packet queue [B] +// Warning: modify spin_types.h if you increase this size! +#define PacketQueueLength (4 * (1 << 20) - 3 * 4) // 4 MiB minus three words meta data + +// size of data payload in each packet [B] +#ifndef PKT_SIZE +#define PKT_SIZE 1024 +#endif + +// number of HPUs per each cluster +#define NUM_CLUSTER_HPUS (NB_CORES) + diff --git a/sw/runtime/include/spin_dma.h b/sw/runtime/include/spin_dma.h new file mode 100644 index 0000000..ed79482 --- /dev/null +++ b/sw/runtime/include/spin_dma.h @@ -0,0 +1,121 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// AXI DMA library for the spinningpulp soc + +#pragma once + +#include "libaxidma.h" + +// cluster address ofsets +#define CLUSTER_BASE 0x10000000 +#define DMA_OFFSET 0x1800 + +#define PRIVATE_DMA_BASE ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET +#define PUPLIC_DMA_BASE CLUSTER_BASE + ARCHI_CLUSTER_PERIPHERALS_OFFSET + DMA_OFFSET + + +// non-blocking private transfer +static inline uint32_t spin__memcpy_nonblk( + void* src_addr, + void* dst_addr, + uint32_t num_bytes +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + return axidma__memcpy_nonblk(dma, src_addr, dst_addr, num_bytes); +} + + +// blocking private transfer +static inline void spin__memcpy( + void* src_addr, + void* dst_addr, + uint32_t num_bytes +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + axidma__memcpy(dma, src_addr, dst_addr, num_bytes); +} + + +// wait for a given private transaction to complete +static inline void spin__wait_for_tf_completion( + uint32_t tf_id +) { + + // spin until transfer is completed + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + while (tf_id > axidma__read_completed_id(dma)) { + asm volatile ("nop"); + } +} + + +// test if a given private transaction has been completed +static inline char spin__tf_completed( + uint32_t tf_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + return (tf_id <= axidma__read_completed_id(dma)); +} + + +// non-blocking public transfer +static inline uint32_t spin__public_memcpy_nonblk( + void* src_addr, + void* dst_addr, + uint32_t num_bytes, + uint32_t cluster_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + return axidma__memcpy_nonblk(dma, src_addr, dst_addr, num_bytes); +} + + +// blocking public transfer +static inline void spin__public_memcpy( + void* src_addr, + void* dst_addr, + uint32_t num_bytes, + uint32_t cluster_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + axidma__memcpy(dma, src_addr, dst_addr, num_bytes); +} + + +// wait for a given private transaction to complete +static inline void spin__public_wait_for_tf_completion( + uint32_t tf_id, + uint32_t cluster_id +) { + + // spin until transfer is completed + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + while (tf_id > axidma__read_completed_id(dma)) { + asm volatile ("nop"); + } +} + + +// test if a given private transaction has been completed +static inline char spin__public_tf_completed( + uint32_t tf_id, + uint32_t cluster_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + return (tf_id <= axidma__read_completed_id(dma)); +} diff --git a/sw/runtime/include/util.h b/sw/runtime/include/util.h new file mode 100644 index 0000000..cf2f18e --- /dev/null +++ b/sw/runtime/include/util.h @@ -0,0 +1,69 @@ +#pragma once + +#include + +// #define LOG + +#define MIN(a, b) (((a)<(b)) ? (a) : (b)) +#define MAX(a, b) (((a)>(b)) ? (a) : (b)) + +//#define FAST_MIN(x, y) (y ^ ((x ^ y) & -(x < y))) +//#define FAST_MAX(x, y) (x ^ ((x ^ y) & -(x < y))) + +#define STRINGIFY(x) #x +#define read_csr(reg, val) asm volatile ("csrr %0, " STRINGIFY(reg) : "=r"(val)); +#define write_csr(reg, val) asm volatile ("csrw " STRINGIFY(reg) ", %0" : : "rK" (val) : "memory"); +#define clear_csr(reg, mask) asm volatile ("csrc " STRINGIFY(reg) ", %0" : : "rK" (mask) : "memory"); +#define read_register(reg, val) asm volatile ("addi %0, " STRINGIFY(reg) ", 0" : "=r"(val)); +#define write_register(reg, val) asm volatile ("addi " STRINGIFY(reg) ", %0, 0" : : "r"(val) : "memory"); + +#define DIV_CEIL(a, b) (((a) + (b) - 1)/(b)) + +//only for powers of 2! +#define FAST_DIV(a, log2_b) ((a) >> log2_b) +#define FAST_MOD(a, b) ((a) & ((b) - 1)) + +#define AND(a, b) ((a) & ((b))) + +#define TERMINATE {*(volatile unsigned int*) 0x1B200000 = 1;} + +/* +#define FAST_MOD2(a, b, c) \ +{ \ + uint32_t tmp = b-1; \ + __asm__ volatile ( \ + "and %0, %1, %2;" \ + : "=r" (c) \ + : "ri" (a) \ + , "ri" (tmp) \ + ); \ +} +*/ + +#define LABEL(name) __asm__ __volatile__ (#name ":;" ::: "memory") + + +#ifdef CHECK_ASSERTS +#define ASSERT(condition)\ +if (!(condition)) {\ +while (true) {\ + printf("Assertion fail: " #condition " at " __FILE__ ":" "%d\n", __LINE__); \ + *(volatile unsigned int*) 0x1B200000 = 1; \ +}} +#else +#define ASSERT(condition) +#endif + +#define SPIN_PRINTF(format, ...) printf("%s:%s:%d: " format, __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__) + +#ifdef LOG +#define DEBUG_PRINT(format, ...) SPIN_PRINTF(format, ##__VA_ARGS__) +#else +#define DEBUG_PRINT(...) +#endif + +#ifdef ENABLE_TRACING +#define TRACING_DUMMY_INSTR() __asm__ __volatile__ ("nop") +#else +#define TRACING_DUMMY_INSTR() +#endif diff --git a/sw/runtime/src/handler.c b/sw/runtime/src/handler.c new file mode 100644 index 0000000..b222825 --- /dev/null +++ b/sw/runtime/src/handler.c @@ -0,0 +1,220 @@ +#include +#include "handler.h" +#include "util.h" +#include "pspin_rt.h" +#include "spin_dma.h" +#include "hwsched.h" + + +/** DMA functions **/ + +int spin_dma(void* source, void* dest, size_t size, int direction, int options, spin_dma_t* xfer) +{ + *xfer = spin__memcpy_nonblk(source, dest, (uint32_t)size); + return SPIN_OK; +} + +int spin_dma_wait(spin_dma_t xfer) +{ + spin__wait_for_tf_completion(xfer); + return SPIN_OK; +} + +int spin_dma_test(spin_dma_t xfer, uint32_t *completed) +{ + *completed = spin__tf_completed(xfer); + return SPIN_OK; +} + +/** Locks **/ + +int spin_lock_init(spin_lock_t* lock) +{ + futex_init(lock); + return SPIN_OK; +} + +int spin_lock_try_lock(spin_lock_t* lock) +{ + return futex_try_lock(lock); +} + +int spin_lock_lock(spin_lock_t* lock) +{ + futex_lock_s(lock); + return SPIN_OK; +} + +int spin_lock_unlock(spin_lock_t* lock) +{ + futex_unlock(lock); + return SPIN_OK; +} + + +int spin_rw_lock_r_lock(spin_rw_lock_t *rwlock) +{ + int32_t num_readers = amo_add(&(rwlock->num_readers), 1) + 1; + if (num_readers == 1) + { + spin_lock_lock(&(rwlock->glock)); + } + return SPIN_OK; +} + +int spin_rw_lock_r_unlock(spin_rw_lock_t *rwlock) +{ + int32_t num_readers = amo_add(&(rwlock->num_readers), -1) - 1; + if (num_readers == 0) + { + spin_lock_unlock(&(rwlock->glock)); + } + return SPIN_OK; +} + +int spin_rw_lock_w_lock(spin_rw_lock_t *rwlock) +{ + spin_lock_lock(&(rwlock->glock)); + return SPIN_OK; +} + +int spin_rw_lock_w_unlock(spin_rw_lock_t *rwlock) +{ + spin_lock_unlock(&(rwlock->glock)); + return SPIN_OK; +} + + +/** NIC commands **/ +int spin_cmd_wait(spin_cmd_t handle) +{ + MMIO_WRITE(CMD_WAIT, handle); + return SPIN_OK; +} + +int spin_cmd_test(spin_cmd_t handle, bool *completed) +{ + MMIO_WRITE(CMD_TEST, handle); + *completed = MMIO_READ(CMD_TEST) == 1; + return SPIN_OK; +} + +int spin_rdma_put(uint32_t dest, void *data, uint32_t length, spin_cmd_t *handle) +{ + uint32_t fid = 1 /* >1 is RDMA */; + uint32_t src_addr_high = 0; + uint32_t cmd_info = 2; + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 168(%1); \ + sw %3, 164(%1); \ + sw %4, 160(%1); \ + sw %5, 156(%1); \ + sw %6, 152(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(dest), "r"(fid), "r"(src_addr_high), "r"((uint32_t)data), "r"(length), "r"(cmd_info)); + + *handle = res; + return SPIN_OK; +} + + +int spin_send_packet(void *data, uint32_t length, spin_cmd_t *handle) +{ + uint32_t dest = 0; + uint32_t fid = 0 /* fid is used as QP ID. fid=0 -> no QP, it's raw data */; + uint32_t src_addr_high = 0; + uint32_t cmd_info = 2; + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 168(%1); \ + sw %3, 164(%1); \ + sw %4, 160(%1); \ + sw %5, 156(%1); \ + sw %6, 152(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(dest), "r"(fid), "r"(src_addr_high), "r"((uint32_t)data), "r"(length), "r"(cmd_info)); + + *handle = res; + return SPIN_OK; +} + +int spin_host_write(uint64_t host_addr, uint64_t user_data, bool generate_event) +{ + /* WARNING: HostDirect is not implemented yet. This method just prepares a dma_to_host command but does not issue it. */ + + uint32_t host_address_high = (uint32_t) (host_addr >> 32); + uint32_t host_address_low = (uint32_t) host_addr; + + uint32_t data_high = (uint32_t) (user_data >> 32); + uint32_t data_low = (uint32_t) user_data; + + uint32_t direction = 1<<31; //NIC -> host + uint32_t cmd_info = (uint8_t) generate_event; + + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 168(%1); \ + sw %3, 164(%1); \ + sw %4, 160(%1); \ + sw %5, 156(%1); \ + sw %6, 144(%1); \ + sw %7, 140(%1); \ + add %0, %0, x0; \ + " : "=r"(res) : "r"(base_addr), "r"(host_address_high), "r"(host_address_low), "r"(data_high), "r"(data_low), "r"(direction), "r"(cmd_info)); + + return SPIN_OK; +} + + +int spin_dma_to_host(uint64_t host_addr, uint32_t nic_addr, uint32_t length, bool generate_event, spin_cmd_t *xfer) +{ + uint32_t host_address_high = (uint32_t) (host_addr >> 32); + uint32_t host_address_low = (uint32_t) host_addr; + uint32_t direction = 1<<31; //NIC -> host + uint32_t cmd_info = (uint8_t) generate_event; + + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 168(%1); \ + sw %3, 164(%1); \ + sw %4, 160(%1); \ + sw %5, 156(%1); \ + sw %6, 144(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(host_address_high), "r"(host_address_low), "r"(nic_addr), "r"(length), "r"(direction), "r"(cmd_info)); + + *xfer = res; + return SPIN_OK; +} + +int spin_dma_from_host(uint64_t host_addr, uint32_t nic_addr, uint32_t length, bool generate_event, spin_cmd_t *xfer) +{ + uint32_t host_address_high = (uint32_t) (host_addr >> 32); + uint32_t host_address_low = (uint32_t) host_addr; + uint32_t direction = 0; //host -> NIC + uint32_t cmd_info = (uint8_t) generate_event; + + //length, src_addr_low, src_addr_high, fid, nid + uint32_t res; + uint32_t base_addr = 0x1b205000; + asm volatile(" sw %2, 168(%1); \ + sw %3, 164(%1); \ + sw %4, 160(%1); \ + sw %5, 156(%1); \ + sw %6, 144(%1); \ + sw %7, 140(%1); \ + lw %0, 128(%1); \ + " : "=r"(res) : "r"(base_addr), "r"(host_address_high), "r"(host_address_low), "r"(nic_addr), "r"(length), "r"(direction), "r"(cmd_info)); + + *xfer = res; + return SPIN_OK; +} + diff --git a/sw/runtime/src/hpu.c b/sw/runtime/src/hpu.c new file mode 100644 index 0000000..0eedf19 --- /dev/null +++ b/sw/runtime/src/hpu.c @@ -0,0 +1,127 @@ +#include "hpu.h" +#include "util.h" +#include "spin_conf.h" +#include "hwsched.h" +#include "pspin_rt.h" + +#define MSTATUS_USER (3<<11) + +#define read_register(reg, val) asm volatile ("addi %0, " STRINGIFY(reg) ", 0" : "=r"(val)); +#define write_register(reg, val) asm volatile ("addi " STRINGIFY(reg) ", %0, 0" : : "r"(val) : "memory"); + +void __attribute__ ((aligned (256))) mtvec(); + +typedef struct hpu_descr { + uint8_t *runtime_sp; +} hpu_descr_t; + +volatile __attribute__ ((section(".data_tiny_l1"))) hpu_descr_t* volatile hpu_descr[NUM_CLUSTER_HPUS]; + +void hpu_run() +{ + handler_args_t handler_args; + + read_register(x10, handler_args.cluster_id); + read_register(x11, handler_args.hpu_id); + + handler_args.hpu_gid = handler_args.cluster_id * NB_CORES + handler_args.hpu_id; + handler_args.task = (task_t *) HWSCHED_HANDLER_MEM_ADDR; + + while (1) { + + handler_fn handler_fun = (handler_fn) MMIO_READ(HWSCHED_HANDLER_FUN_ADDR); + + asm volatile ("nop"); /* TELEMETRY: HANDLER:START */ + handler_fun(&handler_args); + asm volatile ("nop"); /* TELEMETRY: HANDLER:END */ + + MMIO_READ(HWSCHED_DOORBELL); + } +} + +void __attribute__ ((optimize(0))) cluster_init() +{ + uint32_t cluster_id = rt_cluster_id(); + enable_all_icache_banks(); + flush_all_icache_banks(); + hal_icache_cluster_enable(cluster_id); +} + +void hpu_entry() +{ + + uint32_t core_id = rt_core_id(); + uint32_t cluster_id = rt_cluster_id(); + + //printf("HPU (%lu, %lu) hello\n", cluster_id, core_id); + + if (core_id == 0 && cluster_id==0) { + handler_fn hh, ph, th; + void *handler_mem; + init_handlers(&hh, &ph, &th, &handler_mem); + } + + clear_csr(PULP_CSR_MSTATUS, MSTATUS_USER); + write_csr(PULP_CSR_MEPC, hpu_run); + + write_csr(PULP_CSR_MTVEC, mtvec); + + //we save these now because can't access them in user mode + write_register(x10, cluster_id); + write_register(x11, core_id); + + //save the original sp in the HPU descr + read_register(x2, hpu_descr[core_id]); + + //trap to user mode + asm volatile("mret"); +} + +void int0_handler() +{ + uint32_t mcause; + read_csr(PULP_CSR_MCAUSE, mcause); + /* + switch (mcause) + { + case 8: // ECALL + handler_error("ecalls are not suppoerted"); + break; + case 1: + handler_error("Instruction access fault"); + break; + case 2: + handler_error("Illegal instruction"); + break; + case 5: + handler_error("Load access fault"); + break; + case 7: + handler_error("Store/AMO access fault"); + break; + default: + handler_error("Unrecognized mcause"); + break; + } + */ + + MMIO_WRITE(HWSCHED_ERROR, mcause); + MMIO_READ(HWSCHED_DOORBELL); + + //restore the stack pointer + write_register(x2, hpu_descr[rt_core_id()]); + + //we want to resume the runtime and get ready + //for the next handler + clear_csr(PULP_CSR_MSTATUS, MSTATUS_USER); + write_csr(PULP_CSR_MEPC, hpu_run); + + //trap to user mode + asm volatile("mret"); +} + +void __attribute__ ((aligned (256))) mtvec() +{ + /* ecall */ + asm volatile("jalr x0, %0, 0" : : "r"(int0_handler)); +} diff --git a/sw/runtime/src/hpu.h b/sw/runtime/src/hpu.h new file mode 100644 index 0000000..4d25b5c --- /dev/null +++ b/sw/runtime/src/hpu.h @@ -0,0 +1,8 @@ +#pragma once + +#include + +#include "handler.h" +#include "spin_conf.h" + +void hpu_entry(); diff --git a/sw/runtime/src/main.c b/sw/runtime/src/main.c new file mode 100644 index 0000000..4587c8e --- /dev/null +++ b/sw/runtime/src/main.c @@ -0,0 +1,74 @@ +#include +#include + +#include "pulp.h" // PULP API +#include "spinningpulp.h" + +#include "spin_conf.h" +#include "hpu.h" +#include "handler.h" +#include "util.h" + +// Shared variables in L1 of each cluster, initialized to zero. +//volatile __attribute__ ((section(".data_tiny_l1"))) uint8_t* volatile l1_buf; +volatile uint32_t finished[NB_CLUSTERS]; + +void success() +{ + return; +} + +void core_entry(void *arg) +{ + int core_id = rt_core_id(); + hpu_entry(); +} + +void cluster_entry(void *arg) +{ + int cluster_id = rt_cluster_id(); + rt_team_fork(NB_CORES, core_entry, NULL); + finished[cluster_id] = 1; +} + +int main() +{ + // Allocate event so clusters can be mounted and started without blocking. + rt_event_alloc(NULL, 1); + rt_event_t *event = rt_event_get(NULL, success, 0); + + // hack to keep the functions in the binary (THIS POINTERS ARE NOT BEING USED!) + handler_fn hh, ph, th; + void *handler_mem; + init_handlers(&hh, &ph, &th, &handler_mem); + + // Mount clusters. + for (unsigned i = 0; i < NB_CLUSTERS; i++) + { + rt_cluster_mount(1, i, 0, event); + } + + // Start execution on other clusters. + for (unsigned i = 1; i < NB_CLUSTERS; i++) + { + rt_cluster_call(NULL, i, cluster_entry, NULL, NULL, 0, 0, NB_CORES, event); + } + + // Start execution on own cluster. + cluster_entry(NULL); + + // Wait for other clusters to complete execution and then unmount them. + for (unsigned i = 1; i < NB_CLUSTERS; i++) + { + while (!finished[i]) + { + rt_time_wait_cycles(256); + } + rt_cluster_mount(0, i, 0, NULL); + } + + // Send EOC. + *(volatile unsigned int *)0x1B200000 = 1; + + return 0; +} diff --git a/sw/runtime/src/spin_dma.h b/sw/runtime/src/spin_dma.h new file mode 100644 index 0000000..4cb11a7 --- /dev/null +++ b/sw/runtime/src/spin_dma.h @@ -0,0 +1,119 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Thomas Benz + +// AXI DMA library for the spinningpulp soc + +#include "libaxidma.h" + +// cluster address ofsets +#define CLUSTER_BASE 0x10000000 +#define DMA_OFFSET 0x1800 + +#define PRIVATE_DMA_BASE ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET +#define PUPLIC_DMA_BASE CLUSTER_BASE + ARCHI_CLUSTER_PERIPHERALS_OFFSET + DMA_OFFSET + + +// non-blocking private transfer +static inline uint32_t spin__memcpy_nonblk( + void* src_addr, + void* dst_addr, + uint32_t num_bytes +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + return axidma__memcpy_nonblk(dma, src_addr, dst_addr, num_bytes); +} + + +// blocking private transfer +static inline void spin__memcpy( + void* src_addr, + void* dst_addr, + uint32_t num_bytes +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + axidma__memcpy(dma, src_addr, dst_addr, num_bytes); +} + + +// wait for a given private transaction to complete +static inline void spin__wait_for_tf_completion( + uint32_t tf_id +) { + + // spin until transfer is completed + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + while (tf_id > axidma__read_completed_id(dma)) { + asm volatile ("nop"); + } +} + + +// test if a given private transaction has been completed +static inline char spin__tf_completed( + uint32_t tf_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PRIVATE_DMA_BASE); + return (tf_id <= axidma__read_completed_id(dma)); +} + + +// non-blocking public transfer +static inline uint32_t spin__public_memcpy_nonblk( + void* src_addr, + void* dst_addr, + uint32_t num_bytes, + uint32_t cluster_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + return axidma__memcpy_nonblk(dma, src_addr, dst_addr, num_bytes); +} + + +// blocking public transfer +static inline void spin__public_memcpy( + void* src_addr, + void* dst_addr, + uint32_t num_bytes, + uint32_t cluster_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + axidma__memcpy(dma, src_addr, dst_addr, num_bytes); +} + + +// wait for a given private transaction to complete +static inline void spin__public_wait_for_tf_completion( + uint32_t tf_id, + uint32_t cluster_id +) { + + // spin until transfer is completed + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + while (tf_id > axidma__read_completed_id(dma)) { + asm volatile ("nop"); + } +} + + +// test if a given private transaction has been completed +static inline char spin__public_tf_completed( + uint32_t tf_id, + uint32_t cluster_id +) { + + axidma__dma_conf_t* dma = (axidma__dma_conf_t* )(PUPLIC_DMA_BASE + cluster_id * ARCHI_CLUSTER_SIZE); + return (tf_id <= axidma__read_completed_id(dma)); +} diff --git a/sw/scripts/benchmark.py b/sw/scripts/benchmark.py new file mode 100755 index 0000000..d689240 --- /dev/null +++ b/sw/scripts/benchmark.py @@ -0,0 +1,154 @@ +#!/bin/python3 + +# Copyright (C) 2020 ETH Zurich +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Authors: +# Elias Stalder, ETH (staldere@student.ethz.ch) + +import pandas as pd +import subprocess +import os +from pathlib import Path +import sys +import argparse + +def to_name(make_defs, code_defs): + return ('.'.join([f'{key}={value}'for key, value in make_defs.items()]) \ + + ('.' if len(make_defs) > 0 and len(code_defs) > 0 else '') \ + + '.'.join(code_defs)).replace('=', '-') + +def get_filename(cmd, name, suffix): + return f'{cmd}.{name}.{suffix}' + +def run(folder, name, cmd_name, cmd, environment, cwd, suffix='log', to_stdout=False): + if to_stdout: + subprocess.run(cmd, env=environment, check=True, cwd=cwd) + else: + with open(os.path.join(folder, get_filename(cmd_name, name, suffix)), 'w') as f: + subprocess.run(cmd, stdout=f, env=environment, check=True, cwd=cwd) + +START_COLS = ['CLUSTER', 'CORE', 'START_TIME'] +END_COLS = ['CLUSTER', 'CORE', 'END_TIME', 'MSG_ID', 'PKT_SIZE'] +COLS = ['CLUSTER', 'CORE', 'END_TIME', 'START_TIME', 'LATENCY', 'MSG_ID', 'PKT_SIZE'] + +def handler_latencies(folder, name): + with open(os.path.join(folder, get_filename('sim', name, 'log')), 'r') as f: + starts = [] + ends = [] + for line in f: + if 'HANDLER_START' in line: + line = line.strip() + parts = line.split(':') + time = parts[0][1:-7] + parts = parts[1].split(' ') + starts += [[int(parts[3]), int(parts[4]), int(time)]] + elif 'HANDLER_TIME' in line: + line = line.strip() + parts = line.split(':') + time = parts[0][1:-7] + parts = parts[1].split(' ') + ends += [[int(parts[3]), int(parts[4]), int(time), int(parts[5]), int(parts[8])]] + + df_start = pd.DataFrame(data=starts, columns=START_COLS).sort_values(by=START_COLS).reset_index()[START_COLS].reset_index() + df_end = pd.DataFrame(data=ends, columns=END_COLS).sort_values(by=['CLUSTER', 'CORE', 'END_TIME']).reset_index()[END_COLS].reset_index() + df = df_start.merge(df_end, on=['index', 'CORE', 'CLUSTER']) + df['START_TIME'] = df['START_TIME'] / 1000 + df['END_TIME'] = df['END_TIME'] / 1000 + df['LATENCY'] = df['END_TIME'] - df['START_TIME'] + df[['START_TIME', 'END_TIME', 'LATENCY']] = df[['START_TIME', 'END_TIME', 'LATENCY']].astype(int) + df = df[COLS] + df.to_csv( + path_or_buf=os.path.join(folder, get_filename('handlers', name, 'csv')), + sep=' ', + index=False, + header=True + ) + +def run_benchmark(out_folder, make_defs, code_defs, args): + name = to_name(make_defs, code_defs) + environment = {**dict(os.environ), **make_defs} + defs = ' '.join([f'-D{d}' for d in code_defs]) + environment['DEFINITIONS'] = f'{defs}' + + print(name) + print(environment) + + if (not args.repeat) and (os.path.isfile(os.path.join(out_folder, get_filename('handlers', name, 'csv')))): + print('skip') + return + + run(out_folder, name, 'patch', ['make', 'patch'], environment, args.cwd) + run(out_folder, name, 'deploy', ['make', 'deploy'], environment, args.cwd) + if args.generator: + run(out_folder, name, 'generator', ['make', 'generator'], environment, args.cwd) + run(out_folder, name, 'packets', ['make', 'packets'], environment, args.cwd) + sim_cmd = 'simulate' + if args.debug: + sim_cmd = 'simulate-debug' + try: + run(out_folder, name, 'simulate', ['make', sim_cmd], environment, args.cwd, to_stdout=True) + except KeyboardInterrupt as e: + print(e) + run(out_folder, name, 'sim', ['make', 'transcript'], environment, args.cwd) + run(out_folder, name, 'trace', ['make', 'trace-stdout'], environment, args.cwd, suffix='txt') + run(out_folder, name, 'trace', ['make', 'trace-chrome-stdout'], environment, args.cwd, suffix='json') + + handler_latencies(out_folder, name) + +def convert_dict_entry(entry): + key, value = entry + if value == False or value == 'False': + return None + elif value == True or value == 'True': + return f'{key}' + else: + return f'{key}={value}' + +parser = argparse.ArgumentParser(description='') +parser.add_argument('--debug', dest='debug', action='store_true', help='to enable debuggin mode of simulator') +parser.add_argument('--generator', dest='generator', action='store_true', help='to also build packet-generator (make generator has to be defined)') +parser.add_argument('--repeat', dest='repeat', action='store_true', help='to override existing benchmarks with same names') +parser.add_argument('--cwd', dest='cwd', action='store', default='./', type=str, help='to set working directory') +parser.add_argument('--code', dest='code_defs', action='store', default='definitions.code.csv', type=str, help='to specify c flags') +parser.add_argument('--make', dest='make_defs', action='store', default='definitions.make.csv', type=str, help='to specify make definitions') +args = parser.parse_args() + +df_make = pd.read_csv( + filepath_or_buffer=args.make_defs, + sep="\\s+", + quotechar='"', + comment='#', +) +df_make = df_make.astype(str) + +df_code = pd.read_csv( + filepath_or_buffer=args.code_defs, + sep="\\s+", + quotechar='"', + comment='#', +) +code_definitions = [ + list(filter(None, [convert_dict_entry(e) for e in list(d.items())])) for d in df_code.to_dict(orient='records') +] + +OUT_FOLDER = os.path.join(os.path.join(args.cwd, 'out'), os.environ['CONTAINER_NAME']) +Path(OUT_FOLDER).mkdir(parents=True, exist_ok=True) + +try: + for make_defs in df_make.to_dict(orient='records'): + for code_defs in code_definitions: + run_benchmark(OUT_FOLDER, make_defs, code_defs, args) +except subprocess.CalledProcessError as e: + print(e) diff --git a/sw/scripts/extract_info.sh b/sw/scripts/extract_info.sh new file mode 100755 index 0000000..4579d00 --- /dev/null +++ b/sw/scripts/extract_info.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +info_key=$1 +transcript_file=$2 + +info_key_parsed=$(echo $info_key | sed "s/,/ /g") + +#cat $transcript_file | grep INFO | cut -d " " -f 2-4 | sed "s/\(.*\)/$info_key_parsed \1/g" + + +cat $transcript_file | grep INFO | sed "s/\[\([0-9]*\)\]\[.*\]: INFO \([^ ]*\) .*/$info_key_parsed \2 \1/g" diff --git a/sw/scripts/handlers_data.sh b/sw/scripts/handlers_data.sh new file mode 100755 index 0000000..7d92e8e --- /dev/null +++ b/sw/scripts/handlers_data.sh @@ -0,0 +1,112 @@ +#!/bin/bash + +#15067000 15063 1000 00 0 spin_host_write 1d000426 handler.h:267 add "add x13, x13, x0 x13=00000000 x13:00000000" + +key=$1 +trace_file=$2 +#pc_handler_start=$2 +#pc_handler_end=$3 + +cfile=$PSPIN_RT/src/hpu.c + +hstart_line=$(grep -nH "TELEMETRY: HANDLER:START" $cfile) +hstop_line=$(grep -nH "TELEMETRY: HANDLER:END" $cfile) + +old_ifs=$IFS +IFS=$':'; + +hstart_line_array=($hstart_line); +hstart_linenum="${hstart_line_array[1]}"; + +hstop_line_array=($hstop_line); +hstop_linenum="${hstop_line_array[1]}"; + +IFS=$old_ifs + +cfile=$(basename $cfile) +hstart_coord="$cfile:$hstart_linenum" +hstop_coord="$cfile:$hstop_linenum" + +echo "#START: $hstart_coord; END: $hstop_coord" + +echo "#[key] handler cluster_id core_id start_time end_time latency instructions loads stores bsws branches l2_accesses local_l1_accesses remote_l1_accesses other_accesses" + +for cluster_id in 00 01 02 03; do + for hpu_id in 0 1 2 3 4 5 6 7; do + + trace=$(cat $trace_file | grep " $cluster_id $hpu_id ") + + echo "$trace" | gawk -v start="$hstart_coord" -v end="$hstop_coord" -v core_id="$hpu_id" -v cluster_id="$cluster_id" -v key="$key" \ + 'BEGIN{count=0; counting=0; start_time=0; new_handler=0;} + { + if ($8==start) { + counting=1; + #start_time=$1; + loads=0; + stores=0; + branches=0; + bsws=0; + l2_accesses=0; + local_l1_accesses=0; + remote_l1_accesses = 0; + other_accesses = 0; + handler="none"; + new_handler=1; + next; + } + + if (new_handler==1) { + start_time=$1; + new_handler=0; + } + + if (counting==1) { + + if ($9~/lw|lb|lh/) loads = loads + 1; + + is_mem_access = match($0, /PA:([0-9a-fA-F]+)/, addr_match); + if (is_mem_access) { + + #remote vs local accesses + if ($0~/PA:1c/) l2_accesses = l2_accesses + 1; + else { + + addr = strtonum("0x" addr_match[1]); + #print addr_match[1]; + addr_cluster_target = -1; + if (addr >= 0x10000000 && addr < 0x10400000) addr_cluster_target = 0; + else if (addr >= 0x10400000 && addr < 0x10800000) addr_cluster_target = 1; + else if (addr >= 0x10800000 && addr < 0x10c00000) addr_cluster_target = 2; + else if (addr >= 0x10c00000 && addr < 0x11000000) addr_cluster_target = 3; + + if (addr_cluster_target == int($4)) local_l1_accesses = local_l1_accesses + 1; + else if (addr_cluster_target != -1) remote_l1_accesses = remote_l1_accesses + 1; + else { + #print "other access: " addr_match[1]; + other_accesses = other_accesses + 1; + } + } + } + + + if ($9=="bsw") bsws = bsws + 1; + else if ($9~/sw|sb|sh/) stores = stores + 1; + + if ($9~/beq|bne|blt|bge/) branches = branches + 1; + + if ($6~/_ph$|_hh$|_th$/) handler=$6; + + count = count+1; + } + + if ($8==end) { + counting=0; + end_time=$1 + latency=end_time - start_time; + print key " " handler " " cluster_id " " core_id " " start_time " " end_time " " latency " " count " " loads " " stores " " bsws " " branches " " l2_accesses " " local_l1_accesses " " remote_l1_accesses " " other_accesses; + count=0; + } + }' + done +done + diff --git a/sw/scripts/handlers_duration.sh b/sw/scripts/handlers_duration.sh new file mode 100755 index 0000000..891d525 --- /dev/null +++ b/sw/scripts/handlers_duration.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +cat $1 | grep INFO | grep "HANDLER_START\|HPU_TIME" | cut -f 1-5 -d " " | sed "s/\[\([0-9]*\)\]\[.*\]:\(.*\)/\1\2/g" | sort -k 1 -n | sort -k 4,5 -s | awk '{if (NR % 2) {prev=$1} else {diff=$1-prev; starttime=prev; prev=$1; print $1 " " $4 " " $5 " " $4 $5 " " diff " " starttime;}}' > data.tmp + + +cat $1 | grep INFO | grep "HANDLER_START\|HPU_TIME" | cut -f 1-5 -d " " | sed "s/\[\([0-9]*\)\]\[.*\]:\(.*\)/\1\2/g" | sort -k 1 -n | sort -k 4,5 -s | awk 'BEGIN {max=0; min=0; sum=0; count=0;} {if (NR % 2) {prev=$1} else {diff=$1-prev; starttime=prev; prev=$1; sum+=diff; count++; if (NR==2) { max=diff; min=diff; } else { max = (max>diff) ? max : diff; min = (min= args.min_time] +if args.max_time >= 0: + df = df[df['CYCLE'] < args.max_time] +if args.cluster >= 0: + df = df[df['CLUSTER'] == args.cluster] +if args.core >= 0: + df = df[df['CORE'] == args.core] +if len(args.next_file) > 0: + df = df.reset_index() + df['TO_KEEP'] = False + df['NEXT_FILE'] = 'file' + for i in range(len(df)-1): + df.loc[i, 'TO_KEEP'] = df.loc[i+1, 'FILE'] == args.next_file + df.loc[i, 'NEXT_FILE'] = df.loc[i+1, 'FILE'] + df = df[df['TO_KEEP']] +if len(args.pc) > 0: + df = df[df['PC'] == args.pc] +if len(args.pa) > 0: + df = df[df['OP'].str.contains(f'PA:{args.pa}')] +if len(args.file) > 0: + df = df[df['FILE'].str.contains(args.file)] +for op in args.op: + df = df[df['OP'].str.match(op)] +if args.user_only: + df = df[df['FILE'].str.contains('init.c:') == False] + df = df[df['FILE'].str.contains('hpu.c:') == False] + df = df[df['FILE'].str.contains('riscv_v4.h:') == False] + df = df[df['FILE'].str.contains('icache_ctrl_v2.h:') == False] + df = df[df['FILE'].str.contains('pspin_rt.h:') == False] + df = df[df['FILE'] != 'None'] + +if len(args.sort) > 0: + df = df.sort_values(by=[args.sort]) +else: + df = df.sort_values(by=['CYCLE']) + +if args.head >= 0: + df = df.head(args.head) +if args.tail >= 0: + df = df.tail(args.tail) + +pd.set_option('display.max_rows', None) +pd.set_option('display.max_columns', None) +pd.set_option('display.width', None) +pd.set_option('display.max_colwidth', None) + +print(df.reset_index()) + diff --git a/sw/scripts/make_packets.sh b/sw/scripts/make_packets.sh new file mode 100755 index 0000000..9cce010 --- /dev/null +++ b/sw/scripts/make_packets.sh @@ -0,0 +1,27 @@ +#!/bin/bash + + +num_packets=$1 +spin_app_name=$2 +handlers_prefix=$3 +pkt_length=$4 +pkt_delay=$5 +msg_delay=$6 +full_pkt=$7 +num_msgs=$8 +pktgen_bin=$9 +pktgen_params=${10} +has_hh=${11} +has_th=${12} +pkt_seed=${13} +custom_hdr_size=${14} + +echo "CUSTOM HDR SIZE: $custom_hdr_size" +if [ ! -f "$pktgen_bin" ]; then + echo "Generic packet generator not found! Please build $pktgen_bin!" + exit 1 +fi +echo $pktgen_params + +$pktgen_bin --msg-count=$num_msgs --count=$num_packets --pkt-length=$pkt_length --binary="build/$spin_app_name" --handler-prefix="$handlers_prefix" --pkt-delay=$pkt_delay --msg-delay=$msg_delay --full-pkt=$full_pkt --has-hh=$has_hh --has-th=$has_th --target-dir=$PSPIN_HW/sim_files/ --seed=$pkt_seed --custom-hdr=$custom_hdr_size ${pktgen_params} + diff --git a/sw/scripts/telemetry.sh b/sw/scripts/telemetry.sh new file mode 100755 index 0000000..2bf3433 --- /dev/null +++ b/sw/scripts/telemetry.sh @@ -0,0 +1,73 @@ +#/bin/bash + +binary=$1 +traces_dir=$2 +key="$3" +cfiles="$4" +traces="trace_core_*.log" + +echo "#" > data.telemetry.time +echo -n "#" > data.telemetry.instr +key=${key/,/ } +echo "key: $key" +gdb_regex='s/.*0x\([a-f0-9]\+\).*0x.*/\1/' +trace_regex='s/\(.*\):[0-9]*:[ ]*[0-9]*[ ]*\([0-9]*\).*/\1 \2/g' +lines=$(grep -nH "TELEMETRY" $cfiles | sed "s/\(.*\):\([0-9]*\):.*TELEMETRY:[ ]*\([^;]*\).*/\1 \2 \3/g"); +echo $cfiles +echo $lines +IFS=$'\n' +for line in $lines; do + IFS=$' ' + linearr=($line); + IFS=$'\n' + + file=${linearr[0]} + line=${linearr[1]} + label=${linearr[2]} + + pc=$(gdb $binary -ex "info line ${file}:${line}" --batch | sed "$gdb_regex") + grep -n "\s*[0-9]*\s[0-9]*\s${pc}.*" $traces | sed "$trace_regex" | awk -v pc="$pc" -v label="$label" -v key="$key" 'NR==1{old=$2;}{diff=$2-old; print key " " label " " $1 " " pc " " $2 " " diff; old=$2;}' >> data.telemetry.time + + if [[ $label == *":STOP"* ]]; then + #echo "skipping STOP range label" + continue; + fi + + echo "# LABEL: $label; FILE: $file; LINE: $line; PC: $pc" + #continue; + + if [[ $label == *":START"* ]]; then + stop_label=${label/START/STOP}; + label_name=${label/\:START/}; + + stop_label_code=($(grep -n "TELEMETRY: $stop_label" $PSPIN_RT/src/*.c | sed "s/\(.*\):\([0-9]*\):.*TELEMETRY:[ ]*\([^;]*\).*/\1 \2 \3/g")); + + IFS=$' ' + stop_label_code=($stop_label_code) + IFS=$'\n' + + stop_label_file=${stop_label_code[0]} + stop_label_line=${stop_label_code[1]} + + stop_label_pc=$(gdb $binary -ex "info line ${stop_label_file}:${stop_label_line}" --batch | sed "$gdb_regex") + echo " --> THIS IS A RANGE LABEL: $label_name! Stop label: $stop_label; file: $stop_label_file; line: $stop_label_line; pc: $stop_label_pc" + + files=$(grep -r "$pc" $traces | sed "s/\([^:]\):.*/\1/g" | uniq) + for file in $(ls $files); do + cat $file | awk -v pc_start="$pc" -v pc_stop="$stop_label_pc" -v label_name="$label_name" -v f="$file" -v key="$key" 'NR==1{printf " 0"; next;}NR==2{id=-1; old=$2; pid=id;}{diff=$2-old; if ($3==pc_start) {id=id+1; pid=id}; if ($3==pc_stop) {pid=-1;} printf " " diff "\n" key " " f " " label_name " " pid " " $2 " " $3 " " $5; old=$2}' >> data.telemetry.instr + echo -n -e " 0\n#" >> data.telemetry.instr + #the last ID should be removed from the analysis. The last instruction of the last ID has time 0. + #the ID -1 are the instr before the first appearance of the selected PC. + done; + + else + + files=$(grep -r "$pc" $traces | sed "s/\([^:]\):.*/\1/g" | uniq) + for file in $(ls $files); do + cat $file | awk -v pc="$pc" -v label="$label" -v f="$file" -v key="$key" 'NR==1{printf " 0"; next;}NR==2{id=-1; old=$2;}{diff=$2-old; if ($3==pc) {id=id+1;}; printf " " diff "\n" key " " f " " label " " id " " $2 " " $3 " " $5; old=$2}' >> data.telemetry.instr + echo -n -e " 0\n#" >> data.telemetry.instr + #the last ID should be removed from the analysis. The last instruction of the last ID has time 0. + #the ID -1 are the instr before the first appearance of the selected PC. + done; + fi; +done; diff --git a/sw/scripts/telemetry_instructions_tracevis.sh b/sw/scripts/telemetry_instructions_tracevis.sh new file mode 100755 index 0000000..dac69a3 --- /dev/null +++ b/sw/scripts/telemetry_instructions_tracevis.sh @@ -0,0 +1,109 @@ +#!/bin/bash + +trace="$1"; +key="$2"; +cfiles="$3"; + +clines=$(grep -nH "TELEMETRY" $cfiles | sed "s/\(.*\):\([0-9]*\):.*TELEMETRY:[ ]*\([^;]*\).*/\1 \2 \3/g"); +IFS=$'\n'; + + +clean_trace="" + +for cline in $clines; do + IFS=$' '; + cline_array=($cline); + + file_start=$(basename "${cline_array[0]}"); + line_start="${cline_array[1]}"; + label="${cline_array[2]}"; + label_name=$label + + if [[ $label == *":START"* ]]; then + label_name=${label/\:START/}; + label_end="$label_name END"; + + cline_end=$(echo "$clines" | grep "$label_name:END"); + cline_end_array=($cline_end); + file_end=$(basename "${cline_end_array[0]}"); + line_end="${cline_end_array[1]}"; + + elif [[ $label == *":END"* ]]; then + continue; + else + file_end=$file_start + line_end=$line_start + fi; + + echo "#$label start: $file_start:$line_start; end: $file_end:$line_end" + core_ids="$(cat $trace | grep "${file_start}:${line_start}" | cut -d " " -f 4,5 | uniq)"; + + + + IFS=$'\n'; + for core_id in $core_ids; do + IFS=$' '; + + #echo "core_id: $core_id" + + cat $trace | grep " $core_id " | + awk -v start="$file_start:$line_start" -v end="$file_end:$line_end" -v label="$label_name" -v core_id="$core_id" -v key="$key" \ + 'BEGIN{count=0; counting=0; start_time=0;} + { + if ($8==start && $9=="nop" && counting==0){ + counting=1; + start_time=$1; + loads=0; + stores=0; + branches=0; + bsws=0; + l2_accesses=0; + handler="none"; + next; + } + + if (counting==1) { + + if ($9~/lw|lb|lh/) loads = loads + 1; + + if ($0~/PA:1c/) l2_accesses = l2_accesses + 1; + + if ($9=="bsw") bsws = bsws + 1; + else if ($9~/sw|sb|sh/) stores = stores + 1; + + if ($9~/beq|bne|blt|bge/) branches = branches + 1; + + if ($6~/_ph$|_hh$|_th$/) handler=$6; + + count = count+1; + } + + + + if ($8==end && $9=="nop") { + counting=0; + end_time=$1 + latency=end_time - start_time; + print key " " label " " handler " " core_id " " start_time " " end_time " " latency " " count " " loads " " stores " " bsws " " branches " " l2_accesses; + count=0; + + if ($8 == start) { + counting=1; + start_time=$1; + loads=0; + stores=0; + branches=0; + bsws=0; + l2_accesses=0; + handler="none"; + } + + } + + }' + done +done; + + + + diff --git a/sw/scripts/telemetry_time_tracevis.sh b/sw/scripts/telemetry_time_tracevis.sh new file mode 100755 index 0000000..66e504d --- /dev/null +++ b/sw/scripts/telemetry_time_tracevis.sh @@ -0,0 +1,39 @@ +#!/bin/bash + +trace="$1"; +key="$2"; +cfiles="$3"; + +clines=$(grep -nH "TELEMETRY" $cfiles | sed "s/\(.*\):\([0-9]*\):.*TELEMETRY:[ ]*\([^;]*\).*/\1 \2 \3/g"); +IFS=$'\n'; + + +for cline in $clines; do + IFS=$' '; + cline_array=($cline); + + file=$(basename "${cline_array[0]}"); + line="${cline_array[1]}"; + label="${cline_array[2]}"; + + echo "#file: $file; line: $line; label: $label"; + + if [[ $label == *":START"* ]]; then + label_name=${label/\:START/}; + label="$label_name START"; + + elif [[ $label == *":END"* ]]; then + label_name=${label/\:END/}; + label="$label_name END"; + else + label="$label SINGLE" + fi; + + trace_lines=$(cat $trace | grep "${file}:$line" | sed "s/\(.*\)/$key $label \1/g"); + + echo $trace_lines + + IFS=$'\n'; +done + + diff --git a/sw/scripts/tracevis/README.md b/sw/scripts/tracevis/README.md new file mode 100644 index 0000000..fb7b39a --- /dev/null +++ b/sw/scripts/tracevis/README.md @@ -0,0 +1,38 @@ +# tracevis + +**Requires:** perl >= v5.26; addr2line >= 2.30. Could work with lower versions too, but it is not tested. + +**Usage:** +```perl ./parse.pl [-i] [-p] ... ``` + +The trace files are expected to be the ones produced by RI5CY cores in RTL simulation (default) or GVSOC virtual platform (with `-g` flag). + +**Output:** JSON that can be loaded into chrome tracing (about://tracing from chrome or chromium) + +**Options:** + - ```-i```: inlines instructions. Even if a function is inlined, it is still possible to see the inlined function. By default we show + the origin function name, even if it inlined. If this option is specified the instructions are shown as belonging to the inlining function. + - ```-p```: labels the instruction with the PC instead of the instruction type. + - ```-g```: parses traces produced by GVSOC running with `--trace=/sys--trace=/sys/board/chip/cluster/pe0:pe0.log` (or similar for other cores). + +**Example:** +The example/ folder contains: + - bin/pulp_api_example: a sample binary; + - traces/trace*.log: the per-core RI5CY traces produced by the RTL simulation of the above binary file; + - chrome.json: the output file produced by the script when the above binary and traces are given as input. + +The chrome.json can be produced by running the following command: +``` +perl parse.pl example/bin/pulp_api_example example/traces/trace_core_0*.log > chrome.json +``` + +**Known Limitations:** +The tracer embedded in Google Chrome (`chrome://tracing`) is not able to open very large traces. +Empirically we saw that up to ~500k events can be managed. Things that can help: + - Gzipping the trace + - Slicing the JSON trace in https://github.com/facebook/buck/blob/d609be052ddd49a746e185fadf6df08cc19af6d2/scripts/slice_trace.py + - Try switching to Catapult Trace-Viewer: https://chromium.googlesource.com/catapult/+/HEAD/tracing/README.md. It will compile the json trace to a HTML page (still requires a chromium-based browser to open it). + ``` + $CATAPULT/tracing/bin/trace2html my_trace.json --output=my_trace.html && open my_trace.html + ``` + - Using another visualizer? diff --git a/sw/scripts/tracevis/example/bin/pulp_api_example b/sw/scripts/tracevis/example/bin/pulp_api_example new file mode 100755 index 0000000..4a661e7 Binary files /dev/null and b/sw/scripts/tracevis/example/bin/pulp_api_example differ diff --git a/sw/scripts/tracevis/example/chrome.json b/sw/scripts/tracevis/example/chrome.json new file mode 100644 index 0000000..b98a6a0 --- /dev/null +++ b/sw/scripts/tracevis/example/chrome.json @@ -0,0 +1,30955 @@ +{"traceEvents": [ +{"name": "jal", "cat": "jal", "ph": "X", "ts": 79, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_start", "args":{"pc": "1c000080", "instr": "jal x0, 24 ", "time": "79", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 101, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000000", "time": "101", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 102, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000000 x10:00000000", "time": "102", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 125, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000000 x10:00000000", "time": "125", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 126, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000000", "time": "126", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 149, "dur": 48, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000aa", "instr": "beq x10, x0, 8 x10:00000000", "time": "149", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:44"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 197, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000b2", "instr": "auipc x5, 0x2000 x5=1c0020b2", "time": "197", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:82"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 198, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000b6", "instr": "addi x5, x5, 1350 x5=1c0025f8 x5:1c0020b2", "time": "198", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:82"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 199, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000ba", "instr": "auipc x6, 0x2000 x6=1c0020ba", "time": "199", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:83"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 222, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000be", "instr": "addi x6, x6, 1522 x6=1c0026ac x6:1c0020ba", "time": "222", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:83"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 223, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c0025f8 PA:1c0025f8", "time": "223", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c0025fc x5:1c0025f8", "time": "241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 242, "dur": 39, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c0025fc x6:1c0026ac", "time": "242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 281, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c0025fc PA:1c0025fc", "time": "281", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 299, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002600 x5:1c0025fc", "time": "299", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 300, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002600 x6:1c0026ac", "time": "300", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 329, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002600 PA:1c002600", "time": "329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 347, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002604 x5:1c002600", "time": "347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 348, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002604 x6:1c0026ac", "time": "348", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 377, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002604 PA:1c002604", "time": "377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 395, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002608 x5:1c002604", "time": "395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 396, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002608 x6:1c0026ac", "time": "396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 425, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002608 PA:1c002608", "time": "425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 443, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c00260c x5:1c002608", "time": "443", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 444, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c00260c x6:1c0026ac", "time": "444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 473, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c00260c PA:1c00260c", "time": "473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 491, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002610 x5:1c00260c", "time": "491", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 492, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002610 x6:1c0026ac", "time": "492", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 521, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002610 PA:1c002610", "time": "521", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 539, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002614 x5:1c002610", "time": "539", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 540, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002614 x6:1c0026ac", "time": "540", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 569, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 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"cat": "sw", "ph": "X", "ts": 713, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002620 PA:1c002620", "time": "713", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 731, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002624 x5:1c002620", "time": "731", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 732, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002624 x6:1c0026ac", "time": "732", "Origin": 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"cat": "bltu", "ph": "X", "ts": 924, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002634 x6:1c0026ac", "time": "924", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 953, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002634 PA:1c002634", "time": "953", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002638 x5:1c002634", "time": "971", "Origin": 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x5, 4 x5=1c00263c x5:1c002638", "time": "1019", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 1020, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c00263c x6:1c0026ac", "time": "1020", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 1049, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c00263c PA:1c00263c", "time": "1049", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 1067, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c6", "instr": "addi x5, x5, 4 x5=1c002640 x5:1c00263c", "time": "1067", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 1068, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002640 x6:1c0026ac", "time": "1068", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 1097, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002640 PA:1c002640", "time": "1097", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 1115, "dur": 1, "pid": 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x5, 4 x5=1c002674 x5:1c002670", "time": "1691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:90"}}, +{"name": "bltu", "cat": "bltu", "ph": "X", "ts": 1692, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c8", "instr": "bltu x5, x6, -6 x5:1c002674 x6:1c0026ac", "time": "1692", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:92"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 1721, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000c2", "instr": "sw x0, 0(x5) x5:1c002674 PA:1c002674", "time": "1721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:89"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 1739, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020cc", "instr": "lui x15, 0x1c002000 x15=1c002000", "time": "4952", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:217"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 4969, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020d0", "instr": "sw x0, 1640(x15) x15:1c002000 PA:1c002668", "time": "4969", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:217"}}, +{"name": "or", "cat": "or", "ph": "X", "ts": 4987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020d4", "instr": "or x10, x10, x8 x10=00000000 x10:00000000 x8:00000000", "time": "4987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:214"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 4988, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020d6", "instr": "beq x10, x0, 34 x10:00000000", "time": "4988", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:219"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5007, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020f8", "instr": "lw x1, 12(x2) x1=1c000d08 x2:10000960 PA:1000096c", "time": "5007", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:220"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5008, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020fa", "instr": "lw x8, 8(x2) x8=10000990 x2:10000960 PA:10000968", "time": "5008", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:220"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5009, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020fc", "instr": "addi x2, x2, 16 x2=10000970 x2:10000960", "time": "5009", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:220"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 5010, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_init", "args":{"pc": "1c0020fe", "instr": "jalr x0, x1, 0 x1:1c000d08", "time": "5010", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:220"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 5027, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "do_ctors", "args":{"pc": "1c000d08", "instr": "jal x0, -108 ", "time": "5027", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:38"}}, +{"name": "p.lw", "cat": "p.lw", "ph": "X", "ts": 5029, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "do_ctors", "args":{"pc": "1c000c9c", "instr": "p.lw x15, 4(x9!) x15=00000000 x9=10000180 x9:1000017c PA:1000017c", "time": "5029", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:37"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 5031, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "do_ctors", "args":{"pc": "1c000ca0", "instr": "bne x15, x0, 102 x15:00000000", "time": "5031", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:37"}}, +{"name": "csrrwi", "cat": "csrrwi", "ph": "X", "ts": 5032, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c000ca2", "instr": "csrrwi x0, 0x00000008, 0x300", "time": "5032", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5036, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init", "args":{"pc": "1c000ca6", "instr": "addi x10, x0, 0 x10=00000000", "time": "5036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 5037, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init", "args":{"pc": "1c000ca8", "instr": "jal x1, 406 x1=1c000caa", "time": "5037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:122"}}, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 5058, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e46", "instr": "slli x10, x10, 0x2 x10=00000000 x10:00000000", "time": "5058", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5059, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e48", "instr": "addi x8, x8, 88 x8=10000058 x8:10000000", "time": "5059", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5060, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e4c", "instr": "lw x8, x10(x8) x8=1c2fffe0 x10:00000000 x8:10000058 PA:10000058", "time": "5060", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5077, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e50", "instr": "sw x1, 12(x2) x1:1c000caa x2:10000960 PA:1000096c", "time": "5077", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:72"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 5078, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e52", "instr": "bne x8, x0, 12 x8:1c2fffe0", "time": "5078", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:74"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5081, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e5e", "instr": "lw x15, 0(x8) x15=1c0017b8 x8:1c2fffe0 PA:1c2fffe0", "time": "5081", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5095, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e60", "instr": "lw x10, 4(x8) x10=00000000 x8:1c2fffe0 PA:1c2fffe4", "time": "5095", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 5109, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e62", "instr": "jalr x1, x15, 0 x1=1c000e64 x15:1c0017b8", "time": "5109", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5115, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017b8", "instr": "addi x2, x2, -32 x2=10000940 x2:10000960", "time": "5115", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:445"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5116, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017ba", "instr": "addi x10, x2, 8 x10=10000948 x2:10000940", "time": "5116", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:449"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5117, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017bc", "instr": "sw x1, 28(x2) x1:1c000e64 x2:10000940 PA:1000095c", "time": "5117", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:445"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 5134, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017be", "instr": "jal x1, 2144 x1=1c0017c2", "time": "5134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:449"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 5152, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_uart_conf_init", "args":{"pc": "1c00201e", "instr": "lui x15, 0x1c000 x15=0001c000", "time": "5152", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:65"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5169, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_uart_conf_init", "args":{"pc": "1c002020", "instr": "addi x15, x15, 512 x15=0001c200 x15:0001c000", "time": "5169", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:65"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5170, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_uart_conf_init", "args":{"pc": "1c002024", "instr": "sw x15, 0(x10) x15:0001c200 x10:10000948 PA:10000948", "time": "5170", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:65"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 5171, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_uart_conf_init", "args":{"pc": "1c002026", "instr": "jalr x0, x1, 0 x1:1c0017c2", "time": "5171", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:66"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 5173, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017c2", "instr": "lui x15, 0x1c000 x15=0001c000", "time": "5173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:451"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5174, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017c6", "instr": "addi x15, x15, 512 x15=0001c200 x15:0001c000", "time": "5174", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:451"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5175, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017ca", "instr": "sw x15, 8(x2) x15:0001c200 x2:10000940 PA:10000948", "time": "5175", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:95"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5660, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fc8", "instr": "sw x11, 0(x14) x11:000000a7 x14:1a102008 PA:1a102008", "time": "5660", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:96"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5680, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fca", "instr": "addi x14, x0, 3 x14=00000003", "time": "5680", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:97"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5681, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fcc", "instr": "sw x14, 0(x12) x14:00000003 x12:1a10200c PA:1a10200c", "time": "5681", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:97"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5701, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fce", "instr": "lw x14, 0(x13) x14=00000000 x13:1a102004 PA:1a102004", "time": "5701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:99"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5718, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fd0", "instr": "addi x15, x15, 16 x15=1a102010 x15:1a102000", "time": "5718", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:100"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 5719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fd2", "instr": "andi x14, x14, 240 x14=00000000 x14:00000000", "time": "5719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:99"}}, +{"name": "p.bset", "cat": "p.bset", "ph": "X", "ts": 5720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fd6", "instr": "p.bset x14, x14, 0, 1 x14=00000002 x14:00000000", "time": "5720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:99"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5721, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fda", "instr": "sw x14, 0(x13) x14:00000002 x13:1a102004 PA:1a102004", "time": "5721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:99"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5741, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fdc", "instr": "addi x14, x0, 32 x14=00000020", "time": "5741", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:100"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5742, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fe0", "instr": "sw x14, 0(x15) x14:00000020 x15:1a102010 PA:1a102010", "time": "5742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:100"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 5762, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_setup", "args":{"pc": "1c001fe2", "instr": "jalr x0, x1, 0 x1:1c00207a", "time": "5762", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:101"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 5763, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c00207a", "instr": "csrrw x0, x9, 0x300 x9:00001808", "time": "5763", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5780, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_open", "args":{"pc": "1c00207e", "instr": "addi x10, x8, 1640 x10=1c002668 x8:1c002000", "time": "5780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:165"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 5781, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_open", "args":{"pc": "1c002082", "instr": "jal x0, -36 ", "time": "5781", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:165"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5799, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_open", "args":{"pc": "1c00205e", "instr": "lw x1, 12(x2) x1=1c0017f0 x2:10000930 PA:1000093c", "time": "5799", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:166"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5816, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_open", "args":{"pc": "1c002060", "instr": "lw x8, 8(x2) x8=1c2fffe0 x2:10000930 PA:10000938", "time": "5816", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:166"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5817, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_open", "args":{"pc": "1c002062", "instr": "lw x9, 4(x2) x9=10000180 x2:10000930 PA:10000934", "time": "5817", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5818, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_open", "args":{"pc": "1c002064", "instr": "addi x2, x2, 16 x2=10000940 x2:10000930", "time": "5818", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:166"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 5819, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_open", "args":{"pc": "1c002066", "instr": "jalr x0, x1, 0 x1:1c0017f0", "time": "5819", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:166"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017f0", "instr": "lw x1, 28(x2) x1=1c000e64 x2:10000940 PA:1000095c", "time": "5821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:462"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 5822, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017f2", "instr": "lui x15, 0x1c002000 x15=1c002000", "time": "5822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:458"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 5823, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017f6", "instr": "sw x10, 1660(x15) x10:1c002668 x15:1c002000 PA:1c00267c", "time": "5823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:458"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5841, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017fa", "instr": "addi x10, x0, 0 x10=00000000", "time": "5841", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:462"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5842, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017fc", "instr": "addi x2, x2, 32 x2=10000960 x2:10000940", "time": "5842", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:462"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 5843, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_start", "args":{"pc": "1c0017fe", "instr": "jalr x0, x1, 0 x1:1c000e64", "time": "5843", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:462"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 5845, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e64", "instr": "bne x10, x0, 6 x10:00000000", "time": "5845", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5846, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e66", "instr": "lw x8, 8(x8) x8=1c2ffff0 x8:1c2fffe0 PA:1c2fffe8", "time": "5846", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:77"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 5860, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e68", "instr": "jal x0, -22 ", "time": "5860", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:77"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 5861, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e52", "instr": "bne x8, x0, 12 x8:1c2ffff0", "time": "5861", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:74"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5864, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e5e", "instr": "lw x15, 0(x8) x15=1c001324 x8:1c2ffff0 PA:1c2ffff0", "time": "5864", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 5878, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e60", "instr": "lw x10, 4(x8) x10=00000000 x8:1c2ffff0 PA:1c2ffff4", "time": "5878", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 5892, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e62", "instr": "jalr x1, x15, 0 x1=1c000e64 x15:1c001324", "time": "5892", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5898, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001324", "instr": "addi x15, x0, 4 x15=00000004", "time": "5898", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:370"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5899, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001328", "instr": "addi x12, x0, 24 x12=00000018", "time": "5899", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:370"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 5900, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c00132a", "instr": "mul x12, x12, x15 x12=00000060 x12:00000018 x15:00000004", "time": "5900", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:370"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 5901, "dur": 17, "pid": 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x11=1c000172 x11:1c000000", "time": "8210", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:380"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8211, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001372", "instr": "addi x10, x0, 1 x10=00000001", "time": "8211", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:380"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 8212, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001374", "instr": "jal x1, -1556 x1=1c001376", "time": "8212", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:380"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 8230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:49"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8254, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d70", "instr": "p.extract x13, x11, 0, 20 x13=00000000 x11:0000016e", "time": "8254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:55"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8255, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d74", "instr": "p.insert x15, x13, 0, 31 x15=0000006f x15:0000006f x13:00000000", "time": "8255", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:55"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8256, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d78", "instr": "p.extract x13, x11, 9, 1 x13=000000b7 x11:0000016e", "time": "8256", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:56"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8257, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d7c", "instr": "p.insert x15, x13, 9, 21 x15=16e0006f x15:0000006f x13:000000b7", "time": "8257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:56"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8274, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d80", "instr": "p.extract x13, x11, 0, 11 x13=00000000 x11:0000016e", "time": "8274", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:57"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8275, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d84", "instr": "p.insert x15, x13, 0, 20 x15=16e0006f x15:16e0006f x13:00000000", "time": "8275", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:57"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8276, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d88", "instr": "p.extract x11, x11, 7, 12 x11=00000000 x11:0000016e", "time": "8276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:58"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8277, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d8c", "instr": "p.insert x15, x11, 7, 12 x15=16e0006f x15:16e0006f x11:00000000", "time": "8277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:58"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 8294, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_irq_set_handler", "args":{"pc": "1c000d90", "instr": "p.sw x15, x0(x10) x15:16e0006f x10:00000004 PA:1c000004", "time": "8294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:69"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 8312, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_irq_set_handler", "args":{"pc": "1c000d94", "instr": "jalr x0, x1, 0 x1:1c001376", "time": "8312", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:79"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 8313, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_irq_maskSet_base", "args":{"pc": "1c001376", "instr": "lui x8, 0x1b204000 x8=1b204000", "time": "8313", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:220"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8314, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_irq_maskSet_base", "args":{"pc": "1c00137a", "instr": "addi x9, x8, 20 x9=1b204014 x8:1b204000", "time": "8314", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:220"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8315, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_irq_maskSet_base", "args":{"pc": "1c00137e", "instr": "addi x15, x0, 2 x15=00000002", "time": "8315", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:220"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_irq_maskSet_base", "args":{"pc": "1c001380", "instr": "sw x15, 0(x9) x15:00000002 x9:1b204014 PA:1b204014", "time": "8332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:220"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_evt_maskSet_base", "args":{"pc": "1c001382", "instr": "sw x15, 8(x8) x15:00000002 x8:1b204000 PA:1b204008", "time": "8333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:110"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 8334, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001384", "instr": "lui x11, 0x1c000000 x11=1c000000", "time": "8334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:383"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8335, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001388", "instr": "addi x11, x11, 314 x11=1c00013a x11:1c000000", "time": "8335", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:383"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8336, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c00138c", "instr": "addi x10, x0, 4 x10=00000004", "time": "8336", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:383"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 8337, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c00138e", "instr": "jal x1, -1582 x1=1c001390", "time": "8337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:383"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 8354, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_bootaddr_get", "args":{"pc": "1c000d60", "instr": "lui x15, 0x1b200000 x15=1b200000", "time": "8354", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:63"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 8355, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_bootaddr_get", "args":{"pc": "1c000d64", "instr": "lw x14, 64(x15) x14=1c000000 x15:1b200000 PA:1b200040", "time": "8355", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:63"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 8359, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_irq_set_handler", "args":{"pc": "1c000d66", "instr": "slli x10, x10, 0x2 x10=00000010 x10:00000004", "time": "8359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:67"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8360, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d68", "instr": "addi x15, x0, 111 x15=0000006f", "time": "8360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:55"}}, +{"name": "sub", "cat": "sub", "ph": "X", "ts": 8361, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d6c", "instr": "sub x11, x11, x14 x11=0000013a x11:1c00013a x14:1c000000", "time": "8361", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:49"}}, +{"name": "sub", "cat": "sub", "ph": "X", "ts": 8362, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d6e", "instr": "sub x11, x11, x10 x11=0000012a x11:0000013a x10:00000010", "time": "8362", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:49"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8363, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d70", "instr": "p.extract x13, x11, 0, 20 x13=00000000 x11:0000012a", "time": "8363", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:55"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8364, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d74", "instr": "p.insert x15, x13, 0, 31 x15=0000006f x15:0000006f x13:00000000", "time": "8364", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:55"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8365, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d78", "instr": "p.extract x13, x11, 9, 1 x13=00000095 x11:0000012a", "time": "8365", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:56"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8366, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d7c", "instr": "p.insert x15, x13, 9, 21 x15=12a0006f x15:0000006f x13:00000095", "time": "8366", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:56"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8367, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d80", "instr": "p.extract x13, x11, 0, 11 x13=00000000 x11:0000012a", "time": "8367", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:57"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8368, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d84", "instr": "p.insert x15, x13, 0, 20 x15=12a0006f x15:12a0006f x13:00000000", "time": "8368", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:57"}}, +{"name": "p.extract", "cat": "p.extract", "ph": "X", "ts": 8369, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d88", "instr": "p.extract x11, x11, 7, 12 x11=00000000 x11:0000012a", "time": "8369", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:58"}}, +{"name": "p.insert", "cat": "p.insert", "ph": "X", "ts": 8370, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_get_itvec", "args":{"pc": "1c000d8c", "instr": "p.insert x15, x11, 7, 12 x15=12a0006f x15:12a0006f x11:00000000", "time": "8370", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:58"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 8371, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_irq_set_handler", "args":{"pc": "1c000d90", "instr": "p.sw x15, x0(x10) x15:12a0006f x10:00000010 PA:1c000010", "time": "8371", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:69"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 8389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_irq_set_handler", "args":{"pc": "1c000d94", "instr": "jalr x0, x1, 0 x1:1c001390", "time": "8389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/irq.c:79"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8390, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_irq_maskSet_base", "args":{"pc": "1c001390", "instr": "addi x15, x0, 16 x15=00000010", "time": "8390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:220"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8391, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_irq_maskSet_base", "args":{"pc": "1c001392", "instr": "sw x15, 0(x9) x15:00000010 x9:1b204014 PA:1b204014", "time": "8391", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:220"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8392, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_evt_maskSet_base", "args":{"pc": "1c001394", "instr": "sw x15, 8(x8) x15:00000010 x8:1b204000 PA:1b204008", "time": "8392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:110"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 8393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001396", "instr": "lw x1, 28(x2) x1=1c000e64 x2:10000940 PA:1000095c", "time": "8393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:387"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 8394, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c001398", "instr": "lw x8, 24(x2) x8=1c2ffff0 x2:10000940 PA:10000958", "time": "8394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:387"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 8395, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c00139a", "instr": "lw x9, 20(x2) x9=10000180 x2:10000940 PA:10000954", "time": "8395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:387"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8396, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_init", "args":{"pc": "1c00139c", "instr": "addi x10, x0, 0 x10=00000000", "time": "8396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:387"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8397, "dur": 16, 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"cat": "lw", "ph": "X", "ts": 8416, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e66", "instr": "lw x8, 8(x8) x8=00000000 x8:1c2ffff0 PA:1c2ffff8", "time": "8416", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:77"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 8430, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e68", "instr": "jal x0, -22 ", "time": "8430", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:77"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 8431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e52", "instr": "bne x8, x0, 12 x8:00000000", "time": "8431", "Origin": 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8(x2) x8=10000990 x2:10000960 PA:10000968", "time": "8434", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:81"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8435, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e5a", "instr": "addi x2, x2, 16 x2=10000970 x2:10000960", "time": "8435", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:81"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 8436, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e5c", "instr": "jalr x0, x1, 0 x1:1c000caa", "time": "8436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:81"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 8438, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init", "args":{"pc": "1c000caa", "instr": "bne x10, x0, 60 x10:00000000", "time": "8438", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:122"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8439, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_config_cluster_start", "args":{"pc": "1c000cac", "instr": "addi x15, x0, 0 x15=00000000", "time": "8439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_config.h:47"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 8456, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_config_cluster_start", "args":{"pc": "1c000cb0", "instr": "p.bclr x15, x15, 30, 1 x15=00000000 x15:00000000", "time": "8456", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_config.h:47"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 8457, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_clusters_start", "args":{"pc": "1c000cb4", "instr": "beq x15, x0, 110 x15:00000000", "time": "8457", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:248"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8476, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_clusters_start", "args":{"pc": "1c000d22", "instr": "addi x11, x0, 0 x11=00000000", "time": "8476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:282"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 8477, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_clusters_start", "args":{"pc": "1c000d24", "instr": "jal x1, -386 x1=1c000d26", "time": "8477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:282"}}, 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PA:10000964", "time": "8497", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8498, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000ba8", "instr": "sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960", "time": "8498", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8499, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000baa", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "8499", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8500, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bac", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "8500", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8501, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bae", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "8501", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 8517, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_cluster_id", "args":{"pc": "1c000bb0", "instr": "csrrs x14, x0, 0xf14 x14=00000000", "time": "8517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 8518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_cluster_id", "args":{"pc": "1c000bb4", "instr": "lui x19, 0x1000 x19=00001000", "time": "8518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8519, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bb6", "instr": "sw x1, 44(x2) x1:1c000d26 x2:10000940 PA:1000096c", "time": "8519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8520, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bb8", "instr": "sw x22, 16(x2) x22:00000000 x2:10000940 PA:10000950", "time": "8520", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "p.extractu", "cat": "p.extractu", "ph": "X", "ts": 8521, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_cluster_id", "args":{"pc": "1c000bba", "instr": "p.extractu x14, x14, 5, 5 x14=00000000 x14:00000000", "time": "8521", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 8522, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bbe", "instr": "add x8, x0, x10 x8=00000000 x10:00000000", "time": "8522", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8539, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bc0", "instr": "addi x20, x10, 2 x20=00000002 x10:00000000", "time": "8539", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8540, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bc4", "instr": "addi x9, x19, -2048 x9=00000800 x19:00001000", "time": "8540", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8541, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bc8", "instr": "addi x18, x0, 8 x18=00000008", "time": "8541", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:207"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 8542, "dur": 34, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000bcc", "instr": "beq x14, x10, 94 x14:00000000 x10:00000000", "time": "8542", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:208"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 8576, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c2a", "instr": "add x11, x0, x10 x11=00000000 x10:00000000", "time": "8576", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:220"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8577, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c2c", "instr": "addi x13, x0, 0 x13=00000000", "time": "8577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:220"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8578, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c2e", "instr": "addi x10, x0, 1 x10=00000001", "time": "8578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:220"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8594, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c30", "instr": "addi x12, x0, 0 x12=00000000", "time": "8594", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:220"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 8595, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c32", "instr": "jal x1, 1904 x1=1c000c36", "time": "8595", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:220"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8597, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000910 x2:10000940", "time": "8597", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8598, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000000 x2:10000910 PA:10000938", "time": "8598", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 8599, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000000 x11:00000000", "time": "8599", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8600, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a8", "instr": "sw x1, 44(x2) x1:1c000c36 x2:10000910 PA:1000093c", "time": "8600", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8601, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013aa", "instr": "sw x9, 36(x2) x9:00000800 x2:10000910 PA:10000934", "time": "8601", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8602, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ac", "instr": "sw x18, 32(x2) x18:00000008 x2:10000910 PA:10000930", "time": "8602", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8603, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00001000 x2:10000910 PA:1000092c", "time": "8603", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000002 x2:10000910 PA:10000928", "time": "8619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8620, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000910 PA:10000924", "time": "8620", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 8621, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "8621", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8625, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "8625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 8626, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000000 x11:00000000 x20:00000018", "time": "8626", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 8643, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "8643", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 8644, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "8644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 8658, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "8658", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 8659, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff50 x15:1c2fff50 x20:00000000", "time": "8659", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 8660, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000000 x15:1c2fff50 PA:1c2fff50", "time": "8660", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 8675, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000001", "time": "8675", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8676, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ce", "instr": "addi x14, x14, 1 x14=00000001 x14:00000000", "time": "8676", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187 (discriminator 1)"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8679, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000001 x15:1c2fff50 PA:1c2fff50", "time": "8679", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 8697, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000001 x15:1c2fff50 PA:1c2fff50", "time": "8697", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 8712, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000001", "time": "8712", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 8731, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f6", "instr": "p.bneimm x9, -26 x9:00000001", "time": "8731", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8732, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013fa", "instr": "addi x19, x0, 8 x19=00000008", "time": "8732", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 8733, "dur": 34, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c0013fe", "instr": "beq x8, x0, 94 x8:00000000", "time": "8733", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:68"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8767, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145c", "instr": "addi x10, x0, 0 x10=00000000", "time": "8767", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:139"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 8768, "dur": 33, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145e", "instr": "jal x1, -392 x1=1c001460", "time": "8768", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:139"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8801, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012d6", "instr": "addi x2, x2, -16 x2=10000900 x2:10000910", "time": "8801", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8802, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012d8", "instr": "sw x8, 8(x2) x8:00000000 x2:10000900 PA:10000908", "time": "8802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8803, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012da", "instr": "sw x9, 4(x2) x9:00000001 x2:10000900 PA:10000904", "time": "8803", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8804, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012dc", "instr": "addi x8, x10, 64 x8=00000040 x10:00000000", "time": "8804", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 8821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012e0", "instr": "add x9, x0, x10 x9=00000000 x10:00000000", "time": "8821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 8822, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012e2", "instr": "lui x10, 0x1b000000 x10=1b000000", "time": "8822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8823, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012e6", "instr": "addi x10, x10, 8 x10=1b000008 x10:1b000000", "time": "8823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 8824, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012ea", "instr": "slli x8, x8, 0x16 x8=10000000 x8:00000040", "time": "8824", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 8825, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012ec", "instr": "p.bclr x10, x10, 19, 12 x10=00000008 x10:1b000008", "time": "8825", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 8842, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f0", "instr": "add x10, x10, x8 x10=10000008 x10:00000008 x8:10000000", "time": "8842", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8843, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f2", "instr": "addi x12, x0, 64 x12=00000040", "time": "8843", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 8844, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f6", "instr": "addi x11, x0, 0 x11=00000000", "time": "8844", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 8845, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": 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"tid": "eu_evt_trig_cluster_addr", "args":{"pc": "1c00130c", "instr": "lui x14, 0x201000 x14=00201000", "time": "9271", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:265"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9288, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_evt_trig_cluster_addr", "args":{"pc": "1c001310", "instr": "addi x14, x14, -508 x14=00200e04 x14:00201000", "time": "9288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:265"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9289, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_evt_trig_cluster_addr", "args":{"pc": "1c001314", "instr": "add x8, x8, x14 x8=10200e04 x8:10000000 x14:00200e04", "time": "9289", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:265"}}, +{"name": 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"__rt_init_cluster_data", "args":{"pc": "1c001322", "instr": "jalr x0, x1, 0 x1:1c001460", "time": "9329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:62"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 9331, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c001460", "instr": "lui x15, 0x10201000 x15=10201000", "time": "9331", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c001464", "instr": "addi x14, x0, -1 x14=ffffffff", "time": "9332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9333, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c001466", "instr": "sw x14, 1024(x15) x14:ffffffff x15:10201000 PA:10201400", "time": "9333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 9338, "dur": 13, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00146a", "instr": "lui x15, 0x1c000000 x15=1c000000", "time": "9338", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:150"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00146e", "instr": "addi x15, x15, 128 x15=1c000080 x15:1c000000", "time": "9351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:150"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 9352, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001472", "instr": "lui x14, 0x6c80000 x14=06c80000", "time": "9352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:150"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 9353, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001476", "instr": "p.bclr x15, x15, 7, 0 x15=1c000000 x15:1c000080", "time": "9353", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:150"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9354, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147a", "instr": "addi x14, x14, 16 x14=06c80010 x14:06c80000", "time": "9354", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:150"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9355, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000001 x19:00000008", "time": "9355", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148a", "instr": "add x13, x9, x14 x13=06c80011 x9:00000001 x14:06c80010", "time": "9373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9374, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148e", "instr": "slli x13, x13, 0x2 x13=1b200044 x13:06c80011", "time": "9374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9391, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set", "args":{"pc": "1c001490", "instr": "sw x15, 0(x13) x15:1c000000 x13:1b200044 PA:1b200044", "time": "9391", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:55"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9395, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001492", "instr": "addi x9, x9, 1 x9=00000002 x9:00000001", "time": "9395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9396, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001494", "instr": "jal x0, -24 ", "time": "9396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9398, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000002 x19:00000008", "time": "9398", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9401, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148a", "instr": "add x13, x9, x14 x13=06c80012 x9:00000002 x14:06c80010", "time": "9401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148e", "instr": "slli x13, x13, 0x2 x13=1b200048 x13:06c80012", "time": "9402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9403, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set", "args":{"pc": "1c001490", "instr": "sw x15, 0(x13) x15:1c000000 x13:1b200048 PA:1b200048", "time": "9403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:55"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9407, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001492", "instr": "addi x9, x9, 1 x9=00000003 x9:00000002", "time": "9407", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9408, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001494", "instr": "jal x0, -24 ", "time": "9408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9410, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000003 x19:00000008", "time": "9410", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9413, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148a", "instr": "add x13, x9, x14 x13=06c80013 x9:00000003 x14:06c80010", "time": "9413", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9414, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148e", "instr": "slli x13, x13, 0x2 x13=1b20004c x13:06c80013", "time": "9414", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9415, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set", "args":{"pc": "1c001490", "instr": "sw x15, 0(x13) x15:1c000000 x13:1b20004c PA:1b20004c", "time": "9415", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:55"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9419, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001492", "instr": "addi x9, x9, 1 x9=00000004 x9:00000003", "time": "9419", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9420, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001494", "instr": "jal x0, -24 ", "time": "9420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9422, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000004 x19:00000008", "time": "9422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9425, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148a", "instr": "add x13, x9, x14 x13=06c80014 x9:00000004 x14:06c80010", "time": "9425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9426, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148e", "instr": "slli x13, x13, 0x2 x13=1b200050 x13:06c80014", "time": "9426", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9427, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set", "args":{"pc": "1c001490", "instr": "sw x15, 0(x13) x15:1c000000 x13:1b200050 PA:1b200050", "time": "9427", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:55"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001492", "instr": "addi x9, x9, 1 x9=00000005 x9:00000004", "time": "9431", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9432, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001494", "instr": "jal x0, -24 ", "time": "9432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9434, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000005 x19:00000008", "time": "9434", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9437, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148a", "instr": "add x13, x9, x14 x13=06c80015 x9:00000005 x14:06c80010", "time": "9437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9438, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148e", "instr": "slli x13, x13, 0x2 x13=1b200054 x13:06c80015", "time": "9438", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9439, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set", "args":{"pc": "1c001490", "instr": "sw x15, 0(x13) x15:1c000000 x13:1b200054 PA:1b200054", "time": "9439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:55"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9443, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001492", "instr": "addi x9, x9, 1 x9=00000006 x9:00000005", "time": "9443", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9444, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001494", "instr": "jal x0, -24 ", "time": "9444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9446, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000006 x19:00000008", "time": "9446", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9449, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148a", "instr": "add x13, x9, x14 x13=06c80016 x9:00000006 x14:06c80010", "time": "9449", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9450, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148e", "instr": "slli x13, x13, 0x2 x13=1b200058 x13:06c80016", "time": "9450", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9451, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set", "args":{"pc": "1c001490", "instr": "sw x15, 0(x13) x15:1c000000 x13:1b200058 PA:1b200058", "time": "9451", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:55"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9455, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001492", "instr": "addi x9, x9, 1 x9=00000007 x9:00000006", "time": "9455", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9456, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001494", "instr": "jal x0, -24 ", "time": "9456", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9458, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000007 x19:00000008", "time": "9458", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148a", "instr": "add x13, x9, x14 x13=06c80017 x9:00000007 x14:06c80010", "time": "9461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00148e", "instr": "slli x13, x13, 0x2 x13=1b20005c x13:06c80017", "time": "9462", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9463, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set", "args":{"pc": "1c001490", "instr": "sw x15, 0(x13) x15:1c000000 x13:1b20005c PA:1b20005c", "time": "9463", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:55"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9467, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001492", "instr": "addi x9, x9, 1 x9=00000008 x9:00000007", "time": "9467", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9468, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001494", "instr": "jal x0, -24 ", "time": "9468", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 9470, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00147c", "instr": "blt x9, x19, 14 x9:00000008 x19:00000008", "time": "9470", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:149"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 9471, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001480", "instr": "lui x15, 0x10200000 x15=10200000", "time": "9471", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9472, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001484", "instr": "addi x14, x0, -1 x14=ffffffff", "time": "9472", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 9473, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001486", "instr": "sw x14, 8(x15) x14:ffffffff x15:10200000 PA:10200008", "time": "9473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9477, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001488", "instr": "jal x0, -172 ", "time": "9477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 9478, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c0013dc", "instr": "csrrw x0, x18, 0x300 x18:00001808", "time": "9478", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9493, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e0", "instr": "lw x1, 44(x2) x1=1c000c36 x2:10000910 PA:1000093c", "time": "9493", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9494, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e2", "instr": "lw x8, 40(x2) x8=00000000 x2:10000910 PA:10000938", "time": "9494", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9495, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e4", "instr": "lw x9, 36(x2) x9=00000800 x2:10000910 PA:10000934", "time": "9495", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9496, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e6", "instr": "lw x18, 32(x2) x18=00000008 x2:10000910 PA:10000930", "time": "9496", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9497, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e8", "instr": "lw x19, 28(x2) x19=00001000 x2:10000910 PA:1000092c", "time": "9497", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9498, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ea", "instr": "lw x20, 24(x2) x20=00000002 x2:10000910 PA:10000928", "time": "9498", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9499, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ec", "instr": "lw x21, 20(x2) x21=00000000 x2:10000910 PA:10000924", "time": "9499", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9500, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ee", "instr": "addi x2, x2, 48 x2=10000940 x2:10000910", "time": "9500", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 9501, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f0", "instr": "jalr x0, x1, 0 x1:1c000c36", "time": "9501", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9503, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c36", "instr": "addi x11, x18, -1 x11=00000007 x18:00000008", "time": "9503", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:221"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 9504, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c3a", "instr": "mul x11, x11, x9 x11=00003800 x11:00000007 x9:00000800", "time": "9504", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:221"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9505, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c3e", "instr": "add x10, x0, x20 x10=00000002 x20:00000002", "time": "9505", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:221"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9522, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_check_cluster_start", "args":{"pc": "1c000c40", "instr": "jal x1, 1424 x1=1c000c42", "time": "9522", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:221"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9524, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc", "args":{"pc": "1c0011d0", "instr": "addi x15, x0, 1 x15=00000001", "time": "9524", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:218"}}, +{"name": "bgeu", "cat": "bgeu", "ph": "X", "ts": 9525, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc", "args":{"pc": "1c0011d2", "instr": "bgeu x15, x10, 20 x15:00000001 x10:00000002", "time": "9525", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:218"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 9526, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc_l1", "args":{"pc": "1c0011d6", "instr": "lui x15, 0x1c002000 x15=1c002000", "time": "9526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_alloc.h:435"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9527, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc_l1", "args":{"pc": "1c0011da", "instr": "lw x15, 1692(x15) x15=10000990 x15:1c002000 PA:1c00269c", "time": "9527", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_alloc.h:435"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9541, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc", "args":{"pc": "1c0011de", "instr": "addi x10, x10, -2 x10=00000000 x10:00000002", "time": "9541", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:218"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 9542, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc_l1", "args":{"pc": "1c0011e0", "instr": "slli x10, x10, 0x2 x10=00000000 x10:00000000", "time": "9542", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_alloc.h:435"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9543, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc", "args":{"pc": "1c0011e2", "instr": "add x10, x10, x15 x10=10000990 x10:00000000 x15:10000990", "time": "9543", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:235"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 9544, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_alloc", "args":{"pc": "1c0011e4", "instr": "jal x0, -146 ", "time": "9544", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:235"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 9546, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc", "args":{"pc": "1c001152", "instr": "lw x15, 0(x10) x15=100009a0 x10:10000990 PA:10000990", "time": "9546", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:119"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9547, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc", "args":{"pc": "1c001154", "instr": "addi x11, x11, 7 x11=00003807 x11:00003800", "time": "9547", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:121"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 9548, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc", "args":{"pc": "1c001156", "instr": "p.bclr x11, x11, 2, 0 x11=00003800 x11:00003807", "time": "9548", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:121"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 9549, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc", "args":{"pc": "1c00115a", "instr": "addi x13, x0, 0 x13=00000000", "time": "9549", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:119"}}, 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"args":{"pc": "1c000fb6", "instr": "csrrw x0, x13, 0x300 x13:00001808", "time": "10184", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10188, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_get", "args":{"pc": "1c000fba", "instr": "add x10, x0, x15 x10=100fc720 x15:100fc720", "time": "10188", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:115"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 10189, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_get", "args":{"pc": "1c000fbc", "instr": "jalr x0, x1, 0 x1:1c000a6a", "time": "10189", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:115"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10207, "dur": 1, "pid": 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1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a76", "instr": "addi x10, x0, 1 x10=00000001", "time": "10228", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 10229, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a78", "instr": "jal x1, 2346 x1=1c000a7c", "time": "10229", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10231, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000940 x2:10000970", "time": "10231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000001 x2:10000940 PA:10000968", "time": "10232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000000 x11:00000000", "time": "10233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a8", "instr": "sw x1, 44(x2) x1:1c000a7c x2:10000940 PA:1000096c", "time": "10234", "Origin": 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"args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "10237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10253, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "10253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10254, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "10254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 10255, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "10255", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10259, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "10259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 10260, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000000 x11:00000000 x20:00000018", "time": "10260", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 10277, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "10277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10278, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "10278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10292, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "10292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10293, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff50 x15:1c2fff50 x20:00000000", "time": "10293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10294, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000001 x15:1c2fff50 PA:1c2fff50", "time": "10294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 10308, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000001", "time": "10308", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10309, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ce", "instr": "addi x14, x14, 1 x14=00000002 x14:00000001", "time": "10309", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187 (discriminator 1)"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10310, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000002 x15:1c2fff50 PA:1c2fff50", "time": "10310", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10328, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000002 x15:1c2fff50 PA:1c2fff50", "time": "10328", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 10343, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000002", "time": "10343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 10346, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f6", "instr": "p.bneimm x9, -26 x9:00000002", "time": "10346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 10349, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c0013dc", "instr": "csrrw x0, x18, 0x300 x18:00001808", "time": "10349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10353, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e0", "instr": "lw x1, 44(x2) x1=1c000a7c x2:10000940 PA:1000096c", "time": "10353", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10354, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e2", "instr": "lw x8, 40(x2) x8=00000001 x2:10000940 PA:10000968", "time": "10354", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10355, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e4", "instr": "lw x9, 36(x2) x9=100fc720 x2:10000940 PA:10000964", "time": "10355", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10356, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e6", "instr": "lw x18, 32(x2) x18=00000000 x2:10000940 PA:10000960", "time": "10356", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10357, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e8", "instr": "lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c", "time": "10357", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10358, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ea", "instr": "lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958", "time": "10358", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10359, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ec", "instr": "lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954", "time": "10359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10360, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ee", "instr": "addi x2, x2, 48 x2=10000970 x2:10000940", "time": "10360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 10361, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f0", "instr": "jalr x0, x1, 0 x1:1c000a7c", "time": "10361", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 10363, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a7c", "instr": "p.bneimm x8, -14 x8:00000001", "time": "10363", "Origin": "/scratch/digirols/pulp_api_example/main.c:67 (discriminator 3)"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10381, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a6e", "instr": "add x11, x0, x8 x11=00000001 x8:00000001", "time": "10381", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10382, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a70", "instr": "add x13, x0, x9 x13=100fc720 x9:100fc720", "time": "10382", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10383, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a72", "instr": "addi x8, x8, 1 x8=00000002 x8:00000001", "time": "10383", "Origin": "/scratch/digirols/pulp_api_example/main.c:67 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10384, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a74", "instr": "addi x12, x0, 0 x12=00000000", "time": "10384", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10385, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a76", "instr": "addi x10, x0, 1 x10=00000001", "time": "10385", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 10386, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a78", "instr": "jal x1, 2346 x1=1c000a7c", "time": "10386", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10388, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000940 x2:10000970", "time": "10388", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000002 x2:10000940 PA:10000968", "time": "10389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10390, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000001 x11:00000001", "time": "10390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10391, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a8", "instr": "sw x1, 44(x2) x1:1c000a7c x2:10000940 PA:1000096c", "time": "10391", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10392, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013aa", "instr": "sw x9, 36(x2) x9:100fc720 x2:10000940 PA:10000964", "time": "10392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ac", "instr": "sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960", "time": "10393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10394, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "10394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10395, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "10395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10396, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "10396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 10397, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "10397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10401, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "10401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 10402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000018 x11:00000001 x20:00000018", "time": "10402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 10403, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "10403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10404, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "10404", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10418, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "10418", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10419, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff68 x15:1c2fff50 x20:00000018", "time": "10419", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10420, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000000 x15:1c2fff68 PA:1c2fff68", "time": "10420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 10434, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000001", "time": "10434", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10435, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ce", "instr": "addi x14, x14, 1 x14=00000001 x14:00000000", "time": "10435", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187 (discriminator 1)"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10436, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000001 x15:1c2fff68 PA:1c2fff68", "time": "10436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 10454, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000001 x15:1c2fff68 PA:1c2fff68", "time": "10454", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 10469, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000001", "time": "10469", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 10472, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f6", "instr": "p.bneimm x9, -26 x9:00000001", "time": "10472", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10473, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013fa", "instr": "addi x19, x0, 8 x19=00000008", "time": "10473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 10474, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c0013fe", "instr": "beq x8, x0, 94 x8:00000001", "time": "10474", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:68"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10475, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001400", "instr": "add x10, x0, x8 x10=00000001 x8:00000001", "time": "10475", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10476, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001402", "instr": "sw x13, 12(x2) x13:100fc720 x2:10000940 PA:1000094c", "time": "10476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 10477, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001404", "instr": "jal x1, -302 x1=1c001406", "time": "10477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10479, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012d6", "instr": "addi x2, x2, -16 x2=10000930 x2:10000940", "time": "10479", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 10480, "dur": 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"/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 10483, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012e0", "instr": "add x9, x0, x10 x9=00000001 x10:00000001", "time": "10483", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 10484, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012e2", "instr": "lui x10, 0x1b000000 x10=1b000000", "time": "10484", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 10485, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": 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"12216", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12217, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c00141e", "instr": "addi x14, x0, -1 x14=ffffffff", "time": "12217", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12234, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001420", "instr": "sw x0, 4(x20) x20:1c2fff68 PA:1c2fff6c", "time": "12234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:112"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12252, "dur": 26, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c001424", "instr": "p.sw x14, x0(x8) x14:ffffffff x8:10400000 PA:10601400", "time": "12252", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12278, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c001428", "instr": "lw x13, 12(x2) x13=100fc720 x2:10000940 PA:1000094c", "time": "12278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12279, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c00142a", "instr": "lui x15, 0x200000 x15=00200000", "time": "12279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12296, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00142e", "instr": "lui x14, 0x1c000000 x14=1c000000", "time": "12296", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:123"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12297, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001432", "instr": "addi x15, x15, 64 x15=00200040 x15:00200000", "time": "12297", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:123"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12298, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001436", "instr": "addi x14, x14, 128 x14=1c000080 x14:1c000000", "time": "12298", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:123"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12299, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00143a", "instr": "add x15, x15, x8 x15=10600040 x15:00200040 x8:10400000", "time": "12299", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:123"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12300, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00143c", "instr": "addi x12, x0, 0 x12=00000000", "time": "12300", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 12317, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00143e", "instr": "p.bclr x14, x14, 7, 0 x14=1c000000 x14:1c000080", "time": "12317", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:123"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12318, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000000 x19:00000008", "time": "12318", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12321, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10600044 x14:1c000000 x15:10600040 PA:10600040", "time": "12321", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12344, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000001 x12:00000000", "time": "12344", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12345, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12345", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12347, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000001 x19:00000008", "time": "12347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12350, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10600048 x14:1c000000 x15:10600044 PA:10600044", "time": "12350", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000002 x12:00000001", "time": "12373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12374, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12376, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000002 x19:00000008", "time": "12376", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12379, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=1060004c x14:1c000000 x15:10600048 PA:10600048", "time": "12379", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000003 x12:00000002", "time": "12402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12403, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12405, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000003 x19:00000008", "time": "12405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12408, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10600050 x14:1c000000 x15:1060004c PA:1060004c", "time": "12408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000004 x12:00000003", "time": "12431", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12432, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12434, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000004 x19:00000008", "time": "12434", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12437, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10600054 x14:1c000000 x15:10600050 PA:10600050", "time": "12437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12460, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000005 x12:00000004", "time": "12460", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12461, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12463, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000005 x19:00000008", "time": "12463", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12466, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10600058 x14:1c000000 x15:10600054 PA:10600054", "time": "12466", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12489, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000006 x12:00000005", "time": "12489", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12490, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12490", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12492, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000006 x19:00000008", "time": "12492", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12495, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=1060005c x14:1c000000 x15:10600058 PA:10600058", "time": "12495", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000007 x12:00000006", "time": "12518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12519, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12521, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000007 x19:00000008", "time": "12521", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12524, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10600060 x14:1c000000 x15:1060005c PA:1060005c", "time": "12524", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12547, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000008 x12:00000007", "time": "12547", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12548, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "12548", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 12550, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000008 x19:00000008", "time": "12550", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12551, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001446", "instr": "lui x15, 0x200000 x15=00200000", "time": "12551", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12552, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144a", "instr": "addi x15, x15, 8 x15=00200008 x15:00200000", "time": "12552", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12553, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144c", "instr": "addi x14, x0, -1 x14=ffffffff", "time": "12553", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 12554, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144e", "instr": "p.sw x14, x0(x8) x14:ffffffff x8:10400000 PA:10600008", "time": "12554", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12577, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001452", "instr": "jal x0, -124 ", "time": "12577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 12578, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013d6", "instr": "beq x13, x0, 6 x13:100fc720", "time": "12578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12579, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013d8", "instr": "add x10, x0, x13 x10=100fc720 x13:100fc720", "time": "12579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12580, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013da", "instr": "jal x1, -996 x1=1c0013dc", "time": "12580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:131"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 12601, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c000ffc", "instr": "csrrci x8, 0x00000008, 0x300 x8=00001800", "time": "12601", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12618, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c001000", "instr": "lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c", "time": "12618", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:133"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001002", "instr": "sw x0, 8(x10) x10:100fc720 PA:100fc728", "time": "12619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:388"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12620, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001006", "instr": "lw x14, 0(x15) x14=00000000 x15:1000013c PA:1000013c", "time": "12620", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:389"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 12622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001008", "instr": "bne x14, x0, 28 x14:00000000", "time": "12622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:389"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12623, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c00100a", "instr": "sw x10, 0(x15) x10:100fc720 x15:1000013c PA:1000013c", "time": "12623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:390"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12624, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c00100c", "instr": "sw x10, 4(x15) x10:100fc720 x15:1000013c PA:10000140", "time": "12624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:394"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12625, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_wakeup_thread", "args":{"pc": "1c00100e", "instr": "lw x10, 12(x15) x10=00000000 x15:1000013c PA:10000148", "time": "12625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:399"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 12641, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_wakeup_thread", "args":{"pc": "1c001010", "instr": "beq x10, x0, 8 x10:00000000", "time": "12641", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:400"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 12644, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c001018", "instr": "csrrw x0, x8, 0x300 x8:00001800", "time": "12644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12648, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c00101c", "instr": "lw x1, 12(x2) x1=1c0013dc x2:10000930 PA:1000093c", "time": "12648", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:135"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12649, "dur": 13, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c00101e", "instr": "lw x8, 8(x2) x8=10400000 x2:10000930 PA:10000938", "time": "12649", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:135"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12662, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c001020", "instr": "addi x2, x2, 16 x2=10000940 x2:10000930", "time": "12662", "Origin": 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"tid": "main", "args":{"pc": "1c000a70", "instr": "add x13, x0, x9 x13=100fc720 x9:100fc720", "time": "12683", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12684, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a72", "instr": "addi x8, x8, 1 x8=00000003 x8:00000002", "time": "12684", "Origin": "/scratch/digirols/pulp_api_example/main.c:67 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12685, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a74", "instr": "addi x12, x0, 0 x12=00000000", "time": "12685", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12686, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a76", "instr": "addi x10, x0, 1 x10=00000001", "time": "12686", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12687, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a78", "instr": "jal x1, 2346 x1=1c000a7c", "time": "12687", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12689, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000940 x2:10000970", "time": "12689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12690, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000003 x2:10000940 PA:10000968", "time": "12690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12691, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000002 x11:00000002", "time": "12691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12692, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a8", "instr": "sw x1, 44(x2) x1:1c000a7c x2:10000940 PA:1000096c", "time": "12692", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12693, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013aa", "instr": "sw x9, 36(x2) x9:100fc720 x2:10000940 PA:10000964", "time": "12693", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12694, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ac", "instr": "sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960", "time": "12694", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12695, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "12695", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12696, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "12696", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12697, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "12697", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 12698, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "12698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12702, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "12702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 12703, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000030 x11:00000002 x20:00000018", "time": "12703", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12704, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "12704", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12705, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "12705", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "12720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff80 x15:1c2fff50 x20:00000030", "time": "12721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12722, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000000 x15:1c2fff80 PA:1c2fff80", "time": "12722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 12737, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000001", "time": "12737", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12738, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ce", "instr": "addi x14, x14, 1 x14=00000001 x14:00000000", "time": "12738", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187 (discriminator 1)"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12739, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000001 x15:1c2fff80 PA:1c2fff80", "time": "12739", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 12757, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000001 x15:1c2fff80 PA:1c2fff80", "time": "12757", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 12772, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000001", "time": "12772", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 12775, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f6", "instr": "p.bneimm x9, -26 x9:00000001", "time": "12775", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12776, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013fa", "instr": "addi x19, x0, 8 x19=00000008", "time": "12776", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 12777, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c0013fe", "instr": "beq x8, x0, 94 x8:00000002", "time": "12777", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:68"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12778, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001400", "instr": "add x10, x0, x8 x10=00000002 x8:00000002", "time": "12778", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12779, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001402", "instr": "sw x13, 12(x2) x13:100fc720 x2:10000940 PA:1000094c", "time": "12779", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12780, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001404", "instr": "jal x1, -302 x1=1c001406", "time": "12780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12782, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012d6", "instr": "addi x2, x2, -16 x2=10000930 x2:10000940", "time": "12782", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12783, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012d8", "instr": "sw x8, 8(x2) x8:00000002 x2:10000930 PA:10000938", "time": "12783", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12784, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012da", "instr": "sw x9, 4(x2) x9:00000001 x2:10000930 PA:10000934", "time": "12784", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12785, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012dc", "instr": "addi x8, x10, 64 x8=00000042 x10:00000002", "time": "12785", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12786, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012e0", "instr": "add x9, x0, x10 x9=00000002 x10:00000002", "time": "12786", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12787, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012e2", "instr": "lui x10, 0x1b000000 x10=1b000000", "time": "12787", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12788, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012e6", "instr": "addi x10, x10, 8 x10=1b000008 x10:1b000000", "time": "12788", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 12789, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012ea", "instr": "slli x8, x8, 0x16 x8=10800000 x8:00000042", "time": "12789", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 12790, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012ec", "instr": "p.bclr x10, x10, 19, 12 x10=00000008 x10:1b000008", "time": "12790", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 12791, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f0", "instr": "add x10, x10, x8 x10=10800008 x10:00000008 x8:10800000", "time": "12791", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12792, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f2", "instr": "addi x12, x0, 64 x12=00000040", "time": "12792", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12793, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f6", "instr": "addi x11, x0, 0 x11=00000000", "time": "12793", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12794, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f8", "instr": "sw x1, 12(x2) x1:1c001406 x2:10000930 PA:1000093c", "time": "12794", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc_init", "args":{"pc": "1c001136", "instr": "p.bclr x15, x15, 2, 0 x15=10800990 x15:10800997", "time": "14429", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:106"}}, +{"name": "sub", "cat": "sub", "ph": "X", "ts": 14430, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc_init", "args":{"pc": "1c00113a", "instr": "sub x11, x15, x11 x11=00000000 x15:10800990 x11:10800990", "time": "14430", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:108"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc_init", "args":{"pc": "1c00113e", "instr": "sw x15, 0(x10) x15:10800990 x10:10000998 PA:10000998", "time": "14431", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_user_alloc_init", "args":{"pc": "1c001150", "instr": "jalr x0, x1, 0 x1:1c00140a", "time": "14475", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/alloc.c:113"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14476, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00140a", "instr": "lw x15, 1704(x21) x15=1c2fff50 x21:1c002000 PA:1c0026a8", "time": "14476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:112"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14490, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c00140e", "instr": "addi x8, x8, 64 x8=00000042 x8:00000002", "time": "14490", "Origin": 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"args":{"pc": "1c00143a", "instr": "add x15, x15, x8 x15=10a00040 x15:00200040 x8:10800000", "time": "14545", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:123"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14546, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00143c", "instr": "addi x12, x0, 0 x12=00000000", "time": "14546", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 14547, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00143e", "instr": "p.bclr x14, x14, 7, 0 x14=1c000000 x14:1c000080", "time": "14547", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:123"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14548, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000000 x19:00000008", "time": "14548", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14551, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a00044 x14:1c000000 x15:10a00040 PA:10a00040", "time": "14551", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14574, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000001 x12:00000000", "time": "14574", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14575, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14575", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14577, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000001 x19:00000008", "time": "14577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14580, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a00048 x14:1c000000 x15:10a00044 PA:10a00044", "time": "14580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14603, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000002 x12:00000001", "time": "14603", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14604, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14604", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14606, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000002 x19:00000008", "time": "14606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14609, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a0004c x14:1c000000 x15:10a00048 PA:10a00048", "time": "14609", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14632, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000003 x12:00000002", "time": "14632", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14633, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14633", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14635, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000003 x19:00000008", "time": "14635", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14638, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a00050 x14:1c000000 x15:10a0004c PA:10a0004c", "time": "14638", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14661, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000004 x12:00000003", "time": "14661", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14662, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14662", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14664, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000004 x19:00000008", "time": "14664", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14667, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a00054 x14:1c000000 x15:10a00050 PA:10a00050", "time": "14667", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14690, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000005 x12:00000004", "time": "14690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14691, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14693, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000005 x19:00000008", "time": "14693", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14696, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a00058 x14:1c000000 x15:10a00054 PA:10a00054", "time": "14696", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000006 x12:00000005", "time": "14719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14720, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14722, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000006 x19:00000008", "time": "14722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14725, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a0005c x14:1c000000 x15:10a00058 PA:10a00058", "time": "14725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14748, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000007 x12:00000006", "time": "14748", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14749, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14749", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14751, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000007 x19:00000008", "time": "14751", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14754, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10a00060 x14:1c000000 x15:10a0005c PA:10a0005c", "time": "14754", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14777, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000008 x12:00000007", "time": "14777", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14778, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "14778", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 14780, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000008 x19:00000008", "time": "14780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14781, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001446", "instr": "lui x15, 0x200000 x15=00200000", "time": "14781", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14782, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144a", "instr": "addi x15, x15, 8 x15=00200008 x15:00200000", "time": "14782", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14783, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144c", "instr": "addi x14, x0, -1 x14=ffffffff", "time": "14783", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 14784, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144e", "instr": "p.sw x14, x0(x8) x14:ffffffff x8:10800000 PA:10a00008", "time": "14784", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14807, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001452", "instr": "jal x0, -124 ", "time": "14807", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14808, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013d6", "instr": "beq x13, x0, 6 x13:100fc720", "time": "14808", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14809, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013d8", "instr": "add x10, x0, x13 x10=100fc720 x13:100fc720", "time": "14809", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14810, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013da", "instr": "jal x1, -996 x1=1c0013dc", "time": "14810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14812, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c000ff6", "instr": "addi x2, x2, -16 x2=10000930 x2:10000940", "time": "14812", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:131"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14813, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c000ff8", "instr": "sw x1, 12(x2) x1:1c0013dc x2:10000930 PA:1000093c", "time": "14813", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:131"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14814, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c000ffa", "instr": "sw x8, 8(x2) x8:10800000 x2:10000930 PA:10000938", "time": "14814", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:131"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 14815, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c000ffc", "instr": "csrrci x8, 0x00000008, 0x300 x8=00001800", "time": "14815", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14819, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c001000", "instr": "lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c", "time": "14819", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:133"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14820, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001002", "instr": "sw x0, 8(x10) x10:100fc720 PA:100fc728", "time": "14820", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:388"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14821, 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:392"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14828, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001026", "instr": "sw x10, 8(x14) x10:100fc720 x14:100fc720 PA:100fc728", "time": "14828", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:392"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14829, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001028", "instr": "jal x0, -28 ", "time": "14829", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:392"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14831, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c00100c", "instr": "sw x10, 4(x15) x10:100fc720 x15:1000013c PA:10000140", "time": "14831", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:394"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14832, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_wakeup_thread", "args":{"pc": "1c00100e", "instr": "lw x10, 12(x15) x10=00000000 x15:1000013c PA:10000148", "time": "14832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:399"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14834, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_wakeup_thread", "args":{"pc": "1c001010", "instr": "beq x10, x0, 8 x10:00000000", "time": "14834", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:400"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 14837, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c001018", "instr": "csrrw x0, x8, 0x300 x8:00001800", "time": "14837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14841, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c00101c", "instr": "lw x1, 12(x2) x1=1c0013dc x2:10000930 PA:1000093c", "time": "14841", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:135"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14842, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c00101e", "instr": "lw x8, 8(x2) x8=10800000 x2:10000930 PA:10000938", "time": "14842", "Origin": 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14866, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a74", "instr": "addi x12, x0, 0 x12=00000000", "time": "14866", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14867, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a76", "instr": "addi x10, x0, 1 x10=00000001", "time": "14867", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14868, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a78", "instr": "jal x1, 2346 x1=1c000a7c", "time": "14868", "Origin": "/scratch/digirols/pulp_api_example/main.c:68 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14870, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000940 x2:10000970", "time": "14870", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14871, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000004 x2:10000940 PA:10000968", "time": "14871", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14872, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000003 x11:00000003", "time": "14872", "Origin": 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"args":{"pc": "1c0013ac", "instr": "sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960", "time": "14875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14876, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "14876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14877, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "14877", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14878, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "14878", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 14879, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "14879", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14883, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "14883", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 14884, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000048 x11:00000003 x20:00000018", "time": "14884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14885, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "14885", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14886, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "14886", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14900, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "14900", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14901, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff98 x15:1c2fff50 x20:00000048", "time": "14901", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14902, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000000 x15:1c2fff98 PA:1c2fff98", "time": "14902", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14916, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000001", "time": "14916", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14917, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ce", "instr": "addi x14, x14, 1 x14=00000001 x14:00000000", "time": "14917", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187 (discriminator 1)"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14918, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000001 x15:1c2fff98 PA:1c2fff98", "time": "14918", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 14936, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000001 x15:1c2fff98 PA:1c2fff98", "time": "14936", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 14953, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000001", "time": "14953", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 14956, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f6", "instr": "p.bneimm x9, -26 x9:00000001", "time": "14956", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14957, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013fa", "instr": "addi x19, x0, 8 x19=00000008", "time": "14957", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:191"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14958, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c0013fe", "instr": "beq x8, x0, 94 x8:00000003", "time": "14958", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:68"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14959, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001400", "instr": "add x10, x0, x8 x10=00000003 x8:00000003", "time": "14959", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14960, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001402", "instr": "sw x13, 12(x2) x13:100fc720 x2:10000940 PA:1000094c", "time": "14960", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14961, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001404", "instr": "jal x1, -302 x1=1c001406", "time": "14961", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:106"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14963, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012d6", "instr": "addi x2, x2, -16 x2=10000930 x2:10000940", "time": "14963", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14964, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012d8", "instr": "sw x8, 8(x2) x8:00000003 x2:10000930 PA:10000938", "time": "14964", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012da", "instr": "sw x9, 4(x2) x9:00000001 x2:10000930 PA:10000934", "time": "14965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14966, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012dc", "instr": "addi x8, x10, 64 x8=00000043 x10:00000003", "time": "14966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14967, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012e0", "instr": "add x9, x0, x10 x9=00000003 x10:00000003", "time": "14967", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14968, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012e2", "instr": "lui x10, 0x1b000000 x10=1b000000", "time": "14968", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14969, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012e6", "instr": "addi x10, x10, 8 x10=1b000008 x10:1b000000", "time": "14969", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 14970, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012ea", "instr": "slli x8, x8, 0x16 x8=10c00000 x8:00000043", "time": "14970", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 14971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0012ec", "instr": "p.bclr x10, x10, 19, 12 x10=00000008 x10:1b000008", "time": "14971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f0", "instr": "add x10, x10, x8 x10=10c00008 x10:00000008 x8:10c00000", "time": "14972", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f2", "instr": "addi x12, x0, 64 x12=00000040", "time": "14973", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f6", "instr": "addi x11, x0, 0 x11=00000000", "time": "14974", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012f8", "instr": "sw x1, 12(x2) x1:1c001406 x2:10000930 PA:1000093c", "time": "14975", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:41"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14976, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_init_cluster_data", "args":{"pc": "1c0012fa", "instr": "jal x1, 1286 x1=1c0012fc", "time": "14976", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:58"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14978, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "memset", "args":{"pc": "1c001800", "instr": "add x12, x12, x10 x12=10c00048 x12:00000040 x10:10c00008", "time": "14978", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:125"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 14979, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "memset", "args":{"pc": "1c001802", "instr": "add x15, x0, x10 x15=10c00008 x10:10c00008", "time": "14979", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:126"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 14980, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "memset", "args":{"pc": "1c001804", "instr": "bne x15, x12, 6 x15:10c00008 x12:10c00048", "time": "14980", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:127"}}, +{"name": "p.sb", "cat": "p.sb", "ph": "X", "ts": 14983, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "memset", "args":{"pc": "1c00180a", "instr": "p.sb x11, 1(x15!) x15=10c00009 x11:00000000 x15:10c00008 PA:10c00008", "time": "14983", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:128"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 15003, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "memset", "args":{"pc": "1c00180e", "instr": "jal x0, -10 ", "time": "15003", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:128"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 15004, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "memset", "args":{"pc": "1c001804", "instr": "bne x15, x12, 6 x15:10c00009 x12:10c00048", "time": "15004", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:127"}}, +{"name": "p.sb", "cat": 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x15, 1704(x21) x15=1c2fff50 x21:1c002000 PA:1c0026a8", "time": "16657", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:112"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16671, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c00140e", "instr": "addi x8, x8, 64 x8=00000043 x8:00000003", "time": "16671", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 16672, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_icache_cluster_enable", "args":{"pc": "1c001412", "instr": "slli x8, x8, 0x16 x8=10c00000 x8:00000043", "time": "16672", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/icache/icache_ctrl_v2.h:36"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16755, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000001 x12:00000000", "time": "16755", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 16756, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "16756", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 16758, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", 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"jal", "cat": "jal", "ph": "X", "ts": 16785, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "16785", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 16787, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000002 x19:00000008", "time": "16787", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 16790, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10e0004c x14:1c000000 x15:10e00048 PA:10e00048", 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"__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000003 x19:00000008", "time": "16816", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 16819, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10e00050 x14:1c000000 x15:10e0004c PA:10e0004c", "time": "16819", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16842, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000004 x12:00000003", "time": "16842", "Origin": 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"instr": "p.sw x14, 4(x15!) x15=10e00054 x14:1c000000 x15:10e00050 PA:10e00050", "time": "16848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16871, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000005 x12:00000004", "time": "16871", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 16872, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "16872", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 16874, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000005 x19:00000008", "time": "16874", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 16877, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10e00058 x14:1c000000 x15:10e00054 PA:10e00054", "time": "16877", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16900, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000006 x12:00000005", "time": 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"args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10e0005c x14:1c000000 x15:10e00058 PA:10e00058", "time": "16906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000007 x12:00000006", "time": "16929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 16930, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "16930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 16932, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000007 x19:00000008", "time": "16932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 16935, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "plp_ctrl_core_bootaddr_set_remote", "args":{"pc": "1c001454", "instr": "p.sw x14, 4(x15!) x15=10e00060 x14:1c000000 x15:10e0005c PA:10e0005c", "time": "16935", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:59"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16958, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001458", "instr": "addi x12, x12, 1 x12=00000008 x12:00000007", "time": "16958", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 16959, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c00145a", "instr": "jal x0, -24 ", "time": "16959", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "blt", "cat": "blt", "ph": "X", "ts": 16961, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_mount", "args":{"pc": "1c001442", "instr": "blt x12, x19, 18 x12:00000008 x19:00000008", "time": "16961", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:122"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 16962, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c001446", "instr": "lui x15, 0x200000 x15=00200000", "time": "16962", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16963, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144a", "instr": "addi x15, x15, 8 x15=00200008 x15:00200000", "time": "16963", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/cluster_ctrl/cluster_ctrl_v2.h:27"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 16964, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eoc_fetch_enable_remote", "args":{"pc": "1c00144c", "instr": "addi x14, x0, -1 x14=ffffffff", "time": "16964", "Origin": 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:131"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 16996, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c000ffc", "instr": "csrrci x8, 0x00000008, 0x300 x8=00001800", "time": "16996", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17000, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_event_push", "args":{"pc": "1c001000", "instr": "lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c", "time": "17000", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/events.c:133"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17001, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": 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"cat": "lw", "ph": "X", "ts": 17007, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001024", "instr": "lw x14, 4(x15) x14=100fc720 x15:1000013c PA:10000140", "time": "17007", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:392"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17009, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001026", "instr": "sw x10, 8(x14) x10:100fc720 x14:100fc720 PA:100fc728", "time": "17009", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:392"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17010, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_enqueue_event_to_sched", "args":{"pc": "1c001028", "instr": "jal x0, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17138, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014be", "instr": "sw x25, 36(x2) x25:00000000 x2:10000920 PA:10000944", "time": "17138", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 17155, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0014c0", "instr": "csrrci x22, 0x00000008, 0x300 x22=00001808", "time": "17155", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17159, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0014c4", "instr": "add x18, x0, x17 x18=00000008 x17:00000008", "time": "17159", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17160, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014c6", "instr": "bne x17, x0, 8 x17:00000008", "time": "17160", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:294"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17180, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ce", "instr": "lui x15, 0x1c002000 x15=1c002000", "time": "17180", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17181, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014d2", "instr": "lw x25, 1704(x15) x25=1c2fff50 x15:1c002000 PA:1c0026a8", "time": "17181", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17195, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014d6", "instr": "addi x15, x0, 24 x15=00000018", "time": "17195", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17196, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014d8", "instr": "addi x20, x27, 64 x20=00000041 x27:00000001", "time": "17196", "Origin": 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"rt_cluster_tiny_addr", "args":{"pc": "1c0014e4", "instr": "lui x13, 0x1000 x13=00001000", "time": "17215", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 17216, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014e6", "instr": "slli x20, x20, 0x16 x20=10400000 x20:00000041", "time": "17216", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17217, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014e8", "instr": "addi x14, x14, 8 x14=1b000008 x14:1b000000", "time": "17217", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17218, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014ec", "instr": "addi x13, x13, -1 x13=00000fff x13:00001000", "time": "17218", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17235, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ee", "instr": "lw x15, 4(x25) x15=00000000 x25:1c2fff68 PA:1c2fff6c", "time": "17235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:304"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 17250, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014f2", "instr": "slli x8, x15, 0x5 x8=00000000 x15:00000000", "time": "17250", "Origin": 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"rt_cluster_tiny_addr", "args":{"pc": "1c0014fa", "instr": "add x8, x8, x20 x8=10400008 x8:00000008 x20:10400000", "time": "17253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17254, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014fc", "instr": "lw x12, 0(x8) x12=00000000 x8:10400008 PA:10400008", "time": "17254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:308"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17273, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014fe", "instr": "beq x12, x0, 14 x12:00000000", "time": "17273", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:308"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17276, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00150c", "instr": "lw x11, 12(x25) x11=00000000 x25:1c2fff68 PA:1c2fff74", "time": "17276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:315"}}, +{"name": "xori", "cat": "xori", "ph": "X", "ts": 17295, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001510", "instr": "xori x15, x15, 1 x15=00000001 x15:00000000", "time": "17295", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:313"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17296, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001514", "instr": "sw x15, 4(x25) x15:00000001 x25:1c2fff68 PA:1c2fff6c", "time": "17296", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:313"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17314, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001518", "instr": "beq x11, x0, 16 x11:00000000", "time": "17314", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:315"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001528", "instr": "bne x9, x0, 6 x9:00000000", "time": "17333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17334, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cl_master_stack_size_get", "args":{"pc": "1c00152a", "instr": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_evt_trig", "args":{"pc": "1c001582", "instr": "addi x15, x15, -508 x15=00200e04 x15:00201000", "time": "17673", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:286"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 17674, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_evt_trig", "args":{"pc": "1c001586", "instr": "p.sw x0, x0(x20) x20:10400000 PA:10600e04", "time": "17674", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:286"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17697, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00158a", "instr": "addi x27, x0, 0 x27=00000000", "time": "17697", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:291"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17698, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_wait_event_check", "args":{"pc": "1c00158c", "instr": "bne x21, x0, 6 x21:100fc720", "time": "17698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:325"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 17701, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c001592", "instr": "csrrw x0, x22, 0x300 x22:00001808", "time": "17701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17705, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001596", "instr": "lw x1, 76(x2) x1=1c000aa0 x2:10000920 PA:1000096c", "time": "17705", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17706, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001598", "instr": "lw x8, 72(x2) x8=00000002 x2:10000920 PA:10000968", "time": "17706", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17707, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159a", "instr": "add x10, x0, x27 x10=00000000 x27:00000000", "time": "17707", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17708, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159c", "instr": "lw x9, 68(x2) x9=100fc720 x2:10000920 PA:10000964", "time": "17708", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17709, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159e", "instr": "lw x18, 64(x2) x18=1c001000 x2:10000920 PA:10000960", "time": "17709", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17725, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a0", "instr": "lw x19, 60(x2) x19=00000000 x2:10000920 PA:1000095c", "time": "17725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17726, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a2", "instr": "lw x20, 56(x2) x20=00000000 x2:10000920 PA:10000958", "time": "17726", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17727, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a4", "instr": "lw x21, 52(x2) x21=00000000 x2:10000920 PA:10000954", "time": "17727", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17728, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a6", "instr": "lw x22, 48(x2) x22=00000000 x2:10000920 PA:10000950", "time": "17728", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17729, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a8", "instr": "lw x23, 44(x2) x23=00000000 x2:10000920 PA:1000094c", "time": "17729", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17730, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015aa", "instr": "lw x24, 40(x2) x24=00000000 x2:10000920 PA:10000948", "time": "17730", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17731, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015ac", "instr": "lw x25, 36(x2) x25=00000000 x2:10000920 PA:10000944", "time": "17731", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17732, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015ae", "instr": "lw x26, 32(x2) x26=00000000 x2:10000920 PA:10000940", "time": "17732", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17733, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b0", "instr": "lw x27, 28(x2) x27=00000000 x2:10000920 PA:1000093c", "time": "17733", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17734, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b2", "instr": "addi x2, x2, 80 x2=10000970 x2:10000920", "time": "17734", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17735, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b4", "instr": "jalr x0, x1, 0 x1:1c000aa0", "time": "17735", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 17737, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aa0", "instr": "p.bneimm x8, -26 x8:00000002", "time": "17737", "Origin": "/scratch/digirols/pulp_api_example/main.c:72 (discriminator 3)"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17740, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a86", "instr": "add x11, x0, x8 x11=00000002 x8:00000002", "time": "17740", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17741, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a88", "instr": "sw x9, 0(x2) x9:100fc720 x2:10000970 PA:10000970", "time": "17741", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17742, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a8a", "instr": "addi x8, x8, 1 x8=00000003 x8:00000002", "time": "17742", "Origin": "/scratch/digirols/pulp_api_example/main.c:72 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17743, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a8c", "instr": "addi x17, x0, 8 x17=00000008", "time": "17743", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17744, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a8e", "instr": "addi x16, x0, 0 x16=00000000", "time": "17744", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17745, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a90", "instr": "addi x15, x0, 0 x15=00000000", "time": "17745", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17746, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a92", "instr": "addi x14, x0, 0 x14=00000000", "time": "17746", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17747, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a94", "instr": "addi x13, x0, 0 x13=00000000", "time": "17747", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17748, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a96", "instr": "addi x12, x18, -1576 x12=1c0009d8 x18:1c001000", "time": "17748", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17749, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a9a", "instr": "addi x10, x0, 0 x10=00000000", "time": "17749", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17750, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a9c", "instr": "jal x1, 2554 x1=1c000aa0", "time": "17750", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17752, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001496", "instr": "addi x2, x2, -80 x2=10000920 x2:10000970", "time": "17752", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17753, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001498", "instr": "sw x21, 52(x2) x21:00000000 x2:10000920 PA:10000954", "time": "17753", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17754, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00149a", "instr": "lw x21, 80(x2) x21=100fc720 x2:10000920 PA:10000970", "time": "17754", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17755, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00149c", "instr": "sw x9, 68(x2) x9:100fc720 x2:10000920 PA:10000964", "time": "17755", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17756, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00149e", "instr": "sw x19, 60(x2) x19:00000000 x2:10000920 PA:1000095c", "time": "17756", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17757, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a0", "instr": "sw x23, 44(x2) x23:00000000 x2:10000920 PA:1000094c", "time": "17757", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17758, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a2", "instr": "sw x24, 40(x2) x24:00000000 x2:10000920 PA:10000948", "time": "17758", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17759, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a4", "instr": "sw x26, 32(x2) x26:00000000 x2:10000920 PA:10000940", "time": "17759", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17760, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a6", "instr": "sw x27, 28(x2) x27:00000000 x2:10000920 PA:1000093c", "time": "17760", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17761, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a8", "instr": "add x24, x0, x12 x24=1c0009d8 x12:1c0009d8", "time": "17761", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17762, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014aa", "instr": "add x27, x0, x11 x27=00000002 x11:00000002", "time": "17762", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17763, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ac", "instr": "add x23, x0, x13 x23=00000000 x13:00000000", "time": "17763", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17764, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ae", "instr": "add x26, x0, x14 x26=00000000 x14:00000000", "time": "17764", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17765, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014b0", "instr": "add x9, x0, x15 x9=00000000 x15:00000000", "time": "17765", "Origin": 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"1c0014b6", "instr": "sw x8, 72(x2) x8:00000003 x2:10000920 PA:10000968", "time": "17768", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17769, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014b8", "instr": "sw x18, 64(x2) x18:1c001000 x2:10000920 PA:10000960", "time": "17769", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17770, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ba", "instr": "sw x20, 56(x2) x20:00000000 x2:10000920 PA:10000958", "time": "17770", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17771, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014bc", "instr": "sw x22, 48(x2) x22:00000000 x2:10000920 PA:10000950", "time": "17771", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17772, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014be", "instr": "sw x25, 36(x2) x25:00000000 x2:10000920 PA:10000944", "time": "17772", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 17773, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0014c0", "instr": "csrrci x22, 0x00000008, 0x300 x22=00001808", "time": "17773", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17777, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0014c4", "instr": "add x18, x0, x17 x18=00000008 x17:00000008", "time": "17777", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17778, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014c6", "instr": "bne x17, x0, 8 x17:00000008", "time": "17778", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:294"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17782, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ce", "instr": "lui x15, 0x1c002000 x15=1c002000", "time": "17782", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17783, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014d2", "instr": "lw x25, 1704(x15) x25=1c2fff50 x15:1c002000 PA:1c0026a8", "time": "17783", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17798, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014d6", "instr": "addi x15, x0, 24 x15=00000018", "time": "17798", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17799, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014d8", "instr": "addi x20, x27, 64 x20=00000042 x27:00000002", "time": "17799", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "p.mac", "cat": "p.mac", "ph": "X", "ts": 17800, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014dc", "instr": "p.mac x25, x27, x15 x25=1c2fff80 x25:1c2fff50 x27:00000002 x15:00000018", "time": "17800", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17801, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014e0", "instr": "lui x14, 0x1b000000 x14=1b000000", "time": "17801", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17802, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014e4", "instr": "lui x13, 0x1000 x13=00001000", "time": "17802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 17803, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014e6", "instr": "slli x20, x20, 0x16 x20=10800000 x20:00000042", "time": "17803", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17804, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014e8", "instr": "addi x14, x14, 8 x14=1b000008 x14:1b000000", "time": "17804", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17805, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014ec", "instr": "addi x13, x13, -1 x13=00000fff x13:00001000", "time": "17805", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17806, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ee", "instr": "lw x15, 4(x25) x15=00000000 x25:1c2fff80 PA:1c2fff84", "time": "17806", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:304"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 17821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014f2", "instr": "slli x8, x15, 0x5 x8=00000000 x15:00000000", "time": "17821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17822, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014f6", "instr": "add x8, x8, x14 x8=1b000008 x8:00000000 x14:1b000008", "time": "17822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 17823, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014f8", "instr": "and x8, x8, x13 x8=00000008 x8:1b000008 x13:00000fff", "time": "17823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17824, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014fa", "instr": "add x8, x8, x20 x8=10800008 x8:00000008 x20:10800000", "time": "17824", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17825, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014fc", "instr": "lw x12, 0(x8) x12=00000000 x8:10800008 PA:10800008", "time": "17825", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:308"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17843, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014fe", "instr": "beq x12, x0, 14 x12:00000000", "time": "17843", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:308"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 17846, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00150c", "instr": "lw x11, 12(x25) x11=00000000 x25:1c2fff80 PA:1c2fff8c", "time": "17846", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:315"}}, +{"name": "xori", "cat": "xori", "ph": "X", "ts": 17860, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001510", "instr": "xori x15, x15, 1 x15=00000001 x15:00000000", "time": "17860", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:313"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17861, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001514", "instr": "sw x15, 4(x25) x15:00000001 x25:1c2fff80 PA:1c2fff84", "time": "17861", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:313"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17879, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001518", "instr": "beq x11, x0, 16 x11:00000000", "time": "17879", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:315"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17882, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001528", "instr": "bne x9, x0, 6 x9:00000000", "time": "17882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:321"}}, 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:330"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17886, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001536", "instr": "bne x26, x0, 34 x26:00000000", "time": "17886", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:323"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17887, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00153a", "instr": "addi x15, x18, -1 x15=00000007 x18:00000008", "time": "17887", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:325"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17888, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": 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"args":{"pc": "1c00158a", "instr": "addi x27, x0, 0 x27=00000000", "time": "18199", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:291"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18200, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_wait_event_check", "args":{"pc": "1c00158c", "instr": "bne x21, x0, 6 x21:100fc720", "time": "18200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:325"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 18203, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c001592", "instr": "csrrw x0, x22, 0x300 x22:00001808", "time": "18203", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18207, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001596", "instr": "lw x1, 76(x2) x1=1c000aa0 x2:10000920 PA:1000096c", "time": "18207", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18208, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001598", "instr": "lw x8, 72(x2) x8=00000003 x2:10000920 PA:10000968", "time": "18208", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18209, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159a", "instr": "add x10, x0, x27 x10=00000000 x27:00000000", "time": "18209", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18210, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159c", "instr": "lw x9, 68(x2) x9=100fc720 x2:10000920 PA:10000964", "time": "18210", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18211, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159e", "instr": "lw x18, 64(x2) x18=1c001000 x2:10000920 PA:10000960", "time": "18211", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18212, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a0", "instr": "lw x19, 60(x2) x19=00000000 x2:10000920 PA:1000095c", "time": "18212", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18213, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a2", "instr": "lw x20, 56(x2) x20=00000000 x2:10000920 PA:10000958", "time": "18213", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18214, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a4", "instr": "lw x21, 52(x2) x21=00000000 x2:10000920 PA:10000954", "time": "18214", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18215, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a6", "instr": "lw x22, 48(x2) x22=00000000 x2:10000920 PA:10000950", "time": "18215", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18216, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a8", "instr": "lw x23, 44(x2) x23=00000000 x2:10000920 PA:1000094c", "time": "18216", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18217, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015aa", "instr": "lw x24, 40(x2) x24=00000000 x2:10000920 PA:10000948", "time": "18217", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18218, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015ac", "instr": "lw x25, 36(x2) x25=00000000 x2:10000920 PA:10000944", "time": "18218", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18219, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015ae", "instr": "lw x26, 32(x2) x26=00000000 x2:10000920 PA:10000940", "time": "18219", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18220, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b0", "instr": "lw x27, 28(x2) x27=00000000 x2:10000920 PA:1000093c", "time": "18220", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18221, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b2", "instr": "addi x2, x2, 80 x2=10000970 x2:10000920", "time": "18221", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18222, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b4", "instr": "jalr x0, x1, 0 x1:1c000aa0", "time": "18222", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 18224, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aa0", "instr": "p.bneimm x8, -26 x8:00000003", "time": "18224", "Origin": "/scratch/digirols/pulp_api_example/main.c:72 (discriminator 3)"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18227, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a86", "instr": "add x11, x0, x8 x11=00000003 x8:00000003", "time": "18227", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18228, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a88", "instr": "sw x9, 0(x2) x9:100fc720 x2:10000970 PA:10000970", "time": "18228", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18229, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a8a", "instr": "addi x8, x8, 1 x8=00000004 x8:00000003", "time": "18229", "Origin": "/scratch/digirols/pulp_api_example/main.c:72 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a8c", "instr": "addi x17, x0, 8 x17=00000008", "time": "18230", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18231, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a8e", "instr": "addi x16, x0, 0 x16=00000000", "time": "18231", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a90", "instr": "addi x15, x0, 0 x15=00000000", "time": "18232", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a92", "instr": "addi x14, x0, 0 x14=00000000", "time": "18233", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a94", "instr": "addi x13, x0, 0 x13=00000000", "time": "18234", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18235, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a96", "instr": "addi x12, x18, -1576 x12=1c0009d8 x18:1c001000", "time": "18235", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18236, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a9a", "instr": "addi x10, x0, 0 x10=00000000", "time": "18236", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18237, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000a9c", "instr": "jal x1, 2554 x1=1c000aa0", "time": "18237", "Origin": "/scratch/digirols/pulp_api_example/main.c:73 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001496", "instr": "addi x2, x2, -80 x2=10000920 x2:10000970", "time": "18239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001498", "instr": "sw x21, 52(x2) x21:00000000 x2:10000920 PA:10000954", "time": "18240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00149a", "instr": "lw x21, 80(x2) x21=100fc720 x2:10000920 PA:10000970", "time": "18241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18242, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00149c", "instr": "sw x9, 68(x2) x9:100fc720 x2:10000920 PA:10000964", "time": "18242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18243, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00149e", "instr": "sw x19, 60(x2) x19:00000000 x2:10000920 PA:1000095c", "time": "18243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18244, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a0", "instr": "sw x23, 44(x2) x23:00000000 x2:10000920 PA:1000094c", "time": "18244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a2", "instr": "sw x24, 40(x2) x24:00000000 x2:10000920 PA:10000948", "time": "18245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18246, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014a4", "instr": "sw x26, 32(x2) x26:00000000 x2:10000920 PA:10000940", "time": "18246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18247, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18250, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ac", "instr": "add x23, x0, x13 x23=00000000 x13:00000000", "time": "18250", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18251, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ae", "instr": "add x26, x0, x14 x26=00000000 x14:00000000", "time": "18251", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18252, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014b0", "instr": "add x9, x0, x15 x9=00000000 x15:00000000", "time": "18252", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18253, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014b2", "instr": "add x19, x0, x16 x19=00000000 x16:00000000", "time": "18253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18254, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014b4", "instr": "sw x1, 76(x2) x1:1c000aa0 x2:10000920 PA:1000096c", "time": "18254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18255, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014b6", "instr": "sw x8, 72(x2) x8:00000004 x2:10000920 PA:10000968", "time": "18255", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18256, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014b8", "instr": "sw x18, 64(x2) x18:1c001000 x2:10000920 PA:10000960", "time": "18256", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18257, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ba", "instr": "sw x20, 56(x2) x20:00000000 x2:10000920 PA:10000958", "time": "18257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18258, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014bc", "instr": "sw x22, 48(x2) x22:00000000 x2:10000920 PA:10000950", "time": "18258", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18259, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014be", "instr": "sw x25, 36(x2) x25:00000000 x2:10000920 PA:10000944", "time": "18259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:290"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 18260, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0014c0", "instr": "csrrci x22, 0x00000008, 0x300 x22=00001808", "time": "18260", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18264, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0014c4", "instr": "add x18, x0, x17 x18=00000008 x17:00000008", "time": "18264", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18265, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014c6", "instr": "bne x17, x0, 8 x17:00000008", "time": "18265", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:294"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18269, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ce", "instr": "lui x15, 0x1c002000 x15=1c002000", "time": "18269", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18270, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014d2", "instr": "lw x25, 1704(x15) x25=1c2fff50 x15:1c002000 PA:1c0026a8", "time": "18270", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18286, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014d6", "instr": "addi x15, x0, 24 x15=00000018", "time": "18286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18287, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014d8", "instr": "addi x20, x27, 64 x20=00000043 x27:00000003", "time": "18287", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "p.mac", "cat": "p.mac", "ph": "X", "ts": 18288, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014dc", "instr": "p.mac x25, x27, x15 x25=1c2fff98 x25:1c2fff50 x27:00000003 x15:00000018", "time": "18288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:298"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18289, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014e0", "instr": "lui x14, 0x1b000000 x14=1b000000", "time": "18289", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18290, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014e4", "instr": "lui x13, 0x1000 x13=00001000", "time": "18290", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18291, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014e6", "instr": "slli x20, x20, 0x16 x20=10c00000 x20:00000043", "time": "18291", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18292, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014e8", "instr": "addi x14, x14, 8 x14=1b000008 x14:1b000000", "time": "18292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18293, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014ec", "instr": "addi x13, x13, -1 x13=00000fff x13:00001000", "time": "18293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18294, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014ee", "instr": "lw x15, 4(x25) x15=00000000 x25:1c2fff98 PA:1c2fff9c", "time": "18294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:304"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18309, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014f2", "instr": "slli x8, x15, 0x5 x8=00000000 x15:00000000", "time": "18309", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18310, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014f6", "instr": "add x8, x8, x14 x8=1b000008 x8:00000000 x14:1b000008", "time": "18310", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:305"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18311, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014f8", "instr": "and x8, x8, x13 x8=00000008 x8:1b000008 x13:00000fff", "time": "18311", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18312, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_tiny_addr", "args":{"pc": "1c0014fa", "instr": "add x8, x8, x20 x8=10c00008 x8:00000008 x20:10c00000", "time": "18312", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:783"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18313, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014fc", "instr": "lw x12, 0(x8) x12=00000000 x8:10c00008 PA:10c00008", "time": "18313", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:308"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18331, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0014fe", "instr": "beq x12, x0, 14 x12:00000000", "time": "18331", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:308"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18334, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00150c", "instr": "lw x11, 12(x25) x11=00000000 x25:1c2fff98 PA:1c2fffa4", "time": "18334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:315"}}, +{"name": "xori", "cat": "xori", "ph": "X", "ts": 18351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001510", "instr": "xori x15, x15, 1 x15=00000001 x15:00000000", "time": "18351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:313"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18352, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001514", "instr": "sw x15, 4(x25) x15:00000001 x25:1c2fff98 PA:1c2fff9c", "time": "18352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:313"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18370, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001518", "instr": "beq x11, x0, 16 x11:00000000", "time": "18370", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:315"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001528", "instr": "bne x9, x0, 6 x9:00000000", "time": "18373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cl_master_stack_size_get", "args":{"pc": "1c00152a", "instr": "addi x9, x0, 1024 x9=00000400", "time": "18374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_utils.h:320"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18375, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00152e", "instr": "bne x19, x0, 8 x19:00000000", "time": "18375", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:322"}}, 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"tid": "rt_cluster_call", "args":{"pc": "1c001544", "instr": "addi x10, x27, 2 x10=00000005 x27:00000003", "time": "18381", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:326"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18382, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001548", "instr": "addi x27, x0, -1 x27=ffffffff", "time": "18382", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:328"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18383, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00154a", "instr": "sw x11, 16(x25) x11:00002000 x25:1c2fff98 PA:1c2fffa8", "time": "18383", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:325"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18401, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:286"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18690, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00158a", "instr": "addi x27, x0, 0 x27=00000000", "time": "18690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:291"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18691, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_wait_event_check", "args":{"pc": "1c00158c", "instr": "bne x21, x0, 6 x21:100fc720", "time": "18691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_event.h:325"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 18694, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c001592", "instr": "csrrw x0, x22, 0x300 x22:00001808", "time": "18694", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18698, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001596", "instr": "lw x1, 76(x2) x1=1c000aa0 x2:10000920 PA:1000096c", "time": "18698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c001598", "instr": "lw x8, 72(x2) x8=00000004 x2:10000920 PA:10000968", "time": "18699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18700, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159a", "instr": "add x10, x0, x27 x10=00000000 x27:00000000", "time": "18700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159c", "instr": "lw x9, 68(x2) x9=100fc720 x2:10000920 PA:10000964", "time": "18701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18702, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c00159e", "instr": "lw x18, 64(x2) x18=1c001000 x2:10000920 PA:10000960", "time": "18702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18703, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a0", "instr": "lw x19, 60(x2) x19=00000000 x2:10000920 PA:1000095c", "time": "18703", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18704, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a2", "instr": "lw x20, 56(x2) x20=00000000 x2:10000920 PA:10000958", "time": "18704", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18705, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a4", "instr": "lw x21, 52(x2) x21=00000000 x2:10000920 PA:10000954", "time": "18705", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18706, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a6", "instr": "lw x22, 48(x2) x22=00000000 x2:10000920 PA:10000950", "time": "18706", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18707, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015a8", "instr": "lw x23, 44(x2) x23=00000000 x2:10000920 PA:1000094c", "time": "18707", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18708, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015aa", "instr": "lw x24, 40(x2) x24=00000000 x2:10000920 PA:10000948", "time": "18708", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18709, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015ac", "instr": "lw x25, 36(x2) x25=00000000 x2:10000920 PA:10000944", "time": "18709", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18710, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015ae", "instr": "lw x26, 32(x2) x26=00000000 x2:10000920 PA:10000940", "time": "18710", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 18711, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b0", "instr": "lw x27, 28(x2) x27=00000000 x2:10000920 PA:1000093c", "time": "18711", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18712, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b2", "instr": "addi x2, x2, 80 x2=10000970 x2:10000920", "time": "18712", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18713, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_call", "args":{"pc": "1c0015b4", "instr": "jalr x0, x1, 0 x1:1c000aa0", "time": "18713", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:365"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 18715, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aa0", "instr": "p.bneimm x8, -26 x8:00000004", "time": "18715", "Origin": "/scratch/digirols/pulp_api_example/main.c:72 (discriminator 3)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18716, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aa4", "instr": "addi x10, x0, 0 x10=00000000", "time": "18716", "Origin": "/scratch/digirols/pulp_api_example/main.c:77"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18717, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aa6", "instr": "lui x18, 0x1c002000 x18=1c002000", "time": "18717", "Origin": "/scratch/digirols/pulp_api_example/main.c:77"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18718, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aaa", "instr": "jal x1, -210 x1=1c000aac", "time": "18718", "Origin": "/scratch/digirols/pulp_api_example/main.c:77"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18737, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "cluster_entry", "args":{"pc": "1c0009d8", "instr": "addi x2, x2, -16 x2=10000960 x2:10000970", "time": "18737", "Origin": "/scratch/digirols/pulp_api_example/main.c:52"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18738, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_dispatch_team_config", "args":{"pc": "1c0009da", "instr": "addi x14, x0, 255 x14=000000ff", "time": "18738", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:419"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18757, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_dispatch_team_config", "args":{"pc": "1c0009de", "instr": "lui x15, 0x1b204000 x15=1b204000", "time": "18757", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:419"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18758, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "cluster_entry", "args":{"pc": "1c0009e2", "instr": "sw x1, 12(x2) x1:1c000aac x2:10000960 PA:1000096c", "time": "18758", "Origin": "/scratch/digirols/pulp_api_example/main.c:52"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18759, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "cluster_entry", "args":{"pc": "1c0009e4", "instr": "sw x8, 8(x2) x8:00000004 x2:10000960 PA:10000968", "time": "18759", "Origin": "/scratch/digirols/pulp_api_example/main.c:52"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18760, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "cluster_entry", "args":{"pc": "1c0009e6", "instr": "sw x9, 4(x2) x9:100fc720 x2:10000960 PA:10000964", "time": "18760", "Origin": "/scratch/digirols/pulp_api_example/main.c:52"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18761, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_dispatch_team_config", "args":{"pc": "1c0009e8", "instr": "sw x14, 132(x15) x14:000000ff x15:1b204000 PA:1b204084", "time": "18761", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:419"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18762, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_bar_setup_mask", "args":{"pc": "1c0009ec", "instr": "addi x9, x15, 512 x9=1b204200 x15:1b204000", "time": "18762", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:319"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18783, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_bar_setup_mask", "args":{"pc": "1c0009f0", "instr": "sw x14, 0(x9) x14:000000ff x9:1b204200 PA:1b204200", "time": "18783", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:319"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18784, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_bar_setup_mask", "args":{"pc": "1c0009f2", "instr": "addi x15, x15, 524 x15=1b20420c x15:1b204000", "time": "18784", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:320"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18785, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_bar_setup_mask", "args":{"pc": "1c0009f6", "instr": "sw x14, 0(x15) x14:000000ff x15:1b20420c PA:1b20420c", "time": "18785", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:320"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18786, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "eu_dispatch_push", "args":{"pc": "1c0009f8", "instr": "lui x15, 0x1c001000 x15=1c001000", "time": "18786", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:414"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18787, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19217", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19218, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000000", "time": "19218", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19219, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19219", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19220, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000000 x15:00000000", "time": "19220", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19221, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000000 x15:00000000", "time": "19221", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19222, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000", "time": "19222", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19223, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80", "time": "19223", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19224, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000", "time": "19224", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19225, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19225", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19226, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104000", "time": "19226", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19231, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19234, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19237, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19252, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19252", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19253, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19256, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19256", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19257, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19258, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19258", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19260, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19260", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19261, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19261", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19263, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19263", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19264, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000000", "time": "19264", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19265, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19265", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19266, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000000 x15:00000000", "time": "19266", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19267, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000000 x15:00000000", "time": "19267", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19268, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000", "time": "19268", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19302, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19302", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19303, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19303", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19304, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19309", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19310, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000000", "time": "19310", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19311, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19311", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19312, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000000 x15:00000000", "time": "19312", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19313, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000000 x15:00000000", "time": "19313", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19314, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000", "time": "19314", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19315, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80", "time": "19315", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19316, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000", "time": "19316", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19317, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19325, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "19325", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19326, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19326", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19329, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "19329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19347, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "19347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19348, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "19348", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19352, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19353, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19358", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19359, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000000", "time": "19359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19360, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19361, "dur": 1, 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19409, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000000", "time": "19409", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19410, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19410", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19411, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000000 x15:00000000", "time": "19411", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19412, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000000 x15:00000000", "time": "19412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19413, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000", "time": "19413", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19424, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19424", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19425, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19428, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19428", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19447, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19447", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19448, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19448", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19508", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19509, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000000", "time": "19509", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19510, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19510", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19511, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000000 x15:00000000", "time": "19511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19512, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000000 x15:00000000", "time": "19512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19513, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000", "time": "19513", "Origin": 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"/scratch/digirols/pulp_api_example/main.c:80"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21742, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_time_wait_cycles", "args":{"pc": "1c000ab2", "instr": "addi x8, x0, 256 x8=00000100", "time": "21742", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_time.h:113"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 21743, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_time_wait_cycles", "args":{"pc": "1c000ab6", "instr": "slli x14, x9, 0x2 x14=00000004 x9:00000001", "time": "21743", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_time.h:113"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21744, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aba", "instr": "add x14, x14, x18 x14=1c002688 x14:00000004 x18:1c002684", "time": "21744", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21745, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000abc", "instr": "lw x15, 0(x14) x15=00000001 x14:1c002688 PA:1c002688", "time": "21745", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 21761, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000abe", "instr": "bne x15, x0, 20 x15:00000001", "time": "21761", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21783, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad2", "instr": "add x11, x0, x9 x11=00000001 x9:00000001", "time": "21783", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21784, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad4", "instr": "addi x13, x0, 0 x13=00000000", "time": "21784", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21785, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad6", "instr": "addi x9, x9, 1 x9=00000002 x9:00000001", "time": "21785", "Origin": "/scratch/digirols/pulp_api_example/main.c:80 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21786, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad8", "instr": "addi x12, x0, 0 x12=00000000", "time": "21786", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21787, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ada", "instr": "addi x10, x0, 0 x10=00000000", "time": "21787", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21788, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000adc", "instr": "jal x1, 2246 x1=1c000ae0", "time": "21788", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21807, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000940 x2:10000970", "time": "21807", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21808, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000100 x2:10000940 PA:10000968", "time": "21808", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21809, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000001 x11:00000001", "time": "21809", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21810, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a8", "instr": "sw x1, 44(x2) x1:1c000ae0 x2:10000940 PA:1000096c", "time": "21810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21811, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013aa", "instr": "sw x9, 36(x2) x9:00000002 x2:10000940 PA:10000964", "time": "21811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21812, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ac", "instr": "sw x18, 32(x2) x18:1c002684 x2:10000940 PA:10000960", "time": "21812", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21813, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "21813", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21830, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "21830", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21831, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "21831", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 21832, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "21832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21836, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "21836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 21837, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000018 x11:00000001 x20:00000018", "time": "21837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 21854, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "21854", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21855, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "21855", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21869, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "21869", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21870, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff68 x15:1c2fff50 x20:00000018", "time": "21870", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21871, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000001 x15:1c2fff68 PA:1c2fff68", "time": "21871", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21885, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000000", "time": "21885", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f2", "instr": "addi x14, x14, -1 x14=00000000 x14:00000001", "time": "21904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21905, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f4", "instr": "jal x0, -36 ", "time": "21905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000000 x15:1c2fff68 PA:1c2fff68", "time": "21907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21925, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000000 x15:1c2fff68 PA:1c2fff68", "time": "21925", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 21940, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000000", "time": "21940", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21941, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013d6", "instr": "beq x13, x0, 6 x13:00000000", "time": "21941", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 21944, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c0013dc", "instr": "csrrw x0, x18, 0x300 x18:00001808", "time": "21944", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21961, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e0", "instr": "lw x1, 44(x2) x1=1c000ae0 x2:10000940 PA:1000096c", "time": "21961", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21962, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e2", "instr": "lw x8, 40(x2) x8=00000100 x2:10000940 PA:10000968", "time": "21962", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21963, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e4", "instr": "lw x9, 36(x2) x9=00000002 x2:10000940 PA:10000964", "time": "21963", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21964, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e6", "instr": "lw x18, 32(x2) x18=1c002684 x2:10000940 PA:10000960", "time": "21964", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e8", "instr": "lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c", "time": "21965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21966, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ea", "instr": "lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958", "time": "21966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21967, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ec", "instr": "lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954", "time": "21967", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21968, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ee", "instr": "addi x2, x2, 48 x2=10000970 x2:10000940", "time": "21968", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21969, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f0", "instr": "jalr x0, x1, 0 x1:1c000ae0", "time": "21969", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 21971, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ae0", "instr": "p.bneimm x9, -42 x9:00000002", "time": "21971", "Origin": "/scratch/digirols/pulp_api_example/main.c:80 (discriminator 2)"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 21974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_time_wait_cycles", "args":{"pc": "1c000ab6", "instr": "slli x14, x9, 0x2 x14=00000008 x9:00000002", "time": "21974", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_time.h:113"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aba", "instr": "add x14, x14, x18 x14=1c00268c x14:00000008 x18:1c002684", "time": "21975", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21976, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000abc", "instr": "lw x15, 0(x14) x15=00000001 x14:1c00268c PA:1c00268c", "time": "21976", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 21991, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000abe", "instr": "bne x15, x0, 20 x15:00000001", "time": "21991", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21994, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad2", "instr": "add x11, x0, x9 x11=00000002 x9:00000002", "time": "21994", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21995, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad4", "instr": "addi x13, x0, 0 x13=00000000", "time": "21995", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21996, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad6", "instr": "addi x9, x9, 1 x9=00000003 x9:00000002", "time": "21996", "Origin": "/scratch/digirols/pulp_api_example/main.c:80 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21997, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad8", "instr": "addi x12, x0, 0 x12=00000000", "time": "21997", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21998, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ada", "instr": "addi x10, x0, 0 x10=00000000", "time": "21998", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21999, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000adc", "instr": "jal x1, 2246 x1=1c000ae0", "time": "21999", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22001, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000940 x2:10000970", "time": "22001", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22002, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000100 x2:10000940 PA:10000968", "time": "22002", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22003, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000002 x11:00000002", "time": "22003", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22004, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a8", "instr": "sw x1, 44(x2) x1:1c000ae0 x2:10000940 PA:1000096c", "time": "22004", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22005, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013aa", "instr": "sw x9, 36(x2) x9:00000003 x2:10000940 PA:10000964", "time": "22005", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22006, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ac", "instr": "sw x18, 32(x2) x18:1c002684 x2:10000940 PA:10000960", "time": "22006", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22007, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "22007", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22008, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "22008", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22009, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "22009", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 22010, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "22010", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22014, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "22014", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 22015, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000030 x11:00000002 x20:00000018", "time": "22015", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 22016, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "22016", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22017, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "22017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22031, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "22031", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22032, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff80 x15:1c2fff50 x20:00000030", "time": "22032", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22033, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000001 x15:1c2fff80 PA:1c2fff80", "time": "22033", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 22047, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000000", "time": "22047", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22050, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f2", "instr": "addi x14, x14, -1 x14=00000000 x14:00000001", "time": "22050", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 22051, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f4", "instr": "jal x0, -36 ", "time": "22051", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22053, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000000 x15:1c2fff80 PA:1c2fff80", "time": "22053", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22071, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000000 x15:1c2fff80 PA:1c2fff80", "time": "22071", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 22086, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000000", "time": "22086", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 22087, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013d6", "instr": "beq x13, x0, 6 x13:00000000", "time": "22087", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 22090, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c0013dc", "instr": "csrrw x0, x18, 0x300 x18:00001808", "time": "22090", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22094, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e0", "instr": "lw x1, 44(x2) x1=1c000ae0 x2:10000940 PA:1000096c", "time": "22094", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22095, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e2", "instr": "lw x8, 40(x2) x8=00000100 x2:10000940 PA:10000968", "time": "22095", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22096, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e4", "instr": "lw x9, 36(x2) x9=00000003 x2:10000940 PA:10000964", "time": "22096", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22097, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e6", "instr": "lw x18, 32(x2) x18=1c002684 x2:10000940 PA:10000960", "time": "22097", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22098, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e8", "instr": "lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c", "time": "22098", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22099, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ea", "instr": "lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958", "time": "22099", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22100, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ec", "instr": "lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954", "time": "22100", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22101, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ee", "instr": "addi x2, x2, 48 x2=10000970 x2:10000940", "time": "22101", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 22102, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f0", "instr": "jalr x0, x1, 0 x1:1c000ae0", "time": "22102", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 22104, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ae0", "instr": "p.bneimm x9, -42 x9:00000003", "time": "22104", "Origin": "/scratch/digirols/pulp_api_example/main.c:80 (discriminator 2)"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 22107, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_time_wait_cycles", "args":{"pc": "1c000ab6", "instr": "slli x14, x9, 0x2 x14=0000000c x9:00000003", "time": "22107", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/rt/rt_time.h:113"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22108, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aba", "instr": "add x14, x14, x18 x14=1c002690 x14:0000000c x18:1c002684", "time": "22108", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22109, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000abc", "instr": "lw x15, 0(x14) x15=00000001 x14:1c002690 PA:1c002690", "time": "22109", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 22124, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000abe", "instr": "bne x15, x0, 20 x15:00000001", "time": "22124", "Origin": "/scratch/digirols/pulp_api_example/main.c:81"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22127, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad2", "instr": "add x11, x0, x9 x11=00000003 x9:00000003", "time": "22127", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22128, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad4", "instr": "addi x13, x0, 0 x13=00000000", "time": "22128", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22129, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad6", "instr": "addi x9, x9, 1 x9=00000004 x9:00000003", "time": "22129", "Origin": "/scratch/digirols/pulp_api_example/main.c:80 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22130, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ad8", "instr": "addi x12, x0, 0 x12=00000000", "time": "22130", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22131, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ada", "instr": "addi x10, x0, 0 x10=00000000", "time": "22131", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 22132, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000adc", "instr": "jal x1, 2246 x1=1c000ae0", "time": "22132", "Origin": "/scratch/digirols/pulp_api_example/main.c:84 (discriminator 2)"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a2", "instr": "addi x2, x2, -48 x2=10000940 x2:10000970", "time": "22134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22135, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a4", "instr": "sw x8, 40(x2) x8:00000100 x2:10000940 PA:10000968", "time": "22135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22136, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a6", "instr": "add x8, x0, x11 x8=00000003 x11:00000003", "time": "22136", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22137, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013a8", "instr": "sw x1, 44(x2) x1:1c000ae0 x2:10000940 PA:1000096c", "time": "22137", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22138, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013aa", "instr": "sw x9, 36(x2) x9:00000004 x2:10000940 PA:10000964", "time": "22138", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22139, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ac", "instr": "sw x18, 32(x2) x18:1c002684 x2:10000940 PA:10000960", "time": "22139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22140, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ae", "instr": "sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c", "time": "22140", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22141, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b0", "instr": "sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958", "time": "22141", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22142, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b2", "instr": "sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954", "time": "22142", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:182"}}, +{"name": "csrrci", "cat": "csrrci", "ph": "X", "ts": 22143, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_read_then_clr", "args":{"pc": "1c0013b4", "instr": "csrrci x18, 0x00000008, 0x300 x18=00001808", "time": "22143", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:39"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22147, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013b8", "instr": "addi x20, x0, 24 x20=00000018", "time": "22147", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 22148, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ba", "instr": "mul x20, x11, x20 x20=00000048 x11:00000003 x20:00000018", "time": "22148", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 22149, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013be", "instr": "lui x14, 0x1c002000 x14=1c002000", "time": "22149", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22150, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c2", "instr": "lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8", "time": "22150", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22164, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c6", "instr": "add x21, x0, x14 x21=1c002000 x14:1c002000", "time": "22164", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22165, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013c8", "instr": "add x15, x15, x20 x15=1c2fff98 x15:1c2fff50 x20:00000048", "time": "22165", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22166, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ca", "instr": "lw x14, 0(x15) x14=00000001 x15:1c2fff98 PA:1c2fff98", "time": "22166", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:185"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 22180, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013cc", "instr": "beq x10, x0, 38 x10:00000000", "time": "22180", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:187"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22183, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f2", "instr": "addi x14, x14, -1 x14=00000000 x14:00000001", "time": "22183", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 22184, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f4", "instr": "jal x0, -36 ", "time": "22184", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22186, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d0", "instr": "sw x14, 0(x15) x14:00000000 x15:1c2fff98 PA:1c2fff98", "time": "22186", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:188"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22204, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d2", "instr": "lw x9, 0(x15) x9=00000000 x15:1c2fff98 PA:1c2fff98", "time": "22204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 22219, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013d4", "instr": "bne x9, x0, 34 x9:00000000", "time": "22219", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:190"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 22220, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cluster_unmount", "args":{"pc": "1c0013d6", "instr": "beq x13, x0, 6 x13:00000000", "time": "22220", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:176"}}, +{"name": "csrrw", "cat": "csrrw", "ph": "X", "ts": 22223, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "hal_spr_write", "args":{"pc": "1c0013dc", "instr": "csrrw x0, x18, 0x300 x18:00001808", "time": "22223", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:44"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22227, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e0", "instr": "lw x1, 44(x2) x1=1c000ae0 x2:10000940 PA:1000096c", "time": "22227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22228, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e2", "instr": "lw x8, 40(x2) x8=00000100 x2:10000940 PA:10000968", "time": "22228", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22229, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e4", "instr": "lw x9, 36(x2) x9=00000004 x2:10000940 PA:10000964", "time": "22229", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e6", "instr": "lw x18, 32(x2) x18=1c002684 x2:10000940 PA:10000960", "time": "22230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22231, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013e8", "instr": "lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c", "time": "22231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ea", "instr": "lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958", "time": "22232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ec", "instr": "lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954", "time": "22233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013ee", "instr": "addi x2, x2, 48 x2=10000970 x2:10000940", "time": "22234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 22235, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "rt_cluster_mount", "args":{"pc": "1c0013f0", "instr": "jalr x0, x1, 0 x1:1c000ae0", "time": "22235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/cluster.c:194"}}, +{"name": "p.bneimm", "cat": "p.bneimm", "ph": "X", "ts": 22237, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ae0", "instr": "p.bneimm x9, -42 x9:00000004", "time": "22237", "Origin": "/scratch/digirols/pulp_api_example/main.c:80 (discriminator 2)"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22238, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ae4", "instr": "lw x1, 28(x2) x1=1c0000ec x2:10000970 PA:1000098c", "time": "22238", "Origin": "/scratch/digirols/pulp_api_example/main.c:91"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ae6", "instr": "lw x8, 24(x2) x8=00000000 x2:10000970 PA:10000988", "time": "22239", "Origin": "/scratch/digirols/pulp_api_example/main.c:91"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 22240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000ae8", "instr": "lui x15, 0x1b200000 x15=1b200000", "time": "22240", "Origin": "/scratch/digirols/pulp_api_example/main.c:88"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aec", "instr": "addi x14, x0, 1 x14=00000001", "time": "22241", "Origin": "/scratch/digirols/pulp_api_example/main.c:88"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22242, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000aee", "instr": "sw x14, 0(x15) x14:00000001 x15:1b200000 PA:1b200000", "time": "22242", "Origin": "/scratch/digirols/pulp_api_example/main.c:88"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22258, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000af0", "instr": "lw x9, 20(x2) x9=00000000 x2:10000970 PA:10000984", "time": "22258", "Origin": "/scratch/digirols/pulp_api_example/main.c:91"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22259, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000af2", "instr": "lw x18, 16(x2) x18=00000000 x2:10000970 PA:10000980", "time": "22259", "Origin": "/scratch/digirols/pulp_api_example/main.c:91"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22260, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000af4", "instr": "addi x10, x0, 0 x10=00000000", "time": "22260", "Origin": "/scratch/digirols/pulp_api_example/main.c:91"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22261, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000af6", "instr": "addi x2, x2, 32 x2=10000990 x2:10000970", "time": "22261", "Origin": "/scratch/digirols/pulp_api_example/main.c:91"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 22262, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "main", "args":{"pc": "1c000af8", "instr": "jalr x0, x1, 0 x1:1c0000ec", "time": "22262", "Origin": "/scratch/digirols/pulp_api_example/main.c:91"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 22264, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000ec", "instr": "add x8, x0, x10 x8=00000000 x10:00000000", "time": "22264", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:122"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 22265, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "_entry", "args":{"pc": "1c0000ee", "instr": "jal x1, 3150 x1=1c0000f2", "time": "22265", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:125"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22267, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_deinit", "args":{"pc": "1c000d3c", "instr": "addi x2, x2, -16 x2=10000980 x2:10000990", "time": "22267", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:144"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22268, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_deinit", "args":{"pc": "1c000d3e", "instr": "sw x8, 8(x2) x8:00000000 x2:10000980 PA:10000988", "time": "22268", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:144"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22284, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_deinit", "args":{"pc": "1c000d40", "instr": "addi x10, x0, 1 x10=00000001", "time": "22284", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:148"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 22285, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_deinit", "args":{"pc": "1c000d42", "instr": "lui x8, 0x10000000 x8=10000000", "time": "22285", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:148"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22286, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_deinit", "args":{"pc": "1c000d46", "instr": "sw x1, 12(x2) x1:1c0000f2 x2:10000980 PA:1000098c", "time": "22286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:144"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22287, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_deinit", "args":{"pc": "1c000d48", "instr": "addi x8, x8, 392 x8=10000188 x8:10000000", "time": "22287", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:144"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 22288, "dur": 34, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_deinit", "args":{"pc": "1c000d4c", "instr": "jal x1, 242 x1=1c000d4e", "time": "22288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/init.c:148"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22322, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e3e", "instr": "addi x2, x2, -16 x2=10000970 x2:10000980", "time": "22322", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:72"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22339, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e40", "instr": "sw x8, 8(x2) x8:10000188 x2:10000970 PA:10000978", "time": "22339", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:72"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 22340, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e42", "instr": "lui x8, 0x10000000 x8=10000000", "time": "22340", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 22341, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e46", "instr": "slli x10, x10, 0x2 x10=00000004 x10:00000001", "time": "22341", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22342, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e48", "instr": "addi x8, x8, 88 x8=10000058 x8:10000000", "time": "22342", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22343, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e4c", "instr": "lw x8, x10(x8) x8=1c2fffd0 x10:00000004 x8:10000058 PA:1000005c", "time": "22343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:73"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22344, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e50", "instr": "sw x1, 12(x2) x1:1c000d4e x2:10000970 PA:1000097c", "time": "22344", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:72"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 22345, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e52", "instr": "bne x8, x0, 12 x8:1c2fffd0", "time": "22345", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:74"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22348, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e5e", "instr": "lw x15, 0(x8) x15=1c00179c x8:1c2fffd0 PA:1c2fffd0", "time": "22348", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 22362, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e60", "instr": "lw x10, 4(x8) x10=00000000 x8:1c2fffd0 PA:1c2fffd4", "time": "22362", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 22376, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_cbsys_exec", "args":{"pc": "1c000e62", "instr": "jalr x1, x15, 0 x1=1c000e64 x15:1c00179c", "time": "22376", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/utils.c:76"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 22382, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_io_stop", "args":{"pc": "1c00179c", "instr": "addi x2, x2, -16 x2=10000960 x2:10000970", "time": "22382", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:465"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 22383, "dur": 16, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:76"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 23204, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_wait_tx_done", "args":{"pc": "1c00209c", "instr": "beq x15, x0, -6 x15:00000000", "time": "23204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:76"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 23207, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_wait_tx_done", "args":{"pc": "1c002096", "instr": "lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014", "time": "23207", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:76"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 23225, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_0.log", "tid": "__rt_uart_wait_tx_done", "args":{"pc": "1c002098", "instr": "andi x15, x15, 64 x15=00000000 x15:00000000", "time": "23225", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/drivers/uart/uart-v0.c:76"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 81, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "_start", "args":{"pc": "1c000080", "instr": "jal x0, 24 ", "time": "81", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 104, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000001", "time": "104", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 105, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000001 x10:00000001", "time": "105", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 128, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000000 x10:00000001", "time": "128", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 129, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000001", "time": "129", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 130, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "130", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 151, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "151", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 152, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "152", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 153, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "153", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 154, "dur": 70, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000001", "time": "154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 224, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "224", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 225, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000001", "time": "225", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 226, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000001 x19:00000001", "time": "226", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 227, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 244, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 246, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 247, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "247", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 270, "dur": 9344, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "270", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9614, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080", "time": "9614", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 9622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "9622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 9623, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "9623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9641, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "9641", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 9642, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "9642", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9644, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080", "time": "9644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 9668, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000800 x19:00000001 x10:00000800", "time": "9668", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9669, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=100fcf90 x10:00000800 x5:100fc790", "time": "9669", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 9670, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "9670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9690, "dur": 9124, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "9690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18814, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18814", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18822, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18823, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18824, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18824", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18825, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18825", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18848, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000001", "time": "18848", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18868, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18868", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18869, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, 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"tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18872", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18873, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18873", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=100fcf50 x2:100fcf90", "time": "18875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18876, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "printf", 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19169", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19170, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19170", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19171, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19171", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19172, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000008 x15:00000001", "time": "19172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19173, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000004 x15:00000001", "time": "19173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19174, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008", "time": "19174", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19314", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19315, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19315", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19316, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19316", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19317, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19359, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19360, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19361, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19366", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19367, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19367", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19368, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19368", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19369, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000008 x15:00000001", "time": "19369", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19370, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000004 x15:00000001", "time": "19370", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19371, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008", "time": "19371", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19416", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19417, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19417", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19418, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19418", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19419, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000008 x15:00000001", "time": "19419", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000004 x15:00000001", "time": "19420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008", "time": "19421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19422, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80", "time": "19422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19423, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008", "time": "19423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19424, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19424", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19425, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104008", "time": "19425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19429, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19429", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19430, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19430", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19432, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19433, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19433", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19436, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19456, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19456", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19457, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19457", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19460, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19460", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19462, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19467", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19468, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19468", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19469, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19469", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19470, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19473, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80", "time": "19473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19474, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008", "time": "19474", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19475, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19519, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19520, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000008 x15:00000001", "time": "19520", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19521, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000004 x15:00000001", "time": "19521", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19522, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008", "time": "19522", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19523, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80", "time": "19523", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19524, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008", "time": "19524", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19525, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19525", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19526, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104008", "time": "19526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19530, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19530", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19531, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19531", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19533, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19533", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19534, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19534", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19537, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19537", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19562, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19562", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19563, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19563", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19566, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19566", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19567, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19567", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19568, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19568", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19570, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19570", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19571, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19571", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19573, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19573", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19574, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19574", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19575, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19575", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19576, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000008 x15:00000001", "time": "19576", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19577, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000004 x15:00000001", "time": "19577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19578, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008", "time": "19578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19579, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80", "time": "19579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19580, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008", "time": "19580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19581, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", 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"1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19613", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19615, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "19615", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19616, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19616", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19618, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19618", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19620, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19620", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19621, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000008 x15:00000001", "time": "19621", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000004 x15:00000001", "time": "19622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19623, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008", "time": "19623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19624, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80", "time": "19624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19625, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008", "time": "19625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19626, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19632", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19634, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "19634", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19635, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19635", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19638, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19638", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19652, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19652", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19653, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000072", "time": "19653", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19656, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000072 x20:00000025", "time": "19656", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19657, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19657", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19658, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19663", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19664, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000001", "time": "19664", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19665, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19665", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19666, "dur": 1, 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x12, 0x405 x11=00000000 x12:00000002", "time": "18869", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18870, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000", "time": "18870", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18871, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000002 x12:00000002", "time": "18871", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18872, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18872", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18873, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18873", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=100fd750 x2:100fd790", "time": "18875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18876, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000000 x2:100fd750 PA:100fd774", "time": "18876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18882, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18883, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000002 x2:100fd750 PA:100fd778", "time": "18883", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18884, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:100fd750 PA:100fd780", "time": "18904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:100fd750 PA:100fd784", "time": "18905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c00182c", "instr": "sw x16, 56(x2) x16:00000000 x2:100fd750 PA:100fd788", "time": "18906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18907, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:100fd750 PA:100fd78c", "time": "18907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18921, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c001830", "instr": "sw x13, 12(x2) x13:100fd774 x2:100fd750 PA:100fd75c", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18923, "dur": 17, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19265, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19265", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19266, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19266", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19267, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19272", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19273, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19273", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19274, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19274", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19275, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000010 x15:00000002", "time": "19275", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19276, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000008 x15:00000002", "time": "19276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19277, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010", "time": "19277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19278, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80", "time": "19278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19279, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19280, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19280", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19281, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104010", "time": "19281", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19285, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19285", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19286, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19288, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "19288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19289, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19289", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19292, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "19292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19306, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "19306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19307, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19307", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19310, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19310", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19311, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19311", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19312, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19312", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19314, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19314", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19315, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19315", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19317, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19317", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19318, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19318", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19319, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19319", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19320, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000010 x15:00000002", "time": "19320", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19321, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000008 x15:00000002", "time": "19321", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19322, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010", "time": "19322", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19369", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19370, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19370", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19371, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19371", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19372, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000010 x15:00000002", "time": "19372", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000008 x15:00000002", "time": "19373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010", "time": "19374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19375, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80", "time": "19375", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19376, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010", "time": "19376", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19377, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", 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19389, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19408, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19409, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19409", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19412, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19413, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19413", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19414, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19419", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19422, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19425, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80", "time": "19425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19426, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010", "time": "19426", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19427, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19427", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19428, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104010", "time": "19428", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19432, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19433, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19433", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19435, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19435", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19436, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19439, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19458, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19458", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19459, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19459", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19462", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19463, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19463", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19464, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19464", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19466, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19466", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19467, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19467", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19469, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19469", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19470, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19470", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19471, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19471", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19472, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000010 x15:00000002", "time": "19472", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19473, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000008 x15:00000002", "time": "19473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19474, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010", "time": "19474", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19475, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80", "time": "19475", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19476, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010", "time": "19476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19477, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19478, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104010", "time": "19478", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19482, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19482", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19483, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19483", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19485, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19485", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19486, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19486", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19489, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19489", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19507, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19507", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19508, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19508", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19511, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19512, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19513, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19515, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19515", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19516, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19516", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19519, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19520, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19520", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19521, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000010 x15:00000002", "time": "19521", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19522, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000008 x15:00000002", "time": "19522", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19523, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010", "time": "19523", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19576", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19577, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19578, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19579, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000010 x15:00000002", "time": "19579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19580, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000008 x15:00000002", "time": "19580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19581, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010", "time": "19581", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19582, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80", "time": "19582", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19583, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010", "time": "19583", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19584, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19590", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19592, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19592", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19593, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19593", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19596, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19596", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19611, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19611", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19612, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19612", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19615, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19615", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19616, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19616", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19617, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19623, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19624, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19625, "dur": 1, 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19669", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19670, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000002", "time": "19670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19671, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19671", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19672, "dur": 1, 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"jalr", "ph": "X", "ts": 21651, "dur": 10, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_2.log", "tid": "printf", "args":{"pc": "1c00183a", "instr": "jalr x0, x1, 0 x1:1c00220c", "time": "21651", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 85, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "_start", "args":{"pc": "1c000080", "instr": "jal x0, 24 ", "time": "85", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 110, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000003", "time": "110", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 111, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000003 x10:00000003", "time": "111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000000 x10:00000003", "time": "133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000003", "time": "134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 135, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 158, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "158", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 159, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "159", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 160, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "160", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 161, "dur": 68, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000003", "time": "161", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 229, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "229", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000003", "time": "230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 231, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000003 x19:00000003", "time": "231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 232, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 251, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "251", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 252, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "252", "Origin": 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"1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "274", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9614, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080", "time": "9614", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 9622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "9622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 9623, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "9623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9641, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "9641", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 9642, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "9642", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19174, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19174", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19175, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19175", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19176, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19176", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19177, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19177", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19178, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19178", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19187", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19189, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233e x9:1c00233e", "time": "19189", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19190, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19190", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19225, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19225", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19226, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19226", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19227, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19229, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000079 x11:00000079", "time": "19229", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19230, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19235, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19236, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19236", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19237, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19238, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80", "time": "19238", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018", "time": "19239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19241, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104018", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19246, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19248, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19248", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19249, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19249", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19252, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19252", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19269, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19269", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19270, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19270", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19273, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19273", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19274, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19274", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19275, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19275", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19277, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19278, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19280, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19280", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19281, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19281", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19282, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19282", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19283, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19283", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19284, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19284", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19285, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19285", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19330, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19330", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19331, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19331", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19334, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19334", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19372, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19372", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19374, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19379", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19380, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19380", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19381, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19381", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19382, "dur": 1, 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19395, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "19395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19396, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19422, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19423, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19425, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000027 x11:00000027", "time": "19425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19426, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19426", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19428, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19428", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19429, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19429", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19430, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19430", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19431", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19432, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19433, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19433", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19434, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80", "time": "19434", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19435, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018", "time": "19435", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19436, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19437, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104018", "time": "19437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19441, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19441", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19442, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19442", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19444, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19445, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19445", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19448, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19448", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19467, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19467", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19468, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19468", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19471, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19471", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19472, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19472", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19473, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19475, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19475", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19476, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19478, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19478", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19479, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19479", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19480, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19480", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19481, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19481", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19482, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19482", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19483, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19483", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19523", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19524, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19524", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19525, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19525", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19526, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19527, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19527", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19528, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19528", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19529, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80", "time": "19529", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19530, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018", "time": "19530", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19531, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19537", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19539, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19539", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19540, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19540", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19543, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19543", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19572, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19572", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19573, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19573", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19583", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19584, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19584", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19585, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19585", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19586, "dur": 1, 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19628", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19629, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000003", "time": "19629", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19630, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19630", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19631, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000018 x15:00000003", "time": "19631", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19632, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000000c x15:00000003", "time": "19632", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19633, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018", "time": "19633", "Origin": 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x12, 0x405 x11=00000000 x12:00000004", "time": "18869", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18870, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000", "time": "18870", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18871, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000004 x12:00000004", "time": "18871", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18872, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18872", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18873, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18873", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=100fe750 x2:100fe790", "time": "18875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18876, "dur": 7, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000000 x2:100fe750 PA:100fe774", "time": "18876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18883, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "18883", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18884, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000004 x2:100fe750 PA:100fe778", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18885, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19186, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "19186", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19187, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19187", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19188, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19193", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19194, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19194", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19195, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19195", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19196, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19196", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19197, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19197", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19198, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19198", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19199, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80", "time": "19199", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19200, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020", "time": "19200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19201, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19207", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19209, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233e x9:1c00233e", "time": "19209", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19210, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19210", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19213, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "19213", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "19232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19233, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000079", "time": "19233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19236, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19236", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19237, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19238, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19238", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000079 x11:00000079", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19241, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19243, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19244, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19246, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19247, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19247", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19248, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19248", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19259, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19260, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19260", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19283, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19283", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19284, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19284", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19285, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19285", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19287, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19287", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19288, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19290, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19290", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19291, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19291", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19292, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19293, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19294, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19295, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19295", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19296, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80", "time": "19296", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19297, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020", "time": "19297", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19298, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19298", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19299, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104020", "time": "19299", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19303, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19303", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19304, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19304", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19306, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "19306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19307, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19307", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19310, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "19310", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19329, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "19329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19330, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19330", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19334, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19335, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19335", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19338, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19338", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19340, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19340", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19341, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19341", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19342, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19342", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19343, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19344, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19344", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19345, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19345", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80", "time": "19346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19347, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020", "time": "19347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19348, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19348", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19349, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104020", "time": "19349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19353, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19353", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19354, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19354", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19356, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "19356", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19357, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19357", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19387, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19387", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19388, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19388", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19389, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19391, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "19391", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19392, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19394, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19395, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19396, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19397, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19398, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19398", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19399, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19399", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19400, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80", "time": "19400", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19401, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020", "time": "19401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19403, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104020", "time": "19403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19407, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19407", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19408, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19410, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "19410", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19411, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19411", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19414, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19414", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19433, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19433", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19434, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19434", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19437, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19438, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19438", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19439, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19441, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000027 x11:00000027", "time": "19441", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19442, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19442", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19444, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19445, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19445", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19446, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19446", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19447, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19447", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19448, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19448", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19449, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19449", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19450, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80", "time": "19450", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19451, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020", "time": "19451", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19452, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19452", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19453, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104020", "time": "19453", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19457, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19457", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19458, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19458", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19460, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19460", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19461, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19464, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19464", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19486, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19486", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19487, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19487", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19490, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19490", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19491, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19491", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19492, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19492", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19494, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19494", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19495, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19495", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19497, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19497", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19498, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19498", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19499, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19499", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19500, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19500", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19501, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19501", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19502, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19502", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19503, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80", "time": "19503", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19504, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020", "time": "19504", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19505, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19505", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19506, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104020", "time": "19506", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19510, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19510", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19511, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19513, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19514, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19514", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19517, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19532, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19532", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19533, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19533", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19536, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19536", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19537, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19537", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19538, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19543", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19544, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19544", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19545, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19545", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19546, "dur": 1, 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19595", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19596, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19596", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19597, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19597", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19598, "dur": 1, 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19688", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19689, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000004", "time": "19689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19690, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19691, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000020 x15:00000004", "time": "19691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19692, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000010 x15:00000004", "time": "19692", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19693, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020", "time": "19693", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "printf", "args":{"pc": "1c001834", "instr": "lw x1, 28(x2) x1=1c00220c x2:100fe750 PA:100fe76c", "time": "21640", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21641, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "printf", "args":{"pc": "1c001836", "instr": "addi x10, x0, 0 x10=00000000", "time": "21641", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21642, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_4.log", "tid": "printf", "args":{"pc": "1c001838", "instr": "addi x2, x2, 64 x2=100fe790 x2:100fe750", "time": "21642", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "jalr", "cat": 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"cat": "andi", "ph": "X", "ts": 117, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000005 x10:00000005", "time": "117", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 139, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000000 x10:00000005", "time": "139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 140, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000005", "time": "140", "Origin": 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"time": "165", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 166, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "166", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 167, "dur": 67, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000005", "time": "167", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 235, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000005", "time": "235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 236, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000005 x19:00000005", "time": "236", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 237, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 256, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "256", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 257, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 258, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "258", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 259, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 279, "dur": 9335, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9614, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080", "time": "9614", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 9622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "9622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 9623, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "9623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9641, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "9641", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 9642, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "9642", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9644, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080", "time": "9644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 9668, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00002800 x19:00000005 x10:00000800", "time": "9668", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9669, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18814, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18814", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18822, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18823, "dur": 1, "pid": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19086", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19087, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19087", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19088, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19088", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19106, "dur": 1, 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19139, "dur": 31, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19170, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233e x12:1c00233d", "time": "19170", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19171, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19171", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19181", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19182, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19182", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19183, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19183", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19184, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19184", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19185, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19185", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19186, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19186", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19195", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19197, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233e x9:1c00233e", "time": "19197", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19198, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19198", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19201, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "19201", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19222, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "19222", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19223, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000079", "time": "19223", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19226, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19226", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19227, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19228, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19228", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000079 x11:00000079", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19231, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19235, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19236, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19236", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19237, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19238, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19238", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80", "time": "19239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19242, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104028", "time": "19242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19246, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19247, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19247", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19249, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19249", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19250, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19250", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19253, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19271, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19271", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19272, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19272", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19275, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19275", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19276, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19277, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19279, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19280, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19280", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19282, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19282", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19283, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19283", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19284, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19284", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19285, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19285", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19286, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19287, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19287", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19288, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80", "time": "19288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19289, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028", "time": "19289", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19290, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19296", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19298, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "19298", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19299, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19299", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19324, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19325, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19325", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19327, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19327", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19328, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19328", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19330, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19330", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19331, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19331", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19334, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19335, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19335", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19336, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80", "time": "19336", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028", "time": "19337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19338, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19338", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19339, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104028", "time": "19339", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19343, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19344, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19344", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "19346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19347, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19350, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "19350", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19369, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "19369", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19370, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "19370", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19375, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19375", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19377, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "19377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19378, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19378", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19380, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19380", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19381, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19381", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19382, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19382", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19383, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19383", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19384, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19384", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19385, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19385", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19386, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80", "time": "19386", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19387, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028", "time": "19387", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19388, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19388", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19389, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104028", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19394, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19396, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19397, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19423, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19424, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19424", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19425, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19427, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000027 x11:00000027", "time": "19427", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19428, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19428", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19430, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19430", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19431", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19432, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19433, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19433", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19434, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19434", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19435, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19435", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19436, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80", "time": "19436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19437, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028", "time": "19437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19438, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19438", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19439, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104028", "time": "19439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19443, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19443", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19444, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19446, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19446", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19447, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19447", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19450, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19450", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19475, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19475", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19476, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19479, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19479", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19480, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19480", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19481, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19486", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19487, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19487", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19488, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19488", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19489, "dur": 1, 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19533", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19534, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19534", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19535, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19535", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19536, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19536", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19537, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19537", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19538, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19538", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19539, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80", "time": "19539", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19540, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028", "time": "19540", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19541, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19630", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19631, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "19631", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19632, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19632", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19633, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000028 x15:00000005", "time": "19633", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19634, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000014 x15:00000005", "time": "19634", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19635, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028", "time": "19635", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "21603", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 21604, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000005", "time": "21604", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21605, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "21605", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 21606, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 21609, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80", "time": "21609", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21610, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028", "time": "21610", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 21611, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "21617", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002354 x9:1c002354", "time": "21619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21620, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21620", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21623, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354", "time": "21623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21637, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002355 x12:1c002354", "time": "21637", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 21638, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000000", "time": "21638", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21639, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba8", "instr": "lw x1, 92(x2) x1=1c001834 x2:100feef0 PA:100fef4c", "time": "21639", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21640, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001baa", "instr": "lw x8, 88(x2) x8=00000000 x2:100feef0 PA:100fef48", "time": "21640", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21641, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bb2", "instr": "lw x20, 72(x2) x20=1c00220c x2:100feef0 PA:100fef38", "time": "21644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21645, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bb4", "instr": "lw x21, 68(x2) x21=1c002210 x2:100feef0 PA:100fef34", "time": "21645", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bb6", "instr": "lw x22, 64(x2) x22=00000000 x2:100feef0 PA:100fef30", "time": "21646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21647, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bb8", "instr": "lw x23, 60(x2) x23=00000000 x2:100feef0 PA:100fef2c", "time": "21647", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21648, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bba", "instr": "lw x24, 56(x2) x24=00000000 x2:100feef0 PA:100fef28", "time": "21648", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21649, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bbc", "instr": "lw x25, 52(x2) x25=00000000 x2:100feef0 PA:100fef24", "time": "21649", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21650, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bbe", "instr": "addi x2, x2, 96 x2=100fef50 x2:100feef0", "time": "21650", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21651, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc0", "instr": "jalr x0, x1, 0 x1:1c001834", "time": "21651", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:440"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21653, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "printf", "args":{"pc": "1c001834", "instr": "lw x1, 28(x2) x1=1c00220c x2:100fef50 PA:100fef6c", "time": "21653", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21654, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "printf", "args":{"pc": "1c001836", "instr": "addi x10, x0, 0 x10=00000000", "time": "21654", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21655, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "printf", "args":{"pc": "1c001838", "instr": "addi x2, x2, 64 x2=100fef90 x2:100fef50", "time": "21655", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21656, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_5.log", "tid": "printf", "args":{"pc": "1c00183a", "instr": "jalr x0, x1, 0 x1:1c00220c", "time": "21656", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 95, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "_start", "args":{"pc": "1c000080", "instr": "jal x0, 24 ", "time": "95", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 119, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000006", "time": "119", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 120, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000006 x10:00000006", "time": "120", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 143, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000000 x10:00000006", "time": "143", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 144, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000006", "time": "144", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 145, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "145", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 166, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "166", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 167, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "167", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 168, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "168", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 169, "dur": 68, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000006", "time": "169", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 237, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 238, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000006", "time": "238", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000006 x19:00000006", "time": "239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 240, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 259, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 260, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "260", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 261, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "261", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 262, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "262", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 283, "dur": 9331, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "283", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9614, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080", "time": "9614", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 9622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "9622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 9623, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "9623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9641, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "9641", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 9642, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "9642", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9644, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080", "time": "9644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 9668, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00003000 x19:00000006 x10:00000800", "time": "9668", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 9669, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=100ff790 x10:00003000 x5:100fc790", "time": "9669", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 9670, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "9670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 9690, "dur": 9124, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "9690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18814, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18814", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18822, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18823, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18824, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18824", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18825, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18825", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18848, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000006", "time": "18848", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18868, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18868", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18869, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000000 x12:00000006", "time": "18869", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18870, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000", "time": "18870", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18871, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000006 x12:00000006", "time": "18871", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18872, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18872", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18873, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18873", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=100ff750 x2:100ff790", "time": "18875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18876, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000000 x2:100ff750 PA:100ff774", "time": "18876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18878, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "18878", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18879, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000006 x2:100ff750 PA:100ff778", "time": "18879", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c00181a", "instr": "sw x13, 44(x2) x13:00000000 x2:100ff750 PA:100ff77c", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c00181c", "instr": "add x12, x0, x10 x12=1c00233c x10:1c00233c", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18882, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=100ff774 x2:100ff750", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18897, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "18897", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18898, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "18898", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18899, "dur": 7, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:100ff750 PA:100ff76c", "time": "18899", "Origin": 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56(x2) x16:00000000 x2:100ff750 PA:100ff788", "time": "18908", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18909, "dur": 12, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:100ff750 PA:100ff78c", "time": "18909", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18921, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "printf", "args":{"pc": "1c001830", "instr": "sw x13, 12(x2) x13:100ff774 x2:100ff750 PA:100ff75c", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18927, "dur": 13, "pid": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19117", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19135, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233d x9:1c00233d", "time": "19135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19136, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19136", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19139, "dur": 33, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19172, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233e x12:1c00233d", "time": "19172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19173, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19176, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "19176", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19177, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19177", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19178, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19178", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19180, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000065 x11:00000065", "time": "19180", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19181, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19181", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19183, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19183", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19184, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000006", "time": "19184", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19185, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19185", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19186, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000030 x15:00000006", "time": "19186", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19187, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000018 x15:00000006", "time": "19187", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19188, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030", "time": "19188", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19189, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80", "time": "19189", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19190, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030", "time": "19190", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19191, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19191", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19192, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104030", "time": "19192", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19196, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19196", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19197, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19197", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19199, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233e x9:1c00233e", "time": "19199", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19200, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19203, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "19203", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19228, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "19228", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19229, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000079", "time": "19229", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19234, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19236, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000079 x11:00000079", "time": "19236", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19237, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000006", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19242, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000030 x15:00000006", "time": "19242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19243, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000018 x15:00000006", "time": "19243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19244, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030", "time": "19244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80", "time": "19245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19246, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19247, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19247", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19248, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104030", "time": "19248", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19252, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19252", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19253, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19255, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19255", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19256, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19256", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19259, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19275, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19275", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19276, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19279, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19280, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19280", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19281, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19281", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19283, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19283", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19284, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19284", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19286, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19287, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000006", "time": "19287", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19288, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19289, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000030 x15:00000006", "time": "19289", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19290, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000018 x15:00000006", "time": "19290", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19291, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030", "time": "19291", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19292, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80", "time": "19292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19293, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030", "time": "19293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19294, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19295, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104030", "time": "19295", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19299, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19299", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19300, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19300", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19302, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "19302", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19303, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19303", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19306, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "19306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "19323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19324, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19327, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19327", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19328, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19328", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19329, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19331, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19331", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19332, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19334, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19335, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000006", "time": "19335", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19336, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19336", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000030 x15:00000006", "time": "19337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19338, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000018 x15:00000006", "time": "19338", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19339, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030", "time": "19339", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19340, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80", "time": "19340", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19341, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030", "time": "19341", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19342, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19348", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19350, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "19350", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19351, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19379, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19379", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19380, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19380", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19381, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19381", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19383, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "19383", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19384, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19384", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19386, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19386", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19387, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000006", "time": "19387", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19388, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19388", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000030 x15:00000006", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19390, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000018 x15:00000006", "time": "19390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19391, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030", "time": "19391", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19392, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80", "time": "19392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19394, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19395, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104030", "time": "19395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19399, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19399", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19400, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19400", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "19402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19403, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19406, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19406", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19425, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19425", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19426, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19426", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19429, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19429", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19430, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19430", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19431, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19437, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000006", "time": "19437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19438, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19438", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19439, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000030 x15:00000006", "time": "19439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19440, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000018 x15:00000006", "time": "19440", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19441, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030", "time": "19441", "Origin": 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"args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19445, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104030", "time": "19445", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19449, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19449", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19450, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19450", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19452, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19452", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19453, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19453", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19481, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19481", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19482, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19482", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19483, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19488", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19489, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000006", "time": "19489", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19490, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19490", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19491, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000030 x15:00000006", "time": "19491", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19492, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000018 x15:00000006", "time": "19492", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19493, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030", "time": "19493", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19494, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80", "time": "19494", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19495, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030", "time": "19495", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19496, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19496", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19497, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104030", "time": "19497", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19501, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19501", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19502, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19502", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19504, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19504", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19505, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19505", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19508, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19508", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19525, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19525", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19526, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19526", "Origin": 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"cat": "sw", "ph": "X", "ts": 18942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b74", "instr": "sw x8, 88(x2) x8:00000000 x2:100ffef0 PA:100fff48", "time": "18942", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b76", "instr": "sw x18, 80(x2) x18:1b204000 x2:100ffef0 PA:100fff40", "time": "18943", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b78", "instr": "sw x19, 76(x2) x19:00000007 x2:100ffef0 PA:100fff3c", "time": "18944", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18945, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b7a", "instr": "sw x20, 72(x2) x20:1c00220c x2:100ffef0 PA:100fff38", "time": "18945", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18946, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b7c", "instr": "sw x21, 68(x2) x21:1c002210 x2:100ffef0 PA:100fff34", "time": "18946", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18947, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", 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19139, "dur": 41, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19180, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233e x12:1c00233d", "time": "19180", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19181, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19181", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19191", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19192, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19192", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19193, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19193", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19194, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19197, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "19197", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19198, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "19198", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19199, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19199", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19200, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104038", "time": "19200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19204, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19205, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19205", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19207, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233e x9:1c00233e", "time": "19207", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19208, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19208", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19211, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "19211", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19231, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000079", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19235, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19236, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19236", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19238, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000079 x11:00000079", "time": "19238", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19239, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19242, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19243, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19244, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19246, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19247, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "19247", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19248, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "19248", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19249, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19249", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19250, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104038", "time": "19250", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19254, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19255, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19255", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19257, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19258, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19258", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19261, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19261", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19277, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19278, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19281, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19281", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19282, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19282", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19283, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19283", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19285, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19285", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19286, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19288, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19289, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19289", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19290, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19290", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19291, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19291", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19292, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19293, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19294, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "19294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19295, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "19295", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19296, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19296", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19297, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104038", "time": "19297", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19301, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19301", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19302, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19302", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19304, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "19304", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19305, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19305", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19329, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19330, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19330", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19331, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19331", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19334, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19336, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19336", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19338, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19338", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19339, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19339", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19340, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19340", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19341, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19341", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19342, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "19342", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19343, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "19343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19344, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19344", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19345, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104038", "time": "19345", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19349, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19350, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19350", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19352, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "19352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19353, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19353", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19356, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "19356", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19377, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "19377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19378, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "19378", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19381, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19381", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19382, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19382", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19383, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19388", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19390, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19391, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19391", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19392, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19393", "Origin": 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"args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19397, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104038", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19401, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19402, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19404, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "19404", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19405, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19431", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19432, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19433, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19433", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19435, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000027 x11:00000027", "time": "19435", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19436, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19438, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19438", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19439, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19440, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19440", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19441, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19441", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19442, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19442", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19443, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19443", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19444, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "19444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19445, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "19445", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19446, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19446", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19447, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104038", "time": "19447", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19451, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19451", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19452, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19452", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19454, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19454", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19455, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19455", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19458, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19458", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19479, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19479", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19480, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19480", "Origin": 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19510, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19510", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19526, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19527, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19527", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19537", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19538, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19538", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19539, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19539", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19540, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19540", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19541, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19541", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19542, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19542", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19543, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "19543", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19544, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "19544", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19545, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19545", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19546, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104038", "time": "19546", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19550, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19550", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19551, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19551", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19553, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19553", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19554, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19554", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19777", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19778, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19778", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19779, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19779", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19780, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19781, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19781", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19782, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19782", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19783, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "19783", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19784, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "19784", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19785, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19785", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19786, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104038", "time": "19786", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19790, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19790", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19791, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19791", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19793, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00234a x9:1c00234a", "time": "19793", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19794, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19794", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19797, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a", "time": "19797", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19811, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234b x12:1c00234a", "time": "19811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19812, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000028", "time": "19812", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19815, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000028 x20:00000025", "time": "19815", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19816, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19816", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19817, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19817", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19819, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000028 x11:00000028", "time": "19819", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19820, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19820", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19822, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19823, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "19823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19824, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19824", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19825, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000038 x15:00000007", "time": "19825", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19826, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000001c x15:00000007", "time": "19826", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19827, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038", "time": "19827", "Origin": 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"tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "21553", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 21554, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000007", "time": "21554", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21555, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "21555", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 21556, "dur": 1, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 21559, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80", "time": "21559", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21560, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038", "time": "21560", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 21561, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "21567", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21569, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002353 x9:1c002353", "time": "21569", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21570, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21570", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21573, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353", "time": "21573", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21588, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002354 x12:1c002353", "time": "21588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 21589, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000000a", "time": "21589", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21592, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000000a x20:00000025", "time": "21592", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21593, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "21593", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21594, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "21594", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21596, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000000a x11:0000000a", "time": "21596", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21597, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "21597", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 21599, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_00_7.log", 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"time": "17804", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:170"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17805, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "__rt_master_loop_no_slave", "args":{"pc": "1c0021ca", "instr": "bne x8, x9, 6 x8:1b000028 x9:1b000048", "time": "17805", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:171"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17808, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "__rt_master_no_reset", "args":{"pc": "1c0021d0", "instr": "jalr x0, x5, 0 x5:1c0009d8", "time": "17808", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:176"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17826, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "cluster_entry", "args":{"pc": "1c0009d8", "instr": "addi x2, x2, -16 x2=104fe3f0 x2:104fe400", "time": "17826", "Origin": "/scratch/digirols/pulp_api_example/main.c:52"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17827, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "eu_dispatch_team_config", "args":{"pc": "1c0009da", "instr": "addi x14, x0, 255 x14=000000ff", "time": "17827", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:419"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17844, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "eu_dispatch_team_config", "args":{"pc": "1c0009de", "instr": "lui x15, 0x1b204000 x15=1b204000", "time": "17844", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:419"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17845, "dur": 1, "pid": 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"tid": "eu_dispatch_push", "args":{"pc": "1c0009f8", "instr": "lui x15, 0x1c001000 x15=1c001000", "time": "17869", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:414"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17870, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "eu_dispatch_push", "args":{"pc": "1c0009fc", "instr": "addi x15, x15, -1604 x15=1c0009bc x15:1c001000", "time": "17870", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:414"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17887, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "eu_dispatch_push", "args":{"pc": "1c000a00", "instr": "lui x14, 0x1b204000 x14=1b204000", "time": "17887", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:414"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17888, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "eu_dispatch_push", "args":{"pc": "1c000a04", "instr": "sw x15, 128(x14) x15:1c0009bc x14:1b204000 PA:1b204080", "time": "17888", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:414"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17889, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "eu_dispatch_push", "args":{"pc": "1c000a08", "instr": "lui x15, 0x1b204000 x15=1b204000", "time": "17889", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:414"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17890, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "eu_dispatch_push", "args":{"pc": "1c000a0c", "instr": "sw x10, 128(x15) x10:00000000 x15:1b204000 PA:1b204080", "time": "17890", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:414"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17907, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "hal_cluster_id", "args":{"pc": "1c000a10", "instr": "csrrs x12, x0, 0xf14 x12=00000020", "time": "17907", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 17908, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "hal_cluster_id", "args":{"pc": "1c000a14", "instr": "srai x8, x12, 0x405 x8=00000001 x12:00000020", "time": "17908", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17909, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "hal_cluster_id", "args":{"pc": "1c000a18", "instr": "p.bclr x8, x8, 25, 6 x8=00000001 x8:00000001", "time": "17909", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17910, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "core_entry", "args":{"pc": "1c000a1c", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17910", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "core_entry", "args":{"pc": "1c000a20", "instr": "p.bclr x12, x12, 26, 5 x12=00000000 x12:00000020", "time": "17931", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "add", "cat": "add", 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"X", "ts": 18608, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18608", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18611, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "18611", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18626, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "18626", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000", "time": "18690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18691, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18692, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104080", "time": "18692", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18696, "dur": 1, "pid": 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"X", "ts": 18700, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18703, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "18703", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "18719", "Origin": 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x10, x0, x18 x10=00000000 x18:00000000", "time": "18724", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18725, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18727, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000072 x11:00000072", "time": "18727", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18728, "dur": 2, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 12625, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000001", "time": "12625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12626, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "12626", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12644, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "12644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12645, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "12645", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "12646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 12647, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000001", "time": "12647", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "12699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12700, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000021", "time": "12700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000001 x19:00000021", "time": "12701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12702, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "12702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "12719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "12720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "12721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12722, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "12722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 12742, "dur": 5050, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "12742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17792, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "17792", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17810, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "17810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17811, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "17811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17829, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "17829", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17830, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "17830", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17832, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080", "time": "17832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17856, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000400 x19:00000001 x10:00000400", "time": "17856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=104fe800 x10:00000400 x5:104fe400", "time": "17857", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17858, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "17858", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17860, "dur": 36, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "17860", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17896, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "17896", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "17904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "17905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "17906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "17907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17925, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000021", "time": "17925", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17942", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": 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"X", "ts": 18444, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18447, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "18447", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "18461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18462, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "18462", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18465, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "18465", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18466, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18470", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18472, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18472", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18473, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000021", "time": "18473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18474, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18474", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18475, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000108 x15:00000021", "time": "18475", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18476, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000084 x15:00000021", "time": "18476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18477, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108", "time": "18477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18478, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80", "time": "18478", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18479, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008", "time": "18479", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18480, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18480", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18481, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104088", "time": "18481", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18485, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18485", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18486, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18486", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18488, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "18488", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18489, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18489", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18492, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "18492", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18508, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "18508", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18509, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "18509", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18512, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "18512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18513, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18514, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18514", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18516, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "18516", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18517, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18519, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18520, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000021", "time": "18520", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18524, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108", "time": "18524", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18525, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80", "time": "18525", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18526, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008", "time": "18526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18527, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18527", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18528, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104088", "time": "18528", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18532, "dur": 1, "pid": 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"X", "ts": 18536, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18536", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18539, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "18539", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18553, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "18553", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18569, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108", "time": "18569", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18570, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80", "time": "18570", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18571, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008", "time": "18571", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18572, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18572", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18573, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104088", "time": "18573", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18577, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18578, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18580, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "18580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18581, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18581", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18584, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "18584", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18599, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "18599", "Origin": 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x10, x0, x18 x10=00000000 x18:00000000", "time": "18604", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18605, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18605", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18607, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "18607", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18608, "dur": 2, "pid": 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"X", "ts": 18721, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18724, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "18724", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18738, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "18738", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18747", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18749, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18749", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18750, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000021", "time": "18750", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18751, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18751", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18752, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000108 x15:00000021", "time": "18752", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18753, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000084 x15:00000021", "time": "18753", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18754, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108", "time": "18754", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18755, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80", "time": "18755", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18756, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008", "time": "18756", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18757, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18757", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18758, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104088", "time": "18758", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18762, "dur": 1, "pid": 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"X", "ts": 18766, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18766", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18769, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "18769", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18791, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "18791", "Origin": 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"instr": "jal x0, 24 ", "time": "12588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12606, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000022", "time": "12606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12607, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000002 x10:00000022", "time": "12607", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 12624, "dur": 1, "pid": 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"X", "ts": 12644, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "12644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12645, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "12645", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "12646", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12722, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "12722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 12742, "dur": 5050, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "12742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17792, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "17792", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17810, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "17810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17811, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "17811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17829, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "17829", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17830, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "17830", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17832, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080", "time": "17832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17856, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000800 x19:00000002 x10:00000400", "time": "17856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=104fec00 x10:00000800 x5:104fe400", "time": "17857", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17858, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "17858", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17860, "dur": 36, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "17860", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17896, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "17896", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "17904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "17905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "17906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "17907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17925, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000022", "time": "17925", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17942", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 17943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000001 x12:00000022", "time": "17943", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001", "time": "17944", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17945, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000002 x12:00000022", "time": "17945", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17946, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "17946", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17947, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "17947", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=104febc0 x2:104fec00", "time": "17965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17966, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000001 x2:104febc0 PA:104febe4", "time": "17966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "17971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000002 x2:104febc0 PA:104febe8", "time": "17972", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c00181a", "instr": "sw x13, 44(x2) x13:00000000 x2:104febc0 PA:104febec", "time": "17973", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c00181c", "instr": "add x12, x0, x10 x12=1c00233c x10:1c00233c", "time": "17974", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17975, "dur": 12, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=104febe4 x2:104febc0", "time": "17975", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "17987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17988, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "17988", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17989, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:104febc0 PA:104febdc", "time": "17989", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17994, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:104febc0 PA:104febf0", "time": "17994", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17995, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:104febc0 PA:104febf4", "time": "17995", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17996, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c00182c", "instr": "sw x16, 56(x2) x16:00000000 x2:104febc0 PA:104febf8", "time": "17996", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17997, "dur": 12, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:104febc0 PA:104febfc", "time": "17997", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18009, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001830", "instr": "sw x13, 12(x2) x13:104febe4 x2:104febc0 PA:104febcc", "time": "18009", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18013, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "printf", "args":{"pc": "1c001832", "instr": "jal x1, 830 x1=1c001834", "time": "18013", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18028, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001b70", "instr": "addi x2, x2, -96 x2=104feb60 x2:104febc0", "time": "18028", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "addi", 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"X", "ts": 18452, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18452", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18455, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "18455", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18469, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "18469", "Origin": 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"ph": "X", "ts": 18482, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18482", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18483, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000110 x15:00000022", "time": "18483", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18484, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000088 x15:00000022", "time": "18484", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18523", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18525, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18525", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18526, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000022", "time": "18526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18527, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18527", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18528, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000110 x15:00000022", "time": "18528", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18529, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000088 x15:00000022", "time": "18529", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18530, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110", "time": "18530", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18531, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80", "time": "18531", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18532, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010", "time": "18532", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18533, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18533", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18534, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104090", "time": "18534", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18538, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18538", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18539, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18539", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18541, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "18541", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18542, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18542", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18545, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "18545", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18560, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "18560", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18561, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "18561", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18564, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "18564", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18565, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18565", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18566, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18566", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18568, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "18568", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18569, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18569", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18571, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18571", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18572, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000022", "time": "18572", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18576, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110", "time": "18576", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18577, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80", "time": "18577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18578, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010", "time": "18578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18579, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18580, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104090", "time": "18580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18584, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18584", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18585, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18585", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18587, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "18587", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18588, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18591, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "18591", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18605, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "18605", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18606, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "18606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18609, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "18609", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18610, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18614", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18616, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18616", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18617, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000022", "time": "18617", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18618, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18618", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000110 x15:00000022", "time": "18619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18620, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000088 x15:00000022", "time": "18620", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18621, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110", "time": "18621", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80", "time": "18622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18623, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010", "time": "18623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18624, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18625, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104090", "time": "18625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18629, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18629", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18630, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18630", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18632, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "18632", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18633, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18633", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18636, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "18636", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18654, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "18654", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18655, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "18655", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18658, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "18658", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18659, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18659", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18660, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18660", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18662, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "18662", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18663, "dur": 2, "pid": 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"ph": "X", "ts": 18667, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18667", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18668, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000110 x15:00000022", "time": "18668", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18669, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000088 x15:00000022", "time": "18669", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010", "time": "18719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18721, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104090", "time": "18721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18725, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18726, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18726", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18728, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "18728", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18729, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18729", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18732, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "18732", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18746, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "18746", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18747, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "18747", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18750, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "18750", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18751, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"instr": "jal x0, 24 ", "time": "12588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12606, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000023", "time": "12606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12607, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000003 x10:00000023", "time": "12607", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 12624, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000001 x10:00000023", "time": "12624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 12625, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000003", "time": "12625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12626, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "12626", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12644, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "12644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12645, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "12645", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "12646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 12647, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000003", "time": "12647", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "12699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12700, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000023", "time": "12700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000003 x19:00000023", "time": "12701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12702, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "12702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "12719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "12720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "12721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12722, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "12722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 12742, "dur": 5050, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "12742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17792, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "17792", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17810, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "17810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17811, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "17811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17829, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "17829", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17830, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "17830", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17832, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080", "time": "17832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17856, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000c00 x19:00000003 x10:00000400", "time": "17856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=104ff000 x10:00000c00 x5:104fe400", "time": "17857", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17858, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "17858", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17860, "dur": 36, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "17860", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17896, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "17896", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "17904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "17905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "17906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "17907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17925, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000023", "time": "17925", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17942", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 17943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000001 x12:00000023", "time": "17943", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001", "time": "17944", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": 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"X", "ts": 18456, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18456", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18459, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "18459", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18473, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "18473", "Origin": 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"ph": "X", "ts": 18486, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18486", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18487, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000118 x15:00000023", "time": "18487", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18488, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000008c x15:00000023", "time": "18488", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18489, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118", "time": "18489", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18490, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80", "time": "18490", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18491, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018", "time": "18491", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18492, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18492", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18493, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104098", "time": "18493", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18497, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18497", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18498, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18498", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18500, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "18500", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18501, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18501", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18504, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "18504", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "18518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18519, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "18519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18522, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "18522", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18523, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18523", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18524, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18524", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18526, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "18526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18527, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18527", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18529, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18529", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18530, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000023", "time": "18530", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18531, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18531", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18532, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000118 x15:00000023", "time": "18532", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18533, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000008c x15:00000023", "time": "18533", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18579, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118", "time": "18579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18580, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80", "time": "18580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18581, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018", "time": "18581", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18582, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18582", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18583, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104098", "time": "18583", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18587, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18587", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18588, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18590, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "18590", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18591, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18591", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18594, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "18594", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18608, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "18608", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18609, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "18609", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18612, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "18612", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18613, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18617", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18620, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000023", "time": "18620", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18624, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118", "time": "18624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18625, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80", "time": "18625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18626, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", 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"X", "ts": 18636, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18636", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18639, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "18639", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18658, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "18658", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18667", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18669, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18669", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18670, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000023", "time": "18670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18671, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18671", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18672, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000118 x15:00000023", "time": "18672", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18673, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000008c x15:00000023", "time": "18673", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18674, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118", "time": "18674", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18675, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80", "time": "18675", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18676, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018", "time": "18676", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18677, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18677", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18678, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104098", "time": "18678", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18682, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18682", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18683, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18683", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18685, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "18685", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18686, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18686", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18689, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "18689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18705, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "18705", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18706, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000072", "time": "18706", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18709, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000072 x20:00000025", "time": "18709", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18710, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18710", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18711, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18711", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18713, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000072 x11:00000072", "time": "18713", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18714, "dur": 2, "pid": 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"X", "ts": 18780, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18783, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "18783", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18797, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "18797", "Origin": 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"time": "20731", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 20732, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "20732", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 20735, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353", "time": "20735", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 20749, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_3.log", "tid": "tfp_format", "args":{"pc": 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"instr": "jal x0, 24 ", "time": "12588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12606, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000024", "time": "12606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12607, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000004 x10:00000024", "time": "12607", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 12624, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17856, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001000 x19:00000004 x10:00000400", "time": "17856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=104ff400 x10:00001000 x5:104fe400", "time": "17857", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17858, "dur": 2, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "17904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "17905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "17906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "17907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17925, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000024", "time": "17925", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17942", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 17943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000001 x12:00000024", "time": "17943", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001", "time": "17944", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": 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17965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=104ff3c0 x2:104ff400", "time": "17965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17966, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000001 x2:104ff3c0 PA:104ff3e4", "time": "17966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17968, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "17968", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17972, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=104ff3e4 x2:104ff3c0", "time": "17972", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "17987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17988, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "17988", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17989, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:104ff3c0 PA:104ff3dc", "time": "17989", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17990, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:104ff3c0 PA:104ff3f0", "time": "17990", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17991, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:104ff3c0 PA:104ff3f4", "time": "17991", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17992, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c00182c", "instr": "sw x16, 56(x2) x16:00000000 x2:104ff3c0 PA:104ff3f8", "time": "17992", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17993, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:104ff3c0 PA:104ff3fc", "time": "17993", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18009, "dur": 6, "pid": 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"cat": "addi", "ph": "X", "ts": 18029, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001b72", "instr": "addi x15, x2, 24 x15=104ff378 x2:104ff360", "time": "18029", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:278"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18030, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001b74", "instr": "sw x8, 88(x2) x8:00000000 x2:104ff360 PA:104ff3b8", "time": "18030", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18033, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001b76", "instr": "sw x18, 80(x2) x18:1b204000 x2:104ff360 PA:104ff3b0", "time": "18033", "Origin": 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"ph": "X", "ts": 18579, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18580, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000120 x15:00000024", "time": "18580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18581, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000090 x15:00000024", "time": "18581", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18621", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18623, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18624, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000024", "time": "18624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18625, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18626, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000120 x15:00000024", "time": "18626", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18627, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000090 x15:00000024", "time": "18627", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18628, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120", "time": "18628", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18629, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80", "time": "18629", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18630, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020", "time": "18630", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18631, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18631", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18632, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1040a0", "time": "18632", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18636, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18636", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18637, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18637", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18639, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "18639", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18640, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18640", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18643, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "18643", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18662, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "18662", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18663, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "18663", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18666, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "18666", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18667, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18667", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18668, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18668", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18670, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "18670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18671, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18671", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18673, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18673", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18674, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000024", "time": "18674", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18678, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120", "time": "18678", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18679, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80", "time": "18679", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18680, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", 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"X", "ts": 18690, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18693, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "18693", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18707, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "18707", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18716", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18718, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18718", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000024", "time": "18719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000120 x15:00000024", "time": "18721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18722, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000090 x15:00000024", "time": "18722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18723, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120", "time": "18723", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18724, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80", "time": "18724", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18725, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020", "time": "18725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18726, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18726", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18727, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1040a0", "time": "18727", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18731, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18731", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18732, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18732", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18734, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "18734", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18735, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18735", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18738, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "18738", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18756, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "18756", "Origin": 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x10, x0, x18 x10=00000000 x18:00000000", "time": "18761", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18762, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18762", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18764, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000065 x11:00000065", "time": "18764", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18765, "dur": 2, "pid": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000001 x10:00000025", "time": "12624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 12625, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000005", "time": "12625", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12626, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "12626", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12644, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "12644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12645, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "12645", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "12646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 12647, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000005", "time": "12647", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "12699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12700, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000025", "time": "12700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000005 x19:00000025", "time": "12701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12702, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "12702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "12719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "12720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "12721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12722, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "12722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 12742, "dur": 5050, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "12742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17792, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "17792", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17810, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "17810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17811, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "17811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17829, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "17829", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17830, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "17830", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17832, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080", "time": "17832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17856, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001400 x19:00000005 x10:00000400", "time": "17856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=104ff800 x10:00001400 x5:104fe400", "time": "17857", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17858, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "17858", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17860, "dur": 36, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "17860", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17896, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "17896", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "17904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "17905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "17906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "17907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17925, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000025", "time": "17925", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17942", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 17943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000001 x12:00000025", "time": "17943", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001", "time": "17944", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17945, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000005 x12:00000025", "time": "17945", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17946, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "17946", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17947, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "17947", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=104ff7c0 x2:104ff800", "time": "17965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17966, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000001 x2:104ff7c0 PA:104ff7e4", "time": "17966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17969, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "17969", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, 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"X", "ts": 18272, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18272", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18275, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "18275", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18294, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "18294", "Origin": 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"ph": "X", "ts": 18724, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18724", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18725, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000128 x15:00000025", "time": "18725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18726, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000094 x15:00000025", "time": "18726", "Origin": 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"X", "ts": 18739, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18739", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18742, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "18742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18760, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "18760", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18769", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18771, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18771", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18772, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000025", "time": "18772", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18776, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128", "time": "18776", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18777, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80", "time": "18777", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18778, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028", "time": "18778", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18779, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18779", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18780, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040a8", "time": "18780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18784, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18784", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18785, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18785", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18787, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002349 x9:1c002349", "time": "18787", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18788, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18788", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18791, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "18791", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18805, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "18805", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18806, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "18806", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18809, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "18809", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18810, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18811, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18813, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "18813", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18814, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18814", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18816, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18816", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18817, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000025", "time": "18817", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"instr": "jal x0, 24 ", "time": "12588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12606, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000026", "time": "12606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12607, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000006 x10:00000026", "time": "12607", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 12624, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17856, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001800 x19:00000006 x10:00000400", "time": "17856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=104ffc00 x10:00001800 x5:104fe400", "time": "17857", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17858, "dur": 2, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "17904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "17905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "17906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "17907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17925, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000026", "time": "17925", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17942", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 17943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000001 x12:00000026", "time": "17943", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001", "time": "17944", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": 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17965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=104ffbc0 x2:104ffc00", "time": "17965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17966, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000001 x2:104ffbc0 PA:104ffbe4", "time": "17966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "17972", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17976, "dur": 11, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=104ffbe4 x2:104ffbc0", "time": "17976", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "17987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17988, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "17988", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17989, "dur": 7, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:104ffbc0 PA:104ffbdc", "time": "17989", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17996, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:104ffbc0 PA:104ffbf0", "time": "17996", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17997, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:104ffbc0 PA:104ffbf4", "time": "17997", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17998, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c00182c", "instr": "sw x16, 56(x2) x16:00000000 x2:104ffbc0 PA:104ffbf8", "time": "17998", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17999, "dur": 10, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:104ffbc0 PA:104ffbfc", "time": "17999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18009, "dur": 7, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001830", "instr": "sw x13, 12(x2) x13:104ffbe4 x2:104ffbc0 PA:104ffbcc", "time": "18009", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18016, "dur": 12, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "printf", "args":{"pc": "1c001832", "instr": "jal x1, 830 x1=1c001834", "time": "18016", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18028, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b70", "instr": "addi x2, x2, -96 x2=104ffb60 x2:104ffbc0", "time": "18028", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18029, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b72", "instr": "addi x15, x2, 24 x15=104ffb78 x2:104ffb60", "time": "18029", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:278"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18030, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b74", "instr": "sw x8, 88(x2) x8:00000000 x2:104ffb60 PA:104ffbb8", "time": "18030", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18035, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b76", "instr": "sw x18, 80(x2) x18:1b204000 x2:104ffb60 PA:104ffbb0", "time": "18035", "Origin": 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"1c001b7c", "instr": "sw x21, 68(x2) x21:1c002210 x2:104ffb60 PA:104ffba4", "time": "18038", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18039, "dur": 12, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b7e", "instr": "sw x22, 64(x2) x22:00000000 x2:104ffb60 PA:104ffba0", "time": "18039", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18051, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b80", "instr": "sw x23, 60(x2) x23:00000000 x2:104ffb60 PA:104ffb9c", "time": "18051", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18052, "dur": 1, "pid": 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"X", "ts": 18324, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18327, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "18327", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "18346", "Origin": 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"X", "ts": 18374, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18377, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "18377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18391, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "18391", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18400", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18403, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000026", "time": "18403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18404, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18404", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18405, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000130 x15:00000026", "time": "18405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18406, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000098 x15:00000026", "time": "18406", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18415", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18416, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18416", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18418, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "18418", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18419, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18419", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18422, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18436, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "18436", "Origin": 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"X", "ts": 18836, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18839, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a", "time": "18839", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234b x12:1c00234a", "time": "18857", "Origin": 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"X", "ts": 12644, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "12644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12645, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "12645", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 12646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "12646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 12647, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000007", "time": "12647", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 12699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "12699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 12700, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000027", "time": "12700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 12701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000007 x19:00000027", "time": "12701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12702, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "12702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12719, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "12719", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 12720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "12720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 12721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "12721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 12722, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "12722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 12742, "dur": 5050, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "12742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17792, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "17792", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17810, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "17810", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17811, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "17811", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17829, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "17829", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17830, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "17830", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17832, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080", "time": "17832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17856, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001c00 x19:00000007 x10:00000400", "time": "17856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17857, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10500000 x10:00001c00 x5:104fe400", "time": "17857", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17858, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "17858", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17860, "dur": 36, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "17860", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17896, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "17896", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17904, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "17904", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17905, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "17905", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17906, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "17906", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 17907, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "17907", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17925, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000027", "time": "17925", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "17942", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 17943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000001 x12:00000027", "time": "17943", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001", "time": "17944", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 17945, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000007 x12:00000027", "time": "17945", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17946, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "17946", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17947, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "17947", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=104fffc0 x2:10500000", "time": "17965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17966, "dur": 7, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000001 x2:104fffc0 PA:104fffe4", "time": "17966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "17973", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18687, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138", "time": "18687", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18688, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80", "time": "18688", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18689, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038", "time": "18689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18690, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18691, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1040b8", "time": "18691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18695, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18695", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18696, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18696", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18698, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "18698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18699, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18702, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "18702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18717, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "18717", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18718, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000072", "time": "18718", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000072 x20:00000025", "time": "18721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18722, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18723, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18723", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18725, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000072 x11:00000072", "time": "18725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18726, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18726", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18728, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18728", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18729, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000027", "time": "18729", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18730, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18730", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18731, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000138 x15:00000027", "time": "18731", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18732, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000009c x15:00000027", "time": "18732", "Origin": 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"ph": "X", "ts": 18777, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18777", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18778, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000138 x15:00000027", "time": "18778", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18779, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000009c x15:00000027", "time": "18779", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18780, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138", "time": "18780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18781, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80", "time": "18781", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18782, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038", "time": "18782", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18783, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18783", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18784, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040b8", "time": "18784", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18788, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18788", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18789, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18789", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18791, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002349 x9:1c002349", "time": "18791", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18792, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18792", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18795, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "18795", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18812, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "18812", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18813, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "18813", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18816, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "18816", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18817, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18817", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18818, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18818", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18820, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "18820", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18821, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18823, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18824, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_01_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000027", "time": "18824", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:127"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 18250, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c002194", "instr": "auipc x30, 0xfeffe000 x30=1b000194", "time": "18250", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:131"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18251, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c002198", "instr": "addi x30, x30, -332 x30=1b000048 x30:1b000194", "time": "18251", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:131"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18252, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": 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"Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:144"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18295, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c0021ae", "instr": "sw x28, 524(x19) x28:000000ff x19:1b204000 PA:1b20420c", "time": "18295", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:145"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18296, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c0021b2", "instr": "sw x28, 132(x19) x28:000000ff x19:1b204000 PA:1b204084", "time": "18296", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:155"}}, +{"name": "p.beqimm", "cat": "p.beqimm", "ph": "X", "ts": 18297, "dur": 1, "pid": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19057", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19058, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19058", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19060, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19060", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19061, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19061", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19064, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19064", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19078, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19078", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19079, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19079", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19082, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19082", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19083, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19083", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19084, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19084", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19086, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19086", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19087, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19087", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19089, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19089", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19090, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000040", "time": "19090", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19091, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19091", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19092, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000200 x15:00000040", "time": "19092", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19093, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000100 x15:00000040", "time": "19093", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19094, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200", "time": "19094", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19095, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80", "time": "19095", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19096, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000", "time": "19096", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19097, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19097", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19098, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104100", "time": "19098", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19102, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19102", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19103, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19103", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19105, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19105", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19106, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19106", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19109, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19109", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19123, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19123", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19124, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19124", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19127, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19127", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19128, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19128", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19129, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19129", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19131, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19131", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19132, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19135, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000040", "time": "19135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19136, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19136", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19137, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000200 x15:00000040", "time": "19137", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19138, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000100 x15:00000040", "time": "19138", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19139, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19140, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80", "time": "19140", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19141, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19147", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19148, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19148", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19150, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19150", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19151, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19151", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19154, "dur": 33, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19187, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19187", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19188, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19188", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19191, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19191", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19192, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19192", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19193, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19193", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19195, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19195", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19196, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19196", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19198, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19198", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19199, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000040", "time": "19199", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19200, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19201, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000200 x15:00000040", "time": "19201", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19202, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000100 x15:00000040", "time": "19202", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19203, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200", "time": "19203", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19204, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80", "time": "19204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19205, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000", "time": "19205", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19206, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19206", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19207, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104100", "time": "19207", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19211, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19211", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19212, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19212", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19214, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19214", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19215, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19215", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19218, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19218", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19236, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19236", "Origin": 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x10, x0, x18 x10=00000000 x18:00000000", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19242, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19244, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "19244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19245, "dur": 2, "pid": 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"ph": "X", "ts": 19298, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19298", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19299, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000200 x15:00000040", "time": "19299", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19300, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000100 x15:00000040", "time": "19300", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000", "time": "19303", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19304, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19304", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19305, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104100", "time": "19305", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19309, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19309", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19310, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19310", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19312, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "19312", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19313, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19313", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19316, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19316", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19334, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "19337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19338, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19342", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19344, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19344", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19345, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000040", "time": "19345", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19349, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200", "time": "19349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19350, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80", "time": "19350", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000", "time": "19351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19352, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19353, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104100", "time": "19353", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19357, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19357", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19358, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19358", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19360, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002349 x9:1c002349", "time": "19360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19361, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19361", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19364, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19364", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19385, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19385", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19386, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19386", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19390, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19396, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19397, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000040", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19398, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19398", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19399, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000200 x15:00000040", "time": "19399", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19400, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000100 x15:00000040", "time": "19400", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19401, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200", "time": "19401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80", "time": "19402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19403, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000", "time": "19403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19404, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19404", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19405, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104100", "time": "19405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19409, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19409", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19410, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19410", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19412, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00234a x9:1c00234a", "time": "19412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19413, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19413", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19416, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a", "time": "19416", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19437, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234b x12:1c00234a", "time": "19437", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 21315, "dur": 13, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "evt_read32", "args":{"pc": "1c000a2e", "instr": "p.elw x15, 28(x9) x15=00000000 x9:1b204200 PA:1b20421c", "time": "21315", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/eu/eu_v3.h:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 21328, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a32", "instr": "lui x15, 0x1c002000 x15=1c002000", "time": "21328", "Origin": "/scratch/digirols/pulp_api_example/main.c:57"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 21329, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a36", "instr": "slli x8, x8, 0x2 x8=00000008 x8:00000002", "time": "21329", "Origin": "/scratch/digirols/pulp_api_example/main.c:57"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21330, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a38", "instr": "addi x15, x15, 1668 x15=1c002684 x15:1c002000", "time": "21330", "Origin": "/scratch/digirols/pulp_api_example/main.c:57"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21331, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a3c", "instr": "addi x14, x0, 1 x14=00000001", "time": "21331", "Origin": "/scratch/digirols/pulp_api_example/main.c:57"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 21348, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a3e", "instr": "p.sw x14, x0(x15) x14:00000001 x15:1c002684 PA:1c00268c", "time": "21348", "Origin": "/scratch/digirols/pulp_api_example/main.c:57"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21366, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a42", "instr": "lw x1, 12(x2) x1=1c00215a x2:108fe3f0 PA:108fe3fc", "time": "21366", "Origin": "/scratch/digirols/pulp_api_example/main.c:58"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21367, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a44", "instr": "lw x8, 8(x2) x8=1b000028 x2:108fe3f0 PA:108fe3f8", "time": "21367", "Origin": "/scratch/digirols/pulp_api_example/main.c:58"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21368, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a46", "instr": "lw x9, 4(x2) x9=1b000048 x2:108fe3f0 PA:108fe3f4", "time": "21368", "Origin": "/scratch/digirols/pulp_api_example/main.c:58"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21369, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a48", "instr": "addi x2, x2, 16 x2=108fe400 x2:108fe3f0", "time": "21369", "Origin": "/scratch/digirols/pulp_api_example/main.c:58"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21370, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "cluster_entry", "args":{"pc": "1c000a4a", "instr": "jalr x0, x1, 0 x1:1c00215a", "time": "21370", "Origin": "/scratch/digirols/pulp_api_example/main.c:58"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21372, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_event", "args":{"pc": "1c00215a", "instr": "beq x22, x0, 20 x22:100fc720", "time": "21372", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:91"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21374, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_push_event_to_fc_retry", "args":{"pc": "1c00215e", "instr": "lw x5, 0(x23) x5=00000000 x23:1c2fff88 PA:1c2fff88", "time": "21374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:96"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 21389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_push_event_to_fc_retry", "args":{"pc": "1c002162", "instr": "bne x5, x0, 126 x5:00000000", "time": "21389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:97"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21390, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_push_event_to_fc_retry", "args":{"pc": "1c002166", "instr": "sw x22, 0(x23) x22:100fc720 x23:1c2fff88 PA:1c2fff88", "time": "21390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:100"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21408, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_push_event_to_fc_retry", "args":{"pc": "1c00216a", "instr": "sw x24, 0(x25) x24:00000001 x25:10200e04 PA:10200e04", "time": "21408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:103"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21412, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c00216e", "instr": "lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028", "time": "21412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:109"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21414, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c002172", "instr": "beq x28, x0, 96 x28:00000000", "time": "21414", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:110"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21417, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021d2", "instr": "sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008", "time": "21417", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:188"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 21418, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021d6", "instr": "p.elw x0, 60(x19) x19:1b204000 PA:1b20403c", "time": "21418", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:189"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21423, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021da", "instr": "sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004", "time": "21423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:190"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21424, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021de", "instr": "jal x0, -112 ", "time": "21424", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:191"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21427, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c00216e", "instr": "lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028", "time": "21427", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:109"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21429, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c002172", "instr": "beq x28, x0, 96 x28:00000000", "time": "21429", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:110"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14818, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "_start", "args":{"pc": "1c000080", "instr": "jal x0, 24 ", "time": "14818", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14836, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000041", "time": "14836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14837, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000001 x10:00000041", "time": "14837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 14854, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000002 x10:00000041", "time": "14854", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14855, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000001", "time": "14855", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14856, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "14856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14874, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "14874", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "14875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14876, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "14876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 14877, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000001", "time": "14877", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "14929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000041", "time": "14930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000001 x19:00000041", "time": "14931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14932, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "14932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14949, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "14949", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14950, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "14950", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14951, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "14951", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14952, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "14952", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 14971, "dur": 3335, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "14971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18306, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18324, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18347, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18349, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080", "time": "18349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000400 x19:00000001 x10:00000400", "time": "18373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=108fe800 x10:00000400 x5:108fe400", "time": "18374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18375, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18375", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18377, "dur": 35, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18412, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18422, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18423, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18444, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000041", "time": "18444", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18461", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000002 x12:00000041", "time": "18462", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18463, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002", "time": "18463", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18464, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000001 x12:00000041", "time": "18464", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18465, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18465", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18466, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18466", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18487, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=108fe7c0 x2:108fe800", "time": "18487", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18488, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000002 x2:108fe7c0 PA:108fe7e4", "time": "18488", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18492, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "18492", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18493, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000001 x2:108fe7c0 PA:108fe7e8", "time": "18493", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18494, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c00181a", "instr": "sw x13, 44(x2) x13:00000000 x2:108fe7c0 PA:108fe7ec", "time": "18494", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18495, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c00181c", "instr": "add x12, x0, x10 x12=1c00233c x10:1c00233c", "time": "18495", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18496, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=108fe7e4 x2:108fe7c0", "time": "18496", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18511, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "18511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18512, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "18512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18513, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:108fe7c0 PA:108fe7dc", "time": "18513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18516, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:108fe7c0 PA:108fe7f0", "time": "18516", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18517, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:108fe7c0 PA:108fe7f4", "time": "18517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, 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"X", "ts": 18845, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18845", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18848, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18864, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "18864", "Origin": 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"ph": "X", "ts": 18877, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18877", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18878, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "18878", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18879, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "18879", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18882, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18883, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18883", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18884, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104108", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18888, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18888", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18889, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18889", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18891, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "18891", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18892, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18892", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18895, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "18895", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18914, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "18914", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18915, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "18915", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18918, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "18918", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18919, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18919", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18920, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18920", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18922, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "18922", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18923, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18923", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18925, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18925", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18926, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "18926", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18927, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18927", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18928, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "18928", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18932, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18933, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18933", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18934, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104108", "time": "18934", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18938, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18938", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18939, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18939", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18941, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "18941", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18942, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18942", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18945, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "18945", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18960, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "18960", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18961, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "18961", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18964, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "18964", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18965, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18965", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18966, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18966", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18968, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "18968", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18969, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18969", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "18972", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18973", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "18974", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "18975", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18976, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "18976", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18977, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "18977", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18978, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "18978", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18979, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18979", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18980, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104108", "time": "18980", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18984, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18984", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18985, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18985", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "18987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18988, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18988", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18991, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "18991", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19006, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19006", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19007, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19007", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19010, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19010", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19011, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19011", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19012, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19012", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19014, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000027 x11:00000027", "time": "19014", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19015, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19015", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19018, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "19018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19019, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19019", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19020, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "19020", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19021, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "19021", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19022, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "19022", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19023, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "19023", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19024, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "19024", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19025, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19025", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19026, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104108", "time": "19026", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19030, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19030", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19031, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19031", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19033, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19033", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19034, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19034", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19037, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19056, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19056", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19057, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19057", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19060, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19060", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19061, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19061", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19062, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19062", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19064, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19064", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19065, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19065", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19067, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19067", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19068, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "19068", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19069, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19069", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19070, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "19070", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19071, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "19071", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19072, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "19072", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19073, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "19073", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19074, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "19074", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19075, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19075", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19076, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104108", "time": "19076", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19080, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19080", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19081, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19081", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19083, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19083", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19084, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19084", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19087, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19087", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19102, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19102", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19103, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19103", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19106, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19106", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19107, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19107", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19108, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19108", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19110, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19110", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19111, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19113, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19114, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "19114", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19115, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19115", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19116, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "19116", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19117, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "19117", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19118, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "19118", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19119, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "19119", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19120, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "19120", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19121, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19121", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19122, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104108", "time": "19122", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19126, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19126", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19127, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19127", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19129, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19129", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19130, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19130", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19133, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19148, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19148", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19157", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19159, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19159", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19160, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "19160", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19161, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19161", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19162, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "19162", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19163, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "19163", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19164, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "19164", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19165, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "19165", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19166, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "19166", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19167, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19167", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19168, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104108", "time": "19168", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19172, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19173, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19175, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19175", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19176, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19176", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19179, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19179", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19200, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19201, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19201", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19204, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19205, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19209", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19211, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19211", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19212, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "19212", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19216, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "19216", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19217, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "19217", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19218, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "19218", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19219, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19219", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19220, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104108", "time": "19220", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19224, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19224", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19225, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19225", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19227, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "19227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19228, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19228", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19231, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19246, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000072", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19249, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000072 x20:00000025", "time": "19249", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19250, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19256, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19256", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19257, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000041", "time": "19257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19258, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19258", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19259, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "19259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19260, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "19260", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19261, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "19261", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19262, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "19262", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19263, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "19263", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19264, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19264", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19265, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104108", "time": "19265", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19269, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19269", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19270, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19270", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19272, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "19272", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19273, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19273", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19276, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19290, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19290", "Origin": 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"X", "ts": 19318, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19318", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19321, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19321", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19337", "Origin": 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"ph": "X", "ts": 19350, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19350", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000208 x15:00000041", "time": "19351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19352, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000104 x15:00000041", "time": "19352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19353, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208", "time": "19353", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19354, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80", "time": "19354", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19355, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008", "time": "19355", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19356, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19356", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19357, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104108", "time": "19357", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19361, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21148, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "21148", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21149, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "21149", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21151, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002352 x9:1c002352", "time": "21151", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21152, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21152", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21155, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352", "time": "21155", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21171, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_1.log", "tid": "tfp_format", "args":{"pc": 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"instr": "jal x0, 24 ", "time": "14818", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14836, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000042", "time": "14836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14837, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000002 x10:00000042", "time": "14837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 14854, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000002 x10:00000042", "time": "14854", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14855, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000002", "time": "14855", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14856, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "14856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14874, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "14874", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "14875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14876, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "14876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 14877, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000002", "time": "14877", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "14929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000042", "time": "14930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000002 x19:00000042", "time": "14931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14932, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "14932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14949, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "14949", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14950, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "14950", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14951, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "14951", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14952, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "14952", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 14971, "dur": 3335, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "14971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18306, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18324, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18347, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18349, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080", "time": "18349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000800 x19:00000002 x10:00000400", "time": "18373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=108fec00 x10:00000800 x5:108fe400", "time": "18374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18375, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18375", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18377, "dur": 35, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18412, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18422, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18423, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18444, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000042", "time": "18444", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18461, "dur": 1, "pid": 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"X", "ts": 18896, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18896", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18899, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "18899", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18915, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "18915", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18916, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "18916", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18919, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "18919", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18920, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18920", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18921, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18923, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "18923", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18924, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18924", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18926, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18926", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18927, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000042", "time": "18927", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18928, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18928", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18932, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18933, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "18933", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18934, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18934", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18935, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104110", "time": "18935", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18939, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18939", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18940, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18940", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "18942", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18943, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18943", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18946, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "18946", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18963, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "18963", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18964, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "18964", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18967, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "18967", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18968, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18968", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18969, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18969", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "18971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18972, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18972", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18974", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000042", "time": "18975", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18976, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18976", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18977, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "18977", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18978, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "18978", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18979, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210", "time": "18979", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18980, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80", "time": "18980", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18981, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "18981", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18982, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18982", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18983, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104110", "time": "18983", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18988, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18988", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18990, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "18990", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18991, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18991", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18994, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "18994", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19009, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19009", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19010, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19010", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19013, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19013", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19014, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19020, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19020", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19021, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000042", "time": "19021", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19022, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19022", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19023, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "19023", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19024, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "19024", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19025, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210", "time": "19025", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19026, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80", "time": "19026", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19027, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "19027", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19028, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19028", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19029, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104110", "time": "19029", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19033, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19033", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19034, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19034", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19036, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19037, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19040, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19040", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19060, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19060", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19061, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19061", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19064, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19064", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19065, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19065", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19066, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19066", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19068, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19068", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19069, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19069", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19071, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19071", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19072, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000042", "time": "19072", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19073, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19073", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19074, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "19074", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19075, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "19075", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19076, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210", "time": "19076", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19077, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80", "time": "19077", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19078, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "19078", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19079, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19079", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19080, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104110", "time": "19080", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19084, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19084", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19085, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19085", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19087, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19087", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19088, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19088", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19091, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19091", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19105, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19105", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19106, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19106", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19109, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19109", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19110, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19110", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19111, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19113, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19114, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19114", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19116, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19116", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19117, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000042", "time": "19117", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19118, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19118", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19119, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "19119", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19120, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "19120", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19121, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210", "time": "19121", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19122, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80", "time": "19122", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19123, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "19123", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19124, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19124", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19125, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104110", "time": "19125", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19129, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19129", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19130, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19130", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19133, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19136, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19136", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19151, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19151", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19152, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19152", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19155, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19155", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19156, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19156", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19157, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19157", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19159, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19159", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19160, "dur": 2, "pid": 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"ph": "X", "ts": 19164, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19164", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19165, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "19165", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19166, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "19166", "Origin": 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"ph": "X", "ts": 19216, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19216", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19217, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "19217", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19218, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "19218", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "19221", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19222, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19222", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19223, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104110", "time": "19223", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19227, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19228, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19228", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19231, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19234, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19248, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19248", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19259, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19259", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19260, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000042", "time": "19260", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19264, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210", "time": "19264", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19265, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80", "time": "19265", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19266, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "19266", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19267, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19267", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19268, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104110", "time": "19268", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19272, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19272", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19273, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19273", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19275, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "19275", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19276, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19279, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19293, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19294, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19297, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "19297", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19298, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19302", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19304, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19304", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19305, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000042", "time": "19305", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19306, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19307, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000210 x15:00000042", "time": "19307", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19308, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000108 x15:00000042", "time": "19308", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19309, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210", "time": "19309", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19310, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80", "time": "19310", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19311, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010", "time": "19311", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19312, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19312", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19313, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104110", "time": "19313", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19317, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19317", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19318, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19318", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19320, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002349 x9:1c002349", "time": "19320", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19321, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19321", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19324, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19345, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19345", "Origin": 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"time": "21204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21205, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21205", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21208, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353", "time": "21208", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21223, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_2.log", "tid": "tfp_format", "args":{"pc": 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"instr": "jal x0, 24 ", "time": "14818", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14836, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000043", "time": "14836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14837, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000003 x10:00000043", "time": "14837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 14854, "dur": 1, "pid": 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"__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18324, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18347, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18349, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080", "time": "18349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000c00 x19:00000003 x10:00000400", "time": "18373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=108ff000 x10:00000c00 x5:108fe400", "time": "18374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18375, "dur": 2, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18422, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18423, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18444, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000043", "time": "18444", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18461", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000002 x12:00000043", "time": "18462", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18463, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002", "time": "18463", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18464, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000003 x12:00000043", "time": "18464", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18465, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18465", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18466, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18466", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18487, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=108fefc0 x2:108ff000", "time": "18487", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18488, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000002 x2:108fefc0 PA:108fefe4", "time": "18488", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18489, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "18489", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18493, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=108fefe4 x2:108fefc0", "time": "18493", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18511, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "18511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18512, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "18512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18513, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:108fefc0 PA:108fefdc", "time": "18513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18517, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:108fefc0 PA:108feff0", "time": "18517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:108fefc0 PA:108feff4", "time": "18518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18519, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c00182c", "instr": "sw x16, 56(x2) x16:00000000 x2:108fefc0 PA:108feff8", "time": "18519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18520, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:108fefc0 PA:108feffc", "time": "18520", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18534, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001830", "instr": "sw x13, 12(x2) x13:108fefe4 x2:108fefc0 PA:108fefcc", "time": "18534", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18537, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "printf", "args":{"pc": "1c001832", "instr": "jal x1, 830 x1=1c001834", "time": "18537", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18553, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b70", "instr": "addi x2, x2, -96 x2=108fef60 x2:108fefc0", "time": "18553", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "addi", 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"X", "ts": 18946, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18946", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18949, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "18949", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18967, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "18967", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18983, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218", "time": "18983", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18984, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80", "time": "18984", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18985, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018", "time": "18985", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18986, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18986", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18987, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104118", "time": "18987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18991, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18991", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18992, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18992", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18994, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "18994", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18995, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18995", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18998, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "18998", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19013, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19013", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19014, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19014", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19018, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19019, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19019", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19021, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000027 x11:00000027", "time": "19021", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19022, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19022", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19024, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19024", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19025, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000043", "time": "19025", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19026, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19026", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19027, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000218 x15:00000043", "time": "19027", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19028, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000010c x15:00000043", "time": "19028", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19029, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218", "time": "19029", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19030, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80", "time": "19030", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19031, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018", "time": "19031", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19032, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19032", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19033, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104118", "time": "19033", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19037, "dur": 1, "pid": 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"X", "ts": 19041, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19041", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19044, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19044", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19062, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19062", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19063, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19063", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19066, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19066", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19067, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19071", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19073, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19073", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19074, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000043", "time": "19074", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19075, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19075", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19076, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000218 x15:00000043", "time": "19076", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19077, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000010c x15:00000043", "time": "19077", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19078, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218", "time": "19078", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19079, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80", "time": "19079", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19080, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018", "time": "19080", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19081, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19081", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19082, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104118", "time": "19082", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19086, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19086", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19087, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19087", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19089, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19089", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19090, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19090", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19093, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19093", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19108, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19108", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19109, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19109", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19112, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19112", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19113, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19114, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19114", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19116, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19116", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19117, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19117", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19119, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19119", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19120, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000043", "time": "19120", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19121, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19121", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19122, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000218 x15:00000043", "time": "19122", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19123, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000010c x15:00000043", "time": "19123", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19124, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218", "time": "19124", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19125, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80", "time": "19125", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19126, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018", "time": "19126", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19127, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19127", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19128, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104118", "time": "19128", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19133, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19135, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19136, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19136", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19139, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19154, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19155, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19155", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19158, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19158", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19159, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19159", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19160, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19160", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19162, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19162", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19163, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19163", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19165, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19165", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19166, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000043", "time": "19166", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19167, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19167", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19168, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000218 x15:00000043", "time": "19168", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19169, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000010c x15:00000043", "time": "19169", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19170, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218", "time": "19170", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19171, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80", "time": "19171", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19172, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018", "time": "19172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19173, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19174, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104118", "time": "19174", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19178, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19178", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19179, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19179", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19181, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19181", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19182, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19182", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19185, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19185", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19205, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19205", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19206, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19206", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19209, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19209", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19210, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19210", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19211, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19211", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19213, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "19213", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19214, "dur": 2, "pid": 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"ph": "X", "ts": 19218, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19218", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19219, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000218 x15:00000043", "time": "19219", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19220, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000010c x15:00000043", "time": "19220", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018", "time": "19269", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19270, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19270", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19271, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104118", "time": "19271", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19275, "dur": 1, "pid": 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"X", "ts": 19279, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19282, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19282", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19297, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19297", "Origin": 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"X", "ts": 19325, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19325", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19328, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19328", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19351", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19362, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19362", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19363, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000043", "time": "19363", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19364, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19364", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19365, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000218 x15:00000043", "time": "19365", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19366, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000010c x15:00000043", "time": "19366", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19367, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218", "time": "19367", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19368, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80", "time": "19368", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19369, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018", "time": "19369", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19370, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19370", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19371, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104118", "time": "19371", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19375, "dur": 1, "pid": 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"X", "ts": 19379, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19379", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19382, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a", "time": "19382", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19401, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234b x12:1c00234a", "time": "19401", "Origin": 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"time": "21159", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21160, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21160", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21163, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352", "time": "21163", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21178, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21202, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "21202", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21203, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "21203", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21205, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002353 x9:1c002353", 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"instr": "jal x0, 24 ", "time": "14818", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14836, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000044", "time": "14836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14837, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000004 x10:00000044", "time": "14837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 14854, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000002 x10:00000044", "time": "14854", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14855, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000004", "time": "14855", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14856, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "14856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14874, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "14874", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "14875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14876, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "14876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 14877, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000004", "time": "14877", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "14929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000044", "time": "14930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000004 x19:00000044", "time": "14931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14932, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "14932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14949, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "14949", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14950, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "14950", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14951, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "14951", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14952, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "14952", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 14971, "dur": 3335, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "14971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18306, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18324, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18347, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18349, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080", "time": "18349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001000 x19:00000004 x10:00000400", "time": "18373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=108ff400 x10:00001000 x5:108fe400", "time": "18374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18375, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18375", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18377, "dur": 35, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18412, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18422, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18423, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18444, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000044", "time": "18444", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18461", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000002 x12:00000044", "time": "18462", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18463, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002", "time": "18463", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18936, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "18936", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18937, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "18937", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18938, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020", "time": "18938", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18939, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18939", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18940, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104120", "time": "18940", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18944, "dur": 1, "pid": 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"X", "ts": 18948, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18948", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18951, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "18951", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18970, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "18970", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18971, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "18971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "18974", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "18975", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18976, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "18976", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18978, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "18978", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18979, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18979", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18981, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18981", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18982, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000044", "time": "18982", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18983, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18983", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18984, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000220 x15:00000044", "time": "18984", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18985, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000110 x15:00000044", "time": "18985", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18986, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "18986", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "18987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18988, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18994", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18995, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18995", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18997, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "18997", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19033, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "19033", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19034, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "19034", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19035, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020", "time": "19035", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19036, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19037, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104120", "time": "19037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19041, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19041", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19042, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19042", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19044, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19044", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19045, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19045", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19048, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19048", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19063, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19063", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19064, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19064", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19067, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19067", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19068, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19072", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19074, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19074", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19075, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000044", "time": "19075", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19076, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19076", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19077, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000220 x15:00000044", "time": "19077", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19078, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000110 x15:00000044", "time": "19078", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19079, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "19079", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19080, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "19080", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19081, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020", "time": "19081", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19082, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19082", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19083, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104120", "time": "19083", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19087, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19087", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19088, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19088", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19090, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19090", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19091, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19091", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19094, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19094", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19112, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19112", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19113, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19116, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19116", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19117, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19117", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19118, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19118", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19120, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19120", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19121, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19121", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19123, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19123", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19124, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000044", "time": "19124", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19125, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19125", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19126, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000220 x15:00000044", "time": "19126", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19127, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000110 x15:00000044", "time": "19127", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19128, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "19128", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19129, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "19129", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19130, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020", "time": "19130", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19131, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19131", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19132, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104120", "time": "19132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19136, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19136", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19137, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19137", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19139, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19140, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19140", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19143, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19143", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19164, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19164", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19165, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19165", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19168, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19168", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19169, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19169", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19170, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19170", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19172, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19173, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19175, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19175", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19176, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000044", "time": "19176", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19177, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19177", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19178, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000220 x15:00000044", "time": "19178", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19179, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000110 x15:00000044", "time": "19179", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19180, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "19180", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19181, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "19181", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19182, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020", "time": "19182", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19183, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19183", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19184, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104120", "time": "19184", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19188, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19188", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19189, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19189", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19191, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19191", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19192, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19192", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19195, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19195", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19215, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19215", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19216, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19216", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19219, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19219", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19220, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19224", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19226, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19226", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19227, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000044", "time": "19227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19228, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19228", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19229, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000220 x15:00000044", "time": "19229", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000110 x15:00000044", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19231, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "19232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020", "time": "19233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19235, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104120", "time": "19235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19240, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19242, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "19242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19243, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19246, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19263, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19263", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19264, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000072", "time": "19264", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19267, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000072 x20:00000025", "time": "19267", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19268, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19268", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19269, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19269", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19271, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000072 x11:00000072", "time": "19271", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19272, "dur": 2, "pid": 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"ph": "X", "ts": 19276, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19277, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000220 x15:00000044", "time": "19277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19278, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000110 x15:00000044", "time": "19278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19279, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19280, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "19280", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19281, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", 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"X", "ts": 19291, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19291", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19294, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19308, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19308", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19317", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19319, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19319", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19320, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000044", "time": "19320", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19321, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19321", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19322, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000220 x15:00000044", "time": "19322", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000110 x15:00000044", "time": "19323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19324, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220", "time": "19324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19325, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80", "time": "19325", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19326, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020", "time": "19326", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19327, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19327", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19328, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104120", "time": "19328", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19333, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19335, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002349 x9:1c002349", "time": "19335", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19336, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19336", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19339, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19339", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19360, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19361, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19361", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19364, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19364", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19365, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18423, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18444, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000045", "time": "18444", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18461, "dur": 1, "pid": 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x11:1c001000", "time": "18512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18513, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:108ff7c0 PA:108ff7dc", "time": "18513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18515, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:108ff7c0 PA:108ff7f0", "time": "18515", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18516, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "printf", 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"cat": "addi", "ph": "X", "ts": 18554, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b72", "instr": "addi x15, x2, 24 x15=108ff778 x2:108ff760", "time": "18554", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:278"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18555, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b74", "instr": "sw x8, 88(x2) x8:00000000 x2:108ff760 PA:108ff7b8", "time": "18555", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18559, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b76", "instr": "sw x18, 80(x2) x18:1b204000 x2:108ff760 PA:108ff7b0", "time": "18559", "Origin": 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"ph": "X", "ts": 18937, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18937", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18938, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "18938", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18939, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "18939", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028", "time": "18942", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18943", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18944, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104128", "time": "18944", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18948, "dur": 1, "pid": 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"X", "ts": 19048, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19048", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19051, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19051", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19066, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19066", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19067, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19067", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19070, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19070", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19071, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19075", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19077, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19077", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19078, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000045", "time": "19078", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19079, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19079", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19080, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "19080", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19081, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "19081", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19082, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228", "time": "19082", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19083, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80", "time": "19083", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19084, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028", "time": "19084", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19085, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19085", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19086, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104128", "time": "19086", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19090, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19090", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19091, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19091", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19093, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19093", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19094, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19094", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19097, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19097", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19114, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19114", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19115, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19115", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19118, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19118", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19119, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19119", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19120, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19120", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19122, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19122", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19123, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19123", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19125, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19125", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19126, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000045", "time": "19126", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19127, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19127", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19128, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "19128", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19129, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "19129", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19130, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228", "time": "19130", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19131, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80", "time": "19131", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028", "time": "19132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19134, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104128", "time": "19134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19138, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19138", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19139, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19141, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19141", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19142, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19142", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19145, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19145", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19166, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19166", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19167, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19167", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19170, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19170", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19171, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19171", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19172, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19174, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19174", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19175, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19175", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19177, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19177", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19178, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000045", "time": "19178", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19179, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19179", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19180, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "19180", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19181, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "19181", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19182, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228", "time": "19182", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19183, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80", "time": "19183", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19184, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028", "time": "19184", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19185, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19185", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19186, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104128", "time": "19186", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19190, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19190", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19191, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19191", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19193, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19193", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19194, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19194", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19197, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19197", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19216, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19216", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19217, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19217", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19220, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19220", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19221, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19221", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19222, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19222", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19224, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "19224", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19225, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19225", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19227, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19228, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000045", "time": "19228", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19229, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19229", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19231, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19232, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228", "time": "19232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19233, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80", "time": "19233", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19235, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19236, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104128", "time": "19236", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19241, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19243, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "19243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19244, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19247, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19247", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19267, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19267", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19268, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000072", "time": "19268", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19271, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000072 x20:00000025", "time": "19271", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19272, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19276", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19278, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19279, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000045", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19280, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19280", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19281, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "19281", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19282, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "19282", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19283, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228", "time": "19283", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19284, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80", "time": "19284", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19285, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028", "time": "19285", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19286, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19287, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104128", "time": "19287", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19291, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19291", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19292, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19294, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "19294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19295, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19295", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19298, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19298", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19315, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19315", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19316, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19316", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19319, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "19319", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19320, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19320", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19321, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19321", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000065 x11:00000065", "time": "19323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19324, "dur": 2, "pid": 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"ph": "X", "ts": 19328, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19328", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19329, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "19329", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19330, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "19330", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19331, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228", "time": "19331", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80", "time": "19332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", 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"X", "ts": 19343, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19346, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19365, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19365", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19376, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19376", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19377, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000045", "time": "19377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19378, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19378", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19379, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000228 x15:00000045", "time": "19379", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19380, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000114 x15:00000045", "time": "19380", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19381, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228", "time": "19381", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19382, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80", "time": "19382", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19383, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028", "time": "19383", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19384, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19384", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19385, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104128", "time": "19385", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19390, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19392, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00234a x9:1c00234a", "time": "19392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19393, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19396, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19415, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234b x12:1c00234a", "time": "19415", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19416, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000028", "time": "19416", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19419, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000028 x20:00000025", "time": "19419", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"time": "21223", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21224, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21224", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21227, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353", "time": "21227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_5.log", "tid": "tfp_format", "args":{"pc": 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"instr": "jal x0, 24 ", "time": "14818", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14836, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000046", "time": "14836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14837, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000006 x10:00000046", "time": "14837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 14854, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000002 x10:00000046", "time": "14854", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 14855, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000006", "time": "14855", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14856, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "14856", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14874, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "14874", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14875, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "14875", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 14876, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "14876", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 14877, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000006", "time": "14877", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 14929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "14929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 14930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000046", "time": "14930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 14931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000006 x19:00000046", "time": "14931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14932, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "14932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14949, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "14949", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 14950, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "14950", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 14951, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "14951", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 14952, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "14952", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 14971, "dur": 3335, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "14971", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18306, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18323, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18323", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18324, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18324", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18346, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18347, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18347", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18349, "dur": 24, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080", "time": "18349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18373, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001800 x19:00000006 x10:00000400", "time": "18373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18374, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=108ffc00 x10:00001800 x5:108fe400", "time": "18374", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18375, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18375", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18377, "dur": 35, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18412, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18421, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18422, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18423, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18444, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000046", "time": "18444", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18461", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000002 x12:00000046", "time": "18462", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18463, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002", "time": "18463", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18464, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000006 x12:00000046", "time": "18464", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18465, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18465", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18466, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18466", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 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"X", "ts": 18812, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18812", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18815, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "18815", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18829, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "18829", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030", "time": "18944", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18945, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18945", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18946, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104130", "time": "18946", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18950, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "18950", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18951, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "18951", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18953, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "18953", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18954, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "18954", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 18957, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "18957", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "18974", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18975, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "18975", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 18978, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "18978", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18979, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "18983", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18985, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "18985", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18986, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000046", "time": "18986", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18987, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18987", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18988, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000230 x15:00000046", "time": "18988", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18989, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000118 x15:00000046", "time": "18989", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030", "time": "18992", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18993, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18993", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18994, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104130", "time": "18994", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18998, "dur": 1, "pid": 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"X", "ts": 19096, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19096", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19099, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19099", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19115, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19115", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19124", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19126, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19126", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19127, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000046", "time": "19127", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19131, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230", "time": "19131", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80", "time": "19132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030", "time": "19133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19135, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104130", "time": "19135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19139, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19139", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19140, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19140", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19142, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19142", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19143, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19143", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19146, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19146", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19176, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19176", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19177, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19177", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19180, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19180", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19181, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19181", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19182, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19182", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19184, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19184", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19185, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19185", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19187, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19187", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19188, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000046", "time": "19188", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19189, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19189", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19190, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000230 x15:00000046", "time": "19190", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19191, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000118 x15:00000046", "time": "19191", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19192, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230", "time": "19192", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19193, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80", "time": "19193", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19194, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030", "time": "19194", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19195, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19195", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19196, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104130", "time": "19196", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19200, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19201, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19201", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19203, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19203", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19204, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19207, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19207", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19226, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19226", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19227, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19227", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19230, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19231, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19232, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19235, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19237, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19237", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19238, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000046", "time": "19238", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19240, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000230 x15:00000046", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19241, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000118 x15:00000046", "time": "19241", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19242, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230", "time": "19242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19243, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80", "time": "19243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19244, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030", "time": "19244", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19246, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104130", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19250, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19250", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19251, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19251", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19253, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "19253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19254, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19257, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19257", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19273, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19273", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19274, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000072", "time": "19274", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19277, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000072 x20:00000025", "time": "19277", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19278, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19278", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19279, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19279", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19281, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000072 x11:00000072", "time": "19281", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19282, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19282", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19284, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19284", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19285, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000046", "time": "19285", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19286, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19286", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19287, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000230 x15:00000046", "time": "19287", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19288, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000118 x15:00000046", "time": "19288", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19289, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230", "time": "19289", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19290, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80", "time": "19290", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19291, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030", "time": "19291", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19292, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19293, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104130", "time": "19293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19297, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19297", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19298, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19298", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19300, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "19300", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19301, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19301", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19304, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19304", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19321, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19321", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19322, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19322", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19325, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "19325", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19326, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19330", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19333, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000046", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19334, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19334", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19335, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000230 x15:00000046", "time": "19335", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19336, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000118 x15:00000046", "time": "19336", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230", "time": "19337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19338, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80", "time": "19338", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19339, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030", "time": "19339", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19340, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19340", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19341, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104130", "time": "19341", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19345, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19345", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19346, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19346", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19348, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002349 x9:1c002349", "time": "19348", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19349, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19352, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19372, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19372", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19373, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19373", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19376, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19376", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19377, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19377", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19378, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19378", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19380, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19380", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19381, "dur": 2, "pid": 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"args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18422", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18423, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18444, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000047", "time": "18444", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18461", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000002 x12:00000047", "time": "18462", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18463, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002", "time": "18463", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": 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x11:1c001000", "time": "18512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18513, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:108fffc0 PA:108fffdc", "time": "18513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18519, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:108fffc0 PA:108ffff0", "time": "18519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18520, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "printf", 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"cat": "addi", "ph": "X", "ts": 18554, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b72", "instr": "addi x15, x2, 24 x15=108fff78 x2:108fff60", "time": "18554", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:278"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18555, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b74", "instr": "sw x8, 88(x2) x8:00000000 x2:108fff60 PA:108fffb8", "time": "18555", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18561, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b76", "instr": "sw x18, 80(x2) x18:1b204000 x2:108fff60 PA:108fffb0", "time": "18561", "Origin": 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"ph": "X", "ts": 18844, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18844", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18845, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000238 x15:00000047", "time": "18845", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18846, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000011c x15:00000047", "time": "18846", "Origin": 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"ph": "X", "ts": 18941, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "18941", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18942, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000238 x15:00000047", "time": "18942", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 18943, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000011c x15:00000047", "time": "18943", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18944, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238", "time": "18944", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 18945, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80", "time": "18945", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18946, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038", "time": "18946", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18947, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "18947", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 18948, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104138", "time": "18948", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18952, "dur": 1, "pid": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038", "time": "19091", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19092, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19092", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19093, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104138", "time": "19093", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19097, "dur": 1, "pid": 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"X", "ts": 19101, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19101", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19104, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19104", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19118, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19118", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19119, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19119", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19122, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19122", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19123, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19127", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19129, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19129", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19130, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000047", "time": "19130", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19131, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19131", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000238 x15:00000047", "time": "19132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000011c x15:00000047", "time": "19133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238", "time": "19134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19135, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80", "time": "19135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19136, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19142", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19143, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19143", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19145, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19145", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19146, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19146", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19149, "dur": 35, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19149", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19184, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19184", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19193", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19195, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19195", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19196, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000047", "time": "19196", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19197, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19197", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19198, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000238 x15:00000047", "time": "19198", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19199, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000011c x15:00000047", "time": "19199", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19200, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238", "time": "19200", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19201, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80", "time": "19201", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19202, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038", "time": "19202", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19203, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19203", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19204, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104138", "time": "19204", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19208, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19208", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19209, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19209", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19211, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19211", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19212, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19212", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19215, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19215", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19234, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19234", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19235, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19238, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19238", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19239, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19239", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19240, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19240", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19242, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006f x11:0000006f", "time": "19242", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19243, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19243", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19245, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19245", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19246, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000047", "time": "19246", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19247, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19247", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19248, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000238 x15:00000047", "time": "19248", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19249, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000011c x15:00000047", "time": "19249", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19250, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238", "time": "19250", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19251, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80", "time": "19251", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19252, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038", "time": "19252", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19253, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19254, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104138", "time": "19254", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19258, "dur": 1, "pid": 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"X", "ts": 19262, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19262", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19265, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19265", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19281, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19281", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19290", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19292, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19292", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19293, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000047", "time": "19293", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19294, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19294", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19295, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000238 x15:00000047", "time": "19295", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19296, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000011c x15:00000047", "time": "19296", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19297, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238", "time": "19297", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19298, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80", "time": "19298", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19299, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038", "time": "19299", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19300, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19300", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19301, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104138", "time": "19301", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19305, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19305", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19306, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19306", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19308, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002348 x9:1c002348", "time": "19308", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19309, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19309", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19312, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348", "time": "19312", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19332, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002349 x12:1c002348", "time": "19332", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19333, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000065", "time": "19333", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19336, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000065 x20:00000025", "time": "19336", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19337, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19337", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19338, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19338", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19340, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000065 x11:00000065", "time": "19340", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19341, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19341", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19343, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19344, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000047", "time": "19344", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19348, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238", "time": "19348", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19349, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80", "time": "19349", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19350, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038", "time": "19350", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19352, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104138", "time": "19352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19356, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19356", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19357, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19357", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19359, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002349 x9:1c002349", "time": "19359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19360, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19363, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349", "time": "19363", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19381, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234a x12:1c002349", "time": "19381", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19392, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000047", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19394, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19395, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000238 x15:00000047", "time": "19395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19396, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000011c x15:00000047", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19397, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19398, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80", "time": "19398", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19399, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038", "time": "19399", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19400, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19400", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19401, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104138", "time": "19401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19405, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19406, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19406", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19408, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00234a x9:1c00234a", "time": "19408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19409, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19409", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19412, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a", "time": "19412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00234b x12:1c00234a", "time": "19431", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19432, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000028", "time": "19432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19435, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000028 x20:00000025", "time": "19435", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19436, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19436", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19437, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19439, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000028 x11:00000028", "time": "19439", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19440, "dur": 2, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21171, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "21171", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21172, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "21172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21174, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002352 x9:1c002352", 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"time": "21231", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21232, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21232", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21235, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353", "time": "21235", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21249, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002354 x12:1c002353", "time": "21249", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 21250, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000000a", "time": "21250", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21253, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_02_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000000a x20:00000025", "time": "21253", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 21254, "dur": 1, "pid": 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"instr": "jal x0, 24 ", "time": "16999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000060", "time": "17017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17018, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000000 x10:00000060", "time": "17018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 17035, "dur": 1, "pid": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c002138", "instr": "addi x7, x0, 24 x7=00000018", "time": "17131", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:67"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 17132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c00213a", "instr": "mul x7, x7, x10 x7=00000048 x7:00000018 x10:00000003", "time": "17132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:68"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 17133, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c00213e", "instr": "add x23, x23, x7 x23=1c2fff98 x23:1c2fff50 x7:00000048", "time": "17133", "Origin": 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"1c002146", "instr": "addi x25, x25, -508 x25=10200e04 x25:10201000", "time": "17152", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:81"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17153, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c00214a", "instr": "addi x24, x0, 1 x24=00000001", "time": "17153", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:82"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17154, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c00214c", "instr": "auipc x26, 0x0 x26=1c00214c", "time": "17154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:85"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17171, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c002150", "instr": "addi x26, x26, 224 x26=1c00222c x26:1c00214c", "time": "17171", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:85"}}, +{"name": "ori", "cat": "ori", "ph": "X", "ts": 17172, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c002154", "instr": "ori x26, x26, 1 x26=1c00222d x26:1c00222c", "time": "17172", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:86"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17173, "dur": 35, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_pe_start", "args":{"pc": "1c002158", "instr": "jal x0, 22 ", "time": "17173", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:88"}}, 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"time": "17229", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:188"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17230, "dur": 1457, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021d6", "instr": "p.elw x0, 60(x19) x19:1b204000 PA:1b20403c", "time": "17230", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:189"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 18687, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021da", "instr": "sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004", "time": "18687", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:190"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18688, "dur": 3, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19429, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300", "time": "19429", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19430, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80", "time": "19430", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19431, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000", "time": "19431", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19432, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19432", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19433, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104180", "time": "19433", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19437, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19437", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19438, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19438", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19440, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19440", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19441, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19441", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19444, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19473, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19474, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19474", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19477, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19478, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19478", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19479, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19479", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19481, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19481", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19482, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19482", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19484, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19484", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19485, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000060", "time": "19485", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19486, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19486", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19487, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000300 x15:00000060", "time": "19487", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19488, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000180 x15:00000060", "time": "19488", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19536, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300", "time": "19536", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19537, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80", "time": "19537", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19538, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", 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"X", "ts": 19548, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19548", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19551, "dur": 39, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "19551", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19590, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "19590", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19591, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "19591", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19594, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19594", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19595, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19599", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19601, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19601", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19602, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000060", "time": "19602", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19606, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300", "time": "19606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19607, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80", "time": "19607", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19608, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", 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"X", "ts": 19618, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19618", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19621, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19621", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19639, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19639", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19640, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19640", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19643, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19643", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19644, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19648", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19650, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19650", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19651, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000060", "time": "19651", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19652, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19652", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19653, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000300 x15:00000060", "time": "19653", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19654, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000180 x15:00000060", "time": "19654", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19655, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300", "time": "19655", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19656, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80", "time": "19656", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19657, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000", "time": "19657", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19658, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19658", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19659, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104180", "time": "19659", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19663, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19663", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19664, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19664", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19666, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19666", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19667, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19667", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19670, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19685, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19685", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19686, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19686", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19689, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19690, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19691, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19693, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19693", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19694, "dur": 2, "pid": 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"X", "ts": 19758, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19758", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19761, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19761", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19777, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19777", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19778, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19778", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19781, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19781", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19782, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19786", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19788, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19788", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19789, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000060", "time": "19789", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"X", "ts": 19805, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19805", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19808, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19808", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19823, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19823", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19824, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006f", "time": "19824", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19827, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006f x20:00000025", "time": "19827", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19828, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19832", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19834, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19834", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19835, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000060", "time": "19835", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19836, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19836", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19837, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000300 x15:00000060", "time": "19837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19838, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000180 x15:00000060", "time": "19838", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000", "time": "19841", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19842, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19842", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19843, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104180", "time": "19843", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19850, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002347 x9:1c002347", "time": "19850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19851, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19851", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19854, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347", "time": "19854", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19870, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002348 x12:1c002347", "time": "19870", "Origin": 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"__rt_master_sleep", "args":{"pc": "1c0021d6", "instr": "p.elw x0, 60(x19) x19:1b204000 PA:1b20403c", "time": "21952", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:189"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 21957, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021da", "instr": "sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004", "time": "21957", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:190"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21958, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_master_sleep", "args":{"pc": "1c0021de", "instr": "jal x0, -112 ", "time": "21958", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:191"}}, +{"name": "lw", "cat": "lw", "ph": "X", "ts": 21961, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c00216e", "instr": "lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028", "time": "21961", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:109"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 21963, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_0.log", "tid": "__rt_master_loop", "args":{"pc": "1c002172", "instr": "beq x28, x0, 96 x28:00000000", "time": "21963", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:110"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 16999, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "_start", "args":{"pc": "1c000080", "instr": "jal x0, 24 ", "time": "16999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000061", "time": "17017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17018, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000001 x10:00000061", "time": "17018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 17035, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000003 x10:00000061", "time": "17035", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17036, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000001", "time": "17036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17037, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "17037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17055, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "17055", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17056, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "17056", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17057, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "17057", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17058, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000001", "time": "17058", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17110, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "17110", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17111, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000061", "time": "17111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17112, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000001 x19:00000061", "time": "17112", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17113, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "17113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "17132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "17133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "17134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17135, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "17135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17154, "dur": 1648, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "17154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18802, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18822, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18850, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080", "time": "18850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000400 x19:00000001 x10:00000400", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10cfe800 x10:00000400 x5:10cfe400", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18882, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18884, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18921, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18932, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18950, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000061", "time": "18950", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18971", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": 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x10, x0, x18 x10=00000000 x18:00000000", "time": "19340", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19341, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19341", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19343, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000065 x11:00000065", "time": "19343", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19344, "dur": 2, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19351, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308", "time": "19351", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19352, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80", "time": "19352", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19353, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008", "time": "19353", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19354, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19354", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19355, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104188", "time": "19355", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19359, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19360, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19360", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19362, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233e x9:1c00233e", "time": "19362", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19363, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19363", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19366, "dur": 23, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "19366", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19389, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "19389", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19390, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000079", "time": "19390", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19394, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19395, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19395", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19397, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000079 x11:00000079", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19398, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19398", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19400, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19400", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19401, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000061", "time": "19401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19402, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19403, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000308 x15:00000061", "time": "19403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19404, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000184 x15:00000061", "time": "19404", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19405, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308", "time": "19405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19406, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80", "time": "19406", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19407, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008", "time": "19407", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19408, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19409, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104188", "time": "19409", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19413, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19413", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19414, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19414", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19416, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19416", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19417, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19417", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19420, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19442, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19442", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19443, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19443", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19446, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19446", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19447, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19447", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19448, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19448", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19450, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19450", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19451, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19451", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19453, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19453", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19454, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000061", "time": "19454", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19455, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19455", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19456, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000308 x15:00000061", "time": "19456", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19457, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000184 x15:00000061", "time": "19457", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19458, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308", "time": "19458", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19459, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80", "time": "19459", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19460, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008", "time": "19460", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19462, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104188", "time": "19462", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19466, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19466", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19467, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19467", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19469, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "19469", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19470, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19470", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19473, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "19473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19493, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "19493", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19494, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19494", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19497, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19497", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19498, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19502", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19504, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19504", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19505, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000061", "time": "19505", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19506, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19506", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19507, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000308 x15:00000061", "time": "19507", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19508, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000184 x15:00000061", "time": "19508", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19509, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308", "time": "19509", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19510, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80", "time": "19510", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19511, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008", "time": "19511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19512, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19513, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104188", "time": "19513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19517, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19518, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19520, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "19520", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19521, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19521", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19524, "dur": 26, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "19524", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19550, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "19550", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19551, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "19551", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19554, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19554", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19555, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19555", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19556, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19556", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19558, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "19558", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19559, "dur": 2, "pid": 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"ph": "X", "ts": 19563, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19563", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19564, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000308 x15:00000061", "time": "19564", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19565, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000184 x15:00000061", "time": "19565", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008", "time": "19617", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19618, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19618", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19619, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104188", "time": "19619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19623, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19623", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19624, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19626, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19626", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19627, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19627", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19630, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19630", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19647, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19647", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19650, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19650", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19651, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19655", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19657, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19657", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19658, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000061", "time": "19658", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19662, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308", "time": "19662", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19663, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80", "time": "19663", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19664, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008", "time": "19664", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19665, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19665", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19666, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104188", "time": "19666", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19670, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19671, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19671", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19673, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19673", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19674, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19674", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19677, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19677", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19693, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19693", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19694, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19694", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19697, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19697", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19698, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19699, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19702, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19704, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19704", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19705, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000061", "time": "19705", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19706, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19706", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19707, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000308 x15:00000061", "time": "19707", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19708, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000184 x15:00000061", "time": "19708", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19709, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308", "time": "19709", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19710, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80", "time": "19710", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19711, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008", "time": "19711", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19712, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19712", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19713, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104188", "time": "19713", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19717, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19717", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19718, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19718", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19720, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19721, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19724, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19724", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19741, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19741", "Origin": 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"time": "21738", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21739, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21739", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21742, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353", "time": "21742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21756, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_1.log", "tid": "tfp_format", "args":{"pc": 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"instr": "jal x0, 24 ", "time": "16999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000062", "time": "17017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17018, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000002 x10:00000062", "time": "17018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 17035, "dur": 1, "pid": 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"1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000062", "time": "17111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17112, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000002 x19:00000062", "time": "17112", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17113, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "17113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "17132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "17133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "17134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17135, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "17135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17154, "dur": 1648, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "17154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18802, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18822, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18850, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080", "time": "18850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000800 x19:00000002 x10:00000400", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10cfec00 x10:00000800 x5:10cfe400", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18882, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18884, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18921, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18932, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18950, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000062", "time": "18950", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18971", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000003 x12:00000062", "time": "18972", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003", "time": "18973", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000002 x12:00000062", "time": "18974", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18975", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18976, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18976", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19005, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=10cfebc0 x2:10cfec00", "time": "19005", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19006, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000003 x2:10cfebc0 PA:10cfebe4", "time": "19006", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19011, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "19011", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19012, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000002 x2:10cfebc0 PA:10cfebe8", "time": "19012", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19013, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c00181a", "instr": "sw x13, 44(x2) x13:00000000 x2:10cfebc0 PA:10cfebec", "time": "19013", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19014, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c00181c", "instr": "add x12, x0, x10 x12=1c00233c x10:1c00233c", "time": "19014", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19015, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=10cfebe4 x2:10cfebc0", "time": "19015", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19030, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "19030", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19031, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "19031", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19032, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:10cfebc0 PA:10cfebdc", "time": "19032", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19037, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:10cfebc0 PA:10cfebf0", "time": "19037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19038, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", 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"X", "ts": 19317, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19317", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19320, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d", "time": "19320", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19339, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233e x12:1c00233d", "time": "19339", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19355, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19355", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19356, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19356", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19357, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010", "time": "19357", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19358, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19358", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19359, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104190", "time": "19359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19363, "dur": 1, "pid": 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"X", "ts": 19367, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19367", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19370, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "19370", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19392, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "19392", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19393, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000079", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19396, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19396", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19397, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19398, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19398", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19400, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000079 x11:00000079", "time": "19400", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19401, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19401", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19403, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19403", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19404, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000062", "time": "19404", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19405, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19406, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000310 x15:00000062", "time": "19406", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19407, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000188 x15:00000062", "time": "19407", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19408, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19409, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19409", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19410, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010", "time": "19410", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19411, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19411", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19412, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104190", "time": "19412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19416, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19416", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19417, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19417", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19419, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19419", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19420, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19423, "dur": 20, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19423", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19443, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19443", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19444, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19444", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19447, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19447", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19448, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19448", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19449, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19449", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19451, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19451", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19452, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19452", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19454, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19454", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19455, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000062", "time": "19455", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19456, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19456", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19457, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000310 x15:00000062", "time": "19457", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19458, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000188 x15:00000062", "time": "19458", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19459, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19459", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19460, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19460", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010", "time": "19461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19462", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19463, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104190", "time": "19463", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19467, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19467", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19468, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19468", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19470, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002340 x9:1c002340", "time": "19470", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19471, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19471", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19474, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "19474", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19499, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "19499", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19500, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19500", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19503, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19503", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19504, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19504", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19505, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19505", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19507, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19507", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19508, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19508", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19510, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19510", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19511, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000062", "time": "19511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19512, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19513, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000310 x15:00000062", "time": "19513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19514, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000188 x15:00000062", "time": "19514", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19515, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19515", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19516, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19516", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19517, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010", "time": "19517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19519, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104190", "time": "19519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19523, "dur": 1, "pid": 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"X", "ts": 19527, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19527", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19530, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "19530", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19560, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "19560", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19569", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19571, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19571", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19572, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000062", "time": "19572", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19573, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19573", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19574, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000310 x15:00000062", "time": "19574", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19575, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000188 x15:00000062", "time": "19575", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19576, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19576", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19577, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19577", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19578, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010", "time": "19578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19579, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19580, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104190", "time": "19580", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19584, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19584", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19585, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19585", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19587, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "19587", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19588, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19591, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19591", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19605, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19605", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19606, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19606", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19609, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19609", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19610, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19610", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19611, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19611", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19613, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000027 x11:00000027", "time": "19613", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19614, "dur": 2, "pid": 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"ph": "X", "ts": 19618, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19618", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000310 x15:00000062", "time": "19619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19620, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000188 x15:00000062", "time": "19620", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19621, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19621", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19622, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19622", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19623, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", 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"X", "ts": 19633, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19633", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19636, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19636", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19650, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19650", "Origin": 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"ph": "X", "ts": 19663, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19663", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19664, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000310 x15:00000062", "time": "19664", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19665, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000188 x15:00000062", "time": "19665", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19666, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19666", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19667, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19667", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19668, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010", "time": "19668", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19669, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19669", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19670, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104190", "time": "19670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19674, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19674", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19675, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19675", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19677, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19677", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19678, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19678", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19681, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19681", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19700, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19703, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19703", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19704, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19708", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19710, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19710", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19711, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000062", "time": "19711", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"X", "ts": 19727, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19727", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19730, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19730", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19744, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19744", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19753", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19755, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19755", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19756, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000062", "time": "19756", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19757, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19757", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19758, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000310 x15:00000062", "time": "19758", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19759, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000188 x15:00000062", "time": "19759", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19760, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310", "time": "19760", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19761, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80", "time": "19761", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19762, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010", "time": "19762", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19763, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19763", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19764, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104190", "time": "19764", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19768, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19768", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19769, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19769", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19771, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002346 x9:1c002346", "time": "19771", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19772, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19772", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19775, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19775", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19792, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19792", "Origin": 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x0, 0 x10=00000000", "time": "21837", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21838, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c001838", "instr": "addi x2, x2, 64 x2=10cfec00 x2:10cfebc0", "time": "21838", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 21839, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_2.log", "tid": "printf", "args":{"pc": "1c00183a", "instr": "jalr x0, x1, 0 x1:1c00220c", "time": "21839", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:327"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 16999, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "_start", "args":{"pc": "1c000080", "instr": "jal x0, 24 ", "time": "16999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000063", "time": "17017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17018, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000003 x10:00000063", "time": "17018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 17035, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000003 x10:00000063", "time": "17035", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17036, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000003", "time": "17036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17037, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "17037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17055, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "17055", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17056, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "17056", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17057, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "17057", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17058, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000003", "time": "17058", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17110, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "17110", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17111, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000063", "time": "17111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17112, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000003 x19:00000063", "time": "17112", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17113, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "17113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "17132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "17133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "17134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17135, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "17135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17154, "dur": 1648, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "17154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18802, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18822, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18850, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080", "time": "18850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00000c00 x19:00000003 x10:00000400", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10cff000 x10:00000c00 x5:10cfe400", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18882, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18884, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18921, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_fork_entry", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18971", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000003 x12:00000063", "time": "18972", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003", "time": "18973", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": 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"X", "ts": 19369, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19369", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19372, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e", "time": "19372", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19393, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233f x12:1c00233e", "time": "19393", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19394, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000079", "time": "19394", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19397, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000079 x20:00000025", "time": "19397", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19398, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19402", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19404, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19404", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19405, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000063", "time": "19405", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19406, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19406", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19407, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000318 x15:00000063", "time": "19407", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19408, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000018c x15:00000063", "time": "19408", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19409, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318", "time": "19409", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19410, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80", "time": "19410", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19411, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018", "time": "19411", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19412, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19412", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19413, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104198", "time": "19413", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19417, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19417", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19418, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19418", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19420, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c00233f x9:1c00233f", "time": "19420", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19421, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19421", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19424, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f", "time": "19424", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19449, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002340 x12:1c00233f", "time": "19449", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19450, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000002c", "time": "19450", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19453, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000002c x20:00000025", "time": "19453", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19454, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19454", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19455, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19455", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19457, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000002c x11:0000002c", "time": "19457", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19458, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19458", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19460, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19460", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19461, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000063", "time": "19461", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19462, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19462", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19463, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000318 x15:00000063", "time": "19463", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19464, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000018c x15:00000063", "time": "19464", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19465, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318", "time": "19465", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19466, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80", "time": "19466", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19467, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018", "time": "19467", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19468, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19468", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19469, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104198", "time": "19469", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19473, "dur": 1, "pid": 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"X", "ts": 19477, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19480, "dur": 22, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "19480", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19502, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "19502", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19511", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19513, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19513", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19514, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000063", "time": "19514", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318", "time": "19518", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19519, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80", "time": "19519", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19520, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018", "time": "19520", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19521, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19521", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19522, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104198", "time": "19522", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19526, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19526", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19527, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19527", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19529, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002341 x9:1c002341", "time": "19529", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19530, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19530", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19533, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341", "time": "19533", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19570, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002342 x12:1c002341", "time": "19570", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19571, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "19571", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19574, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19574", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19575, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19575", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19576, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19576", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19578, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000049 x11:00000049", "time": "19578", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19579, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19579", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19581, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19581", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19582, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000063", "time": "19582", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19583, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19583", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19584, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000318 x15:00000063", "time": "19584", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19585, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000018c x15:00000063", "time": "19585", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19586, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318", "time": "19586", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19587, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80", "time": "19587", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19588, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018", "time": "19588", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19589, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19589", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19590, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104198", "time": "19590", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19594, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19594", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19595, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19595", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19597, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002342 x9:1c002342", "time": "19597", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19598, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19598", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19601, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19601", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19615, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19615", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19616, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19616", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19619, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19619", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19620, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19626, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19626", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19627, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000063", "time": "19627", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19628, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19628", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19629, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000318 x15:00000063", "time": "19629", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19630, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000018c x15:00000063", "time": "19630", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19631, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318", "time": "19631", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19632, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80", "time": "19632", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19633, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018", "time": "19633", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19634, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19634", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19635, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104198", "time": "19635", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19639, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19639", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19640, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19640", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19642, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19642", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19643, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19643", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19646, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19660, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19660", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19661, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19661", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19664, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19664", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19665, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19665", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19666, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19666", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19668, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19668", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19669, "dur": 2, "pid": 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"time": "21744", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 21745, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "21745", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 21748, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353", "time": "21748", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 21766, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_3.log", "tid": "tfp_format", "args":{"pc": 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"__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18822, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18850, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080", "time": "18850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001000 x19:00000004 x10:00000400", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10cff400 x10:00001000 x5:10cfe400", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18882, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18884, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18921, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18932, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18950, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000064", "time": "18950", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18971", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000003 x12:00000064", "time": "18972", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003", "time": "18973", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000004 x12:00000064", "time": "18974", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18975", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18976, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18976", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19005, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=10cff3c0 x2:10cff400", "time": "19005", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19006, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000003 x2:10cff3c0 PA:10cff3e4", "time": "19006", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19008, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "19008", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19009, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000004 x2:10cff3c0 PA:10cff3e8", "time": "19009", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19010, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c00181a", "instr": "sw x13, 44(x2) x13:00000000 x2:10cff3c0 PA:10cff3ec", "time": "19010", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19011, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c00181c", "instr": "add x12, x0, x10 x12=1c00233c x10:1c00233c", "time": "19011", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19012, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=10cff3e4 x2:10cff3c0", "time": "19012", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19030, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "19030", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19031, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "19031", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19032, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:10cff3c0 PA:10cff3dc", "time": "19032", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19033, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:10cff3c0 PA:10cff3f0", "time": "19033", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19034, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:10cff3c0 PA:10cff3f4", "time": "19034", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19035, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c00182c", "instr": "sw x16, 56(x2) x16:00000000 x2:10cff3c0 PA:10cff3f8", "time": "19035", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19036, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:10cff3c0 PA:10cff3fc", "time": "19036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19057, "dur": 6, "pid": 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"ph": "X", "ts": 19413, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19413", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19414, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000320 x15:00000064", "time": "19414", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19415, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000190 x15:00000064", "time": "19415", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020", "time": "19471", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19472, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19472", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19473, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041a0", "time": "19473", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19477, "dur": 1, "pid": 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"X", "ts": 19481, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19481", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19484, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340", "time": "19484", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19503, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002341 x12:1c002340", "time": "19503", "Origin": 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19512", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19514, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19514", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19515, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000064", "time": "19515", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19516, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19516", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19517, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000320 x15:00000064", "time": "19517", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19518, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000190 x15:00000064", "time": "19518", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19597, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320", "time": "19597", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19598, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80", "time": "19598", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19599, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020", "time": "19599", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19600, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19600", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19601, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1041a0", "time": "19601", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19605, "dur": 1, "pid": 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"X", "ts": 19609, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19609", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19612, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19612", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19627, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19627", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19628, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000027", "time": "19628", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19631, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000027 x20:00000025", "time": "19631", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19632, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19636", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19638, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19638", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19639, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000064", "time": "19639", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19643, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320", "time": "19643", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19644, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80", "time": "19644", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19645, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020", "time": "19645", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19646, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19646", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19647, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1041a0", "time": "19647", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19651, "dur": 1, "pid": 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"X", "ts": 19655, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19655", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19658, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19658", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19672, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19672", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19673, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19673", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19676, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19676", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19677, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19681", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19683, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19683", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19684, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000064", "time": "19684", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19685, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19685", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19686, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000320 x15:00000064", "time": "19686", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19687, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000190 x15:00000064", "time": "19687", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19688, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320", "time": "19688", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19689, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80", "time": "19689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19690, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020", "time": "19690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19691, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19692, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1041a0", "time": "19692", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19696, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19696", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19697, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19697", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19700, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19703, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19703", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19717, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19717", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19718, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19718", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19721, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19721", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19722, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19722", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19723, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19723", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19725, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19725", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19726, "dur": 2, "pid": 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"X", "ts": 19790, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19790", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19793, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19793", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19807, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_4.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19807", "Origin": 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"instr": "jal x0, 24 ", "time": "16999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000065", "time": "17017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17018, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000005 x10:00000065", "time": "17018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 17035, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000003 x10:00000065", "time": "17035", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17036, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000005", "time": "17036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17037, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "17037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17055, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "17055", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17056, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "17056", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17057, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "17057", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17058, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000005", "time": "17058", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17110, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "17110", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17111, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000065", "time": "17111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17112, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000005 x19:00000065", "time": "17112", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17113, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "17113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "17132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "17133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "17134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17135, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "17135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17154, "dur": 1648, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "17154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18802, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18822, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18850, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080", "time": "18850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001400 x19:00000005 x10:00000400", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10cff800 x10:00001400 x5:10cfe400", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18882, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18884, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18921, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18932, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18950, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000065", "time": "18950", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18971, "dur": 1, "pid": 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"X", "ts": 19317, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19317", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19320, "dur": 33, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d", "time": "19320", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19353, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c00233e x12:1c00233d", "time": "19353", "Origin": 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x10, x0, x18 x10=00000000 x18:00000000", "time": "19358", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19359, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19359", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19361, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000065 x11:00000065", "time": "19361", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19362, "dur": 2, "pid": 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"ph": "X", "ts": 19366, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19366", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19367, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000328 x15:00000065", "time": "19367", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19368, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000194 x15:00000065", "time": "19368", "Origin": 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"ph": "X", "ts": 19476, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19476", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19477, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000328 x15:00000065", "time": "19477", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19478, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000194 x15:00000065", "time": "19478", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19479, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328", "time": "19479", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19480, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80", "time": "19480", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19481, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", 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"ph": "X", "ts": 19599, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19599", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19600, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000328 x15:00000065", "time": "19600", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19601, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000194 x15:00000065", "time": "19601", "Origin": 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"X", "ts": 19614, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19614", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19617, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19617", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19635, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19635", "Origin": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19651, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328", "time": "19651", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19652, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80", "time": "19652", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19653, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028", "time": "19653", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19654, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19654", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19655, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1041a8", "time": "19655", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19659, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19659", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19660, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19660", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19662, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19662", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19663, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19663", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19666, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19666", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19681, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19681", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19682, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19682", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19685, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19685", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19686, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19686", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19687, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19687", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19689, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19690, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19692, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19692", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19693, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000065", "time": "19693", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19697, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328", "time": "19697", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19698, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80", "time": "19698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19742, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328", "time": "19742", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19743, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80", "time": "19743", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19744, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19750", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19751, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19751", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19753, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19753", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19754, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19754", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19757, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19757", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19771, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_5.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19771", "Origin": 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"instr": "jal x0, 24 ", "time": "16999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000066", "time": "17017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17018, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000006 x10:00000066", "time": "17018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 17035, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17135, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "17135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17154, "dur": 1648, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "17154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18802, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18822, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18850, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080", "time": "18850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001800 x19:00000006 x10:00000400", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10cffc00 x10:00001800 x5:10cfe400", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18882, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18884, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18921, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18932, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18950, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000066", "time": "18950", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18971, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "core_entry", "args":{"pc": "1c0009c0", "instr": "lui x10, 0x1c002000 x10=1c002000", "time": "18971", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "srai", "cat": "srai", "ph": "X", "ts": 18972, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009c4", "instr": "srai x11, x12, 0x405 x11=00000003 x12:00000066", "time": "18972", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:187"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18973, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "core_entry", "args":{"pc": "1c0009c8", "instr": "p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003", "time": "18973", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 18974, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "core_entry", "args":{"pc": "1c0009cc", "instr": "p.bclr x12, x12, 26, 5 x12=00000006 x12:00000066", "time": "18974", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 18975, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "core_entry", "args":{"pc": "1c0009d0", "instr": "addi x10, x10, 828 x10=1c00233c x10:1c002000", "time": "18975", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 18976, "dur": 29, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "core_entry", "args":{"pc": "1c0009d4", "instr": "jal x0, 3644 ", "time": "18976", "Origin": "/scratch/digirols/pulp_api_example/main.c:48"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19005, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001810", "instr": "addi x2, x2, -64 x2=10cffbc0 x2:10cffc00", "time": "19005", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19006, "dur": 6, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001812", "instr": "sw x11, 36(x2) x11:00000003 x2:10cffbc0 PA:10cffbe4", "time": "19006", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19012, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001814", "instr": "lui x11, 0x1c001000 x11=1c001000", "time": "19012", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19013, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001818", "instr": "sw x12, 40(x2) x12:00000006 x2:10cffbc0 PA:10cffbe8", "time": "19013", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19014, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c00181a", "instr": "sw x13, 44(x2) x13:00000000 x2:10cffbc0 PA:10cffbec", "time": "19014", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19015, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c00181c", "instr": "add x12, x0, x10 x12=1c00233c x10:1c00233c", "time": "19015", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19016, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c00181e", "instr": "addi x13, x2, 36 x13=10cffbe4 x2:10cffbc0", "time": "19016", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19030, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001820", "instr": "addi x10, x0, 0 x10=00000000", "time": "19030", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19031, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001822", "instr": "addi x11, x11, 1910 x11=1c001776 x11:1c001000", "time": "19031", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19032, "dur": 7, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001826", "instr": "sw x1, 28(x2) x1:1c00220c x2:10cffbc0 PA:10cffbdc", "time": "19032", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19039, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001828", "instr": "sw x14, 48(x2) x14:00000000 x2:10cffbc0 PA:10cffbf0", "time": "19039", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19040, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c00182a", "instr": "sw x15, 52(x2) x15:00000000 x2:10cffbc0 PA:10cffbf4", "time": "19040", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19041, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c00182c", "instr": "sw x16, 56(x2) x16:00000000 x2:10cffbc0 PA:10cffbf8", "time": "19041", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19042, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c00182e", "instr": "sw x17, 60(x2) x17:00000000 x2:10cffbc0 PA:10cffbfc", "time": "19042", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:315"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19057, "dur": 7, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001830", "instr": "sw x13, 12(x2) x13:10cffbe4 x2:10cffbc0 PA:10cffbcc", "time": "19057", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:320"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19064, "dur": 13, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "printf", "args":{"pc": "1c001832", "instr": "jal x1, 830 x1=1c001834", "time": "19064", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:321"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19077, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001b70", "instr": "addi x2, x2, -96 x2=10cffb60 x2:10cffbc0", "time": "19077", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19078, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001b72", "instr": "addi x15, x2, 24 x15=10cffb78 x2:10cffb60", "time": "19078", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:278"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19079, "dur": 5, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001b74", "instr": "sw x8, 88(x2) x8:00000000 x2:10cffb60 PA:10cffbb8", "time": "19079", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:270"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 19084, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001b76", "instr": "sw x18, 80(x2) x18:1b204000 x2:10cffb60 PA:10cffbb0", "time": "19084", "Origin": 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"X", "ts": 19669, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19669", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19672, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19672", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19687, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19687", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19688, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19688", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19691, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19691", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19692, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19696", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19698, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19699, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000066", "time": "19699", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19700, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000330 x15:00000066", "time": "19701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19702, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=00000198 x15:00000066", "time": "19702", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19703, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330", "time": "19703", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19704, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80", "time": "19704", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19705, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030", "time": "19705", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19706, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19706", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19707, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1041b0", "time": "19707", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19711, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19711", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19712, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19712", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19714, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19714", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19715, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19715", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19718, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19718", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19732, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19732", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19733, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19733", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19736, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19736", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19737, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19737", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19738, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19738", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19740, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000020 x11:00000020", "time": "19740", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19741, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19741", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19743, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19743", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19744, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000066", "time": "19744", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19748, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330", "time": "19748", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19749, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80", "time": "19749", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19750, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "__rt_putc_stdout", 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"X", "ts": 19806, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19806", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19809, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346", "time": "19809", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19825, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_6.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002347 x12:1c002346", "time": "19825", "Origin": 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"instr": "jal x0, 24 ", "time": "16999", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:191"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17017, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "_entry", "args":{"pc": "1c000098", "instr": "csrrs x10, x0, 0xf14 x10=00000067", "time": "17017", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:31"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17018, "dur": 17, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "_entry", "args":{"pc": "1c00009c", "instr": "andi x11, x10, 31 x11=00000007 x10:00000067", "time": "17018", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:35"}}, +{"name": "srli", "cat": "srli", "ph": "X", "ts": 17035, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "_entry", "args":{"pc": "1c0000a0", "instr": "srli x10, x10, 0x5 x10=00000003 x10:00000067", "time": "17035", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:36"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 17036, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "_entry", "args":{"pc": "1c0000a2", "instr": "beq x11, x0, 8 x11:00000007", "time": "17036", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17037, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "_entry", "args":{"pc": "1c0000a6", "instr": "jal x0, 8282 ", "time": "17037", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/rt/crt0.S:43"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17055, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c002100", "instr": "lui x5, 0x70000 x5=00070000", "time": "17055", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:47"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17056, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c002104", "instr": "lui x6, 0x1b204000 x6=1b204000", "time": "17056", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:48"}}, +{"name": "sw", "cat": "sw", "ph": "X", "ts": 17057, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c002108", "instr": "sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000", "time": "17057", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:49"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 17058, "dur": 52, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_pe_start", "args":{"pc": "1c00210c", "instr": "bne x11, x0, 226 x11:00000007", "time": "17058", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:55"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 17110, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021ee", "instr": "lui x18, 0x1b204000 x18=1b204000", "time": "17110", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:213"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 17111, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f2", "instr": "csrrs x19, x0, 0xf14 x19=00000067", "time": "17111", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:214"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 17112, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021f6", "instr": "andi x19, x19, 31 x19=00000007 x19:00000067", "time": "17112", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:215"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17113, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fa", "instr": "auipc x20, 0x0 x20=1c0021fa", "time": "17113", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17132, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c0021fe", "instr": "addi x20, x20, 18 x20=1c00220c x20:1c0021fa", "time": "17132", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:216"}}, +{"name": "auipc", "cat": "auipc", "ph": "X", "ts": 17133, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c002202", "instr": "auipc x21, 0x0 x21=1c002202", "time": "17133", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 17134, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c002206", "instr": "addi x21, x21, 14 x21=1c002210 x21:1c002202", "time": "17134", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:217"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 17135, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_slave_start", "args":{"pc": "1c00220a", "instr": "jal x0, 6 ", "time": "17135", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:218"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 17154, "dur": 1648, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080", "time": "17154", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18802, "dur": 19, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080", "time": "18802", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18821, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000001 x5:1c00222d", "time": "18821", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18822, "dur": 25, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000001", "time": "18822", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18847, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_other_entry", "args":{"pc": "1c002226", "instr": "add x1, x21, x0 x1=1c002210 x21:1c002210", "time": "18847", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:255"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18848, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_other_entry", "args":{"pc": "1c00222a", "instr": "jalr x0, x5, 0 x5:1c00222d", "time": "18848", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:256"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18850, "dur": 30, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c00222c", "instr": "p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080", "time": "18850", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:264"}}, +{"name": "mul", "cat": "mul", "ph": "X", "ts": 18880, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002230", "instr": "mul x10, x19, x10 x10=00001c00 x19:00000007 x10:00000400", "time": "18880", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:270"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18881, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002234", "instr": "add x2, x10, x5 x2=10d00000 x10:00001c00 x5:10cfe400", "time": "18881", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:271"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18882, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_set_slave_stack", "args":{"pc": "1c002238", "instr": "jalr x0, x1, 0 x1:1c002210", "time": "18882", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:272"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18884, "dur": 37, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002210", "instr": "p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080", "time": "18884", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:239"}}, +{"name": "p.elw", "cat": "p.elw", "ph": "X", "ts": 18921, "dur": 8, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002214", "instr": "p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080", "time": "18921", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:240"}}, +{"name": "andi", "cat": "andi", "ph": "X", "ts": 18929, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c002218", "instr": "andi x6, x5, 1 x6=00000000 x5:1c0009bc", "time": "18929", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:243"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 18930, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_wait_for_dispatch", "args":{"pc": "1c00221c", "instr": "bne x6, x0, 10 x6:00000000", "time": "18930", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:244"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 18931, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002220", "instr": "add x1, x20, x0 x1=1c00220c x20:1c00220c", "time": "18931", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:249"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 18932, "dur": 18, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_fork_entry", "args":{"pc": "1c002224", "instr": "jalr x0, x5, 0 x5:1c0009bc", "time": "18932", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/kernel/riscv/pe-eu-v3.S:250"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 18950, "dur": 21, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "hal_cluster_id", "args":{"pc": "1c0009bc", "instr": "csrrs x12, x0, 0xf14 x12=00000067", "time": "18950", "Origin": "/scratch/digirols/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:181"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 18971, "dur": 1, "pid": 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19597, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000049", "time": "19597", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19600, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000049 x20:00000025", "time": "19600", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19601, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19605", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19607, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19607", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19608, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000067", "time": "19608", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19609, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19609", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19610, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000338 x15:00000067", "time": "19610", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19611, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000019c x15:00000067", "time": "19611", "Origin": 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"args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038", "time": "19614", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19615, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19615", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19616, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1041b8", "time": "19616", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19620, "dur": 1, "pid": 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"X", "ts": 19624, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19624", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19627, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342", "time": "19627", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19642, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002343 x12:1c002342", "time": "19642", "Origin": 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"ph": "X", "ts": 19655, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19655", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19656, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000338 x15:00000067", "time": "19656", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19657, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000019c x15:00000067", "time": "19657", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19658, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338", "time": "19658", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19659, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80", "time": "19659", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19660, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038", "time": "19660", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19661, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19661", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19662, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1041b8", "time": "19662", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19666, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19666", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19667, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19667", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19669, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002343 x9:1c002343", "time": "19669", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19670, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19670", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19673, "dur": 16, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343", "time": "19673", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19689, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002344 x12:1c002343", "time": "19689", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19690, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:0000006d", "time": "19690", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19693, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:0000006d x20:00000025", "time": "19693", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19694, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19694", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19695, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19695", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19697, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=0000006d x11:0000006d", "time": "19697", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19698, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19698", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19700, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19700", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19701, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000067", "time": "19701", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", 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"/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19705, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338", "time": "19705", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19706, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80", "time": "19706", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19707, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038", "time": "19707", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19708, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19708", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19709, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1041b8", "time": "19709", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19713, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19713", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19714, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19714", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19716, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002344 x9:1c002344", "time": "19716", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19717, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19717", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19720, "dur": 15, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344", "time": "19720", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19735, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002345 x12:1c002344", "time": "19735", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19736, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000020", "time": "19736", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19739, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000020 x20:00000025", "time": "19739", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19740, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add 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"/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_putc", "args":{"pc": "1c001778", "instr": "jal x0, -36 ", "time": "19744", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19746, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001754", "instr": "lui x13, 0x2000 x13=00002000", "time": "19746", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "csrrs", "cat": "csrrs", "ph": "X", "ts": 19747, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "hal_core_id", "args":{"pc": "1c001756", "instr": "csrrs x15, x0, 0xf14 x15=00000067", "time": "19747", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/pkg/sdk/dev/install/include/hal/riscv/riscv_v4.h:166"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19748, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175a", "instr": "addi x13, x13, -128 x13=00001f80 x13:00002000", "time": "19748", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19749, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00175e", "instr": "slli x14, x15, 0x3 x14=00000338 x15:00000067", "time": "19749", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "slli", "cat": "slli", "ph": "X", "ts": 19750, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001762", "instr": "slli x15, x15, 0x2 x15=0000019c x15:00000067", "time": "19750", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.bclr", "cat": "p.bclr", "ph": "X", "ts": 19751, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001764", "instr": "p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338", "time": "19751", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "and", "cat": "and", "ph": "X", "ts": 19752, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001768", "instr": "and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80", "time": "19752", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19753, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176a", "instr": "add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038", "time": "19753", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "lui", "cat": "lui", "ph": "X", "ts": 19754, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c00176c", "instr": "lui x14, 0x1a104000 x14=1a104000", "time": "19754", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "p.sw", "cat": "p.sw", "ph": "X", "ts": 19755, "dur": 4, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001770", "instr": "p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b8", "time": "19755", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:155"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19759, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "__rt_putc_stdout", "args":{"pc": "1c001774", "instr": "jalr x0, x1, 0 x1:1c001bca", "time": "19759", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:159"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19760, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bca", "instr": "jal x0, 362 ", "time": "19760", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19762, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001d34", "instr": "add x12, x0, x9 x12=1c002345 x9:1c002345", "time": "19762", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19763, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001d36", "instr": "jal x0, -408 ", "time": "19763", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:354"}}, +{"name": "lbu", "cat": "lbu", "ph": "X", "ts": 19766, "dur": 14, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001b9e", "instr": "lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345", "time": "19766", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "addi", "cat": "addi", "ph": "X", "ts": 19780, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba2", "instr": "addi x9, x12, 1 x9=1c002346 x12:1c002345", "time": "19780", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "bne", "cat": "bne", "ph": "X", "ts": 19781, "dur": 3, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001ba6", "instr": "bne x11, x0, 28 x11:00000063", "time": "19781", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:280"}}, +{"name": "beq", "cat": "beq", "ph": "X", "ts": 19784, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc2", "instr": "beq x11, x20, 10 x11:00000063 x20:00000025", "time": "19784", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:281"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19785, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc6", "instr": "add x10, x0, x18 x10=00000000 x18:00000000", "time": "19785", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "jalr", "cat": "jalr", "ph": "X", "ts": 19786, "dur": 2, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_format", "args":{"pc": "1c001bc8", "instr": "jalr x1, x19, 0 x1=1c001bca x19:1c001776", "time": "19786", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/tinyprintf.c:433"}}, +{"name": "add", "cat": "add", "ph": "X", "ts": 19788, "dur": 1, "pid": "/home/salvo/ETH/mulix/pulp_spin/spinningpulp_v0.2/vsim/trace_core_03_7.log", "tid": "tfp_putc", "args":{"pc": "1c001776", "instr": "add x10, x0, x11 x10=00000063 x11:00000063", "time": "19788", "Origin": "/scratch/andkurt/pulp_spin/pulp-sdk/runtime/pulp-rt/libs/io/io.c:251"}}, +{"name": "jal", "cat": "jal", "ph": "X", "ts": 19789, "dur": 2, "pid": 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x5:1c002648 PA:1c002648 + 1226500 1211 1c0000c6 00428293 addi x5, x5, 4 x5=1c00264c x5:1c002648 + 1227500 1212 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c00264c x6:1c0026ac + 1256500 1241 1c0000c2 0002a023 sw x0, 0(x5) x5:1c00264c PA:1c00264c + 1274500 1259 1c0000c6 00428293 addi x5, x5, 4 x5=1c002650 x5:1c00264c + 1275500 1260 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002650 x6:1c0026ac + 1304500 1289 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002650 PA:1c002650 + 1322500 1307 1c0000c6 00428293 addi x5, x5, 4 x5=1c002654 x5:1c002650 + 1323500 1308 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002654 x6:1c0026ac + 1352500 1337 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002654 PA:1c002654 + 1370500 1355 1c0000c6 00428293 addi x5, x5, 4 x5=1c002658 x5:1c002654 + 1371500 1356 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002658 x6:1c0026ac + 1400500 1385 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002658 PA:1c002658 + 1418500 1403 1c0000c6 00428293 addi x5, x5, 4 x5=1c00265c x5:1c002658 + 1419500 1404 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c00265c x6:1c0026ac + 1448500 1433 1c0000c2 0002a023 sw x0, 0(x5) x5:1c00265c PA:1c00265c + 1466500 1451 1c0000c6 00428293 addi x5, x5, 4 x5=1c002660 x5:1c00265c + 1467500 1452 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002660 x6:1c0026ac + 1496500 1481 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002660 PA:1c002660 + 1514500 1499 1c0000c6 00428293 addi x5, x5, 4 x5=1c002664 x5:1c002660 + 1515500 1500 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002664 x6:1c0026ac + 1544500 1529 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002664 PA:1c002664 + 1562500 1547 1c0000c6 00428293 addi x5, x5, 4 x5=1c002668 x5:1c002664 + 1563500 1548 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002668 x6:1c0026ac + 1592500 1577 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002668 PA:1c002668 + 1610500 1595 1c0000c6 00428293 addi x5, x5, 4 x5=1c00266c x5:1c002668 + 1611500 1596 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c00266c x6:1c0026ac + 1640500 1625 1c0000c2 0002a023 sw x0, 0(x5) x5:1c00266c PA:1c00266c + 1658500 1643 1c0000c6 00428293 addi x5, x5, 4 x5=1c002670 x5:1c00266c + 1659500 1644 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002670 x6:1c0026ac + 1688500 1673 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002670 PA:1c002670 + 1706500 1691 1c0000c6 00428293 addi x5, x5, 4 x5=1c002674 x5:1c002670 + 1707500 1692 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002674 x6:1c0026ac + 1736500 1721 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002674 PA:1c002674 + 1754500 1739 1c0000c6 00428293 addi x5, x5, 4 x5=1c002678 x5:1c002674 + 1755500 1740 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002678 x6:1c0026ac + 1784500 1769 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002678 PA:1c002678 + 1802500 1787 1c0000c6 00428293 addi x5, x5, 4 x5=1c00267c x5:1c002678 + 1803500 1788 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c00267c x6:1c0026ac + 1832500 1817 1c0000c2 0002a023 sw x0, 0(x5) x5:1c00267c PA:1c00267c + 1850500 1835 1c0000c6 00428293 addi x5, x5, 4 x5=1c002680 x5:1c00267c + 1851500 1836 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002680 x6:1c0026ac + 1880500 1865 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002680 PA:1c002680 + 1898500 1883 1c0000c6 00428293 addi x5, x5, 4 x5=1c002684 x5:1c002680 + 1899500 1884 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002684 x6:1c0026ac + 1928500 1913 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002684 PA:1c002684 + 1946500 1931 1c0000c6 00428293 addi x5, x5, 4 x5=1c002688 x5:1c002684 + 1947500 1932 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002688 x6:1c0026ac + 1976500 1961 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002688 PA:1c002688 + 1994500 1979 1c0000c6 00428293 addi x5, x5, 4 x5=1c00268c x5:1c002688 + 1995500 1980 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c00268c x6:1c0026ac + 2024500 2009 1c0000c2 0002a023 sw x0, 0(x5) x5:1c00268c PA:1c00268c + 2042500 2027 1c0000c6 00428293 addi x5, x5, 4 x5=1c002690 x5:1c00268c + 2043500 2028 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002690 x6:1c0026ac + 2072500 2057 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002690 PA:1c002690 + 2090500 2075 1c0000c6 00428293 addi x5, x5, 4 x5=1c002694 x5:1c002690 + 2091500 2076 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002694 x6:1c0026ac + 2120500 2105 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002694 PA:1c002694 + 2138500 2123 1c0000c6 00428293 addi x5, x5, 4 x5=1c002698 x5:1c002694 + 2139500 2124 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c002698 x6:1c0026ac + 2168500 2153 1c0000c2 0002a023 sw x0, 0(x5) x5:1c002698 PA:1c002698 + 2186500 2171 1c0000c6 00428293 addi x5, x5, 4 x5=1c00269c x5:1c002698 + 2187500 2172 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c00269c x6:1c0026ac + 2216500 2201 1c0000c2 0002a023 sw x0, 0(x5) x5:1c00269c PA:1c00269c + 2234500 2219 1c0000c6 00428293 addi x5, x5, 4 x5=1c0026a0 x5:1c00269c + 2235500 2220 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c0026a0 x6:1c0026ac + 2264500 2249 1c0000c2 0002a023 sw x0, 0(x5) x5:1c0026a0 PA:1c0026a0 + 2282500 2267 1c0000c6 00428293 addi x5, x5, 4 x5=1c0026a4 x5:1c0026a0 + 2283500 2268 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c0026a4 x6:1c0026ac + 2312500 2297 1c0000c2 0002a023 sw x0, 0(x5) x5:1c0026a4 PA:1c0026a4 + 2330500 2315 1c0000c6 00428293 addi x5, x5, 4 x5=1c0026a8 x5:1c0026a4 + 2331500 2316 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c0026a8 x6:1c0026ac + 2360500 2345 1c0000c2 0002a023 sw x0, 0(x5) x5:1c0026a8 PA:1c0026a8 + 2378500 2363 1c0000c6 00428293 addi x5, x5, 4 x5=1c0026ac x5:1c0026a8 + 2379500 2364 1c0000c8 fe62ede3 bltu x5, x6, -6 x5:1c0026ac x6:1c0026ac + 2380500 2365 1c0000cc f4001117 auipc x2, 0xf4001000 x2=100010cc + 2394500 2379 1c0000d0 8c410113 addi x2, x2, -1852 x2=10000990 x2:100010cc + 2395500 2380 1c0000d4 3a1000ef jal x1, 2976 x1=1c0000d8 + 2410500 2395 1c000c74 fe010113 addi x2, x2, -32 x2=10000970 x2:10000990 + 2411500 2396 1c000c76 00112e23 sw x1, 28(x2) x1:1c0000d8 x2:10000970 PA:1000098c + 2412500 2397 1c000c78 00812c23 sw x8, 24(x2) x8:00000000 x2:10000970 PA:10000988 + 2413500 2398 1c000c7a 00912a23 sw x9, 20(x2) x9:00000000 x2:10000970 PA:10000984 + 2414500 2399 1c000c7c 02010413 addi x8, x2, 32 x8=10000990 x2:10000970 + 2415500 2400 1c000c7e 01212823 sw x18, 16(x2) x18:00000000 x2:10000970 PA:10000980 + 2428500 2413 1c000c80 01312623 sw x19, 12(x2) x19:00000000 x2:10000970 PA:1000097c + 2429500 2414 1c000c82 01412423 sw x20, 8(x2) x20:00000000 x2:10000970 PA:10000978 + 2430500 2415 1c000c84 1b2017b7 lui x15, 0x1b201000 x15=1b201000 + 2431500 2416 1c000c88 fff00713 addi x14, x0, -1 x14=ffffffff + 2432500 2417 1c000c8a 40e7a023 sw x14, 1024(x15) x14:ffffffff x15:1b201000 PA:1b201400 + 2450500 2435 1c000c8e 100004b7 lui x9, 0x10000000 x9=10000000 + 2451500 2436 1c000c92 156000ef jal x1, 342 x1=1c000c94 + 2526500 2511 1c000de8 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 2527500 2512 1c000dec fff00713 addi x14, x0, -1 x14=ffffffff + 2528500 2513 1c000dee 00e7a823 sw x14, 16(x15) x14:ffffffff x15:1b204000 PA:1b204010 + 2544500 2529 1c000df0 1c0007b7 lui x15, 0x1c000000 x15=1c000000 + 2545500 2530 1c000df4 1b200737 lui x14, 0x1b200000 x14=1b200000 + 2546500 2531 1c000df8 00078793 addi x15, x15, 0 x15=1c000000 x15:1c000000 + 2547500 2532 1c000dfc 04f72023 sw x15, 64(x14) x15:1c000000 x14:1b200000 PA:1b200040 + 2551500 2536 1c000dfe 00008067 jalr x0, x1, 0 x1:1c000c94 + 2581500 2566 1c000c94 16848493 addi x9, x9, 360 x9=10000168 x9:10000000 + 2582500 2567 1c000c98 1d6000ef jal x1, 470 x1=1c000c9a + 2617500 2602 1c000e6e 100007b7 lui x15, 0x10000000 x15=10000000 + 2618500 2603 1c000e72 05878793 addi x15, x15, 88 x15=10000058 x15:10000000 + 2619500 2604 1c000e76 0007a023 sw x0, 0(x15) x15:10000058 PA:10000058 + 2620500 2605 1c000e7a 0007a223 sw x0, 4(x15) x15:10000058 PA:1000005c + 2637500 2622 1c000e7e 0007a423 sw x0, 8(x15) x15:10000058 PA:10000060 + 2638500 2623 1c000e82 0007a623 sw x0, 12(x15) x15:10000058 PA:10000064 + 2639500 2624 1c000e86 0007a823 sw x0, 16(x15) x15:10000058 PA:10000068 + 2640500 2625 1c000e8a 0007aa23 sw x0, 20(x15) x15:10000058 PA:1000006c + 2641500 2626 1c000e8e 00008067 jalr x0, x1, 0 x1:1c000c9a + 2659500 2644 1c000c9a 5d0000ef jal x1, 1488 x1=1c000c9c + 2677500 2662 1c00126a ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 2678500 2663 1c00126c 00812423 sw x8, 8(x2) x8:10000990 x2:10000960 PA:10000968 + 2695500 2680 1c00126e 002ce437 lui x8, 0x2ce000 x8=002ce000 + 2696500 2681 1c001272 94c40413 addi x8, x8, -1716 x8=002cd94c x8:002ce000 + 2697500 2682 1c001276 00912223 sw x9, 4(x2) x9:10000168 x2:10000960 PA:10000964 + 2698500 2683 1c001278 1c002537 lui x10, 0x1c002000 x10=1c002000 + 2699500 2684 1c00127c 1c0024b7 lui x9, 0x1c002000 x9=1c002000 + 2716500 2701 1c001280 00800633 add x12, x0, x8 x12=002cd94c x8:002cd94c + 2717500 2702 1c001282 6b448593 addi x11, x9, 1716 x11=1c0026b4 x9:1c002000 + 2718500 2703 1c001286 6a050513 addi x10, x10, 1696 x10=1c0026a0 x10:1c002000 + 2719500 2704 1c00128a 00112623 sw x1, 12(x2) x1:1c000c9c x2:10000960 PA:1000096c + 2720500 2705 1c00128c ea7ff0ef jal x1, -346 x1=1c00128e + 2754500 2739 1c001132 00758793 addi x15, x11, 7 x15=1c0026bb x11:1c0026b4 + 2755500 2740 1c001136 c407b7b3 p.bclr x15, x15, 2, 0 x15=1c0026b8 x15:1c0026bb + 2756500 2741 1c00113a 40b785b3 sub x11, x15, x11 x11=00000004 x15:1c0026b8 x11:1c0026b4 + 2757500 2742 1c00113e 00f52023 sw x15, 0(x10) x15:1c0026b8 x10:1c0026a0 PA:1c0026a0 + 2776500 2761 1c001140 40b60633 sub x12, x12, x11 x12=002cd948 x12:002cd94c x11:00000004 + 2777500 2762 1c001142 00c05763 bge x0, x12, 14 x12:002cd948 + 2778500 2763 1c001146 c4063633 p.bclr x12, x12, 2, 0 x12=002cd948 x12:002cd948 + 2779500 2764 1c00114a 00c7a023 sw x12, 0(x15) x12:002cd948 x15:1c0026b8 PA:1c0026b8 + 2797500 2782 1c00114c 0007a223 sw x0, 4(x15) x15:1c0026b8 PA:1c0026bc + 2815500 2800 1c001150 00008067 jalr x0, x1, 0 x1:1c00128e + 2816500 2801 1c00128e 6b448593 addi x11, x9, 1716 x11=1c0026b4 x9:1c002000 + 2817500 2802 1c001292 008585b3 add x11, x11, x8 x11=1c2d0000 x11:1c0026b4 x8:002cd94c + 2818500 2803 1c001294 1c002437 lui x8, 0x1c002000 x8=1c002000 + 2819500 2804 1c001298 00030637 lui x12, 0x30000 x12=00030000 + 2820500 2805 1c00129c 6a440513 addi x10, x8, 1700 x10=1c0026a4 x8:1c002000 + 2837500 2822 1c0012a0 e93ff0ef jal x1, -366 x1=1c0012a2 + 2839500 2824 1c001132 00758793 addi x15, x11, 7 x15=1c2d0007 x11:1c2d0000 + 2840500 2825 1c001136 c407b7b3 p.bclr x15, x15, 2, 0 x15=1c2d0000 x15:1c2d0007 + 2841500 2826 1c00113a 40b785b3 sub x11, x15, x11 x11=00000000 x15:1c2d0000 x11:1c2d0000 + 2842500 2827 1c00113e 00f52023 sw x15, 0(x10) x15:1c2d0000 x10:1c0026a4 PA:1c0026a4 + 2860500 2845 1c001140 40b60633 sub x12, x12, x11 x12=00030000 x12:00030000 x11:00000000 + 2861500 2846 1c001142 00c05763 bge x0, x12, 14 x12:00030000 + 2862500 2847 1c001146 c4063633 p.bclr x12, x12, 2, 0 x12=00030000 x12:00030000 + 2863500 2848 1c00114a 00c7a023 sw x12, 0(x15) x12:00030000 x15:1c2d0000 PA:1c2d0000 + 2881500 2866 1c00114c 0007a223 sw x0, 4(x15) x15:1c2d0000 PA:1c2d0004 + 2899500 2884 1c001150 00008067 jalr x0, x1, 0 x1:1c0012a2 + 2900500 2885 1c0012a2 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 2901500 2886 1c0012a6 ca5797b3 p.extractu x15, x15, 5, 5 x15=00000000 x15:00000000 + 2902500 2887 1c0012aa 00079763 bne x15, x0, 14 x15:00000000 + 2903500 2888 1c0012ac 00812403 lw x8, 8(x2) x8=10000990 x2:10000960 PA:10000968 + 2904500 2889 1c0012ae 00c12083 lw x1, 12(x2) x1=1c000c9c x2:10000960 PA:1000096c + 2920500 2905 1c0012b0 00412483 lw x9, 4(x2) x9=10000168 x2:10000960 PA:10000964 + 2921500 2906 1c0012b2 00000513 addi x10, x0, 0 x10=00000000 + 2922500 2907 1c0012b4 01010113 addi x2, x2, 16 x2=10000970 x2:10000960 + 2923500 2908 1c0012b6 f83ff06f jal x0, -126 + 2941500 2926 1c001238 100015b7 lui x11, 0x10001000 x11=10001000 + 2942500 2927 1c00123c 01651713 slli x14, x10, 0x16 x14=00000000 x10:00000000 + 2959500 2944 1c001240 99058593 addi x11, x11, -1648 x11=10000990 x11:10001000 + 2960500 2945 1c001244 00b706b3 add x13, x14, x11 x13=10000990 x14:00000000 x11:10000990 + 2961500 2946 1c001248 1c002637 lui x12, 0x1c002000 x12=1c002000 + 2962500 2947 1c00124c 00400793 addi x15, x0, 4 x15=00000004 + 2979500 2964 1c001250 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 2980500 2965 1c001252 68d62e23 sw x13, 1692(x12) x13:10000990 x12:1c002000 PA:1c00269c + 2998500 2983 1c001256 000ff637 lui x12, 0xff000 x12=000ff000 + 2999500 2984 1c00125a 00f70733 add x14, x14, x15 x14=00000010 x14:00000000 x15:00000010 + 3000500 2985 1c00125c 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 3001500 2986 1c00125e 67060613 addi x12, x12, 1648 x12=000ff670 x12:000ff000 + 3002500 2987 1c001262 40f60633 sub x12, x12, x15 x12=000ff660 x12:000ff670 x15:00000010 + 3003500 2988 1c001264 00e585b3 add x11, x11, x14 x11=100009a0 x11:10000990 x14:00000010 + 3004500 2989 1c001266 00d50533 add x10, x10, x13 x10=10000990 x10:00000000 x13:10000990 + 3005500 2990 1c001268 ecbff06f jal x0, -310 + 3007500 2992 1c001132 00758793 addi x15, x11, 7 x15=100009a7 x11:100009a0 + 3008500 2993 1c001136 c407b7b3 p.bclr x15, x15, 2, 0 x15=100009a0 x15:100009a7 + 3009500 2994 1c00113a 40b785b3 sub x11, x15, x11 x11=00000000 x15:100009a0 x11:100009a0 + 3010500 2995 1c00113e 00f52023 sw x15, 0(x10) x15:100009a0 x10:10000990 PA:10000990 + 3011500 2996 1c001140 40b60633 sub x12, x12, x11 x12=000ff660 x12:000ff660 x11:00000000 + 3012500 2997 1c001142 00c05763 bge x0, x12, 14 x12:000ff660 + 3013500 2998 1c001146 c4063633 p.bclr x12, x12, 2, 0 x12=000ff660 x12:000ff660 + 3014500 2999 1c00114a 00c7a023 sw x12, 0(x15) x12:000ff660 x15:100009a0 PA:100009a0 + 3015500 3000 1c00114c 0007a223 sw x0, 4(x15) x15:100009a0 PA:100009a4 + 3016500 3001 1c001150 00008067 jalr x0, x1, 0 x1:1c000c9c + 3018500 3003 1c000c9c 0044a78b p.lw x15, 4(x9!) x15=1c001118 x9=1000016c x9:10000168 PA:10000168 + 3035500 3020 1c000ca0 06079363 bne x15, x0, 102 x15:1c001118 + 3054500 3039 1c000d06 000780e7 jalr x1, x15, 0 x1=1c000d08 x15:1c001118 + 3072500 3057 1c001118 10000537 lui x10, 0x10000000 x10=10000000 + 3073500 3058 1c00111c 13850513 addi x10, x10, 312 x10=10000138 x10:10000000 + 3090500 3075 1c001120 00052023 sw x0, 0(x10) x10:10000138 PA:10000138 + 3091500 3076 1c001124 00052223 sw x0, 4(x10) x10:10000138 PA:1000013c + 3092500 3077 1c001128 00052823 sw x0, 16(x10) x10:10000138 PA:10000148 + 3093500 3078 1c00112c 00100593 addi x11, x0, 1 x11=00000001 + 3094500 3079 1c00112e 00450513 addi x10, x10, 4 x10=1000013c x10:10000138 + 3095500 3080 1c001130 dd5ff06f jal x0, -556 + 3113500 3098 1c000f04 fe010113 addi x2, x2, -32 x2=10000950 x2:10000970 + 3114500 3099 1c000f06 01312623 sw x19, 12(x2) x19:00000000 x2:10000950 PA:1000095c + 3115500 3100 1c000f08 00b009b3 add x19, x0, x11 x19=00000001 x11:00000001 + 3116500 3101 1c000f0a 00112e23 sw x1, 28(x2) x1:1c000d08 x2:10000950 PA:1000096c + 3117500 3102 1c000f0c 00812c23 sw x8, 24(x2) x8:10000990 x2:10000950 PA:10000968 + 3118500 3103 1c000f0e 00912a23 sw x9, 20(x2) x9:1000016c x2:10000950 PA:10000964 + 3134500 3119 1c000f10 01212823 sw x18, 16(x2) x18:00000000 x2:10000950 PA:10000960 + 3135500 3120 1c000f12 01412423 sw x20, 8(x2) x20:00000000 x2:10000950 PA:10000958 + 3136500 3121 1c000f14 01512223 sw x21, 4(x2) x21:00000000 x2:10000950 PA:10000954 + 3137500 3122 1c000f16 01612023 sw x22, 0(x2) x22:00000000 x2:10000950 PA:10000950 + 3138500 3123 1c000f18 30047af3 csrrci x21, 0x00000008, 0x300 x21=00001800 + 3142500 3127 1c000f1c 00a00933 add x18, x0, x10 x18=1000013c x10:1000013c + 3143500 3128 1c000f1e 00051763 bne x10, x0, 14 x10:1000013c + 3157500 3142 1c000f2c 07000593 addi x11, x0, 112 x11=00000070 + 3174500 3159 1c000f30 02b985b3 mul x11, x19, x11 x11=00000070 x19:00000001 x11:00000070 + 3175500 3160 1c000f34 f1402573 csrrs x10, x0, 0xf14 x10=00000000 + 3176500 3161 1c000f38 40555513 srai x10, x10, 0x405 x10=00000000 x10:00000000 + 3177500 3162 1c000f3a f2653533 p.bclr x10, x10, 25, 6 x10=00000000 x10:00000000 + 3178500 3163 1c000f3e 00250513 addi x10, x10, 2 x10=00000002 x10:00000000 + 3195500 3180 1c000f40 290000ef jal x1, 656 x1=1c000f42 + 3213500 3198 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 3214500 3199 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000002 + 3215500 3200 1c0011d6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 3216500 3201 1c0011da 69c7a783 lw x15, 1692(x15) x15=10000990 x15:1c002000 PA:1c00269c + 3231500 3216 1c0011de ffe50513 addi x10, x10, -2 x10=00000000 x10:00000002 + 3235500 3220 1c0011e0 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 3236500 3221 1c0011e2 00f50533 add x10, x10, x15 x10=10000990 x10:00000000 x15:10000990 + 3237500 3222 1c0011e4 f6fff06f jal x0, -146 + 3239500 3224 1c001152 00052783 lw x15, 0(x10) x15=100009a0 x10:10000990 PA:10000990 + 3240500 3225 1c001154 00758593 addi x11, x11, 7 x11=00000077 x11:00000070 + 3241500 3226 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000070 x11:00000077 + 3242500 3227 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 3243500 3228 1c00115c 00078963 beq x15, x0, 18 x15:100009a0 + 3244500 3229 1c00115e 0007a703 lw x14, 0(x15) x14=000ff660 x15:100009a0 PA:100009a0 + 3260500 3245 1c001160 00b74963 blt x14, x11, 18 x14:000ff660 x11:00000070 + 3261500 3246 1c001164 00b71c63 bne x14, x11, 24 x14:000ff660 x11:00000070 + 3280500 3265 1c00117c 40b70733 sub x14, x14, x11 x14=000ff5f0 x14:000ff660 x11:00000070 + 3281500 3266 1c00117e 00e7a023 sw x14, 0(x15) x14:000ff5f0 x15:100009a0 PA:100009a0 + 3297500 3282 1c001180 00e787b3 add x15, x15, x14 x15=100fff90 x15:100009a0 x14:000ff5f0 + 3298500 3283 1c001182 fedff06f jal x0, -20 + 3300500 3285 1c00116e 00f00533 add x10, x0, x15 x10=100fff90 x15:100fff90 + 3301500 3286 1c001170 00008067 jalr x0, x1, 0 x1:1c000f42 + 3303500 3288 1c000f42 00a00433 add x8, x0, x10 x8=100fff90 x10:100fff90 + 3304500 3289 1c000f44 fff00513 addi x10, x0, -1 x10=ffffffff + 3305500 3290 1c000f46 00040c63 beq x8, x0, 24 x8:100fff90 + 3306500 3291 1c000f48 00840413 addi x8, x8, 8 x8=100fff98 x8:100fff90 + 3307500 3292 1c000f4a 00000493 addi x9, x0, 0 x9=00000000 + 3308500 3293 1c000f4c 10000b37 lui x22, 0x10000000 x22=10000000 + 3325500 3310 1c000f50 ff840a13 addi x20, x8, -8 x20=100fff90 x8:100fff98 + 3326500 3311 1c000f54 0134cf63 blt x9, x19, 30 x9:00000000 x19:00000001 + 3345500 3330 1c000f72 012005b3 add x11, x0, x18 x11=1000013c x18:1000013c + 3346500 3331 1c000f74 01400533 add x10, x0, x20 x10=100fff90 x20:100fff90 + 3347500 3332 1c000f76 f43ff0ef jal x1, -190 x1=1c000f78 + 3365500 3350 1c000eb8 ff010113 addi x2, x2, -16 x2=10000940 x2:10000950 + 3366500 3351 1c000eba 00812423 sw x8, 8(x2) x8:100fff98 x2:10000940 PA:10000948 + 3367500 3352 1c000ebc 00912223 sw x9, 4(x2) x9:00000000 x2:10000940 PA:10000944 + 3368500 3353 1c000ebe 00112623 sw x1, 12(x2) x1:1c000f78 x2:10000940 PA:1000094c + 3384500 3369 1c000ec0 00a00433 add x8, x0, x10 x8=100fff90 x10:100fff90 + 3385500 3370 1c000ec2 00b004b3 add x9, x0, x11 x9=1000013c x11:1000013c + 3386500 3371 1c000ec4 00052823 sw x0, 16(x10) x10:100fff90 PA:100fffa0 + 3387500 3372 1c000ec8 00052a23 sw x0, 20(x10) x10:100fff90 PA:100fffa4 + 3388500 3373 1c000ecc 01000593 addi x11, x0, 16 x11=00000010 + 3389500 3374 1c000ece 00000513 addi x10, x0, 0 x10=00000000 + 3405500 3390 1c000ed0 300000ef jal x1, 768 x1=1c000ed2 + 3407500 3392 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 3408500 3393 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000000 + 3411500 3396 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 3412500 3397 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 3413500 3398 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 3430500 3415 1c0011f0 ff3ff06f jal x0, -14 + 3432500 3417 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a0 x10:00000000 x15:1c0026a0 + 3433500 3418 1c0011e4 f6fff06f jal x0, -146 + 3435500 3420 1c001152 00052783 lw x15, 0(x10) x15=1c0026b8 x10:1c0026a0 PA:1c0026a0 + 3449500 3434 1c001154 00758593 addi x11, x11, 7 x11=00000017 x11:00000010 + 3450500 3435 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000017 + 3451500 3436 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 3452500 3437 1c00115c 00078963 beq x15, x0, 18 x15:1c0026b8 + 3453500 3438 1c00115e 0007a703 lw x14, 0(x15) x14=002cd948 x15:1c0026b8 PA:1c0026b8 + 3468500 3453 1c001160 00b74963 blt x14, x11, 18 x14:002cd948 x11:00000010 + 3469500 3454 1c001164 00b71c63 bne x14, x11, 24 x14:002cd948 x11:00000010 + 3472500 3457 1c00117c 40b70733 sub x14, x14, x11 x14=002cd938 x14:002cd948 x11:00000010 + 3473500 3458 1c00117e 00e7a023 sw x14, 0(x15) x14:002cd938 x15:1c0026b8 PA:1c0026b8 + 3491500 3476 1c001180 00e787b3 add x15, x15, x14 x15=1c2cfff0 x15:1c0026b8 x14:002cd938 + 3492500 3477 1c001182 fedff06f jal x0, -20 + 3494500 3479 1c00116e 00f00533 add x10, x0, x15 x10=1c2cfff0 x15:1c2cfff0 + 3495500 3480 1c001170 00008067 jalr x0, x1, 0 x1:1c000ed2 + 3497500 3482 1c000ed2 06a42623 sw x10, 108(x8) x10:1c2cfff0 x8:100fff90 PA:100ffffc + 3498500 3483 1c000ed4 00942623 sw x9, 12(x8) x9:1000013c x8:100fff90 PA:100fff9c + 3499500 3484 1c000ed6 00042023 sw x0, 0(x8) x8:100fff90 PA:100fff90 + 3500500 3485 1c000eda 00c12083 lw x1, 12(x2) x1=1c000f78 x2:10000940 PA:1000094c + 3501500 3486 1c000edc 00812403 lw x8, 8(x2) x8=100fff98 x2:10000940 PA:10000948 + 3502500 3487 1c000ede 00412483 lw x9, 4(x2) x9=00000000 x2:10000940 PA:10000944 + 3518500 3503 1c000ee0 01010113 addi x2, x2, 16 x2=10000950 x2:10000940 + 3519500 3504 1c000ee2 00008067 jalr x0, x1, 0 x1:1c000f78 + 3521500 3506 1c000f78 138b0793 addi x15, x22, 312 x15=10000138 x22:10000000 + 3522500 3507 1c000f7c 0007a703 lw x14, 0(x15) x14=00000000 x15:10000138 PA:10000138 + 3523500 3508 1c000f7e 00148493 addi x9, x9, 1 x9=00000001 x9:00000000 + 3539500 3524 1c000f80 06e4282b p.sw x14, 112(x8!) x8=10100008 x14:00000000 x8:100fff98 PA:100fff98 + 3540500 3525 1c000f84 0147a023 sw x20, 0(x15) x20:100fff90 x15:10000138 PA:10000138 + 3541500 3526 1c000f88 fc9ff06f jal x0, -56 + 3543500 3528 1c000f50 ff840a13 addi x20, x8, -8 x20=10100000 x8:10100008 + 3544500 3529 1c000f54 0134cf63 blt x9, x19, 30 x9:00000001 x19:00000001 + 3545500 3530 1c000f58 300a9073 csrrw x0, x21, 0x300 x21:00001800 + 3549500 3534 1c000f5c 00000513 addi x10, x0, 0 x10=00000000 + 3550500 3535 1c000f5e 01c12083 lw x1, 28(x2) x1=1c000d08 x2:10000950 PA:1000096c + 3563500 3548 1c000f60 01812403 lw x8, 24(x2) x8=10000990 x2:10000950 PA:10000968 + 3564500 3549 1c000f62 01412483 lw x9, 20(x2) x9=1000016c x2:10000950 PA:10000964 + 3565500 3550 1c000f64 01012903 lw x18, 16(x2) x18=00000000 x2:10000950 PA:10000960 + 3566500 3551 1c000f66 00c12983 lw x19, 12(x2) x19=00000000 x2:10000950 PA:1000095c + 3567500 3552 1c000f68 00812a03 lw x20, 8(x2) x20=00000000 x2:10000950 PA:10000958 + 3568500 3553 1c000f6a 00412a83 lw x21, 4(x2) x21=00000000 x2:10000950 PA:10000954 + 3569500 3554 1c000f6c 00012b03 lw x22, 0(x2) x22=00000000 x2:10000950 PA:10000950 + 3570500 3555 1c000f6e 02010113 addi x2, x2, 32 x2=10000970 x2:10000950 + 3571500 3556 1c000f70 00008067 jalr x0, x1, 0 x1:1c000d08 + 3573500 3558 1c000d08 f95ff06f jal x0, -108 + 3575500 3560 1c000c9c 0044a78b p.lw x15, 4(x9!) x15=1c0015b6 x9=10000170 x9:1000016c PA:1000016c + 3577500 3562 1c000ca0 06079363 bne x15, x0, 102 x15:1c0015b6 + 3580500 3565 1c000d06 000780e7 jalr x1, x15, 0 x1=1c000d08 x15:1c0015b6 + 3598500 3583 1c0015b6 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 3599500 3584 1c0015ba ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 3600500 3585 1c0015bc 00000613 addi x12, x0, 0 x12=00000000 + 3617500 3602 1c0015be 32458593 addi x11, x11, 804 x11=1c001324 x11:1c001000 + 3618500 3603 1c0015c2 00000513 addi x10, x0, 0 x10=00000000 + 3619500 3604 1c0015c4 00112623 sw x1, 12(x2) x1:1c000d08 x2:10000960 PA:1000096c + 3620500 3605 1c0015c6 83bff0ef jal x1, -1990 x1=1c0015ca + 3622500 3607 1c000e00 fe010113 addi x2, x2, -32 x2=10000940 x2:10000960 + 3623500 3608 1c000e02 00812c23 sw x8, 24(x2) x8:10000990 x2:10000940 PA:10000958 + 3624500 3609 1c000e04 00912a23 sw x9, 20(x2) x9:10000170 x2:10000940 PA:10000954 + 3625500 3610 1c000e06 00a00433 add x8, x0, x10 x8=00000000 x10:00000000 + 3626500 3611 1c000e08 00b004b3 add x9, x0, x11 x9=1c001324 x11:1c001324 + 3627500 3612 1c000e0a 00100513 addi x10, x0, 1 x10=00000001 + 3628500 3613 1c000e0c 00c00593 addi x11, x0, 12 x11=0000000c + 3629500 3614 1c000e0e 00c12623 sw x12, 12(x2) x12:00000000 x2:10000940 PA:1000094c + 3645500 3630 1c000e10 00112e23 sw x1, 28(x2) x1:1c0015ca x2:10000940 PA:1000095c + 3646500 3631 1c000e12 3be000ef jal x1, 958 x1=1c000e14 + 3648500 3633 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 3649500 3634 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000001 + 3652500 3637 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 3653500 3638 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 3654500 3639 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 3655500 3640 1c0011f0 ff3ff06f jal x0, -14 + 3657500 3642 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a4 x10:00000004 x15:1c0026a0 + 3658500 3643 1c0011e4 f6fff06f jal x0, -146 + 3660500 3645 1c001152 00052783 lw x15, 0(x10) x15=1c2d0000 x10:1c0026a4 PA:1c0026a4 + 3674500 3659 1c001154 00758593 addi x11, x11, 7 x11=00000013 x11:0000000c + 3675500 3660 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000013 + 3676500 3661 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 3677500 3662 1c00115c 00078963 beq x15, x0, 18 x15:1c2d0000 + 3678500 3663 1c00115e 0007a703 lw x14, 0(x15) x14=00030000 x15:1c2d0000 PA:1c2d0000 + 3693500 3678 1c001160 00b74963 blt x14, x11, 18 x14:00030000 x11:00000010 + 3694500 3679 1c001164 00b71c63 bne x14, x11, 24 x14:00030000 x11:00000010 + 3697500 3682 1c00117c 40b70733 sub x14, x14, x11 x14=0002fff0 x14:00030000 x11:00000010 + 3698500 3683 1c00117e 00e7a023 sw x14, 0(x15) x14:0002fff0 x15:1c2d0000 PA:1c2d0000 + 3716500 3701 1c001180 00e787b3 add x15, x15, x14 x15=1c2ffff0 x15:1c2d0000 x14:0002fff0 + 3717500 3702 1c001182 fedff06f jal x0, -20 + 3719500 3704 1c00116e 00f00533 add x10, x0, x15 x10=1c2ffff0 x15:1c2ffff0 + 3720500 3705 1c001170 00008067 jalr x0, x1, 0 x1:1c000e14 + 3722500 3707 1c000e14 00c12603 lw x12, 12(x2) x12=00000000 x2:10000940 PA:1000094c + 3723500 3708 1c000e16 02050263 beq x10, x0, 36 x10:1c2ffff0 + 3724500 3709 1c000e18 100007b7 lui x15, 0x10000000 x15=10000000 + 3725500 3710 1c000e1c 00241413 slli x8, x8, 0x2 x8=00000000 x8:00000000 + 3742500 3727 1c000e1e 05878793 addi x15, x15, 88 x15=10000058 x15:10000000 + 3743500 3728 1c000e22 008787b3 add x15, x15, x8 x15=10000058 x15:10000058 x8:00000000 + 3744500 3729 1c000e24 0007a703 lw x14, 0(x15) x14=00000000 x15:10000058 PA:10000058 + 3745500 3730 1c000e26 00952023 sw x9, 0(x10) x9:1c001324 x10:1c2ffff0 PA:1c2ffff0 + 3763500 3748 1c000e28 00c52223 sw x12, 4(x10) x12:00000000 x10:1c2ffff0 PA:1c2ffff4 + 3781500 3766 1c000e2a 00e52423 sw x14, 8(x10) x14:00000000 x10:1c2ffff0 PA:1c2ffff8 + 3799500 3784 1c000e2c 00a7a023 sw x10, 0(x15) x10:1c2ffff0 x15:10000058 PA:10000058 + 3800500 3785 1c000e2e 00000513 addi x10, x0, 0 x10=00000000 + 3801500 3786 1c000e30 01c12083 lw x1, 28(x2) x1=1c0015ca x2:10000940 PA:1000095c + 3802500 3787 1c000e32 01812403 lw x8, 24(x2) x8=10000990 x2:10000940 PA:10000958 + 3803500 3788 1c000e34 01412483 lw x9, 20(x2) x9=10000170 x2:10000940 PA:10000954 + 3804500 3789 1c000e36 02010113 addi x2, x2, 32 x2=10000960 x2:10000940 + 3805500 3790 1c000e38 00008067 jalr x0, x1, 0 x1:1c0015ca + 3807500 3792 1c0015ca 00050f63 beq x10, x0, 30 x10:00000000 + 3842500 3827 1c0015e8 00c12083 lw x1, 12(x2) x1=1c000d08 x2:10000960 PA:1000096c + 3843500 3828 1c0015ea 01010113 addi x2, x2, 16 x2=10000970 x2:10000960 + 3845500 3830 1c0015ec 00008067 jalr x0, x1, 0 x1:1c000d08 + 3862500 3847 1c000d08 f95ff06f jal x0, -108 + 3864500 3849 1c000c9c 0044a78b p.lw x15, 4(x9!) x15=1c0016da x9=10000174 x9:10000170 PA:10000170 + 3866500 3851 1c000ca0 06079363 bne x15, x0, 102 x15:1c0016da + 3869500 3854 1c000d06 000780e7 jalr x1, x15, 0 x1=1c000d08 x15:1c0016da + 3887500 3872 1c0016da ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 3888500 3873 1c0016dc 00812423 sw x8, 8(x2) x8:10000990 x2:10000960 PA:10000968 + 3905500 3890 1c0016de 1c0007b7 lui x15, 0x1c000000 x15=1c000000 + 3906500 3891 1c0016e2 10000437 lui x8, 0x10000000 x8=10000000 + 3907500 3892 1c0016e6 00912223 sw x9, 4(x2) x9:10000174 x2:10000960 PA:10000964 + 3908500 3893 1c0016e8 01212023 sw x18, 0(x2) x18:00000000 x2:10000960 PA:10000960 + 3909500 3894 1c0016ea 00112623 sw x1, 12(x2) x1:1c000d08 x2:10000960 PA:1000096c + 3910500 3895 1c0016ec 07040413 addi x8, x8, 112 x8=10000070 x8:10000000 + 3927500 3912 1c0016f0 29878793 addi x15, x15, 664 x15=1c000298 x15:1c000000 + 3928500 3913 1c0016f4 00f42023 sw x15, 0(x8) x15:1c000298 x8:10000070 PA:10000070 + 3929500 3914 1c0016f6 1c0017b7 lui x15, 0x1c001000 x15=1c001000 + 3930500 3915 1c0016fa 6b278793 addi x15, x15, 1714 x15=1c0016b2 x15:1c001000 + 3947500 3932 1c0016fe 100005b7 lui x11, 0x10000000 x11=10000000 + 3948500 3933 1c001702 04840913 addi x18, x8, 72 x18=100000b8 x8:10000070 + 3949500 3934 1c001706 00f42623 sw x15, 12(x8) x15:1c0016b2 x8:10000070 PA:1000007c + 3950500 3935 1c001708 100004b7 lui x9, 0x10000000 x9=10000000 + 3951500 3936 1c00170c 13c58793 addi x15, x11, 316 x15=1000013c x11:10000000 + 3968500 3953 1c001710 15448493 addi x9, x9, 340 x9=10000154 x9:10000000 + 3969500 3954 1c001714 0af42c23 sw x15, 184(x8) x15:1000013c x8:10000070 PA:10000128 + 3970500 3955 1c001718 01200533 add x10, x0, x18 x10=100000b8 x18:100000b8 + 3971500 3956 1c00171a 00100793 addi x15, x0, 1 x15=00000001 + 3972500 3957 1c00171c 13c58593 addi x11, x11, 316 x11=1000013c x11:10000000 + 3989500 3974 1c001720 0af42e23 sw x15, 188(x8) x15:00000001 x8:10000070 PA:1000012c + 3990500 3975 1c001724 0004a023 sw x0, 0(x9) x9:10000154 PA:10000154 + 3991500 3976 1c001728 02042a23 sw x0, 52(x8) x8:10000070 PA:100000a4 + 3992500 3977 1c00172c 00042223 sw x0, 4(x8) x8:10000070 PA:10000074 + 4009500 3994 1c001730 00042423 sw x0, 8(x8) x8:10000070 PA:10000078 + 4010500 3995 1c001734 f84ff0ef jal x1, -2172 x1=1c001738 + 4012500 3997 1c000eb8 ff010113 addi x2, x2, -16 x2=10000950 x2:10000960 + 4013500 3998 1c000eba 00812423 sw x8, 8(x2) x8:10000070 x2:10000950 PA:10000958 + 4014500 3999 1c000ebc 00912223 sw x9, 4(x2) x9:10000154 x2:10000950 PA:10000954 + 4015500 4000 1c000ebe 00112623 sw x1, 12(x2) x1:1c001738 x2:10000950 PA:1000095c + 4016500 4001 1c000ec0 00a00433 add x8, x0, x10 x8=100000b8 x10:100000b8 + 4017500 4002 1c000ec2 00b004b3 add x9, x0, x11 x9=1000013c x11:1000013c + 4018500 4003 1c000ec4 00052823 sw x0, 16(x10) x10:100000b8 PA:100000c8 + 4019500 4004 1c000ec8 00052a23 sw x0, 20(x10) x10:100000b8 PA:100000cc + 4020500 4005 1c000ecc 01000593 addi x11, x0, 16 x11=00000010 + 4021500 4006 1c000ece 00000513 addi x10, x0, 0 x10=00000000 + 4022500 4007 1c000ed0 300000ef jal x1, 768 x1=1c000ed2 + 4024500 4009 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 4025500 4010 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000000 + 4028500 4013 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4029500 4014 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 4030500 4015 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 4031500 4016 1c0011f0 ff3ff06f jal x0, -14 + 4033500 4018 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a0 x10:00000000 x15:1c0026a0 + 4034500 4019 1c0011e4 f6fff06f jal x0, -146 + 4036500 4021 1c001152 00052783 lw x15, 0(x10) x15=1c0026b8 x10:1c0026a0 PA:1c0026a0 + 4050500 4035 1c001154 00758593 addi x11, x11, 7 x11=00000017 x11:00000010 + 4051500 4036 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000017 + 4052500 4037 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 4053500 4038 1c00115c 00078963 beq x15, x0, 18 x15:1c0026b8 + 4054500 4039 1c00115e 0007a703 lw x14, 0(x15) x14=002cd938 x15:1c0026b8 PA:1c0026b8 + 4069500 4054 1c001160 00b74963 blt x14, x11, 18 x14:002cd938 x11:00000010 + 4070500 4055 1c001164 00b71c63 bne x14, x11, 24 x14:002cd938 x11:00000010 + 4073500 4058 1c00117c 40b70733 sub x14, x14, x11 x14=002cd928 x14:002cd938 x11:00000010 + 4074500 4059 1c00117e 00e7a023 sw x14, 0(x15) x14:002cd928 x15:1c0026b8 PA:1c0026b8 + 4092500 4077 1c001180 00e787b3 add x15, x15, x14 x15=1c2cffe0 x15:1c0026b8 x14:002cd928 + 4093500 4078 1c001182 fedff06f jal x0, -20 + 4095500 4080 1c00116e 00f00533 add x10, x0, x15 x10=1c2cffe0 x15:1c2cffe0 + 4096500 4081 1c001170 00008067 jalr x0, x1, 0 x1:1c000ed2 + 4098500 4083 1c000ed2 06a42623 sw x10, 108(x8) x10:1c2cffe0 x8:100000b8 PA:10000124 + 4099500 4084 1c000ed4 00942623 sw x9, 12(x8) x9:1000013c x8:100000b8 PA:100000c4 + 4100500 4085 1c000ed6 00042023 sw x0, 0(x8) x8:100000b8 PA:100000b8 + 4101500 4086 1c000eda 00c12083 lw x1, 12(x2) x1=1c001738 x2:10000950 PA:1000095c + 4102500 4087 1c000edc 00812403 lw x8, 8(x2) x8=10000070 x2:10000950 PA:10000958 + 4103500 4088 1c000ede 00412483 lw x9, 4(x2) x9=10000154 x2:10000950 PA:10000954 + 4104500 4089 1c000ee0 01010113 addi x2, x2, 16 x2=10000960 x2:10000950 + 4105500 4090 1c000ee2 00008067 jalr x0, x1, 0 x1:1c001738 + 4107500 4092 1c001738 100007b7 lui x15, 0x10000000 x15=10000000 + 4108500 4093 1c00173c 1387a703 lw x14, 312(x15) x14=100fff90 x15:10000000 PA:10000138 + 4125500 4110 1c001740 0084a423 sw x8, 8(x9) x8:10000070 x9:10000154 PA:1000015c + 4126500 4111 1c001742 00c12083 lw x1, 12(x2) x1=1c000d08 x2:10000960 PA:1000096c + 4127500 4112 1c001744 04e42823 sw x14, 80(x8) x14:100fff90 x8:10000070 PA:100000c0 + 4128500 4113 1c001746 00812403 lw x8, 8(x2) x8=10000990 x2:10000960 PA:10000968 + 4129500 4114 1c001748 1327ac23 sw x18, 312(x15) x18:100000b8 x15:10000000 PA:10000138 + 4130500 4115 1c00174c 00412483 lw x9, 4(x2) x9=10000174 x2:10000960 PA:10000964 + 4131500 4116 1c00174e 00012903 lw x18, 0(x2) x18=00000000 x2:10000960 PA:10000960 + 4147500 4132 1c001750 01010113 addi x2, x2, 16 x2=10000970 x2:10000960 + 4148500 4133 1c001752 00008067 jalr x0, x1, 0 x1:1c000d08 + 4150500 4135 1c000d08 f95ff06f jal x0, -108 + 4152500 4137 1c000c9c 0044a78b p.lw x15, 4(x9!) x15=1c001874 x9=10000178 x9:10000174 PA:10000174 + 4154500 4139 1c000ca0 06079363 bne x15, x0, 102 x15:1c001874 + 4157500 4142 1c000d06 000780e7 jalr x1, x15, 0 x1=1c000d08 x15:1c001874 + 4175500 4160 1c001874 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4176500 4161 1c001878 6607ae23 sw x0, 1660(x15) x15:1c002000 PA:1c00267c + 4194500 4179 1c00187c 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4195500 4180 1c001880 6607ac23 sw x0, 1656(x15) x15:1c002000 PA:1c002678 + 4213500 4198 1c001884 00100793 addi x15, x0, 1 x15=00000001 + 4214500 4199 1c001888 0217b663 p.bneimm x15, 44 x15:00000001 + 4215500 4200 1c00188c 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 4232500 4217 1c001890 ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 4233500 4218 1c001892 00000613 addi x12, x0, 0 x12=00000000 + 4234500 4219 1c001894 7b858593 addi x11, x11, 1976 x11=1c0017b8 x11:1c001000 + 4235500 4220 1c001898 00000513 addi x10, x0, 0 x10=00000000 + 4236500 4221 1c00189a 00112623 sw x1, 12(x2) x1:1c000d08 x2:10000960 PA:1000096c + 4237500 4222 1c00189c d64ff0ef jal x1, -2716 x1=1c0018a0 + 4255500 4240 1c000e00 fe010113 addi x2, x2, -32 x2=10000940 x2:10000960 + 4256500 4241 1c000e02 00812c23 sw x8, 24(x2) x8:10000990 x2:10000940 PA:10000958 + 4257500 4242 1c000e04 00912a23 sw x9, 20(x2) x9:10000178 x2:10000940 PA:10000954 + 4258500 4243 1c000e06 00a00433 add x8, x0, x10 x8=00000000 x10:00000000 + 4259500 4244 1c000e08 00b004b3 add x9, x0, x11 x9=1c0017b8 x11:1c0017b8 + 4260500 4245 1c000e0a 00100513 addi x10, x0, 1 x10=00000001 + 4261500 4246 1c000e0c 00c00593 addi x11, x0, 12 x11=0000000c + 4262500 4247 1c000e0e 00c12623 sw x12, 12(x2) x12:00000000 x2:10000940 PA:1000094c + 4263500 4248 1c000e10 00112e23 sw x1, 28(x2) x1:1c0018a0 x2:10000940 PA:1000095c + 4264500 4249 1c000e12 3be000ef jal x1, 958 x1=1c000e14 + 4266500 4251 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 4267500 4252 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000001 + 4270500 4255 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4271500 4256 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 4272500 4257 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 4273500 4258 1c0011f0 ff3ff06f jal x0, -14 + 4275500 4260 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a4 x10:00000004 x15:1c0026a0 + 4276500 4261 1c0011e4 f6fff06f jal x0, -146 + 4278500 4263 1c001152 00052783 lw x15, 0(x10) x15=1c2d0000 x10:1c0026a4 PA:1c0026a4 + 4292500 4277 1c001154 00758593 addi x11, x11, 7 x11=00000013 x11:0000000c + 4293500 4278 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000013 + 4294500 4279 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 4295500 4280 1c00115c 00078963 beq x15, x0, 18 x15:1c2d0000 + 4296500 4281 1c00115e 0007a703 lw x14, 0(x15) x14=0002fff0 x15:1c2d0000 PA:1c2d0000 + 4311500 4296 1c001160 00b74963 blt x14, x11, 18 x14:0002fff0 x11:00000010 + 4312500 4297 1c001164 00b71c63 bne x14, x11, 24 x14:0002fff0 x11:00000010 + 4315500 4300 1c00117c 40b70733 sub x14, x14, x11 x14=0002ffe0 x14:0002fff0 x11:00000010 + 4316500 4301 1c00117e 00e7a023 sw x14, 0(x15) x14:0002ffe0 x15:1c2d0000 PA:1c2d0000 + 4334500 4319 1c001180 00e787b3 add x15, x15, x14 x15=1c2fffe0 x15:1c2d0000 x14:0002ffe0 + 4335500 4320 1c001182 fedff06f jal x0, -20 + 4337500 4322 1c00116e 00f00533 add x10, x0, x15 x10=1c2fffe0 x15:1c2fffe0 + 4338500 4323 1c001170 00008067 jalr x0, x1, 0 x1:1c000e14 + 4340500 4325 1c000e14 00c12603 lw x12, 12(x2) x12=00000000 x2:10000940 PA:1000094c + 4341500 4326 1c000e16 02050263 beq x10, x0, 36 x10:1c2fffe0 + 4342500 4327 1c000e18 100007b7 lui x15, 0x10000000 x15=10000000 + 4343500 4328 1c000e1c 00241413 slli x8, x8, 0x2 x8=00000000 x8:00000000 + 4344500 4329 1c000e1e 05878793 addi x15, x15, 88 x15=10000058 x15:10000000 + 4345500 4330 1c000e22 008787b3 add x15, x15, x8 x15=10000058 x15:10000058 x8:00000000 + 4346500 4331 1c000e24 0007a703 lw x14, 0(x15) x14=1c2ffff0 x15:10000058 PA:10000058 + 4347500 4332 1c000e26 00952023 sw x9, 0(x10) x9:1c0017b8 x10:1c2fffe0 PA:1c2fffe0 + 4365500 4350 1c000e28 00c52223 sw x12, 4(x10) x12:00000000 x10:1c2fffe0 PA:1c2fffe4 + 4383500 4368 1c000e2a 00e52423 sw x14, 8(x10) x14:1c2ffff0 x10:1c2fffe0 PA:1c2fffe8 + 4401500 4386 1c000e2c 00a7a023 sw x10, 0(x15) x10:1c2fffe0 x15:10000058 PA:10000058 + 4402500 4387 1c000e2e 00000513 addi x10, x0, 0 x10=00000000 + 4403500 4388 1c000e30 01c12083 lw x1, 28(x2) x1=1c0018a0 x2:10000940 PA:1000095c + 4404500 4389 1c000e32 01812403 lw x8, 24(x2) x8=10000990 x2:10000940 PA:10000958 + 4405500 4390 1c000e34 01412483 lw x9, 20(x2) x9=10000178 x2:10000940 PA:10000954 + 4406500 4391 1c000e36 02010113 addi x2, x2, 32 x2=10000960 x2:10000940 + 4407500 4392 1c000e38 00008067 jalr x0, x1, 0 x1:1c0018a0 + 4409500 4394 1c0018a0 00c12083 lw x1, 12(x2) x1=1c000d08 x2:10000960 PA:1000096c + 4410500 4395 1c0018a2 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 4411500 4396 1c0018a6 00000613 addi x12, x0, 0 x12=00000000 + 4412500 4397 1c0018a8 79c58593 addi x11, x11, 1948 x11=1c00179c x11:1c001000 + 4413500 4398 1c0018ac 00100513 addi x10, x0, 1 x10=00000001 + 4414500 4399 1c0018ae 01010113 addi x2, x2, 16 x2=10000970 x2:10000960 + 4430500 4415 1c0018b0 d50ff06f jal x0, -2736 + 4432500 4417 1c000e00 fe010113 addi x2, x2, -32 x2=10000950 x2:10000970 + 4433500 4418 1c000e02 00812c23 sw x8, 24(x2) x8:10000990 x2:10000950 PA:10000968 + 4434500 4419 1c000e04 00912a23 sw x9, 20(x2) x9:10000178 x2:10000950 PA:10000964 + 4435500 4420 1c000e06 00a00433 add x8, x0, x10 x8=00000001 x10:00000001 + 4436500 4421 1c000e08 00b004b3 add x9, x0, x11 x9=1c00179c x11:1c00179c + 4437500 4422 1c000e0a 00100513 addi x10, x0, 1 x10=00000001 + 4438500 4423 1c000e0c 00c00593 addi x11, x0, 12 x11=0000000c + 4439500 4424 1c000e0e 00c12623 sw x12, 12(x2) x12:00000000 x2:10000950 PA:1000095c + 4440500 4425 1c000e10 00112e23 sw x1, 28(x2) x1:1c000d08 x2:10000950 PA:1000096c + 4441500 4426 1c000e12 3be000ef jal x1, 958 x1=1c000e14 + 4443500 4428 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 4444500 4429 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000001 + 4447500 4432 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4448500 4433 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 4449500 4434 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 4450500 4435 1c0011f0 ff3ff06f jal x0, -14 + 4452500 4437 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a4 x10:00000004 x15:1c0026a0 + 4453500 4438 1c0011e4 f6fff06f jal x0, -146 + 4455500 4440 1c001152 00052783 lw x15, 0(x10) x15=1c2d0000 x10:1c0026a4 PA:1c0026a4 + 4469500 4454 1c001154 00758593 addi x11, x11, 7 x11=00000013 x11:0000000c + 4470500 4455 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000013 + 4471500 4456 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 4472500 4457 1c00115c 00078963 beq x15, x0, 18 x15:1c2d0000 + 4473500 4458 1c00115e 0007a703 lw x14, 0(x15) x14=0002ffe0 x15:1c2d0000 PA:1c2d0000 + 4488500 4473 1c001160 00b74963 blt x14, x11, 18 x14:0002ffe0 x11:00000010 + 4489500 4474 1c001164 00b71c63 bne x14, x11, 24 x14:0002ffe0 x11:00000010 + 4492500 4477 1c00117c 40b70733 sub x14, x14, x11 x14=0002ffd0 x14:0002ffe0 x11:00000010 + 4493500 4478 1c00117e 00e7a023 sw x14, 0(x15) x14:0002ffd0 x15:1c2d0000 PA:1c2d0000 + 4511500 4496 1c001180 00e787b3 add x15, x15, x14 x15=1c2fffd0 x15:1c2d0000 x14:0002ffd0 + 4512500 4497 1c001182 fedff06f jal x0, -20 + 4514500 4499 1c00116e 00f00533 add x10, x0, x15 x10=1c2fffd0 x15:1c2fffd0 + 4515500 4500 1c001170 00008067 jalr x0, x1, 0 x1:1c000e14 + 4517500 4502 1c000e14 00c12603 lw x12, 12(x2) x12=00000000 x2:10000950 PA:1000095c + 4518500 4503 1c000e16 02050263 beq x10, x0, 36 x10:1c2fffd0 + 4519500 4504 1c000e18 100007b7 lui x15, 0x10000000 x15=10000000 + 4520500 4505 1c000e1c 00241413 slli x8, x8, 0x2 x8=00000004 x8:00000001 + 4521500 4506 1c000e1e 05878793 addi x15, x15, 88 x15=10000058 x15:10000000 + 4522500 4507 1c000e22 008787b3 add x15, x15, x8 x15=1000005c x15:10000058 x8:00000004 + 4523500 4508 1c000e24 0007a703 lw x14, 0(x15) x14=00000000 x15:1000005c PA:1000005c + 4524500 4509 1c000e26 00952023 sw x9, 0(x10) x9:1c00179c x10:1c2fffd0 PA:1c2fffd0 + 4542500 4527 1c000e28 00c52223 sw x12, 4(x10) x12:00000000 x10:1c2fffd0 PA:1c2fffd4 + 4560500 4545 1c000e2a 00e52423 sw x14, 8(x10) x14:00000000 x10:1c2fffd0 PA:1c2fffd8 + 4578500 4563 1c000e2c 00a7a023 sw x10, 0(x15) x10:1c2fffd0 x15:1000005c PA:1000005c + 4579500 4564 1c000e2e 00000513 addi x10, x0, 0 x10=00000000 + 4580500 4565 1c000e30 01c12083 lw x1, 28(x2) x1=1c000d08 x2:10000950 PA:1000096c + 4581500 4566 1c000e32 01812403 lw x8, 24(x2) x8=10000990 x2:10000950 PA:10000968 + 4582500 4567 1c000e34 01412483 lw x9, 20(x2) x9=10000178 x2:10000950 PA:10000964 + 4583500 4568 1c000e36 02010113 addi x2, x2, 32 x2=10000970 x2:10000950 + 4584500 4569 1c000e38 00008067 jalr x0, x1, 0 x1:1c000d08 + 4586500 4571 1c000d08 f95ff06f jal x0, -108 + 4588500 4573 1c000c9c 0044a78b p.lw x15, 4(x9!) x15=1c0020a4 x9=1000017c x9:10000178 PA:10000178 + 4590500 4575 1c000ca0 06079363 bne x15, x0, 102 x15:1c0020a4 + 4593500 4578 1c000d06 000780e7 jalr x1, x15, 0 x1=1c000d08 x15:1c0020a4 + 4611500 4596 1c0020a4 1c0025b7 lui x11, 0x1c002000 x11=1c002000 + 4612500 4597 1c0020a8 ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 4613500 4598 1c0020aa 00000613 addi x12, x0, 0 x12=00000000 + 4614500 4599 1c0020ac 00458593 addi x11, x11, 4 x11=1c002004 x11:1c002000 + 4631500 4616 1c0020b0 00400513 addi x10, x0, 4 x10=00000004 + 4632500 4617 1c0020b2 00112623 sw x1, 12(x2) x1:1c000d08 x2:10000960 PA:1000096c + 4633500 4618 1c0020b4 00812423 sw x8, 8(x2) x8:10000990 x2:10000960 PA:10000968 + 4634500 4619 1c0020b6 d4bfe0ef jal x1, -4790 x1=1c0020ba + 4636500 4621 1c000e00 fe010113 addi x2, x2, -32 x2=10000940 x2:10000960 + 4637500 4622 1c000e02 00812c23 sw x8, 24(x2) x8:10000990 x2:10000940 PA:10000958 + 4638500 4623 1c000e04 00912a23 sw x9, 20(x2) x9:1000017c x2:10000940 PA:10000954 + 4639500 4624 1c000e06 00a00433 add x8, x0, x10 x8=00000004 x10:00000004 + 4640500 4625 1c000e08 00b004b3 add x9, x0, x11 x9=1c002004 x11:1c002004 + 4641500 4626 1c000e0a 00100513 addi x10, x0, 1 x10=00000001 + 4642500 4627 1c000e0c 00c00593 addi x11, x0, 12 x11=0000000c + 4643500 4628 1c000e0e 00c12623 sw x12, 12(x2) x12:00000000 x2:10000940 PA:1000094c + 4644500 4629 1c000e10 00112e23 sw x1, 28(x2) x1:1c0020ba x2:10000940 PA:1000095c + 4645500 4630 1c000e12 3be000ef jal x1, 958 x1=1c000e14 + 4647500 4632 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 4648500 4633 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000001 + 4651500 4636 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4652500 4637 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 4653500 4638 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 4654500 4639 1c0011f0 ff3ff06f jal x0, -14 + 4656500 4641 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a4 x10:00000004 x15:1c0026a0 + 4657500 4642 1c0011e4 f6fff06f jal x0, -146 + 4659500 4644 1c001152 00052783 lw x15, 0(x10) x15=1c2d0000 x10:1c0026a4 PA:1c0026a4 + 4673500 4658 1c001154 00758593 addi x11, x11, 7 x11=00000013 x11:0000000c + 4674500 4659 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000013 + 4675500 4660 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 4676500 4661 1c00115c 00078963 beq x15, x0, 18 x15:1c2d0000 + 4677500 4662 1c00115e 0007a703 lw x14, 0(x15) x14=0002ffd0 x15:1c2d0000 PA:1c2d0000 + 4692500 4677 1c001160 00b74963 blt x14, x11, 18 x14:0002ffd0 x11:00000010 + 4693500 4678 1c001164 00b71c63 bne x14, x11, 24 x14:0002ffd0 x11:00000010 + 4696500 4681 1c00117c 40b70733 sub x14, x14, x11 x14=0002ffc0 x14:0002ffd0 x11:00000010 + 4697500 4682 1c00117e 00e7a023 sw x14, 0(x15) x14:0002ffc0 x15:1c2d0000 PA:1c2d0000 + 4715500 4700 1c001180 00e787b3 add x15, x15, x14 x15=1c2fffc0 x15:1c2d0000 x14:0002ffc0 + 4716500 4701 1c001182 fedff06f jal x0, -20 + 4718500 4703 1c00116e 00f00533 add x10, x0, x15 x10=1c2fffc0 x15:1c2fffc0 + 4719500 4704 1c001170 00008067 jalr x0, x1, 0 x1:1c000e14 + 4721500 4706 1c000e14 00c12603 lw x12, 12(x2) x12=00000000 x2:10000940 PA:1000094c + 4722500 4707 1c000e16 02050263 beq x10, x0, 36 x10:1c2fffc0 + 4723500 4708 1c000e18 100007b7 lui x15, 0x10000000 x15=10000000 + 4724500 4709 1c000e1c 00241413 slli x8, x8, 0x2 x8=00000010 x8:00000004 + 4725500 4710 1c000e1e 05878793 addi x15, x15, 88 x15=10000058 x15:10000000 + 4726500 4711 1c000e22 008787b3 add x15, x15, x8 x15=10000068 x15:10000058 x8:00000010 + 4727500 4712 1c000e24 0007a703 lw x14, 0(x15) x14=00000000 x15:10000068 PA:10000068 + 4728500 4713 1c000e26 00952023 sw x9, 0(x10) x9:1c002004 x10:1c2fffc0 PA:1c2fffc0 + 4746500 4731 1c000e28 00c52223 sw x12, 4(x10) x12:00000000 x10:1c2fffc0 PA:1c2fffc4 + 4764500 4749 1c000e2a 00e52423 sw x14, 8(x10) x14:00000000 x10:1c2fffc0 PA:1c2fffc8 + 4782500 4767 1c000e2c 00a7a023 sw x10, 0(x15) x10:1c2fffc0 x15:10000068 PA:10000068 + 4783500 4768 1c000e2e 00000513 addi x10, x0, 0 x10=00000000 + 4784500 4769 1c000e30 01c12083 lw x1, 28(x2) x1=1c0020ba x2:10000940 PA:1000095c + 4785500 4770 1c000e32 01812403 lw x8, 24(x2) x8=10000990 x2:10000940 PA:10000958 + 4786500 4771 1c000e34 01412483 lw x9, 20(x2) x9=1000017c x2:10000940 PA:10000954 + 4787500 4772 1c000e36 02010113 addi x2, x2, 32 x2=10000960 x2:10000940 + 4788500 4773 1c000e38 00008067 jalr x0, x1, 0 x1:1c0020ba + 4790500 4775 1c0020ba 1c0025b7 lui x11, 0x1c002000 x11=1c002000 + 4791500 4776 1c0020be 00a00433 add x8, x0, x10 x8=00000000 x10:00000000 + 4808500 4793 1c0020c0 00000613 addi x12, x0, 0 x12=00000000 + 4809500 4794 1c0020c2 fe458593 addi x11, x11, -28 x11=1c001fe4 x11:1c002000 + 4810500 4795 1c0020c6 00500513 addi x10, x0, 5 x10=00000005 + 4811500 4796 1c0020c8 d39fe0ef jal x1, -4808 x1=1c0020cc + 4813500 4798 1c000e00 fe010113 addi x2, x2, -32 x2=10000940 x2:10000960 + 4814500 4799 1c000e02 00812c23 sw x8, 24(x2) x8:00000000 x2:10000940 PA:10000958 + 4815500 4800 1c000e04 00912a23 sw x9, 20(x2) x9:1000017c x2:10000940 PA:10000954 + 4816500 4801 1c000e06 00a00433 add x8, x0, x10 x8=00000005 x10:00000005 + 4817500 4802 1c000e08 00b004b3 add x9, x0, x11 x9=1c001fe4 x11:1c001fe4 + 4818500 4803 1c000e0a 00100513 addi x10, x0, 1 x10=00000001 + 4819500 4804 1c000e0c 00c00593 addi x11, x0, 12 x11=0000000c + 4820500 4805 1c000e0e 00c12623 sw x12, 12(x2) x12:00000000 x2:10000940 PA:1000094c + 4821500 4806 1c000e10 00112e23 sw x1, 28(x2) x1:1c0020cc x2:10000940 PA:1000095c + 4822500 4807 1c000e12 3be000ef jal x1, 958 x1=1c000e14 + 4824500 4809 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 4825500 4810 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000001 + 4828500 4813 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4829500 4814 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 4830500 4815 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 4831500 4816 1c0011f0 ff3ff06f jal x0, -14 + 4833500 4818 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a4 x10:00000004 x15:1c0026a0 + 4834500 4819 1c0011e4 f6fff06f jal x0, -146 + 4836500 4821 1c001152 00052783 lw x15, 0(x10) x15=1c2d0000 x10:1c0026a4 PA:1c0026a4 + 4850500 4835 1c001154 00758593 addi x11, x11, 7 x11=00000013 x11:0000000c + 4851500 4836 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000013 + 4852500 4837 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 4853500 4838 1c00115c 00078963 beq x15, x0, 18 x15:1c2d0000 + 4854500 4839 1c00115e 0007a703 lw x14, 0(x15) x14=0002ffc0 x15:1c2d0000 PA:1c2d0000 + 4869500 4854 1c001160 00b74963 blt x14, x11, 18 x14:0002ffc0 x11:00000010 + 4870500 4855 1c001164 00b71c63 bne x14, x11, 24 x14:0002ffc0 x11:00000010 + 4873500 4858 1c00117c 40b70733 sub x14, x14, x11 x14=0002ffb0 x14:0002ffc0 x11:00000010 + 4874500 4859 1c00117e 00e7a023 sw x14, 0(x15) x14:0002ffb0 x15:1c2d0000 PA:1c2d0000 + 4892500 4877 1c001180 00e787b3 add x15, x15, x14 x15=1c2fffb0 x15:1c2d0000 x14:0002ffb0 + 4893500 4878 1c001182 fedff06f jal x0, -20 + 4895500 4880 1c00116e 00f00533 add x10, x0, x15 x10=1c2fffb0 x15:1c2fffb0 + 4896500 4881 1c001170 00008067 jalr x0, x1, 0 x1:1c000e14 + 4898500 4883 1c000e14 00c12603 lw x12, 12(x2) x12=00000000 x2:10000940 PA:1000094c + 4899500 4884 1c000e16 02050263 beq x10, x0, 36 x10:1c2fffb0 + 4900500 4885 1c000e18 100007b7 lui x15, 0x10000000 x15=10000000 + 4901500 4886 1c000e1c 00241413 slli x8, x8, 0x2 x8=00000014 x8:00000005 + 4902500 4887 1c000e1e 05878793 addi x15, x15, 88 x15=10000058 x15:10000000 + 4903500 4888 1c000e22 008787b3 add x15, x15, x8 x15=1000006c x15:10000058 x8:00000014 + 4904500 4889 1c000e24 0007a703 lw x14, 0(x15) x14=00000000 x15:1000006c PA:1000006c + 4905500 4890 1c000e26 00952023 sw x9, 0(x10) x9:1c001fe4 x10:1c2fffb0 PA:1c2fffb0 + 4923500 4908 1c000e28 00c52223 sw x12, 4(x10) x12:00000000 x10:1c2fffb0 PA:1c2fffb4 + 4941500 4926 1c000e2a 00e52423 sw x14, 8(x10) x14:00000000 x10:1c2fffb0 PA:1c2fffb8 + 4959500 4944 1c000e2c 00a7a023 sw x10, 0(x15) x10:1c2fffb0 x15:1000006c PA:1000006c + 4960500 4945 1c000e2e 00000513 addi x10, x0, 0 x10=00000000 + 4961500 4946 1c000e30 01c12083 lw x1, 28(x2) x1=1c0020cc x2:10000940 PA:1000095c + 4962500 4947 1c000e32 01812403 lw x8, 24(x2) x8=00000000 x2:10000940 PA:10000958 + 4963500 4948 1c000e34 01412483 lw x9, 20(x2) x9=1000017c x2:10000940 PA:10000954 + 4964500 4949 1c000e36 02010113 addi x2, x2, 32 x2=10000960 x2:10000940 + 4965500 4950 1c000e38 00008067 jalr x0, x1, 0 x1:1c0020cc + 4967500 4952 1c0020cc 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 4984500 4969 1c0020d0 6607a423 sw x0, 1640(x15) x15:1c002000 PA:1c002668 + 5002500 4987 1c0020d4 00856533 or x10, x10, x8 x10=00000000 x10:00000000 x8:00000000 + 5003500 4988 1c0020d6 02050163 beq x10, x0, 34 x10:00000000 + 5022500 5007 1c0020f8 00c12083 lw x1, 12(x2) x1=1c000d08 x2:10000960 PA:1000096c + 5023500 5008 1c0020fa 00812403 lw x8, 8(x2) x8=10000990 x2:10000960 PA:10000968 + 5024500 5009 1c0020fc 01010113 addi x2, x2, 16 x2=10000970 x2:10000960 + 5025500 5010 1c0020fe 00008067 jalr x0, x1, 0 x1:1c000d08 + 5042500 5027 1c000d08 f95ff06f jal x0, -108 + 5044500 5029 1c000c9c 0044a78b p.lw x15, 4(x9!) x15=00000000 x9=10000180 x9:1000017c PA:1000017c + 5046500 5031 1c000ca0 06079363 bne x15, x0, 102 x15:00000000 + 5047500 5032 1c000ca2 30045073 csrrwi x0, 0x00000008, 0x300 + 5051500 5036 1c000ca6 00000513 addi x10, x0, 0 x10=00000000 + 5052500 5037 1c000ca8 196000ef jal x1, 406 x1=1c000caa + 5054500 5039 1c000e3e ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 5071500 5056 1c000e40 00812423 sw x8, 8(x2) x8:10000990 x2:10000960 PA:10000968 + 5072500 5057 1c000e42 10000437 lui x8, 0x10000000 x8=10000000 + 5073500 5058 1c000e46 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 5074500 5059 1c000e48 05840413 addi x8, x8, 88 x8=10000058 x8:10000000 + 5075500 5060 1c000e4c 20a47403 lw x8, x10(x8) x8=1c2fffe0 x10:00000000 x8:10000058 PA:10000058 + 5092500 5077 1c000e50 00112623 sw x1, 12(x2) x1:1c000caa x2:10000960 PA:1000096c + 5093500 5078 1c000e52 00041663 bne x8, x0, 12 x8:1c2fffe0 + 5096500 5081 1c000e5e 00042783 lw x15, 0(x8) x15=1c0017b8 x8:1c2fffe0 PA:1c2fffe0 + 5110500 5095 1c000e60 00442503 lw x10, 4(x8) x10=00000000 x8:1c2fffe0 PA:1c2fffe4 + 5124500 5109 1c000e62 000780e7 jalr x1, x15, 0 x1=1c000e64 x15:1c0017b8 + 5130500 5115 1c0017b8 fe010113 addi x2, x2, -32 x2=10000940 x2:10000960 + 5131500 5116 1c0017ba 00810513 addi x10, x2, 8 x10=10000948 x2:10000940 + 5132500 5117 1c0017bc 00112e23 sw x1, 28(x2) x1:1c000e64 x2:10000940 PA:1000095c + 5149500 5134 1c0017be 061000ef jal x1, 2144 x1=1c0017c2 + 5167500 5152 1c00201e 0001c7b7 lui x15, 0x1c000 x15=0001c000 + 5184500 5169 1c002020 20078793 addi x15, x15, 512 x15=0001c200 x15:0001c000 + 5185500 5170 1c002024 00f52023 sw x15, 0(x10) x15:0001c200 x10:10000948 PA:10000948 + 5186500 5171 1c002026 00008067 jalr x0, x1, 0 x1:1c0017c2 + 5188500 5173 1c0017c2 0001c7b7 lui x15, 0x1c000 x15=0001c000 + 5189500 5174 1c0017c6 20078793 addi x15, x15, 512 x15=0001c200 x15:0001c000 + 5190500 5175 1c0017ca 00f12423 sw x15, 8(x2) x15:0001c200 x2:10000940 PA:10000948 + 5191500 5176 1c0017cc 100007b7 lui x15, 0x10000000 x15=10000000 + 5208500 5193 1c0017d0 15c7a783 lw x15, 348(x15) x15=10000070 x15:10000000 PA:1000015c + 5209500 5194 1c0017d4 1c002537 lui x10, 0x1c002000 x10=1c002000 + 5210500 5195 1c0017d8 5f850513 addi x10, x10, 1528 x10=1c0025f8 x10:1c002000 + 5211500 5196 1c0017dc 0b87a583 lw x11, 184(x15) x11=1000013c x15:10000070 PA:10000128 + 5228500 5213 1c0017e0 ed8ff0ef jal x1, -2344 x1=1c0017e4 + 5230500 5215 1c000eb8 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 5231500 5216 1c000eba 00812423 sw x8, 8(x2) x8:1c2fffe0 x2:10000930 PA:10000938 + 5232500 5217 1c000ebc 00912223 sw x9, 4(x2) x9:10000180 x2:10000930 PA:10000934 + 5233500 5218 1c000ebe 00112623 sw x1, 12(x2) x1:1c0017e4 x2:10000930 PA:1000093c + 5234500 5219 1c000ec0 00a00433 add x8, x0, x10 x8=1c0025f8 x10:1c0025f8 + 5235500 5220 1c000ec2 00b004b3 add x9, x0, x11 x9=1000013c x11:1000013c + 5236500 5221 1c000ec4 00052823 sw x0, 16(x10) x10:1c0025f8 PA:1c002608 + 5254500 5239 1c000ec8 00052a23 sw x0, 20(x10) x10:1c0025f8 PA:1c00260c + 5272500 5257 1c000ecc 01000593 addi x11, x0, 16 x11=00000010 + 5273500 5258 1c000ece 00000513 addi x10, x0, 0 x10=00000000 + 5274500 5259 1c000ed0 300000ef jal x1, 768 x1=1c000ed2 + 5276500 5261 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 5277500 5262 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000000 + 5280500 5265 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 5281500 5266 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 5282500 5267 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 5283500 5268 1c0011f0 ff3ff06f jal x0, -14 + 5285500 5270 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a0 x10:00000000 x15:1c0026a0 + 5286500 5271 1c0011e4 f6fff06f jal x0, -146 + 5288500 5273 1c001152 00052783 lw x15, 0(x10) x15=1c0026b8 x10:1c0026a0 PA:1c0026a0 + 5302500 5287 1c001154 00758593 addi x11, x11, 7 x11=00000017 x11:00000010 + 5303500 5288 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000017 + 5304500 5289 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 5305500 5290 1c00115c 00078963 beq x15, x0, 18 x15:1c0026b8 + 5306500 5291 1c00115e 0007a703 lw x14, 0(x15) x14=002cd928 x15:1c0026b8 PA:1c0026b8 + 5321500 5306 1c001160 00b74963 blt x14, x11, 18 x14:002cd928 x11:00000010 + 5322500 5307 1c001164 00b71c63 bne x14, x11, 24 x14:002cd928 x11:00000010 + 5325500 5310 1c00117c 40b70733 sub x14, x14, x11 x14=002cd918 x14:002cd928 x11:00000010 + 5326500 5311 1c00117e 00e7a023 sw x14, 0(x15) x14:002cd918 x15:1c0026b8 PA:1c0026b8 + 5344500 5329 1c001180 00e787b3 add x15, x15, x14 x15=1c2cffd0 x15:1c0026b8 x14:002cd918 + 5345500 5330 1c001182 fedff06f jal x0, -20 + 5347500 5332 1c00116e 00f00533 add x10, x0, x15 x10=1c2cffd0 x15:1c2cffd0 + 5348500 5333 1c001170 00008067 jalr x0, x1, 0 x1:1c000ed2 + 5350500 5335 1c000ed2 06a42623 sw x10, 108(x8) x10:1c2cffd0 x8:1c0025f8 PA:1c002664 + 5368500 5353 1c000ed4 00942623 sw x9, 12(x8) x9:1000013c x8:1c0025f8 PA:1c002604 + 5386500 5371 1c000ed6 00042023 sw x0, 0(x8) x8:1c0025f8 PA:1c0025f8 + 5404500 5389 1c000eda 00c12083 lw x1, 12(x2) x1=1c0017e4 x2:10000930 PA:1000093c + 5405500 5390 1c000edc 00812403 lw x8, 8(x2) x8=1c2fffe0 x2:10000930 PA:10000938 + 5406500 5391 1c000ede 00412483 lw x9, 4(x2) x9=10000180 x2:10000930 PA:10000934 + 5407500 5392 1c000ee0 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 5408500 5393 1c000ee2 00008067 jalr x0, x1, 0 x1:1c0017e4 + 5410500 5395 1c0017e4 00810593 addi x11, x2, 8 x11=10000948 x2:10000940 + 5411500 5396 1c0017e6 00000693 addi x13, x0, 0 x13=00000000 + 5412500 5397 1c0017e8 00000613 addi x12, x0, 0 x12=00000000 + 5413500 5398 1c0017ea 00000513 addi x10, x0, 0 x10=00000000 + 5414500 5399 1c0017ec 03d000ef jal x1, 2108 x1=1c0017f0 + 5432500 5417 1c002028 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 5433500 5418 1c00202a 00112623 sw x1, 12(x2) x1:1c0017f0 x2:10000930 PA:1000093c + 5434500 5419 1c00202c 00812423 sw x8, 8(x2) x8:1c2fffe0 x2:10000930 PA:10000938 + 5435500 5420 1c00202e 00912223 sw x9, 4(x2) x9:10000180 x2:10000930 PA:10000934 + 5451500 5436 1c002030 300474f3 csrrci x9, 0x00000008, 0x300 x9=00001808 + 5455500 5440 1c002034 02058a63 beq x11, x0, 52 x11:10000948 + 5456500 5441 1c002036 0005a503 lw x10, 0(x11) x10=0001c200 x11:10000948 PA:10000948 + 5457500 5442 1c002038 1c002437 lui x8, 0x1c002000 x8=1c002000 + 5458500 5443 1c00203c 66840793 addi x15, x8, 1640 x15=1c002668 x8:1c002000 + 5475500 5460 1c002040 0007a703 lw x14, 0(x15) x14=00000000 x15:1c002668 PA:1c002668 + 5489500 5474 1c002042 008006b3 add x13, x0, x8 x13=1c002000 x8:1c002000 + 5490500 5475 1c002044 66840613 addi x12, x8, 1640 x12=1c002668 x8:1c002000 + 5491500 5476 1c002048 02070463 beq x14, x0, 40 x14:00000000 + 5510500 5495 1c002070 00100713 addi x14, x0, 1 x14=00000001 + 5511500 5496 1c002072 00e7a023 sw x14, 0(x15) x14:00000001 x15:1c002668 PA:1c002668 + 5529500 5514 1c002074 00a7a423 sw x10, 8(x15) x10:0001c200 x15:1c002668 PA:1c002670 + 5547500 5532 1c002076 00e7a623 sw x14, 12(x15) x14:00000001 x15:1c002668 PA:1c002674 + 5565500 5550 1c002078 f17ff0ef jal x1, -234 x1=1c00207a + 5583500 5568 1c001f8e 02faf7b7 lui x15, 0x2faf000 x15=02faf000 + 5584500 5569 1c001f92 08078793 addi x15, x15, 128 x15=02faf080 x15:02faf000 + 5585500 5570 1c001f96 02a7d533 divu x10, x15, x10 x10=000001b2 x15:02faf000 x10:0001c200 + 5603500 5588 1c001f9a 1a1027b7 lui x15, 0x1a102000 x15=1a102000 + 5604500 5589 1c001f9e 00c78613 addi x12, x15, 12 x12=1a10200c x15:1a102000 + 5605500 5590 1c001fa2 08300713 addi x14, x0, 131 x14=00000083 + 5606500 5591 1c001fa6 00e62023 sw x14, 0(x12) x14:00000083 x12:1a10200c PA:1a10200c + 5626500 5611 1c001fa8 00478693 addi x13, x15, 4 x13=1a102004 x15:1a102000 + 5627500 5612 1c001fac 0a700593 addi x11, x0, 167 x11=000000a7 + 5628500 5613 1c001fb0 00455513 srli x10, x10, 0x4 x10=0000001b x10:000001b2 + 5629500 5614 1c001fb2 fff50513 addi x10, x10, -1 x10=0000001a x10:0000001b + 5630500 5615 1c001fb4 40855713 srai x14, x10, 0x408 x14=00000000 x10:0000001a + 5631500 5616 1c001fb8 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 5632500 5617 1c001fbc 00e6a023 sw x14, 0(x13) x14:00000000 x13:1a102004 PA:1a102004 + 5653500 5638 1c001fbe ee853533 p.bclr x10, x10, 23, 8 x10=0000001a x10:0000001a + 5654500 5639 1c001fc2 00f00733 add x14, x0, x15 x14=1a102000 x15:1a102000 + 5655500 5640 1c001fc4 00a7242b p.sw x10, 8(x14!) x14=1a102008 x10:0000001a x14:1a102000 PA:1a102000 + 5675500 5660 1c001fc8 00b72023 sw x11, 0(x14) x11:000000a7 x14:1a102008 PA:1a102008 + 5695500 5680 1c001fca 00300713 addi x14, x0, 3 x14=00000003 + 5696500 5681 1c001fcc 00e62023 sw x14, 0(x12) x14:00000003 x12:1a10200c PA:1a10200c + 5716500 5701 1c001fce 0006a703 lw x14, 0(x13) x14=00000000 x13:1a102004 PA:1a102004 + 5733500 5718 1c001fd0 01078793 addi x15, x15, 16 x15=1a102010 x15:1a102000 + 5734500 5719 1c001fd2 0f077713 andi x14, x14, 240 x14=00000000 x14:00000000 + 5735500 5720 1c001fd6 c0174733 p.bset x14, x14, 0, 1 x14=00000002 x14:00000000 + 5736500 5721 1c001fda 00e6a023 sw x14, 0(x13) x14:00000002 x13:1a102004 PA:1a102004 + 5756500 5741 1c001fdc 02000713 addi x14, x0, 32 x14=00000020 + 5757500 5742 1c001fe0 00e7a023 sw x14, 0(x15) x14:00000020 x15:1a102010 PA:1a102010 + 5777500 5762 1c001fe2 00008067 jalr x0, x1, 0 x1:1c00207a + 5778500 5763 1c00207a 30049073 csrrw x0, x9, 0x300 x9:00001808 + 5795500 5780 1c00207e 66840513 addi x10, x8, 1640 x10=1c002668 x8:1c002000 + 5796500 5781 1c002082 fddff06f jal x0, -36 + 5814500 5799 1c00205e 00c12083 lw x1, 12(x2) x1=1c0017f0 x2:10000930 PA:1000093c + 5831500 5816 1c002060 00812403 lw x8, 8(x2) x8=1c2fffe0 x2:10000930 PA:10000938 + 5832500 5817 1c002062 00412483 lw x9, 4(x2) x9=10000180 x2:10000930 PA:10000934 + 5833500 5818 1c002064 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 5834500 5819 1c002066 00008067 jalr x0, x1, 0 x1:1c0017f0 + 5836500 5821 1c0017f0 01c12083 lw x1, 28(x2) x1=1c000e64 x2:10000940 PA:1000095c + 5837500 5822 1c0017f2 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 5838500 5823 1c0017f6 66a7ae23 sw x10, 1660(x15) x10:1c002668 x15:1c002000 PA:1c00267c + 5856500 5841 1c0017fa 00000513 addi x10, x0, 0 x10=00000000 + 5857500 5842 1c0017fc 02010113 addi x2, x2, 32 x2=10000960 x2:10000940 + 5858500 5843 1c0017fe 00008067 jalr x0, x1, 0 x1:1c000e64 + 5860500 5845 1c000e64 00051363 bne x10, x0, 6 x10:00000000 + 5861500 5846 1c000e66 00842403 lw x8, 8(x8) x8=1c2ffff0 x8:1c2fffe0 PA:1c2fffe8 + 5875500 5860 1c000e68 febff06f jal x0, -22 + 5876500 5861 1c000e52 00041663 bne x8, x0, 12 x8:1c2ffff0 + 5879500 5864 1c000e5e 00042783 lw x15, 0(x8) x15=1c001324 x8:1c2ffff0 PA:1c2ffff0 + 5893500 5878 1c000e60 00442503 lw x10, 4(x8) x10=00000000 x8:1c2ffff0 PA:1c2ffff4 + 5907500 5892 1c000e62 000780e7 jalr x1, x15, 0 x1=1c000e64 x15:1c001324 + 5913500 5898 1c001324 00400793 addi x15, x0, 4 x15=00000004 + 5914500 5899 1c001328 01800613 addi x12, x0, 24 x12=00000018 + 5915500 5900 1c00132a 02f60633 mul x12, x12, x15 x12=00000060 x12:00000018 x15:00000004 + 5916500 5901 1c00132e fe010113 addi x2, x2, -32 x2=10000940 x2:10000960 + 5933500 5918 1c001330 00100513 addi x10, x0, 1 x10=00000001 + 5934500 5919 1c001332 00112e23 sw x1, 28(x2) x1:1c000e64 x2:10000940 PA:1000095c + 5935500 5920 1c001334 00812c23 sw x8, 24(x2) x8:1c2ffff0 x2:10000940 PA:10000958 + 5936500 5921 1c001336 00912a23 sw x9, 20(x2) x9:10000180 x2:10000940 PA:10000954 + 5937500 5922 1c001338 00c005b3 add x11, x0, x12 x11=00000060 x12:00000060 + 5938500 5923 1c00133a 00c12623 sw x12, 12(x2) x12:00000060 x2:10000940 PA:1000094c + 5939500 5924 1c00133c e95ff0ef jal x1, -364 x1=1c00133e + 5957500 5942 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 5958500 5943 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000001 + 5961500 5946 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 5962500 5947 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 5963500 5948 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 5964500 5949 1c0011f0 ff3ff06f jal x0, -14 + 5966500 5951 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a4 x10:00000004 x15:1c0026a0 + 5967500 5952 1c0011e4 f6fff06f jal x0, -146 + 5969500 5954 1c001152 00052783 lw x15, 0(x10) x15=1c2d0000 x10:1c0026a4 PA:1c0026a4 + 5983500 5968 1c001154 00758593 addi x11, x11, 7 x11=00000067 x11:00000060 + 5984500 5969 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000060 x11:00000067 + 5985500 5970 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 5986500 5971 1c00115c 00078963 beq x15, x0, 18 x15:1c2d0000 + 5987500 5972 1c00115e 0007a703 lw x14, 0(x15) x14=0002ffb0 x15:1c2d0000 PA:1c2d0000 + 6002500 5987 1c001160 00b74963 blt x14, x11, 18 x14:0002ffb0 x11:00000060 + 6003500 5988 1c001164 00b71c63 bne x14, x11, 24 x14:0002ffb0 x11:00000060 + 6006500 5991 1c00117c 40b70733 sub x14, x14, x11 x14=0002ff50 x14:0002ffb0 x11:00000060 + 6007500 5992 1c00117e 00e7a023 sw x14, 0(x15) x14:0002ff50 x15:1c2d0000 PA:1c2d0000 + 6025500 6010 1c001180 00e787b3 add x15, x15, x14 x15=1c2fff50 x15:1c2d0000 x14:0002ff50 + 6026500 6011 1c001182 fedff06f jal x0, -20 + 6028500 6013 1c00116e 00f00533 add x10, x0, x15 x10=1c2fff50 x15:1c2fff50 + 6029500 6014 1c001170 00008067 jalr x0, x1, 0 x1:1c00133e + 6032500 6017 1c00133e 1c002737 lui x14, 0x1c002000 x14=1c002000 + 6033500 6018 1c001342 6aa72423 sw x10, 1704(x14) x10:1c2fff50 x14:1c002000 PA:1c0026a8 + 6051500 6036 1c001346 00c12603 lw x12, 12(x2) x12=00000060 x2:10000940 PA:1000094c + 6052500 6037 1c001348 00051f63 bne x10, x0, 30 x10:1c2fff50 + 6087500 6072 1c001366 00000593 addi x11, x0, 0 x11=00000000 + 6088500 6073 1c001368 498000ef jal x1, 1176 x1=1c00136a + 6090500 6075 1c001800 00a60633 add x12, x12, x10 x12=1c2fffb0 x12:00000060 x10:1c2fff50 + 6091500 6076 1c001802 00a007b3 add x15, x0, x10 x15=1c2fff50 x10:1c2fff50 + 6092500 6077 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff50 x12:1c2fffb0 + 6095500 6080 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff51 x11:00000000 x15:1c2fff50 PA:1c2fff50 + 6113500 6098 1c00180e ff7ff06f jal x0, -10 + 6114500 6099 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff51 x12:1c2fffb0 + 6117500 6102 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff52 x11:00000000 x15:1c2fff51 PA:1c2fff51 + 6135500 6120 1c00180e ff7ff06f jal x0, -10 + 6136500 6121 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff52 x12:1c2fffb0 + 6139500 6124 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff53 x11:00000000 x15:1c2fff52 PA:1c2fff52 + 6157500 6142 1c00180e ff7ff06f jal x0, -10 + 6158500 6143 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff53 x12:1c2fffb0 + 6161500 6146 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff54 x11:00000000 x15:1c2fff53 PA:1c2fff53 + 6179500 6164 1c00180e ff7ff06f jal x0, -10 + 6180500 6165 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff54 x12:1c2fffb0 + 6183500 6168 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff55 x11:00000000 x15:1c2fff54 PA:1c2fff54 + 6201500 6186 1c00180e ff7ff06f jal x0, -10 + 6202500 6187 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff55 x12:1c2fffb0 + 6205500 6190 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff56 x11:00000000 x15:1c2fff55 PA:1c2fff55 + 6223500 6208 1c00180e ff7ff06f jal x0, -10 + 6224500 6209 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff56 x12:1c2fffb0 + 6227500 6212 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff57 x11:00000000 x15:1c2fff56 PA:1c2fff56 + 6245500 6230 1c00180e ff7ff06f jal x0, -10 + 6246500 6231 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff57 x12:1c2fffb0 + 6249500 6234 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff58 x11:00000000 x15:1c2fff57 PA:1c2fff57 + 6267500 6252 1c00180e ff7ff06f jal x0, -10 + 6268500 6253 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff58 x12:1c2fffb0 + 6271500 6256 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff59 x11:00000000 x15:1c2fff58 PA:1c2fff58 + 6289500 6274 1c00180e ff7ff06f jal x0, -10 + 6290500 6275 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff59 x12:1c2fffb0 + 6293500 6278 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff5a x11:00000000 x15:1c2fff59 PA:1c2fff59 + 6311500 6296 1c00180e ff7ff06f jal x0, -10 + 6312500 6297 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff5a x12:1c2fffb0 + 6315500 6300 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff5b x11:00000000 x15:1c2fff5a PA:1c2fff5a + 6333500 6318 1c00180e ff7ff06f jal x0, -10 + 6334500 6319 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff5b x12:1c2fffb0 + 6337500 6322 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff5c x11:00000000 x15:1c2fff5b PA:1c2fff5b + 6355500 6340 1c00180e ff7ff06f jal x0, -10 + 6356500 6341 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff5c x12:1c2fffb0 + 6359500 6344 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff5d x11:00000000 x15:1c2fff5c PA:1c2fff5c + 6377500 6362 1c00180e ff7ff06f jal x0, -10 + 6378500 6363 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff5d x12:1c2fffb0 + 6381500 6366 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff5e x11:00000000 x15:1c2fff5d PA:1c2fff5d + 6399500 6384 1c00180e ff7ff06f jal x0, -10 + 6400500 6385 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff5e x12:1c2fffb0 + 6403500 6388 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff5f x11:00000000 x15:1c2fff5e PA:1c2fff5e + 6421500 6406 1c00180e ff7ff06f jal x0, -10 + 6422500 6407 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff5f x12:1c2fffb0 + 6425500 6410 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff60 x11:00000000 x15:1c2fff5f PA:1c2fff5f + 6443500 6428 1c00180e ff7ff06f jal x0, -10 + 6444500 6429 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff60 x12:1c2fffb0 + 6447500 6432 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff61 x11:00000000 x15:1c2fff60 PA:1c2fff60 + 6465500 6450 1c00180e ff7ff06f jal x0, -10 + 6466500 6451 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff61 x12:1c2fffb0 + 6469500 6454 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff62 x11:00000000 x15:1c2fff61 PA:1c2fff61 + 6487500 6472 1c00180e ff7ff06f jal x0, -10 + 6488500 6473 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff62 x12:1c2fffb0 + 6491500 6476 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff63 x11:00000000 x15:1c2fff62 PA:1c2fff62 + 6509500 6494 1c00180e ff7ff06f jal x0, -10 + 6510500 6495 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff63 x12:1c2fffb0 + 6513500 6498 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff64 x11:00000000 x15:1c2fff63 PA:1c2fff63 + 6531500 6516 1c00180e ff7ff06f jal x0, -10 + 6532500 6517 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff64 x12:1c2fffb0 + 6535500 6520 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff65 x11:00000000 x15:1c2fff64 PA:1c2fff64 + 6553500 6538 1c00180e ff7ff06f jal x0, -10 + 6554500 6539 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff65 x12:1c2fffb0 + 6557500 6542 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff66 x11:00000000 x15:1c2fff65 PA:1c2fff65 + 6575500 6560 1c00180e ff7ff06f jal x0, -10 + 6576500 6561 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff66 x12:1c2fffb0 + 6579500 6564 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff67 x11:00000000 x15:1c2fff66 PA:1c2fff66 + 6597500 6582 1c00180e ff7ff06f jal x0, -10 + 6598500 6583 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff67 x12:1c2fffb0 + 6601500 6586 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff68 x11:00000000 x15:1c2fff67 PA:1c2fff67 + 6619500 6604 1c00180e ff7ff06f jal x0, -10 + 6620500 6605 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff68 x12:1c2fffb0 + 6623500 6608 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff69 x11:00000000 x15:1c2fff68 PA:1c2fff68 + 6641500 6626 1c00180e ff7ff06f jal x0, -10 + 6642500 6627 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff69 x12:1c2fffb0 + 6645500 6630 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff6a x11:00000000 x15:1c2fff69 PA:1c2fff69 + 6663500 6648 1c00180e ff7ff06f jal x0, -10 + 6664500 6649 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff6a x12:1c2fffb0 + 6667500 6652 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff6b x11:00000000 x15:1c2fff6a PA:1c2fff6a + 6685500 6670 1c00180e ff7ff06f jal x0, -10 + 6686500 6671 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff6b x12:1c2fffb0 + 6689500 6674 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff6c x11:00000000 x15:1c2fff6b PA:1c2fff6b + 6707500 6692 1c00180e ff7ff06f jal x0, -10 + 6708500 6693 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff6c x12:1c2fffb0 + 6711500 6696 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff6d x11:00000000 x15:1c2fff6c PA:1c2fff6c + 6729500 6714 1c00180e ff7ff06f jal x0, -10 + 6730500 6715 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff6d x12:1c2fffb0 + 6733500 6718 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff6e x11:00000000 x15:1c2fff6d PA:1c2fff6d + 6751500 6736 1c00180e ff7ff06f jal x0, -10 + 6752500 6737 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff6e x12:1c2fffb0 + 6755500 6740 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff6f x11:00000000 x15:1c2fff6e PA:1c2fff6e + 6773500 6758 1c00180e ff7ff06f jal x0, -10 + 6774500 6759 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff6f x12:1c2fffb0 + 6777500 6762 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff70 x11:00000000 x15:1c2fff6f PA:1c2fff6f + 6795500 6780 1c00180e ff7ff06f jal x0, -10 + 6796500 6781 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff70 x12:1c2fffb0 + 6799500 6784 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff71 x11:00000000 x15:1c2fff70 PA:1c2fff70 + 6817500 6802 1c00180e ff7ff06f jal x0, -10 + 6818500 6803 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff71 x12:1c2fffb0 + 6821500 6806 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff72 x11:00000000 x15:1c2fff71 PA:1c2fff71 + 6839500 6824 1c00180e ff7ff06f jal x0, -10 + 6840500 6825 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff72 x12:1c2fffb0 + 6843500 6828 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff73 x11:00000000 x15:1c2fff72 PA:1c2fff72 + 6861500 6846 1c00180e ff7ff06f jal x0, -10 + 6862500 6847 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff73 x12:1c2fffb0 + 6865500 6850 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff74 x11:00000000 x15:1c2fff73 PA:1c2fff73 + 6883500 6868 1c00180e ff7ff06f jal x0, -10 + 6884500 6869 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff74 x12:1c2fffb0 + 6887500 6872 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff75 x11:00000000 x15:1c2fff74 PA:1c2fff74 + 6905500 6890 1c00180e ff7ff06f jal x0, -10 + 6906500 6891 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff75 x12:1c2fffb0 + 6909500 6894 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff76 x11:00000000 x15:1c2fff75 PA:1c2fff75 + 6927500 6912 1c00180e ff7ff06f jal x0, -10 + 6928500 6913 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff76 x12:1c2fffb0 + 6931500 6916 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff77 x11:00000000 x15:1c2fff76 PA:1c2fff76 + 6949500 6934 1c00180e ff7ff06f jal x0, -10 + 6950500 6935 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff77 x12:1c2fffb0 + 6953500 6938 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff78 x11:00000000 x15:1c2fff77 PA:1c2fff77 + 6971500 6956 1c00180e ff7ff06f jal x0, -10 + 6972500 6957 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff78 x12:1c2fffb0 + 6975500 6960 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff79 x11:00000000 x15:1c2fff78 PA:1c2fff78 + 6993500 6978 1c00180e ff7ff06f jal x0, -10 + 6994500 6979 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff79 x12:1c2fffb0 + 6997500 6982 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff7a x11:00000000 x15:1c2fff79 PA:1c2fff79 + 7015500 7000 1c00180e ff7ff06f jal x0, -10 + 7016500 7001 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff7a x12:1c2fffb0 + 7019500 7004 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff7b x11:00000000 x15:1c2fff7a PA:1c2fff7a + 7037500 7022 1c00180e ff7ff06f jal x0, -10 + 7038500 7023 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff7b x12:1c2fffb0 + 7041500 7026 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff7c x11:00000000 x15:1c2fff7b PA:1c2fff7b + 7059500 7044 1c00180e ff7ff06f jal x0, -10 + 7060500 7045 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff7c x12:1c2fffb0 + 7063500 7048 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff7d x11:00000000 x15:1c2fff7c PA:1c2fff7c + 7081500 7066 1c00180e ff7ff06f jal x0, -10 + 7082500 7067 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff7d x12:1c2fffb0 + 7085500 7070 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff7e x11:00000000 x15:1c2fff7d PA:1c2fff7d + 7103500 7088 1c00180e ff7ff06f jal x0, -10 + 7104500 7089 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff7e x12:1c2fffb0 + 7107500 7092 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff7f x11:00000000 x15:1c2fff7e PA:1c2fff7e + 7125500 7110 1c00180e ff7ff06f jal x0, -10 + 7126500 7111 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff7f x12:1c2fffb0 + 7129500 7114 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff80 x11:00000000 x15:1c2fff7f PA:1c2fff7f + 7147500 7132 1c00180e ff7ff06f jal x0, -10 + 7148500 7133 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff80 x12:1c2fffb0 + 7151500 7136 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff81 x11:00000000 x15:1c2fff80 PA:1c2fff80 + 7169500 7154 1c00180e ff7ff06f jal x0, -10 + 7170500 7155 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff81 x12:1c2fffb0 + 7173500 7158 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff82 x11:00000000 x15:1c2fff81 PA:1c2fff81 + 7191500 7176 1c00180e ff7ff06f jal x0, -10 + 7192500 7177 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff82 x12:1c2fffb0 + 7195500 7180 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff83 x11:00000000 x15:1c2fff82 PA:1c2fff82 + 7213500 7198 1c00180e ff7ff06f jal x0, -10 + 7214500 7199 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff83 x12:1c2fffb0 + 7217500 7202 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff84 x11:00000000 x15:1c2fff83 PA:1c2fff83 + 7235500 7220 1c00180e ff7ff06f jal x0, -10 + 7236500 7221 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff84 x12:1c2fffb0 + 7239500 7224 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff85 x11:00000000 x15:1c2fff84 PA:1c2fff84 + 7257500 7242 1c00180e ff7ff06f jal x0, -10 + 7258500 7243 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff85 x12:1c2fffb0 + 7261500 7246 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff86 x11:00000000 x15:1c2fff85 PA:1c2fff85 + 7279500 7264 1c00180e ff7ff06f jal x0, -10 + 7280500 7265 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff86 x12:1c2fffb0 + 7283500 7268 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff87 x11:00000000 x15:1c2fff86 PA:1c2fff86 + 7301500 7286 1c00180e ff7ff06f jal x0, -10 + 7302500 7287 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff87 x12:1c2fffb0 + 7305500 7290 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff88 x11:00000000 x15:1c2fff87 PA:1c2fff87 + 7323500 7308 1c00180e ff7ff06f jal x0, -10 + 7324500 7309 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff88 x12:1c2fffb0 + 7327500 7312 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff89 x11:00000000 x15:1c2fff88 PA:1c2fff88 + 7345500 7330 1c00180e ff7ff06f jal x0, -10 + 7346500 7331 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff89 x12:1c2fffb0 + 7349500 7334 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff8a x11:00000000 x15:1c2fff89 PA:1c2fff89 + 7367500 7352 1c00180e ff7ff06f jal x0, -10 + 7368500 7353 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff8a x12:1c2fffb0 + 7371500 7356 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff8b x11:00000000 x15:1c2fff8a PA:1c2fff8a + 7389500 7374 1c00180e ff7ff06f jal x0, -10 + 7390500 7375 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff8b x12:1c2fffb0 + 7393500 7378 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff8c x11:00000000 x15:1c2fff8b PA:1c2fff8b + 7411500 7396 1c00180e ff7ff06f jal x0, -10 + 7412500 7397 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff8c x12:1c2fffb0 + 7415500 7400 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff8d x11:00000000 x15:1c2fff8c PA:1c2fff8c + 7433500 7418 1c00180e ff7ff06f jal x0, -10 + 7434500 7419 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff8d x12:1c2fffb0 + 7437500 7422 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff8e x11:00000000 x15:1c2fff8d PA:1c2fff8d + 7455500 7440 1c00180e ff7ff06f jal x0, -10 + 7456500 7441 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff8e x12:1c2fffb0 + 7459500 7444 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff8f x11:00000000 x15:1c2fff8e PA:1c2fff8e + 7477500 7462 1c00180e ff7ff06f jal x0, -10 + 7478500 7463 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff8f x12:1c2fffb0 + 7481500 7466 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff90 x11:00000000 x15:1c2fff8f PA:1c2fff8f + 7499500 7484 1c00180e ff7ff06f jal x0, -10 + 7500500 7485 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff90 x12:1c2fffb0 + 7503500 7488 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff91 x11:00000000 x15:1c2fff90 PA:1c2fff90 + 7521500 7506 1c00180e ff7ff06f jal x0, -10 + 7522500 7507 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff91 x12:1c2fffb0 + 7525500 7510 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff92 x11:00000000 x15:1c2fff91 PA:1c2fff91 + 7543500 7528 1c00180e ff7ff06f jal x0, -10 + 7544500 7529 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff92 x12:1c2fffb0 + 7547500 7532 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff93 x11:00000000 x15:1c2fff92 PA:1c2fff92 + 7565500 7550 1c00180e ff7ff06f jal x0, -10 + 7566500 7551 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff93 x12:1c2fffb0 + 7569500 7554 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff94 x11:00000000 x15:1c2fff93 PA:1c2fff93 + 7587500 7572 1c00180e ff7ff06f jal x0, -10 + 7588500 7573 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff94 x12:1c2fffb0 + 7591500 7576 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff95 x11:00000000 x15:1c2fff94 PA:1c2fff94 + 7609500 7594 1c00180e ff7ff06f jal x0, -10 + 7610500 7595 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff95 x12:1c2fffb0 + 7613500 7598 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff96 x11:00000000 x15:1c2fff95 PA:1c2fff95 + 7631500 7616 1c00180e ff7ff06f jal x0, -10 + 7632500 7617 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff96 x12:1c2fffb0 + 7635500 7620 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff97 x11:00000000 x15:1c2fff96 PA:1c2fff96 + 7653500 7638 1c00180e ff7ff06f jal x0, -10 + 7654500 7639 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff97 x12:1c2fffb0 + 7657500 7642 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff98 x11:00000000 x15:1c2fff97 PA:1c2fff97 + 7675500 7660 1c00180e ff7ff06f jal x0, -10 + 7676500 7661 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff98 x12:1c2fffb0 + 7679500 7664 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff99 x11:00000000 x15:1c2fff98 PA:1c2fff98 + 7697500 7682 1c00180e ff7ff06f jal x0, -10 + 7698500 7683 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff99 x12:1c2fffb0 + 7701500 7686 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff9a x11:00000000 x15:1c2fff99 PA:1c2fff99 + 7719500 7704 1c00180e ff7ff06f jal x0, -10 + 7720500 7705 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff9a x12:1c2fffb0 + 7723500 7708 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff9b x11:00000000 x15:1c2fff9a PA:1c2fff9a + 7741500 7726 1c00180e ff7ff06f jal x0, -10 + 7742500 7727 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff9b x12:1c2fffb0 + 7745500 7730 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff9c x11:00000000 x15:1c2fff9b PA:1c2fff9b + 7763500 7748 1c00180e ff7ff06f jal x0, -10 + 7764500 7749 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff9c x12:1c2fffb0 + 7767500 7752 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff9d x11:00000000 x15:1c2fff9c PA:1c2fff9c + 7785500 7770 1c00180e ff7ff06f jal x0, -10 + 7786500 7771 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff9d x12:1c2fffb0 + 7789500 7774 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff9e x11:00000000 x15:1c2fff9d PA:1c2fff9d + 7807500 7792 1c00180e ff7ff06f jal x0, -10 + 7808500 7793 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff9e x12:1c2fffb0 + 7811500 7796 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fff9f x11:00000000 x15:1c2fff9e PA:1c2fff9e + 7829500 7814 1c00180e ff7ff06f jal x0, -10 + 7830500 7815 1c001804 00c79363 bne x15, x12, 6 x15:1c2fff9f x12:1c2fffb0 + 7833500 7818 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa0 x11:00000000 x15:1c2fff9f PA:1c2fff9f + 7851500 7836 1c00180e ff7ff06f jal x0, -10 + 7852500 7837 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa0 x12:1c2fffb0 + 7855500 7840 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa1 x11:00000000 x15:1c2fffa0 PA:1c2fffa0 + 7873500 7858 1c00180e ff7ff06f jal x0, -10 + 7874500 7859 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa1 x12:1c2fffb0 + 7877500 7862 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa2 x11:00000000 x15:1c2fffa1 PA:1c2fffa1 + 7895500 7880 1c00180e ff7ff06f jal x0, -10 + 7896500 7881 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa2 x12:1c2fffb0 + 7899500 7884 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa3 x11:00000000 x15:1c2fffa2 PA:1c2fffa2 + 7917500 7902 1c00180e ff7ff06f jal x0, -10 + 7918500 7903 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa3 x12:1c2fffb0 + 7921500 7906 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa4 x11:00000000 x15:1c2fffa3 PA:1c2fffa3 + 7939500 7924 1c00180e ff7ff06f jal x0, -10 + 7940500 7925 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa4 x12:1c2fffb0 + 7943500 7928 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa5 x11:00000000 x15:1c2fffa4 PA:1c2fffa4 + 7961500 7946 1c00180e ff7ff06f jal x0, -10 + 7962500 7947 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa5 x12:1c2fffb0 + 7965500 7950 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa6 x11:00000000 x15:1c2fffa5 PA:1c2fffa5 + 7983500 7968 1c00180e ff7ff06f jal x0, -10 + 7984500 7969 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa6 x12:1c2fffb0 + 7987500 7972 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa7 x11:00000000 x15:1c2fffa6 PA:1c2fffa6 + 8005500 7990 1c00180e ff7ff06f jal x0, -10 + 8006500 7991 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa7 x12:1c2fffb0 + 8009500 7994 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa8 x11:00000000 x15:1c2fffa7 PA:1c2fffa7 + 8027500 8012 1c00180e ff7ff06f jal x0, -10 + 8028500 8013 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa8 x12:1c2fffb0 + 8031500 8016 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffa9 x11:00000000 x15:1c2fffa8 PA:1c2fffa8 + 8049500 8034 1c00180e ff7ff06f jal x0, -10 + 8050500 8035 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffa9 x12:1c2fffb0 + 8053500 8038 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffaa x11:00000000 x15:1c2fffa9 PA:1c2fffa9 + 8071500 8056 1c00180e ff7ff06f jal x0, -10 + 8072500 8057 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffaa x12:1c2fffb0 + 8075500 8060 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffab x11:00000000 x15:1c2fffaa PA:1c2fffaa + 8093500 8078 1c00180e ff7ff06f jal x0, -10 + 8094500 8079 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffab x12:1c2fffb0 + 8097500 8082 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffac x11:00000000 x15:1c2fffab PA:1c2fffab + 8115500 8100 1c00180e ff7ff06f jal x0, -10 + 8116500 8101 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffac x12:1c2fffb0 + 8119500 8104 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffad x11:00000000 x15:1c2fffac PA:1c2fffac + 8137500 8122 1c00180e ff7ff06f jal x0, -10 + 8138500 8123 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffad x12:1c2fffb0 + 8141500 8126 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffae x11:00000000 x15:1c2fffad PA:1c2fffad + 8159500 8144 1c00180e ff7ff06f jal x0, -10 + 8160500 8145 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffae x12:1c2fffb0 + 8163500 8148 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffaf x11:00000000 x15:1c2fffae PA:1c2fffae + 8181500 8166 1c00180e ff7ff06f jal x0, -10 + 8182500 8167 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffaf x12:1c2fffb0 + 8185500 8170 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1c2fffb0 x11:00000000 x15:1c2fffaf PA:1c2fffaf + 8203500 8188 1c00180e ff7ff06f jal x0, -10 + 8204500 8189 1c001804 00c79363 bne x15, x12, 6 x15:1c2fffb0 x12:1c2fffb0 + 8205500 8190 1c001808 00008067 jalr x0, x1, 0 x1:1c00136a + 8207500 8192 1c00136a 1c0005b7 lui x11, 0x1c000000 x11=1c000000 + 8225500 8210 1c00136e 17258593 addi x11, x11, 370 x11=1c000172 x11:1c000000 + 8226500 8211 1c001372 00100513 addi x10, x0, 1 x10=00000001 + 8227500 8212 1c001374 9edff0ef jal x1, -1556 x1=1c001376 + 8245500 8230 1c000d60 1b2007b7 lui x15, 0x1b200000 x15=1b200000 + 8246500 8231 1c000d64 0407a703 lw x14, 64(x15) x14=1c000000 x15:1b200000 PA:1b200040 + 8250500 8235 1c000d66 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 8251500 8236 1c000d68 06f00793 addi x15, x0, 111 x15=0000006f + 8252500 8237 1c000d6c 40e585b3 sub x11, x11, x14 x11=00000172 x11:1c000172 x14:1c000000 + 8253500 8238 1c000d6e 40a585b3 sub x11, x11, x10 x11=0000016e x11:00000172 x10:00000004 + 8269500 8254 1c000d70 c14586b3 p.extract x13, x11, 0, 20 x13=00000000 x11:0000016e + 8270500 8255 1c000d74 c1f6a7b3 p.insert x15, x13, 0, 31 x15=0000006f x15:0000006f x13:00000000 + 8271500 8256 1c000d78 d21586b3 p.extract x13, x11, 9, 1 x13=000000b7 x11:0000016e + 8272500 8257 1c000d7c d356a7b3 p.insert x15, x13, 9, 21 x15=16e0006f x15:0000006f x13:000000b7 + 8289500 8274 1c000d80 c0b586b3 p.extract x13, x11, 0, 11 x13=00000000 x11:0000016e + 8290500 8275 1c000d84 c146a7b3 p.insert x15, x13, 0, 20 x15=16e0006f x15:16e0006f x13:00000000 + 8291500 8276 1c000d88 cec585b3 p.extract x11, x11, 7, 12 x11=00000000 x11:0000016e + 8292500 8277 1c000d8c cec5a7b3 p.insert x15, x11, 7, 12 x15=16e0006f x15:16e0006f x11:00000000 + 8309500 8294 1c000d90 00f56723 p.sw x15, x0(x10) x15:16e0006f x10:00000004 PA:1c000004 + 8327500 8312 1c000d94 00008067 jalr x0, x1, 0 x1:1c001376 + 8328500 8313 1c001376 1b204437 lui x8, 0x1b204000 x8=1b204000 + 8329500 8314 1c00137a 01440493 addi x9, x8, 20 x9=1b204014 x8:1b204000 + 8330500 8315 1c00137e 00200793 addi x15, x0, 2 x15=00000002 + 8347500 8332 1c001380 00f4a023 sw x15, 0(x9) x15:00000002 x9:1b204014 PA:1b204014 + 8348500 8333 1c001382 00f42423 sw x15, 8(x8) x15:00000002 x8:1b204000 PA:1b204008 + 8349500 8334 1c001384 1c0005b7 lui x11, 0x1c000000 x11=1c000000 + 8350500 8335 1c001388 13a58593 addi x11, x11, 314 x11=1c00013a x11:1c000000 + 8351500 8336 1c00138c 00400513 addi x10, x0, 4 x10=00000004 + 8352500 8337 1c00138e 9d3ff0ef jal x1, -1582 x1=1c001390 + 8369500 8354 1c000d60 1b2007b7 lui x15, 0x1b200000 x15=1b200000 + 8370500 8355 1c000d64 0407a703 lw x14, 64(x15) x14=1c000000 x15:1b200000 PA:1b200040 + 8374500 8359 1c000d66 00251513 slli x10, x10, 0x2 x10=00000010 x10:00000004 + 8375500 8360 1c000d68 06f00793 addi x15, x0, 111 x15=0000006f + 8376500 8361 1c000d6c 40e585b3 sub x11, x11, x14 x11=0000013a x11:1c00013a x14:1c000000 + 8377500 8362 1c000d6e 40a585b3 sub x11, x11, x10 x11=0000012a x11:0000013a x10:00000010 + 8378500 8363 1c000d70 c14586b3 p.extract x13, x11, 0, 20 x13=00000000 x11:0000012a + 8379500 8364 1c000d74 c1f6a7b3 p.insert x15, x13, 0, 31 x15=0000006f x15:0000006f x13:00000000 + 8380500 8365 1c000d78 d21586b3 p.extract x13, x11, 9, 1 x13=00000095 x11:0000012a + 8381500 8366 1c000d7c d356a7b3 p.insert x15, x13, 9, 21 x15=12a0006f x15:0000006f x13:00000095 + 8382500 8367 1c000d80 c0b586b3 p.extract x13, x11, 0, 11 x13=00000000 x11:0000012a + 8383500 8368 1c000d84 c146a7b3 p.insert x15, x13, 0, 20 x15=12a0006f x15:12a0006f x13:00000000 + 8384500 8369 1c000d88 cec585b3 p.extract x11, x11, 7, 12 x11=00000000 x11:0000012a + 8385500 8370 1c000d8c cec5a7b3 p.insert x15, x11, 7, 12 x15=12a0006f x15:12a0006f x11:00000000 + 8386500 8371 1c000d90 00f56723 p.sw x15, x0(x10) x15:12a0006f x10:00000010 PA:1c000010 + 8404500 8389 1c000d94 00008067 jalr x0, x1, 0 x1:1c001390 + 8405500 8390 1c001390 01000793 addi x15, x0, 16 x15=00000010 + 8406500 8391 1c001392 00f4a023 sw x15, 0(x9) x15:00000010 x9:1b204014 PA:1b204014 + 8407500 8392 1c001394 00f42423 sw x15, 8(x8) x15:00000010 x8:1b204000 PA:1b204008 + 8408500 8393 1c001396 01c12083 lw x1, 28(x2) x1=1c000e64 x2:10000940 PA:1000095c + 8409500 8394 1c001398 01812403 lw x8, 24(x2) x8=1c2ffff0 x2:10000940 PA:10000958 + 8410500 8395 1c00139a 01412483 lw x9, 20(x2) x9=10000180 x2:10000940 PA:10000954 + 8411500 8396 1c00139c 00000513 addi x10, x0, 0 x10=00000000 + 8412500 8397 1c00139e 02010113 addi x2, x2, 32 x2=10000960 x2:10000940 + 8428500 8413 1c0013a0 00008067 jalr x0, x1, 0 x1:1c000e64 + 8430500 8415 1c000e64 00051363 bne x10, x0, 6 x10:00000000 + 8431500 8416 1c000e66 00842403 lw x8, 8(x8) x8=00000000 x8:1c2ffff0 PA:1c2ffff8 + 8445500 8430 1c000e68 febff06f jal x0, -22 + 8446500 8431 1c000e52 00041663 bne x8, x0, 12 x8:00000000 + 8447500 8432 1c000e54 00000513 addi x10, x0, 0 x10=00000000 + 8448500 8433 1c000e56 00c12083 lw x1, 12(x2) x1=1c000caa x2:10000960 PA:1000096c + 8449500 8434 1c000e58 00812403 lw x8, 8(x2) x8=10000990 x2:10000960 PA:10000968 + 8450500 8435 1c000e5a 01010113 addi x2, x2, 16 x2=10000970 x2:10000960 + 8451500 8436 1c000e5c 00008067 jalr x0, x1, 0 x1:1c000caa + 8453500 8438 1c000caa 02051e63 bne x10, x0, 60 x10:00000000 + 8454500 8439 1c000cac 00000793 addi x15, x0, 0 x15=00000000 + 8471500 8456 1c000cb0 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:00000000 + 8472500 8457 1c000cb4 06078763 beq x15, x0, 110 x15:00000000 + 8491500 8476 1c000d22 00000593 addi x11, x0, 0 x11=00000000 + 8492500 8477 1c000d24 e7fff0ef jal x1, -386 x1=1c000d26 + 8510500 8495 1c000ba2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 8511500 8496 1c000ba4 02812423 sw x8, 40(x2) x8:10000990 x2:10000940 PA:10000968 + 8512500 8497 1c000ba6 02912223 sw x9, 36(x2) x9:10000180 x2:10000940 PA:10000964 + 8513500 8498 1c000ba8 03212023 sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960 + 8514500 8499 1c000baa 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 8515500 8500 1c000bac 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 8516500 8501 1c000bae 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 8532500 8517 1c000bb0 f1402773 csrrs x14, x0, 0xf14 x14=00000000 + 8533500 8518 1c000bb4 000019b7 lui x19, 0x1000 x19=00001000 + 8534500 8519 1c000bb6 02112623 sw x1, 44(x2) x1:1c000d26 x2:10000940 PA:1000096c + 8535500 8520 1c000bb8 01612823 sw x22, 16(x2) x22:00000000 x2:10000940 PA:10000950 + 8536500 8521 1c000bba ca571733 p.extractu x14, x14, 5, 5 x14=00000000 x14:00000000 + 8537500 8522 1c000bbe 00a00433 add x8, x0, x10 x8=00000000 x10:00000000 + 8554500 8539 1c000bc0 00250a13 addi x20, x10, 2 x20=00000002 x10:00000000 + 8555500 8540 1c000bc4 80098493 addi x9, x19, -2048 x9=00000800 x19:00001000 + 8556500 8541 1c000bc8 00800913 addi x18, x0, 8 x18=00000008 + 8557500 8542 1c000bcc 04a70f63 beq x14, x10, 94 x14:00000000 x10:00000000 + 8591500 8576 1c000c2a 00a005b3 add x11, x0, x10 x11=00000000 x10:00000000 + 8592500 8577 1c000c2c 00000693 addi x13, x0, 0 x13=00000000 + 8593500 8578 1c000c2e 00100513 addi x10, x0, 1 x10=00000001 + 8609500 8594 1c000c30 00000613 addi x12, x0, 0 x12=00000000 + 8610500 8595 1c000c32 770000ef jal x1, 1904 x1=1c000c36 + 8612500 8597 1c0013a2 fd010113 addi x2, x2, -48 x2=10000910 x2:10000940 + 8613500 8598 1c0013a4 02812423 sw x8, 40(x2) x8:00000000 x2:10000910 PA:10000938 + 8614500 8599 1c0013a6 00b00433 add x8, x0, x11 x8=00000000 x11:00000000 + 8615500 8600 1c0013a8 02112623 sw x1, 44(x2) x1:1c000c36 x2:10000910 PA:1000093c + 8616500 8601 1c0013aa 02912223 sw x9, 36(x2) x9:00000800 x2:10000910 PA:10000934 + 8617500 8602 1c0013ac 03212023 sw x18, 32(x2) x18:00000008 x2:10000910 PA:10000930 + 8618500 8603 1c0013ae 01312e23 sw x19, 28(x2) x19:00001000 x2:10000910 PA:1000092c + 8634500 8619 1c0013b0 01412c23 sw x20, 24(x2) x20:00000002 x2:10000910 PA:10000928 + 8635500 8620 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000910 PA:10000924 + 8636500 8621 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 8640500 8625 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 8641500 8626 1c0013ba 03458a33 mul x20, x11, x20 x20=00000000 x11:00000000 x20:00000018 + 8658500 8643 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 8659500 8644 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 8673500 8658 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 8674500 8659 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff50 x15:1c2fff50 x20:00000000 + 8675500 8660 1c0013ca 0007a703 lw x14, 0(x15) x14=00000000 x15:1c2fff50 PA:1c2fff50 + 8690500 8675 1c0013cc 02050363 beq x10, x0, 38 x10:00000001 + 8691500 8676 1c0013ce 00170713 addi x14, x14, 1 x14=00000001 x14:00000000 + 8694500 8679 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000001 x15:1c2fff50 PA:1c2fff50 + 8712500 8697 1c0013d2 0007a483 lw x9, 0(x15) x9=00000001 x15:1c2fff50 PA:1c2fff50 + 8727500 8712 1c0013d4 02049163 bne x9, x0, 34 x9:00000001 + 8746500 8731 1c0013f6 fe14b3e3 p.bneimm x9, -26 x9:00000001 + 8747500 8732 1c0013fa 00800993 addi x19, x0, 8 x19=00000008 + 8748500 8733 1c0013fe 04040f63 beq x8, x0, 94 x8:00000000 + 8782500 8767 1c00145c 00000513 addi x10, x0, 0 x10=00000000 + 8783500 8768 1c00145e e79ff0ef jal x1, -392 x1=1c001460 + 8816500 8801 1c0012d6 ff010113 addi x2, x2, -16 x2=10000900 x2:10000910 + 8817500 8802 1c0012d8 00812423 sw x8, 8(x2) x8:00000000 x2:10000900 PA:10000908 + 8818500 8803 1c0012da 00912223 sw x9, 4(x2) x9:00000001 x2:10000900 PA:10000904 + 8819500 8804 1c0012dc 04050413 addi x8, x10, 64 x8=00000040 x10:00000000 + 8836500 8821 1c0012e0 00a004b3 add x9, x0, x10 x9=00000000 x10:00000000 + 8837500 8822 1c0012e2 1b000537 lui x10, 0x1b000000 x10=1b000000 + 8838500 8823 1c0012e6 00850513 addi x10, x10, 8 x10=1b000008 x10:1b000000 + 8839500 8824 1c0012ea 01641413 slli x8, x8, 0x16 x8=10000000 x8:00000040 + 8840500 8825 1c0012ec e6c53533 p.bclr x10, x10, 19, 12 x10=00000008 x10:1b000008 + 8857500 8842 1c0012f0 00850533 add x10, x10, x8 x10=10000008 x10:00000008 x8:10000000 + 8858500 8843 1c0012f2 04000613 addi x12, x0, 64 x12=00000040 + 8859500 8844 1c0012f6 00000593 addi x11, x0, 0 x11=00000000 + 8860500 8845 1c0012f8 00112623 sw x1, 12(x2) x1:1c001460 x2:10000900 PA:1000090c + 8861500 8846 1c0012fa 506000ef jal x1, 1286 x1=1c0012fc + 8863500 8848 1c001800 00a60633 add x12, x12, x10 x12=10000048 x12:00000040 x10:10000008 + 8864500 8849 1c001802 00a007b3 add x15, x0, x10 x15=10000008 x10:10000008 + 8865500 8850 1c001804 00c79363 bne x15, x12, 6 x15:10000008 x12:10000048 + 8868500 8853 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000009 x11:00000000 x15:10000008 PA:10000008 + 8869500 8854 1c00180e ff7ff06f jal x0, -10 + 8871500 8856 1c001804 00c79363 bne x15, x12, 6 x15:10000009 x12:10000048 + 8874500 8859 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000000a x11:00000000 x15:10000009 PA:10000009 + 8875500 8860 1c00180e ff7ff06f jal x0, -10 + 8877500 8862 1c001804 00c79363 bne x15, x12, 6 x15:1000000a x12:10000048 + 8880500 8865 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000000b x11:00000000 x15:1000000a PA:1000000a + 8881500 8866 1c00180e ff7ff06f jal x0, -10 + 8883500 8868 1c001804 00c79363 bne x15, x12, 6 x15:1000000b x12:10000048 + 8886500 8871 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000000c x11:00000000 x15:1000000b PA:1000000b + 8887500 8872 1c00180e ff7ff06f jal x0, -10 + 8889500 8874 1c001804 00c79363 bne x15, x12, 6 x15:1000000c x12:10000048 + 8892500 8877 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000000d x11:00000000 x15:1000000c PA:1000000c + 8893500 8878 1c00180e ff7ff06f jal x0, -10 + 8895500 8880 1c001804 00c79363 bne x15, x12, 6 x15:1000000d x12:10000048 + 8898500 8883 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000000e x11:00000000 x15:1000000d PA:1000000d + 8899500 8884 1c00180e ff7ff06f jal x0, -10 + 8901500 8886 1c001804 00c79363 bne x15, x12, 6 x15:1000000e x12:10000048 + 8904500 8889 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000000f x11:00000000 x15:1000000e PA:1000000e + 8905500 8890 1c00180e ff7ff06f jal x0, -10 + 8907500 8892 1c001804 00c79363 bne x15, x12, 6 x15:1000000f x12:10000048 + 8910500 8895 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000010 x11:00000000 x15:1000000f PA:1000000f + 8911500 8896 1c00180e ff7ff06f jal x0, -10 + 8913500 8898 1c001804 00c79363 bne x15, x12, 6 x15:10000010 x12:10000048 + 8916500 8901 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000011 x11:00000000 x15:10000010 PA:10000010 + 8917500 8902 1c00180e ff7ff06f jal x0, -10 + 8919500 8904 1c001804 00c79363 bne x15, x12, 6 x15:10000011 x12:10000048 + 8922500 8907 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000012 x11:00000000 x15:10000011 PA:10000011 + 8923500 8908 1c00180e ff7ff06f jal x0, -10 + 8925500 8910 1c001804 00c79363 bne x15, x12, 6 x15:10000012 x12:10000048 + 8928500 8913 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000013 x11:00000000 x15:10000012 PA:10000012 + 8929500 8914 1c00180e ff7ff06f jal x0, -10 + 8931500 8916 1c001804 00c79363 bne x15, x12, 6 x15:10000013 x12:10000048 + 8934500 8919 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000014 x11:00000000 x15:10000013 PA:10000013 + 8935500 8920 1c00180e ff7ff06f jal x0, -10 + 8937500 8922 1c001804 00c79363 bne x15, x12, 6 x15:10000014 x12:10000048 + 8940500 8925 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000015 x11:00000000 x15:10000014 PA:10000014 + 8941500 8926 1c00180e ff7ff06f jal x0, -10 + 8943500 8928 1c001804 00c79363 bne x15, x12, 6 x15:10000015 x12:10000048 + 8946500 8931 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000016 x11:00000000 x15:10000015 PA:10000015 + 8947500 8932 1c00180e ff7ff06f jal x0, -10 + 8949500 8934 1c001804 00c79363 bne x15, x12, 6 x15:10000016 x12:10000048 + 8952500 8937 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000017 x11:00000000 x15:10000016 PA:10000016 + 8953500 8938 1c00180e ff7ff06f jal x0, -10 + 8955500 8940 1c001804 00c79363 bne x15, x12, 6 x15:10000017 x12:10000048 + 8958500 8943 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000018 x11:00000000 x15:10000017 PA:10000017 + 8959500 8944 1c00180e ff7ff06f jal x0, -10 + 8961500 8946 1c001804 00c79363 bne x15, x12, 6 x15:10000018 x12:10000048 + 8964500 8949 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000019 x11:00000000 x15:10000018 PA:10000018 + 8965500 8950 1c00180e ff7ff06f jal x0, -10 + 8967500 8952 1c001804 00c79363 bne x15, x12, 6 x15:10000019 x12:10000048 + 8970500 8955 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000001a x11:00000000 x15:10000019 PA:10000019 + 8971500 8956 1c00180e ff7ff06f jal x0, -10 + 8973500 8958 1c001804 00c79363 bne x15, x12, 6 x15:1000001a x12:10000048 + 8976500 8961 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000001b x11:00000000 x15:1000001a PA:1000001a + 8977500 8962 1c00180e ff7ff06f jal x0, -10 + 8979500 8964 1c001804 00c79363 bne x15, x12, 6 x15:1000001b x12:10000048 + 8982500 8967 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000001c x11:00000000 x15:1000001b PA:1000001b + 8983500 8968 1c00180e ff7ff06f jal x0, -10 + 8985500 8970 1c001804 00c79363 bne x15, x12, 6 x15:1000001c x12:10000048 + 8988500 8973 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000001d x11:00000000 x15:1000001c PA:1000001c + 8989500 8974 1c00180e ff7ff06f jal x0, -10 + 8991500 8976 1c001804 00c79363 bne x15, x12, 6 x15:1000001d x12:10000048 + 8994500 8979 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000001e x11:00000000 x15:1000001d PA:1000001d + 8995500 8980 1c00180e ff7ff06f jal x0, -10 + 8997500 8982 1c001804 00c79363 bne x15, x12, 6 x15:1000001e x12:10000048 + 9000500 8985 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000001f x11:00000000 x15:1000001e PA:1000001e + 9001500 8986 1c00180e ff7ff06f jal x0, -10 + 9003500 8988 1c001804 00c79363 bne x15, x12, 6 x15:1000001f x12:10000048 + 9006500 8991 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000020 x11:00000000 x15:1000001f PA:1000001f + 9007500 8992 1c00180e ff7ff06f jal x0, -10 + 9009500 8994 1c001804 00c79363 bne x15, x12, 6 x15:10000020 x12:10000048 + 9012500 8997 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000021 x11:00000000 x15:10000020 PA:10000020 + 9013500 8998 1c00180e ff7ff06f jal x0, -10 + 9015500 9000 1c001804 00c79363 bne x15, x12, 6 x15:10000021 x12:10000048 + 9018500 9003 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000022 x11:00000000 x15:10000021 PA:10000021 + 9019500 9004 1c00180e ff7ff06f jal x0, -10 + 9021500 9006 1c001804 00c79363 bne x15, x12, 6 x15:10000022 x12:10000048 + 9024500 9009 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000023 x11:00000000 x15:10000022 PA:10000022 + 9025500 9010 1c00180e ff7ff06f jal x0, -10 + 9027500 9012 1c001804 00c79363 bne x15, x12, 6 x15:10000023 x12:10000048 + 9030500 9015 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000024 x11:00000000 x15:10000023 PA:10000023 + 9031500 9016 1c00180e ff7ff06f jal x0, -10 + 9033500 9018 1c001804 00c79363 bne x15, x12, 6 x15:10000024 x12:10000048 + 9036500 9021 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000025 x11:00000000 x15:10000024 PA:10000024 + 9037500 9022 1c00180e ff7ff06f jal x0, -10 + 9039500 9024 1c001804 00c79363 bne x15, x12, 6 x15:10000025 x12:10000048 + 9042500 9027 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000026 x11:00000000 x15:10000025 PA:10000025 + 9043500 9028 1c00180e ff7ff06f jal x0, -10 + 9045500 9030 1c001804 00c79363 bne x15, x12, 6 x15:10000026 x12:10000048 + 9048500 9033 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000027 x11:00000000 x15:10000026 PA:10000026 + 9049500 9034 1c00180e ff7ff06f jal x0, -10 + 9051500 9036 1c001804 00c79363 bne x15, x12, 6 x15:10000027 x12:10000048 + 9054500 9039 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000028 x11:00000000 x15:10000027 PA:10000027 + 9055500 9040 1c00180e ff7ff06f jal x0, -10 + 9057500 9042 1c001804 00c79363 bne x15, x12, 6 x15:10000028 x12:10000048 + 9060500 9045 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000029 x11:00000000 x15:10000028 PA:10000028 + 9061500 9046 1c00180e ff7ff06f jal x0, -10 + 9063500 9048 1c001804 00c79363 bne x15, x12, 6 x15:10000029 x12:10000048 + 9066500 9051 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000002a x11:00000000 x15:10000029 PA:10000029 + 9067500 9052 1c00180e ff7ff06f jal x0, -10 + 9069500 9054 1c001804 00c79363 bne x15, x12, 6 x15:1000002a x12:10000048 + 9072500 9057 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000002b x11:00000000 x15:1000002a PA:1000002a + 9073500 9058 1c00180e ff7ff06f jal x0, -10 + 9075500 9060 1c001804 00c79363 bne x15, x12, 6 x15:1000002b x12:10000048 + 9078500 9063 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000002c x11:00000000 x15:1000002b PA:1000002b + 9079500 9064 1c00180e ff7ff06f jal x0, -10 + 9081500 9066 1c001804 00c79363 bne x15, x12, 6 x15:1000002c x12:10000048 + 9084500 9069 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000002d x11:00000000 x15:1000002c PA:1000002c + 9085500 9070 1c00180e ff7ff06f jal x0, -10 + 9087500 9072 1c001804 00c79363 bne x15, x12, 6 x15:1000002d x12:10000048 + 9090500 9075 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000002e x11:00000000 x15:1000002d PA:1000002d + 9091500 9076 1c00180e ff7ff06f jal x0, -10 + 9093500 9078 1c001804 00c79363 bne x15, x12, 6 x15:1000002e x12:10000048 + 9096500 9081 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000002f x11:00000000 x15:1000002e PA:1000002e + 9097500 9082 1c00180e ff7ff06f jal x0, -10 + 9099500 9084 1c001804 00c79363 bne x15, x12, 6 x15:1000002f x12:10000048 + 9102500 9087 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000030 x11:00000000 x15:1000002f PA:1000002f + 9103500 9088 1c00180e ff7ff06f jal x0, -10 + 9105500 9090 1c001804 00c79363 bne x15, x12, 6 x15:10000030 x12:10000048 + 9108500 9093 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000031 x11:00000000 x15:10000030 PA:10000030 + 9109500 9094 1c00180e ff7ff06f jal x0, -10 + 9111500 9096 1c001804 00c79363 bne x15, x12, 6 x15:10000031 x12:10000048 + 9114500 9099 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000032 x11:00000000 x15:10000031 PA:10000031 + 9115500 9100 1c00180e ff7ff06f jal x0, -10 + 9117500 9102 1c001804 00c79363 bne x15, x12, 6 x15:10000032 x12:10000048 + 9120500 9105 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000033 x11:00000000 x15:10000032 PA:10000032 + 9121500 9106 1c00180e ff7ff06f jal x0, -10 + 9123500 9108 1c001804 00c79363 bne x15, x12, 6 x15:10000033 x12:10000048 + 9126500 9111 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000034 x11:00000000 x15:10000033 PA:10000033 + 9127500 9112 1c00180e ff7ff06f jal x0, -10 + 9129500 9114 1c001804 00c79363 bne x15, x12, 6 x15:10000034 x12:10000048 + 9132500 9117 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000035 x11:00000000 x15:10000034 PA:10000034 + 9133500 9118 1c00180e ff7ff06f jal x0, -10 + 9135500 9120 1c001804 00c79363 bne x15, x12, 6 x15:10000035 x12:10000048 + 9138500 9123 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000036 x11:00000000 x15:10000035 PA:10000035 + 9139500 9124 1c00180e ff7ff06f jal x0, -10 + 9141500 9126 1c001804 00c79363 bne x15, x12, 6 x15:10000036 x12:10000048 + 9144500 9129 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000037 x11:00000000 x15:10000036 PA:10000036 + 9145500 9130 1c00180e ff7ff06f jal x0, -10 + 9147500 9132 1c001804 00c79363 bne x15, x12, 6 x15:10000037 x12:10000048 + 9150500 9135 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000038 x11:00000000 x15:10000037 PA:10000037 + 9151500 9136 1c00180e ff7ff06f jal x0, -10 + 9153500 9138 1c001804 00c79363 bne x15, x12, 6 x15:10000038 x12:10000048 + 9156500 9141 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000039 x11:00000000 x15:10000038 PA:10000038 + 9157500 9142 1c00180e ff7ff06f jal x0, -10 + 9159500 9144 1c001804 00c79363 bne x15, x12, 6 x15:10000039 x12:10000048 + 9162500 9147 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000003a x11:00000000 x15:10000039 PA:10000039 + 9163500 9148 1c00180e ff7ff06f jal x0, -10 + 9165500 9150 1c001804 00c79363 bne x15, x12, 6 x15:1000003a x12:10000048 + 9168500 9153 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000003b x11:00000000 x15:1000003a PA:1000003a + 9169500 9154 1c00180e ff7ff06f jal x0, -10 + 9171500 9156 1c001804 00c79363 bne x15, x12, 6 x15:1000003b x12:10000048 + 9174500 9159 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000003c x11:00000000 x15:1000003b PA:1000003b + 9175500 9160 1c00180e ff7ff06f jal x0, -10 + 9177500 9162 1c001804 00c79363 bne x15, x12, 6 x15:1000003c x12:10000048 + 9180500 9165 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000003d x11:00000000 x15:1000003c PA:1000003c + 9181500 9166 1c00180e ff7ff06f jal x0, -10 + 9183500 9168 1c001804 00c79363 bne x15, x12, 6 x15:1000003d x12:10000048 + 9186500 9171 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000003e x11:00000000 x15:1000003d PA:1000003d + 9187500 9172 1c00180e ff7ff06f jal x0, -10 + 9189500 9174 1c001804 00c79363 bne x15, x12, 6 x15:1000003e x12:10000048 + 9192500 9177 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1000003f x11:00000000 x15:1000003e PA:1000003e + 9193500 9178 1c00180e ff7ff06f jal x0, -10 + 9195500 9180 1c001804 00c79363 bne x15, x12, 6 x15:1000003f x12:10000048 + 9198500 9183 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000040 x11:00000000 x15:1000003f PA:1000003f + 9199500 9184 1c00180e ff7ff06f jal x0, -10 + 9201500 9186 1c001804 00c79363 bne x15, x12, 6 x15:10000040 x12:10000048 + 9204500 9189 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000041 x11:00000000 x15:10000040 PA:10000040 + 9205500 9190 1c00180e ff7ff06f jal x0, -10 + 9207500 9192 1c001804 00c79363 bne x15, x12, 6 x15:10000041 x12:10000048 + 9210500 9195 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000042 x11:00000000 x15:10000041 PA:10000041 + 9211500 9196 1c00180e ff7ff06f jal x0, -10 + 9213500 9198 1c001804 00c79363 bne x15, x12, 6 x15:10000042 x12:10000048 + 9216500 9201 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000043 x11:00000000 x15:10000042 PA:10000042 + 9217500 9202 1c00180e ff7ff06f jal x0, -10 + 9219500 9204 1c001804 00c79363 bne x15, x12, 6 x15:10000043 x12:10000048 + 9222500 9207 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000044 x11:00000000 x15:10000043 PA:10000043 + 9223500 9208 1c00180e ff7ff06f jal x0, -10 + 9225500 9210 1c001804 00c79363 bne x15, x12, 6 x15:10000044 x12:10000048 + 9228500 9213 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000045 x11:00000000 x15:10000044 PA:10000044 + 9229500 9214 1c00180e ff7ff06f jal x0, -10 + 9231500 9216 1c001804 00c79363 bne x15, x12, 6 x15:10000045 x12:10000048 + 9234500 9219 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000046 x11:00000000 x15:10000045 PA:10000045 + 9235500 9220 1c00180e ff7ff06f jal x0, -10 + 9237500 9222 1c001804 00c79363 bne x15, x12, 6 x15:10000046 x12:10000048 + 9240500 9225 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000047 x11:00000000 x15:10000046 PA:10000046 + 9241500 9226 1c00180e ff7ff06f jal x0, -10 + 9243500 9228 1c001804 00c79363 bne x15, x12, 6 x15:10000047 x12:10000048 + 9246500 9231 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10000048 x11:00000000 x15:10000047 PA:10000047 + 9247500 9232 1c00180e ff7ff06f jal x0, -10 + 9249500 9234 1c001804 00c79363 bne x15, x12, 6 x15:10000048 x12:10000048 + 9250500 9235 1c001808 00008067 jalr x0, x1, 0 x1:1c0012fc + 9252500 9237 1c0012fc 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 9269500 9254 1c001300 6a87a783 lw x15, 1704(x15) x15=1c2fff50 x15:1c002000 PA:1c0026a8 + 9283500 9268 1c001304 01800713 addi x14, x0, 24 x14=00000018 + 9284500 9269 1c001306 00c12083 lw x1, 12(x2) x1=1c001460 x2:10000900 PA:1000090c + 9285500 9270 1c001308 42e487b3 p.mac x15, x9, x14 x15=1c2fff50 x15:1c2fff50 x9:00000000 x14:00000018 + 9286500 9271 1c00130c 00201737 lui x14, 0x201000 x14=00201000 + 9303500 9288 1c001310 e0470713 addi x14, x14, -508 x14=00200e04 x14:00201000 + 9304500 9289 1c001314 00e40433 add x8, x8, x14 x8=10200e04 x8:10000000 x14:00200e04 + 9305500 9290 1c001316 00412483 lw x9, 4(x2) x9=00000001 x2:10000900 PA:10000904 + 9306500 9291 1c001318 0087aa23 sw x8, 20(x15) x8:10200e04 x15:1c2fff50 PA:1c2fff64 + 9324500 9309 1c00131a 00812403 lw x8, 8(x2) x8=00000000 x2:10000900 PA:10000908 + 9325500 9310 1c00131c 0007a623 sw x0, 12(x15) x15:1c2fff50 PA:1c2fff5c + 9343500 9328 1c001320 01010113 addi x2, x2, 16 x2=10000910 x2:10000900 + 9344500 9329 1c001322 00008067 jalr x0, x1, 0 x1:1c001460 + 9346500 9331 1c001460 102017b7 lui x15, 0x10201000 x15=10201000 + 9347500 9332 1c001464 fff00713 addi x14, x0, -1 x14=ffffffff + 9348500 9333 1c001466 40e7a023 sw x14, 1024(x15) x14:ffffffff x15:10201000 PA:10201400 + 9353500 9338 1c00146a 1c0007b7 lui x15, 0x1c000000 x15=1c000000 + 9366500 9351 1c00146e 08078793 addi x15, x15, 128 x15=1c000080 x15:1c000000 + 9367500 9352 1c001472 06c80737 lui x14, 0x6c80000 x14=06c80000 + 9368500 9353 1c001476 ce07b7b3 p.bclr x15, x15, 7, 0 x15=1c000000 x15:1c000080 + 9369500 9354 1c00147a 01070713 addi x14, x14, 16 x14=06c80010 x14:06c80000 + 9370500 9355 1c00147c 0134c763 blt x9, x19, 14 x9:00000001 x19:00000008 + 9388500 9373 1c00148a 00e486b3 add x13, x9, x14 x13=06c80011 x9:00000001 x14:06c80010 + 9389500 9374 1c00148e 00269693 slli x13, x13, 0x2 x13=1b200044 x13:06c80011 + 9406500 9391 1c001490 00f6a023 sw x15, 0(x13) x15:1c000000 x13:1b200044 PA:1b200044 + 9410500 9395 1c001492 00148493 addi x9, x9, 1 x9=00000002 x9:00000001 + 9411500 9396 1c001494 fe9ff06f jal x0, -24 + 9413500 9398 1c00147c 0134c763 blt x9, x19, 14 x9:00000002 x19:00000008 + 9416500 9401 1c00148a 00e486b3 add x13, x9, x14 x13=06c80012 x9:00000002 x14:06c80010 + 9417500 9402 1c00148e 00269693 slli x13, x13, 0x2 x13=1b200048 x13:06c80012 + 9418500 9403 1c001490 00f6a023 sw x15, 0(x13) x15:1c000000 x13:1b200048 PA:1b200048 + 9422500 9407 1c001492 00148493 addi x9, x9, 1 x9=00000003 x9:00000002 + 9423500 9408 1c001494 fe9ff06f jal x0, -24 + 9425500 9410 1c00147c 0134c763 blt x9, x19, 14 x9:00000003 x19:00000008 + 9428500 9413 1c00148a 00e486b3 add x13, x9, x14 x13=06c80013 x9:00000003 x14:06c80010 + 9429500 9414 1c00148e 00269693 slli x13, x13, 0x2 x13=1b20004c x13:06c80013 + 9430500 9415 1c001490 00f6a023 sw x15, 0(x13) x15:1c000000 x13:1b20004c PA:1b20004c + 9434500 9419 1c001492 00148493 addi x9, x9, 1 x9=00000004 x9:00000003 + 9435500 9420 1c001494 fe9ff06f jal x0, -24 + 9437500 9422 1c00147c 0134c763 blt x9, x19, 14 x9:00000004 x19:00000008 + 9440500 9425 1c00148a 00e486b3 add x13, x9, x14 x13=06c80014 x9:00000004 x14:06c80010 + 9441500 9426 1c00148e 00269693 slli x13, x13, 0x2 x13=1b200050 x13:06c80014 + 9442500 9427 1c001490 00f6a023 sw x15, 0(x13) x15:1c000000 x13:1b200050 PA:1b200050 + 9446500 9431 1c001492 00148493 addi x9, x9, 1 x9=00000005 x9:00000004 + 9447500 9432 1c001494 fe9ff06f jal x0, -24 + 9449500 9434 1c00147c 0134c763 blt x9, x19, 14 x9:00000005 x19:00000008 + 9452500 9437 1c00148a 00e486b3 add x13, x9, x14 x13=06c80015 x9:00000005 x14:06c80010 + 9453500 9438 1c00148e 00269693 slli x13, x13, 0x2 x13=1b200054 x13:06c80015 + 9454500 9439 1c001490 00f6a023 sw x15, 0(x13) x15:1c000000 x13:1b200054 PA:1b200054 + 9458500 9443 1c001492 00148493 addi x9, x9, 1 x9=00000006 x9:00000005 + 9459500 9444 1c001494 fe9ff06f jal x0, -24 + 9461500 9446 1c00147c 0134c763 blt x9, x19, 14 x9:00000006 x19:00000008 + 9464500 9449 1c00148a 00e486b3 add x13, x9, x14 x13=06c80016 x9:00000006 x14:06c80010 + 9465500 9450 1c00148e 00269693 slli x13, x13, 0x2 x13=1b200058 x13:06c80016 + 9466500 9451 1c001490 00f6a023 sw x15, 0(x13) x15:1c000000 x13:1b200058 PA:1b200058 + 9470500 9455 1c001492 00148493 addi x9, x9, 1 x9=00000007 x9:00000006 + 9471500 9456 1c001494 fe9ff06f jal x0, -24 + 9473500 9458 1c00147c 0134c763 blt x9, x19, 14 x9:00000007 x19:00000008 + 9476500 9461 1c00148a 00e486b3 add x13, x9, x14 x13=06c80017 x9:00000007 x14:06c80010 + 9477500 9462 1c00148e 00269693 slli x13, x13, 0x2 x13=1b20005c x13:06c80017 + 9478500 9463 1c001490 00f6a023 sw x15, 0(x13) x15:1c000000 x13:1b20005c PA:1b20005c + 9482500 9467 1c001492 00148493 addi x9, x9, 1 x9=00000008 x9:00000007 + 9483500 9468 1c001494 fe9ff06f jal x0, -24 + 9485500 9470 1c00147c 0134c763 blt x9, x19, 14 x9:00000008 x19:00000008 + 9486500 9471 1c001480 102007b7 lui x15, 0x10200000 x15=10200000 + 9487500 9472 1c001484 fff00713 addi x14, x0, -1 x14=ffffffff + 9488500 9473 1c001486 00e7a423 sw x14, 8(x15) x14:ffffffff x15:10200000 PA:10200008 + 9492500 9477 1c001488 f55ff06f jal x0, -172 + 9493500 9478 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 9508500 9493 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000c36 x2:10000910 PA:1000093c + 9509500 9494 1c0013e2 02812403 lw x8, 40(x2) x8=00000000 x2:10000910 PA:10000938 + 9510500 9495 1c0013e4 02412483 lw x9, 36(x2) x9=00000800 x2:10000910 PA:10000934 + 9511500 9496 1c0013e6 02012903 lw x18, 32(x2) x18=00000008 x2:10000910 PA:10000930 + 9512500 9497 1c0013e8 01c12983 lw x19, 28(x2) x19=00001000 x2:10000910 PA:1000092c + 9513500 9498 1c0013ea 01812a03 lw x20, 24(x2) x20=00000002 x2:10000910 PA:10000928 + 9514500 9499 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000910 PA:10000924 + 9515500 9500 1c0013ee 03010113 addi x2, x2, 48 x2=10000940 x2:10000910 + 9516500 9501 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000c36 + 9518500 9503 1c000c36 fff90593 addi x11, x18, -1 x11=00000007 x18:00000008 + 9519500 9504 1c000c3a 029585b3 mul x11, x11, x9 x11=00003800 x11:00000007 x9:00000800 + 9520500 9505 1c000c3e 01400533 add x10, x0, x20 x10=00000002 x20:00000002 + 9537500 9522 1c000c40 590000ef jal x1, 1424 x1=1c000c42 + 9539500 9524 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 9540500 9525 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000002 + 9541500 9526 1c0011d6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 9542500 9527 1c0011da 69c7a783 lw x15, 1692(x15) x15=10000990 x15:1c002000 PA:1c00269c + 9556500 9541 1c0011de ffe50513 addi x10, x10, -2 x10=00000000 x10:00000002 + 9557500 9542 1c0011e0 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 9558500 9543 1c0011e2 00f50533 add x10, x10, x15 x10=10000990 x10:00000000 x15:10000990 + 9559500 9544 1c0011e4 f6fff06f jal x0, -146 + 9561500 9546 1c001152 00052783 lw x15, 0(x10) x15=100009a0 x10:10000990 PA:10000990 + 9562500 9547 1c001154 00758593 addi x11, x11, 7 x11=00003807 x11:00003800 + 9563500 9548 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00003800 x11:00003807 + 9564500 9549 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 9565500 9550 1c00115c 00078963 beq x15, x0, 18 x15:100009a0 + 9566500 9551 1c00115e 0007a703 lw x14, 0(x15) x14=000ff5f0 x15:100009a0 PA:100009a0 + 9568500 9553 1c001160 00b74963 blt x14, x11, 18 x14:000ff5f0 x11:00003800 + 9569500 9554 1c001164 00b71c63 bne x14, x11, 24 x14:000ff5f0 x11:00003800 + 9572500 9557 1c00117c 40b70733 sub x14, x14, x11 x14=000fbdf0 x14:000ff5f0 x11:00003800 + 9573500 9558 1c00117e 00e7a023 sw x14, 0(x15) x14:000fbdf0 x15:100009a0 PA:100009a0 + 9574500 9559 1c001180 00e787b3 add x15, x15, x14 x15=100fc790 x15:100009a0 x14:000fbdf0 + 9575500 9560 1c001182 fedff06f jal x0, -20 + 9577500 9562 1c00116e 00f00533 add x10, x0, x15 x10=100fc790 x15:100fc790 + 9578500 9563 1c001170 00008067 jalr x0, x1, 0 x1:1c000c42 + 9580500 9565 1c000c42 fa0504e3 beq x10, x0, -88 x10:100fc790 + 9581500 9566 1c000c44 00100793 addi x15, x0, 1 x15=00000001 + 9582500 9567 1c000c46 012797b3 sll x15, x15, x18 x15=00000100 x15:00000001 x18:00000008 + 9583500 9568 1c000c4a fff78793 addi x15, x15, -1 x15=000000ff x15:00000100 + 9584500 9569 1c000c4c 1b204737 lui x14, 0x1b204000 x14=1b204000 + 9601500 9586 1c000c50 08f72223 sw x15, 132(x14) x15:000000ff x14:1b204000 PA:1b204084 + 9602500 9587 1c000c54 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 9603500 9588 1c000c58 22c78793 addi x15, x15, 556 x15=1c00222c x15:1c002000 + 9604500 9589 1c000c5c c007c7b3 p.bset x15, x15, 0, 0 x15=1c00222d x15:1c00222c + 9621500 9606 1c000c60 08f72023 sw x15, 128(x14) x15:1c00222d x14:1b204000 PA:1b204080 + 9622500 9607 1c000c64 08972023 sw x9, 128(x14) x9:00000800 x14:1b204000 PA:1b204080 + 9623500 9608 1c000c68 08a72023 sw x10, 128(x14) x10:100fc790 x14:1b204000 PA:1b204080 + 9624500 9609 1c000c6c 00000513 addi x10, x0, 0 x10=00000000 + 9625500 9610 1c000c6e ea5ff0ef jal x1, -348 x1=1c000c70 + 9661500 9646 1c000b12 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 9662500 9647 1c000b16 00070737 lui x14, 0x70000 x14=00070000 + 9663500 9648 1c000b1a 00e7a423 sw x14, 8(x15) x14:00070000 x15:1b204000 PA:1b204008 + 9664500 9649 1c000b1c 00000713 addi x14, x0, 0 x14=00000000 + 9682500 9667 1c000b20 fc173733 p.bclr x14, x14, 30, 1 x14=00000000 x14:00000000 + 9683500 9668 1c000b24 04070e63 beq x14, x0, 92 x14:00000000 + 9703500 9688 1c000b80 00800693 addi x13, x0, 8 x13=00000008 + 9704500 9689 1c000b84 00100713 addi x14, x0, 1 x14=00000001 + 9705500 9690 1c000b86 00d71733 sll x14, x14, x13 x14=00000100 x14:00000001 x13:00000008 + 9706500 9691 1c000b8a fff70713 addi x14, x14, -1 x14=000000ff x14:00000100 + 9707500 9692 1c000b8c 1b2046b7 lui x13, 0x1b204000 x13=1b204000 + 9724500 9709 1c000b90 08e6a223 sw x14, 132(x13) x14:000000ff x13:1b204000 PA:1b204084 + 9725500 9710 1c000b94 20078693 addi x13, x15, 512 x13=1b204200 x15:1b204000 + 9726500 9711 1c000b98 00e6a023 sw x14, 0(x13) x14:000000ff x13:1b204200 PA:1b204200 + 9727500 9712 1c000b9a 20c78793 addi x15, x15, 524 x15=1b20420c x15:1b204000 + 9728500 9713 1c000b9e 00e7a023 sw x14, 0(x15) x14:000000ff x15:1b20420c PA:1b20420c + 9729500 9714 1c000ba0 00008067 jalr x0, x1, 0 x1:1c000c70 + 9731500 9716 1c000c70 00000513 addi x10, x0, 0 x10=00000000 + 9732500 9717 1c000c72 f7bff06f jal x0, -134 + 9750500 9735 1c000bec 02c12083 lw x1, 44(x2) x1=1c000d26 x2:10000940 PA:1000096c + 9751500 9736 1c000bee 02812403 lw x8, 40(x2) x8=10000990 x2:10000940 PA:10000968 + 9767500 9752 1c000bf0 02412483 lw x9, 36(x2) x9=10000180 x2:10000940 PA:10000964 + 9768500 9753 1c000bf2 02012903 lw x18, 32(x2) x18=00000000 x2:10000940 PA:10000960 + 9769500 9754 1c000bf4 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 9770500 9755 1c000bf6 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 9771500 9756 1c000bf8 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 9772500 9757 1c000bfa 01012b03 lw x22, 16(x2) x22=00000000 x2:10000940 PA:10000950 + 9773500 9758 1c000bfc 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 9774500 9759 1c000bfe 00008067 jalr x0, x1, 0 x1:1c000d26 + 9791500 9776 1c000d26 fc0510e3 bne x10, x0, -64 x10:00000000 + 9792500 9777 1c000d28 fe040113 addi x2, x8, -32 x2=10000970 x8:10000990 + 9793500 9778 1c000d2c 01c12083 lw x1, 28(x2) x1=1c0000d8 x2:10000970 PA:1000098c + 9794500 9779 1c000d2e 01812403 lw x8, 24(x2) x8=00000000 x2:10000970 PA:10000988 + 9810500 9795 1c000d30 01412483 lw x9, 20(x2) x9=00000000 x2:10000970 PA:10000984 + 9811500 9796 1c000d32 01012903 lw x18, 16(x2) x18=00000000 x2:10000970 PA:10000980 + 9812500 9797 1c000d34 00c12983 lw x19, 12(x2) x19=00000000 x2:10000970 PA:1000097c + 9813500 9798 1c000d36 00812a03 lw x20, 8(x2) x20=00000000 x2:10000970 PA:10000978 + 9814500 9799 1c000d38 02010113 addi x2, x2, 32 x2=10000990 x2:10000970 + 9815500 9800 1c000d3a 00008067 jalr x0, x1, 0 x1:1c0000d8 + 9833500 9818 1c0000d8 00000513 addi x10, x0, 0 x10=00000000 + 9834500 9819 1c0000dc 00000593 addi x11, x0, 0 x11=00000000 + 9851500 9836 1c0000e0 00001397 auipc x7, 0x1000 x7=1c0010e0 + 9852500 9837 1c0000e4 96c38393 addi x7, x7, -1684 x7=1c000a4c x7:1c0010e0 + 9854500 9839 1c0000e8 000380e7 jalr x1, x7, 0 x1=1c0000ec x7:1c000a4c + 9888500 9873 1c000a4c fe010113 addi x2, x2, -32 x2=10000970 x2:10000990 + 9889500 9874 1c000a4e 00100593 addi x11, x0, 1 x11=00000001 + 9905500 9890 1c000a50 00000513 addi x10, x0, 0 x10=00000000 + 9906500 9891 1c000a52 00112e23 sw x1, 28(x2) x1:1c0000ec x2:10000970 PA:1000098c + 9907500 9892 1c000a54 00812c23 sw x8, 24(x2) x8:00000000 x2:10000970 PA:10000988 + 9908500 9893 1c000a56 00912a23 sw x9, 20(x2) x9:00000000 x2:10000970 PA:10000984 + 9909500 9894 1c000a58 01212823 sw x18, 16(x2) x18:00000000 x2:10000970 PA:10000980 + 9910500 9895 1c000a5a 4aa000ef jal x1, 1194 x1=1c000a5c + 9912500 9897 1c000f04 fe010113 addi x2, x2, -32 x2=10000950 x2:10000970 + 9913500 9898 1c000f06 01312623 sw x19, 12(x2) x19:00000000 x2:10000950 PA:1000095c + 9914500 9899 1c000f08 00b009b3 add x19, x0, x11 x19=00000001 x11:00000001 + 9915500 9900 1c000f0a 00112e23 sw x1, 28(x2) x1:1c000a5c x2:10000950 PA:1000096c + 9916500 9901 1c000f0c 00812c23 sw x8, 24(x2) x8:00000000 x2:10000950 PA:10000968 + 9917500 9902 1c000f0e 00912a23 sw x9, 20(x2) x9:00000000 x2:10000950 PA:10000964 + 9918500 9903 1c000f10 01212823 sw x18, 16(x2) x18:00000000 x2:10000950 PA:10000960 + 9919500 9904 1c000f12 01412423 sw x20, 8(x2) x20:00000000 x2:10000950 PA:10000958 + 9920500 9905 1c000f14 01512223 sw x21, 4(x2) x21:00000000 x2:10000950 PA:10000954 + 9921500 9906 1c000f16 01612023 sw x22, 0(x2) x22:00000000 x2:10000950 PA:10000950 + 9922500 9907 1c000f18 30047af3 csrrci x21, 0x00000008, 0x300 x21=00001808 + 9926500 9911 1c000f1c 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 9927500 9912 1c000f1e 00051763 bne x10, x0, 14 x10:00000000 + 9928500 9913 1c000f20 100007b7 lui x15, 0x10000000 x15=10000000 + 9929500 9914 1c000f24 15c7a783 lw x15, 348(x15) x15=10000070 x15:10000000 PA:1000015c + 9931500 9916 1c000f28 0b87a903 lw x18, 184(x15) x18=1000013c x15:10000070 PA:10000128 + 9932500 9917 1c000f2c 07000593 addi x11, x0, 112 x11=00000070 + 9933500 9918 1c000f30 02b985b3 mul x11, x19, x11 x11=00000070 x19:00000001 x11:00000070 + 9934500 9919 1c000f34 f1402573 csrrs x10, x0, 0xf14 x10=00000000 + 9935500 9920 1c000f38 40555513 srai x10, x10, 0x405 x10=00000000 x10:00000000 + 9936500 9921 1c000f3a f2653533 p.bclr x10, x10, 25, 6 x10=00000000 x10:00000000 + 9937500 9922 1c000f3e 00250513 addi x10, x10, 2 x10=00000002 x10:00000000 + 9938500 9923 1c000f40 290000ef jal x1, 656 x1=1c000f42 + 9940500 9925 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 9941500 9926 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000002 + 9942500 9927 1c0011d6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 9943500 9928 1c0011da 69c7a783 lw x15, 1692(x15) x15=10000990 x15:1c002000 PA:1c00269c + 9957500 9942 1c0011de ffe50513 addi x10, x10, -2 x10=00000000 x10:00000002 + 9958500 9943 1c0011e0 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 9959500 9944 1c0011e2 00f50533 add x10, x10, x15 x10=10000990 x10:00000000 x15:10000990 + 9960500 9945 1c0011e4 f6fff06f jal x0, -146 + 9962500 9947 1c001152 00052783 lw x15, 0(x10) x15=100009a0 x10:10000990 PA:10000990 + 9963500 9948 1c001154 00758593 addi x11, x11, 7 x11=00000077 x11:00000070 + 9964500 9949 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000070 x11:00000077 + 9965500 9950 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 9966500 9951 1c00115c 00078963 beq x15, x0, 18 x15:100009a0 + 9967500 9952 1c00115e 0007a703 lw x14, 0(x15) x14=000fbdf0 x15:100009a0 PA:100009a0 + 9969500 9954 1c001160 00b74963 blt x14, x11, 18 x14:000fbdf0 x11:00000070 + 9970500 9955 1c001164 00b71c63 bne x14, x11, 24 x14:000fbdf0 x11:00000070 + 9973500 9958 1c00117c 40b70733 sub x14, x14, x11 x14=000fbd80 x14:000fbdf0 x11:00000070 + 9974500 9959 1c00117e 00e7a023 sw x14, 0(x15) x14:000fbd80 x15:100009a0 PA:100009a0 + 9975500 9960 1c001180 00e787b3 add x15, x15, x14 x15=100fc720 x15:100009a0 x14:000fbd80 + 9976500 9961 1c001182 fedff06f jal x0, -20 + 9978500 9963 1c00116e 00f00533 add x10, x0, x15 x10=100fc720 x15:100fc720 + 9979500 9964 1c001170 00008067 jalr x0, x1, 0 x1:1c000f42 + 9981500 9966 1c000f42 00a00433 add x8, x0, x10 x8=100fc720 x10:100fc720 + 9982500 9967 1c000f44 fff00513 addi x10, x0, -1 x10=ffffffff + 9983500 9968 1c000f46 00040c63 beq x8, x0, 24 x8:100fc720 + 9984500 9969 1c000f48 00840413 addi x8, x8, 8 x8=100fc728 x8:100fc720 + 9985500 9970 1c000f4a 00000493 addi x9, x0, 0 x9=00000000 + 9986500 9971 1c000f4c 10000b37 lui x22, 0x10000000 x22=10000000 + 9987500 9972 1c000f50 ff840a13 addi x20, x8, -8 x20=100fc720 x8:100fc728 + 9988500 9973 1c000f54 0134cf63 blt x9, x19, 30 x9:00000000 x19:00000001 + 9991500 9976 1c000f72 012005b3 add x11, x0, x18 x11=1000013c x18:1000013c + 9992500 9977 1c000f74 01400533 add x10, x0, x20 x10=100fc720 x20:100fc720 + 9993500 9978 1c000f76 f43ff0ef jal x1, -190 x1=1c000f78 + 9995500 9980 1c000eb8 ff010113 addi x2, x2, -16 x2=10000940 x2:10000950 + 9996500 9981 1c000eba 00812423 sw x8, 8(x2) x8:100fc728 x2:10000940 PA:10000948 + 9997500 9982 1c000ebc 00912223 sw x9, 4(x2) x9:00000000 x2:10000940 PA:10000944 + 9998500 9983 1c000ebe 00112623 sw x1, 12(x2) x1:1c000f78 x2:10000940 PA:1000094c + 9999500 9984 1c000ec0 00a00433 add x8, x0, x10 x8=100fc720 x10:100fc720 + 10000500 9985 1c000ec2 00b004b3 add x9, x0, x11 x9=1000013c x11:1000013c + 10001500 9986 1c000ec4 00052823 sw x0, 16(x10) x10:100fc720 PA:100fc730 + 10002500 9987 1c000ec8 00052a23 sw x0, 20(x10) x10:100fc720 PA:100fc734 + 10003500 9988 1c000ecc 01000593 addi x11, x0, 16 x11=00000010 + 10004500 9989 1c000ece 00000513 addi x10, x0, 0 x10=00000000 + 10005500 9990 1c000ed0 300000ef jal x1, 768 x1=1c000ed2 + 10007500 9992 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 10008500 9993 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000000 + 10011500 9996 1c0011e6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 10012500 9997 1c0011ea 00251513 slli x10, x10, 0x2 x10=00000000 x10:00000000 + 10013500 9998 1c0011ec 6a078793 addi x15, x15, 1696 x15=1c0026a0 x15:1c002000 + 10014500 9999 1c0011f0 ff3ff06f jal x0, -14 + 10016500 10001 1c0011e2 00f50533 add x10, x10, x15 x10=1c0026a0 x10:00000000 x15:1c0026a0 + 10017500 10002 1c0011e4 f6fff06f jal x0, -146 + 10019500 10004 1c001152 00052783 lw x15, 0(x10) x15=1c0026b8 x10:1c0026a0 PA:1c0026a0 + 10033500 10018 1c001154 00758593 addi x11, x11, 7 x11=00000017 x11:00000010 + 10034500 10019 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00000010 x11:00000017 + 10035500 10020 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 10036500 10021 1c00115c 00078963 beq x15, x0, 18 x15:1c0026b8 + 10037500 10022 1c00115e 0007a703 lw x14, 0(x15) x14=002cd918 x15:1c0026b8 PA:1c0026b8 + 10052500 10037 1c001160 00b74963 blt x14, x11, 18 x14:002cd918 x11:00000010 + 10053500 10038 1c001164 00b71c63 bne x14, x11, 24 x14:002cd918 x11:00000010 + 10056500 10041 1c00117c 40b70733 sub x14, x14, x11 x14=002cd908 x14:002cd918 x11:00000010 + 10057500 10042 1c00117e 00e7a023 sw x14, 0(x15) x14:002cd908 x15:1c0026b8 PA:1c0026b8 + 10075500 10060 1c001180 00e787b3 add x15, x15, x14 x15=1c2cffc0 x15:1c0026b8 x14:002cd908 + 10076500 10061 1c001182 fedff06f jal x0, -20 + 10078500 10063 1c00116e 00f00533 add x10, x0, x15 x10=1c2cffc0 x15:1c2cffc0 + 10079500 10064 1c001170 00008067 jalr x0, x1, 0 x1:1c000ed2 + 10081500 10066 1c000ed2 06a42623 sw x10, 108(x8) x10:1c2cffc0 x8:100fc720 PA:100fc78c + 10082500 10067 1c000ed4 00942623 sw x9, 12(x8) x9:1000013c x8:100fc720 PA:100fc72c + 10083500 10068 1c000ed6 00042023 sw x0, 0(x8) x8:100fc720 PA:100fc720 + 10084500 10069 1c000eda 00c12083 lw x1, 12(x2) x1=1c000f78 x2:10000940 PA:1000094c + 10085500 10070 1c000edc 00812403 lw x8, 8(x2) x8=100fc728 x2:10000940 PA:10000948 + 10086500 10071 1c000ede 00412483 lw x9, 4(x2) x9=00000000 x2:10000940 PA:10000944 + 10087500 10072 1c000ee0 01010113 addi x2, x2, 16 x2=10000950 x2:10000940 + 10088500 10073 1c000ee2 00008067 jalr x0, x1, 0 x1:1c000f78 + 10090500 10075 1c000f78 138b0793 addi x15, x22, 312 x15=10000138 x22:10000000 + 10091500 10076 1c000f7c 0007a703 lw x14, 0(x15) x14=100000b8 x15:10000138 PA:10000138 + 10092500 10077 1c000f7e 00148493 addi x9, x9, 1 x9=00000001 x9:00000000 + 10093500 10078 1c000f80 06e4282b p.sw x14, 112(x8!) x8=100fc798 x14:100000b8 x8:100fc728 PA:100fc728 + 10094500 10079 1c000f84 0147a023 sw x20, 0(x15) x20:100fc720 x15:10000138 PA:10000138 + 10095500 10080 1c000f88 fc9ff06f jal x0, -56 + 10097500 10082 1c000f50 ff840a13 addi x20, x8, -8 x20=100fc790 x8:100fc798 + 10098500 10083 1c000f54 0134cf63 blt x9, x19, 30 x9:00000001 x19:00000001 + 10099500 10084 1c000f58 300a9073 csrrw x0, x21, 0x300 x21:00001808 + 10103500 10088 1c000f5c 00000513 addi x10, x0, 0 x10=00000000 + 10104500 10089 1c000f5e 01c12083 lw x1, 28(x2) x1=1c000a5c x2:10000950 PA:1000096c + 10105500 10090 1c000f60 01812403 lw x8, 24(x2) x8=00000000 x2:10000950 PA:10000968 + 10106500 10091 1c000f62 01412483 lw x9, 20(x2) x9=00000000 x2:10000950 PA:10000964 + 10107500 10092 1c000f64 01012903 lw x18, 16(x2) x18=00000000 x2:10000950 PA:10000960 + 10108500 10093 1c000f66 00c12983 lw x19, 12(x2) x19=00000000 x2:10000950 PA:1000095c + 10109500 10094 1c000f68 00812a03 lw x20, 8(x2) x20=00000000 x2:10000950 PA:10000958 + 10110500 10095 1c000f6a 00412a83 lw x21, 4(x2) x21=00000000 x2:10000950 PA:10000954 + 10111500 10096 1c000f6c 00012b03 lw x22, 0(x2) x22=00000000 x2:10000950 PA:10000950 + 10112500 10097 1c000f6e 02010113 addi x2, x2, 32 x2=10000970 x2:10000950 + 10113500 10098 1c000f70 00008067 jalr x0, x1, 0 x1:1c000a5c + 10115500 10100 1c000a5c 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 10132500 10117 1c000a60 00000613 addi x12, x0, 0 x12=00000000 + 10133500 10118 1c000a62 9ba58593 addi x11, x11, -1606 x11=1c0009ba x11:1c001000 + 10134500 10119 1c000a66 00000513 addi x10, x0, 0 x10=00000000 + 10135500 10120 1c000a68 522000ef jal x1, 1314 x1=1c000a6a + 10137500 10122 1c000f8a 300476f3 csrrci x13, 0x00000008, 0x300 x13=00001808 + 10141500 10126 1c000f8e 00051763 bne x10, x0, 14 x10:00000000 + 10155500 10140 1c000f90 100007b7 lui x15, 0x10000000 x15=10000000 + 10156500 10141 1c000f94 15c7a783 lw x15, 348(x15) x15=10000070 x15:10000000 PA:1000015c + 10158500 10143 1c000f98 0b87a503 lw x10, 184(x15) x10=1000013c x15:10000070 PA:10000128 + 10159500 10144 1c000f9c 10000737 lui x14, 0x10000000 x14=10000000 + 10175500 10160 1c000fa0 13870713 addi x14, x14, 312 x14=10000138 x14:10000000 + 10176500 10161 1c000fa4 00072783 lw x15, 0(x14) x15=100fc720 x14:10000138 PA:10000138 + 10178500 10163 1c000fa6 00078863 beq x15, x0, 16 x15:100fc720 + 10179500 10164 1c000fa8 0087a803 lw x16, 8(x15) x16=100000b8 x15:100fc720 PA:100fc728 + 10180500 10165 1c000fac 00c7a223 sw x12, 4(x15) x12:00000000 x15:100fc720 PA:100fc724 + 10181500 10166 1c000fae 00a7a623 sw x10, 12(x15) x10:1000013c x15:100fc720 PA:100fc72c + 10197500 10182 1c000fb0 01072023 sw x16, 0(x14) x16:100000b8 x14:10000138 PA:10000138 + 10198500 10183 1c000fb4 00b7a023 sw x11, 0(x15) x11:1c0009ba x15:100fc720 PA:100fc720 + 10199500 10184 1c000fb6 30069073 csrrw x0, x13, 0x300 x13:00001808 + 10203500 10188 1c000fba 00f00533 add x10, x0, x15 x10=100fc720 x15:100fc720 + 10204500 10189 1c000fbc 00008067 jalr x0, x1, 0 x1:1c000a6a + 10222500 10207 1c000a6a 00a004b3 add x9, x0, x10 x9=100fc720 x10:100fc720 + 10223500 10208 1c000a6c 00000413 addi x8, x0, 0 x8=00000000 + 10224500 10209 1c000a6e 008005b3 add x11, x0, x8 x11=00000000 x8:00000000 + 10240500 10225 1c000a70 009006b3 add x13, x0, x9 x13=100fc720 x9:100fc720 + 10241500 10226 1c000a72 00140413 addi x8, x8, 1 x8=00000001 x8:00000000 + 10242500 10227 1c000a74 00000613 addi x12, x0, 0 x12=00000000 + 10243500 10228 1c000a76 00100513 addi x10, x0, 1 x10=00000001 + 10244500 10229 1c000a78 12b000ef jal x1, 2346 x1=1c000a7c + 10246500 10231 1c0013a2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 10247500 10232 1c0013a4 02812423 sw x8, 40(x2) x8:00000001 x2:10000940 PA:10000968 + 10248500 10233 1c0013a6 00b00433 add x8, x0, x11 x8=00000000 x11:00000000 + 10249500 10234 1c0013a8 02112623 sw x1, 44(x2) x1:1c000a7c x2:10000940 PA:1000096c + 10250500 10235 1c0013aa 02912223 sw x9, 36(x2) x9:100fc720 x2:10000940 PA:10000964 + 10251500 10236 1c0013ac 03212023 sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960 + 10252500 10237 1c0013ae 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 10268500 10253 1c0013b0 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 10269500 10254 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 10270500 10255 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 10274500 10259 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 10275500 10260 1c0013ba 03458a33 mul x20, x11, x20 x20=00000000 x11:00000000 x20:00000018 + 10292500 10277 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 10293500 10278 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 10307500 10292 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 10308500 10293 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff50 x15:1c2fff50 x20:00000000 + 10309500 10294 1c0013ca 0007a703 lw x14, 0(x15) x14=00000001 x15:1c2fff50 PA:1c2fff50 + 10323500 10308 1c0013cc 02050363 beq x10, x0, 38 x10:00000001 + 10324500 10309 1c0013ce 00170713 addi x14, x14, 1 x14=00000002 x14:00000001 + 10325500 10310 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000002 x15:1c2fff50 PA:1c2fff50 + 10343500 10328 1c0013d2 0007a483 lw x9, 0(x15) x9=00000002 x15:1c2fff50 PA:1c2fff50 + 10358500 10343 1c0013d4 02049163 bne x9, x0, 34 x9:00000002 + 10361500 10346 1c0013f6 fe14b3e3 p.bneimm x9, -26 x9:00000002 + 10364500 10349 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 10368500 10353 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000a7c x2:10000940 PA:1000096c + 10369500 10354 1c0013e2 02812403 lw x8, 40(x2) x8=00000001 x2:10000940 PA:10000968 + 10370500 10355 1c0013e4 02412483 lw x9, 36(x2) x9=100fc720 x2:10000940 PA:10000964 + 10371500 10356 1c0013e6 02012903 lw x18, 32(x2) x18=00000000 x2:10000940 PA:10000960 + 10372500 10357 1c0013e8 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 10373500 10358 1c0013ea 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 10374500 10359 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 10375500 10360 1c0013ee 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 10376500 10361 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000a7c + 10378500 10363 1c000a7c fe4439e3 p.bneimm x8, -14 x8:00000001 + 10396500 10381 1c000a6e 008005b3 add x11, x0, x8 x11=00000001 x8:00000001 + 10397500 10382 1c000a70 009006b3 add x13, x0, x9 x13=100fc720 x9:100fc720 + 10398500 10383 1c000a72 00140413 addi x8, x8, 1 x8=00000002 x8:00000001 + 10399500 10384 1c000a74 00000613 addi x12, x0, 0 x12=00000000 + 10400500 10385 1c000a76 00100513 addi x10, x0, 1 x10=00000001 + 10401500 10386 1c000a78 12b000ef jal x1, 2346 x1=1c000a7c + 10403500 10388 1c0013a2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 10404500 10389 1c0013a4 02812423 sw x8, 40(x2) x8:00000002 x2:10000940 PA:10000968 + 10405500 10390 1c0013a6 00b00433 add x8, x0, x11 x8=00000001 x11:00000001 + 10406500 10391 1c0013a8 02112623 sw x1, 44(x2) x1:1c000a7c x2:10000940 PA:1000096c + 10407500 10392 1c0013aa 02912223 sw x9, 36(x2) x9:100fc720 x2:10000940 PA:10000964 + 10408500 10393 1c0013ac 03212023 sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960 + 10409500 10394 1c0013ae 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 10410500 10395 1c0013b0 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 10411500 10396 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 10412500 10397 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 10416500 10401 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 10417500 10402 1c0013ba 03458a33 mul x20, x11, x20 x20=00000018 x11:00000001 x20:00000018 + 10418500 10403 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 10419500 10404 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 10433500 10418 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 10434500 10419 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff68 x15:1c2fff50 x20:00000018 + 10435500 10420 1c0013ca 0007a703 lw x14, 0(x15) x14=00000000 x15:1c2fff68 PA:1c2fff68 + 10449500 10434 1c0013cc 02050363 beq x10, x0, 38 x10:00000001 + 10450500 10435 1c0013ce 00170713 addi x14, x14, 1 x14=00000001 x14:00000000 + 10451500 10436 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000001 x15:1c2fff68 PA:1c2fff68 + 10469500 10454 1c0013d2 0007a483 lw x9, 0(x15) x9=00000001 x15:1c2fff68 PA:1c2fff68 + 10484500 10469 1c0013d4 02049163 bne x9, x0, 34 x9:00000001 + 10487500 10472 1c0013f6 fe14b3e3 p.bneimm x9, -26 x9:00000001 + 10488500 10473 1c0013fa 00800993 addi x19, x0, 8 x19=00000008 + 10489500 10474 1c0013fe 04040f63 beq x8, x0, 94 x8:00000001 + 10490500 10475 1c001400 00800533 add x10, x0, x8 x10=00000001 x8:00000001 + 10491500 10476 1c001402 00d12623 sw x13, 12(x2) x13:100fc720 x2:10000940 PA:1000094c + 10492500 10477 1c001404 ed3ff0ef jal x1, -302 x1=1c001406 + 10494500 10479 1c0012d6 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 10495500 10480 1c0012d8 00812423 sw x8, 8(x2) x8:00000001 x2:10000930 PA:10000938 + 10496500 10481 1c0012da 00912223 sw x9, 4(x2) x9:00000001 x2:10000930 PA:10000934 + 10497500 10482 1c0012dc 04050413 addi x8, x10, 64 x8=00000041 x10:00000001 + 10498500 10483 1c0012e0 00a004b3 add x9, x0, x10 x9=00000001 x10:00000001 + 10499500 10484 1c0012e2 1b000537 lui x10, 0x1b000000 x10=1b000000 + 10500500 10485 1c0012e6 00850513 addi x10, x10, 8 x10=1b000008 x10:1b000000 + 10501500 10486 1c0012ea 01641413 slli x8, x8, 0x16 x8=10400000 x8:00000041 + 10502500 10487 1c0012ec e6c53533 p.bclr x10, x10, 19, 12 x10=00000008 x10:1b000008 + 10503500 10488 1c0012f0 00850533 add x10, x10, x8 x10=10400008 x10:00000008 x8:10400000 + 10504500 10489 1c0012f2 04000613 addi x12, x0, 64 x12=00000040 + 10505500 10490 1c0012f6 00000593 addi x11, x0, 0 x11=00000000 + 10506500 10491 1c0012f8 00112623 sw x1, 12(x2) x1:1c001406 x2:10000930 PA:1000093c + 10507500 10492 1c0012fa 506000ef jal x1, 1286 x1=1c0012fc + 10509500 10494 1c001800 00a60633 add x12, x12, x10 x12=10400048 x12:00000040 x10:10400008 + 10510500 10495 1c001802 00a007b3 add x15, x0, x10 x15=10400008 x10:10400008 + 10511500 10496 1c001804 00c79363 bne x15, x12, 6 x15:10400008 x12:10400048 + 10514500 10499 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400009 x11:00000000 x15:10400008 PA:10400008 + 10534500 10519 1c00180e ff7ff06f jal x0, -10 + 10535500 10520 1c001804 00c79363 bne x15, x12, 6 x15:10400009 x12:10400048 + 10538500 10523 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040000a x11:00000000 x15:10400009 PA:10400009 + 10558500 10543 1c00180e ff7ff06f jal x0, -10 + 10559500 10544 1c001804 00c79363 bne x15, x12, 6 x15:1040000a x12:10400048 + 10562500 10547 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040000b x11:00000000 x15:1040000a PA:1040000a + 10582500 10567 1c00180e ff7ff06f jal x0, -10 + 10583500 10568 1c001804 00c79363 bne x15, x12, 6 x15:1040000b x12:10400048 + 10586500 10571 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040000c x11:00000000 x15:1040000b PA:1040000b + 10606500 10591 1c00180e ff7ff06f jal x0, -10 + 10607500 10592 1c001804 00c79363 bne x15, x12, 6 x15:1040000c x12:10400048 + 10610500 10595 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040000d x11:00000000 x15:1040000c PA:1040000c + 10630500 10615 1c00180e ff7ff06f jal x0, -10 + 10631500 10616 1c001804 00c79363 bne x15, x12, 6 x15:1040000d x12:10400048 + 10634500 10619 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040000e x11:00000000 x15:1040000d PA:1040000d + 10654500 10639 1c00180e ff7ff06f jal x0, -10 + 10655500 10640 1c001804 00c79363 bne x15, x12, 6 x15:1040000e x12:10400048 + 10658500 10643 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040000f x11:00000000 x15:1040000e PA:1040000e + 10678500 10663 1c00180e ff7ff06f jal x0, -10 + 10679500 10664 1c001804 00c79363 bne x15, x12, 6 x15:1040000f x12:10400048 + 10682500 10667 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400010 x11:00000000 x15:1040000f PA:1040000f + 10702500 10687 1c00180e ff7ff06f jal x0, -10 + 10703500 10688 1c001804 00c79363 bne x15, x12, 6 x15:10400010 x12:10400048 + 10706500 10691 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400011 x11:00000000 x15:10400010 PA:10400010 + 10726500 10711 1c00180e ff7ff06f jal x0, -10 + 10727500 10712 1c001804 00c79363 bne x15, x12, 6 x15:10400011 x12:10400048 + 10730500 10715 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400012 x11:00000000 x15:10400011 PA:10400011 + 10750500 10735 1c00180e ff7ff06f jal x0, -10 + 10751500 10736 1c001804 00c79363 bne x15, x12, 6 x15:10400012 x12:10400048 + 10754500 10739 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400013 x11:00000000 x15:10400012 PA:10400012 + 10774500 10759 1c00180e ff7ff06f jal x0, -10 + 10775500 10760 1c001804 00c79363 bne x15, x12, 6 x15:10400013 x12:10400048 + 10778500 10763 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400014 x11:00000000 x15:10400013 PA:10400013 + 10798500 10783 1c00180e ff7ff06f jal x0, -10 + 10799500 10784 1c001804 00c79363 bne x15, x12, 6 x15:10400014 x12:10400048 + 10802500 10787 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400015 x11:00000000 x15:10400014 PA:10400014 + 10822500 10807 1c00180e ff7ff06f jal x0, -10 + 10823500 10808 1c001804 00c79363 bne x15, x12, 6 x15:10400015 x12:10400048 + 10826500 10811 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400016 x11:00000000 x15:10400015 PA:10400015 + 10846500 10831 1c00180e ff7ff06f jal x0, -10 + 10847500 10832 1c001804 00c79363 bne x15, x12, 6 x15:10400016 x12:10400048 + 10850500 10835 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400017 x11:00000000 x15:10400016 PA:10400016 + 10870500 10855 1c00180e ff7ff06f jal x0, -10 + 10871500 10856 1c001804 00c79363 bne x15, x12, 6 x15:10400017 x12:10400048 + 10874500 10859 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400018 x11:00000000 x15:10400017 PA:10400017 + 10894500 10879 1c00180e ff7ff06f jal x0, -10 + 10895500 10880 1c001804 00c79363 bne x15, x12, 6 x15:10400018 x12:10400048 + 10898500 10883 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400019 x11:00000000 x15:10400018 PA:10400018 + 10918500 10903 1c00180e ff7ff06f jal x0, -10 + 10919500 10904 1c001804 00c79363 bne x15, x12, 6 x15:10400019 x12:10400048 + 10922500 10907 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040001a x11:00000000 x15:10400019 PA:10400019 + 10942500 10927 1c00180e ff7ff06f jal x0, -10 + 10943500 10928 1c001804 00c79363 bne x15, x12, 6 x15:1040001a x12:10400048 + 10946500 10931 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040001b x11:00000000 x15:1040001a PA:1040001a + 10966500 10951 1c00180e ff7ff06f jal x0, -10 + 10967500 10952 1c001804 00c79363 bne x15, x12, 6 x15:1040001b x12:10400048 + 10970500 10955 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040001c x11:00000000 x15:1040001b PA:1040001b + 10990500 10975 1c00180e ff7ff06f jal x0, -10 + 10991500 10976 1c001804 00c79363 bne x15, x12, 6 x15:1040001c x12:10400048 + 10994500 10979 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040001d x11:00000000 x15:1040001c PA:1040001c + 11014500 10999 1c00180e ff7ff06f jal x0, -10 + 11015500 11000 1c001804 00c79363 bne x15, x12, 6 x15:1040001d x12:10400048 + 11018500 11003 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040001e x11:00000000 x15:1040001d PA:1040001d + 11038500 11023 1c00180e ff7ff06f jal x0, -10 + 11039500 11024 1c001804 00c79363 bne x15, x12, 6 x15:1040001e x12:10400048 + 11042500 11027 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040001f x11:00000000 x15:1040001e PA:1040001e + 11062500 11047 1c00180e ff7ff06f jal x0, -10 + 11063500 11048 1c001804 00c79363 bne x15, x12, 6 x15:1040001f x12:10400048 + 11066500 11051 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400020 x11:00000000 x15:1040001f PA:1040001f + 11086500 11071 1c00180e ff7ff06f jal x0, -10 + 11087500 11072 1c001804 00c79363 bne x15, x12, 6 x15:10400020 x12:10400048 + 11090500 11075 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400021 x11:00000000 x15:10400020 PA:10400020 + 11110500 11095 1c00180e ff7ff06f jal x0, -10 + 11111500 11096 1c001804 00c79363 bne x15, x12, 6 x15:10400021 x12:10400048 + 11114500 11099 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400022 x11:00000000 x15:10400021 PA:10400021 + 11134500 11119 1c00180e ff7ff06f jal x0, -10 + 11135500 11120 1c001804 00c79363 bne x15, x12, 6 x15:10400022 x12:10400048 + 11138500 11123 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400023 x11:00000000 x15:10400022 PA:10400022 + 11158500 11143 1c00180e ff7ff06f jal x0, -10 + 11159500 11144 1c001804 00c79363 bne x15, x12, 6 x15:10400023 x12:10400048 + 11162500 11147 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400024 x11:00000000 x15:10400023 PA:10400023 + 11182500 11167 1c00180e ff7ff06f jal x0, -10 + 11183500 11168 1c001804 00c79363 bne x15, x12, 6 x15:10400024 x12:10400048 + 11186500 11171 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400025 x11:00000000 x15:10400024 PA:10400024 + 11206500 11191 1c00180e ff7ff06f jal x0, -10 + 11207500 11192 1c001804 00c79363 bne x15, x12, 6 x15:10400025 x12:10400048 + 11210500 11195 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400026 x11:00000000 x15:10400025 PA:10400025 + 11230500 11215 1c00180e ff7ff06f jal x0, -10 + 11231500 11216 1c001804 00c79363 bne x15, x12, 6 x15:10400026 x12:10400048 + 11234500 11219 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400027 x11:00000000 x15:10400026 PA:10400026 + 11254500 11239 1c00180e ff7ff06f jal x0, -10 + 11255500 11240 1c001804 00c79363 bne x15, x12, 6 x15:10400027 x12:10400048 + 11258500 11243 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400028 x11:00000000 x15:10400027 PA:10400027 + 11278500 11263 1c00180e ff7ff06f jal x0, -10 + 11279500 11264 1c001804 00c79363 bne x15, x12, 6 x15:10400028 x12:10400048 + 11282500 11267 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400029 x11:00000000 x15:10400028 PA:10400028 + 11302500 11287 1c00180e ff7ff06f jal x0, -10 + 11303500 11288 1c001804 00c79363 bne x15, x12, 6 x15:10400029 x12:10400048 + 11306500 11291 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040002a x11:00000000 x15:10400029 PA:10400029 + 11326500 11311 1c00180e ff7ff06f jal x0, -10 + 11327500 11312 1c001804 00c79363 bne x15, x12, 6 x15:1040002a x12:10400048 + 11330500 11315 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040002b x11:00000000 x15:1040002a PA:1040002a + 11350500 11335 1c00180e ff7ff06f jal x0, -10 + 11351500 11336 1c001804 00c79363 bne x15, x12, 6 x15:1040002b x12:10400048 + 11354500 11339 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040002c x11:00000000 x15:1040002b PA:1040002b + 11374500 11359 1c00180e ff7ff06f jal x0, -10 + 11375500 11360 1c001804 00c79363 bne x15, x12, 6 x15:1040002c x12:10400048 + 11378500 11363 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040002d x11:00000000 x15:1040002c PA:1040002c + 11398500 11383 1c00180e ff7ff06f jal x0, -10 + 11399500 11384 1c001804 00c79363 bne x15, x12, 6 x15:1040002d x12:10400048 + 11402500 11387 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040002e x11:00000000 x15:1040002d PA:1040002d + 11422500 11407 1c00180e ff7ff06f jal x0, -10 + 11423500 11408 1c001804 00c79363 bne x15, x12, 6 x15:1040002e x12:10400048 + 11426500 11411 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040002f x11:00000000 x15:1040002e PA:1040002e + 11446500 11431 1c00180e ff7ff06f jal x0, -10 + 11447500 11432 1c001804 00c79363 bne x15, x12, 6 x15:1040002f x12:10400048 + 11450500 11435 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400030 x11:00000000 x15:1040002f PA:1040002f + 11470500 11455 1c00180e ff7ff06f jal x0, -10 + 11471500 11456 1c001804 00c79363 bne x15, x12, 6 x15:10400030 x12:10400048 + 11474500 11459 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400031 x11:00000000 x15:10400030 PA:10400030 + 11494500 11479 1c00180e ff7ff06f jal x0, -10 + 11495500 11480 1c001804 00c79363 bne x15, x12, 6 x15:10400031 x12:10400048 + 11498500 11483 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400032 x11:00000000 x15:10400031 PA:10400031 + 11518500 11503 1c00180e ff7ff06f jal x0, -10 + 11519500 11504 1c001804 00c79363 bne x15, x12, 6 x15:10400032 x12:10400048 + 11522500 11507 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400033 x11:00000000 x15:10400032 PA:10400032 + 11542500 11527 1c00180e ff7ff06f jal x0, -10 + 11543500 11528 1c001804 00c79363 bne x15, x12, 6 x15:10400033 x12:10400048 + 11546500 11531 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400034 x11:00000000 x15:10400033 PA:10400033 + 11566500 11551 1c00180e ff7ff06f jal x0, -10 + 11567500 11552 1c001804 00c79363 bne x15, x12, 6 x15:10400034 x12:10400048 + 11570500 11555 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400035 x11:00000000 x15:10400034 PA:10400034 + 11590500 11575 1c00180e ff7ff06f jal x0, -10 + 11591500 11576 1c001804 00c79363 bne x15, x12, 6 x15:10400035 x12:10400048 + 11594500 11579 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400036 x11:00000000 x15:10400035 PA:10400035 + 11614500 11599 1c00180e ff7ff06f jal x0, -10 + 11615500 11600 1c001804 00c79363 bne x15, x12, 6 x15:10400036 x12:10400048 + 11618500 11603 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400037 x11:00000000 x15:10400036 PA:10400036 + 11638500 11623 1c00180e ff7ff06f jal x0, -10 + 11639500 11624 1c001804 00c79363 bne x15, x12, 6 x15:10400037 x12:10400048 + 11642500 11627 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400038 x11:00000000 x15:10400037 PA:10400037 + 11662500 11647 1c00180e ff7ff06f jal x0, -10 + 11663500 11648 1c001804 00c79363 bne x15, x12, 6 x15:10400038 x12:10400048 + 11666500 11651 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400039 x11:00000000 x15:10400038 PA:10400038 + 11686500 11671 1c00180e ff7ff06f jal x0, -10 + 11687500 11672 1c001804 00c79363 bne x15, x12, 6 x15:10400039 x12:10400048 + 11690500 11675 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040003a x11:00000000 x15:10400039 PA:10400039 + 11710500 11695 1c00180e ff7ff06f jal x0, -10 + 11711500 11696 1c001804 00c79363 bne x15, x12, 6 x15:1040003a x12:10400048 + 11714500 11699 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040003b x11:00000000 x15:1040003a PA:1040003a + 11734500 11719 1c00180e ff7ff06f jal x0, -10 + 11735500 11720 1c001804 00c79363 bne x15, x12, 6 x15:1040003b x12:10400048 + 11738500 11723 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040003c x11:00000000 x15:1040003b PA:1040003b + 11758500 11743 1c00180e ff7ff06f jal x0, -10 + 11759500 11744 1c001804 00c79363 bne x15, x12, 6 x15:1040003c x12:10400048 + 11762500 11747 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040003d x11:00000000 x15:1040003c PA:1040003c + 11782500 11767 1c00180e ff7ff06f jal x0, -10 + 11783500 11768 1c001804 00c79363 bne x15, x12, 6 x15:1040003d x12:10400048 + 11786500 11771 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040003e x11:00000000 x15:1040003d PA:1040003d + 11806500 11791 1c00180e ff7ff06f jal x0, -10 + 11807500 11792 1c001804 00c79363 bne x15, x12, 6 x15:1040003e x12:10400048 + 11810500 11795 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1040003f x11:00000000 x15:1040003e PA:1040003e + 11830500 11815 1c00180e ff7ff06f jal x0, -10 + 11831500 11816 1c001804 00c79363 bne x15, x12, 6 x15:1040003f x12:10400048 + 11834500 11819 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400040 x11:00000000 x15:1040003f PA:1040003f + 11854500 11839 1c00180e ff7ff06f jal x0, -10 + 11855500 11840 1c001804 00c79363 bne x15, x12, 6 x15:10400040 x12:10400048 + 11858500 11843 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400041 x11:00000000 x15:10400040 PA:10400040 + 11878500 11863 1c00180e ff7ff06f jal x0, -10 + 11879500 11864 1c001804 00c79363 bne x15, x12, 6 x15:10400041 x12:10400048 + 11882500 11867 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400042 x11:00000000 x15:10400041 PA:10400041 + 11902500 11887 1c00180e ff7ff06f jal x0, -10 + 11903500 11888 1c001804 00c79363 bne x15, x12, 6 x15:10400042 x12:10400048 + 11906500 11891 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400043 x11:00000000 x15:10400042 PA:10400042 + 11926500 11911 1c00180e ff7ff06f jal x0, -10 + 11927500 11912 1c001804 00c79363 bne x15, x12, 6 x15:10400043 x12:10400048 + 11930500 11915 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400044 x11:00000000 x15:10400043 PA:10400043 + 11950500 11935 1c00180e ff7ff06f jal x0, -10 + 11951500 11936 1c001804 00c79363 bne x15, x12, 6 x15:10400044 x12:10400048 + 11954500 11939 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400045 x11:00000000 x15:10400044 PA:10400044 + 11974500 11959 1c00180e ff7ff06f jal x0, -10 + 11975500 11960 1c001804 00c79363 bne x15, x12, 6 x15:10400045 x12:10400048 + 11978500 11963 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400046 x11:00000000 x15:10400045 PA:10400045 + 11998500 11983 1c00180e ff7ff06f jal x0, -10 + 11999500 11984 1c001804 00c79363 bne x15, x12, 6 x15:10400046 x12:10400048 + 12002500 11987 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400047 x11:00000000 x15:10400046 PA:10400046 + 12022500 12007 1c00180e ff7ff06f jal x0, -10 + 12023500 12008 1c001804 00c79363 bne x15, x12, 6 x15:10400047 x12:10400048 + 12026500 12011 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10400048 x11:00000000 x15:10400047 PA:10400047 + 12046500 12031 1c00180e ff7ff06f jal x0, -10 + 12047500 12032 1c001804 00c79363 bne x15, x12, 6 x15:10400048 x12:10400048 + 12048500 12033 1c001808 00008067 jalr x0, x1, 0 x1:1c0012fc + 12050500 12035 1c0012fc 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 12051500 12036 1c001300 6a87a783 lw x15, 1704(x15) x15=1c2fff50 x15:1c002000 PA:1c0026a8 + 12065500 12050 1c001304 01800713 addi x14, x0, 24 x14=00000018 + 12066500 12051 1c001306 00c12083 lw x1, 12(x2) x1=1c001406 x2:10000930 PA:1000093c + 12067500 12052 1c001308 42e487b3 p.mac x15, x9, x14 x15=1c2fff68 x15:1c2fff50 x9:00000001 x14:00000018 + 12068500 12053 1c00130c 00201737 lui x14, 0x201000 x14=00201000 + 12069500 12054 1c001310 e0470713 addi x14, x14, -508 x14=00200e04 x14:00201000 + 12070500 12055 1c001314 00e40433 add x8, x8, x14 x8=10600e04 x8:10400000 x14:00200e04 + 12071500 12056 1c001316 00412483 lw x9, 4(x2) x9=00000001 x2:10000930 PA:10000934 + 12072500 12057 1c001318 0087aa23 sw x8, 20(x15) x8:10600e04 x15:1c2fff68 PA:1c2fff7c + 12090500 12075 1c00131a 00812403 lw x8, 8(x2) x8=00000001 x2:10000930 PA:10000938 + 12091500 12076 1c00131c 0007a623 sw x0, 12(x15) x15:1c2fff68 PA:1c2fff74 + 12109500 12094 1c001320 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 12110500 12095 1c001322 00008067 jalr x0, x1, 0 x1:1c001406 + 12112500 12097 1c001406 00800533 add x10, x0, x8 x10=00000001 x8:00000001 + 12113500 12098 1c001408 e0dff0ef jal x1, -500 x1=1c00140a + 12131500 12116 1c001214 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 12132500 12117 1c001218 69c7a703 lw x14, 1692(x15) x14=10000990 x15:1c002000 PA:1c00269c + 12147500 12132 1c00121c 100017b7 lui x15, 0x10001000 x15=10001000 + 12151500 12136 1c001220 01651593 slli x11, x10, 0x16 x11=00400000 x10:00000001 + 12152500 12137 1c001224 000ff637 lui x12, 0xff000 x12=000ff000 + 12153500 12138 1c001228 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 12154500 12139 1c00122a 99078793 addi x15, x15, -1648 x15=10000990 x15:10001000 + 12155500 12140 1c00122e 67060613 addi x12, x12, 1648 x12=000ff670 x12:000ff000 + 12156500 12141 1c001232 00f585b3 add x11, x11, x15 x11=10400990 x11:00400000 x15:10000990 + 12157500 12142 1c001234 00e50533 add x10, x10, x14 x10=10000994 x10:00000004 x14:10000990 + 12158500 12143 1c001236 efdff06f jal x0, -260 + 12160500 12145 1c001132 00758793 addi x15, x11, 7 x15=10400997 x11:10400990 + 12161500 12146 1c001136 c407b7b3 p.bclr x15, x15, 2, 0 x15=10400990 x15:10400997 + 12162500 12147 1c00113a 40b785b3 sub x11, x15, x11 x11=00000000 x15:10400990 x11:10400990 + 12163500 12148 1c00113e 00f52023 sw x15, 0(x10) x15:10400990 x10:10000994 PA:10000994 + 12164500 12149 1c001140 40b60633 sub x12, x12, x11 x12=000ff670 x12:000ff670 x11:00000000 + 12165500 12150 1c001142 00c05763 bge x0, x12, 14 x12:000ff670 + 12166500 12151 1c001146 c4063633 p.bclr x12, x12, 2, 0 x12=000ff670 x12:000ff670 + 12167500 12152 1c00114a 00c7a023 sw x12, 0(x15) x12:000ff670 x15:10400990 PA:10400990 + 12187500 12172 1c00114c 0007a223 sw x0, 4(x15) x15:10400990 PA:10400994 + 12207500 12192 1c001150 00008067 jalr x0, x1, 0 x1:1c00140a + 12208500 12193 1c00140a 6a8aa783 lw x15, 1704(x21) x15=1c2fff50 x21:1c002000 PA:1c0026a8 + 12227500 12212 1c00140e 04040413 addi x8, x8, 64 x8=00000041 x8:00000001 + 12228500 12213 1c001412 01641413 slli x8, x8, 0x16 x8=10400000 x8:00000041 + 12229500 12214 1c001414 00fa0a33 add x20, x20, x15 x20=1c2fff68 x20:00000018 x15:1c2fff50 + 12230500 12215 1c001416 002017b7 lui x15, 0x201000 x15=00201000 + 12231500 12216 1c00141a 40078793 addi x15, x15, 1024 x15=00201400 x15:00201000 + 12232500 12217 1c00141e fff00713 addi x14, x0, -1 x14=ffffffff + 12249500 12234 1c001420 000a2223 sw x0, 4(x20) x20:1c2fff68 PA:1c2fff6c + 12267500 12252 1c001424 00e467a3 p.sw x14, x0(x8) x14:ffffffff x8:10400000 PA:10601400 + 12293500 12278 1c001428 00c12683 lw x13, 12(x2) x13=100fc720 x2:10000940 PA:1000094c + 12294500 12279 1c00142a 002007b7 lui x15, 0x200000 x15=00200000 + 12311500 12296 1c00142e 1c000737 lui x14, 0x1c000000 x14=1c000000 + 12312500 12297 1c001432 04078793 addi x15, x15, 64 x15=00200040 x15:00200000 + 12313500 12298 1c001436 08070713 addi x14, x14, 128 x14=1c000080 x14:1c000000 + 12314500 12299 1c00143a 008787b3 add x15, x15, x8 x15=10600040 x15:00200040 x8:10400000 + 12315500 12300 1c00143c 00000613 addi x12, x0, 0 x12=00000000 + 12332500 12317 1c00143e ce073733 p.bclr x14, x14, 7, 0 x14=1c000000 x14:1c000080 + 12333500 12318 1c001442 01364963 blt x12, x19, 18 x12:00000000 x19:00000008 + 12336500 12321 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10600044 x14:1c000000 x15:10600040 PA:10600040 + 12359500 12344 1c001458 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 12360500 12345 1c00145a fe9ff06f jal x0, -24 + 12362500 12347 1c001442 01364963 blt x12, x19, 18 x12:00000001 x19:00000008 + 12365500 12350 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10600048 x14:1c000000 x15:10600044 PA:10600044 + 12388500 12373 1c001458 00160613 addi x12, x12, 1 x12=00000002 x12:00000001 + 12389500 12374 1c00145a fe9ff06f jal x0, -24 + 12391500 12376 1c001442 01364963 blt x12, x19, 18 x12:00000002 x19:00000008 + 12394500 12379 1c001454 00e7a22b p.sw x14, 4(x15!) x15=1060004c x14:1c000000 x15:10600048 PA:10600048 + 12417500 12402 1c001458 00160613 addi x12, x12, 1 x12=00000003 x12:00000002 + 12418500 12403 1c00145a fe9ff06f jal x0, -24 + 12420500 12405 1c001442 01364963 blt x12, x19, 18 x12:00000003 x19:00000008 + 12423500 12408 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10600050 x14:1c000000 x15:1060004c PA:1060004c + 12446500 12431 1c001458 00160613 addi x12, x12, 1 x12=00000004 x12:00000003 + 12447500 12432 1c00145a fe9ff06f jal x0, -24 + 12449500 12434 1c001442 01364963 blt x12, x19, 18 x12:00000004 x19:00000008 + 12452500 12437 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10600054 x14:1c000000 x15:10600050 PA:10600050 + 12475500 12460 1c001458 00160613 addi x12, x12, 1 x12=00000005 x12:00000004 + 12476500 12461 1c00145a fe9ff06f jal x0, -24 + 12478500 12463 1c001442 01364963 blt x12, x19, 18 x12:00000005 x19:00000008 + 12481500 12466 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10600058 x14:1c000000 x15:10600054 PA:10600054 + 12504500 12489 1c001458 00160613 addi x12, x12, 1 x12=00000006 x12:00000005 + 12505500 12490 1c00145a fe9ff06f jal x0, -24 + 12507500 12492 1c001442 01364963 blt x12, x19, 18 x12:00000006 x19:00000008 + 12510500 12495 1c001454 00e7a22b p.sw x14, 4(x15!) x15=1060005c x14:1c000000 x15:10600058 PA:10600058 + 12533500 12518 1c001458 00160613 addi x12, x12, 1 x12=00000007 x12:00000006 + 12534500 12519 1c00145a fe9ff06f jal x0, -24 + 12536500 12521 1c001442 01364963 blt x12, x19, 18 x12:00000007 x19:00000008 + 12539500 12524 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10600060 x14:1c000000 x15:1060005c PA:1060005c + 12562500 12547 1c001458 00160613 addi x12, x12, 1 x12=00000008 x12:00000007 + 12563500 12548 1c00145a fe9ff06f jal x0, -24 + 12565500 12550 1c001442 01364963 blt x12, x19, 18 x12:00000008 x19:00000008 + 12566500 12551 1c001446 002007b7 lui x15, 0x200000 x15=00200000 + 12567500 12552 1c00144a 00878793 addi x15, x15, 8 x15=00200008 x15:00200000 + 12568500 12553 1c00144c fff00713 addi x14, x0, -1 x14=ffffffff + 12569500 12554 1c00144e 00e467a3 p.sw x14, x0(x8) x14:ffffffff x8:10400000 PA:10600008 + 12592500 12577 1c001452 f85ff06f jal x0, -124 + 12593500 12578 1c0013d6 00068363 beq x13, x0, 6 x13:100fc720 + 12594500 12579 1c0013d8 00d00533 add x10, x0, x13 x10=100fc720 x13:100fc720 + 12595500 12580 1c0013da c1dff0ef jal x1, -996 x1=1c0013dc + 12613500 12598 1c000ff6 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 12614500 12599 1c000ff8 00112623 sw x1, 12(x2) x1:1c0013dc x2:10000930 PA:1000093c + 12615500 12600 1c000ffa 00812423 sw x8, 8(x2) x8:10400000 x2:10000930 PA:10000938 + 12616500 12601 1c000ffc 30047473 csrrci x8, 0x00000008, 0x300 x8=00001800 + 12633500 12618 1c001000 00c52783 lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c + 12634500 12619 1c001002 00052423 sw x0, 8(x10) x10:100fc720 PA:100fc728 + 12635500 12620 1c001006 0007a703 lw x14, 0(x15) x14=00000000 x15:1000013c PA:1000013c + 12637500 12622 1c001008 00071e63 bne x14, x0, 28 x14:00000000 + 12638500 12623 1c00100a 00a7a023 sw x10, 0(x15) x10:100fc720 x15:1000013c PA:1000013c + 12639500 12624 1c00100c 00a7a223 sw x10, 4(x15) x10:100fc720 x15:1000013c PA:10000140 + 12640500 12625 1c00100e 00c7a503 lw x10, 12(x15) x10=00000000 x15:1000013c PA:10000148 + 12656500 12641 1c001010 00050463 beq x10, x0, 8 x10:00000000 + 12659500 12644 1c001018 30041073 csrrw x0, x8, 0x300 x8:00001800 + 12663500 12648 1c00101c 00c12083 lw x1, 12(x2) x1=1c0013dc x2:10000930 PA:1000093c + 12664500 12649 1c00101e 00812403 lw x8, 8(x2) x8=10400000 x2:10000930 PA:10000938 + 12677500 12662 1c001020 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 12678500 12663 1c001022 00008067 jalr x0, x1, 0 x1:1c0013dc + 12680500 12665 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 12684500 12669 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000a7c x2:10000940 PA:1000096c + 12685500 12670 1c0013e2 02812403 lw x8, 40(x2) x8=00000002 x2:10000940 PA:10000968 + 12686500 12671 1c0013e4 02412483 lw x9, 36(x2) x9=100fc720 x2:10000940 PA:10000964 + 12687500 12672 1c0013e6 02012903 lw x18, 32(x2) x18=00000000 x2:10000940 PA:10000960 + 12688500 12673 1c0013e8 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 12689500 12674 1c0013ea 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 12690500 12675 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 12691500 12676 1c0013ee 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 12692500 12677 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000a7c + 12694500 12679 1c000a7c fe4439e3 p.bneimm x8, -14 x8:00000002 + 12697500 12682 1c000a6e 008005b3 add x11, x0, x8 x11=00000002 x8:00000002 + 12698500 12683 1c000a70 009006b3 add x13, x0, x9 x13=100fc720 x9:100fc720 + 12699500 12684 1c000a72 00140413 addi x8, x8, 1 x8=00000003 x8:00000002 + 12700500 12685 1c000a74 00000613 addi x12, x0, 0 x12=00000000 + 12701500 12686 1c000a76 00100513 addi x10, x0, 1 x10=00000001 + 12702500 12687 1c000a78 12b000ef jal x1, 2346 x1=1c000a7c + 12704500 12689 1c0013a2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 12705500 12690 1c0013a4 02812423 sw x8, 40(x2) x8:00000003 x2:10000940 PA:10000968 + 12706500 12691 1c0013a6 00b00433 add x8, x0, x11 x8=00000002 x11:00000002 + 12707500 12692 1c0013a8 02112623 sw x1, 44(x2) x1:1c000a7c x2:10000940 PA:1000096c + 12708500 12693 1c0013aa 02912223 sw x9, 36(x2) x9:100fc720 x2:10000940 PA:10000964 + 12709500 12694 1c0013ac 03212023 sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960 + 12710500 12695 1c0013ae 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 12711500 12696 1c0013b0 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 12712500 12697 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 12713500 12698 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 12717500 12702 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 12718500 12703 1c0013ba 03458a33 mul x20, x11, x20 x20=00000030 x11:00000002 x20:00000018 + 12719500 12704 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 12720500 12705 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 12735500 12720 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 12736500 12721 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff80 x15:1c2fff50 x20:00000030 + 12737500 12722 1c0013ca 0007a703 lw x14, 0(x15) x14=00000000 x15:1c2fff80 PA:1c2fff80 + 12752500 12737 1c0013cc 02050363 beq x10, x0, 38 x10:00000001 + 12753500 12738 1c0013ce 00170713 addi x14, x14, 1 x14=00000001 x14:00000000 + 12754500 12739 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000001 x15:1c2fff80 PA:1c2fff80 + 12772500 12757 1c0013d2 0007a483 lw x9, 0(x15) x9=00000001 x15:1c2fff80 PA:1c2fff80 + 12787500 12772 1c0013d4 02049163 bne x9, x0, 34 x9:00000001 + 12790500 12775 1c0013f6 fe14b3e3 p.bneimm x9, -26 x9:00000001 + 12791500 12776 1c0013fa 00800993 addi x19, x0, 8 x19=00000008 + 12792500 12777 1c0013fe 04040f63 beq x8, x0, 94 x8:00000002 + 12793500 12778 1c001400 00800533 add x10, x0, x8 x10=00000002 x8:00000002 + 12794500 12779 1c001402 00d12623 sw x13, 12(x2) x13:100fc720 x2:10000940 PA:1000094c + 12795500 12780 1c001404 ed3ff0ef jal x1, -302 x1=1c001406 + 12797500 12782 1c0012d6 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 12798500 12783 1c0012d8 00812423 sw x8, 8(x2) x8:00000002 x2:10000930 PA:10000938 + 12799500 12784 1c0012da 00912223 sw x9, 4(x2) x9:00000001 x2:10000930 PA:10000934 + 12800500 12785 1c0012dc 04050413 addi x8, x10, 64 x8=00000042 x10:00000002 + 12801500 12786 1c0012e0 00a004b3 add x9, x0, x10 x9=00000002 x10:00000002 + 12802500 12787 1c0012e2 1b000537 lui x10, 0x1b000000 x10=1b000000 + 12803500 12788 1c0012e6 00850513 addi x10, x10, 8 x10=1b000008 x10:1b000000 + 12804500 12789 1c0012ea 01641413 slli x8, x8, 0x16 x8=10800000 x8:00000042 + 12805500 12790 1c0012ec e6c53533 p.bclr x10, x10, 19, 12 x10=00000008 x10:1b000008 + 12806500 12791 1c0012f0 00850533 add x10, x10, x8 x10=10800008 x10:00000008 x8:10800000 + 12807500 12792 1c0012f2 04000613 addi x12, x0, 64 x12=00000040 + 12808500 12793 1c0012f6 00000593 addi x11, x0, 0 x11=00000000 + 12809500 12794 1c0012f8 00112623 sw x1, 12(x2) x1:1c001406 x2:10000930 PA:1000093c + 12810500 12795 1c0012fa 506000ef jal x1, 1286 x1=1c0012fc + 12812500 12797 1c001800 00a60633 add x12, x12, x10 x12=10800048 x12:00000040 x10:10800008 + 12813500 12798 1c001802 00a007b3 add x15, x0, x10 x15=10800008 x10:10800008 + 12814500 12799 1c001804 00c79363 bne x15, x12, 6 x15:10800008 x12:10800048 + 12817500 12802 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800009 x11:00000000 x15:10800008 PA:10800008 + 12837500 12822 1c00180e ff7ff06f jal x0, -10 + 12838500 12823 1c001804 00c79363 bne x15, x12, 6 x15:10800009 x12:10800048 + 12841500 12826 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080000a x11:00000000 x15:10800009 PA:10800009 + 12861500 12846 1c00180e ff7ff06f jal x0, -10 + 12862500 12847 1c001804 00c79363 bne x15, x12, 6 x15:1080000a x12:10800048 + 12865500 12850 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080000b x11:00000000 x15:1080000a PA:1080000a + 12885500 12870 1c00180e ff7ff06f jal x0, -10 + 12886500 12871 1c001804 00c79363 bne x15, x12, 6 x15:1080000b x12:10800048 + 12889500 12874 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080000c x11:00000000 x15:1080000b PA:1080000b + 12909500 12894 1c00180e ff7ff06f jal x0, -10 + 12910500 12895 1c001804 00c79363 bne x15, x12, 6 x15:1080000c x12:10800048 + 12913500 12898 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080000d x11:00000000 x15:1080000c PA:1080000c + 12933500 12918 1c00180e ff7ff06f jal x0, -10 + 12934500 12919 1c001804 00c79363 bne x15, x12, 6 x15:1080000d x12:10800048 + 12937500 12922 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080000e x11:00000000 x15:1080000d PA:1080000d + 12957500 12942 1c00180e ff7ff06f jal x0, -10 + 12958500 12943 1c001804 00c79363 bne x15, x12, 6 x15:1080000e x12:10800048 + 12961500 12946 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080000f x11:00000000 x15:1080000e PA:1080000e + 12981500 12966 1c00180e ff7ff06f jal x0, -10 + 12982500 12967 1c001804 00c79363 bne x15, x12, 6 x15:1080000f x12:10800048 + 12985500 12970 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800010 x11:00000000 x15:1080000f PA:1080000f + 13005500 12990 1c00180e ff7ff06f jal x0, -10 + 13006500 12991 1c001804 00c79363 bne x15, x12, 6 x15:10800010 x12:10800048 + 13009500 12994 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800011 x11:00000000 x15:10800010 PA:10800010 + 13029500 13014 1c00180e ff7ff06f jal x0, -10 + 13030500 13015 1c001804 00c79363 bne x15, x12, 6 x15:10800011 x12:10800048 + 13033500 13018 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800012 x11:00000000 x15:10800011 PA:10800011 + 13053500 13038 1c00180e ff7ff06f jal x0, -10 + 13054500 13039 1c001804 00c79363 bne x15, x12, 6 x15:10800012 x12:10800048 + 13057500 13042 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800013 x11:00000000 x15:10800012 PA:10800012 + 13077500 13062 1c00180e ff7ff06f jal x0, -10 + 13078500 13063 1c001804 00c79363 bne x15, x12, 6 x15:10800013 x12:10800048 + 13081500 13066 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800014 x11:00000000 x15:10800013 PA:10800013 + 13101500 13086 1c00180e ff7ff06f jal x0, -10 + 13102500 13087 1c001804 00c79363 bne x15, x12, 6 x15:10800014 x12:10800048 + 13105500 13090 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800015 x11:00000000 x15:10800014 PA:10800014 + 13125500 13110 1c00180e ff7ff06f jal x0, -10 + 13126500 13111 1c001804 00c79363 bne x15, x12, 6 x15:10800015 x12:10800048 + 13129500 13114 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800016 x11:00000000 x15:10800015 PA:10800015 + 13149500 13134 1c00180e ff7ff06f jal x0, -10 + 13150500 13135 1c001804 00c79363 bne x15, x12, 6 x15:10800016 x12:10800048 + 13153500 13138 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800017 x11:00000000 x15:10800016 PA:10800016 + 13173500 13158 1c00180e ff7ff06f jal x0, -10 + 13174500 13159 1c001804 00c79363 bne x15, x12, 6 x15:10800017 x12:10800048 + 13177500 13162 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800018 x11:00000000 x15:10800017 PA:10800017 + 13197500 13182 1c00180e ff7ff06f jal x0, -10 + 13198500 13183 1c001804 00c79363 bne x15, x12, 6 x15:10800018 x12:10800048 + 13201500 13186 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800019 x11:00000000 x15:10800018 PA:10800018 + 13221500 13206 1c00180e ff7ff06f jal x0, -10 + 13222500 13207 1c001804 00c79363 bne x15, x12, 6 x15:10800019 x12:10800048 + 13225500 13210 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080001a x11:00000000 x15:10800019 PA:10800019 + 13245500 13230 1c00180e ff7ff06f jal x0, -10 + 13246500 13231 1c001804 00c79363 bne x15, x12, 6 x15:1080001a x12:10800048 + 13249500 13234 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080001b x11:00000000 x15:1080001a PA:1080001a + 13269500 13254 1c00180e ff7ff06f jal x0, -10 + 13270500 13255 1c001804 00c79363 bne x15, x12, 6 x15:1080001b x12:10800048 + 13273500 13258 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080001c x11:00000000 x15:1080001b PA:1080001b + 13293500 13278 1c00180e ff7ff06f jal x0, -10 + 13294500 13279 1c001804 00c79363 bne x15, x12, 6 x15:1080001c x12:10800048 + 13297500 13282 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080001d x11:00000000 x15:1080001c PA:1080001c + 13317500 13302 1c00180e ff7ff06f jal x0, -10 + 13318500 13303 1c001804 00c79363 bne x15, x12, 6 x15:1080001d x12:10800048 + 13321500 13306 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080001e x11:00000000 x15:1080001d PA:1080001d + 13341500 13326 1c00180e ff7ff06f jal x0, -10 + 13342500 13327 1c001804 00c79363 bne x15, x12, 6 x15:1080001e x12:10800048 + 13345500 13330 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080001f x11:00000000 x15:1080001e PA:1080001e + 13365500 13350 1c00180e ff7ff06f jal x0, -10 + 13366500 13351 1c001804 00c79363 bne x15, x12, 6 x15:1080001f x12:10800048 + 13369500 13354 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800020 x11:00000000 x15:1080001f PA:1080001f + 13389500 13374 1c00180e ff7ff06f jal x0, -10 + 13390500 13375 1c001804 00c79363 bne x15, x12, 6 x15:10800020 x12:10800048 + 13393500 13378 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800021 x11:00000000 x15:10800020 PA:10800020 + 13413500 13398 1c00180e ff7ff06f jal x0, -10 + 13414500 13399 1c001804 00c79363 bne x15, x12, 6 x15:10800021 x12:10800048 + 13417500 13402 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800022 x11:00000000 x15:10800021 PA:10800021 + 13437500 13422 1c00180e ff7ff06f jal x0, -10 + 13438500 13423 1c001804 00c79363 bne x15, x12, 6 x15:10800022 x12:10800048 + 13441500 13426 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800023 x11:00000000 x15:10800022 PA:10800022 + 13461500 13446 1c00180e ff7ff06f jal x0, -10 + 13462500 13447 1c001804 00c79363 bne x15, x12, 6 x15:10800023 x12:10800048 + 13465500 13450 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800024 x11:00000000 x15:10800023 PA:10800023 + 13485500 13470 1c00180e ff7ff06f jal x0, -10 + 13486500 13471 1c001804 00c79363 bne x15, x12, 6 x15:10800024 x12:10800048 + 13489500 13474 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800025 x11:00000000 x15:10800024 PA:10800024 + 13509500 13494 1c00180e ff7ff06f jal x0, -10 + 13510500 13495 1c001804 00c79363 bne x15, x12, 6 x15:10800025 x12:10800048 + 13513500 13498 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800026 x11:00000000 x15:10800025 PA:10800025 + 13533500 13518 1c00180e ff7ff06f jal x0, -10 + 13534500 13519 1c001804 00c79363 bne x15, x12, 6 x15:10800026 x12:10800048 + 13537500 13522 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800027 x11:00000000 x15:10800026 PA:10800026 + 13557500 13542 1c00180e ff7ff06f jal x0, -10 + 13558500 13543 1c001804 00c79363 bne x15, x12, 6 x15:10800027 x12:10800048 + 13561500 13546 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800028 x11:00000000 x15:10800027 PA:10800027 + 13581500 13566 1c00180e ff7ff06f jal x0, -10 + 13582500 13567 1c001804 00c79363 bne x15, x12, 6 x15:10800028 x12:10800048 + 13585500 13570 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800029 x11:00000000 x15:10800028 PA:10800028 + 13605500 13590 1c00180e ff7ff06f jal x0, -10 + 13606500 13591 1c001804 00c79363 bne x15, x12, 6 x15:10800029 x12:10800048 + 13609500 13594 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080002a x11:00000000 x15:10800029 PA:10800029 + 13629500 13614 1c00180e ff7ff06f jal x0, -10 + 13630500 13615 1c001804 00c79363 bne x15, x12, 6 x15:1080002a x12:10800048 + 13633500 13618 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080002b x11:00000000 x15:1080002a PA:1080002a + 13653500 13638 1c00180e ff7ff06f jal x0, -10 + 13654500 13639 1c001804 00c79363 bne x15, x12, 6 x15:1080002b x12:10800048 + 13657500 13642 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080002c x11:00000000 x15:1080002b PA:1080002b + 13677500 13662 1c00180e ff7ff06f jal x0, -10 + 13678500 13663 1c001804 00c79363 bne x15, x12, 6 x15:1080002c x12:10800048 + 13681500 13666 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080002d x11:00000000 x15:1080002c PA:1080002c + 13701500 13686 1c00180e ff7ff06f jal x0, -10 + 13702500 13687 1c001804 00c79363 bne x15, x12, 6 x15:1080002d x12:10800048 + 13705500 13690 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080002e x11:00000000 x15:1080002d PA:1080002d + 13725500 13710 1c00180e ff7ff06f jal x0, -10 + 13726500 13711 1c001804 00c79363 bne x15, x12, 6 x15:1080002e x12:10800048 + 13729500 13714 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080002f x11:00000000 x15:1080002e PA:1080002e + 13749500 13734 1c00180e ff7ff06f jal x0, -10 + 13750500 13735 1c001804 00c79363 bne x15, x12, 6 x15:1080002f x12:10800048 + 13753500 13738 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800030 x11:00000000 x15:1080002f PA:1080002f + 13773500 13758 1c00180e ff7ff06f jal x0, -10 + 13774500 13759 1c001804 00c79363 bne x15, x12, 6 x15:10800030 x12:10800048 + 13777500 13762 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800031 x11:00000000 x15:10800030 PA:10800030 + 13797500 13782 1c00180e ff7ff06f jal x0, -10 + 13798500 13783 1c001804 00c79363 bne x15, x12, 6 x15:10800031 x12:10800048 + 13801500 13786 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800032 x11:00000000 x15:10800031 PA:10800031 + 13821500 13806 1c00180e ff7ff06f jal x0, -10 + 13822500 13807 1c001804 00c79363 bne x15, x12, 6 x15:10800032 x12:10800048 + 13825500 13810 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800033 x11:00000000 x15:10800032 PA:10800032 + 13845500 13830 1c00180e ff7ff06f jal x0, -10 + 13846500 13831 1c001804 00c79363 bne x15, x12, 6 x15:10800033 x12:10800048 + 13849500 13834 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800034 x11:00000000 x15:10800033 PA:10800033 + 13869500 13854 1c00180e ff7ff06f jal x0, -10 + 13870500 13855 1c001804 00c79363 bne x15, x12, 6 x15:10800034 x12:10800048 + 13873500 13858 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800035 x11:00000000 x15:10800034 PA:10800034 + 13893500 13878 1c00180e ff7ff06f jal x0, -10 + 13894500 13879 1c001804 00c79363 bne x15, x12, 6 x15:10800035 x12:10800048 + 13897500 13882 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800036 x11:00000000 x15:10800035 PA:10800035 + 13917500 13902 1c00180e ff7ff06f jal x0, -10 + 13918500 13903 1c001804 00c79363 bne x15, x12, 6 x15:10800036 x12:10800048 + 13921500 13906 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800037 x11:00000000 x15:10800036 PA:10800036 + 13941500 13926 1c00180e ff7ff06f jal x0, -10 + 13942500 13927 1c001804 00c79363 bne x15, x12, 6 x15:10800037 x12:10800048 + 13945500 13930 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800038 x11:00000000 x15:10800037 PA:10800037 + 13965500 13950 1c00180e ff7ff06f jal x0, -10 + 13966500 13951 1c001804 00c79363 bne x15, x12, 6 x15:10800038 x12:10800048 + 13969500 13954 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800039 x11:00000000 x15:10800038 PA:10800038 + 13989500 13974 1c00180e ff7ff06f jal x0, -10 + 13990500 13975 1c001804 00c79363 bne x15, x12, 6 x15:10800039 x12:10800048 + 13993500 13978 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080003a x11:00000000 x15:10800039 PA:10800039 + 14013500 13998 1c00180e ff7ff06f jal x0, -10 + 14014500 13999 1c001804 00c79363 bne x15, x12, 6 x15:1080003a x12:10800048 + 14017500 14002 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080003b x11:00000000 x15:1080003a PA:1080003a + 14037500 14022 1c00180e ff7ff06f jal x0, -10 + 14038500 14023 1c001804 00c79363 bne x15, x12, 6 x15:1080003b x12:10800048 + 14041500 14026 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080003c x11:00000000 x15:1080003b PA:1080003b + 14061500 14046 1c00180e ff7ff06f jal x0, -10 + 14062500 14047 1c001804 00c79363 bne x15, x12, 6 x15:1080003c x12:10800048 + 14065500 14050 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080003d x11:00000000 x15:1080003c PA:1080003c + 14085500 14070 1c00180e ff7ff06f jal x0, -10 + 14086500 14071 1c001804 00c79363 bne x15, x12, 6 x15:1080003d x12:10800048 + 14089500 14074 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080003e x11:00000000 x15:1080003d PA:1080003d + 14109500 14094 1c00180e ff7ff06f jal x0, -10 + 14110500 14095 1c001804 00c79363 bne x15, x12, 6 x15:1080003e x12:10800048 + 14113500 14098 1c00180a 00b780ab p.sb x11, 1(x15!) x15=1080003f x11:00000000 x15:1080003e PA:1080003e + 14133500 14118 1c00180e ff7ff06f jal x0, -10 + 14134500 14119 1c001804 00c79363 bne x15, x12, 6 x15:1080003f x12:10800048 + 14137500 14122 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800040 x11:00000000 x15:1080003f PA:1080003f + 14157500 14142 1c00180e ff7ff06f jal x0, -10 + 14158500 14143 1c001804 00c79363 bne x15, x12, 6 x15:10800040 x12:10800048 + 14161500 14146 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800041 x11:00000000 x15:10800040 PA:10800040 + 14181500 14166 1c00180e ff7ff06f jal x0, -10 + 14182500 14167 1c001804 00c79363 bne x15, x12, 6 x15:10800041 x12:10800048 + 14185500 14170 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800042 x11:00000000 x15:10800041 PA:10800041 + 14205500 14190 1c00180e ff7ff06f jal x0, -10 + 14206500 14191 1c001804 00c79363 bne x15, x12, 6 x15:10800042 x12:10800048 + 14209500 14194 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800043 x11:00000000 x15:10800042 PA:10800042 + 14229500 14214 1c00180e ff7ff06f jal x0, -10 + 14230500 14215 1c001804 00c79363 bne x15, x12, 6 x15:10800043 x12:10800048 + 14233500 14218 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800044 x11:00000000 x15:10800043 PA:10800043 + 14253500 14238 1c00180e ff7ff06f jal x0, -10 + 14254500 14239 1c001804 00c79363 bne x15, x12, 6 x15:10800044 x12:10800048 + 14257500 14242 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800045 x11:00000000 x15:10800044 PA:10800044 + 14277500 14262 1c00180e ff7ff06f jal x0, -10 + 14278500 14263 1c001804 00c79363 bne x15, x12, 6 x15:10800045 x12:10800048 + 14281500 14266 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800046 x11:00000000 x15:10800045 PA:10800045 + 14301500 14286 1c00180e ff7ff06f jal x0, -10 + 14302500 14287 1c001804 00c79363 bne x15, x12, 6 x15:10800046 x12:10800048 + 14305500 14290 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800047 x11:00000000 x15:10800046 PA:10800046 + 14325500 14310 1c00180e ff7ff06f jal x0, -10 + 14326500 14311 1c001804 00c79363 bne x15, x12, 6 x15:10800047 x12:10800048 + 14329500 14314 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10800048 x11:00000000 x15:10800047 PA:10800047 + 14349500 14334 1c00180e ff7ff06f jal x0, -10 + 14350500 14335 1c001804 00c79363 bne x15, x12, 6 x15:10800048 x12:10800048 + 14351500 14336 1c001808 00008067 jalr x0, x1, 0 x1:1c0012fc + 14353500 14338 1c0012fc 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 14354500 14339 1c001300 6a87a783 lw x15, 1704(x15) x15=1c2fff50 x15:1c002000 PA:1c0026a8 + 14368500 14353 1c001304 01800713 addi x14, x0, 24 x14=00000018 + 14369500 14354 1c001306 00c12083 lw x1, 12(x2) x1=1c001406 x2:10000930 PA:1000093c + 14370500 14355 1c001308 42e487b3 p.mac x15, x9, x14 x15=1c2fff80 x15:1c2fff50 x9:00000002 x14:00000018 + 14371500 14356 1c00130c 00201737 lui x14, 0x201000 x14=00201000 + 14372500 14357 1c001310 e0470713 addi x14, x14, -508 x14=00200e04 x14:00201000 + 14373500 14358 1c001314 00e40433 add x8, x8, x14 x8=10a00e04 x8:10800000 x14:00200e04 + 14374500 14359 1c001316 00412483 lw x9, 4(x2) x9=00000001 x2:10000930 PA:10000934 + 14375500 14360 1c001318 0087aa23 sw x8, 20(x15) x8:10a00e04 x15:1c2fff80 PA:1c2fff94 + 14393500 14378 1c00131a 00812403 lw x8, 8(x2) x8=00000002 x2:10000930 PA:10000938 + 14394500 14379 1c00131c 0007a623 sw x0, 12(x15) x15:1c2fff80 PA:1c2fff8c + 14412500 14397 1c001320 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 14413500 14398 1c001322 00008067 jalr x0, x1, 0 x1:1c001406 + 14415500 14400 1c001406 00800533 add x10, x0, x8 x10=00000002 x8:00000002 + 14416500 14401 1c001408 e0dff0ef jal x1, -500 x1=1c00140a + 14418500 14403 1c001214 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 14419500 14404 1c001218 69c7a703 lw x14, 1692(x15) x14=10000990 x15:1c002000 PA:1c00269c + 14433500 14418 1c00121c 100017b7 lui x15, 0x10001000 x15=10001000 + 14434500 14419 1c001220 01651593 slli x11, x10, 0x16 x11=00800000 x10:00000002 + 14435500 14420 1c001224 000ff637 lui x12, 0xff000 x12=000ff000 + 14436500 14421 1c001228 00251513 slli x10, x10, 0x2 x10=00000008 x10:00000002 + 14437500 14422 1c00122a 99078793 addi x15, x15, -1648 x15=10000990 x15:10001000 + 14438500 14423 1c00122e 67060613 addi x12, x12, 1648 x12=000ff670 x12:000ff000 + 14439500 14424 1c001232 00f585b3 add x11, x11, x15 x11=10800990 x11:00800000 x15:10000990 + 14440500 14425 1c001234 00e50533 add x10, x10, x14 x10=10000998 x10:00000008 x14:10000990 + 14441500 14426 1c001236 efdff06f jal x0, -260 + 14443500 14428 1c001132 00758793 addi x15, x11, 7 x15=10800997 x11:10800990 + 14444500 14429 1c001136 c407b7b3 p.bclr x15, x15, 2, 0 x15=10800990 x15:10800997 + 14445500 14430 1c00113a 40b785b3 sub x11, x15, x11 x11=00000000 x15:10800990 x11:10800990 + 14446500 14431 1c00113e 00f52023 sw x15, 0(x10) x15:10800990 x10:10000998 PA:10000998 + 14447500 14432 1c001140 40b60633 sub x12, x12, x11 x12=000ff670 x12:000ff670 x11:00000000 + 14448500 14433 1c001142 00c05763 bge x0, x12, 14 x12:000ff670 + 14449500 14434 1c001146 c4063633 p.bclr x12, x12, 2, 0 x12=000ff670 x12:000ff670 + 14450500 14435 1c00114a 00c7a023 sw x12, 0(x15) x12:000ff670 x15:10800990 PA:10800990 + 14470500 14455 1c00114c 0007a223 sw x0, 4(x15) x15:10800990 PA:10800994 + 14490500 14475 1c001150 00008067 jalr x0, x1, 0 x1:1c00140a + 14491500 14476 1c00140a 6a8aa783 lw x15, 1704(x21) x15=1c2fff50 x21:1c002000 PA:1c0026a8 + 14505500 14490 1c00140e 04040413 addi x8, x8, 64 x8=00000042 x8:00000002 + 14506500 14491 1c001412 01641413 slli x8, x8, 0x16 x8=10800000 x8:00000042 + 14507500 14492 1c001414 00fa0a33 add x20, x20, x15 x20=1c2fff80 x20:00000030 x15:1c2fff50 + 14508500 14493 1c001416 002017b7 lui x15, 0x201000 x15=00201000 + 14509500 14494 1c00141a 40078793 addi x15, x15, 1024 x15=00201400 x15:00201000 + 14510500 14495 1c00141e fff00713 addi x14, x0, -1 x14=ffffffff + 14511500 14496 1c001420 000a2223 sw x0, 4(x20) x20:1c2fff80 PA:1c2fff84 + 14529500 14514 1c001424 00e467a3 p.sw x14, x0(x8) x14:ffffffff x8:10800000 PA:10a01400 + 14555500 14540 1c001428 00c12683 lw x13, 12(x2) x13=100fc720 x2:10000940 PA:1000094c + 14556500 14541 1c00142a 002007b7 lui x15, 0x200000 x15=00200000 + 14557500 14542 1c00142e 1c000737 lui x14, 0x1c000000 x14=1c000000 + 14558500 14543 1c001432 04078793 addi x15, x15, 64 x15=00200040 x15:00200000 + 14559500 14544 1c001436 08070713 addi x14, x14, 128 x14=1c000080 x14:1c000000 + 14560500 14545 1c00143a 008787b3 add x15, x15, x8 x15=10a00040 x15:00200040 x8:10800000 + 14561500 14546 1c00143c 00000613 addi x12, x0, 0 x12=00000000 + 14562500 14547 1c00143e ce073733 p.bclr x14, x14, 7, 0 x14=1c000000 x14:1c000080 + 14563500 14548 1c001442 01364963 blt x12, x19, 18 x12:00000000 x19:00000008 + 14566500 14551 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a00044 x14:1c000000 x15:10a00040 PA:10a00040 + 14589500 14574 1c001458 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 14590500 14575 1c00145a fe9ff06f jal x0, -24 + 14592500 14577 1c001442 01364963 blt x12, x19, 18 x12:00000001 x19:00000008 + 14595500 14580 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a00048 x14:1c000000 x15:10a00044 PA:10a00044 + 14618500 14603 1c001458 00160613 addi x12, x12, 1 x12=00000002 x12:00000001 + 14619500 14604 1c00145a fe9ff06f jal x0, -24 + 14621500 14606 1c001442 01364963 blt x12, x19, 18 x12:00000002 x19:00000008 + 14624500 14609 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a0004c x14:1c000000 x15:10a00048 PA:10a00048 + 14647500 14632 1c001458 00160613 addi x12, x12, 1 x12=00000003 x12:00000002 + 14648500 14633 1c00145a fe9ff06f jal x0, -24 + 14650500 14635 1c001442 01364963 blt x12, x19, 18 x12:00000003 x19:00000008 + 14653500 14638 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a00050 x14:1c000000 x15:10a0004c PA:10a0004c + 14676500 14661 1c001458 00160613 addi x12, x12, 1 x12=00000004 x12:00000003 + 14677500 14662 1c00145a fe9ff06f jal x0, -24 + 14679500 14664 1c001442 01364963 blt x12, x19, 18 x12:00000004 x19:00000008 + 14682500 14667 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a00054 x14:1c000000 x15:10a00050 PA:10a00050 + 14705500 14690 1c001458 00160613 addi x12, x12, 1 x12=00000005 x12:00000004 + 14706500 14691 1c00145a fe9ff06f jal x0, -24 + 14708500 14693 1c001442 01364963 blt x12, x19, 18 x12:00000005 x19:00000008 + 14711500 14696 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a00058 x14:1c000000 x15:10a00054 PA:10a00054 + 14734500 14719 1c001458 00160613 addi x12, x12, 1 x12=00000006 x12:00000005 + 14735500 14720 1c00145a fe9ff06f jal x0, -24 + 14737500 14722 1c001442 01364963 blt x12, x19, 18 x12:00000006 x19:00000008 + 14740500 14725 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a0005c x14:1c000000 x15:10a00058 PA:10a00058 + 14763500 14748 1c001458 00160613 addi x12, x12, 1 x12=00000007 x12:00000006 + 14764500 14749 1c00145a fe9ff06f jal x0, -24 + 14766500 14751 1c001442 01364963 blt x12, x19, 18 x12:00000007 x19:00000008 + 14769500 14754 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10a00060 x14:1c000000 x15:10a0005c PA:10a0005c + 14792500 14777 1c001458 00160613 addi x12, x12, 1 x12=00000008 x12:00000007 + 14793500 14778 1c00145a fe9ff06f jal x0, -24 + 14795500 14780 1c001442 01364963 blt x12, x19, 18 x12:00000008 x19:00000008 + 14796500 14781 1c001446 002007b7 lui x15, 0x200000 x15=00200000 + 14797500 14782 1c00144a 00878793 addi x15, x15, 8 x15=00200008 x15:00200000 + 14798500 14783 1c00144c fff00713 addi x14, x0, -1 x14=ffffffff + 14799500 14784 1c00144e 00e467a3 p.sw x14, x0(x8) x14:ffffffff x8:10800000 PA:10a00008 + 14822500 14807 1c001452 f85ff06f jal x0, -124 + 14823500 14808 1c0013d6 00068363 beq x13, x0, 6 x13:100fc720 + 14824500 14809 1c0013d8 00d00533 add x10, x0, x13 x10=100fc720 x13:100fc720 + 14825500 14810 1c0013da c1dff0ef jal x1, -996 x1=1c0013dc + 14827500 14812 1c000ff6 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 14828500 14813 1c000ff8 00112623 sw x1, 12(x2) x1:1c0013dc x2:10000930 PA:1000093c + 14829500 14814 1c000ffa 00812423 sw x8, 8(x2) x8:10800000 x2:10000930 PA:10000938 + 14830500 14815 1c000ffc 30047473 csrrci x8, 0x00000008, 0x300 x8=00001800 + 14834500 14819 1c001000 00c52783 lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c + 14835500 14820 1c001002 00052423 sw x0, 8(x10) x10:100fc720 PA:100fc728 + 14836500 14821 1c001006 0007a703 lw x14, 0(x15) x14=100fc720 x15:1000013c PA:1000013c + 14838500 14823 1c001008 00071e63 bne x14, x0, 28 x14:100fc720 + 14841500 14826 1c001024 0047a703 lw x14, 4(x15) x14=100fc720 x15:1000013c PA:10000140 + 14843500 14828 1c001026 00a72423 sw x10, 8(x14) x10:100fc720 x14:100fc720 PA:100fc728 + 14844500 14829 1c001028 fe5ff06f jal x0, -28 + 14846500 14831 1c00100c 00a7a223 sw x10, 4(x15) x10:100fc720 x15:1000013c PA:10000140 + 14847500 14832 1c00100e 00c7a503 lw x10, 12(x15) x10=00000000 x15:1000013c PA:10000148 + 14849500 14834 1c001010 00050463 beq x10, x0, 8 x10:00000000 + 14852500 14837 1c001018 30041073 csrrw x0, x8, 0x300 x8:00001800 + 14856500 14841 1c00101c 00c12083 lw x1, 12(x2) x1=1c0013dc x2:10000930 PA:1000093c + 14857500 14842 1c00101e 00812403 lw x8, 8(x2) x8=10800000 x2:10000930 PA:10000938 + 14858500 14843 1c001020 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 14859500 14844 1c001022 00008067 jalr x0, x1, 0 x1:1c0013dc + 14861500 14846 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 14865500 14850 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000a7c x2:10000940 PA:1000096c + 14866500 14851 1c0013e2 02812403 lw x8, 40(x2) x8=00000003 x2:10000940 PA:10000968 + 14867500 14852 1c0013e4 02412483 lw x9, 36(x2) x9=100fc720 x2:10000940 PA:10000964 + 14868500 14853 1c0013e6 02012903 lw x18, 32(x2) x18=00000000 x2:10000940 PA:10000960 + 14869500 14854 1c0013e8 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 14870500 14855 1c0013ea 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 14871500 14856 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 14872500 14857 1c0013ee 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 14873500 14858 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000a7c + 14875500 14860 1c000a7c fe4439e3 p.bneimm x8, -14 x8:00000003 + 14878500 14863 1c000a6e 008005b3 add x11, x0, x8 x11=00000003 x8:00000003 + 14879500 14864 1c000a70 009006b3 add x13, x0, x9 x13=100fc720 x9:100fc720 + 14880500 14865 1c000a72 00140413 addi x8, x8, 1 x8=00000004 x8:00000003 + 14881500 14866 1c000a74 00000613 addi x12, x0, 0 x12=00000000 + 14882500 14867 1c000a76 00100513 addi x10, x0, 1 x10=00000001 + 14883500 14868 1c000a78 12b000ef jal x1, 2346 x1=1c000a7c + 14885500 14870 1c0013a2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 14886500 14871 1c0013a4 02812423 sw x8, 40(x2) x8:00000004 x2:10000940 PA:10000968 + 14887500 14872 1c0013a6 00b00433 add x8, x0, x11 x8=00000003 x11:00000003 + 14888500 14873 1c0013a8 02112623 sw x1, 44(x2) x1:1c000a7c x2:10000940 PA:1000096c + 14889500 14874 1c0013aa 02912223 sw x9, 36(x2) x9:100fc720 x2:10000940 PA:10000964 + 14890500 14875 1c0013ac 03212023 sw x18, 32(x2) x18:00000000 x2:10000940 PA:10000960 + 14891500 14876 1c0013ae 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 14892500 14877 1c0013b0 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 14893500 14878 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 14894500 14879 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 14898500 14883 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 14899500 14884 1c0013ba 03458a33 mul x20, x11, x20 x20=00000048 x11:00000003 x20:00000018 + 14900500 14885 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 14901500 14886 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 14915500 14900 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 14916500 14901 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff98 x15:1c2fff50 x20:00000048 + 14917500 14902 1c0013ca 0007a703 lw x14, 0(x15) x14=00000000 x15:1c2fff98 PA:1c2fff98 + 14931500 14916 1c0013cc 02050363 beq x10, x0, 38 x10:00000001 + 14932500 14917 1c0013ce 00170713 addi x14, x14, 1 x14=00000001 x14:00000000 + 14933500 14918 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000001 x15:1c2fff98 PA:1c2fff98 + 14951500 14936 1c0013d2 0007a483 lw x9, 0(x15) x9=00000001 x15:1c2fff98 PA:1c2fff98 + 14968500 14953 1c0013d4 02049163 bne x9, x0, 34 x9:00000001 + 14971500 14956 1c0013f6 fe14b3e3 p.bneimm x9, -26 x9:00000001 + 14972500 14957 1c0013fa 00800993 addi x19, x0, 8 x19=00000008 + 14973500 14958 1c0013fe 04040f63 beq x8, x0, 94 x8:00000003 + 14974500 14959 1c001400 00800533 add x10, x0, x8 x10=00000003 x8:00000003 + 14975500 14960 1c001402 00d12623 sw x13, 12(x2) x13:100fc720 x2:10000940 PA:1000094c + 14976500 14961 1c001404 ed3ff0ef jal x1, -302 x1=1c001406 + 14978500 14963 1c0012d6 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 14979500 14964 1c0012d8 00812423 sw x8, 8(x2) x8:00000003 x2:10000930 PA:10000938 + 14980500 14965 1c0012da 00912223 sw x9, 4(x2) x9:00000001 x2:10000930 PA:10000934 + 14981500 14966 1c0012dc 04050413 addi x8, x10, 64 x8=00000043 x10:00000003 + 14982500 14967 1c0012e0 00a004b3 add x9, x0, x10 x9=00000003 x10:00000003 + 14983500 14968 1c0012e2 1b000537 lui x10, 0x1b000000 x10=1b000000 + 14984500 14969 1c0012e6 00850513 addi x10, x10, 8 x10=1b000008 x10:1b000000 + 14985500 14970 1c0012ea 01641413 slli x8, x8, 0x16 x8=10c00000 x8:00000043 + 14986500 14971 1c0012ec e6c53533 p.bclr x10, x10, 19, 12 x10=00000008 x10:1b000008 + 14987500 14972 1c0012f0 00850533 add x10, x10, x8 x10=10c00008 x10:00000008 x8:10c00000 + 14988500 14973 1c0012f2 04000613 addi x12, x0, 64 x12=00000040 + 14989500 14974 1c0012f6 00000593 addi x11, x0, 0 x11=00000000 + 14990500 14975 1c0012f8 00112623 sw x1, 12(x2) x1:1c001406 x2:10000930 PA:1000093c + 14991500 14976 1c0012fa 506000ef jal x1, 1286 x1=1c0012fc + 14993500 14978 1c001800 00a60633 add x12, x12, x10 x12=10c00048 x12:00000040 x10:10c00008 + 14994500 14979 1c001802 00a007b3 add x15, x0, x10 x15=10c00008 x10:10c00008 + 14995500 14980 1c001804 00c79363 bne x15, x12, 6 x15:10c00008 x12:10c00048 + 14998500 14983 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00009 x11:00000000 x15:10c00008 PA:10c00008 + 15018500 15003 1c00180e ff7ff06f jal x0, -10 + 15019500 15004 1c001804 00c79363 bne x15, x12, 6 x15:10c00009 x12:10c00048 + 15022500 15007 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0000a x11:00000000 x15:10c00009 PA:10c00009 + 15042500 15027 1c00180e ff7ff06f jal x0, -10 + 15043500 15028 1c001804 00c79363 bne x15, x12, 6 x15:10c0000a x12:10c00048 + 15046500 15031 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0000b x11:00000000 x15:10c0000a PA:10c0000a + 15066500 15051 1c00180e ff7ff06f jal x0, -10 + 15067500 15052 1c001804 00c79363 bne x15, x12, 6 x15:10c0000b x12:10c00048 + 15070500 15055 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0000c x11:00000000 x15:10c0000b PA:10c0000b + 15090500 15075 1c00180e ff7ff06f jal x0, -10 + 15091500 15076 1c001804 00c79363 bne x15, x12, 6 x15:10c0000c x12:10c00048 + 15094500 15079 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0000d x11:00000000 x15:10c0000c PA:10c0000c + 15114500 15099 1c00180e ff7ff06f jal x0, -10 + 15115500 15100 1c001804 00c79363 bne x15, x12, 6 x15:10c0000d x12:10c00048 + 15118500 15103 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0000e x11:00000000 x15:10c0000d PA:10c0000d + 15138500 15123 1c00180e ff7ff06f jal x0, -10 + 15139500 15124 1c001804 00c79363 bne x15, x12, 6 x15:10c0000e x12:10c00048 + 15142500 15127 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0000f x11:00000000 x15:10c0000e PA:10c0000e + 15162500 15147 1c00180e ff7ff06f jal x0, -10 + 15163500 15148 1c001804 00c79363 bne x15, x12, 6 x15:10c0000f x12:10c00048 + 15166500 15151 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00010 x11:00000000 x15:10c0000f PA:10c0000f + 15186500 15171 1c00180e ff7ff06f jal x0, -10 + 15187500 15172 1c001804 00c79363 bne x15, x12, 6 x15:10c00010 x12:10c00048 + 15190500 15175 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00011 x11:00000000 x15:10c00010 PA:10c00010 + 15210500 15195 1c00180e ff7ff06f jal x0, -10 + 15211500 15196 1c001804 00c79363 bne x15, x12, 6 x15:10c00011 x12:10c00048 + 15214500 15199 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00012 x11:00000000 x15:10c00011 PA:10c00011 + 15234500 15219 1c00180e ff7ff06f jal x0, -10 + 15235500 15220 1c001804 00c79363 bne x15, x12, 6 x15:10c00012 x12:10c00048 + 15238500 15223 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00013 x11:00000000 x15:10c00012 PA:10c00012 + 15258500 15243 1c00180e ff7ff06f jal x0, -10 + 15259500 15244 1c001804 00c79363 bne x15, x12, 6 x15:10c00013 x12:10c00048 + 15262500 15247 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00014 x11:00000000 x15:10c00013 PA:10c00013 + 15282500 15267 1c00180e ff7ff06f jal x0, -10 + 15283500 15268 1c001804 00c79363 bne x15, x12, 6 x15:10c00014 x12:10c00048 + 15286500 15271 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00015 x11:00000000 x15:10c00014 PA:10c00014 + 15306500 15291 1c00180e ff7ff06f jal x0, -10 + 15307500 15292 1c001804 00c79363 bne x15, x12, 6 x15:10c00015 x12:10c00048 + 15310500 15295 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00016 x11:00000000 x15:10c00015 PA:10c00015 + 15330500 15315 1c00180e ff7ff06f jal x0, -10 + 15331500 15316 1c001804 00c79363 bne x15, x12, 6 x15:10c00016 x12:10c00048 + 15334500 15319 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00017 x11:00000000 x15:10c00016 PA:10c00016 + 15354500 15339 1c00180e ff7ff06f jal x0, -10 + 15355500 15340 1c001804 00c79363 bne x15, x12, 6 x15:10c00017 x12:10c00048 + 15358500 15343 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00018 x11:00000000 x15:10c00017 PA:10c00017 + 15378500 15363 1c00180e ff7ff06f jal x0, -10 + 15379500 15364 1c001804 00c79363 bne x15, x12, 6 x15:10c00018 x12:10c00048 + 15382500 15367 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00019 x11:00000000 x15:10c00018 PA:10c00018 + 15402500 15387 1c00180e ff7ff06f jal x0, -10 + 15403500 15388 1c001804 00c79363 bne x15, x12, 6 x15:10c00019 x12:10c00048 + 15406500 15391 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0001a x11:00000000 x15:10c00019 PA:10c00019 + 15426500 15411 1c00180e ff7ff06f jal x0, -10 + 15427500 15412 1c001804 00c79363 bne x15, x12, 6 x15:10c0001a x12:10c00048 + 15430500 15415 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0001b x11:00000000 x15:10c0001a PA:10c0001a + 15450500 15435 1c00180e ff7ff06f jal x0, -10 + 15451500 15436 1c001804 00c79363 bne x15, x12, 6 x15:10c0001b x12:10c00048 + 15454500 15439 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0001c x11:00000000 x15:10c0001b PA:10c0001b + 15474500 15459 1c00180e ff7ff06f jal x0, -10 + 15475500 15460 1c001804 00c79363 bne x15, x12, 6 x15:10c0001c x12:10c00048 + 15478500 15463 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0001d x11:00000000 x15:10c0001c PA:10c0001c + 15498500 15483 1c00180e ff7ff06f jal x0, -10 + 15499500 15484 1c001804 00c79363 bne x15, x12, 6 x15:10c0001d x12:10c00048 + 15502500 15487 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0001e x11:00000000 x15:10c0001d PA:10c0001d + 15522500 15507 1c00180e ff7ff06f jal x0, -10 + 15523500 15508 1c001804 00c79363 bne x15, x12, 6 x15:10c0001e x12:10c00048 + 15526500 15511 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0001f x11:00000000 x15:10c0001e PA:10c0001e + 15546500 15531 1c00180e ff7ff06f jal x0, -10 + 15547500 15532 1c001804 00c79363 bne x15, x12, 6 x15:10c0001f x12:10c00048 + 15550500 15535 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00020 x11:00000000 x15:10c0001f PA:10c0001f + 15570500 15555 1c00180e ff7ff06f jal x0, -10 + 15571500 15556 1c001804 00c79363 bne x15, x12, 6 x15:10c00020 x12:10c00048 + 15574500 15559 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00021 x11:00000000 x15:10c00020 PA:10c00020 + 15594500 15579 1c00180e ff7ff06f jal x0, -10 + 15595500 15580 1c001804 00c79363 bne x15, x12, 6 x15:10c00021 x12:10c00048 + 15598500 15583 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00022 x11:00000000 x15:10c00021 PA:10c00021 + 15618500 15603 1c00180e ff7ff06f jal x0, -10 + 15619500 15604 1c001804 00c79363 bne x15, x12, 6 x15:10c00022 x12:10c00048 + 15622500 15607 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00023 x11:00000000 x15:10c00022 PA:10c00022 + 15642500 15627 1c00180e ff7ff06f jal x0, -10 + 15643500 15628 1c001804 00c79363 bne x15, x12, 6 x15:10c00023 x12:10c00048 + 15646500 15631 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00024 x11:00000000 x15:10c00023 PA:10c00023 + 15666500 15651 1c00180e ff7ff06f jal x0, -10 + 15667500 15652 1c001804 00c79363 bne x15, x12, 6 x15:10c00024 x12:10c00048 + 15670500 15655 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00025 x11:00000000 x15:10c00024 PA:10c00024 + 15690500 15675 1c00180e ff7ff06f jal x0, -10 + 15691500 15676 1c001804 00c79363 bne x15, x12, 6 x15:10c00025 x12:10c00048 + 15694500 15679 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00026 x11:00000000 x15:10c00025 PA:10c00025 + 15714500 15699 1c00180e ff7ff06f jal x0, -10 + 15715500 15700 1c001804 00c79363 bne x15, x12, 6 x15:10c00026 x12:10c00048 + 15718500 15703 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00027 x11:00000000 x15:10c00026 PA:10c00026 + 15738500 15723 1c00180e ff7ff06f jal x0, -10 + 15739500 15724 1c001804 00c79363 bne x15, x12, 6 x15:10c00027 x12:10c00048 + 15742500 15727 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00028 x11:00000000 x15:10c00027 PA:10c00027 + 15762500 15747 1c00180e ff7ff06f jal x0, -10 + 15763500 15748 1c001804 00c79363 bne x15, x12, 6 x15:10c00028 x12:10c00048 + 15766500 15751 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00029 x11:00000000 x15:10c00028 PA:10c00028 + 15786500 15771 1c00180e ff7ff06f jal x0, -10 + 15787500 15772 1c001804 00c79363 bne x15, x12, 6 x15:10c00029 x12:10c00048 + 15790500 15775 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0002a x11:00000000 x15:10c00029 PA:10c00029 + 15810500 15795 1c00180e ff7ff06f jal x0, -10 + 15811500 15796 1c001804 00c79363 bne x15, x12, 6 x15:10c0002a x12:10c00048 + 15814500 15799 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0002b x11:00000000 x15:10c0002a PA:10c0002a + 15834500 15819 1c00180e ff7ff06f jal x0, -10 + 15835500 15820 1c001804 00c79363 bne x15, x12, 6 x15:10c0002b x12:10c00048 + 15838500 15823 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0002c x11:00000000 x15:10c0002b PA:10c0002b + 15858500 15843 1c00180e ff7ff06f jal x0, -10 + 15859500 15844 1c001804 00c79363 bne x15, x12, 6 x15:10c0002c x12:10c00048 + 15862500 15847 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0002d x11:00000000 x15:10c0002c PA:10c0002c + 15882500 15867 1c00180e ff7ff06f jal x0, -10 + 15883500 15868 1c001804 00c79363 bne x15, x12, 6 x15:10c0002d x12:10c00048 + 15886500 15871 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0002e x11:00000000 x15:10c0002d PA:10c0002d + 15906500 15891 1c00180e ff7ff06f jal x0, -10 + 15907500 15892 1c001804 00c79363 bne x15, x12, 6 x15:10c0002e x12:10c00048 + 15910500 15895 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0002f x11:00000000 x15:10c0002e PA:10c0002e + 15930500 15915 1c00180e ff7ff06f jal x0, -10 + 15931500 15916 1c001804 00c79363 bne x15, x12, 6 x15:10c0002f x12:10c00048 + 15934500 15919 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00030 x11:00000000 x15:10c0002f PA:10c0002f + 15954500 15939 1c00180e ff7ff06f jal x0, -10 + 15955500 15940 1c001804 00c79363 bne x15, x12, 6 x15:10c00030 x12:10c00048 + 15958500 15943 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00031 x11:00000000 x15:10c00030 PA:10c00030 + 15978500 15963 1c00180e ff7ff06f jal x0, -10 + 15979500 15964 1c001804 00c79363 bne x15, x12, 6 x15:10c00031 x12:10c00048 + 15982500 15967 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00032 x11:00000000 x15:10c00031 PA:10c00031 + 16002500 15987 1c00180e ff7ff06f jal x0, -10 + 16003500 15988 1c001804 00c79363 bne x15, x12, 6 x15:10c00032 x12:10c00048 + 16006500 15991 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00033 x11:00000000 x15:10c00032 PA:10c00032 + 16026500 16011 1c00180e ff7ff06f jal x0, -10 + 16027500 16012 1c001804 00c79363 bne x15, x12, 6 x15:10c00033 x12:10c00048 + 16030500 16015 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00034 x11:00000000 x15:10c00033 PA:10c00033 + 16050500 16035 1c00180e ff7ff06f jal x0, -10 + 16051500 16036 1c001804 00c79363 bne x15, x12, 6 x15:10c00034 x12:10c00048 + 16054500 16039 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00035 x11:00000000 x15:10c00034 PA:10c00034 + 16074500 16059 1c00180e ff7ff06f jal x0, -10 + 16075500 16060 1c001804 00c79363 bne x15, x12, 6 x15:10c00035 x12:10c00048 + 16078500 16063 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00036 x11:00000000 x15:10c00035 PA:10c00035 + 16098500 16083 1c00180e ff7ff06f jal x0, -10 + 16099500 16084 1c001804 00c79363 bne x15, x12, 6 x15:10c00036 x12:10c00048 + 16102500 16087 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00037 x11:00000000 x15:10c00036 PA:10c00036 + 16122500 16107 1c00180e ff7ff06f jal x0, -10 + 16123500 16108 1c001804 00c79363 bne x15, x12, 6 x15:10c00037 x12:10c00048 + 16126500 16111 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00038 x11:00000000 x15:10c00037 PA:10c00037 + 16146500 16131 1c00180e ff7ff06f jal x0, -10 + 16147500 16132 1c001804 00c79363 bne x15, x12, 6 x15:10c00038 x12:10c00048 + 16150500 16135 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00039 x11:00000000 x15:10c00038 PA:10c00038 + 16170500 16155 1c00180e ff7ff06f jal x0, -10 + 16171500 16156 1c001804 00c79363 bne x15, x12, 6 x15:10c00039 x12:10c00048 + 16174500 16159 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0003a x11:00000000 x15:10c00039 PA:10c00039 + 16194500 16179 1c00180e ff7ff06f jal x0, -10 + 16195500 16180 1c001804 00c79363 bne x15, x12, 6 x15:10c0003a x12:10c00048 + 16198500 16183 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0003b x11:00000000 x15:10c0003a PA:10c0003a + 16218500 16203 1c00180e ff7ff06f jal x0, -10 + 16219500 16204 1c001804 00c79363 bne x15, x12, 6 x15:10c0003b x12:10c00048 + 16222500 16207 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0003c x11:00000000 x15:10c0003b PA:10c0003b + 16242500 16227 1c00180e ff7ff06f jal x0, -10 + 16243500 16228 1c001804 00c79363 bne x15, x12, 6 x15:10c0003c x12:10c00048 + 16246500 16231 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0003d x11:00000000 x15:10c0003c PA:10c0003c + 16266500 16251 1c00180e ff7ff06f jal x0, -10 + 16267500 16252 1c001804 00c79363 bne x15, x12, 6 x15:10c0003d x12:10c00048 + 16270500 16255 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0003e x11:00000000 x15:10c0003d PA:10c0003d + 16290500 16275 1c00180e ff7ff06f jal x0, -10 + 16291500 16276 1c001804 00c79363 bne x15, x12, 6 x15:10c0003e x12:10c00048 + 16294500 16279 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c0003f x11:00000000 x15:10c0003e PA:10c0003e + 16314500 16299 1c00180e ff7ff06f jal x0, -10 + 16315500 16300 1c001804 00c79363 bne x15, x12, 6 x15:10c0003f x12:10c00048 + 16318500 16303 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00040 x11:00000000 x15:10c0003f PA:10c0003f + 16338500 16323 1c00180e ff7ff06f jal x0, -10 + 16339500 16324 1c001804 00c79363 bne x15, x12, 6 x15:10c00040 x12:10c00048 + 16342500 16327 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00041 x11:00000000 x15:10c00040 PA:10c00040 + 16362500 16347 1c00180e ff7ff06f jal x0, -10 + 16363500 16348 1c001804 00c79363 bne x15, x12, 6 x15:10c00041 x12:10c00048 + 16366500 16351 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00042 x11:00000000 x15:10c00041 PA:10c00041 + 16386500 16371 1c00180e ff7ff06f jal x0, -10 + 16387500 16372 1c001804 00c79363 bne x15, x12, 6 x15:10c00042 x12:10c00048 + 16390500 16375 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00043 x11:00000000 x15:10c00042 PA:10c00042 + 16410500 16395 1c00180e ff7ff06f jal x0, -10 + 16411500 16396 1c001804 00c79363 bne x15, x12, 6 x15:10c00043 x12:10c00048 + 16414500 16399 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00044 x11:00000000 x15:10c00043 PA:10c00043 + 16434500 16419 1c00180e ff7ff06f jal x0, -10 + 16435500 16420 1c001804 00c79363 bne x15, x12, 6 x15:10c00044 x12:10c00048 + 16438500 16423 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00045 x11:00000000 x15:10c00044 PA:10c00044 + 16458500 16443 1c00180e ff7ff06f jal x0, -10 + 16459500 16444 1c001804 00c79363 bne x15, x12, 6 x15:10c00045 x12:10c00048 + 16462500 16447 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00046 x11:00000000 x15:10c00045 PA:10c00045 + 16482500 16467 1c00180e ff7ff06f jal x0, -10 + 16483500 16468 1c001804 00c79363 bne x15, x12, 6 x15:10c00046 x12:10c00048 + 16486500 16471 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00047 x11:00000000 x15:10c00046 PA:10c00046 + 16506500 16491 1c00180e ff7ff06f jal x0, -10 + 16507500 16492 1c001804 00c79363 bne x15, x12, 6 x15:10c00047 x12:10c00048 + 16510500 16495 1c00180a 00b780ab p.sb x11, 1(x15!) x15=10c00048 x11:00000000 x15:10c00047 PA:10c00047 + 16530500 16515 1c00180e ff7ff06f jal x0, -10 + 16531500 16516 1c001804 00c79363 bne x15, x12, 6 x15:10c00048 x12:10c00048 + 16532500 16517 1c001808 00008067 jalr x0, x1, 0 x1:1c0012fc + 16534500 16519 1c0012fc 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 16535500 16520 1c001300 6a87a783 lw x15, 1704(x15) x15=1c2fff50 x15:1c002000 PA:1c0026a8 + 16549500 16534 1c001304 01800713 addi x14, x0, 24 x14=00000018 + 16550500 16535 1c001306 00c12083 lw x1, 12(x2) x1=1c001406 x2:10000930 PA:1000093c + 16551500 16536 1c001308 42e487b3 p.mac x15, x9, x14 x15=1c2fff98 x15:1c2fff50 x9:00000003 x14:00000018 + 16552500 16537 1c00130c 00201737 lui x14, 0x201000 x14=00201000 + 16553500 16538 1c001310 e0470713 addi x14, x14, -508 x14=00200e04 x14:00201000 + 16554500 16539 1c001314 00e40433 add x8, x8, x14 x8=10e00e04 x8:10c00000 x14:00200e04 + 16555500 16540 1c001316 00412483 lw x9, 4(x2) x9=00000001 x2:10000930 PA:10000934 + 16556500 16541 1c001318 0087aa23 sw x8, 20(x15) x8:10e00e04 x15:1c2fff98 PA:1c2fffac + 16574500 16559 1c00131a 00812403 lw x8, 8(x2) x8=00000003 x2:10000930 PA:10000938 + 16575500 16560 1c00131c 0007a623 sw x0, 12(x15) x15:1c2fff98 PA:1c2fffa4 + 16593500 16578 1c001320 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 16594500 16579 1c001322 00008067 jalr x0, x1, 0 x1:1c001406 + 16596500 16581 1c001406 00800533 add x10, x0, x8 x10=00000003 x8:00000003 + 16597500 16582 1c001408 e0dff0ef jal x1, -500 x1=1c00140a + 16599500 16584 1c001214 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 16600500 16585 1c001218 69c7a703 lw x14, 1692(x15) x14=10000990 x15:1c002000 PA:1c00269c + 16614500 16599 1c00121c 100017b7 lui x15, 0x10001000 x15=10001000 + 16615500 16600 1c001220 01651593 slli x11, x10, 0x16 x11=00c00000 x10:00000003 + 16616500 16601 1c001224 000ff637 lui x12, 0xff000 x12=000ff000 + 16617500 16602 1c001228 00251513 slli x10, x10, 0x2 x10=0000000c x10:00000003 + 16618500 16603 1c00122a 99078793 addi x15, x15, -1648 x15=10000990 x15:10001000 + 16619500 16604 1c00122e 67060613 addi x12, x12, 1648 x12=000ff670 x12:000ff000 + 16620500 16605 1c001232 00f585b3 add x11, x11, x15 x11=10c00990 x11:00c00000 x15:10000990 + 16621500 16606 1c001234 00e50533 add x10, x10, x14 x10=1000099c x10:0000000c x14:10000990 + 16622500 16607 1c001236 efdff06f jal x0, -260 + 16624500 16609 1c001132 00758793 addi x15, x11, 7 x15=10c00997 x11:10c00990 + 16625500 16610 1c001136 c407b7b3 p.bclr x15, x15, 2, 0 x15=10c00990 x15:10c00997 + 16626500 16611 1c00113a 40b785b3 sub x11, x15, x11 x11=00000000 x15:10c00990 x11:10c00990 + 16627500 16612 1c00113e 00f52023 sw x15, 0(x10) x15:10c00990 x10:1000099c PA:1000099c + 16628500 16613 1c001140 40b60633 sub x12, x12, x11 x12=000ff670 x12:000ff670 x11:00000000 + 16629500 16614 1c001142 00c05763 bge x0, x12, 14 x12:000ff670 + 16630500 16615 1c001146 c4063633 p.bclr x12, x12, 2, 0 x12=000ff670 x12:000ff670 + 16631500 16616 1c00114a 00c7a023 sw x12, 0(x15) x12:000ff670 x15:10c00990 PA:10c00990 + 16651500 16636 1c00114c 0007a223 sw x0, 4(x15) x15:10c00990 PA:10c00994 + 16671500 16656 1c001150 00008067 jalr x0, x1, 0 x1:1c00140a + 16672500 16657 1c00140a 6a8aa783 lw x15, 1704(x21) x15=1c2fff50 x21:1c002000 PA:1c0026a8 + 16686500 16671 1c00140e 04040413 addi x8, x8, 64 x8=00000043 x8:00000003 + 16687500 16672 1c001412 01641413 slli x8, x8, 0x16 x8=10c00000 x8:00000043 + 16688500 16673 1c001414 00fa0a33 add x20, x20, x15 x20=1c2fff98 x20:00000048 x15:1c2fff50 + 16689500 16674 1c001416 002017b7 lui x15, 0x201000 x15=00201000 + 16690500 16675 1c00141a 40078793 addi x15, x15, 1024 x15=00201400 x15:00201000 + 16691500 16676 1c00141e fff00713 addi x14, x0, -1 x14=ffffffff + 16692500 16677 1c001420 000a2223 sw x0, 4(x20) x20:1c2fff98 PA:1c2fff9c + 16710500 16695 1c001424 00e467a3 p.sw x14, x0(x8) x14:ffffffff x8:10c00000 PA:10e01400 + 16736500 16721 1c001428 00c12683 lw x13, 12(x2) x13=100fc720 x2:10000940 PA:1000094c + 16737500 16722 1c00142a 002007b7 lui x15, 0x200000 x15=00200000 + 16738500 16723 1c00142e 1c000737 lui x14, 0x1c000000 x14=1c000000 + 16739500 16724 1c001432 04078793 addi x15, x15, 64 x15=00200040 x15:00200000 + 16740500 16725 1c001436 08070713 addi x14, x14, 128 x14=1c000080 x14:1c000000 + 16741500 16726 1c00143a 008787b3 add x15, x15, x8 x15=10e00040 x15:00200040 x8:10c00000 + 16742500 16727 1c00143c 00000613 addi x12, x0, 0 x12=00000000 + 16743500 16728 1c00143e ce073733 p.bclr x14, x14, 7, 0 x14=1c000000 x14:1c000080 + 16744500 16729 1c001442 01364963 blt x12, x19, 18 x12:00000000 x19:00000008 + 16747500 16732 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e00044 x14:1c000000 x15:10e00040 PA:10e00040 + 16770500 16755 1c001458 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 16771500 16756 1c00145a fe9ff06f jal x0, -24 + 16773500 16758 1c001442 01364963 blt x12, x19, 18 x12:00000001 x19:00000008 + 16776500 16761 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e00048 x14:1c000000 x15:10e00044 PA:10e00044 + 16799500 16784 1c001458 00160613 addi x12, x12, 1 x12=00000002 x12:00000001 + 16800500 16785 1c00145a fe9ff06f jal x0, -24 + 16802500 16787 1c001442 01364963 blt x12, x19, 18 x12:00000002 x19:00000008 + 16805500 16790 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e0004c x14:1c000000 x15:10e00048 PA:10e00048 + 16828500 16813 1c001458 00160613 addi x12, x12, 1 x12=00000003 x12:00000002 + 16829500 16814 1c00145a fe9ff06f jal x0, -24 + 16831500 16816 1c001442 01364963 blt x12, x19, 18 x12:00000003 x19:00000008 + 16834500 16819 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e00050 x14:1c000000 x15:10e0004c PA:10e0004c + 16857500 16842 1c001458 00160613 addi x12, x12, 1 x12=00000004 x12:00000003 + 16858500 16843 1c00145a fe9ff06f jal x0, -24 + 16860500 16845 1c001442 01364963 blt x12, x19, 18 x12:00000004 x19:00000008 + 16863500 16848 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e00054 x14:1c000000 x15:10e00050 PA:10e00050 + 16886500 16871 1c001458 00160613 addi x12, x12, 1 x12=00000005 x12:00000004 + 16887500 16872 1c00145a fe9ff06f jal x0, -24 + 16889500 16874 1c001442 01364963 blt x12, x19, 18 x12:00000005 x19:00000008 + 16892500 16877 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e00058 x14:1c000000 x15:10e00054 PA:10e00054 + 16915500 16900 1c001458 00160613 addi x12, x12, 1 x12=00000006 x12:00000005 + 16916500 16901 1c00145a fe9ff06f jal x0, -24 + 16918500 16903 1c001442 01364963 blt x12, x19, 18 x12:00000006 x19:00000008 + 16921500 16906 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e0005c x14:1c000000 x15:10e00058 PA:10e00058 + 16944500 16929 1c001458 00160613 addi x12, x12, 1 x12=00000007 x12:00000006 + 16945500 16930 1c00145a fe9ff06f jal x0, -24 + 16947500 16932 1c001442 01364963 blt x12, x19, 18 x12:00000007 x19:00000008 + 16950500 16935 1c001454 00e7a22b p.sw x14, 4(x15!) x15=10e00060 x14:1c000000 x15:10e0005c PA:10e0005c + 16973500 16958 1c001458 00160613 addi x12, x12, 1 x12=00000008 x12:00000007 + 16974500 16959 1c00145a fe9ff06f jal x0, -24 + 16976500 16961 1c001442 01364963 blt x12, x19, 18 x12:00000008 x19:00000008 + 16977500 16962 1c001446 002007b7 lui x15, 0x200000 x15=00200000 + 16978500 16963 1c00144a 00878793 addi x15, x15, 8 x15=00200008 x15:00200000 + 16979500 16964 1c00144c fff00713 addi x14, x0, -1 x14=ffffffff + 16980500 16965 1c00144e 00e467a3 p.sw x14, x0(x8) x14:ffffffff x8:10c00000 PA:10e00008 + 17003500 16988 1c001452 f85ff06f jal x0, -124 + 17004500 16989 1c0013d6 00068363 beq x13, x0, 6 x13:100fc720 + 17005500 16990 1c0013d8 00d00533 add x10, x0, x13 x10=100fc720 x13:100fc720 + 17006500 16991 1c0013da c1dff0ef jal x1, -996 x1=1c0013dc + 17008500 16993 1c000ff6 ff010113 addi x2, x2, -16 x2=10000930 x2:10000940 + 17009500 16994 1c000ff8 00112623 sw x1, 12(x2) x1:1c0013dc x2:10000930 PA:1000093c + 17010500 16995 1c000ffa 00812423 sw x8, 8(x2) x8:10c00000 x2:10000930 PA:10000938 + 17011500 16996 1c000ffc 30047473 csrrci x8, 0x00000008, 0x300 x8=00001800 + 17015500 17000 1c001000 00c52783 lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c + 17016500 17001 1c001002 00052423 sw x0, 8(x10) x10:100fc720 PA:100fc728 + 17017500 17002 1c001006 0007a703 lw x14, 0(x15) x14=100fc720 x15:1000013c PA:1000013c + 17019500 17004 1c001008 00071e63 bne x14, x0, 28 x14:100fc720 + 17022500 17007 1c001024 0047a703 lw x14, 4(x15) x14=100fc720 x15:1000013c PA:10000140 + 17024500 17009 1c001026 00a72423 sw x10, 8(x14) x10:100fc720 x14:100fc720 PA:100fc728 + 17025500 17010 1c001028 fe5ff06f jal x0, -28 + 17027500 17012 1c00100c 00a7a223 sw x10, 4(x15) x10:100fc720 x15:1000013c PA:10000140 + 17028500 17013 1c00100e 00c7a503 lw x10, 12(x15) x10=00000000 x15:1000013c PA:10000148 + 17030500 17015 1c001010 00050463 beq x10, x0, 8 x10:00000000 + 17033500 17018 1c001018 30041073 csrrw x0, x8, 0x300 x8:00001800 + 17037500 17022 1c00101c 00c12083 lw x1, 12(x2) x1=1c0013dc x2:10000930 PA:1000093c + 17038500 17023 1c00101e 00812403 lw x8, 8(x2) x8=10c00000 x2:10000930 PA:10000938 + 17039500 17024 1c001020 01010113 addi x2, x2, 16 x2=10000940 x2:10000930 + 17040500 17025 1c001022 00008067 jalr x0, x1, 0 x1:1c0013dc + 17042500 17027 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 17046500 17031 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000a7c x2:10000940 PA:1000096c + 17047500 17032 1c0013e2 02812403 lw x8, 40(x2) x8=00000004 x2:10000940 PA:10000968 + 17048500 17033 1c0013e4 02412483 lw x9, 36(x2) x9=100fc720 x2:10000940 PA:10000964 + 17049500 17034 1c0013e6 02012903 lw x18, 32(x2) x18=00000000 x2:10000940 PA:10000960 + 17050500 17035 1c0013e8 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 17051500 17036 1c0013ea 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 17052500 17037 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 17053500 17038 1c0013ee 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 17054500 17039 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000a7c + 17056500 17041 1c000a7c fe4439e3 p.bneimm x8, -14 x8:00000004 + 17057500 17042 1c000a80 00100413 addi x8, x0, 1 x8=00000001 + 17058500 17043 1c000a82 1c001937 lui x18, 0x1c001000 x18=1c001000 + 17059500 17044 1c000a86 008005b3 add x11, x0, x8 x11=00000001 x8:00000001 + 17060500 17045 1c000a88 00912023 sw x9, 0(x2) x9:100fc720 x2:10000970 PA:10000970 + 17061500 17046 1c000a8a 00140413 addi x8, x8, 1 x8=00000002 x8:00000001 + 17062500 17047 1c000a8c 00800893 addi x17, x0, 8 x17=00000008 + 17063500 17048 1c000a8e 00000813 addi x16, x0, 0 x16=00000000 + 17079500 17064 1c000a90 00000793 addi x15, x0, 0 x15=00000000 + 17080500 17065 1c000a92 00000713 addi x14, x0, 0 x14=00000000 + 17081500 17066 1c000a94 00000693 addi x13, x0, 0 x13=00000000 + 17082500 17067 1c000a96 9d890613 addi x12, x18, -1576 x12=1c0009d8 x18:1c001000 + 17083500 17068 1c000a9a 00000513 addi x10, x0, 0 x10=00000000 + 17084500 17069 1c000a9c 1fb000ef jal x1, 2554 x1=1c000aa0 + 17102500 17087 1c001496 fb010113 addi x2, x2, -80 x2=10000920 x2:10000970 + 17103500 17088 1c001498 03512a23 sw x21, 52(x2) x21:00000000 x2:10000920 PA:10000954 + 17104500 17089 1c00149a 05012a83 lw x21, 80(x2) x21=100fc720 x2:10000920 PA:10000970 + 17105500 17090 1c00149c 04912223 sw x9, 68(x2) x9:100fc720 x2:10000920 PA:10000964 + 17106500 17091 1c00149e 03312e23 sw x19, 60(x2) x19:00000000 x2:10000920 PA:1000095c + 17122500 17107 1c0014a0 03712623 sw x23, 44(x2) x23:00000000 x2:10000920 PA:1000094c + 17123500 17108 1c0014a2 03812423 sw x24, 40(x2) x24:00000000 x2:10000920 PA:10000948 + 17124500 17109 1c0014a4 03a12023 sw x26, 32(x2) x26:00000000 x2:10000920 PA:10000940 + 17125500 17110 1c0014a6 01b12e23 sw x27, 28(x2) x27:00000000 x2:10000920 PA:1000093c + 17126500 17111 1c0014a8 00c00c33 add x24, x0, x12 x24=1c0009d8 x12:1c0009d8 + 17127500 17112 1c0014aa 00b00db3 add x27, x0, x11 x27=00000001 x11:00000001 + 17128500 17113 1c0014ac 00d00bb3 add x23, x0, x13 x23=00000000 x13:00000000 + 17129500 17114 1c0014ae 00e00d33 add x26, x0, x14 x26=00000000 x14:00000000 + 17146500 17131 1c0014b0 00f004b3 add x9, x0, x15 x9=00000000 x15:00000000 + 17147500 17132 1c0014b2 010009b3 add x19, x0, x16 x19=00000000 x16:00000000 + 17148500 17133 1c0014b4 04112623 sw x1, 76(x2) x1:1c000aa0 x2:10000920 PA:1000096c + 17149500 17134 1c0014b6 04812423 sw x8, 72(x2) x8:00000002 x2:10000920 PA:10000968 + 17150500 17135 1c0014b8 05212023 sw x18, 64(x2) x18:1c001000 x2:10000920 PA:10000960 + 17151500 17136 1c0014ba 03412c23 sw x20, 56(x2) x20:00000000 x2:10000920 PA:10000958 + 17152500 17137 1c0014bc 03612823 sw x22, 48(x2) x22:00000000 x2:10000920 PA:10000950 + 17153500 17138 1c0014be 03912223 sw x25, 36(x2) x25:00000000 x2:10000920 PA:10000944 + 17170500 17155 1c0014c0 30047b73 csrrci x22, 0x00000008, 0x300 x22=00001808 + 17174500 17159 1c0014c4 01100933 add x18, x0, x17 x18=00000008 x17:00000008 + 17175500 17160 1c0014c6 00089463 bne x17, x0, 8 x17:00000008 + 17195500 17180 1c0014ce 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 17196500 17181 1c0014d2 6a87ac83 lw x25, 1704(x15) x25=1c2fff50 x15:1c002000 PA:1c0026a8 + 17210500 17195 1c0014d6 01800793 addi x15, x0, 24 x15=00000018 + 17211500 17196 1c0014d8 040d8a13 addi x20, x27, 64 x20=00000041 x27:00000001 + 17212500 17197 1c0014dc 42fd8cb3 p.mac x25, x27, x15 x25=1c2fff68 x25:1c2fff50 x27:00000001 x15:00000018 + 17229500 17214 1c0014e0 1b000737 lui x14, 0x1b000000 x14=1b000000 + 17230500 17215 1c0014e4 000016b7 lui x13, 0x1000 x13=00001000 + 17231500 17216 1c0014e6 016a1a13 slli x20, x20, 0x16 x20=10400000 x20:00000041 + 17232500 17217 1c0014e8 00870713 addi x14, x14, 8 x14=1b000008 x14:1b000000 + 17233500 17218 1c0014ec fff68693 addi x13, x13, -1 x13=00000fff x13:00001000 + 17250500 17235 1c0014ee 004ca783 lw x15, 4(x25) x15=00000000 x25:1c2fff68 PA:1c2fff6c + 17265500 17250 1c0014f2 00579413 slli x8, x15, 0x5 x8=00000000 x15:00000000 + 17266500 17251 1c0014f6 00e40433 add x8, x8, x14 x8=1b000008 x8:00000000 x14:1b000008 + 17267500 17252 1c0014f8 00d47433 and x8, x8, x13 x8=00000008 x8:1b000008 x13:00000fff + 17268500 17253 1c0014fa 01440433 add x8, x8, x20 x8=10400008 x8:00000008 x20:10400000 + 17269500 17254 1c0014fc 00042603 lw x12, 0(x8) x12=00000000 x8:10400008 PA:10400008 + 17288500 17273 1c0014fe 00060763 beq x12, x0, 14 x12:00000000 + 17291500 17276 1c00150c 00cca583 lw x11, 12(x25) x11=00000000 x25:1c2fff68 PA:1c2fff74 + 17310500 17295 1c001510 0017c793 xori x15, x15, 1 x15=00000001 x15:00000000 + 17311500 17296 1c001514 00fca223 sw x15, 4(x25) x15:00000001 x25:1c2fff68 PA:1c2fff6c + 17329500 17314 1c001518 00058863 beq x11, x0, 16 x11:00000000 + 17348500 17333 1c001528 00049363 bne x9, x0, 6 x9:00000000 + 17349500 17334 1c00152a 40000493 addi x9, x0, 1024 x9=00000400 + 17366500 17351 1c00152e 00099463 bne x19, x0, 8 x19:00000000 + 17367500 17352 1c001532 40000993 addi x19, x0, 1024 x19=00000400 + 17368500 17353 1c001536 020d1163 bne x26, x0, 34 x26:00000000 + 17369500 17354 1c00153a fff90793 addi x15, x18, -1 x15=00000007 x18:00000008 + 17370500 17355 1c00153e 009005b3 add x11, x0, x9 x11=00000400 x9:00000400 + 17387500 17372 1c001540 433785b3 p.mac x11, x15, x19 x11=00002000 x11:00000400 x15:00000007 x19:00000400 + 17388500 17373 1c001544 002d8513 addi x10, x27, 2 x10=00000003 x27:00000001 + 17389500 17374 1c001548 fff00d93 addi x27, x0, -1 x27=ffffffff + 17390500 17375 1c00154a 00bca823 sw x11, 16(x25) x11:00002000 x25:1c2fff68 PA:1c2fff78 + 17408500 17393 1c00154e c83ff0ef jal x1, -894 x1=1c001550 + 17409500 17394 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 17410500 17395 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000003 + 17411500 17396 1c0011d6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 17412500 17397 1c0011da 69c7a783 lw x15, 1692(x15) x15=10000990 x15:1c002000 PA:1c00269c + 17426500 17411 1c0011de ffe50513 addi x10, x10, -2 x10=00000001 x10:00000003 + 17427500 17412 1c0011e0 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 17428500 17413 1c0011e2 00f50533 add x10, x10, x15 x10=10000994 x10:00000004 x15:10000990 + 17429500 17414 1c0011e4 f6fff06f jal x0, -146 + 17431500 17416 1c001152 00052783 lw x15, 0(x10) x15=10400990 x10:10000994 PA:10000994 + 17432500 17417 1c001154 00758593 addi x11, x11, 7 x11=00002007 x11:00002000 + 17433500 17418 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00002000 x11:00002007 + 17434500 17419 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 17435500 17420 1c00115c 00078963 beq x15, x0, 18 x15:10400990 + 17436500 17421 1c00115e 0007a703 lw x14, 0(x15) x14=000ff670 x15:10400990 PA:10400990 + 17454500 17439 1c001160 00b74963 blt x14, x11, 18 x14:000ff670 x11:00002000 + 17455500 17440 1c001164 00b71c63 bne x14, x11, 24 x14:000ff670 x11:00002000 + 17458500 17443 1c00117c 40b70733 sub x14, x14, x11 x14=000fd670 x14:000ff670 x11:00002000 + 17459500 17444 1c00117e 00e7a023 sw x14, 0(x15) x14:000fd670 x15:10400990 PA:10400990 + 17479500 17464 1c001180 00e787b3 add x15, x15, x14 x15=104fe000 x15:10400990 x14:000fd670 + 17480500 17465 1c001182 fedff06f jal x0, -20 + 17482500 17467 1c00116e 00f00533 add x10, x0, x15 x10=104fe000 x15:104fe000 + 17483500 17468 1c001170 00008067 jalr x0, x1, 0 x1:1c001550 + 17485500 17470 1c001550 00a00d33 add x26, x0, x10 x26=104fe000 x10:104fe000 + 17486500 17471 1c001552 04050063 beq x10, x0, 64 x10:104fe000 + 17487500 17472 1c001554 00aca623 sw x10, 12(x25) x10:104fe000 x25:1c2fff68 PA:1c2fff74 + 17505500 17490 1c001558 01500533 add x10, x0, x21 x10=100fc720 x21:100fc720 + 17506500 17491 1c00155a 000a9363 bne x21, x0, 6 x21:100fc720 + 17525500 17510 1c001560 00c52783 lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c + 17526500 17511 1c001562 009d0733 add x14, x26, x9 x14=104fe400 x26:104fe000 x9:00000400 + 17527500 17512 1c001566 01842223 sw x24, 4(x8) x24:1c0009d8 x8:10400008 PA:1040000c + 17547500 17532 1c00156a 01742423 sw x23, 8(x8) x23:00000000 x8:10400008 PA:10400010 + 17567500 17552 1c00156e 00e42623 sw x14, 12(x8) x14:104fe400 x8:10400008 PA:10400014 + 17587500 17572 1c001570 00942823 sw x9, 16(x8) x9:00000400 x8:10400008 PA:10400018 + 17607500 17592 1c001572 01342a23 sw x19, 20(x8) x19:00000400 x8:10400008 PA:1040001c + 17627500 17612 1c001576 00a42c23 sw x10, 24(x8) x10:100fc720 x8:10400008 PA:10400020 + 17647500 17632 1c001578 00f42e23 sw x15, 28(x8) x15:1000013c x8:10400008 PA:10400024 + 17667500 17652 1c00157a 002017b7 lui x15, 0x201000 x15=00201000 + 17668500 17653 1c00157e 01242023 sw x18, 0(x8) x18:00000008 x8:10400008 PA:10400008 + 17688500 17673 1c001582 e0478793 addi x15, x15, -508 x15=00200e04 x15:00201000 + 17689500 17674 1c001586 000a67a3 p.sw x0, x0(x20) x20:10400000 PA:10600e04 + 17712500 17697 1c00158a 00000d93 addi x27, x0, 0 x27=00000000 + 17713500 17698 1c00158c 000a9363 bne x21, x0, 6 x21:100fc720 + 17716500 17701 1c001592 300b1073 csrrw x0, x22, 0x300 x22:00001808 + 17720500 17705 1c001596 04c12083 lw x1, 76(x2) x1=1c000aa0 x2:10000920 PA:1000096c + 17721500 17706 1c001598 04812403 lw x8, 72(x2) x8=00000002 x2:10000920 PA:10000968 + 17722500 17707 1c00159a 01b00533 add x10, x0, x27 x10=00000000 x27:00000000 + 17723500 17708 1c00159c 04412483 lw x9, 68(x2) x9=100fc720 x2:10000920 PA:10000964 + 17724500 17709 1c00159e 04012903 lw x18, 64(x2) x18=1c001000 x2:10000920 PA:10000960 + 17740500 17725 1c0015a0 03c12983 lw x19, 60(x2) x19=00000000 x2:10000920 PA:1000095c + 17741500 17726 1c0015a2 03812a03 lw x20, 56(x2) x20=00000000 x2:10000920 PA:10000958 + 17742500 17727 1c0015a4 03412a83 lw x21, 52(x2) x21=00000000 x2:10000920 PA:10000954 + 17743500 17728 1c0015a6 03012b03 lw x22, 48(x2) x22=00000000 x2:10000920 PA:10000950 + 17744500 17729 1c0015a8 02c12b83 lw x23, 44(x2) x23=00000000 x2:10000920 PA:1000094c + 17745500 17730 1c0015aa 02812c03 lw x24, 40(x2) x24=00000000 x2:10000920 PA:10000948 + 17746500 17731 1c0015ac 02412c83 lw x25, 36(x2) x25=00000000 x2:10000920 PA:10000944 + 17747500 17732 1c0015ae 02012d03 lw x26, 32(x2) x26=00000000 x2:10000920 PA:10000940 + 17748500 17733 1c0015b0 01c12d83 lw x27, 28(x2) x27=00000000 x2:10000920 PA:1000093c + 17749500 17734 1c0015b2 05010113 addi x2, x2, 80 x2=10000970 x2:10000920 + 17750500 17735 1c0015b4 00008067 jalr x0, x1, 0 x1:1c000aa0 + 17752500 17737 1c000aa0 fe4433e3 p.bneimm x8, -26 x8:00000002 + 17755500 17740 1c000a86 008005b3 add x11, x0, x8 x11=00000002 x8:00000002 + 17756500 17741 1c000a88 00912023 sw x9, 0(x2) x9:100fc720 x2:10000970 PA:10000970 + 17757500 17742 1c000a8a 00140413 addi x8, x8, 1 x8=00000003 x8:00000002 + 17758500 17743 1c000a8c 00800893 addi x17, x0, 8 x17=00000008 + 17759500 17744 1c000a8e 00000813 addi x16, x0, 0 x16=00000000 + 17760500 17745 1c000a90 00000793 addi x15, x0, 0 x15=00000000 + 17761500 17746 1c000a92 00000713 addi x14, x0, 0 x14=00000000 + 17762500 17747 1c000a94 00000693 addi x13, x0, 0 x13=00000000 + 17763500 17748 1c000a96 9d890613 addi x12, x18, -1576 x12=1c0009d8 x18:1c001000 + 17764500 17749 1c000a9a 00000513 addi x10, x0, 0 x10=00000000 + 17765500 17750 1c000a9c 1fb000ef jal x1, 2554 x1=1c000aa0 + 17767500 17752 1c001496 fb010113 addi x2, x2, -80 x2=10000920 x2:10000970 + 17768500 17753 1c001498 03512a23 sw x21, 52(x2) x21:00000000 x2:10000920 PA:10000954 + 17769500 17754 1c00149a 05012a83 lw x21, 80(x2) x21=100fc720 x2:10000920 PA:10000970 + 17770500 17755 1c00149c 04912223 sw x9, 68(x2) x9:100fc720 x2:10000920 PA:10000964 + 17771500 17756 1c00149e 03312e23 sw x19, 60(x2) x19:00000000 x2:10000920 PA:1000095c + 17772500 17757 1c0014a0 03712623 sw x23, 44(x2) x23:00000000 x2:10000920 PA:1000094c + 17773500 17758 1c0014a2 03812423 sw x24, 40(x2) x24:00000000 x2:10000920 PA:10000948 + 17774500 17759 1c0014a4 03a12023 sw x26, 32(x2) x26:00000000 x2:10000920 PA:10000940 + 17775500 17760 1c0014a6 01b12e23 sw x27, 28(x2) x27:00000000 x2:10000920 PA:1000093c + 17776500 17761 1c0014a8 00c00c33 add x24, x0, x12 x24=1c0009d8 x12:1c0009d8 + 17777500 17762 1c0014aa 00b00db3 add x27, x0, x11 x27=00000002 x11:00000002 + 17778500 17763 1c0014ac 00d00bb3 add x23, x0, x13 x23=00000000 x13:00000000 + 17779500 17764 1c0014ae 00e00d33 add x26, x0, x14 x26=00000000 x14:00000000 + 17780500 17765 1c0014b0 00f004b3 add x9, x0, x15 x9=00000000 x15:00000000 + 17781500 17766 1c0014b2 010009b3 add x19, x0, x16 x19=00000000 x16:00000000 + 17782500 17767 1c0014b4 04112623 sw x1, 76(x2) x1:1c000aa0 x2:10000920 PA:1000096c + 17783500 17768 1c0014b6 04812423 sw x8, 72(x2) x8:00000003 x2:10000920 PA:10000968 + 17784500 17769 1c0014b8 05212023 sw x18, 64(x2) x18:1c001000 x2:10000920 PA:10000960 + 17785500 17770 1c0014ba 03412c23 sw x20, 56(x2) x20:00000000 x2:10000920 PA:10000958 + 17786500 17771 1c0014bc 03612823 sw x22, 48(x2) x22:00000000 x2:10000920 PA:10000950 + 17787500 17772 1c0014be 03912223 sw x25, 36(x2) x25:00000000 x2:10000920 PA:10000944 + 17788500 17773 1c0014c0 30047b73 csrrci x22, 0x00000008, 0x300 x22=00001808 + 17792500 17777 1c0014c4 01100933 add x18, x0, x17 x18=00000008 x17:00000008 + 17793500 17778 1c0014c6 00089463 bne x17, x0, 8 x17:00000008 + 17797500 17782 1c0014ce 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 17798500 17783 1c0014d2 6a87ac83 lw x25, 1704(x15) x25=1c2fff50 x15:1c002000 PA:1c0026a8 + 17813500 17798 1c0014d6 01800793 addi x15, x0, 24 x15=00000018 + 17814500 17799 1c0014d8 040d8a13 addi x20, x27, 64 x20=00000042 x27:00000002 + 17815500 17800 1c0014dc 42fd8cb3 p.mac x25, x27, x15 x25=1c2fff80 x25:1c2fff50 x27:00000002 x15:00000018 + 17816500 17801 1c0014e0 1b000737 lui x14, 0x1b000000 x14=1b000000 + 17817500 17802 1c0014e4 000016b7 lui x13, 0x1000 x13=00001000 + 17818500 17803 1c0014e6 016a1a13 slli x20, x20, 0x16 x20=10800000 x20:00000042 + 17819500 17804 1c0014e8 00870713 addi x14, x14, 8 x14=1b000008 x14:1b000000 + 17820500 17805 1c0014ec fff68693 addi x13, x13, -1 x13=00000fff x13:00001000 + 17821500 17806 1c0014ee 004ca783 lw x15, 4(x25) x15=00000000 x25:1c2fff80 PA:1c2fff84 + 17836500 17821 1c0014f2 00579413 slli x8, x15, 0x5 x8=00000000 x15:00000000 + 17837500 17822 1c0014f6 00e40433 add x8, x8, x14 x8=1b000008 x8:00000000 x14:1b000008 + 17838500 17823 1c0014f8 00d47433 and x8, x8, x13 x8=00000008 x8:1b000008 x13:00000fff + 17839500 17824 1c0014fa 01440433 add x8, x8, x20 x8=10800008 x8:00000008 x20:10800000 + 17840500 17825 1c0014fc 00042603 lw x12, 0(x8) x12=00000000 x8:10800008 PA:10800008 + 17858500 17843 1c0014fe 00060763 beq x12, x0, 14 x12:00000000 + 17861500 17846 1c00150c 00cca583 lw x11, 12(x25) x11=00000000 x25:1c2fff80 PA:1c2fff8c + 17875500 17860 1c001510 0017c793 xori x15, x15, 1 x15=00000001 x15:00000000 + 17876500 17861 1c001514 00fca223 sw x15, 4(x25) x15:00000001 x25:1c2fff80 PA:1c2fff84 + 17894500 17879 1c001518 00058863 beq x11, x0, 16 x11:00000000 + 17897500 17882 1c001528 00049363 bne x9, x0, 6 x9:00000000 + 17898500 17883 1c00152a 40000493 addi x9, x0, 1024 x9=00000400 + 17899500 17884 1c00152e 00099463 bne x19, x0, 8 x19:00000000 + 17900500 17885 1c001532 40000993 addi x19, x0, 1024 x19=00000400 + 17901500 17886 1c001536 020d1163 bne x26, x0, 34 x26:00000000 + 17902500 17887 1c00153a fff90793 addi x15, x18, -1 x15=00000007 x18:00000008 + 17903500 17888 1c00153e 009005b3 add x11, x0, x9 x11=00000400 x9:00000400 + 17904500 17889 1c001540 433785b3 p.mac x11, x15, x19 x11=00002000 x11:00000400 x15:00000007 x19:00000400 + 17905500 17890 1c001544 002d8513 addi x10, x27, 2 x10=00000004 x27:00000002 + 17906500 17891 1c001548 fff00d93 addi x27, x0, -1 x27=ffffffff + 17907500 17892 1c00154a 00bca823 sw x11, 16(x25) x11:00002000 x25:1c2fff80 PA:1c2fff90 + 17925500 17910 1c00154e c83ff0ef jal x1, -894 x1=1c001550 + 17926500 17911 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 17927500 17912 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000004 + 17928500 17913 1c0011d6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 17929500 17914 1c0011da 69c7a783 lw x15, 1692(x15) x15=10000990 x15:1c002000 PA:1c00269c + 17944500 17929 1c0011de ffe50513 addi x10, x10, -2 x10=00000002 x10:00000004 + 17945500 17930 1c0011e0 00251513 slli x10, x10, 0x2 x10=00000008 x10:00000002 + 17946500 17931 1c0011e2 00f50533 add x10, x10, x15 x10=10000998 x10:00000008 x15:10000990 + 17947500 17932 1c0011e4 f6fff06f jal x0, -146 + 17949500 17934 1c001152 00052783 lw x15, 0(x10) x15=10800990 x10:10000998 PA:10000998 + 17950500 17935 1c001154 00758593 addi x11, x11, 7 x11=00002007 x11:00002000 + 17951500 17936 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00002000 x11:00002007 + 17952500 17937 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 17953500 17938 1c00115c 00078963 beq x15, x0, 18 x15:10800990 + 17954500 17939 1c00115e 0007a703 lw x14, 0(x15) x14=000ff670 x15:10800990 PA:10800990 + 17972500 17957 1c001160 00b74963 blt x14, x11, 18 x14:000ff670 x11:00002000 + 17973500 17958 1c001164 00b71c63 bne x14, x11, 24 x14:000ff670 x11:00002000 + 17976500 17961 1c00117c 40b70733 sub x14, x14, x11 x14=000fd670 x14:000ff670 x11:00002000 + 17977500 17962 1c00117e 00e7a023 sw x14, 0(x15) x14:000fd670 x15:10800990 PA:10800990 + 17997500 17982 1c001180 00e787b3 add x15, x15, x14 x15=108fe000 x15:10800990 x14:000fd670 + 17998500 17983 1c001182 fedff06f jal x0, -20 + 18000500 17985 1c00116e 00f00533 add x10, x0, x15 x10=108fe000 x15:108fe000 + 18001500 17986 1c001170 00008067 jalr x0, x1, 0 x1:1c001550 + 18003500 17988 1c001550 00a00d33 add x26, x0, x10 x26=108fe000 x10:108fe000 + 18004500 17989 1c001552 04050063 beq x10, x0, 64 x10:108fe000 + 18005500 17990 1c001554 00aca623 sw x10, 12(x25) x10:108fe000 x25:1c2fff80 PA:1c2fff8c + 18023500 18008 1c001558 01500533 add x10, x0, x21 x10=100fc720 x21:100fc720 + 18024500 18009 1c00155a 000a9363 bne x21, x0, 6 x21:100fc720 + 18027500 18012 1c001560 00c52783 lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c + 18028500 18013 1c001562 009d0733 add x14, x26, x9 x14=108fe400 x26:108fe000 x9:00000400 + 18029500 18014 1c001566 01842223 sw x24, 4(x8) x24:1c0009d8 x8:10800008 PA:1080000c + 18049500 18034 1c00156a 01742423 sw x23, 8(x8) x23:00000000 x8:10800008 PA:10800010 + 18069500 18054 1c00156e 00e42623 sw x14, 12(x8) x14:108fe400 x8:10800008 PA:10800014 + 18089500 18074 1c001570 00942823 sw x9, 16(x8) x9:00000400 x8:10800008 PA:10800018 + 18109500 18094 1c001572 01342a23 sw x19, 20(x8) x19:00000400 x8:10800008 PA:1080001c + 18129500 18114 1c001576 00a42c23 sw x10, 24(x8) x10:100fc720 x8:10800008 PA:10800020 + 18149500 18134 1c001578 00f42e23 sw x15, 28(x8) x15:1000013c x8:10800008 PA:10800024 + 18169500 18154 1c00157a 002017b7 lui x15, 0x201000 x15=00201000 + 18170500 18155 1c00157e 01242023 sw x18, 0(x8) x18:00000008 x8:10800008 PA:10800008 + 18190500 18175 1c001582 e0478793 addi x15, x15, -508 x15=00200e04 x15:00201000 + 18191500 18176 1c001586 000a67a3 p.sw x0, x0(x20) x20:10800000 PA:10a00e04 + 18214500 18199 1c00158a 00000d93 addi x27, x0, 0 x27=00000000 + 18215500 18200 1c00158c 000a9363 bne x21, x0, 6 x21:100fc720 + 18218500 18203 1c001592 300b1073 csrrw x0, x22, 0x300 x22:00001808 + 18222500 18207 1c001596 04c12083 lw x1, 76(x2) x1=1c000aa0 x2:10000920 PA:1000096c + 18223500 18208 1c001598 04812403 lw x8, 72(x2) x8=00000003 x2:10000920 PA:10000968 + 18224500 18209 1c00159a 01b00533 add x10, x0, x27 x10=00000000 x27:00000000 + 18225500 18210 1c00159c 04412483 lw x9, 68(x2) x9=100fc720 x2:10000920 PA:10000964 + 18226500 18211 1c00159e 04012903 lw x18, 64(x2) x18=1c001000 x2:10000920 PA:10000960 + 18227500 18212 1c0015a0 03c12983 lw x19, 60(x2) x19=00000000 x2:10000920 PA:1000095c + 18228500 18213 1c0015a2 03812a03 lw x20, 56(x2) x20=00000000 x2:10000920 PA:10000958 + 18229500 18214 1c0015a4 03412a83 lw x21, 52(x2) x21=00000000 x2:10000920 PA:10000954 + 18230500 18215 1c0015a6 03012b03 lw x22, 48(x2) x22=00000000 x2:10000920 PA:10000950 + 18231500 18216 1c0015a8 02c12b83 lw x23, 44(x2) x23=00000000 x2:10000920 PA:1000094c + 18232500 18217 1c0015aa 02812c03 lw x24, 40(x2) x24=00000000 x2:10000920 PA:10000948 + 18233500 18218 1c0015ac 02412c83 lw x25, 36(x2) x25=00000000 x2:10000920 PA:10000944 + 18234500 18219 1c0015ae 02012d03 lw x26, 32(x2) x26=00000000 x2:10000920 PA:10000940 + 18235500 18220 1c0015b0 01c12d83 lw x27, 28(x2) x27=00000000 x2:10000920 PA:1000093c + 18236500 18221 1c0015b2 05010113 addi x2, x2, 80 x2=10000970 x2:10000920 + 18237500 18222 1c0015b4 00008067 jalr x0, x1, 0 x1:1c000aa0 + 18239500 18224 1c000aa0 fe4433e3 p.bneimm x8, -26 x8:00000003 + 18242500 18227 1c000a86 008005b3 add x11, x0, x8 x11=00000003 x8:00000003 + 18243500 18228 1c000a88 00912023 sw x9, 0(x2) x9:100fc720 x2:10000970 PA:10000970 + 18244500 18229 1c000a8a 00140413 addi x8, x8, 1 x8=00000004 x8:00000003 + 18245500 18230 1c000a8c 00800893 addi x17, x0, 8 x17=00000008 + 18246500 18231 1c000a8e 00000813 addi x16, x0, 0 x16=00000000 + 18247500 18232 1c000a90 00000793 addi x15, x0, 0 x15=00000000 + 18248500 18233 1c000a92 00000713 addi x14, x0, 0 x14=00000000 + 18249500 18234 1c000a94 00000693 addi x13, x0, 0 x13=00000000 + 18250500 18235 1c000a96 9d890613 addi x12, x18, -1576 x12=1c0009d8 x18:1c001000 + 18251500 18236 1c000a9a 00000513 addi x10, x0, 0 x10=00000000 + 18252500 18237 1c000a9c 1fb000ef jal x1, 2554 x1=1c000aa0 + 18254500 18239 1c001496 fb010113 addi x2, x2, -80 x2=10000920 x2:10000970 + 18255500 18240 1c001498 03512a23 sw x21, 52(x2) x21:00000000 x2:10000920 PA:10000954 + 18256500 18241 1c00149a 05012a83 lw x21, 80(x2) x21=100fc720 x2:10000920 PA:10000970 + 18257500 18242 1c00149c 04912223 sw x9, 68(x2) x9:100fc720 x2:10000920 PA:10000964 + 18258500 18243 1c00149e 03312e23 sw x19, 60(x2) x19:00000000 x2:10000920 PA:1000095c + 18259500 18244 1c0014a0 03712623 sw x23, 44(x2) x23:00000000 x2:10000920 PA:1000094c + 18260500 18245 1c0014a2 03812423 sw x24, 40(x2) x24:00000000 x2:10000920 PA:10000948 + 18261500 18246 1c0014a4 03a12023 sw x26, 32(x2) x26:00000000 x2:10000920 PA:10000940 + 18262500 18247 1c0014a6 01b12e23 sw x27, 28(x2) x27:00000000 x2:10000920 PA:1000093c + 18263500 18248 1c0014a8 00c00c33 add x24, x0, x12 x24=1c0009d8 x12:1c0009d8 + 18264500 18249 1c0014aa 00b00db3 add x27, x0, x11 x27=00000003 x11:00000003 + 18265500 18250 1c0014ac 00d00bb3 add x23, x0, x13 x23=00000000 x13:00000000 + 18266500 18251 1c0014ae 00e00d33 add x26, x0, x14 x26=00000000 x14:00000000 + 18267500 18252 1c0014b0 00f004b3 add x9, x0, x15 x9=00000000 x15:00000000 + 18268500 18253 1c0014b2 010009b3 add x19, x0, x16 x19=00000000 x16:00000000 + 18269500 18254 1c0014b4 04112623 sw x1, 76(x2) x1:1c000aa0 x2:10000920 PA:1000096c + 18270500 18255 1c0014b6 04812423 sw x8, 72(x2) x8:00000004 x2:10000920 PA:10000968 + 18271500 18256 1c0014b8 05212023 sw x18, 64(x2) x18:1c001000 x2:10000920 PA:10000960 + 18272500 18257 1c0014ba 03412c23 sw x20, 56(x2) x20:00000000 x2:10000920 PA:10000958 + 18273500 18258 1c0014bc 03612823 sw x22, 48(x2) x22:00000000 x2:10000920 PA:10000950 + 18274500 18259 1c0014be 03912223 sw x25, 36(x2) x25:00000000 x2:10000920 PA:10000944 + 18275500 18260 1c0014c0 30047b73 csrrci x22, 0x00000008, 0x300 x22=00001808 + 18279500 18264 1c0014c4 01100933 add x18, x0, x17 x18=00000008 x17:00000008 + 18280500 18265 1c0014c6 00089463 bne x17, x0, 8 x17:00000008 + 18284500 18269 1c0014ce 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 18285500 18270 1c0014d2 6a87ac83 lw x25, 1704(x15) x25=1c2fff50 x15:1c002000 PA:1c0026a8 + 18301500 18286 1c0014d6 01800793 addi x15, x0, 24 x15=00000018 + 18302500 18287 1c0014d8 040d8a13 addi x20, x27, 64 x20=00000043 x27:00000003 + 18303500 18288 1c0014dc 42fd8cb3 p.mac x25, x27, x15 x25=1c2fff98 x25:1c2fff50 x27:00000003 x15:00000018 + 18304500 18289 1c0014e0 1b000737 lui x14, 0x1b000000 x14=1b000000 + 18305500 18290 1c0014e4 000016b7 lui x13, 0x1000 x13=00001000 + 18306500 18291 1c0014e6 016a1a13 slli x20, x20, 0x16 x20=10c00000 x20:00000043 + 18307500 18292 1c0014e8 00870713 addi x14, x14, 8 x14=1b000008 x14:1b000000 + 18308500 18293 1c0014ec fff68693 addi x13, x13, -1 x13=00000fff x13:00001000 + 18309500 18294 1c0014ee 004ca783 lw x15, 4(x25) x15=00000000 x25:1c2fff98 PA:1c2fff9c + 18324500 18309 1c0014f2 00579413 slli x8, x15, 0x5 x8=00000000 x15:00000000 + 18325500 18310 1c0014f6 00e40433 add x8, x8, x14 x8=1b000008 x8:00000000 x14:1b000008 + 18326500 18311 1c0014f8 00d47433 and x8, x8, x13 x8=00000008 x8:1b000008 x13:00000fff + 18327500 18312 1c0014fa 01440433 add x8, x8, x20 x8=10c00008 x8:00000008 x20:10c00000 + 18328500 18313 1c0014fc 00042603 lw x12, 0(x8) x12=00000000 x8:10c00008 PA:10c00008 + 18346500 18331 1c0014fe 00060763 beq x12, x0, 14 x12:00000000 + 18349500 18334 1c00150c 00cca583 lw x11, 12(x25) x11=00000000 x25:1c2fff98 PA:1c2fffa4 + 18366500 18351 1c001510 0017c793 xori x15, x15, 1 x15=00000001 x15:00000000 + 18367500 18352 1c001514 00fca223 sw x15, 4(x25) x15:00000001 x25:1c2fff98 PA:1c2fff9c + 18385500 18370 1c001518 00058863 beq x11, x0, 16 x11:00000000 + 18388500 18373 1c001528 00049363 bne x9, x0, 6 x9:00000000 + 18389500 18374 1c00152a 40000493 addi x9, x0, 1024 x9=00000400 + 18390500 18375 1c00152e 00099463 bne x19, x0, 8 x19:00000000 + 18391500 18376 1c001532 40000993 addi x19, x0, 1024 x19=00000400 + 18392500 18377 1c001536 020d1163 bne x26, x0, 34 x26:00000000 + 18393500 18378 1c00153a fff90793 addi x15, x18, -1 x15=00000007 x18:00000008 + 18394500 18379 1c00153e 009005b3 add x11, x0, x9 x11=00000400 x9:00000400 + 18395500 18380 1c001540 433785b3 p.mac x11, x15, x19 x11=00002000 x11:00000400 x15:00000007 x19:00000400 + 18396500 18381 1c001544 002d8513 addi x10, x27, 2 x10=00000005 x27:00000003 + 18397500 18382 1c001548 fff00d93 addi x27, x0, -1 x27=ffffffff + 18398500 18383 1c00154a 00bca823 sw x11, 16(x25) x11:00002000 x25:1c2fff98 PA:1c2fffa8 + 18416500 18401 1c00154e c83ff0ef jal x1, -894 x1=1c001550 + 18417500 18402 1c0011d0 00100793 addi x15, x0, 1 x15=00000001 + 18418500 18403 1c0011d2 00a7fa63 bgeu x15, x10, 20 x15:00000001 x10:00000005 + 18419500 18404 1c0011d6 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 18420500 18405 1c0011da 69c7a783 lw x15, 1692(x15) x15=10000990 x15:1c002000 PA:1c00269c + 18435500 18420 1c0011de ffe50513 addi x10, x10, -2 x10=00000003 x10:00000005 + 18436500 18421 1c0011e0 00251513 slli x10, x10, 0x2 x10=0000000c x10:00000003 + 18437500 18422 1c0011e2 00f50533 add x10, x10, x15 x10=1000099c x10:0000000c x15:10000990 + 18438500 18423 1c0011e4 f6fff06f jal x0, -146 + 18440500 18425 1c001152 00052783 lw x15, 0(x10) x15=10c00990 x10:1000099c PA:1000099c + 18441500 18426 1c001154 00758593 addi x11, x11, 7 x11=00002007 x11:00002000 + 18442500 18427 1c001156 c405b5b3 p.bclr x11, x11, 2, 0 x11=00002000 x11:00002007 + 18443500 18428 1c00115a 00000693 addi x13, x0, 0 x13=00000000 + 18444500 18429 1c00115c 00078963 beq x15, x0, 18 x15:10c00990 + 18445500 18430 1c00115e 0007a703 lw x14, 0(x15) x14=000ff670 x15:10c00990 PA:10c00990 + 18463500 18448 1c001160 00b74963 blt x14, x11, 18 x14:000ff670 x11:00002000 + 18464500 18449 1c001164 00b71c63 bne x14, x11, 24 x14:000ff670 x11:00002000 + 18467500 18452 1c00117c 40b70733 sub x14, x14, x11 x14=000fd670 x14:000ff670 x11:00002000 + 18468500 18453 1c00117e 00e7a023 sw x14, 0(x15) x14:000fd670 x15:10c00990 PA:10c00990 + 18488500 18473 1c001180 00e787b3 add x15, x15, x14 x15=10cfe000 x15:10c00990 x14:000fd670 + 18489500 18474 1c001182 fedff06f jal x0, -20 + 18491500 18476 1c00116e 00f00533 add x10, x0, x15 x10=10cfe000 x15:10cfe000 + 18492500 18477 1c001170 00008067 jalr x0, x1, 0 x1:1c001550 + 18494500 18479 1c001550 00a00d33 add x26, x0, x10 x26=10cfe000 x10:10cfe000 + 18495500 18480 1c001552 04050063 beq x10, x0, 64 x10:10cfe000 + 18496500 18481 1c001554 00aca623 sw x10, 12(x25) x10:10cfe000 x25:1c2fff98 PA:1c2fffa4 + 18514500 18499 1c001558 01500533 add x10, x0, x21 x10=100fc720 x21:100fc720 + 18515500 18500 1c00155a 000a9363 bne x21, x0, 6 x21:100fc720 + 18518500 18503 1c001560 00c52783 lw x15, 12(x10) x15=1000013c x10:100fc720 PA:100fc72c + 18519500 18504 1c001562 009d0733 add x14, x26, x9 x14=10cfe400 x26:10cfe000 x9:00000400 + 18520500 18505 1c001566 01842223 sw x24, 4(x8) x24:1c0009d8 x8:10c00008 PA:10c0000c + 18540500 18525 1c00156a 01742423 sw x23, 8(x8) x23:00000000 x8:10c00008 PA:10c00010 + 18560500 18545 1c00156e 00e42623 sw x14, 12(x8) x14:10cfe400 x8:10c00008 PA:10c00014 + 18580500 18565 1c001570 00942823 sw x9, 16(x8) x9:00000400 x8:10c00008 PA:10c00018 + 18600500 18585 1c001572 01342a23 sw x19, 20(x8) x19:00000400 x8:10c00008 PA:10c0001c + 18620500 18605 1c001576 00a42c23 sw x10, 24(x8) x10:100fc720 x8:10c00008 PA:10c00020 + 18640500 18625 1c001578 00f42e23 sw x15, 28(x8) x15:1000013c x8:10c00008 PA:10c00024 + 18660500 18645 1c00157a 002017b7 lui x15, 0x201000 x15=00201000 + 18661500 18646 1c00157e 01242023 sw x18, 0(x8) x18:00000008 x8:10c00008 PA:10c00008 + 18681500 18666 1c001582 e0478793 addi x15, x15, -508 x15=00200e04 x15:00201000 + 18682500 18667 1c001586 000a67a3 p.sw x0, x0(x20) x20:10c00000 PA:10e00e04 + 18705500 18690 1c00158a 00000d93 addi x27, x0, 0 x27=00000000 + 18706500 18691 1c00158c 000a9363 bne x21, x0, 6 x21:100fc720 + 18709500 18694 1c001592 300b1073 csrrw x0, x22, 0x300 x22:00001808 + 18713500 18698 1c001596 04c12083 lw x1, 76(x2) x1=1c000aa0 x2:10000920 PA:1000096c + 18714500 18699 1c001598 04812403 lw x8, 72(x2) x8=00000004 x2:10000920 PA:10000968 + 18715500 18700 1c00159a 01b00533 add x10, x0, x27 x10=00000000 x27:00000000 + 18716500 18701 1c00159c 04412483 lw x9, 68(x2) x9=100fc720 x2:10000920 PA:10000964 + 18717500 18702 1c00159e 04012903 lw x18, 64(x2) x18=1c001000 x2:10000920 PA:10000960 + 18718500 18703 1c0015a0 03c12983 lw x19, 60(x2) x19=00000000 x2:10000920 PA:1000095c + 18719500 18704 1c0015a2 03812a03 lw x20, 56(x2) x20=00000000 x2:10000920 PA:10000958 + 18720500 18705 1c0015a4 03412a83 lw x21, 52(x2) x21=00000000 x2:10000920 PA:10000954 + 18721500 18706 1c0015a6 03012b03 lw x22, 48(x2) x22=00000000 x2:10000920 PA:10000950 + 18722500 18707 1c0015a8 02c12b83 lw x23, 44(x2) x23=00000000 x2:10000920 PA:1000094c + 18723500 18708 1c0015aa 02812c03 lw x24, 40(x2) x24=00000000 x2:10000920 PA:10000948 + 18724500 18709 1c0015ac 02412c83 lw x25, 36(x2) x25=00000000 x2:10000920 PA:10000944 + 18725500 18710 1c0015ae 02012d03 lw x26, 32(x2) x26=00000000 x2:10000920 PA:10000940 + 18726500 18711 1c0015b0 01c12d83 lw x27, 28(x2) x27=00000000 x2:10000920 PA:1000093c + 18727500 18712 1c0015b2 05010113 addi x2, x2, 80 x2=10000970 x2:10000920 + 18728500 18713 1c0015b4 00008067 jalr x0, x1, 0 x1:1c000aa0 + 18730500 18715 1c000aa0 fe4433e3 p.bneimm x8, -26 x8:00000004 + 18731500 18716 1c000aa4 00000513 addi x10, x0, 0 x10=00000000 + 18732500 18717 1c000aa6 1c002937 lui x18, 0x1c002000 x18=1c002000 + 18733500 18718 1c000aaa f2fff0ef jal x1, -210 x1=1c000aac + 18752500 18737 1c0009d8 ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 18753500 18738 1c0009da 0ff00713 addi x14, x0, 255 x14=000000ff + 18772500 18757 1c0009de 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 18773500 18758 1c0009e2 00112623 sw x1, 12(x2) x1:1c000aac x2:10000960 PA:1000096c + 18774500 18759 1c0009e4 00812423 sw x8, 8(x2) x8:00000004 x2:10000960 PA:10000968 + 18775500 18760 1c0009e6 00912223 sw x9, 4(x2) x9:100fc720 x2:10000960 PA:10000964 + 18776500 18761 1c0009e8 08e7a223 sw x14, 132(x15) x14:000000ff x15:1b204000 PA:1b204084 + 18777500 18762 1c0009ec 20078493 addi x9, x15, 512 x9=1b204200 x15:1b204000 + 18798500 18783 1c0009f0 00e4a023 sw x14, 0(x9) x14:000000ff x9:1b204200 PA:1b204200 + 18799500 18784 1c0009f2 20c78793 addi x15, x15, 524 x15=1b20420c x15:1b204000 + 18800500 18785 1c0009f6 00e7a023 sw x14, 0(x15) x14:000000ff x15:1b20420c PA:1b20420c + 18801500 18786 1c0009f8 1c0017b7 lui x15, 0x1c001000 x15=1c001000 + 18802500 18787 1c0009fc 9bc78793 addi x15, x15, -1604 x15=1c0009bc x15:1c001000 + 18820500 18805 1c000a00 1b204737 lui x14, 0x1b204000 x14=1b204000 + 18821500 18806 1c000a04 08f72023 sw x15, 128(x14) x15:1c0009bc x14:1b204000 PA:1b204080 + 18822500 18807 1c000a08 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 18823500 18808 1c000a0c 08a7a023 sw x10, 128(x15) x10:00000000 x15:1b204000 PA:1b204080 + 18842500 18827 1c000a10 f1402673 csrrs x12, x0, 0xf14 x12=00000000 + 18843500 18828 1c000a14 40565413 srai x8, x12, 0x405 x8=00000000 x12:00000000 + 18844500 18829 1c000a18 f2643433 p.bclr x8, x8, 25, 6 x8=00000000 x8:00000000 + 18845500 18830 1c000a1c 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18867500 18852 1c000a20 f4563633 p.bclr x12, x12, 26, 5 x12=00000000 x12:00000000 + 18868500 18853 1c000a24 008005b3 add x11, x0, x8 x11=00000000 x8:00000000 + 18869500 18854 1c000a26 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18870500 18855 1c000a2a 5e7000ef jal x1, 3558 x1=1c000a2e + 18892500 18877 1c001810 fc010113 addi x2, x2, -64 x2=10000920 x2:10000960 + 18893500 18878 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:10000920 PA:10000944 + 18894500 18879 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18895500 18880 1c001818 02c12423 sw x12, 40(x2) x12:00000000 x2:10000920 PA:10000948 + 18896500 18881 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10000920 PA:1000094c + 18897500 18882 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18898500 18883 1c00181e 02410693 addi x13, x2, 36 x13=10000944 x2:10000920 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c000a2e x2:10000920 PA:1000093c + 18915500 18900 1c001828 02e12823 sw x14, 48(x2) x14:1b204000 x2:10000920 PA:10000950 + 18916500 18901 1c00182a 02f12a23 sw x15, 52(x2) x15:1b204000 x2:10000920 PA:10000954 + 18917500 18902 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10000920 PA:10000958 + 18918500 18903 1c00182e 03112e23 sw x17, 60(x2) x17:00000008 x2:10000920 PA:1000095c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:10000944 x2:10000920 PA:1000092c + 18937500 18922 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100008c0 x2:10000920 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100008d8 x2:100008c0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100008c0 PA:10000918 + 18958500 18943 1c001b76 05212823 sw x18, 80(x2) x18:1c002000 x2:100008c0 PA:10000910 + 18959500 18944 1c001b78 05312623 sw x19, 76(x2) x19:00000000 x2:100008c0 PA:1000090c + 18960500 18945 1c001b7a 05412423 sw x20, 72(x2) x20:00000000 x2:100008c0 PA:10000908 + 18962500 18947 1c001b7c 05512223 sw x21, 68(x2) x21:00000000 x2:100008c0 PA:10000904 + 18963500 18948 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100008c0 PA:10000900 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100008c0 PA:100008fc + 18983500 18968 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100008c0 PA:1000091c + 18984500 18969 1c001b84 04912a23 sw x9, 84(x2) x9:1b204200 x2:100008c0 PA:10000914 + 18985500 18970 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100008c0 PA:100008f8 + 18986500 18971 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100008c0 PA:100008f4 + 18987500 18972 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18988500 18973 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18989500 18974 1c001b8e 00d00433 add x8, x0, x13 x8=10000944 x13:10000944 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100008d8 x2:100008c0 PA:100008d4 + 19013500 18998 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19014500 18999 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19015500 19000 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19016500 19001 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19051500 19036 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19052500 19037 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104000 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19171500 19156 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19172500 19157 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19175500 19160 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19176500 19161 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19177500 19162 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19179500 19164 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19180500 19165 1c001778 fddff06f jal x0, -36 + 19182500 19167 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19183500 19168 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19184500 19169 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19185500 19170 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19186500 19171 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19187500 19172 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19188500 19173 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19189500 19174 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19190500 19175 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19191500 19176 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104000 + 19195500 19180 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19196500 19181 1c001bca 16a0006f jal x0, 362 + 19198500 19183 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19199500 19184 1c001d36 e69ff06f jal x0, -408 + 19202500 19187 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19221500 19206 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19222500 19207 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19225500 19210 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19226500 19211 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19227500 19212 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19229500 19214 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19230500 19215 1c001778 fddff06f jal x0, -36 + 19232500 19217 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19233500 19218 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19234500 19219 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19235500 19220 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19236500 19221 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19237500 19222 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19238500 19223 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19239500 19224 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19240500 19225 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19241500 19226 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104000 + 19245500 19230 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19246500 19231 1c001bca 16a0006f jal x0, 362 + 19248500 19233 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19249500 19234 1c001d36 e69ff06f jal x0, -408 + 19252500 19237 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19267500 19252 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19268500 19253 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19271500 19256 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19272500 19257 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19273500 19258 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19275500 19260 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19276500 19261 1c001778 fddff06f jal x0, -36 + 19278500 19263 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19279500 19264 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19280500 19265 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19281500 19266 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19282500 19267 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19283500 19268 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19284500 19269 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19285500 19270 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19286500 19271 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19287500 19272 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104000 + 19291500 19276 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19292500 19277 1c001bca 16a0006f jal x0, 362 + 19294500 19279 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19295500 19280 1c001d36 e69ff06f jal x0, -408 + 19298500 19283 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19313500 19298 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19314500 19299 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19317500 19302 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19318500 19303 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19319500 19304 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19321500 19306 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19322500 19307 1c001778 fddff06f jal x0, -36 + 19324500 19309 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19325500 19310 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19326500 19311 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19327500 19312 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19328500 19313 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19329500 19314 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19330500 19315 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19331500 19316 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19332500 19317 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19333500 19318 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104000 + 19337500 19322 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19338500 19323 1c001bca 16a0006f jal x0, 362 + 19340500 19325 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19341500 19326 1c001d36 e69ff06f jal x0, -408 + 19344500 19329 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19362500 19347 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19363500 19348 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19366500 19351 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19367500 19352 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19368500 19353 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19370500 19355 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19371500 19356 1c001778 fddff06f jal x0, -36 + 19373500 19358 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19374500 19359 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19375500 19360 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19376500 19361 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19377500 19362 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19378500 19363 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19379500 19364 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19380500 19365 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19381500 19366 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19382500 19367 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104000 + 19386500 19371 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19387500 19372 1c001bca 16a0006f jal x0, 362 + 19389500 19374 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19390500 19375 1c001d36 e69ff06f jal x0, -408 + 19393500 19378 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19412500 19397 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19413500 19398 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19416500 19401 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19417500 19402 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19418500 19403 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19420500 19405 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19421500 19406 1c001778 fddff06f jal x0, -36 + 19423500 19408 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19424500 19409 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19425500 19410 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19426500 19411 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19427500 19412 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19428500 19413 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19429500 19414 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19430500 19415 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19431500 19416 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19432500 19417 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104000 + 19436500 19421 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19437500 19422 1c001bca 16a0006f jal x0, 362 + 19439500 19424 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19440500 19425 1c001d36 e69ff06f jal x0, -408 + 19443500 19428 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19462500 19447 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19463500 19448 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19466500 19451 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19467500 19452 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19468500 19453 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19470500 19455 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19471500 19456 1c001778 fddff06f jal x0, -36 + 19473500 19458 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19474500 19459 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19475500 19460 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19476500 19461 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19477500 19462 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19478500 19463 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19479500 19464 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19480500 19465 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19481500 19466 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19482500 19467 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104000 + 19486500 19471 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19487500 19472 1c001bca 16a0006f jal x0, 362 + 19489500 19474 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19490500 19475 1c001d36 e69ff06f jal x0, -408 + 19493500 19478 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19512500 19497 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19513500 19498 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19516500 19501 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19517500 19502 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19518500 19503 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19520500 19505 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19521500 19506 1c001778 fddff06f jal x0, -36 + 19523500 19508 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19524500 19509 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19525500 19510 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19526500 19511 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19527500 19512 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19528500 19513 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19529500 19514 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19530500 19515 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19531500 19516 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19532500 19517 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104000 + 19536500 19521 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19537500 19522 1c001bca 16a0006f jal x0, 362 + 19539500 19524 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19540500 19525 1c001d36 e69ff06f jal x0, -408 + 19543500 19528 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19567500 19552 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19568500 19553 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19571500 19556 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19572500 19557 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19573500 19558 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19575500 19560 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19576500 19561 1c001778 fddff06f jal x0, -36 + 19578500 19563 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19579500 19564 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19580500 19565 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19581500 19566 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19582500 19567 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19583500 19568 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19584500 19569 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19585500 19570 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19586500 19571 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19587500 19572 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104000 + 19591500 19576 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19592500 19577 1c001bca 16a0006f jal x0, 362 + 19594500 19579 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19595500 19580 1c001d36 e69ff06f jal x0, -408 + 19598500 19583 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19614500 19599 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19615500 19600 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19618500 19603 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19619500 19604 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19620500 19605 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19622500 19607 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19623500 19608 1c001778 fddff06f jal x0, -36 + 19625500 19610 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19626500 19611 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19627500 19612 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19628500 19613 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19629500 19614 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19630500 19615 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19631500 19616 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19632500 19617 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19633500 19618 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19634500 19619 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104000 + 19638500 19623 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19639500 19624 1c001bca 16a0006f jal x0, 362 + 19641500 19626 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19642500 19627 1c001d36 e69ff06f jal x0, -408 + 19645500 19630 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19661500 19646 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19662500 19647 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19665500 19650 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19666500 19651 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19667500 19652 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19669500 19654 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19670500 19655 1c001778 fddff06f jal x0, -36 + 19672500 19657 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19673500 19658 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19674500 19659 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19675500 19660 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19676500 19661 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19677500 19662 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19678500 19663 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19679500 19664 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19680500 19665 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19681500 19666 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104000 + 19685500 19670 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19686500 19671 1c001bca 16a0006f jal x0, 362 + 19688500 19673 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19689500 19674 1c001d36 e69ff06f jal x0, -408 + 19692500 19677 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19707500 19692 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19708500 19693 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19711500 19696 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19712500 19697 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19713500 19698 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19715500 19700 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19716500 19701 1c001778 fddff06f jal x0, -36 + 19718500 19703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19719500 19704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19720500 19705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19721500 19706 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19722500 19707 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19723500 19708 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19724500 19709 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19725500 19710 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19726500 19711 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19727500 19712 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104000 + 19731500 19716 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19732500 19717 1c001bca 16a0006f jal x0, 362 + 19734500 19719 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19735500 19720 1c001d36 e69ff06f jal x0, -408 + 19738500 19723 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19755500 19740 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19756500 19741 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19759500 19744 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19760500 19745 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19761500 19746 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19763500 19748 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19764500 19749 1c001778 fddff06f jal x0, -36 + 19766500 19751 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19767500 19752 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19768500 19753 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19769500 19754 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19770500 19755 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19771500 19756 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19772500 19757 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19773500 19758 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19774500 19759 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19775500 19760 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104000 + 19779500 19764 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19780500 19765 1c001bca 16a0006f jal x0, 362 + 19782500 19767 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19783500 19768 1c001d36 e69ff06f jal x0, -408 + 19786500 19771 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19802500 19787 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19803500 19788 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19806500 19791 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19807500 19792 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19810500 19795 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19811500 19796 1c001778 fddff06f jal x0, -36 + 19813500 19798 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19814500 19799 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 19815500 19800 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19816500 19801 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 19817500 19802 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 19818500 19803 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 19819500 19804 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 19820500 19805 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 19821500 19806 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19822500 19807 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104000 + 19826500 19811 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19827500 19812 1c001bca 16a0006f jal x0, 362 + 19829500 19814 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19830500 19815 1c001d36 e69ff06f jal x0, -408 + 19833500 19818 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19848500 19833 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19849500 19834 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19852500 19837 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19855500 19840 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100008c0 PA:100008c4 + 19876500 19861 1c001bd0 00012423 sw x0, 8(x2) x2:100008c0 PA:100008c8 + 19877500 19862 1c001bd2 00010623 sb x0, 12(x2) x2:100008c0 PA:100008cc + 19878500 19863 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19879500 19864 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19896500 19881 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19897500 19882 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100008c0 PA:100008c4 + 19898500 19883 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19899500 19884 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19900500 19885 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19901500 19886 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19902500 19887 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19936500 19921 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19947500 19932 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100008c0 PA:100008d0 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=10000948 x8:10000944 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:10000944 PA:10000944 + 20309500 20294 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100008c4 x2:100008c0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100008d8 x11:100008c4 PA:100008d4 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100008c4 PA:100008d0 + 20403500 20388 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20404500 20389 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20438500 20423 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20439500 20424 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20440500 20425 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20441500 20426 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20444500 20429 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100008c4 PA:100008d0 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100008d8 PA:100008d8 + 20584500 20569 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20585500 20570 1c001a5e 00168693 addi x13, x13, 1 x13=100008d9 x13:100008d8 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100008d9 PA:100008d9 + 20605500 20590 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20607500 20592 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100008c4 x2:100008c0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100008a0 x2:100008c0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:10000944 x2:100008a0 PA:100008b8 + 20648500 20633 1c001a66 01062783 lw x15, 16(x12) x15=100008d8 x12:100008c4 PA:100008d4 + 20649500 20634 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100008c4 PA:100008c8 + 20650500 20635 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100008a0 PA:100008b4 + 20651500 20636 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100008a0 PA:100008b0 + 20652500 20637 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100008a0 PA:100008ac + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100008a0 PA:100008bc + 20674500 20659 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100008a0 PA:100008a8 + 20675500 20660 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20676500 20661 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20677500 20662 1c001a78 00c004b3 add x9, x0, x12 x9=100008c4 x12:100008c4 + 20678500 20663 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100008d9 x15:100008d8 PA:100008d8 + 20680500 20665 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100008c4 PA:100008cc + 20699500 20684 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20702500 20687 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100008c4 PA:100008cc + 20794500 20779 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 20815500 20800 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20816500 20801 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100008d8 x9:100008c4 PA:100008d4 + 20857500 20842 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100008d9 x20:100008d8 PA:100008d8 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104000 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100008da x20:100008d9 PA:100008d9 + 20933500 20918 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20934500 20919 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 20936500 20921 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20937500 20922 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100008a0 PA:100008bc + 20958500 20943 1c001b02 01812403 lw x8, 24(x2) x8=10000944 x2:100008a0 PA:100008b8 + 20959500 20944 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100008a0 PA:100008b4 + 20960500 20945 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100008a0 PA:100008b0 + 20961500 20946 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100008a0 PA:100008ac + 20962500 20947 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100008a0 PA:100008a8 + 20963500 20948 1c001b0c 02010113 addi x2, x2, 32 x2=100008c0 x2:100008a0 + 20964500 20949 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=10000948 x24:10000948 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21003500 20988 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21004500 20989 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21007500 20992 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21008500 20993 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21009500 20994 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21011500 20996 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21012500 20997 1c001778 fddff06f jal x0, -36 + 21014500 20999 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21015500 21000 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 21016500 21001 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21017500 21002 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 21018500 21003 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 21019500 21004 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 21020500 21005 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 21021500 21006 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 21022500 21007 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21023500 21008 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104000 + 21027500 21012 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21028500 21013 1c001bca 16a0006f jal x0, 362 + 21030500 21015 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21031500 21016 1c001d36 e69ff06f jal x0, -408 + 21034500 21019 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21048500 21033 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21049500 21034 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21052500 21037 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21053500 21038 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21054500 21039 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21056500 21041 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21057500 21042 1c001778 fddff06f jal x0, -36 + 21059500 21044 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21060500 21045 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 21061500 21046 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21062500 21047 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 21063500 21048 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 21064500 21049 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 21065500 21050 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 21066500 21051 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 21067500 21052 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21068500 21053 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104000 + 21072500 21057 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21073500 21058 1c001bca 16a0006f jal x0, 362 + 21075500 21060 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21076500 21061 1c001d36 e69ff06f jal x0, -408 + 21079500 21064 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21094500 21079 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21095500 21080 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21098500 21083 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21101500 21086 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100008c0 PA:100008c4 + 21102500 21087 1c001bd0 00012423 sw x0, 8(x2) x2:100008c0 PA:100008c8 + 21103500 21088 1c001bd2 00010623 sb x0, 12(x2) x2:100008c0 PA:100008cc + 21104500 21089 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21105500 21090 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21106500 21091 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21107500 21092 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100008c0 PA:100008c4 + 21108500 21093 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21109500 21094 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21110500 21095 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21111500 21096 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21112500 21097 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21113500 21098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21114500 21099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21115500 21100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21130500 21115 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21131500 21116 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21134500 21119 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21135500 21120 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21136500 21121 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21139500 21124 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21142500 21127 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21145500 21130 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21148500 21133 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21149500 21134 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21150500 21135 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21151500 21136 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21154500 21139 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21155500 21140 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21158500 21143 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21159500 21144 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21162500 21147 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21164500 21149 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21167500 21152 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21168500 21153 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21171500 21156 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21172500 21157 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21173500 21158 1c001f42 e09ff06f jal x0, -504 + 21175500 21160 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21176500 21161 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100008c0 PA:100008d0 + 21177500 21162 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21180500 21165 1c001e34 00440c13 addi x24, x8, 4 x24=1000094c x8:10000948 + 21181500 21166 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:10000948 PA:10000948 + 21182500 21167 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21185500 21170 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 21188500 21173 1c001e64 00410593 addi x11, x2, 4 x11=100008c4 x2:100008c0 + 21189500 21174 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21191500 21176 1c0019fe 0105a683 lw x13, 16(x11) x13=100008d8 x11:100008c4 PA:100008d4 + 21192500 21177 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100008c4 PA:100008d0 + 21193500 21178 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21194500 21179 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 21228500 21213 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 21229500 21214 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21230500 21215 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21231500 21216 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21234500 21219 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100008c4 PA:100008d0 + 21235500 21220 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 21269500 21254 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 21303500 21288 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21334500 21319 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21335500 21320 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 21336500 21321 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 21337500 21322 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 21338500 21323 1c001a38 01e0006f jal x0, 30 + 21340500 21325 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 21341500 21326 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100008d8 PA:100008d8 + 21342500 21327 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21343500 21328 1c001a5e 00168693 addi x13, x13, 1 x13=100008d9 x13:100008d8 + 21344500 21329 1c001a60 fb1ff06f jal x0, -80 + 21346500 21331 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21347500 21332 1c001a12 00068023 sb x0, 0(x13) x13:100008d9 PA:100008d9 + 21348500 21333 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21350500 21335 1c001e68 f17ff06f jal x0, -234 + 21352500 21337 1c001d7e 00410613 addi x12, x2, 4 x12=100008c4 x2:100008c0 + 21353500 21338 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21354500 21339 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21355500 21340 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21357500 21342 1c001a62 fe010113 addi x2, x2, -32 x2=100008a0 x2:100008c0 + 21358500 21343 1c001a64 00812c23 sw x8, 24(x2) x8:10000948 x2:100008a0 PA:100008b8 + 21359500 21344 1c001a66 01062783 lw x15, 16(x12) x15=100008d8 x12:100008c4 PA:100008d4 + 21360500 21345 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100008c4 PA:100008c8 + 21361500 21346 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100008a0 PA:100008b4 + 21362500 21347 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100008a0 PA:100008b0 + 21363500 21348 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100008a0 PA:100008ac + 21364500 21349 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100008a0 PA:100008bc + 21365500 21350 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100008a0 PA:100008a8 + 21366500 21351 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21367500 21352 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21368500 21353 1c001a78 00c004b3 add x9, x0, x12 x9=100008c4 x12:100008c4 + 21369500 21354 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100008d9 x15:100008d8 PA:100008d8 + 21371500 21356 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 21372500 21357 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21373500 21358 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100008c4 PA:100008cc + 21375500 21360 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21378500 21363 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 21380500 21365 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21381500 21366 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21384500 21369 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21385500 21370 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21386500 21371 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21389500 21374 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21390500 21375 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21391500 21376 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21392500 21377 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21393500 21378 1c001b36 f71ff06f jal x0, -144 + 21395500 21380 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100008c4 PA:100008cc + 21397500 21382 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21400500 21385 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 21402500 21387 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21403500 21388 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21406500 21391 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 21407500 21392 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21408500 21393 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21409500 21394 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21410500 21395 1c001ae8 0104aa03 lw x20, 16(x9) x20=100008d8 x9:100008c4 PA:100008d4 + 21412500 21397 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100008d9 x20:100008d8 PA:100008d8 + 21414500 21399 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 21417500 21402 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21418500 21403 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21420500 21405 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 21421500 21406 1c001778 fddff06f jal x0, -36 + 21423500 21408 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21424500 21409 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 21425500 21410 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21426500 21411 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 21427500 21412 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 21428500 21413 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 21429500 21414 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 21430500 21415 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 21431500 21416 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21432500 21417 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104000 + 21436500 21421 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21437500 21422 1c001b62 f8bff06f jal x0, -118 + 21439500 21424 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100008da x20:100008d9 PA:100008d9 + 21441500 21426 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21442500 21427 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100008c4 PA:100008c4 + 21444500 21429 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21445500 21430 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21448500 21433 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100008a0 PA:100008bc + 21449500 21434 1c001b02 01812403 lw x8, 24(x2) x8=10000948 x2:100008a0 PA:100008b8 + 21450500 21435 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100008a0 PA:100008b4 + 21451500 21436 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100008a0 PA:100008b0 + 21452500 21437 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100008a0 PA:100008ac + 21453500 21438 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100008a0 PA:100008a8 + 21454500 21439 1c001b0c 02010113 addi x2, x2, 32 x2=100008c0 x2:100008a0 + 21455500 21440 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21457500 21442 1c001d86 01800433 add x8, x0, x24 x8=1000094c x24:1000094c + 21458500 21443 1c001d88 fadff06f jal x0, -84 + 21460500 21445 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21461500 21446 1c001d36 e69ff06f jal x0, -408 + 21464500 21449 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21478500 21463 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21479500 21464 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21482500 21467 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21483500 21468 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21484500 21469 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21486500 21471 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21487500 21472 1c001778 fddff06f jal x0, -36 + 21489500 21474 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21490500 21475 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 21491500 21476 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21492500 21477 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 21493500 21478 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 21494500 21479 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 21495500 21480 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 21496500 21481 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 21497500 21482 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21498500 21483 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104000 + 21502500 21487 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21503500 21488 1c001bca 16a0006f jal x0, 362 + 21505500 21490 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21506500 21491 1c001d36 e69ff06f jal x0, -408 + 21509500 21494 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21523500 21508 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21524500 21509 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21527500 21512 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21528500 21513 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21529500 21514 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21531500 21516 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21532500 21517 1c001778 fddff06f jal x0, -36 + 21534500 21519 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21535500 21520 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 21536500 21521 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21537500 21522 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 21538500 21523 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 21539500 21524 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 21540500 21525 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 21541500 21526 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 21542500 21527 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21543500 21528 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104000 + 21547500 21532 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21548500 21533 1c001bca 16a0006f jal x0, 362 + 21550500 21535 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21551500 21536 1c001d36 e69ff06f jal x0, -408 + 21554500 21539 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21568500 21553 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21569500 21554 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21572500 21557 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21573500 21558 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21574500 21559 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21576500 21561 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21577500 21562 1c001778 fddff06f jal x0, -36 + 21579500 21564 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21580500 21565 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000000 + 21581500 21566 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21582500 21567 1c00175e 00379713 slli x14, x15, 0x3 x14=00000000 x15:00000000 + 21583500 21568 1c001762 00279793 slli x15, x15, 0x2 x15=00000000 x15:00000000 + 21584500 21569 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000000 + 21585500 21570 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000000 x13:00001f80 + 21586500 21571 1c00176a 00e787b3 add x15, x15, x14 x15=00000000 x15:00000000 x14:00000000 + 21587500 21572 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21588500 21573 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104000 + 21592500 21577 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21593500 21578 1c001bca 16a0006f jal x0, 362 + 21595500 21580 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21596500 21581 1c001d36 e69ff06f jal x0, -408 + 21599500 21584 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21613500 21598 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21614500 21599 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21615500 21600 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100008c0 PA:1000091c + 21616500 21601 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100008c0 PA:10000918 + 21617500 21602 1c001bac 05412483 lw x9, 84(x2) x9=1b204200 x2:100008c0 PA:10000914 + 21618500 21603 1c001bae 05012903 lw x18, 80(x2) x18=1c002000 x2:100008c0 PA:10000910 + 21634500 21619 1c001bb0 04c12983 lw x19, 76(x2) x19=00000000 x2:100008c0 PA:1000090c + 21635500 21620 1c001bb2 04812a03 lw x20, 72(x2) x20=00000000 x2:100008c0 PA:10000908 + 21636500 21621 1c001bb4 04412a83 lw x21, 68(x2) x21=00000000 x2:100008c0 PA:10000904 + 21637500 21622 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100008c0 PA:10000900 + 21638500 21623 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100008c0 PA:100008fc + 21639500 21624 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100008c0 PA:100008f8 + 21640500 21625 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100008c0 PA:100008f4 + 21641500 21626 1c001bbe 06010113 addi x2, x2, 96 x2=10000920 x2:100008c0 + 21642500 21627 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21644500 21629 1c001834 01c12083 lw x1, 28(x2) x1=1c000a2e x2:10000920 PA:1000093c + 21645500 21630 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21646500 21631 1c001838 04010113 addi x2, x2, 64 x2=10000960 x2:10000920 + 21647500 21632 1c00183a 00008067 jalr x0, x1, 0 x1:1c000a2e + 21685500 21670 1c000a2e 01c4e783 p.elw x15, 28(x9) x15=00000000 x9:1b204200 PA:1b20421c + 21694500 21679 1c000a32 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 21695500 21680 1c000a36 00241413 slli x8, x8, 0x2 x8=00000000 x8:00000000 + 21696500 21681 1c000a38 68478793 addi x15, x15, 1668 x15=1c002684 x15:1c002000 + 21697500 21682 1c000a3c 00100713 addi x14, x0, 1 x14=00000001 + 21714500 21699 1c000a3e 00e7e423 p.sw x14, x0(x15) x14:00000001 x15:1c002684 PA:1c002684 + 21733500 21718 1c000a42 00c12083 lw x1, 12(x2) x1=1c000aac x2:10000960 PA:1000096c + 21734500 21719 1c000a44 00812403 lw x8, 8(x2) x8=00000004 x2:10000960 PA:10000968 + 21735500 21720 1c000a46 00412483 lw x9, 4(x2) x9=100fc720 x2:10000960 PA:10000964 + 21736500 21721 1c000a48 01010113 addi x2, x2, 16 x2=10000970 x2:10000960 + 21737500 21722 1c000a4a 00008067 jalr x0, x1, 0 x1:1c000aac + 21739500 21724 1c000aac 00100493 addi x9, x0, 1 x9=00000001 + 21756500 21741 1c000aae 68490913 addi x18, x18, 1668 x18=1c002684 x18:1c002000 + 21757500 21742 1c000ab2 10000413 addi x8, x0, 256 x8=00000100 + 21758500 21743 1c000ab6 00249713 slli x14, x9, 0x2 x14=00000004 x9:00000001 + 21759500 21744 1c000aba 01270733 add x14, x14, x18 x14=1c002688 x14:00000004 x18:1c002684 + 21760500 21745 1c000abc 00072783 lw x15, 0(x14) x15=00000001 x14:1c002688 PA:1c002688 + 21776500 21761 1c000abe 00079a63 bne x15, x0, 20 x15:00000001 + 21798500 21783 1c000ad2 009005b3 add x11, x0, x9 x11=00000001 x9:00000001 + 21799500 21784 1c000ad4 00000693 addi x13, x0, 0 x13=00000000 + 21800500 21785 1c000ad6 00148493 addi x9, x9, 1 x9=00000002 x9:00000001 + 21801500 21786 1c000ad8 00000613 addi x12, x0, 0 x12=00000000 + 21802500 21787 1c000ada 00000513 addi x10, x0, 0 x10=00000000 + 21803500 21788 1c000adc 0c7000ef jal x1, 2246 x1=1c000ae0 + 21822500 21807 1c0013a2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 21823500 21808 1c0013a4 02812423 sw x8, 40(x2) x8:00000100 x2:10000940 PA:10000968 + 21824500 21809 1c0013a6 00b00433 add x8, x0, x11 x8=00000001 x11:00000001 + 21825500 21810 1c0013a8 02112623 sw x1, 44(x2) x1:1c000ae0 x2:10000940 PA:1000096c + 21826500 21811 1c0013aa 02912223 sw x9, 36(x2) x9:00000002 x2:10000940 PA:10000964 + 21827500 21812 1c0013ac 03212023 sw x18, 32(x2) x18:1c002684 x2:10000940 PA:10000960 + 21828500 21813 1c0013ae 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 21845500 21830 1c0013b0 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 21846500 21831 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 21847500 21832 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 21851500 21836 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 21852500 21837 1c0013ba 03458a33 mul x20, x11, x20 x20=00000018 x11:00000001 x20:00000018 + 21869500 21854 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 21870500 21855 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 21884500 21869 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 21885500 21870 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff68 x15:1c2fff50 x20:00000018 + 21886500 21871 1c0013ca 0007a703 lw x14, 0(x15) x14=00000001 x15:1c2fff68 PA:1c2fff68 + 21900500 21885 1c0013cc 02050363 beq x10, x0, 38 x10:00000000 + 21919500 21904 1c0013f2 fff70713 addi x14, x14, -1 x14=00000000 x14:00000001 + 21920500 21905 1c0013f4 fddff06f jal x0, -36 + 21922500 21907 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000000 x15:1c2fff68 PA:1c2fff68 + 21940500 21925 1c0013d2 0007a483 lw x9, 0(x15) x9=00000000 x15:1c2fff68 PA:1c2fff68 + 21955500 21940 1c0013d4 02049163 bne x9, x0, 34 x9:00000000 + 21956500 21941 1c0013d6 00068363 beq x13, x0, 6 x13:00000000 + 21959500 21944 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 21976500 21961 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000ae0 x2:10000940 PA:1000096c + 21977500 21962 1c0013e2 02812403 lw x8, 40(x2) x8=00000100 x2:10000940 PA:10000968 + 21978500 21963 1c0013e4 02412483 lw x9, 36(x2) x9=00000002 x2:10000940 PA:10000964 + 21979500 21964 1c0013e6 02012903 lw x18, 32(x2) x18=1c002684 x2:10000940 PA:10000960 + 21980500 21965 1c0013e8 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 21981500 21966 1c0013ea 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 21982500 21967 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 21983500 21968 1c0013ee 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 21984500 21969 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000ae0 + 21986500 21971 1c000ae0 fc44bbe3 p.bneimm x9, -42 x9:00000002 + 21989500 21974 1c000ab6 00249713 slli x14, x9, 0x2 x14=00000008 x9:00000002 + 21990500 21975 1c000aba 01270733 add x14, x14, x18 x14=1c00268c x14:00000008 x18:1c002684 + 21991500 21976 1c000abc 00072783 lw x15, 0(x14) x15=00000001 x14:1c00268c PA:1c00268c + 22006500 21991 1c000abe 00079a63 bne x15, x0, 20 x15:00000001 + 22009500 21994 1c000ad2 009005b3 add x11, x0, x9 x11=00000002 x9:00000002 + 22010500 21995 1c000ad4 00000693 addi x13, x0, 0 x13=00000000 + 22011500 21996 1c000ad6 00148493 addi x9, x9, 1 x9=00000003 x9:00000002 + 22012500 21997 1c000ad8 00000613 addi x12, x0, 0 x12=00000000 + 22013500 21998 1c000ada 00000513 addi x10, x0, 0 x10=00000000 + 22014500 21999 1c000adc 0c7000ef jal x1, 2246 x1=1c000ae0 + 22016500 22001 1c0013a2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 22017500 22002 1c0013a4 02812423 sw x8, 40(x2) x8:00000100 x2:10000940 PA:10000968 + 22018500 22003 1c0013a6 00b00433 add x8, x0, x11 x8=00000002 x11:00000002 + 22019500 22004 1c0013a8 02112623 sw x1, 44(x2) x1:1c000ae0 x2:10000940 PA:1000096c + 22020500 22005 1c0013aa 02912223 sw x9, 36(x2) x9:00000003 x2:10000940 PA:10000964 + 22021500 22006 1c0013ac 03212023 sw x18, 32(x2) x18:1c002684 x2:10000940 PA:10000960 + 22022500 22007 1c0013ae 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 22023500 22008 1c0013b0 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 22024500 22009 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 22025500 22010 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 22029500 22014 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 22030500 22015 1c0013ba 03458a33 mul x20, x11, x20 x20=00000030 x11:00000002 x20:00000018 + 22031500 22016 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 22032500 22017 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 22046500 22031 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 22047500 22032 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff80 x15:1c2fff50 x20:00000030 + 22048500 22033 1c0013ca 0007a703 lw x14, 0(x15) x14=00000001 x15:1c2fff80 PA:1c2fff80 + 22062500 22047 1c0013cc 02050363 beq x10, x0, 38 x10:00000000 + 22065500 22050 1c0013f2 fff70713 addi x14, x14, -1 x14=00000000 x14:00000001 + 22066500 22051 1c0013f4 fddff06f jal x0, -36 + 22068500 22053 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000000 x15:1c2fff80 PA:1c2fff80 + 22086500 22071 1c0013d2 0007a483 lw x9, 0(x15) x9=00000000 x15:1c2fff80 PA:1c2fff80 + 22101500 22086 1c0013d4 02049163 bne x9, x0, 34 x9:00000000 + 22102500 22087 1c0013d6 00068363 beq x13, x0, 6 x13:00000000 + 22105500 22090 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 22109500 22094 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000ae0 x2:10000940 PA:1000096c + 22110500 22095 1c0013e2 02812403 lw x8, 40(x2) x8=00000100 x2:10000940 PA:10000968 + 22111500 22096 1c0013e4 02412483 lw x9, 36(x2) x9=00000003 x2:10000940 PA:10000964 + 22112500 22097 1c0013e6 02012903 lw x18, 32(x2) x18=1c002684 x2:10000940 PA:10000960 + 22113500 22098 1c0013e8 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 22114500 22099 1c0013ea 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 22115500 22100 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 22116500 22101 1c0013ee 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 22117500 22102 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000ae0 + 22119500 22104 1c000ae0 fc44bbe3 p.bneimm x9, -42 x9:00000003 + 22122500 22107 1c000ab6 00249713 slli x14, x9, 0x2 x14=0000000c x9:00000003 + 22123500 22108 1c000aba 01270733 add x14, x14, x18 x14=1c002690 x14:0000000c x18:1c002684 + 22124500 22109 1c000abc 00072783 lw x15, 0(x14) x15=00000001 x14:1c002690 PA:1c002690 + 22139500 22124 1c000abe 00079a63 bne x15, x0, 20 x15:00000001 + 22142500 22127 1c000ad2 009005b3 add x11, x0, x9 x11=00000003 x9:00000003 + 22143500 22128 1c000ad4 00000693 addi x13, x0, 0 x13=00000000 + 22144500 22129 1c000ad6 00148493 addi x9, x9, 1 x9=00000004 x9:00000003 + 22145500 22130 1c000ad8 00000613 addi x12, x0, 0 x12=00000000 + 22146500 22131 1c000ada 00000513 addi x10, x0, 0 x10=00000000 + 22147500 22132 1c000adc 0c7000ef jal x1, 2246 x1=1c000ae0 + 22149500 22134 1c0013a2 fd010113 addi x2, x2, -48 x2=10000940 x2:10000970 + 22150500 22135 1c0013a4 02812423 sw x8, 40(x2) x8:00000100 x2:10000940 PA:10000968 + 22151500 22136 1c0013a6 00b00433 add x8, x0, x11 x8=00000003 x11:00000003 + 22152500 22137 1c0013a8 02112623 sw x1, 44(x2) x1:1c000ae0 x2:10000940 PA:1000096c + 22153500 22138 1c0013aa 02912223 sw x9, 36(x2) x9:00000004 x2:10000940 PA:10000964 + 22154500 22139 1c0013ac 03212023 sw x18, 32(x2) x18:1c002684 x2:10000940 PA:10000960 + 22155500 22140 1c0013ae 01312e23 sw x19, 28(x2) x19:00000000 x2:10000940 PA:1000095c + 22156500 22141 1c0013b0 01412c23 sw x20, 24(x2) x20:00000000 x2:10000940 PA:10000958 + 22157500 22142 1c0013b2 01512a23 sw x21, 20(x2) x21:00000000 x2:10000940 PA:10000954 + 22158500 22143 1c0013b4 30047973 csrrci x18, 0x00000008, 0x300 x18=00001808 + 22162500 22147 1c0013b8 01800a13 addi x20, x0, 24 x20=00000018 + 22163500 22148 1c0013ba 03458a33 mul x20, x11, x20 x20=00000048 x11:00000003 x20:00000018 + 22164500 22149 1c0013be 1c002737 lui x14, 0x1c002000 x14=1c002000 + 22165500 22150 1c0013c2 6a872783 lw x15, 1704(x14) x15=1c2fff50 x14:1c002000 PA:1c0026a8 + 22179500 22164 1c0013c6 00e00ab3 add x21, x0, x14 x21=1c002000 x14:1c002000 + 22180500 22165 1c0013c8 014787b3 add x15, x15, x20 x15=1c2fff98 x15:1c2fff50 x20:00000048 + 22181500 22166 1c0013ca 0007a703 lw x14, 0(x15) x14=00000001 x15:1c2fff98 PA:1c2fff98 + 22195500 22180 1c0013cc 02050363 beq x10, x0, 38 x10:00000000 + 22198500 22183 1c0013f2 fff70713 addi x14, x14, -1 x14=00000000 x14:00000001 + 22199500 22184 1c0013f4 fddff06f jal x0, -36 + 22201500 22186 1c0013d0 00e7a023 sw x14, 0(x15) x14:00000000 x15:1c2fff98 PA:1c2fff98 + 22219500 22204 1c0013d2 0007a483 lw x9, 0(x15) x9=00000000 x15:1c2fff98 PA:1c2fff98 + 22234500 22219 1c0013d4 02049163 bne x9, x0, 34 x9:00000000 + 22235500 22220 1c0013d6 00068363 beq x13, x0, 6 x13:00000000 + 22238500 22223 1c0013dc 30091073 csrrw x0, x18, 0x300 x18:00001808 + 22242500 22227 1c0013e0 02c12083 lw x1, 44(x2) x1=1c000ae0 x2:10000940 PA:1000096c + 22243500 22228 1c0013e2 02812403 lw x8, 40(x2) x8=00000100 x2:10000940 PA:10000968 + 22244500 22229 1c0013e4 02412483 lw x9, 36(x2) x9=00000004 x2:10000940 PA:10000964 + 22245500 22230 1c0013e6 02012903 lw x18, 32(x2) x18=1c002684 x2:10000940 PA:10000960 + 22246500 22231 1c0013e8 01c12983 lw x19, 28(x2) x19=00000000 x2:10000940 PA:1000095c + 22247500 22232 1c0013ea 01812a03 lw x20, 24(x2) x20=00000000 x2:10000940 PA:10000958 + 22248500 22233 1c0013ec 01412a83 lw x21, 20(x2) x21=00000000 x2:10000940 PA:10000954 + 22249500 22234 1c0013ee 03010113 addi x2, x2, 48 x2=10000970 x2:10000940 + 22250500 22235 1c0013f0 00008067 jalr x0, x1, 0 x1:1c000ae0 + 22252500 22237 1c000ae0 fc44bbe3 p.bneimm x9, -42 x9:00000004 + 22253500 22238 1c000ae4 01c12083 lw x1, 28(x2) x1=1c0000ec x2:10000970 PA:1000098c + 22254500 22239 1c000ae6 01812403 lw x8, 24(x2) x8=00000000 x2:10000970 PA:10000988 + 22255500 22240 1c000ae8 1b2007b7 lui x15, 0x1b200000 x15=1b200000 + 22256500 22241 1c000aec 00100713 addi x14, x0, 1 x14=00000001 + 22257500 22242 1c000aee 00e7a023 sw x14, 0(x15) x14:00000001 x15:1b200000 PA:1b200000 + 22273500 22258 1c000af0 01412483 lw x9, 20(x2) x9=00000000 x2:10000970 PA:10000984 + 22274500 22259 1c000af2 01012903 lw x18, 16(x2) x18=00000000 x2:10000970 PA:10000980 + 22275500 22260 1c000af4 00000513 addi x10, x0, 0 x10=00000000 + 22276500 22261 1c000af6 02010113 addi x2, x2, 32 x2=10000990 x2:10000970 + 22277500 22262 1c000af8 00008067 jalr x0, x1, 0 x1:1c0000ec + 22279500 22264 1c0000ec 00a00433 add x8, x0, x10 x8=00000000 x10:00000000 + 22280500 22265 1c0000ee 44f000ef jal x1, 3150 x1=1c0000f2 + 22282500 22267 1c000d3c ff010113 addi x2, x2, -16 x2=10000980 x2:10000990 + 22283500 22268 1c000d3e 00812423 sw x8, 8(x2) x8:00000000 x2:10000980 PA:10000988 + 22299500 22284 1c000d40 00100513 addi x10, x0, 1 x10=00000001 + 22300500 22285 1c000d42 10000437 lui x8, 0x10000000 x8=10000000 + 22301500 22286 1c000d46 00112623 sw x1, 12(x2) x1:1c0000f2 x2:10000980 PA:1000098c + 22302500 22287 1c000d48 18840413 addi x8, x8, 392 x8=10000188 x8:10000000 + 22303500 22288 1c000d4c 0f2000ef jal x1, 242 x1=1c000d4e + 22337500 22322 1c000e3e ff010113 addi x2, x2, -16 x2=10000970 x2:10000980 + 22354500 22339 1c000e40 00812423 sw x8, 8(x2) x8:10000188 x2:10000970 PA:10000978 + 22355500 22340 1c000e42 10000437 lui x8, 0x10000000 x8=10000000 + 22356500 22341 1c000e46 00251513 slli x10, x10, 0x2 x10=00000004 x10:00000001 + 22357500 22342 1c000e48 05840413 addi x8, x8, 88 x8=10000058 x8:10000000 + 22358500 22343 1c000e4c 20a47403 lw x8, x10(x8) x8=1c2fffd0 x10:00000004 x8:10000058 PA:1000005c + 22359500 22344 1c000e50 00112623 sw x1, 12(x2) x1:1c000d4e x2:10000970 PA:1000097c + 22360500 22345 1c000e52 00041663 bne x8, x0, 12 x8:1c2fffd0 + 22363500 22348 1c000e5e 00042783 lw x15, 0(x8) x15=1c00179c x8:1c2fffd0 PA:1c2fffd0 + 22377500 22362 1c000e60 00442503 lw x10, 4(x8) x10=00000000 x8:1c2fffd0 PA:1c2fffd4 + 22391500 22376 1c000e62 000780e7 jalr x1, x15, 0 x1=1c000e64 x15:1c00179c + 22397500 22382 1c00179c ff010113 addi x2, x2, -16 x2=10000960 x2:10000970 + 22398500 22383 1c00179e 00112623 sw x1, 12(x2) x1:1c000e64 x2:10000960 PA:1000096c + 22414500 22399 1c0017a0 fdbff0ef jal x1, -38 x1=1c0017a2 + 22416500 22401 1c00177a ff010113 addi x2, x2, -16 x2=10000950 x2:10000960 + 22417500 22402 1c00177c 00812423 sw x8, 8(x2) x8:1c2fffd0 x2:10000950 PA:10000958 + 22434500 22419 1c00177e 1c002437 lui x8, 0x1c002000 x8=1c002000 + 22435500 22420 1c001782 67840413 addi x8, x8, 1656 x8=1c002678 x8:1c002000 + 22436500 22421 1c001786 00042503 lw x10, 0(x8) x10=00000000 x8:1c002678 PA:1c002678 + 22450500 22435 1c001788 00112623 sw x1, 12(x2) x1:1c0017a2 x2:10000950 PA:1000095c + 22451500 22436 1c00178a 00050563 beq x10, x0, 10 x10:00000000 + 22454500 22439 1c001794 00c12083 lw x1, 12(x2) x1=1c0017a2 x2:10000950 PA:1000095c + 22455500 22440 1c001796 00812403 lw x8, 8(x2) x8=1c2fffd0 x2:10000950 PA:10000958 + 22456500 22441 1c001798 01010113 addi x2, x2, 16 x2=10000960 x2:10000950 + 22457500 22442 1c00179a 00008067 jalr x0, x1, 0 x1:1c0017a2 + 22459500 22444 1c0017a2 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 22460500 22445 1c0017a6 67c7a503 lw x10, 1660(x15) x10=1c002668 x15:1c002000 PA:1c00267c + 22474500 22459 1c0017aa 00000593 addi x11, x0, 0 x11=00000000 + 22475500 22460 1c0017ac 0d9000ef jal x1, 2264 x1=1c0017b0 + 22477500 22462 1c002084 300476f3 csrrci x13, 0x00000008, 0x300 x13=00001808 + 22481500 22466 1c002088 00052783 lw x15, 0(x10) x15=00000001 x10:1c002668 PA:1c002668 + 22496500 22481 1c00208a fff78793 addi x15, x15, -1 x15=00000000 x15:00000001 + 22497500 22482 1c00208c 00f52023 sw x15, 0(x10) x15:00000000 x10:1c002668 PA:1c002668 + 22515500 22500 1c00208e 00079863 bne x15, x0, 16 x15:00000000 + 22516500 22501 1c002090 1a102737 lui x14, 0x1a102000 x14=1a102000 + 22517500 22502 1c002094 01470713 addi x14, x14, 20 x14=1a102014 x14:1a102000 + 22518500 22503 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22536500 22521 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22537500 22522 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22540500 22525 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22558500 22543 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22559500 22544 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22562500 22547 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22580500 22565 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22581500 22566 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22584500 22569 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22602500 22587 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22603500 22588 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22606500 22591 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22624500 22609 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22625500 22610 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22628500 22613 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22646500 22631 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22647500 22632 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22650500 22635 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22668500 22653 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22669500 22654 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22672500 22657 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22690500 22675 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22691500 22676 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22694500 22679 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22712500 22697 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22713500 22698 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22716500 22701 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22734500 22719 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22735500 22720 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22738500 22723 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22756500 22741 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22757500 22742 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22760500 22745 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22778500 22763 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22779500 22764 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22782500 22767 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22800500 22785 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22801500 22786 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22804500 22789 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22822500 22807 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22823500 22808 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22826500 22811 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22844500 22829 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22845500 22830 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22848500 22833 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22866500 22851 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22867500 22852 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22870500 22855 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22888500 22873 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22889500 22874 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22892500 22877 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22910500 22895 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22911500 22896 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22914500 22899 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22932500 22917 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22933500 22918 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22936500 22921 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22954500 22939 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22955500 22940 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22958500 22943 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22976500 22961 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22977500 22962 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 22980500 22965 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 22998500 22983 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 22999500 22984 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23002500 22987 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23020500 23005 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23021500 23006 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23024500 23009 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23042500 23027 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23043500 23028 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23046500 23031 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23064500 23049 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23065500 23050 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23068500 23053 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23086500 23071 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23087500 23072 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23090500 23075 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23108500 23093 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23109500 23094 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23112500 23097 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23130500 23115 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23131500 23116 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23134500 23119 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23152500 23137 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23153500 23138 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23156500 23141 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23174500 23159 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23175500 23160 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23178500 23163 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23196500 23181 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23197500 23182 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23200500 23185 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23218500 23203 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23219500 23204 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 + 23222500 23207 1c002096 00072783 lw x15, 0(x14) x15=00000000 x14:1a102014 PA:1a102014 + 23240500 23225 1c002098 0407f793 andi x15, x15, 64 x15=00000000 x15:00000000 + 23241500 23226 1c00209c fe078de3 beq x15, x0, -6 x15:00000000 diff --git a/sw/scripts/tracevis/example/traces/trace_core_00_1.log b/sw/scripts/tracevis/example/traces/trace_core_00_1.log new file mode 100644 index 0000000..da46142 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_00_1.log @@ -0,0 +1,847 @@ + Time Cycles PC Instr Mnemonic + 96500 81 1c000080 0180006f jal x0, 24 + 119500 104 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000001 + 120500 105 1c00009c 01f57593 andi x11, x10, 31 x11=00000001 x10:00000001 + 143500 128 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000000 x10:00000001 + 144500 129 1c0000a2 00058463 beq x11, x0, 8 x11:00000001 + 145500 130 1c0000a6 05a0206f jal x0, 8282 + 166500 151 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 167500 152 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 168500 153 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 169500 154 1c00210c 0e059163 bne x11, x0, 226 x11:00000001 + 239500 224 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 240500 225 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000001 + 241500 226 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000001 x19:00000001 + 242500 227 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 259500 244 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 260500 245 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 261500 246 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 262500 247 1c00220a 0060006f jal x0, 6 + 285500 270 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 9629500 9614 1c002214 08096503 p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080 + 9637500 9622 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 9638500 9623 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 9656500 9641 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 9657500 9642 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 9659500 9644 1c00222c 08096283 p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080 + 9683500 9668 1c002230 02a98533 mul x10, x19, x10 x10=00000800 x19:00000001 x10:00000800 + 9684500 9669 1c002234 00550133 add x2, x10, x5 x2=100fcf90 x10:00000800 x5:100fc790 + 9685500 9670 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 9705500 9690 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18829500 18814 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18837500 18822 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18838500 18823 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18839500 18824 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18840500 18825 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18863500 18848 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000001 + 18883500 18868 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18884500 18869 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000000 x12:00000001 + 18885500 18870 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000 + 18886500 18871 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000001 x12:00000001 + 18887500 18872 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18888500 18873 1c0009d4 63d0006f jal x0, 3644 + 18890500 18875 1c001810 fc010113 addi x2, x2, -64 x2=100fcf50 x2:100fcf90 + 18891500 18876 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:100fcf50 PA:100fcf74 + 18895500 18880 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18896500 18881 1c001818 02c12423 sw x12, 40(x2) x12:00000001 x2:100fcf50 PA:100fcf78 + 18897500 18882 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:100fcf50 PA:100fcf7c + 18898500 18883 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18899500 18884 1c00181e 02410693 addi x13, x2, 36 x13=100fcf74 x2:100fcf50 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:100fcf50 PA:100fcf6c + 18917500 18902 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:100fcf50 PA:100fcf80 + 18918500 18903 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:100fcf50 PA:100fcf84 + 18919500 18904 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:100fcf50 PA:100fcf88 + 18920500 18905 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:100fcf50 PA:100fcf8c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:100fcf74 x2:100fcf50 PA:100fcf5c + 18937500 18922 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100fcef0 x2:100fcf50 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100fcf08 x2:100fcef0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100fcef0 PA:100fcf48 + 18959500 18944 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:100fcef0 PA:100fcf40 + 18960500 18945 1c001b78 05312623 sw x19, 76(x2) x19:00000001 x2:100fcef0 PA:100fcf3c + 18961500 18946 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:100fcef0 PA:100fcf38 + 18962500 18947 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:100fcef0 PA:100fcf34 + 18963500 18948 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100fcef0 PA:100fcf30 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100fcef0 PA:100fcf2c + 18985500 18970 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100fcef0 PA:100fcf4c + 18986500 18971 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:100fcef0 PA:100fcf44 + 18987500 18972 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100fcef0 PA:100fcf28 + 18988500 18973 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100fcef0 PA:100fcf24 + 18989500 18974 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18990500 18975 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18991500 18976 1c001b8e 00d00433 add x8, x0, x13 x8=100fcf74 x13:100fcf74 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100fcf08 x2:100fcef0 PA:100fcf04 + 19013500 18998 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19014500 18999 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19015500 19000 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19016500 19001 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19053500 19038 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19054500 19039 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104008 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19173500 19158 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19174500 19159 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19177500 19162 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19178500 19163 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19179500 19164 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19181500 19166 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19182500 19167 1c001778 fddff06f jal x0, -36 + 19184500 19169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19185500 19170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19186500 19171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19187500 19172 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19188500 19173 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19189500 19174 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19190500 19175 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19191500 19176 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19192500 19177 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19193500 19178 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104008 + 19197500 19182 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19198500 19183 1c001bca 16a0006f jal x0, 362 + 19200500 19185 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19201500 19186 1c001d36 e69ff06f jal x0, -408 + 19204500 19189 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19226500 19211 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19227500 19212 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19230500 19215 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19231500 19216 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19232500 19217 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19234500 19219 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19235500 19220 1c001778 fddff06f jal x0, -36 + 19237500 19222 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19238500 19223 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19239500 19224 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19240500 19225 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19241500 19226 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19242500 19227 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19243500 19228 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19244500 19229 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19245500 19230 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19246500 19231 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104008 + 19250500 19235 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19251500 19236 1c001bca 16a0006f jal x0, 362 + 19253500 19238 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19254500 19239 1c001d36 e69ff06f jal x0, -408 + 19257500 19242 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19272500 19257 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19273500 19258 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19276500 19261 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19277500 19262 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19278500 19263 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19280500 19265 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19281500 19266 1c001778 fddff06f jal x0, -36 + 19283500 19268 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19284500 19269 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19285500 19270 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19286500 19271 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19287500 19272 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19288500 19273 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19289500 19274 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19290500 19275 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19291500 19276 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19292500 19277 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104008 + 19296500 19281 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19297500 19282 1c001bca 16a0006f jal x0, 362 + 19299500 19284 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19300500 19285 1c001d36 e69ff06f jal x0, -408 + 19303500 19288 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19318500 19303 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19319500 19304 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19322500 19307 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19323500 19308 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19324500 19309 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19326500 19311 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19327500 19312 1c001778 fddff06f jal x0, -36 + 19329500 19314 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19330500 19315 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19331500 19316 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19332500 19317 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19333500 19318 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19334500 19319 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19335500 19320 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19336500 19321 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19337500 19322 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19338500 19323 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104008 + 19342500 19327 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19343500 19328 1c001bca 16a0006f jal x0, 362 + 19345500 19330 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19346500 19331 1c001d36 e69ff06f jal x0, -408 + 19349500 19334 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19370500 19355 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19371500 19356 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19374500 19359 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19375500 19360 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19376500 19361 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19378500 19363 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19379500 19364 1c001778 fddff06f jal x0, -36 + 19381500 19366 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19382500 19367 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19383500 19368 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19384500 19369 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19385500 19370 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19386500 19371 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19387500 19372 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19388500 19373 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19389500 19374 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19390500 19375 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104008 + 19394500 19379 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19395500 19380 1c001bca 16a0006f jal x0, 362 + 19397500 19382 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19398500 19383 1c001d36 e69ff06f jal x0, -408 + 19401500 19386 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19420500 19405 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19421500 19406 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19424500 19409 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19425500 19410 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19426500 19411 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19428500 19413 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19429500 19414 1c001778 fddff06f jal x0, -36 + 19431500 19416 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19432500 19417 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19433500 19418 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19434500 19419 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19435500 19420 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19436500 19421 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19437500 19422 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19438500 19423 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19439500 19424 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19440500 19425 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104008 + 19444500 19429 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19445500 19430 1c001bca 16a0006f jal x0, 362 + 19447500 19432 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19448500 19433 1c001d36 e69ff06f jal x0, -408 + 19451500 19436 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19471500 19456 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19472500 19457 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19475500 19460 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19476500 19461 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19477500 19462 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19479500 19464 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19480500 19465 1c001778 fddff06f jal x0, -36 + 19482500 19467 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19483500 19468 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19484500 19469 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19485500 19470 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19486500 19471 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19487500 19472 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19488500 19473 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19489500 19474 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19490500 19475 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19491500 19476 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104008 + 19495500 19480 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19496500 19481 1c001bca 16a0006f jal x0, 362 + 19498500 19483 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19499500 19484 1c001d36 e69ff06f jal x0, -408 + 19502500 19487 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19521500 19506 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19522500 19507 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19525500 19510 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19526500 19511 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19527500 19512 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19529500 19514 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19530500 19515 1c001778 fddff06f jal x0, -36 + 19532500 19517 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19533500 19518 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19534500 19519 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19535500 19520 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19536500 19521 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19537500 19522 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19538500 19523 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19539500 19524 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19540500 19525 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19541500 19526 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104008 + 19545500 19530 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19546500 19531 1c001bca 16a0006f jal x0, 362 + 19548500 19533 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19549500 19534 1c001d36 e69ff06f jal x0, -408 + 19552500 19537 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19577500 19562 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19578500 19563 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19581500 19566 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19582500 19567 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19583500 19568 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19585500 19570 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19586500 19571 1c001778 fddff06f jal x0, -36 + 19588500 19573 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19589500 19574 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19590500 19575 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19591500 19576 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19592500 19577 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19593500 19578 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19594500 19579 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19595500 19580 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19596500 19581 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19597500 19582 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104008 + 19601500 19586 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19602500 19587 1c001bca 16a0006f jal x0, 362 + 19604500 19589 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19605500 19590 1c001d36 e69ff06f jal x0, -408 + 19608500 19593 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19622500 19607 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19623500 19608 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19626500 19611 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19627500 19612 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19628500 19613 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19630500 19615 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19631500 19616 1c001778 fddff06f jal x0, -36 + 19633500 19618 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19634500 19619 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19635500 19620 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19636500 19621 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19637500 19622 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19638500 19623 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19639500 19624 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19640500 19625 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19641500 19626 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19642500 19627 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104008 + 19646500 19631 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19647500 19632 1c001bca 16a0006f jal x0, 362 + 19649500 19634 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19650500 19635 1c001d36 e69ff06f jal x0, -408 + 19653500 19638 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19667500 19652 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19668500 19653 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19671500 19656 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19672500 19657 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19673500 19658 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19675500 19660 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19676500 19661 1c001778 fddff06f jal x0, -36 + 19678500 19663 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19679500 19664 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19680500 19665 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19681500 19666 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19682500 19667 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19683500 19668 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19684500 19669 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19685500 19670 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19686500 19671 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19687500 19672 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104008 + 19691500 19676 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19692500 19677 1c001bca 16a0006f jal x0, 362 + 19694500 19679 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19695500 19680 1c001d36 e69ff06f jal x0, -408 + 19698500 19683 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19716500 19701 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19717500 19702 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19720500 19705 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19721500 19706 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19722500 19707 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19724500 19709 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19725500 19710 1c001778 fddff06f jal x0, -36 + 19727500 19712 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19728500 19713 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19729500 19714 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19730500 19715 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19731500 19716 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19732500 19717 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19733500 19718 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19734500 19719 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19735500 19720 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19736500 19721 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104008 + 19740500 19725 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19741500 19726 1c001bca 16a0006f jal x0, 362 + 19743500 19728 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19744500 19729 1c001d36 e69ff06f jal x0, -408 + 19747500 19732 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19761500 19746 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19762500 19747 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19765500 19750 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19766500 19751 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19767500 19752 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19769500 19754 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19770500 19755 1c001778 fddff06f jal x0, -36 + 19772500 19757 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19773500 19758 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19774500 19759 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19775500 19760 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19776500 19761 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19777500 19762 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19778500 19763 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19779500 19764 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19780500 19765 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19781500 19766 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104008 + 19785500 19770 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19786500 19771 1c001bca 16a0006f jal x0, 362 + 19788500 19773 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19789500 19774 1c001d36 e69ff06f jal x0, -408 + 19792500 19777 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19809500 19794 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19810500 19795 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19813500 19798 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19814500 19799 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19815500 19800 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19817500 19802 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19818500 19803 1c001778 fddff06f jal x0, -36 + 19820500 19805 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19821500 19806 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 19822500 19807 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19823500 19808 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 19824500 19809 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 19825500 19810 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 19826500 19811 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 19827500 19812 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 19828500 19813 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19829500 19814 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104008 + 19833500 19818 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19834500 19819 1c001bca 16a0006f jal x0, 362 + 19836500 19821 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19837500 19822 1c001d36 e69ff06f jal x0, -408 + 19840500 19825 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19857500 19842 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19858500 19843 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19861500 19846 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19864500 19849 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100fcef0 PA:100fcef4 + 19876500 19861 1c001bd0 00012423 sw x0, 8(x2) x2:100fcef0 PA:100fcef8 + 19877500 19862 1c001bd2 00010623 sb x0, 12(x2) x2:100fcef0 PA:100fcefc + 19878500 19863 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19879500 19864 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19896500 19881 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19897500 19882 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fcef0 PA:100fcef4 + 19899500 19884 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19900500 19885 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19901500 19886 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19902500 19887 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19903500 19888 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19938500 19923 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19947500 19932 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fcef0 PA:100fcf00 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=100fcf78 x8:100fcf74 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:100fcf74 PA:100fcf74 + 20311500 20296 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100fcef4 x2:100fcef0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100fcf08 x11:100fcef4 PA:100fcf04 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fcef4 PA:100fcf00 + 20403500 20388 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20404500 20389 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20438500 20423 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20439500 20424 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20440500 20425 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20441500 20426 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20444500 20429 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fcef4 PA:100fcf00 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100fcf08 PA:100fcf08 + 20590500 20575 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20591500 20576 1c001a5e 00168693 addi x13, x13, 1 x13=100fcf09 x13:100fcf08 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100fcf09 PA:100fcf09 + 20605500 20590 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20607500 20592 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100fcef4 x2:100fcef0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100fced0 x2:100fcef0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:100fcf74 x2:100fced0 PA:100fcee8 + 20653500 20638 1c001a66 01062783 lw x15, 16(x12) x15=100fcf08 x12:100fcef4 PA:100fcf04 + 20654500 20639 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fcef4 PA:100fcef8 + 20655500 20640 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100fced0 PA:100fcee4 + 20656500 20641 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fced0 PA:100fcee0 + 20657500 20642 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fced0 PA:100fcedc + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fced0 PA:100fceec + 20674500 20659 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fced0 PA:100fced8 + 20675500 20660 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20676500 20661 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20677500 20662 1c001a78 00c004b3 add x9, x0, x12 x9=100fcef4 x12:100fcef4 + 20678500 20663 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100fcf09 x15:100fcf08 PA:100fcf08 + 20680500 20665 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fcef4 PA:100fcefc + 20701500 20686 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20704500 20689 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fcef4 PA:100fcefc + 20795500 20780 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 20816500 20801 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20817500 20802 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fcf08 x9:100fcef4 PA:100fcf04 + 20857500 20842 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100fcf09 x20:100fcf08 PA:100fcf08 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104008 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fcf0a x20:100fcf09 PA:100fcf09 + 20938500 20923 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20939500 20924 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 20941500 20926 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20942500 20927 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fced0 PA:100fceec + 20959500 20944 1c001b02 01812403 lw x8, 24(x2) x8=100fcf74 x2:100fced0 PA:100fcee8 + 20960500 20945 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100fced0 PA:100fcee4 + 20961500 20946 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fced0 PA:100fcee0 + 20962500 20947 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fced0 PA:100fcedc + 20963500 20948 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fced0 PA:100fced8 + 20964500 20949 1c001b0c 02010113 addi x2, x2, 32 x2=100fcef0 x2:100fced0 + 20965500 20950 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=100fcf78 x24:100fcf78 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21005500 20990 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21006500 20991 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21009500 20994 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21010500 20995 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21011500 20996 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21013500 20998 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21014500 20999 1c001778 fddff06f jal x0, -36 + 21016500 21001 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21017500 21002 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 21018500 21003 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21019500 21004 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 21020500 21005 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 21021500 21006 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 21022500 21007 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 21023500 21008 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 21024500 21009 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21025500 21010 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104008 + 21029500 21014 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21030500 21015 1c001bca 16a0006f jal x0, 362 + 21032500 21017 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21033500 21018 1c001d36 e69ff06f jal x0, -408 + 21036500 21021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21050500 21035 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21051500 21036 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21054500 21039 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21055500 21040 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21056500 21041 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21058500 21043 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21059500 21044 1c001778 fddff06f jal x0, -36 + 21061500 21046 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21062500 21047 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 21063500 21048 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21064500 21049 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 21065500 21050 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 21066500 21051 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 21067500 21052 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 21068500 21053 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 21069500 21054 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21070500 21055 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104008 + 21074500 21059 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21075500 21060 1c001bca 16a0006f jal x0, 362 + 21077500 21062 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21078500 21063 1c001d36 e69ff06f jal x0, -408 + 21081500 21066 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21096500 21081 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21097500 21082 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21100500 21085 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21103500 21088 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100fcef0 PA:100fcef4 + 21104500 21089 1c001bd0 00012423 sw x0, 8(x2) x2:100fcef0 PA:100fcef8 + 21105500 21090 1c001bd2 00010623 sb x0, 12(x2) x2:100fcef0 PA:100fcefc + 21106500 21091 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21107500 21092 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21108500 21093 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21109500 21094 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fcef0 PA:100fcef4 + 21110500 21095 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21111500 21096 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21112500 21097 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21113500 21098 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21114500 21099 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21115500 21100 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21116500 21101 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21117500 21102 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21133500 21118 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21134500 21119 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21137500 21122 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21138500 21123 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21139500 21124 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21142500 21127 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21145500 21130 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21148500 21133 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21151500 21136 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21152500 21137 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21153500 21138 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21154500 21139 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21157500 21142 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21158500 21143 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21161500 21146 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21162500 21147 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21165500 21150 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21167500 21152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21170500 21155 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21171500 21156 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21174500 21159 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21175500 21160 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21176500 21161 1c001f42 e09ff06f jal x0, -504 + 21178500 21163 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21179500 21164 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fcef0 PA:100fcf00 + 21180500 21165 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21183500 21168 1c001e34 00440c13 addi x24, x8, 4 x24=100fcf7c x8:100fcf78 + 21184500 21169 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:100fcf78 PA:100fcf78 + 21185500 21170 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21188500 21173 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 21191500 21176 1c001e64 00410593 addi x11, x2, 4 x11=100fcef4 x2:100fcef0 + 21192500 21177 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21194500 21179 1c0019fe 0105a683 lw x13, 16(x11) x13=100fcf08 x11:100fcef4 PA:100fcf04 + 21195500 21180 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fcef4 PA:100fcf00 + 21197500 21182 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21198500 21183 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 21232500 21217 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 21233500 21218 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21234500 21219 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21235500 21220 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21238500 21223 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fcef4 PA:100fcf00 + 21239500 21224 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 21273500 21258 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 21307500 21292 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21338500 21323 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21339500 21324 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 21342500 21327 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21360500 21345 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 21363500 21348 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 21364500 21349 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:100fcf08 PA:100fcf08 + 21366500 21351 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21367500 21352 1c001a5e 00168693 addi x13, x13, 1 x13=100fcf09 x13:100fcf08 + 21368500 21353 1c001a60 fb1ff06f jal x0, -80 + 21370500 21355 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21371500 21356 1c001a12 00068023 sb x0, 0(x13) x13:100fcf09 PA:100fcf09 + 21372500 21357 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21374500 21359 1c001e68 f17ff06f jal x0, -234 + 21376500 21361 1c001d7e 00410613 addi x12, x2, 4 x12=100fcef4 x2:100fcef0 + 21377500 21362 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21378500 21363 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21379500 21364 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21381500 21366 1c001a62 fe010113 addi x2, x2, -32 x2=100fced0 x2:100fcef0 + 21382500 21367 1c001a64 00812c23 sw x8, 24(x2) x8:100fcf78 x2:100fced0 PA:100fcee8 + 21383500 21368 1c001a66 01062783 lw x15, 16(x12) x15=100fcf08 x12:100fcef4 PA:100fcf04 + 21384500 21369 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fcef4 PA:100fcef8 + 21385500 21370 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100fced0 PA:100fcee4 + 21386500 21371 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fced0 PA:100fcee0 + 21387500 21372 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fced0 PA:100fcedc + 21388500 21373 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fced0 PA:100fceec + 21389500 21374 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fced0 PA:100fced8 + 21390500 21375 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21391500 21376 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21392500 21377 1c001a78 00c004b3 add x9, x0, x12 x9=100fcef4 x12:100fcef4 + 21393500 21378 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=100fcf09 x15:100fcf08 PA:100fcf08 + 21395500 21380 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 21396500 21381 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21397500 21382 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fcef4 PA:100fcefc + 21399500 21384 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21402500 21387 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 21404500 21389 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21405500 21390 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21408500 21393 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21409500 21394 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21410500 21395 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21413500 21398 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21414500 21399 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21415500 21400 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21416500 21401 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21417500 21402 1c001b36 f71ff06f jal x0, -144 + 21419500 21404 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fcef4 PA:100fcefc + 21421500 21406 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21424500 21409 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 21426500 21411 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21427500 21412 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21430500 21415 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 21431500 21416 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21432500 21417 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21433500 21418 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21434500 21419 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fcf08 x9:100fcef4 PA:100fcf04 + 21436500 21421 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=100fcf09 x20:100fcf08 PA:100fcf08 + 21438500 21423 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 21441500 21426 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21442500 21427 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21444500 21429 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 21445500 21430 1c001778 fddff06f jal x0, -36 + 21447500 21432 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21448500 21433 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 21449500 21434 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21450500 21435 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 21451500 21436 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 21452500 21437 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 21453500 21438 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 21454500 21439 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 21455500 21440 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21456500 21441 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104008 + 21460500 21445 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21461500 21446 1c001b62 f8bff06f jal x0, -118 + 21463500 21448 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fcf0a x20:100fcf09 PA:100fcf09 + 21465500 21450 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21466500 21451 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fcef4 PA:100fcef4 + 21468500 21453 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21469500 21454 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21472500 21457 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fced0 PA:100fceec + 21473500 21458 1c001b02 01812403 lw x8, 24(x2) x8=100fcf78 x2:100fced0 PA:100fcee8 + 21474500 21459 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100fced0 PA:100fcee4 + 21475500 21460 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fced0 PA:100fcee0 + 21476500 21461 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fced0 PA:100fcedc + 21477500 21462 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fced0 PA:100fced8 + 21478500 21463 1c001b0c 02010113 addi x2, x2, 32 x2=100fcef0 x2:100fced0 + 21479500 21464 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21481500 21466 1c001d86 01800433 add x8, x0, x24 x8=100fcf7c x24:100fcf7c + 21482500 21467 1c001d88 fadff06f jal x0, -84 + 21484500 21469 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21485500 21470 1c001d36 e69ff06f jal x0, -408 + 21488500 21473 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21504500 21489 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21505500 21490 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21508500 21493 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21509500 21494 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21510500 21495 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21512500 21497 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21513500 21498 1c001778 fddff06f jal x0, -36 + 21515500 21500 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21516500 21501 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 21517500 21502 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21518500 21503 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 21519500 21504 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 21520500 21505 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 21521500 21506 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 21522500 21507 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 21523500 21508 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21524500 21509 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104008 + 21528500 21513 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21529500 21514 1c001bca 16a0006f jal x0, 362 + 21531500 21516 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21532500 21517 1c001d36 e69ff06f jal x0, -408 + 21535500 21520 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21550500 21535 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21551500 21536 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21554500 21539 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21555500 21540 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21556500 21541 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21558500 21543 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21559500 21544 1c001778 fddff06f jal x0, -36 + 21561500 21546 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21562500 21547 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 21563500 21548 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21564500 21549 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 21565500 21550 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 21566500 21551 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 21567500 21552 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 21568500 21553 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 21569500 21554 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21570500 21555 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104008 + 21574500 21559 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21575500 21560 1c001bca 16a0006f jal x0, 362 + 21577500 21562 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21578500 21563 1c001d36 e69ff06f jal x0, -408 + 21581500 21566 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21596500 21581 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21597500 21582 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21600500 21585 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21601500 21586 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21602500 21587 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21604500 21589 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21605500 21590 1c001778 fddff06f jal x0, -36 + 21607500 21592 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21608500 21593 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000001 + 21609500 21594 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21610500 21595 1c00175e 00379713 slli x14, x15, 0x3 x14=00000008 x15:00000001 + 21611500 21596 1c001762 00279793 slli x15, x15, 0x2 x15=00000004 x15:00000001 + 21612500 21597 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000008 + 21613500 21598 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000004 x13:00001f80 + 21614500 21599 1c00176a 00e787b3 add x15, x15, x14 x15=00000008 x15:00000000 x14:00000008 + 21615500 21600 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21616500 21601 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104008 + 21620500 21605 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21621500 21606 1c001bca 16a0006f jal x0, 362 + 21623500 21608 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21624500 21609 1c001d36 e69ff06f jal x0, -408 + 21627500 21612 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21642500 21627 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21643500 21628 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21644500 21629 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100fcef0 PA:100fcf4c + 21645500 21630 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100fcef0 PA:100fcf48 + 21646500 21631 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:100fcef0 PA:100fcf44 + 21647500 21632 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:100fcef0 PA:100fcf40 + 21648500 21633 1c001bb0 04c12983 lw x19, 76(x2) x19=00000001 x2:100fcef0 PA:100fcf3c + 21649500 21634 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:100fcef0 PA:100fcf38 + 21650500 21635 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:100fcef0 PA:100fcf34 + 21651500 21636 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100fcef0 PA:100fcf30 + 21652500 21637 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100fcef0 PA:100fcf2c + 21653500 21638 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100fcef0 PA:100fcf28 + 21654500 21639 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100fcef0 PA:100fcf24 + 21655500 21640 1c001bbe 06010113 addi x2, x2, 96 x2=100fcf50 x2:100fcef0 + 21656500 21641 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21658500 21643 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:100fcf50 PA:100fcf6c + 21659500 21644 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21660500 21645 1c001838 04010113 addi x2, x2, 64 x2=100fcf90 x2:100fcf50 + 21661500 21646 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21676500 21661 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_00_2.log b/sw/scripts/tracevis/example/traces/trace_core_00_2.log new file mode 100644 index 0000000..6c6578f --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_00_2.log @@ -0,0 +1,847 @@ + Time Cycles PC Instr Mnemonic + 98500 83 1c000080 0180006f jal x0, 24 + 122500 107 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000002 + 123500 108 1c00009c 01f57593 andi x11, x10, 31 x11=00000002 x10:00000002 + 146500 131 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000000 x10:00000002 + 147500 132 1c0000a2 00058463 beq x11, x0, 8 x11:00000002 + 148500 133 1c0000a6 05a0206f jal x0, 8282 + 169500 154 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 170500 155 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 171500 156 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 172500 157 1c00210c 0e059163 bne x11, x0, 226 x11:00000002 + 242500 227 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 243500 228 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000002 + 244500 229 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000002 x19:00000002 + 245500 230 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 262500 247 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 263500 248 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 264500 249 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 265500 250 1c00220a 0060006f jal x0, 6 + 287500 272 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 9629500 9614 1c002214 08096503 p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080 + 9637500 9622 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 9638500 9623 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 9656500 9641 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 9657500 9642 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 9659500 9644 1c00222c 08096283 p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080 + 9683500 9668 1c002230 02a98533 mul x10, x19, x10 x10=00001000 x19:00000002 x10:00000800 + 9684500 9669 1c002234 00550133 add x2, x10, x5 x2=100fd790 x10:00001000 x5:100fc790 + 9685500 9670 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 9705500 9690 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18829500 18814 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18837500 18822 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18838500 18823 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18839500 18824 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18840500 18825 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18863500 18848 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000002 + 18883500 18868 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18884500 18869 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000000 x12:00000002 + 18885500 18870 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000 + 18886500 18871 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000002 x12:00000002 + 18887500 18872 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18888500 18873 1c0009d4 63d0006f jal x0, 3644 + 18890500 18875 1c001810 fc010113 addi x2, x2, -64 x2=100fd750 x2:100fd790 + 18891500 18876 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:100fd750 PA:100fd774 + 18897500 18882 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18898500 18883 1c001818 02c12423 sw x12, 40(x2) x12:00000002 x2:100fd750 PA:100fd778 + 18899500 18884 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:100fd750 PA:100fd77c + 18900500 18885 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18901500 18886 1c00181e 02410693 addi x13, x2, 36 x13=100fd774 x2:100fd750 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:100fd750 PA:100fd76c + 18919500 18904 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:100fd750 PA:100fd780 + 18920500 18905 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:100fd750 PA:100fd784 + 18921500 18906 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:100fd750 PA:100fd788 + 18922500 18907 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:100fd750 PA:100fd78c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:100fd774 x2:100fd750 PA:100fd75c + 18938500 18923 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100fd6f0 x2:100fd750 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100fd708 x2:100fd6f0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100fd6f0 PA:100fd748 + 18961500 18946 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:100fd6f0 PA:100fd740 + 18962500 18947 1c001b78 05312623 sw x19, 76(x2) x19:00000002 x2:100fd6f0 PA:100fd73c + 18963500 18948 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:100fd6f0 PA:100fd738 + 18964500 18949 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:100fd6f0 PA:100fd734 + 18965500 18950 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100fd6f0 PA:100fd730 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100fd6f0 PA:100fd72c + 18987500 18972 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100fd6f0 PA:100fd74c + 18988500 18973 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:100fd6f0 PA:100fd744 + 18989500 18974 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100fd6f0 PA:100fd728 + 18990500 18975 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100fd6f0 PA:100fd724 + 18991500 18976 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18992500 18977 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18993500 18978 1c001b8e 00d00433 add x8, x0, x13 x8=100fd774 x13:100fd774 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100fd708 x2:100fd6f0 PA:100fd704 + 19014500 18999 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19015500 19000 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19016500 19001 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19017500 19002 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19055500 19040 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19056500 19041 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104010 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19175500 19160 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19176500 19161 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19179500 19164 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19180500 19165 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19181500 19166 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19183500 19168 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19184500 19169 1c001778 fddff06f jal x0, -36 + 19186500 19171 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19187500 19172 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19188500 19173 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19189500 19174 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19190500 19175 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19191500 19176 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19192500 19177 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19193500 19178 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19194500 19179 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19195500 19180 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104010 + 19199500 19184 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19200500 19185 1c001bca 16a0006f jal x0, 362 + 19202500 19187 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19203500 19188 1c001d36 e69ff06f jal x0, -408 + 19206500 19191 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19227500 19212 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19228500 19213 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19231500 19216 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19232500 19217 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19233500 19218 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19235500 19220 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19236500 19221 1c001778 fddff06f jal x0, -36 + 19238500 19223 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19239500 19224 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19240500 19225 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19241500 19226 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19242500 19227 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19243500 19228 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19244500 19229 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19245500 19230 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19246500 19231 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19247500 19232 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104010 + 19251500 19236 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19252500 19237 1c001bca 16a0006f jal x0, 362 + 19254500 19239 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19255500 19240 1c001d36 e69ff06f jal x0, -408 + 19258500 19243 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19276500 19261 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19277500 19262 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19280500 19265 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19281500 19266 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19282500 19267 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19284500 19269 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19285500 19270 1c001778 fddff06f jal x0, -36 + 19287500 19272 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19288500 19273 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19289500 19274 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19290500 19275 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19291500 19276 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19292500 19277 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19293500 19278 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19294500 19279 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19295500 19280 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19296500 19281 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104010 + 19300500 19285 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19301500 19286 1c001bca 16a0006f jal x0, 362 + 19303500 19288 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19304500 19289 1c001d36 e69ff06f jal x0, -408 + 19307500 19292 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19321500 19306 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19322500 19307 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19325500 19310 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19326500 19311 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19327500 19312 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19329500 19314 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19330500 19315 1c001778 fddff06f jal x0, -36 + 19332500 19317 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19333500 19318 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19334500 19319 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19335500 19320 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19336500 19321 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19337500 19322 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19338500 19323 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19339500 19324 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19340500 19325 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19341500 19326 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104010 + 19345500 19330 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19346500 19331 1c001bca 16a0006f jal x0, 362 + 19348500 19333 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19349500 19334 1c001d36 e69ff06f jal x0, -408 + 19352500 19337 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19373500 19358 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19374500 19359 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19377500 19362 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19378500 19363 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19379500 19364 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19381500 19366 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19382500 19367 1c001778 fddff06f jal x0, -36 + 19384500 19369 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19385500 19370 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19386500 19371 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19387500 19372 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19388500 19373 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19389500 19374 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19390500 19375 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19391500 19376 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19392500 19377 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19393500 19378 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104010 + 19397500 19382 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19398500 19383 1c001bca 16a0006f jal x0, 362 + 19400500 19385 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19401500 19386 1c001d36 e69ff06f jal x0, -408 + 19404500 19389 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19423500 19408 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19424500 19409 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19427500 19412 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19428500 19413 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19429500 19414 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19431500 19416 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19432500 19417 1c001778 fddff06f jal x0, -36 + 19434500 19419 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19435500 19420 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19436500 19421 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19437500 19422 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19438500 19423 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19439500 19424 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19440500 19425 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19441500 19426 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19442500 19427 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19443500 19428 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104010 + 19447500 19432 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19448500 19433 1c001bca 16a0006f jal x0, 362 + 19450500 19435 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19451500 19436 1c001d36 e69ff06f jal x0, -408 + 19454500 19439 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19473500 19458 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19474500 19459 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19477500 19462 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19478500 19463 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19479500 19464 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19481500 19466 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19482500 19467 1c001778 fddff06f jal x0, -36 + 19484500 19469 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19485500 19470 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19486500 19471 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19487500 19472 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19488500 19473 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19489500 19474 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19490500 19475 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19491500 19476 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19492500 19477 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19493500 19478 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104010 + 19497500 19482 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19498500 19483 1c001bca 16a0006f jal x0, 362 + 19500500 19485 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19501500 19486 1c001d36 e69ff06f jal x0, -408 + 19504500 19489 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19522500 19507 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19523500 19508 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19526500 19511 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19527500 19512 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19528500 19513 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19530500 19515 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19531500 19516 1c001778 fddff06f jal x0, -36 + 19533500 19518 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19534500 19519 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19535500 19520 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19536500 19521 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19537500 19522 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19538500 19523 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19539500 19524 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19540500 19525 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19541500 19526 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19542500 19527 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104010 + 19546500 19531 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19547500 19532 1c001bca 16a0006f jal x0, 362 + 19549500 19534 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19550500 19535 1c001d36 e69ff06f jal x0, -408 + 19553500 19538 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19580500 19565 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19581500 19566 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19584500 19569 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19585500 19570 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19586500 19571 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19588500 19573 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19589500 19574 1c001778 fddff06f jal x0, -36 + 19591500 19576 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19592500 19577 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19593500 19578 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19594500 19579 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19595500 19580 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19596500 19581 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19597500 19582 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19598500 19583 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19599500 19584 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19600500 19585 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104010 + 19604500 19589 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19605500 19590 1c001bca 16a0006f jal x0, 362 + 19607500 19592 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19608500 19593 1c001d36 e69ff06f jal x0, -408 + 19611500 19596 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19626500 19611 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19627500 19612 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19630500 19615 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19631500 19616 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19632500 19617 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19634500 19619 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19635500 19620 1c001778 fddff06f jal x0, -36 + 19637500 19622 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19638500 19623 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19639500 19624 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19640500 19625 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19641500 19626 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19642500 19627 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19643500 19628 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19644500 19629 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19645500 19630 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19646500 19631 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104010 + 19650500 19635 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19651500 19636 1c001bca 16a0006f jal x0, 362 + 19653500 19638 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19654500 19639 1c001d36 e69ff06f jal x0, -408 + 19657500 19642 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19673500 19658 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19674500 19659 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19677500 19662 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19678500 19663 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19679500 19664 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19681500 19666 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19682500 19667 1c001778 fddff06f jal x0, -36 + 19684500 19669 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19685500 19670 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19686500 19671 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19687500 19672 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19688500 19673 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19689500 19674 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19690500 19675 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19691500 19676 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19692500 19677 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19693500 19678 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104010 + 19697500 19682 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19698500 19683 1c001bca 16a0006f jal x0, 362 + 19700500 19685 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19701500 19686 1c001d36 e69ff06f jal x0, -408 + 19704500 19689 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19718500 19703 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19719500 19704 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19722500 19707 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19723500 19708 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19724500 19709 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19726500 19711 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19727500 19712 1c001778 fddff06f jal x0, -36 + 19729500 19714 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19730500 19715 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19731500 19716 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19732500 19717 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19733500 19718 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19734500 19719 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19735500 19720 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19736500 19721 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19737500 19722 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19738500 19723 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104010 + 19742500 19727 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19743500 19728 1c001bca 16a0006f jal x0, 362 + 19745500 19730 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19746500 19731 1c001d36 e69ff06f jal x0, -408 + 19749500 19734 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19763500 19748 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19764500 19749 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19767500 19752 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19768500 19753 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19769500 19754 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19771500 19756 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19772500 19757 1c001778 fddff06f jal x0, -36 + 19774500 19759 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19775500 19760 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19776500 19761 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19777500 19762 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19778500 19763 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19779500 19764 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19780500 19765 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19781500 19766 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19782500 19767 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19783500 19768 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104010 + 19787500 19772 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19788500 19773 1c001bca 16a0006f jal x0, 362 + 19790500 19775 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19791500 19776 1c001d36 e69ff06f jal x0, -408 + 19794500 19779 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19811500 19796 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19812500 19797 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19815500 19800 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19816500 19801 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19817500 19802 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19819500 19804 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19820500 19805 1c001778 fddff06f jal x0, -36 + 19822500 19807 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19823500 19808 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 19824500 19809 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19825500 19810 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 19826500 19811 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 19827500 19812 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 19828500 19813 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 19829500 19814 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 19830500 19815 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19831500 19816 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104010 + 19835500 19820 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19836500 19821 1c001bca 16a0006f jal x0, 362 + 19838500 19823 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19839500 19824 1c001d36 e69ff06f jal x0, -408 + 19842500 19827 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19861500 19846 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19862500 19847 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19865500 19850 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19868500 19853 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100fd6f0 PA:100fd6f4 + 19876500 19861 1c001bd0 00012423 sw x0, 8(x2) x2:100fd6f0 PA:100fd6f8 + 19878500 19863 1c001bd2 00010623 sb x0, 12(x2) x2:100fd6f0 PA:100fd6fc + 19879500 19864 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19880500 19865 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19896500 19881 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19897500 19882 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fd6f0 PA:100fd6f4 + 19901500 19886 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19902500 19887 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19903500 19888 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19904500 19889 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19905500 19890 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19946500 19931 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19947500 19932 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fd6f0 PA:100fd700 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=100fd778 x8:100fd774 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:100fd774 PA:100fd774 + 20313500 20298 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100fd6f4 x2:100fd6f0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100fd708 x11:100fd6f4 PA:100fd704 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fd6f4 PA:100fd700 + 20405500 20390 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20406500 20391 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20440500 20425 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20441500 20426 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20442500 20427 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20443500 20428 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20446500 20431 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fd6f4 PA:100fd700 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100fd708 PA:100fd708 + 20584500 20569 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20585500 20570 1c001a5e 00168693 addi x13, x13, 1 x13=100fd709 x13:100fd708 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100fd709 PA:100fd709 + 20606500 20591 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20607500 20592 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100fd6f4 x2:100fd6f0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100fd6d0 x2:100fd6f0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:100fd774 x2:100fd6d0 PA:100fd6e8 + 20654500 20639 1c001a66 01062783 lw x15, 16(x12) x15=100fd708 x12:100fd6f4 PA:100fd704 + 20655500 20640 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fd6f4 PA:100fd6f8 + 20656500 20641 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100fd6d0 PA:100fd6e4 + 20657500 20642 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fd6d0 PA:100fd6e0 + 20658500 20643 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fd6d0 PA:100fd6dc + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fd6d0 PA:100fd6ec + 20676500 20661 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fd6d0 PA:100fd6d8 + 20677500 20662 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20678500 20663 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20679500 20664 1c001a78 00c004b3 add x9, x0, x12 x9=100fd6f4 x12:100fd6f4 + 20680500 20665 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100fd709 x15:100fd708 PA:100fd708 + 20682500 20667 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fd6f4 PA:100fd6fc + 20703500 20688 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20706500 20691 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fd6f4 PA:100fd6fc + 20797500 20782 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 20818500 20803 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20819500 20804 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fd708 x9:100fd6f4 PA:100fd704 + 20859500 20844 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100fd709 x20:100fd708 PA:100fd708 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104010 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fd70a x20:100fd709 PA:100fd709 + 20939500 20924 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20940500 20925 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 20942500 20927 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20943500 20928 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fd6d0 PA:100fd6ec + 20961500 20946 1c001b02 01812403 lw x8, 24(x2) x8=100fd774 x2:100fd6d0 PA:100fd6e8 + 20962500 20947 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100fd6d0 PA:100fd6e4 + 20963500 20948 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fd6d0 PA:100fd6e0 + 20964500 20949 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fd6d0 PA:100fd6dc + 20965500 20950 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fd6d0 PA:100fd6d8 + 20966500 20951 1c001b0c 02010113 addi x2, x2, 32 x2=100fd6f0 x2:100fd6d0 + 20967500 20952 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=100fd778 x24:100fd778 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21007500 20992 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21008500 20993 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21011500 20996 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21012500 20997 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21013500 20998 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21015500 21000 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21016500 21001 1c001778 fddff06f jal x0, -36 + 21018500 21003 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21019500 21004 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 21020500 21005 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21021500 21006 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 21022500 21007 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 21023500 21008 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 21024500 21009 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 21025500 21010 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 21026500 21011 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21027500 21012 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104010 + 21031500 21016 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21032500 21017 1c001bca 16a0006f jal x0, 362 + 21034500 21019 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21035500 21020 1c001d36 e69ff06f jal x0, -408 + 21038500 21023 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21052500 21037 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21053500 21038 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21056500 21041 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21057500 21042 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21058500 21043 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21060500 21045 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21061500 21046 1c001778 fddff06f jal x0, -36 + 21063500 21048 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21064500 21049 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 21065500 21050 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21066500 21051 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 21067500 21052 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 21068500 21053 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 21069500 21054 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 21070500 21055 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 21071500 21056 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21072500 21057 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104010 + 21076500 21061 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21077500 21062 1c001bca 16a0006f jal x0, 362 + 21079500 21064 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21080500 21065 1c001d36 e69ff06f jal x0, -408 + 21083500 21068 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21100500 21085 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21101500 21086 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21104500 21089 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21107500 21092 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100fd6f0 PA:100fd6f4 + 21108500 21093 1c001bd0 00012423 sw x0, 8(x2) x2:100fd6f0 PA:100fd6f8 + 21109500 21094 1c001bd2 00010623 sb x0, 12(x2) x2:100fd6f0 PA:100fd6fc + 21110500 21095 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21111500 21096 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21112500 21097 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21113500 21098 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fd6f0 PA:100fd6f4 + 21115500 21100 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21116500 21101 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21117500 21102 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21118500 21103 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21119500 21104 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21120500 21105 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21121500 21106 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21122500 21107 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21136500 21121 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21137500 21122 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21140500 21125 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21141500 21126 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21142500 21127 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21145500 21130 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21148500 21133 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21151500 21136 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21154500 21139 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21155500 21140 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21156500 21141 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21157500 21142 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21160500 21145 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21161500 21146 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21164500 21149 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21165500 21150 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21168500 21153 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21170500 21155 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21173500 21158 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21174500 21159 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21177500 21162 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21178500 21163 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21179500 21164 1c001f42 e09ff06f jal x0, -504 + 21181500 21166 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21182500 21167 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fd6f0 PA:100fd700 + 21183500 21168 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21186500 21171 1c001e34 00440c13 addi x24, x8, 4 x24=100fd77c x8:100fd778 + 21187500 21172 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:100fd778 PA:100fd778 + 21188500 21173 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21191500 21176 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 21194500 21179 1c001e64 00410593 addi x11, x2, 4 x11=100fd6f4 x2:100fd6f0 + 21195500 21180 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21197500 21182 1c0019fe 0105a683 lw x13, 16(x11) x13=100fd708 x11:100fd6f4 PA:100fd704 + 21198500 21183 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fd6f4 PA:100fd700 + 21199500 21184 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21200500 21185 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 21234500 21219 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 21235500 21220 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21236500 21221 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21237500 21222 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21240500 21225 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fd6f4 PA:100fd700 + 21241500 21226 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 21275500 21260 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 21309500 21294 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21340500 21325 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21341500 21326 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 21344500 21329 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21360500 21345 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 21363500 21348 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 21364500 21349 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:100fd708 PA:100fd708 + 21368500 21353 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21369500 21354 1c001a5e 00168693 addi x13, x13, 1 x13=100fd709 x13:100fd708 + 21370500 21355 1c001a60 fb1ff06f jal x0, -80 + 21372500 21357 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21373500 21358 1c001a12 00068023 sb x0, 0(x13) x13:100fd709 PA:100fd709 + 21374500 21359 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21376500 21361 1c001e68 f17ff06f jal x0, -234 + 21378500 21363 1c001d7e 00410613 addi x12, x2, 4 x12=100fd6f4 x2:100fd6f0 + 21379500 21364 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21380500 21365 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21381500 21366 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21383500 21368 1c001a62 fe010113 addi x2, x2, -32 x2=100fd6d0 x2:100fd6f0 + 21384500 21369 1c001a64 00812c23 sw x8, 24(x2) x8:100fd778 x2:100fd6d0 PA:100fd6e8 + 21385500 21370 1c001a66 01062783 lw x15, 16(x12) x15=100fd708 x12:100fd6f4 PA:100fd704 + 21386500 21371 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fd6f4 PA:100fd6f8 + 21387500 21372 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100fd6d0 PA:100fd6e4 + 21388500 21373 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fd6d0 PA:100fd6e0 + 21389500 21374 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fd6d0 PA:100fd6dc + 21390500 21375 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fd6d0 PA:100fd6ec + 21391500 21376 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fd6d0 PA:100fd6d8 + 21392500 21377 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21393500 21378 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21394500 21379 1c001a78 00c004b3 add x9, x0, x12 x9=100fd6f4 x12:100fd6f4 + 21395500 21380 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=100fd709 x15:100fd708 PA:100fd708 + 21397500 21382 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 21398500 21383 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21399500 21384 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fd6f4 PA:100fd6fc + 21401500 21386 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21404500 21389 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 21406500 21391 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21407500 21392 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21410500 21395 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21411500 21396 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21412500 21397 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21415500 21400 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21416500 21401 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21417500 21402 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21418500 21403 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21419500 21404 1c001b36 f71ff06f jal x0, -144 + 21421500 21406 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fd6f4 PA:100fd6fc + 21423500 21408 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21426500 21411 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 21428500 21413 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21429500 21414 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21432500 21417 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 21433500 21418 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21434500 21419 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21435500 21420 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21436500 21421 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fd708 x9:100fd6f4 PA:100fd704 + 21438500 21423 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=100fd709 x20:100fd708 PA:100fd708 + 21440500 21425 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 21443500 21428 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21444500 21429 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21446500 21431 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 21447500 21432 1c001778 fddff06f jal x0, -36 + 21449500 21434 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21450500 21435 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 21451500 21436 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21452500 21437 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 21453500 21438 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 21454500 21439 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 21455500 21440 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 21456500 21441 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 21457500 21442 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21458500 21443 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104010 + 21462500 21447 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21463500 21448 1c001b62 f8bff06f jal x0, -118 + 21465500 21450 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fd70a x20:100fd709 PA:100fd709 + 21467500 21452 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21468500 21453 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fd6f4 PA:100fd6f4 + 21470500 21455 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21471500 21456 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21474500 21459 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fd6d0 PA:100fd6ec + 21475500 21460 1c001b02 01812403 lw x8, 24(x2) x8=100fd778 x2:100fd6d0 PA:100fd6e8 + 21476500 21461 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100fd6d0 PA:100fd6e4 + 21477500 21462 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fd6d0 PA:100fd6e0 + 21478500 21463 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fd6d0 PA:100fd6dc + 21479500 21464 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fd6d0 PA:100fd6d8 + 21480500 21465 1c001b0c 02010113 addi x2, x2, 32 x2=100fd6f0 x2:100fd6d0 + 21481500 21466 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21483500 21468 1c001d86 01800433 add x8, x0, x24 x8=100fd77c x24:100fd77c + 21484500 21469 1c001d88 fadff06f jal x0, -84 + 21486500 21471 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21487500 21472 1c001d36 e69ff06f jal x0, -408 + 21490500 21475 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21508500 21493 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21509500 21494 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21512500 21497 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21513500 21498 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21514500 21499 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21516500 21501 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21517500 21502 1c001778 fddff06f jal x0, -36 + 21519500 21504 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21520500 21505 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 21521500 21506 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21522500 21507 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 21523500 21508 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 21524500 21509 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 21525500 21510 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 21526500 21511 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 21527500 21512 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21528500 21513 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104010 + 21532500 21517 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21533500 21518 1c001bca 16a0006f jal x0, 362 + 21535500 21520 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21536500 21521 1c001d36 e69ff06f jal x0, -408 + 21539500 21524 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21553500 21538 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21554500 21539 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21557500 21542 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21558500 21543 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21559500 21544 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21561500 21546 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21562500 21547 1c001778 fddff06f jal x0, -36 + 21564500 21549 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21565500 21550 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 21566500 21551 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21567500 21552 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 21568500 21553 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 21569500 21554 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 21570500 21555 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 21571500 21556 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 21572500 21557 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21573500 21558 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104010 + 21577500 21562 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21578500 21563 1c001bca 16a0006f jal x0, 362 + 21580500 21565 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21581500 21566 1c001d36 e69ff06f jal x0, -408 + 21584500 21569 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21599500 21584 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21600500 21585 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21603500 21588 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21604500 21589 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21605500 21590 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21607500 21592 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21608500 21593 1c001778 fddff06f jal x0, -36 + 21610500 21595 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21611500 21596 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000002 + 21612500 21597 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21613500 21598 1c00175e 00379713 slli x14, x15, 0x3 x14=00000010 x15:00000002 + 21614500 21599 1c001762 00279793 slli x15, x15, 0x2 x15=00000008 x15:00000002 + 21615500 21600 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000010 + 21616500 21601 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000008 x13:00001f80 + 21617500 21602 1c00176a 00e787b3 add x15, x15, x14 x15=00000010 x15:00000000 x14:00000010 + 21618500 21603 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21619500 21604 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104010 + 21623500 21608 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21624500 21609 1c001bca 16a0006f jal x0, 362 + 21626500 21611 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21627500 21612 1c001d36 e69ff06f jal x0, -408 + 21630500 21615 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21646500 21631 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21647500 21632 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21648500 21633 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100fd6f0 PA:100fd74c + 21649500 21634 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100fd6f0 PA:100fd748 + 21650500 21635 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:100fd6f0 PA:100fd744 + 21651500 21636 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:100fd6f0 PA:100fd740 + 21652500 21637 1c001bb0 04c12983 lw x19, 76(x2) x19=00000002 x2:100fd6f0 PA:100fd73c + 21653500 21638 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:100fd6f0 PA:100fd738 + 21654500 21639 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:100fd6f0 PA:100fd734 + 21655500 21640 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100fd6f0 PA:100fd730 + 21656500 21641 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100fd6f0 PA:100fd72c + 21657500 21642 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100fd6f0 PA:100fd728 + 21658500 21643 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100fd6f0 PA:100fd724 + 21659500 21644 1c001bbe 06010113 addi x2, x2, 96 x2=100fd750 x2:100fd6f0 + 21660500 21645 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21662500 21647 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:100fd750 PA:100fd76c + 21664500 21649 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21665500 21650 1c001838 04010113 addi x2, x2, 64 x2=100fd790 x2:100fd750 + 21666500 21651 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21676500 21661 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_00_3.log b/sw/scripts/tracevis/example/traces/trace_core_00_3.log new file mode 100644 index 0000000..4d4699a --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_00_3.log @@ -0,0 +1,847 @@ + Time Cycles PC Instr Mnemonic + 100500 85 1c000080 0180006f jal x0, 24 + 125500 110 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000003 + 126500 111 1c00009c 01f57593 andi x11, x10, 31 x11=00000003 x10:00000003 + 148500 133 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000000 x10:00000003 + 149500 134 1c0000a2 00058463 beq x11, x0, 8 x11:00000003 + 150500 135 1c0000a6 05a0206f jal x0, 8282 + 173500 158 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 174500 159 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 175500 160 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 176500 161 1c00210c 0e059163 bne x11, x0, 226 x11:00000003 + 244500 229 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 245500 230 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000003 + 246500 231 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000003 x19:00000003 + 247500 232 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 266500 251 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 267500 252 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 268500 253 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 269500 254 1c00220a 0060006f jal x0, 6 + 289500 274 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 9629500 9614 1c002214 08096503 p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080 + 9637500 9622 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 9638500 9623 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 9656500 9641 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 9657500 9642 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 9659500 9644 1c00222c 08096283 p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080 + 9683500 9668 1c002230 02a98533 mul x10, x19, x10 x10=00001800 x19:00000003 x10:00000800 + 9684500 9669 1c002234 00550133 add x2, x10, x5 x2=100fdf90 x10:00001800 x5:100fc790 + 9685500 9670 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 9705500 9690 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18829500 18814 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18837500 18822 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18838500 18823 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18839500 18824 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18840500 18825 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18863500 18848 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000003 + 18883500 18868 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18884500 18869 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000000 x12:00000003 + 18885500 18870 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000 + 18886500 18871 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000003 x12:00000003 + 18887500 18872 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18888500 18873 1c0009d4 63d0006f jal x0, 3644 + 18890500 18875 1c001810 fc010113 addi x2, x2, -64 x2=100fdf50 x2:100fdf90 + 18891500 18876 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:100fdf50 PA:100fdf74 + 18896500 18881 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18897500 18882 1c001818 02c12423 sw x12, 40(x2) x12:00000003 x2:100fdf50 PA:100fdf78 + 18898500 18883 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:100fdf50 PA:100fdf7c + 18899500 18884 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18900500 18885 1c00181e 02410693 addi x13, x2, 36 x13=100fdf74 x2:100fdf50 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:100fdf50 PA:100fdf6c + 18918500 18903 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:100fdf50 PA:100fdf80 + 18919500 18904 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:100fdf50 PA:100fdf84 + 18920500 18905 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:100fdf50 PA:100fdf88 + 18921500 18906 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:100fdf50 PA:100fdf8c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:100fdf74 x2:100fdf50 PA:100fdf5c + 18939500 18924 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100fdef0 x2:100fdf50 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100fdf08 x2:100fdef0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100fdef0 PA:100fdf48 + 18960500 18945 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:100fdef0 PA:100fdf40 + 18961500 18946 1c001b78 05312623 sw x19, 76(x2) x19:00000003 x2:100fdef0 PA:100fdf3c + 18962500 18947 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:100fdef0 PA:100fdf38 + 18963500 18948 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:100fdef0 PA:100fdf34 + 18964500 18949 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100fdef0 PA:100fdf30 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100fdef0 PA:100fdf2c + 18986500 18971 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100fdef0 PA:100fdf4c + 18987500 18972 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:100fdef0 PA:100fdf44 + 18988500 18973 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100fdef0 PA:100fdf28 + 18989500 18974 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100fdef0 PA:100fdf24 + 18990500 18975 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18991500 18976 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18992500 18977 1c001b8e 00d00433 add x8, x0, x13 x8=100fdf74 x13:100fdf74 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100fdf08 x2:100fdef0 PA:100fdf04 + 19015500 19000 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19016500 19001 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19017500 19002 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19018500 19003 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19057500 19042 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19058500 19043 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104018 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19177500 19162 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19178500 19163 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19181500 19166 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19182500 19167 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19183500 19168 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19185500 19170 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19186500 19171 1c001778 fddff06f jal x0, -36 + 19188500 19173 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19189500 19174 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19190500 19175 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19191500 19176 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19192500 19177 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19193500 19178 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19194500 19179 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19195500 19180 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19196500 19181 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19197500 19182 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104018 + 19201500 19186 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19202500 19187 1c001bca 16a0006f jal x0, 362 + 19204500 19189 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19205500 19190 1c001d36 e69ff06f jal x0, -408 + 19208500 19193 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19236500 19221 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19237500 19222 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19240500 19225 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19241500 19226 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19242500 19227 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19244500 19229 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19245500 19230 1c001778 fddff06f jal x0, -36 + 19247500 19232 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19248500 19233 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19249500 19234 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19250500 19235 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19251500 19236 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19252500 19237 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19253500 19238 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19254500 19239 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19255500 19240 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19256500 19241 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104018 + 19260500 19245 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19261500 19246 1c001bca 16a0006f jal x0, 362 + 19263500 19248 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19264500 19249 1c001d36 e69ff06f jal x0, -408 + 19267500 19252 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19284500 19269 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19285500 19270 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19288500 19273 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19289500 19274 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19290500 19275 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19292500 19277 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19293500 19278 1c001778 fddff06f jal x0, -36 + 19295500 19280 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19296500 19281 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19297500 19282 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19298500 19283 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19299500 19284 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19300500 19285 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19301500 19286 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19302500 19287 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19303500 19288 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19304500 19289 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104018 + 19308500 19293 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19309500 19294 1c001bca 16a0006f jal x0, 362 + 19311500 19296 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19312500 19297 1c001d36 e69ff06f jal x0, -408 + 19315500 19300 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19333500 19318 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19334500 19319 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19337500 19322 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19338500 19323 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19339500 19324 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19341500 19326 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19342500 19327 1c001778 fddff06f jal x0, -36 + 19344500 19329 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19345500 19330 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19346500 19331 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19347500 19332 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19348500 19333 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19349500 19334 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19350500 19335 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19351500 19336 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19352500 19337 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19353500 19338 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104018 + 19357500 19342 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19358500 19343 1c001bca 16a0006f jal x0, 362 + 19360500 19345 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19361500 19346 1c001d36 e69ff06f jal x0, -408 + 19364500 19349 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19383500 19368 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19384500 19369 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19387500 19372 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19388500 19373 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19389500 19374 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19391500 19376 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19392500 19377 1c001778 fddff06f jal x0, -36 + 19394500 19379 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19395500 19380 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19396500 19381 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19397500 19382 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19398500 19383 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19399500 19384 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19400500 19385 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19401500 19386 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19402500 19387 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19403500 19388 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104018 + 19407500 19392 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19408500 19393 1c001bca 16a0006f jal x0, 362 + 19410500 19395 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19411500 19396 1c001d36 e69ff06f jal x0, -408 + 19414500 19399 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19432500 19417 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19433500 19418 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19436500 19421 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19437500 19422 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19438500 19423 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19440500 19425 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19441500 19426 1c001778 fddff06f jal x0, -36 + 19443500 19428 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19444500 19429 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19445500 19430 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19446500 19431 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19447500 19432 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19448500 19433 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19449500 19434 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19450500 19435 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19451500 19436 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19452500 19437 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104018 + 19456500 19441 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19457500 19442 1c001bca 16a0006f jal x0, 362 + 19459500 19444 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19460500 19445 1c001d36 e69ff06f jal x0, -408 + 19463500 19448 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19482500 19467 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19483500 19468 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19486500 19471 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19487500 19472 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19488500 19473 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19490500 19475 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19491500 19476 1c001778 fddff06f jal x0, -36 + 19493500 19478 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19494500 19479 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19495500 19480 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19496500 19481 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19497500 19482 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19498500 19483 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19499500 19484 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19500500 19485 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19501500 19486 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19502500 19487 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104018 + 19506500 19491 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19507500 19492 1c001bca 16a0006f jal x0, 362 + 19509500 19494 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19510500 19495 1c001d36 e69ff06f jal x0, -408 + 19513500 19498 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19527500 19512 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19528500 19513 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19531500 19516 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19532500 19517 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19533500 19518 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19535500 19520 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19536500 19521 1c001778 fddff06f jal x0, -36 + 19538500 19523 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19539500 19524 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19540500 19525 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19541500 19526 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19542500 19527 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19543500 19528 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19544500 19529 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19545500 19530 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19546500 19531 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19547500 19532 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104018 + 19551500 19536 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19552500 19537 1c001bca 16a0006f jal x0, 362 + 19554500 19539 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19555500 19540 1c001d36 e69ff06f jal x0, -408 + 19558500 19543 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19587500 19572 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19588500 19573 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19591500 19576 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19592500 19577 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19593500 19578 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19595500 19580 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19596500 19581 1c001778 fddff06f jal x0, -36 + 19598500 19583 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19599500 19584 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19600500 19585 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19601500 19586 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19602500 19587 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19603500 19588 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19604500 19589 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19605500 19590 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19606500 19591 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19607500 19592 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104018 + 19611500 19596 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19612500 19597 1c001bca 16a0006f jal x0, 362 + 19614500 19599 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19615500 19600 1c001d36 e69ff06f jal x0, -408 + 19618500 19603 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19632500 19617 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19633500 19618 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19636500 19621 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19637500 19622 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19638500 19623 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19640500 19625 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19641500 19626 1c001778 fddff06f jal x0, -36 + 19643500 19628 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19644500 19629 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19645500 19630 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19646500 19631 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19647500 19632 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19648500 19633 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19649500 19634 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19650500 19635 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19651500 19636 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19652500 19637 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104018 + 19656500 19641 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19657500 19642 1c001bca 16a0006f jal x0, 362 + 19659500 19644 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19660500 19645 1c001d36 e69ff06f jal x0, -408 + 19663500 19648 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19677500 19662 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19678500 19663 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19681500 19666 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19682500 19667 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19683500 19668 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19685500 19670 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19686500 19671 1c001778 fddff06f jal x0, -36 + 19688500 19673 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19689500 19674 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19690500 19675 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19691500 19676 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19692500 19677 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19693500 19678 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19694500 19679 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19695500 19680 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19696500 19681 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19697500 19682 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104018 + 19701500 19686 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19702500 19687 1c001bca 16a0006f jal x0, 362 + 19704500 19689 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19705500 19690 1c001d36 e69ff06f jal x0, -408 + 19708500 19693 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19722500 19707 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19723500 19708 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19726500 19711 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19727500 19712 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19728500 19713 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19730500 19715 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19731500 19716 1c001778 fddff06f jal x0, -36 + 19733500 19718 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19734500 19719 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19735500 19720 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19736500 19721 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19737500 19722 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19738500 19723 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19739500 19724 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19740500 19725 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19741500 19726 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19742500 19727 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104018 + 19746500 19731 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19747500 19732 1c001bca 16a0006f jal x0, 362 + 19749500 19734 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19750500 19735 1c001d36 e69ff06f jal x0, -408 + 19753500 19738 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19767500 19752 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19768500 19753 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19771500 19756 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19772500 19757 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19773500 19758 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19775500 19760 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19776500 19761 1c001778 fddff06f jal x0, -36 + 19778500 19763 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19779500 19764 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19780500 19765 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19781500 19766 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19782500 19767 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19783500 19768 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19784500 19769 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19785500 19770 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19786500 19771 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19787500 19772 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104018 + 19791500 19776 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19792500 19777 1c001bca 16a0006f jal x0, 362 + 19794500 19779 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19795500 19780 1c001d36 e69ff06f jal x0, -408 + 19798500 19783 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19817500 19802 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19818500 19803 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19821500 19806 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19822500 19807 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19823500 19808 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19825500 19810 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19826500 19811 1c001778 fddff06f jal x0, -36 + 19828500 19813 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19829500 19814 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 19830500 19815 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19831500 19816 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 19832500 19817 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 19833500 19818 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 19834500 19819 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 19835500 19820 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 19836500 19821 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19837500 19822 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104018 + 19841500 19826 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19842500 19827 1c001bca 16a0006f jal x0, 362 + 19844500 19829 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19845500 19830 1c001d36 e69ff06f jal x0, -408 + 19848500 19833 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19865500 19850 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19866500 19851 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19869500 19854 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19872500 19857 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100fdef0 PA:100fdef4 + 19877500 19862 1c001bd0 00012423 sw x0, 8(x2) x2:100fdef0 PA:100fdef8 + 19879500 19864 1c001bd2 00010623 sb x0, 12(x2) x2:100fdef0 PA:100fdefc + 19880500 19865 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19881500 19866 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19896500 19881 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19897500 19882 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fdef0 PA:100fdef4 + 19900500 19885 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19901500 19886 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19902500 19887 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19903500 19888 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19904500 19889 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19950500 19935 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19951500 19936 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fdef0 PA:100fdf00 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=100fdf78 x8:100fdf74 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:100fdf74 PA:100fdf74 + 20312500 20297 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100fdef4 x2:100fdef0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100fdf08 x11:100fdef4 PA:100fdf04 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fdef4 PA:100fdf00 + 20404500 20389 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20405500 20390 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20439500 20424 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20440500 20425 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20441500 20426 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20442500 20427 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20445500 20430 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fdef4 PA:100fdf00 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100fdf08 PA:100fdf08 + 20585500 20570 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20586500 20571 1c001a5e 00168693 addi x13, x13, 1 x13=100fdf09 x13:100fdf08 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100fdf09 PA:100fdf09 + 20607500 20592 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20608500 20593 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100fdef4 x2:100fdef0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100fded0 x2:100fdef0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:100fdf74 x2:100fded0 PA:100fdee8 + 20648500 20633 1c001a66 01062783 lw x15, 16(x12) x15=100fdf08 x12:100fdef4 PA:100fdf04 + 20649500 20634 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fdef4 PA:100fdef8 + 20650500 20635 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100fded0 PA:100fdee4 + 20651500 20636 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fded0 PA:100fdee0 + 20652500 20637 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fded0 PA:100fdedc + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fded0 PA:100fdeec + 20675500 20660 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fded0 PA:100fded8 + 20676500 20661 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20677500 20662 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20678500 20663 1c001a78 00c004b3 add x9, x0, x12 x9=100fdef4 x12:100fdef4 + 20679500 20664 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100fdf09 x15:100fdf08 PA:100fdf08 + 20681500 20666 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fdef4 PA:100fdefc + 20702500 20687 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20705500 20690 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fdef4 PA:100fdefc + 20796500 20781 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 20817500 20802 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20818500 20803 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fdf08 x9:100fdef4 PA:100fdf04 + 20858500 20843 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100fdf09 x20:100fdf08 PA:100fdf08 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104018 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fdf0a x20:100fdf09 PA:100fdf09 + 20933500 20918 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20934500 20919 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 20936500 20921 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20937500 20922 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fded0 PA:100fdeec + 20960500 20945 1c001b02 01812403 lw x8, 24(x2) x8=100fdf74 x2:100fded0 PA:100fdee8 + 20961500 20946 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100fded0 PA:100fdee4 + 20962500 20947 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fded0 PA:100fdee0 + 20963500 20948 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fded0 PA:100fdedc + 20964500 20949 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fded0 PA:100fded8 + 20965500 20950 1c001b0c 02010113 addi x2, x2, 32 x2=100fdef0 x2:100fded0 + 20966500 20951 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=100fdf78 x24:100fdf78 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21009500 20994 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21010500 20995 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21013500 20998 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21014500 20999 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21015500 21000 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21017500 21002 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21018500 21003 1c001778 fddff06f jal x0, -36 + 21020500 21005 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21021500 21006 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 21022500 21007 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21023500 21008 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 21024500 21009 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 21025500 21010 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 21026500 21011 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 21027500 21012 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 21028500 21013 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21029500 21014 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104018 + 21033500 21018 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21034500 21019 1c001bca 16a0006f jal x0, 362 + 21036500 21021 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21037500 21022 1c001d36 e69ff06f jal x0, -408 + 21040500 21025 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21055500 21040 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21056500 21041 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21059500 21044 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21060500 21045 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21061500 21046 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21063500 21048 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21064500 21049 1c001778 fddff06f jal x0, -36 + 21066500 21051 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21067500 21052 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 21068500 21053 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21069500 21054 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 21070500 21055 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 21071500 21056 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 21072500 21057 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 21073500 21058 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 21074500 21059 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21075500 21060 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104018 + 21079500 21064 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21080500 21065 1c001bca 16a0006f jal x0, 362 + 21082500 21067 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21083500 21068 1c001d36 e69ff06f jal x0, -408 + 21086500 21071 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21103500 21088 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21104500 21089 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21107500 21092 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21110500 21095 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100fdef0 PA:100fdef4 + 21111500 21096 1c001bd0 00012423 sw x0, 8(x2) x2:100fdef0 PA:100fdef8 + 21112500 21097 1c001bd2 00010623 sb x0, 12(x2) x2:100fdef0 PA:100fdefc + 21113500 21098 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21114500 21099 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21115500 21100 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21116500 21101 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fdef0 PA:100fdef4 + 21117500 21102 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21118500 21103 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21119500 21104 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21120500 21105 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21121500 21106 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21122500 21107 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21123500 21108 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21124500 21109 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21141500 21126 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21142500 21127 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21145500 21130 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21146500 21131 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21147500 21132 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21150500 21135 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21153500 21138 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21156500 21141 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21159500 21144 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21160500 21145 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21161500 21146 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21162500 21147 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21165500 21150 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21166500 21151 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21169500 21154 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21170500 21155 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21173500 21158 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21175500 21160 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21178500 21163 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21179500 21164 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21182500 21167 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21183500 21168 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21184500 21169 1c001f42 e09ff06f jal x0, -504 + 21186500 21171 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21187500 21172 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fdef0 PA:100fdf00 + 21188500 21173 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21191500 21176 1c001e34 00440c13 addi x24, x8, 4 x24=100fdf7c x8:100fdf78 + 21192500 21177 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:100fdf78 PA:100fdf78 + 21193500 21178 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21196500 21181 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 21199500 21184 1c001e64 00410593 addi x11, x2, 4 x11=100fdef4 x2:100fdef0 + 21200500 21185 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21202500 21187 1c0019fe 0105a683 lw x13, 16(x11) x13=100fdf08 x11:100fdef4 PA:100fdf04 + 21203500 21188 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fdef4 PA:100fdf00 + 21204500 21189 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21205500 21190 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 21239500 21224 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 21240500 21225 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21241500 21226 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21242500 21227 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21245500 21230 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fdef4 PA:100fdf00 + 21246500 21231 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 21280500 21265 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 21314500 21299 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21345500 21330 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21346500 21331 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 21349500 21334 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21360500 21345 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 21363500 21348 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 21364500 21349 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:100fdf08 PA:100fdf08 + 21367500 21352 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21368500 21353 1c001a5e 00168693 addi x13, x13, 1 x13=100fdf09 x13:100fdf08 + 21369500 21354 1c001a60 fb1ff06f jal x0, -80 + 21371500 21356 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21372500 21357 1c001a12 00068023 sb x0, 0(x13) x13:100fdf09 PA:100fdf09 + 21373500 21358 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21375500 21360 1c001e68 f17ff06f jal x0, -234 + 21377500 21362 1c001d7e 00410613 addi x12, x2, 4 x12=100fdef4 x2:100fdef0 + 21378500 21363 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21379500 21364 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21380500 21365 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21382500 21367 1c001a62 fe010113 addi x2, x2, -32 x2=100fded0 x2:100fdef0 + 21383500 21368 1c001a64 00812c23 sw x8, 24(x2) x8:100fdf78 x2:100fded0 PA:100fdee8 + 21384500 21369 1c001a66 01062783 lw x15, 16(x12) x15=100fdf08 x12:100fdef4 PA:100fdf04 + 21385500 21370 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fdef4 PA:100fdef8 + 21386500 21371 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100fded0 PA:100fdee4 + 21387500 21372 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fded0 PA:100fdee0 + 21388500 21373 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fded0 PA:100fdedc + 21389500 21374 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fded0 PA:100fdeec + 21390500 21375 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fded0 PA:100fded8 + 21391500 21376 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21392500 21377 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21393500 21378 1c001a78 00c004b3 add x9, x0, x12 x9=100fdef4 x12:100fdef4 + 21394500 21379 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=100fdf09 x15:100fdf08 PA:100fdf08 + 21396500 21381 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 21397500 21382 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21398500 21383 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fdef4 PA:100fdefc + 21400500 21385 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21403500 21388 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 21405500 21390 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21406500 21391 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21409500 21394 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21410500 21395 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21411500 21396 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21414500 21399 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21415500 21400 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21416500 21401 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21417500 21402 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21418500 21403 1c001b36 f71ff06f jal x0, -144 + 21420500 21405 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fdef4 PA:100fdefc + 21422500 21407 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21425500 21410 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 21427500 21412 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21428500 21413 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21431500 21416 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 21432500 21417 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21433500 21418 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21434500 21419 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21435500 21420 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fdf08 x9:100fdef4 PA:100fdf04 + 21437500 21422 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=100fdf09 x20:100fdf08 PA:100fdf08 + 21439500 21424 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21442500 21427 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21443500 21428 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21445500 21430 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21446500 21431 1c001778 fddff06f jal x0, -36 + 21448500 21433 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21449500 21434 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 21450500 21435 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21451500 21436 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 21452500 21437 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 21453500 21438 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 21454500 21439 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 21455500 21440 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 21456500 21441 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21457500 21442 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104018 + 21461500 21446 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21462500 21447 1c001b62 f8bff06f jal x0, -118 + 21464500 21449 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fdf0a x20:100fdf09 PA:100fdf09 + 21466500 21451 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21467500 21452 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fdef4 PA:100fdef4 + 21469500 21454 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21470500 21455 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21473500 21458 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fded0 PA:100fdeec + 21474500 21459 1c001b02 01812403 lw x8, 24(x2) x8=100fdf78 x2:100fded0 PA:100fdee8 + 21475500 21460 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100fded0 PA:100fdee4 + 21476500 21461 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fded0 PA:100fdee0 + 21477500 21462 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fded0 PA:100fdedc + 21478500 21463 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fded0 PA:100fded8 + 21479500 21464 1c001b0c 02010113 addi x2, x2, 32 x2=100fdef0 x2:100fded0 + 21480500 21465 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21482500 21467 1c001d86 01800433 add x8, x0, x24 x8=100fdf7c x24:100fdf7c + 21483500 21468 1c001d88 fadff06f jal x0, -84 + 21485500 21470 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21486500 21471 1c001d36 e69ff06f jal x0, -408 + 21489500 21474 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21506500 21491 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21507500 21492 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21510500 21495 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21511500 21496 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21512500 21497 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21514500 21499 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21515500 21500 1c001778 fddff06f jal x0, -36 + 21517500 21502 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21518500 21503 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 21519500 21504 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21520500 21505 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 21521500 21506 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 21522500 21507 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 21523500 21508 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 21524500 21509 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 21525500 21510 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21526500 21511 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104018 + 21530500 21515 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21531500 21516 1c001bca 16a0006f jal x0, 362 + 21533500 21518 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21534500 21519 1c001d36 e69ff06f jal x0, -408 + 21537500 21522 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21551500 21536 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21552500 21537 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21555500 21540 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21556500 21541 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21557500 21542 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21559500 21544 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21560500 21545 1c001778 fddff06f jal x0, -36 + 21562500 21547 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21563500 21548 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 21564500 21549 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21565500 21550 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 21566500 21551 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 21567500 21552 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 21568500 21553 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 21569500 21554 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 21570500 21555 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21571500 21556 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104018 + 21575500 21560 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21576500 21561 1c001bca 16a0006f jal x0, 362 + 21578500 21563 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21579500 21564 1c001d36 e69ff06f jal x0, -408 + 21582500 21567 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21598500 21583 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21599500 21584 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21602500 21587 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21603500 21588 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21604500 21589 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21606500 21591 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21607500 21592 1c001778 fddff06f jal x0, -36 + 21609500 21594 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21610500 21595 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000003 + 21611500 21596 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21612500 21597 1c00175e 00379713 slli x14, x15, 0x3 x14=00000018 x15:00000003 + 21613500 21598 1c001762 00279793 slli x15, x15, 0x2 x15=0000000c x15:00000003 + 21614500 21599 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000018 + 21615500 21600 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000000c x13:00001f80 + 21616500 21601 1c00176a 00e787b3 add x15, x15, x14 x15=00000018 x15:00000000 x14:00000018 + 21617500 21602 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21618500 21603 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104018 + 21622500 21607 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21623500 21608 1c001bca 16a0006f jal x0, 362 + 21625500 21610 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21626500 21611 1c001d36 e69ff06f jal x0, -408 + 21629500 21614 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21644500 21629 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21645500 21630 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21646500 21631 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100fdef0 PA:100fdf4c + 21647500 21632 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100fdef0 PA:100fdf48 + 21648500 21633 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:100fdef0 PA:100fdf44 + 21649500 21634 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:100fdef0 PA:100fdf40 + 21650500 21635 1c001bb0 04c12983 lw x19, 76(x2) x19=00000003 x2:100fdef0 PA:100fdf3c + 21651500 21636 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:100fdef0 PA:100fdf38 + 21652500 21637 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:100fdef0 PA:100fdf34 + 21653500 21638 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100fdef0 PA:100fdf30 + 21654500 21639 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100fdef0 PA:100fdf2c + 21655500 21640 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100fdef0 PA:100fdf28 + 21656500 21641 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100fdef0 PA:100fdf24 + 21657500 21642 1c001bbe 06010113 addi x2, x2, 96 x2=100fdf50 x2:100fdef0 + 21658500 21643 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21660500 21645 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:100fdf50 PA:100fdf6c + 21661500 21646 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21662500 21647 1c001838 04010113 addi x2, x2, 64 x2=100fdf90 x2:100fdf50 + 21663500 21648 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21676500 21661 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_00_4.log b/sw/scripts/tracevis/example/traces/trace_core_00_4.log new file mode 100644 index 0000000..03d4526 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_00_4.log @@ -0,0 +1,847 @@ + Time Cycles PC Instr Mnemonic + 104500 89 1c000080 0180006f jal x0, 24 + 128500 113 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000004 + 129500 114 1c00009c 01f57593 andi x11, x10, 31 x11=00000004 x10:00000004 + 151500 136 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000000 x10:00000004 + 152500 137 1c0000a2 00058463 beq x11, x0, 8 x11:00000004 + 153500 138 1c0000a6 05a0206f jal x0, 8282 + 176500 161 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 177500 162 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 178500 163 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 179500 164 1c00210c 0e059163 bne x11, x0, 226 x11:00000004 + 246500 231 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 247500 232 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000004 + 248500 233 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000004 x19:00000004 + 249500 234 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 268500 253 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 269500 254 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 270500 255 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 271500 256 1c00220a 0060006f jal x0, 6 + 292500 277 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 9629500 9614 1c002214 08096503 p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080 + 9637500 9622 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 9638500 9623 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 9656500 9641 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 9657500 9642 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 9659500 9644 1c00222c 08096283 p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080 + 9683500 9668 1c002230 02a98533 mul x10, x19, x10 x10=00002000 x19:00000004 x10:00000800 + 9684500 9669 1c002234 00550133 add x2, x10, x5 x2=100fe790 x10:00002000 x5:100fc790 + 9685500 9670 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 9705500 9690 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18829500 18814 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18837500 18822 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18838500 18823 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18839500 18824 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18840500 18825 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18863500 18848 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000004 + 18883500 18868 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18884500 18869 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000000 x12:00000004 + 18885500 18870 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000 + 18886500 18871 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000004 x12:00000004 + 18887500 18872 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18888500 18873 1c0009d4 63d0006f jal x0, 3644 + 18890500 18875 1c001810 fc010113 addi x2, x2, -64 x2=100fe750 x2:100fe790 + 18891500 18876 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:100fe750 PA:100fe774 + 18898500 18883 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18899500 18884 1c001818 02c12423 sw x12, 40(x2) x12:00000004 x2:100fe750 PA:100fe778 + 18900500 18885 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:100fe750 PA:100fe77c + 18901500 18886 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18902500 18887 1c00181e 02410693 addi x13, x2, 36 x13=100fe774 x2:100fe750 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:100fe750 PA:100fe76c + 18915500 18900 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:100fe750 PA:100fe780 + 18916500 18901 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:100fe750 PA:100fe784 + 18917500 18902 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:100fe750 PA:100fe788 + 18918500 18903 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:100fe750 PA:100fe78c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:100fe774 x2:100fe750 PA:100fe75c + 18940500 18925 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100fe6f0 x2:100fe750 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100fe708 x2:100fe6f0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100fe6f0 PA:100fe748 + 18963500 18948 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:100fe6f0 PA:100fe740 + 18965500 18950 1c001b78 05312623 sw x19, 76(x2) x19:00000004 x2:100fe6f0 PA:100fe73c + 18966500 18951 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:100fe6f0 PA:100fe738 + 18967500 18952 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:100fe6f0 PA:100fe734 + 18968500 18953 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100fe6f0 PA:100fe730 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100fe6f0 PA:100fe72c + 18989500 18974 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100fe6f0 PA:100fe74c + 18990500 18975 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:100fe6f0 PA:100fe744 + 18991500 18976 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100fe6f0 PA:100fe728 + 18992500 18977 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100fe6f0 PA:100fe724 + 18993500 18978 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18994500 18979 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18995500 18980 1c001b8e 00d00433 add x8, x0, x13 x8=100fe774 x13:100fe774 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100fe708 x2:100fe6f0 PA:100fe704 + 19016500 19001 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19017500 19002 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19018500 19003 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19019500 19004 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19059500 19044 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19060500 19045 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104020 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19197500 19182 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19198500 19183 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19201500 19186 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19202500 19187 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19203500 19188 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19205500 19190 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19206500 19191 1c001778 fddff06f jal x0, -36 + 19208500 19193 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19209500 19194 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19210500 19195 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19211500 19196 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19212500 19197 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19213500 19198 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19214500 19199 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19215500 19200 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19216500 19201 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19217500 19202 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104020 + 19221500 19206 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19222500 19207 1c001bca 16a0006f jal x0, 362 + 19224500 19209 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19225500 19210 1c001d36 e69ff06f jal x0, -408 + 19228500 19213 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19247500 19232 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19248500 19233 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19251500 19236 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19252500 19237 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19253500 19238 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19258500 19243 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19259500 19244 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19260500 19245 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19261500 19246 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19262500 19247 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19263500 19248 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19264500 19249 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19265500 19250 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19266500 19251 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19267500 19252 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104020 + 19271500 19256 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19272500 19257 1c001bca 16a0006f jal x0, 362 + 19274500 19259 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19275500 19260 1c001d36 e69ff06f jal x0, -408 + 19278500 19263 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19294500 19279 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19295500 19280 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19298500 19283 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19299500 19284 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19300500 19285 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19302500 19287 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19303500 19288 1c001778 fddff06f jal x0, -36 + 19305500 19290 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19306500 19291 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19307500 19292 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19308500 19293 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19309500 19294 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19310500 19295 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19311500 19296 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19312500 19297 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19313500 19298 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19314500 19299 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104020 + 19318500 19303 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19319500 19304 1c001bca 16a0006f jal x0, 362 + 19321500 19306 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19322500 19307 1c001d36 e69ff06f jal x0, -408 + 19325500 19310 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19344500 19329 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19345500 19330 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19348500 19333 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19349500 19334 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19350500 19335 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19352500 19337 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19353500 19338 1c001778 fddff06f jal x0, -36 + 19355500 19340 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19356500 19341 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19357500 19342 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19358500 19343 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19359500 19344 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19360500 19345 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19361500 19346 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19362500 19347 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19363500 19348 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19364500 19349 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104020 + 19368500 19353 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19369500 19354 1c001bca 16a0006f jal x0, 362 + 19371500 19356 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19372500 19357 1c001d36 e69ff06f jal x0, -408 + 19375500 19360 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19398500 19383 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19399500 19384 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19402500 19387 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19403500 19388 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19404500 19389 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19406500 19391 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19407500 19392 1c001778 fddff06f jal x0, -36 + 19409500 19394 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19410500 19395 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19411500 19396 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19412500 19397 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19413500 19398 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19414500 19399 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19415500 19400 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19416500 19401 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19417500 19402 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19418500 19403 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104020 + 19422500 19407 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19423500 19408 1c001bca 16a0006f jal x0, 362 + 19425500 19410 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19426500 19411 1c001d36 e69ff06f jal x0, -408 + 19429500 19414 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19448500 19433 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19449500 19434 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19452500 19437 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19453500 19438 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19454500 19439 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19456500 19441 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19457500 19442 1c001778 fddff06f jal x0, -36 + 19459500 19444 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19460500 19445 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19461500 19446 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19462500 19447 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19463500 19448 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19464500 19449 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19465500 19450 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19466500 19451 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19467500 19452 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19468500 19453 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104020 + 19472500 19457 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19473500 19458 1c001bca 16a0006f jal x0, 362 + 19475500 19460 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19476500 19461 1c001d36 e69ff06f jal x0, -408 + 19479500 19464 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19501500 19486 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19502500 19487 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19505500 19490 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19506500 19491 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19507500 19492 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19509500 19494 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19510500 19495 1c001778 fddff06f jal x0, -36 + 19512500 19497 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19513500 19498 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19514500 19499 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19515500 19500 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19516500 19501 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19517500 19502 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19518500 19503 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19519500 19504 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19520500 19505 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19521500 19506 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104020 + 19525500 19510 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19526500 19511 1c001bca 16a0006f jal x0, 362 + 19528500 19513 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19529500 19514 1c001d36 e69ff06f jal x0, -408 + 19532500 19517 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19547500 19532 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19548500 19533 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19551500 19536 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19552500 19537 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19553500 19538 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19555500 19540 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19556500 19541 1c001778 fddff06f jal x0, -36 + 19558500 19543 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19559500 19544 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19560500 19545 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19561500 19546 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19562500 19547 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19563500 19548 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19564500 19549 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19565500 19550 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19566500 19551 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19567500 19552 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104020 + 19571500 19556 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19572500 19557 1c001bca 16a0006f jal x0, 362 + 19574500 19559 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19575500 19560 1c001d36 e69ff06f jal x0, -408 + 19578500 19563 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19599500 19584 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19600500 19585 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19603500 19588 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19604500 19589 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19605500 19590 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19607500 19592 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19608500 19593 1c001778 fddff06f jal x0, -36 + 19610500 19595 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19611500 19596 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19612500 19597 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19613500 19598 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19614500 19599 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19615500 19600 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19616500 19601 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19617500 19602 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19618500 19603 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19619500 19604 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104020 + 19623500 19608 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19624500 19609 1c001bca 16a0006f jal x0, 362 + 19626500 19611 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19627500 19612 1c001d36 e69ff06f jal x0, -408 + 19630500 19615 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19646500 19631 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19647500 19632 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19650500 19635 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19651500 19636 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19652500 19637 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19654500 19639 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19655500 19640 1c001778 fddff06f jal x0, -36 + 19657500 19642 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19658500 19643 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19659500 19644 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19660500 19645 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19661500 19646 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19662500 19647 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19663500 19648 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19664500 19649 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19665500 19650 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19666500 19651 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104020 + 19670500 19655 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19671500 19656 1c001bca 16a0006f jal x0, 362 + 19673500 19658 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19674500 19659 1c001d36 e69ff06f jal x0, -408 + 19677500 19662 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19692500 19677 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19693500 19678 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19696500 19681 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19697500 19682 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19698500 19683 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19700500 19685 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19701500 19686 1c001778 fddff06f jal x0, -36 + 19703500 19688 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19704500 19689 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19705500 19690 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19706500 19691 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19707500 19692 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19708500 19693 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19709500 19694 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19710500 19695 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19711500 19696 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19712500 19697 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104020 + 19716500 19701 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19717500 19702 1c001bca 16a0006f jal x0, 362 + 19719500 19704 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19720500 19705 1c001d36 e69ff06f jal x0, -408 + 19723500 19708 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19738500 19723 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19739500 19724 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19742500 19727 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19743500 19728 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19744500 19729 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19746500 19731 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19747500 19732 1c001778 fddff06f jal x0, -36 + 19749500 19734 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19750500 19735 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19751500 19736 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19752500 19737 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19753500 19738 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19754500 19739 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19755500 19740 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19756500 19741 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19757500 19742 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19758500 19743 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104020 + 19762500 19747 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19763500 19748 1c001bca 16a0006f jal x0, 362 + 19765500 19750 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19766500 19751 1c001d36 e69ff06f jal x0, -408 + 19769500 19754 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19784500 19769 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19785500 19770 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19788500 19773 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19789500 19774 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19790500 19775 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19792500 19777 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19793500 19778 1c001778 fddff06f jal x0, -36 + 19795500 19780 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19796500 19781 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19797500 19782 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19798500 19783 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19799500 19784 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19800500 19785 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19801500 19786 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19802500 19787 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19803500 19788 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19804500 19789 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104020 + 19808500 19793 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19809500 19794 1c001bca 16a0006f jal x0, 362 + 19811500 19796 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19812500 19797 1c001d36 e69ff06f jal x0, -408 + 19815500 19800 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19830500 19815 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19831500 19816 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19834500 19819 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19835500 19820 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19836500 19821 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19838500 19823 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19839500 19824 1c001778 fddff06f jal x0, -36 + 19841500 19826 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19842500 19827 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 19843500 19828 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19844500 19829 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 19845500 19830 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 19846500 19831 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 19847500 19832 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 19848500 19833 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 19849500 19834 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19850500 19835 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104020 + 19854500 19839 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19855500 19840 1c001bca 16a0006f jal x0, 362 + 19857500 19842 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19858500 19843 1c001d36 e69ff06f jal x0, -408 + 19861500 19846 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19878500 19863 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19879500 19864 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19882500 19867 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19885500 19870 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100fe6f0 PA:100fe6f4 + 19886500 19871 1c001bd0 00012423 sw x0, 8(x2) x2:100fe6f0 PA:100fe6f8 + 19887500 19872 1c001bd2 00010623 sb x0, 12(x2) x2:100fe6f0 PA:100fe6fc + 19888500 19873 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19889500 19874 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19896500 19881 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19897500 19882 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fe6f0 PA:100fe6f4 + 19898500 19883 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19899500 19884 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19900500 19885 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19901500 19886 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19902500 19887 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19960500 19945 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19961500 19946 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fe6f0 PA:100fe700 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=100fe778 x8:100fe774 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:100fe774 PA:100fe774 + 20315500 20300 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100fe6f4 x2:100fe6f0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100fe708 x11:100fe6f4 PA:100fe704 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fe6f4 PA:100fe700 + 20407500 20392 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20408500 20393 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20442500 20427 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20443500 20428 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20444500 20429 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20445500 20430 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20448500 20433 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fe6f4 PA:100fe700 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100fe708 PA:100fe708 + 20586500 20571 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20587500 20572 1c001a5e 00168693 addi x13, x13, 1 x13=100fe709 x13:100fe708 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100fe709 PA:100fe709 + 20608500 20593 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20609500 20594 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100fe6f4 x2:100fe6f0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100fe6d0 x2:100fe6f0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:100fe774 x2:100fe6d0 PA:100fe6e8 + 20649500 20634 1c001a66 01062783 lw x15, 16(x12) x15=100fe708 x12:100fe6f4 PA:100fe704 + 20650500 20635 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fe6f4 PA:100fe6f8 + 20651500 20636 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100fe6d0 PA:100fe6e4 + 20652500 20637 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fe6d0 PA:100fe6e0 + 20653500 20638 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fe6d0 PA:100fe6dc + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fe6d0 PA:100fe6ec + 20678500 20663 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fe6d0 PA:100fe6d8 + 20680500 20665 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20681500 20666 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20682500 20667 1c001a78 00c004b3 add x9, x0, x12 x9=100fe6f4 x12:100fe6f4 + 20683500 20668 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100fe709 x15:100fe708 PA:100fe708 + 20685500 20670 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fe6f4 PA:100fe6fc + 20705500 20690 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20708500 20693 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fe6f4 PA:100fe6fc + 20799500 20784 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 20820500 20805 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20821500 20806 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fe708 x9:100fe6f4 PA:100fe704 + 20861500 20846 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100fe709 x20:100fe708 PA:100fe708 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104020 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fe70a x20:100fe709 PA:100fe709 + 20934500 20919 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20935500 20920 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 20937500 20922 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20938500 20923 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fe6d0 PA:100fe6ec + 20963500 20948 1c001b02 01812403 lw x8, 24(x2) x8=100fe774 x2:100fe6d0 PA:100fe6e8 + 20964500 20949 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100fe6d0 PA:100fe6e4 + 20965500 20950 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fe6d0 PA:100fe6e0 + 20966500 20951 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fe6d0 PA:100fe6dc + 20967500 20952 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fe6d0 PA:100fe6d8 + 20968500 20953 1c001b0c 02010113 addi x2, x2, 32 x2=100fe6f0 x2:100fe6d0 + 20969500 20954 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=100fe778 x24:100fe778 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21011500 20996 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21012500 20997 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21015500 21000 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21016500 21001 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21017500 21002 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21019500 21004 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21020500 21005 1c001778 fddff06f jal x0, -36 + 21022500 21007 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21023500 21008 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 21024500 21009 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21025500 21010 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 21026500 21011 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 21027500 21012 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 21028500 21013 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 21029500 21014 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 21030500 21015 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21031500 21016 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104020 + 21035500 21020 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21036500 21021 1c001bca 16a0006f jal x0, 362 + 21038500 21023 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21039500 21024 1c001d36 e69ff06f jal x0, -408 + 21042500 21027 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21057500 21042 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21058500 21043 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21061500 21046 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21062500 21047 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21063500 21048 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21065500 21050 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21066500 21051 1c001778 fddff06f jal x0, -36 + 21068500 21053 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21069500 21054 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 21070500 21055 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21071500 21056 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 21072500 21057 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 21073500 21058 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 21074500 21059 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 21075500 21060 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 21076500 21061 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21077500 21062 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104020 + 21081500 21066 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21082500 21067 1c001bca 16a0006f jal x0, 362 + 21084500 21069 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21085500 21070 1c001d36 e69ff06f jal x0, -408 + 21088500 21073 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21104500 21089 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21105500 21090 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21108500 21093 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21111500 21096 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100fe6f0 PA:100fe6f4 + 21112500 21097 1c001bd0 00012423 sw x0, 8(x2) x2:100fe6f0 PA:100fe6f8 + 21113500 21098 1c001bd2 00010623 sb x0, 12(x2) x2:100fe6f0 PA:100fe6fc + 21114500 21099 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21115500 21100 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21116500 21101 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21117500 21102 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100fe6f0 PA:100fe6f4 + 21118500 21103 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21119500 21104 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21120500 21105 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21121500 21106 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21122500 21107 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21123500 21108 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21124500 21109 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21125500 21110 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21143500 21128 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21144500 21129 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21147500 21132 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21148500 21133 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21149500 21134 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21152500 21137 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21155500 21140 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21158500 21143 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21161500 21146 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21162500 21147 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21163500 21148 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21164500 21149 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21167500 21152 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21168500 21153 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21171500 21156 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21172500 21157 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21175500 21160 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21177500 21162 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21180500 21165 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21181500 21166 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21184500 21169 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21185500 21170 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21186500 21171 1c001f42 e09ff06f jal x0, -504 + 21188500 21173 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21189500 21174 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100fe6f0 PA:100fe700 + 21190500 21175 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21193500 21178 1c001e34 00440c13 addi x24, x8, 4 x24=100fe77c x8:100fe778 + 21194500 21179 1c001e38 00042503 lw x10, 0(x8) x10=00000004 x8:100fe778 PA:100fe778 + 21195500 21180 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21198500 21183 1c001e54 00055863 bge x10, x0, 16 x10:00000004 + 21201500 21186 1c001e64 00410593 addi x11, x2, 4 x11=100fe6f4 x2:100fe6f0 + 21202500 21187 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21204500 21189 1c0019fe 0105a683 lw x13, 16(x11) x13=100fe708 x11:100fe6f4 PA:100fe704 + 21205500 21190 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fe6f4 PA:100fe700 + 21206500 21191 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21207500 21192 1c001a04 02f55633 divu x12, x10, x15 x12=00000004 x10:00000004 x15:00000001 + 21241500 21226 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000004 x14:0000000a + 21242500 21227 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21243500 21228 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21244500 21229 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21247500 21232 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100fe6f4 PA:100fe700 + 21248500 21233 1c001a20 02f55833 divu x16, x10, x15 x16=00000004 x10:00000004 x15:00000001 + 21282500 21267 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000004 x15:00000001 + 21316500 21301 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21347500 21332 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21348500 21333 1c001a2e 01004663 blt x0, x16, 12 x16:00000004 + 21351500 21336 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21360500 21345 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000004 + 21363500 21348 1c001a56 01070733 add x14, x14, x16 x14=00000034 x14:00000030 x16:00000004 + 21364500 21349 1c001a58 00e68023 sb x14, 0(x13) x14:00000034 x13:100fe708 PA:100fe708 + 21365500 21350 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21366500 21351 1c001a5e 00168693 addi x13, x13, 1 x13=100fe709 x13:100fe708 + 21367500 21352 1c001a60 fb1ff06f jal x0, -80 + 21369500 21354 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21370500 21355 1c001a12 00068023 sb x0, 0(x13) x13:100fe709 PA:100fe709 + 21371500 21356 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21373500 21358 1c001e68 f17ff06f jal x0, -234 + 21375500 21360 1c001d7e 00410613 addi x12, x2, 4 x12=100fe6f4 x2:100fe6f0 + 21376500 21361 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21377500 21362 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21378500 21363 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21380500 21365 1c001a62 fe010113 addi x2, x2, -32 x2=100fe6d0 x2:100fe6f0 + 21381500 21366 1c001a64 00812c23 sw x8, 24(x2) x8:100fe778 x2:100fe6d0 PA:100fe6e8 + 21382500 21367 1c001a66 01062783 lw x15, 16(x12) x15=100fe708 x12:100fe6f4 PA:100fe704 + 21383500 21368 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100fe6f4 PA:100fe6f8 + 21384500 21369 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100fe6d0 PA:100fe6e4 + 21385500 21370 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100fe6d0 PA:100fe6e0 + 21386500 21371 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100fe6d0 PA:100fe6dc + 21387500 21372 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100fe6d0 PA:100fe6ec + 21388500 21373 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100fe6d0 PA:100fe6d8 + 21389500 21374 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21390500 21375 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21391500 21376 1c001a78 00c004b3 add x9, x0, x12 x9=100fe6f4 x12:100fe6f4 + 21392500 21377 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000034 x15=100fe709 x15:100fe708 PA:100fe708 + 21394500 21379 1c001a7e 00070363 beq x14, x0, 6 x14:00000034 + 21395500 21380 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21396500 21381 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100fe6f4 PA:100fe6fc + 21398500 21383 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21401500 21386 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 21403500 21388 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21404500 21389 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21407500 21392 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21408500 21393 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21409500 21394 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21412500 21397 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21413500 21398 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21414500 21399 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21415500 21400 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21416500 21401 1c001b36 f71ff06f jal x0, -144 + 21418500 21403 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100fe6f4 PA:100fe6fc + 21420500 21405 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21423500 21408 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 21425500 21410 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21426500 21411 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21429500 21414 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 21430500 21415 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21431500 21416 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21432500 21417 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21433500 21418 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fe708 x9:100fe6f4 PA:100fe704 + 21435500 21420 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000034 x20=100fe709 x20:100fe708 PA:100fe708 + 21437500 21422 1c001af0 06059763 bne x11, x0, 110 x11:00000034 + 21440500 21425 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21441500 21426 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21443500 21428 1c001776 00b00533 add x10, x0, x11 x10=00000034 x11:00000034 + 21444500 21429 1c001778 fddff06f jal x0, -36 + 21446500 21431 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21447500 21432 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 21448500 21433 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21449500 21434 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 21450500 21435 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 21451500 21436 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 21452500 21437 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 21453500 21438 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 21454500 21439 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21455500 21440 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000034 x14:1a104000 PA:1a104020 + 21459500 21444 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21460500 21445 1c001b62 f8bff06f jal x0, -118 + 21462500 21447 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fe70a x20:100fe709 PA:100fe709 + 21464500 21449 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21465500 21450 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100fe6f4 PA:100fe6f4 + 21467500 21452 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21468500 21453 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21471500 21456 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100fe6d0 PA:100fe6ec + 21472500 21457 1c001b02 01812403 lw x8, 24(x2) x8=100fe778 x2:100fe6d0 PA:100fe6e8 + 21473500 21458 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100fe6d0 PA:100fe6e4 + 21474500 21459 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100fe6d0 PA:100fe6e0 + 21475500 21460 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100fe6d0 PA:100fe6dc + 21476500 21461 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100fe6d0 PA:100fe6d8 + 21477500 21462 1c001b0c 02010113 addi x2, x2, 32 x2=100fe6f0 x2:100fe6d0 + 21478500 21463 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21480500 21465 1c001d86 01800433 add x8, x0, x24 x8=100fe77c x24:100fe77c + 21481500 21466 1c001d88 fadff06f jal x0, -84 + 21483500 21468 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21484500 21469 1c001d36 e69ff06f jal x0, -408 + 21487500 21472 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21502500 21487 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21503500 21488 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21506500 21491 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21507500 21492 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21508500 21493 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21510500 21495 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21511500 21496 1c001778 fddff06f jal x0, -36 + 21513500 21498 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21514500 21499 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 21515500 21500 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21516500 21501 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 21517500 21502 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 21518500 21503 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 21519500 21504 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 21520500 21505 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 21521500 21506 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21522500 21507 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104020 + 21526500 21511 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21527500 21512 1c001bca 16a0006f jal x0, 362 + 21529500 21514 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21530500 21515 1c001d36 e69ff06f jal x0, -408 + 21533500 21518 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21547500 21532 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21548500 21533 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21551500 21536 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21552500 21537 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21553500 21538 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21555500 21540 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21556500 21541 1c001778 fddff06f jal x0, -36 + 21558500 21543 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21559500 21544 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 21560500 21545 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21561500 21546 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 21562500 21547 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 21563500 21548 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 21564500 21549 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 21565500 21550 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 21566500 21551 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21567500 21552 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104020 + 21571500 21556 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21572500 21557 1c001bca 16a0006f jal x0, 362 + 21574500 21559 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21575500 21560 1c001d36 e69ff06f jal x0, -408 + 21578500 21563 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21592500 21577 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21593500 21578 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21596500 21581 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21597500 21582 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21598500 21583 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21600500 21585 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21601500 21586 1c001778 fddff06f jal x0, -36 + 21603500 21588 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21604500 21589 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000004 + 21605500 21590 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21606500 21591 1c00175e 00379713 slli x14, x15, 0x3 x14=00000020 x15:00000004 + 21607500 21592 1c001762 00279793 slli x15, x15, 0x2 x15=00000010 x15:00000004 + 21608500 21593 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000020 + 21609500 21594 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000010 x13:00001f80 + 21610500 21595 1c00176a 00e787b3 add x15, x15, x14 x15=00000020 x15:00000000 x14:00000020 + 21611500 21596 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21612500 21597 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104020 + 21616500 21601 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21617500 21602 1c001bca 16a0006f jal x0, 362 + 21619500 21604 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21620500 21605 1c001d36 e69ff06f jal x0, -408 + 21623500 21608 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21638500 21623 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21639500 21624 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21640500 21625 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100fe6f0 PA:100fe74c + 21641500 21626 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100fe6f0 PA:100fe748 + 21642500 21627 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:100fe6f0 PA:100fe744 + 21643500 21628 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:100fe6f0 PA:100fe740 + 21644500 21629 1c001bb0 04c12983 lw x19, 76(x2) x19=00000004 x2:100fe6f0 PA:100fe73c + 21646500 21631 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:100fe6f0 PA:100fe738 + 21647500 21632 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:100fe6f0 PA:100fe734 + 21648500 21633 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100fe6f0 PA:100fe730 + 21649500 21634 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100fe6f0 PA:100fe72c + 21650500 21635 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100fe6f0 PA:100fe728 + 21651500 21636 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100fe6f0 PA:100fe724 + 21652500 21637 1c001bbe 06010113 addi x2, x2, 96 x2=100fe750 x2:100fe6f0 + 21653500 21638 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21655500 21640 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:100fe750 PA:100fe76c + 21656500 21641 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21657500 21642 1c001838 04010113 addi x2, x2, 64 x2=100fe790 x2:100fe750 + 21658500 21643 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21676500 21661 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_00_5.log b/sw/scripts/tracevis/example/traces/trace_core_00_5.log new file mode 100644 index 0000000..d8820aa --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_00_5.log @@ -0,0 +1,847 @@ + Time Cycles PC Instr Mnemonic + 108500 93 1c000080 0180006f jal x0, 24 + 131500 116 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000005 + 132500 117 1c00009c 01f57593 andi x11, x10, 31 x11=00000005 x10:00000005 + 154500 139 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000000 x10:00000005 + 155500 140 1c0000a2 00058463 beq x11, x0, 8 x11:00000005 + 156500 141 1c0000a6 05a0206f jal x0, 8282 + 179500 164 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 180500 165 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 181500 166 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 182500 167 1c00210c 0e059163 bne x11, x0, 226 x11:00000005 + 249500 234 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 250500 235 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000005 + 251500 236 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000005 x19:00000005 + 252500 237 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 271500 256 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 272500 257 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 273500 258 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 274500 259 1c00220a 0060006f jal x0, 6 + 294500 279 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 9629500 9614 1c002214 08096503 p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080 + 9637500 9622 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 9638500 9623 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 9656500 9641 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 9657500 9642 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 9659500 9644 1c00222c 08096283 p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080 + 9683500 9668 1c002230 02a98533 mul x10, x19, x10 x10=00002800 x19:00000005 x10:00000800 + 9684500 9669 1c002234 00550133 add x2, x10, x5 x2=100fef90 x10:00002800 x5:100fc790 + 9685500 9670 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 9705500 9690 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18829500 18814 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18837500 18822 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18838500 18823 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18839500 18824 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18840500 18825 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18863500 18848 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000005 + 18883500 18868 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18884500 18869 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000000 x12:00000005 + 18885500 18870 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000 + 18886500 18871 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000005 x12:00000005 + 18887500 18872 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18888500 18873 1c0009d4 63d0006f jal x0, 3644 + 18890500 18875 1c001810 fc010113 addi x2, x2, -64 x2=100fef50 x2:100fef90 + 18891500 18876 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:100fef50 PA:100fef74 + 18892500 18877 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18893500 18878 1c001818 02c12423 sw x12, 40(x2) x12:00000005 x2:100fef50 PA:100fef78 + 18894500 18879 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:100fef50 PA:100fef7c + 18895500 18880 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18896500 18881 1c00181e 02410693 addi x13, x2, 36 x13=100fef74 x2:100fef50 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:100fef50 PA:100fef6c + 18916500 18901 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:100fef50 PA:100fef80 + 18917500 18902 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:100fef50 PA:100fef84 + 18918500 18903 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:100fef50 PA:100fef88 + 18919500 18904 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:100fef50 PA:100fef8c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:100fef74 x2:100fef50 PA:100fef5c + 18941500 18926 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100feef0 x2:100fef50 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100fef08 x2:100feef0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100feef0 PA:100fef48 + 18964500 18949 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:100feef0 PA:100fef40 + 18966500 18951 1c001b78 05312623 sw x19, 76(x2) x19:00000005 x2:100feef0 PA:100fef3c + 18967500 18952 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:100feef0 PA:100fef38 + 18968500 18953 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:100feef0 PA:100fef34 + 18969500 18954 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100feef0 PA:100fef30 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100feef0 PA:100fef2c + 18988500 18973 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100feef0 PA:100fef4c + 18989500 18974 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:100feef0 PA:100fef44 + 18990500 18975 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100feef0 PA:100fef28 + 18991500 18976 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100feef0 PA:100fef24 + 18992500 18977 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18993500 18978 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18994500 18979 1c001b8e 00d00433 add x8, x0, x13 x8=100fef74 x13:100fef74 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100fef08 x2:100feef0 PA:100fef04 + 19017500 19002 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19018500 19003 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19019500 19004 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19020500 19005 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19062500 19047 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19063500 19048 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104028 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19185500 19170 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19186500 19171 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19189500 19174 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19190500 19175 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19191500 19176 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19193500 19178 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19194500 19179 1c001778 fddff06f jal x0, -36 + 19196500 19181 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19197500 19182 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19198500 19183 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19199500 19184 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19200500 19185 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19201500 19186 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19202500 19187 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19203500 19188 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19204500 19189 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19205500 19190 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104028 + 19209500 19194 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19210500 19195 1c001bca 16a0006f jal x0, 362 + 19212500 19197 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19213500 19198 1c001d36 e69ff06f jal x0, -408 + 19216500 19201 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19237500 19222 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19238500 19223 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19241500 19226 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19242500 19227 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19243500 19228 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19245500 19230 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19246500 19231 1c001778 fddff06f jal x0, -36 + 19248500 19233 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19249500 19234 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19250500 19235 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19251500 19236 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19252500 19237 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19253500 19238 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19254500 19239 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19255500 19240 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19256500 19241 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19257500 19242 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104028 + 19261500 19246 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19262500 19247 1c001bca 16a0006f jal x0, 362 + 19264500 19249 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19265500 19250 1c001d36 e69ff06f jal x0, -408 + 19268500 19253 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19286500 19271 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19287500 19272 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19290500 19275 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19291500 19276 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19292500 19277 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19294500 19279 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19295500 19280 1c001778 fddff06f jal x0, -36 + 19297500 19282 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19298500 19283 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19299500 19284 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19300500 19285 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19301500 19286 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19302500 19287 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19303500 19288 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19304500 19289 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19305500 19290 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19306500 19291 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104028 + 19310500 19295 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19311500 19296 1c001bca 16a0006f jal x0, 362 + 19313500 19298 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19314500 19299 1c001d36 e69ff06f jal x0, -408 + 19317500 19302 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19334500 19319 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19335500 19320 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19338500 19323 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19339500 19324 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19340500 19325 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19342500 19327 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19343500 19328 1c001778 fddff06f jal x0, -36 + 19345500 19330 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19346500 19331 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19347500 19332 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19348500 19333 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19349500 19334 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19350500 19335 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19351500 19336 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19352500 19337 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19353500 19338 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19354500 19339 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104028 + 19358500 19343 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19359500 19344 1c001bca 16a0006f jal x0, 362 + 19361500 19346 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19362500 19347 1c001d36 e69ff06f jal x0, -408 + 19365500 19350 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19384500 19369 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19385500 19370 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19388500 19373 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19389500 19374 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19390500 19375 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19392500 19377 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19393500 19378 1c001778 fddff06f jal x0, -36 + 19395500 19380 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19396500 19381 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19397500 19382 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19398500 19383 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19399500 19384 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19400500 19385 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19401500 19386 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19402500 19387 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19403500 19388 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19404500 19389 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104028 + 19408500 19393 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19409500 19394 1c001bca 16a0006f jal x0, 362 + 19411500 19396 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19412500 19397 1c001d36 e69ff06f jal x0, -408 + 19415500 19400 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19434500 19419 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19435500 19420 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19438500 19423 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19439500 19424 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19440500 19425 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19442500 19427 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19443500 19428 1c001778 fddff06f jal x0, -36 + 19445500 19430 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19446500 19431 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19447500 19432 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19448500 19433 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19449500 19434 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19450500 19435 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19451500 19436 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19452500 19437 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19453500 19438 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19454500 19439 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104028 + 19458500 19443 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19459500 19444 1c001bca 16a0006f jal x0, 362 + 19461500 19446 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19462500 19447 1c001d36 e69ff06f jal x0, -408 + 19465500 19450 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19490500 19475 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19491500 19476 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19494500 19479 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19495500 19480 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19496500 19481 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19498500 19483 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19499500 19484 1c001778 fddff06f jal x0, -36 + 19501500 19486 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19502500 19487 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19503500 19488 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19504500 19489 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19505500 19490 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19506500 19491 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19507500 19492 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19508500 19493 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19509500 19494 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19510500 19495 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104028 + 19514500 19499 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19515500 19500 1c001bca 16a0006f jal x0, 362 + 19517500 19502 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19518500 19503 1c001d36 e69ff06f jal x0, -408 + 19521500 19506 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19537500 19522 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19538500 19523 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19541500 19526 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19542500 19527 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19543500 19528 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19545500 19530 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19546500 19531 1c001778 fddff06f jal x0, -36 + 19548500 19533 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19549500 19534 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19550500 19535 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19551500 19536 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19552500 19537 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19553500 19538 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19554500 19539 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19555500 19540 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19556500 19541 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19557500 19542 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104028 + 19561500 19546 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19562500 19547 1c001bca 16a0006f jal x0, 362 + 19564500 19549 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19565500 19550 1c001d36 e69ff06f jal x0, -408 + 19568500 19553 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19589500 19574 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19590500 19575 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19593500 19578 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19594500 19579 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19595500 19580 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19597500 19582 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19598500 19583 1c001778 fddff06f jal x0, -36 + 19600500 19585 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19601500 19586 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19602500 19587 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19603500 19588 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19604500 19589 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19605500 19590 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19606500 19591 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19607500 19592 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19608500 19593 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19609500 19594 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104028 + 19613500 19598 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19614500 19599 1c001bca 16a0006f jal x0, 362 + 19616500 19601 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19617500 19602 1c001d36 e69ff06f jal x0, -408 + 19620500 19605 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19634500 19619 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19635500 19620 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19638500 19623 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19639500 19624 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19640500 19625 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19642500 19627 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19643500 19628 1c001778 fddff06f jal x0, -36 + 19645500 19630 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19646500 19631 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19647500 19632 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19648500 19633 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19649500 19634 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19650500 19635 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19651500 19636 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19652500 19637 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19653500 19638 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19654500 19639 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104028 + 19658500 19643 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19659500 19644 1c001bca 16a0006f jal x0, 362 + 19661500 19646 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19662500 19647 1c001d36 e69ff06f jal x0, -408 + 19665500 19650 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19679500 19664 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19680500 19665 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19683500 19668 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19684500 19669 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19685500 19670 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19687500 19672 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19688500 19673 1c001778 fddff06f jal x0, -36 + 19690500 19675 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19691500 19676 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19692500 19677 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19693500 19678 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19694500 19679 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19695500 19680 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19696500 19681 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19697500 19682 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19698500 19683 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19699500 19684 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104028 + 19703500 19688 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19704500 19689 1c001bca 16a0006f jal x0, 362 + 19706500 19691 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19707500 19692 1c001d36 e69ff06f jal x0, -408 + 19710500 19695 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19724500 19709 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19725500 19710 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19728500 19713 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19729500 19714 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19730500 19715 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19732500 19717 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19733500 19718 1c001778 fddff06f jal x0, -36 + 19735500 19720 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19736500 19721 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19737500 19722 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19738500 19723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19739500 19724 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19740500 19725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19741500 19726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19742500 19727 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19743500 19728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19744500 19729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104028 + 19748500 19733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19749500 19734 1c001bca 16a0006f jal x0, 362 + 19751500 19736 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19752500 19737 1c001d36 e69ff06f jal x0, -408 + 19755500 19740 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19770500 19755 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19771500 19756 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19774500 19759 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19775500 19760 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19776500 19761 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19778500 19763 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19779500 19764 1c001778 fddff06f jal x0, -36 + 19781500 19766 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19782500 19767 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19783500 19768 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19784500 19769 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19785500 19770 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19786500 19771 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19787500 19772 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19788500 19773 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19789500 19774 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19790500 19775 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104028 + 19794500 19779 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19795500 19780 1c001bca 16a0006f jal x0, 362 + 19797500 19782 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19798500 19783 1c001d36 e69ff06f jal x0, -408 + 19801500 19786 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19820500 19805 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19821500 19806 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19824500 19809 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19825500 19810 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19826500 19811 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19828500 19813 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19829500 19814 1c001778 fddff06f jal x0, -36 + 19831500 19816 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19832500 19817 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 19833500 19818 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19834500 19819 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 19835500 19820 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 19836500 19821 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 19837500 19822 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 19838500 19823 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 19839500 19824 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19840500 19825 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104028 + 19844500 19829 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19845500 19830 1c001bca 16a0006f jal x0, 362 + 19847500 19832 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19848500 19833 1c001d36 e69ff06f jal x0, -408 + 19851500 19836 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19867500 19852 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19868500 19853 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19871500 19856 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19874500 19859 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100feef0 PA:100feef4 + 19893500 19878 1c001bd0 00012423 sw x0, 8(x2) x2:100feef0 PA:100feef8 + 19894500 19879 1c001bd2 00010623 sb x0, 12(x2) x2:100feef0 PA:100feefc + 19895500 19880 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19896500 19881 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19897500 19882 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19898500 19883 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100feef0 PA:100feef4 + 19903500 19888 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19904500 19889 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19905500 19890 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19906500 19891 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19907500 19892 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19954500 19939 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19955500 19940 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100feef0 PA:100fef00 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=100fef78 x8:100fef74 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:100fef74 PA:100fef74 + 20314500 20299 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100feef4 x2:100feef0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100fef08 x11:100feef4 PA:100fef04 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100feef4 PA:100fef00 + 20408500 20393 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20409500 20394 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20443500 20428 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20444500 20429 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20445500 20430 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20446500 20431 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20449500 20434 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100feef4 PA:100fef00 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100fef08 PA:100fef08 + 20587500 20572 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20588500 20573 1c001a5e 00168693 addi x13, x13, 1 x13=100fef09 x13:100fef08 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100fef09 PA:100fef09 + 20609500 20594 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20610500 20595 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100feef4 x2:100feef0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100feed0 x2:100feef0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:100fef74 x2:100feed0 PA:100feee8 + 20650500 20635 1c001a66 01062783 lw x15, 16(x12) x15=100fef08 x12:100feef4 PA:100fef04 + 20651500 20636 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100feef4 PA:100feef8 + 20652500 20637 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100feed0 PA:100feee4 + 20653500 20638 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100feed0 PA:100feee0 + 20654500 20639 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100feed0 PA:100feedc + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100feed0 PA:100feeec + 20679500 20664 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100feed0 PA:100feed8 + 20681500 20666 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20682500 20667 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20683500 20668 1c001a78 00c004b3 add x9, x0, x12 x9=100feef4 x12:100feef4 + 20684500 20669 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100fef09 x15:100fef08 PA:100fef08 + 20686500 20671 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100feef4 PA:100feefc + 20704500 20689 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20707500 20692 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100feef4 PA:100feefc + 20794500 20779 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 20821500 20806 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20822500 20807 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fef08 x9:100feef4 PA:100fef04 + 20862500 20847 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100fef09 x20:100fef08 PA:100fef08 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104028 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fef0a x20:100fef09 PA:100fef09 + 20935500 20920 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20936500 20921 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 20938500 20923 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20939500 20924 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100feed0 PA:100feeec + 20964500 20949 1c001b02 01812403 lw x8, 24(x2) x8=100fef74 x2:100feed0 PA:100feee8 + 20965500 20950 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100feed0 PA:100feee4 + 20966500 20951 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100feed0 PA:100feee0 + 20967500 20952 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100feed0 PA:100feedc + 20968500 20953 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100feed0 PA:100feed8 + 20969500 20954 1c001b0c 02010113 addi x2, x2, 32 x2=100feef0 x2:100feed0 + 20970500 20955 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=100fef78 x24:100fef78 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21013500 20998 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21014500 20999 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21017500 21002 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21018500 21003 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21019500 21004 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21021500 21006 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21022500 21007 1c001778 fddff06f jal x0, -36 + 21024500 21009 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21025500 21010 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 21026500 21011 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21027500 21012 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 21028500 21013 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 21029500 21014 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 21030500 21015 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 21031500 21016 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 21032500 21017 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21033500 21018 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104028 + 21037500 21022 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21038500 21023 1c001bca 16a0006f jal x0, 362 + 21040500 21025 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21041500 21026 1c001d36 e69ff06f jal x0, -408 + 21044500 21029 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21061500 21046 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21062500 21047 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21065500 21050 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21066500 21051 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21067500 21052 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21069500 21054 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21070500 21055 1c001778 fddff06f jal x0, -36 + 21072500 21057 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21073500 21058 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 21074500 21059 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21075500 21060 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 21076500 21061 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 21077500 21062 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 21078500 21063 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 21079500 21064 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 21080500 21065 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21081500 21066 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104028 + 21085500 21070 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21086500 21071 1c001bca 16a0006f jal x0, 362 + 21088500 21073 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21089500 21074 1c001d36 e69ff06f jal x0, -408 + 21092500 21077 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21106500 21091 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21107500 21092 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21110500 21095 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21113500 21098 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100feef0 PA:100feef4 + 21114500 21099 1c001bd0 00012423 sw x0, 8(x2) x2:100feef0 PA:100feef8 + 21115500 21100 1c001bd2 00010623 sb x0, 12(x2) x2:100feef0 PA:100feefc + 21116500 21101 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21117500 21102 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21118500 21103 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21119500 21104 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100feef0 PA:100feef4 + 21121500 21106 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21122500 21107 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21123500 21108 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21124500 21109 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21125500 21110 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21126500 21111 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21127500 21112 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21128500 21113 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21149500 21134 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21150500 21135 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21153500 21138 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21154500 21139 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21155500 21140 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21158500 21143 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21161500 21146 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21164500 21149 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21167500 21152 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21168500 21153 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21169500 21154 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21170500 21155 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21173500 21158 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21174500 21159 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21177500 21162 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21178500 21163 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21181500 21166 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21183500 21168 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21186500 21171 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21187500 21172 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21190500 21175 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21191500 21176 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21192500 21177 1c001f42 e09ff06f jal x0, -504 + 21194500 21179 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21195500 21180 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100feef0 PA:100fef00 + 21196500 21181 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21199500 21184 1c001e34 00440c13 addi x24, x8, 4 x24=100fef7c x8:100fef78 + 21200500 21185 1c001e38 00042503 lw x10, 0(x8) x10=00000005 x8:100fef78 PA:100fef78 + 21201500 21186 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21204500 21189 1c001e54 00055863 bge x10, x0, 16 x10:00000005 + 21207500 21192 1c001e64 00410593 addi x11, x2, 4 x11=100feef4 x2:100feef0 + 21208500 21193 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21210500 21195 1c0019fe 0105a683 lw x13, 16(x11) x13=100fef08 x11:100feef4 PA:100fef04 + 21211500 21196 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100feef4 PA:100fef00 + 21212500 21197 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21213500 21198 1c001a04 02f55633 divu x12, x10, x15 x12=00000005 x10:00000005 x15:00000001 + 21247500 21232 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000005 x14:0000000a + 21248500 21233 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21249500 21234 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21250500 21235 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21253500 21238 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100feef4 PA:100fef00 + 21254500 21239 1c001a20 02f55833 divu x16, x10, x15 x16=00000005 x10:00000005 x15:00000001 + 21288500 21273 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000005 x15:00000001 + 21322500 21307 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21353500 21338 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21354500 21339 1c001a2e 01004663 blt x0, x16, 12 x16:00000005 + 21357500 21342 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21375500 21360 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000005 + 21378500 21363 1c001a56 01070733 add x14, x14, x16 x14=00000035 x14:00000030 x16:00000005 + 21379500 21364 1c001a58 00e68023 sb x14, 0(x13) x14:00000035 x13:100fef08 PA:100fef08 + 21380500 21365 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21381500 21366 1c001a5e 00168693 addi x13, x13, 1 x13=100fef09 x13:100fef08 + 21382500 21367 1c001a60 fb1ff06f jal x0, -80 + 21384500 21369 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21385500 21370 1c001a12 00068023 sb x0, 0(x13) x13:100fef09 PA:100fef09 + 21386500 21371 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21388500 21373 1c001e68 f17ff06f jal x0, -234 + 21390500 21375 1c001d7e 00410613 addi x12, x2, 4 x12=100feef4 x2:100feef0 + 21391500 21376 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21392500 21377 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21393500 21378 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21395500 21380 1c001a62 fe010113 addi x2, x2, -32 x2=100feed0 x2:100feef0 + 21396500 21381 1c001a64 00812c23 sw x8, 24(x2) x8:100fef78 x2:100feed0 PA:100feee8 + 21397500 21382 1c001a66 01062783 lw x15, 16(x12) x15=100fef08 x12:100feef4 PA:100fef04 + 21398500 21383 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100feef4 PA:100feef8 + 21399500 21384 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100feed0 PA:100feee4 + 21400500 21385 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100feed0 PA:100feee0 + 21401500 21386 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100feed0 PA:100feedc + 21402500 21387 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100feed0 PA:100feeec + 21403500 21388 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100feed0 PA:100feed8 + 21404500 21389 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21405500 21390 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21406500 21391 1c001a78 00c004b3 add x9, x0, x12 x9=100feef4 x12:100feef4 + 21407500 21392 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000035 x15=100fef09 x15:100fef08 PA:100fef08 + 21409500 21394 1c001a7e 00070363 beq x14, x0, 6 x14:00000035 + 21410500 21395 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21411500 21396 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100feef4 PA:100feefc + 21413500 21398 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21416500 21401 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 21418500 21403 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21419500 21404 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21422500 21407 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21423500 21408 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21424500 21409 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21427500 21412 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21428500 21413 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21429500 21414 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21430500 21415 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21431500 21416 1c001b36 f71ff06f jal x0, -144 + 21433500 21418 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100feef4 PA:100feefc + 21435500 21420 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21438500 21423 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 21440500 21425 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21441500 21426 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21444500 21429 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 21445500 21430 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21446500 21431 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21447500 21432 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21448500 21433 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fef08 x9:100feef4 PA:100fef04 + 21450500 21435 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000035 x20=100fef09 x20:100fef08 PA:100fef08 + 21452500 21437 1c001af0 06059763 bne x11, x0, 110 x11:00000035 + 21455500 21440 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21456500 21441 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21458500 21443 1c001776 00b00533 add x10, x0, x11 x10=00000035 x11:00000035 + 21459500 21444 1c001778 fddff06f jal x0, -36 + 21461500 21446 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21462500 21447 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 21463500 21448 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21464500 21449 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 21465500 21450 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 21466500 21451 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 21467500 21452 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 21468500 21453 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 21469500 21454 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21470500 21455 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000035 x14:1a104000 PA:1a104028 + 21474500 21459 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21475500 21460 1c001b62 f8bff06f jal x0, -118 + 21477500 21462 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fef0a x20:100fef09 PA:100fef09 + 21479500 21464 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21480500 21465 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100feef4 PA:100feef4 + 21482500 21467 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21483500 21468 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21486500 21471 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100feed0 PA:100feeec + 21487500 21472 1c001b02 01812403 lw x8, 24(x2) x8=100fef78 x2:100feed0 PA:100feee8 + 21488500 21473 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100feed0 PA:100feee4 + 21489500 21474 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100feed0 PA:100feee0 + 21490500 21475 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100feed0 PA:100feedc + 21491500 21476 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100feed0 PA:100feed8 + 21492500 21477 1c001b0c 02010113 addi x2, x2, 32 x2=100feef0 x2:100feed0 + 21493500 21478 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21495500 21480 1c001d86 01800433 add x8, x0, x24 x8=100fef7c x24:100fef7c + 21496500 21481 1c001d88 fadff06f jal x0, -84 + 21498500 21483 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21499500 21484 1c001d36 e69ff06f jal x0, -408 + 21502500 21487 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21517500 21502 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21518500 21503 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21521500 21506 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21522500 21507 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21523500 21508 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21525500 21510 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21526500 21511 1c001778 fddff06f jal x0, -36 + 21528500 21513 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21529500 21514 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 21530500 21515 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21531500 21516 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 21532500 21517 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 21533500 21518 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 21534500 21519 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 21535500 21520 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 21536500 21521 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21537500 21522 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104028 + 21541500 21526 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21542500 21527 1c001bca 16a0006f jal x0, 362 + 21544500 21529 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21545500 21530 1c001d36 e69ff06f jal x0, -408 + 21548500 21533 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21562500 21547 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21563500 21548 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21566500 21551 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21567500 21552 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21568500 21553 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21570500 21555 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21571500 21556 1c001778 fddff06f jal x0, -36 + 21573500 21558 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21574500 21559 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 21575500 21560 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21576500 21561 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 21577500 21562 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 21578500 21563 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 21579500 21564 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 21580500 21565 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 21581500 21566 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21582500 21567 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104028 + 21586500 21571 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21587500 21572 1c001bca 16a0006f jal x0, 362 + 21589500 21574 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21590500 21575 1c001d36 e69ff06f jal x0, -408 + 21593500 21578 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21607500 21592 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21608500 21593 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21611500 21596 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21612500 21597 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21613500 21598 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21615500 21600 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21616500 21601 1c001778 fddff06f jal x0, -36 + 21618500 21603 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21619500 21604 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000005 + 21620500 21605 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21621500 21606 1c00175e 00379713 slli x14, x15, 0x3 x14=00000028 x15:00000005 + 21622500 21607 1c001762 00279793 slli x15, x15, 0x2 x15=00000014 x15:00000005 + 21623500 21608 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000028 + 21624500 21609 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000014 x13:00001f80 + 21625500 21610 1c00176a 00e787b3 add x15, x15, x14 x15=00000028 x15:00000000 x14:00000028 + 21626500 21611 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21627500 21612 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104028 + 21631500 21616 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21632500 21617 1c001bca 16a0006f jal x0, 362 + 21634500 21619 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21635500 21620 1c001d36 e69ff06f jal x0, -408 + 21638500 21623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21652500 21637 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21653500 21638 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21654500 21639 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100feef0 PA:100fef4c + 21655500 21640 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100feef0 PA:100fef48 + 21656500 21641 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:100feef0 PA:100fef44 + 21657500 21642 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:100feef0 PA:100fef40 + 21658500 21643 1c001bb0 04c12983 lw x19, 76(x2) x19=00000005 x2:100feef0 PA:100fef3c + 21659500 21644 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:100feef0 PA:100fef38 + 21660500 21645 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:100feef0 PA:100fef34 + 21661500 21646 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100feef0 PA:100fef30 + 21662500 21647 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100feef0 PA:100fef2c + 21663500 21648 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100feef0 PA:100fef28 + 21664500 21649 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100feef0 PA:100fef24 + 21665500 21650 1c001bbe 06010113 addi x2, x2, 96 x2=100fef50 x2:100feef0 + 21666500 21651 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21668500 21653 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:100fef50 PA:100fef6c + 21669500 21654 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21670500 21655 1c001838 04010113 addi x2, x2, 64 x2=100fef90 x2:100fef50 + 21671500 21656 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21677500 21662 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_00_6.log b/sw/scripts/tracevis/example/traces/trace_core_00_6.log new file mode 100644 index 0000000..f1bc1bc --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_00_6.log @@ -0,0 +1,847 @@ + Time Cycles PC Instr Mnemonic + 110500 95 1c000080 0180006f jal x0, 24 + 134500 119 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000006 + 135500 120 1c00009c 01f57593 andi x11, x10, 31 x11=00000006 x10:00000006 + 158500 143 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000000 x10:00000006 + 159500 144 1c0000a2 00058463 beq x11, x0, 8 x11:00000006 + 160500 145 1c0000a6 05a0206f jal x0, 8282 + 181500 166 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 182500 167 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 183500 168 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 184500 169 1c00210c 0e059163 bne x11, x0, 226 x11:00000006 + 252500 237 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 253500 238 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000006 + 254500 239 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000006 x19:00000006 + 255500 240 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 274500 259 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 275500 260 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 276500 261 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 277500 262 1c00220a 0060006f jal x0, 6 + 298500 283 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 9629500 9614 1c002214 08096503 p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080 + 9637500 9622 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 9638500 9623 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 9656500 9641 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 9657500 9642 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 9659500 9644 1c00222c 08096283 p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080 + 9683500 9668 1c002230 02a98533 mul x10, x19, x10 x10=00003000 x19:00000006 x10:00000800 + 9684500 9669 1c002234 00550133 add x2, x10, x5 x2=100ff790 x10:00003000 x5:100fc790 + 9685500 9670 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 9705500 9690 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18829500 18814 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18837500 18822 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18838500 18823 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18839500 18824 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18840500 18825 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18863500 18848 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000006 + 18883500 18868 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18884500 18869 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000000 x12:00000006 + 18885500 18870 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000 + 18886500 18871 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000006 x12:00000006 + 18887500 18872 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18888500 18873 1c0009d4 63d0006f jal x0, 3644 + 18890500 18875 1c001810 fc010113 addi x2, x2, -64 x2=100ff750 x2:100ff790 + 18891500 18876 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:100ff750 PA:100ff774 + 18893500 18878 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18894500 18879 1c001818 02c12423 sw x12, 40(x2) x12:00000006 x2:100ff750 PA:100ff778 + 18895500 18880 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:100ff750 PA:100ff77c + 18896500 18881 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18897500 18882 1c00181e 02410693 addi x13, x2, 36 x13=100ff774 x2:100ff750 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:100ff750 PA:100ff76c + 18921500 18906 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:100ff750 PA:100ff780 + 18922500 18907 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:100ff750 PA:100ff784 + 18923500 18908 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:100ff750 PA:100ff788 + 18924500 18909 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:100ff750 PA:100ff78c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:100ff774 x2:100ff750 PA:100ff75c + 18942500 18927 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100ff6f0 x2:100ff750 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100ff708 x2:100ff6f0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100ff6f0 PA:100ff748 + 18965500 18950 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:100ff6f0 PA:100ff740 + 18967500 18952 1c001b78 05312623 sw x19, 76(x2) x19:00000006 x2:100ff6f0 PA:100ff73c + 18968500 18953 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:100ff6f0 PA:100ff738 + 18969500 18954 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:100ff6f0 PA:100ff734 + 18970500 18955 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100ff6f0 PA:100ff730 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100ff6f0 PA:100ff72c + 18983500 18968 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100ff6f0 PA:100ff74c + 18984500 18969 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:100ff6f0 PA:100ff744 + 18985500 18970 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100ff6f0 PA:100ff728 + 18986500 18971 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100ff6f0 PA:100ff724 + 18987500 18972 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18988500 18973 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18989500 18974 1c001b8e 00d00433 add x8, x0, x13 x8=100ff774 x13:100ff774 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100ff708 x2:100ff6f0 PA:100ff704 + 19018500 19003 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19019500 19004 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19020500 19005 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19021500 19006 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19067500 19052 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19068500 19053 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104030 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19187500 19172 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19188500 19173 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19191500 19176 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19192500 19177 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19193500 19178 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19195500 19180 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19196500 19181 1c001778 fddff06f jal x0, -36 + 19198500 19183 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19199500 19184 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19200500 19185 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19201500 19186 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19202500 19187 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19203500 19188 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19204500 19189 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19205500 19190 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19206500 19191 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19207500 19192 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104030 + 19211500 19196 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19212500 19197 1c001bca 16a0006f jal x0, 362 + 19214500 19199 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19215500 19200 1c001d36 e69ff06f jal x0, -408 + 19218500 19203 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19243500 19228 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19244500 19229 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19247500 19232 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19248500 19233 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19249500 19234 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19251500 19236 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19252500 19237 1c001778 fddff06f jal x0, -36 + 19254500 19239 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19255500 19240 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19256500 19241 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19257500 19242 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19258500 19243 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19259500 19244 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19260500 19245 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19261500 19246 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19262500 19247 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19263500 19248 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104030 + 19267500 19252 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19268500 19253 1c001bca 16a0006f jal x0, 362 + 19270500 19255 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19271500 19256 1c001d36 e69ff06f jal x0, -408 + 19274500 19259 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19290500 19275 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19291500 19276 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19294500 19279 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19295500 19280 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19296500 19281 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19298500 19283 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19299500 19284 1c001778 fddff06f jal x0, -36 + 19301500 19286 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19302500 19287 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19303500 19288 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19304500 19289 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19305500 19290 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19306500 19291 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19307500 19292 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19308500 19293 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19309500 19294 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19310500 19295 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104030 + 19314500 19299 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19315500 19300 1c001bca 16a0006f jal x0, 362 + 19317500 19302 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19318500 19303 1c001d36 e69ff06f jal x0, -408 + 19321500 19306 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19338500 19323 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19339500 19324 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19342500 19327 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19343500 19328 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19344500 19329 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19346500 19331 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19347500 19332 1c001778 fddff06f jal x0, -36 + 19349500 19334 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19350500 19335 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19351500 19336 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19352500 19337 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19353500 19338 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19354500 19339 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19355500 19340 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19356500 19341 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19357500 19342 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19358500 19343 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104030 + 19362500 19347 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19363500 19348 1c001bca 16a0006f jal x0, 362 + 19365500 19350 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19366500 19351 1c001d36 e69ff06f jal x0, -408 + 19369500 19354 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19390500 19375 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19391500 19376 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19394500 19379 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19395500 19380 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19396500 19381 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19398500 19383 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19399500 19384 1c001778 fddff06f jal x0, -36 + 19401500 19386 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19402500 19387 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19403500 19388 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19404500 19389 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19405500 19390 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19406500 19391 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19407500 19392 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19408500 19393 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19409500 19394 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19410500 19395 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104030 + 19414500 19399 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19415500 19400 1c001bca 16a0006f jal x0, 362 + 19417500 19402 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19418500 19403 1c001d36 e69ff06f jal x0, -408 + 19421500 19406 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19440500 19425 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19441500 19426 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19444500 19429 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19445500 19430 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19446500 19431 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19448500 19433 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19449500 19434 1c001778 fddff06f jal x0, -36 + 19451500 19436 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19452500 19437 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19453500 19438 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19454500 19439 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19455500 19440 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19456500 19441 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19457500 19442 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19458500 19443 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19459500 19444 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19460500 19445 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104030 + 19464500 19449 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19465500 19450 1c001bca 16a0006f jal x0, 362 + 19467500 19452 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19468500 19453 1c001d36 e69ff06f jal x0, -408 + 19471500 19456 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19492500 19477 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19493500 19478 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19496500 19481 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19497500 19482 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19498500 19483 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19500500 19485 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19501500 19486 1c001778 fddff06f jal x0, -36 + 19503500 19488 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19504500 19489 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19505500 19490 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19506500 19491 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19507500 19492 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19508500 19493 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19509500 19494 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19510500 19495 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19511500 19496 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19512500 19497 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104030 + 19516500 19501 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19517500 19502 1c001bca 16a0006f jal x0, 362 + 19519500 19504 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19520500 19505 1c001d36 e69ff06f jal x0, -408 + 19523500 19508 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19540500 19525 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19541500 19526 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19544500 19529 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19545500 19530 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19546500 19531 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19548500 19533 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19549500 19534 1c001778 fddff06f jal x0, -36 + 19551500 19536 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19552500 19537 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19553500 19538 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19554500 19539 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19555500 19540 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19556500 19541 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19557500 19542 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19558500 19543 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19559500 19544 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19560500 19545 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104030 + 19564500 19549 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19565500 19550 1c001bca 16a0006f jal x0, 362 + 19567500 19552 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19568500 19553 1c001d36 e69ff06f jal x0, -408 + 19571500 19556 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19593500 19578 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19594500 19579 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19597500 19582 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19598500 19583 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19599500 19584 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19601500 19586 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19602500 19587 1c001778 fddff06f jal x0, -36 + 19604500 19589 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19605500 19590 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19606500 19591 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19607500 19592 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19608500 19593 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19609500 19594 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19610500 19595 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19611500 19596 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19612500 19597 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19613500 19598 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104030 + 19617500 19602 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19618500 19603 1c001bca 16a0006f jal x0, 362 + 19620500 19605 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19621500 19606 1c001d36 e69ff06f jal x0, -408 + 19624500 19609 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19638500 19623 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19639500 19624 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19642500 19627 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19643500 19628 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19644500 19629 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19646500 19631 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19647500 19632 1c001778 fddff06f jal x0, -36 + 19649500 19634 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19650500 19635 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19651500 19636 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19652500 19637 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19653500 19638 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19654500 19639 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19655500 19640 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19656500 19641 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19657500 19642 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19658500 19643 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104030 + 19662500 19647 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19663500 19648 1c001bca 16a0006f jal x0, 362 + 19665500 19650 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19666500 19651 1c001d36 e69ff06f jal x0, -408 + 19669500 19654 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19683500 19668 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19684500 19669 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19687500 19672 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19688500 19673 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19689500 19674 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19691500 19676 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19692500 19677 1c001778 fddff06f jal x0, -36 + 19694500 19679 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19695500 19680 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19696500 19681 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19697500 19682 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19698500 19683 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19699500 19684 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19700500 19685 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19701500 19686 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19702500 19687 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19703500 19688 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104030 + 19707500 19692 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19708500 19693 1c001bca 16a0006f jal x0, 362 + 19710500 19695 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19711500 19696 1c001d36 e69ff06f jal x0, -408 + 19714500 19699 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19728500 19713 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19729500 19714 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19732500 19717 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19733500 19718 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19734500 19719 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19736500 19721 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19737500 19722 1c001778 fddff06f jal x0, -36 + 19739500 19724 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19740500 19725 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19741500 19726 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19742500 19727 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19743500 19728 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19744500 19729 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19745500 19730 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19746500 19731 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19747500 19732 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19748500 19733 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104030 + 19752500 19737 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19753500 19738 1c001bca 16a0006f jal x0, 362 + 19755500 19740 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19756500 19741 1c001d36 e69ff06f jal x0, -408 + 19759500 19744 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19774500 19759 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19775500 19760 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19778500 19763 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19779500 19764 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19780500 19765 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19782500 19767 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19783500 19768 1c001778 fddff06f jal x0, -36 + 19785500 19770 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19786500 19771 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19787500 19772 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19788500 19773 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19789500 19774 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19790500 19775 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19791500 19776 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19792500 19777 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19793500 19778 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19794500 19779 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104030 + 19798500 19783 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19799500 19784 1c001bca 16a0006f jal x0, 362 + 19801500 19786 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19802500 19787 1c001d36 e69ff06f jal x0, -408 + 19805500 19790 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19821500 19806 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19822500 19807 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19825500 19810 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19826500 19811 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19827500 19812 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19829500 19814 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19830500 19815 1c001778 fddff06f jal x0, -36 + 19832500 19817 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19833500 19818 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 19834500 19819 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19835500 19820 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 19836500 19821 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 19837500 19822 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 19838500 19823 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 19839500 19824 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 19840500 19825 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19841500 19826 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104030 + 19845500 19830 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19846500 19831 1c001bca 16a0006f jal x0, 362 + 19848500 19833 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19849500 19834 1c001d36 e69ff06f jal x0, -408 + 19852500 19837 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19869500 19854 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19870500 19855 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19873500 19858 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19876500 19861 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100ff6f0 PA:100ff6f4 + 19877500 19862 1c001bd0 00012423 sw x0, 8(x2) x2:100ff6f0 PA:100ff6f8 + 19880500 19865 1c001bd2 00010623 sb x0, 12(x2) x2:100ff6f0 PA:100ff6fc + 19881500 19866 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19882500 19867 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19896500 19881 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19897500 19882 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100ff6f0 PA:100ff6f4 + 19904500 19889 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19905500 19890 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19906500 19891 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19907500 19892 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19908500 19893 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19957500 19942 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19958500 19943 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100ff6f0 PA:100ff700 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=100ff778 x8:100ff774 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:100ff774 PA:100ff774 + 20309500 20294 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100ff6f4 x2:100ff6f0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100ff708 x11:100ff6f4 PA:100ff704 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ff6f4 PA:100ff700 + 20409500 20394 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20410500 20395 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20444500 20429 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20445500 20430 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20446500 20431 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20447500 20432 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20450500 20435 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ff6f4 PA:100ff700 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100ff708 PA:100ff708 + 20588500 20573 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20589500 20574 1c001a5e 00168693 addi x13, x13, 1 x13=100ff709 x13:100ff708 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100ff709 PA:100ff709 + 20610500 20595 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20611500 20596 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100ff6f4 x2:100ff6f0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100ff6d0 x2:100ff6f0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:100ff774 x2:100ff6d0 PA:100ff6e8 + 20651500 20636 1c001a66 01062783 lw x15, 16(x12) x15=100ff708 x12:100ff6f4 PA:100ff704 + 20652500 20637 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100ff6f4 PA:100ff6f8 + 20653500 20638 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100ff6d0 PA:100ff6e4 + 20654500 20639 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100ff6d0 PA:100ff6e0 + 20655500 20640 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100ff6d0 PA:100ff6dc + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100ff6d0 PA:100ff6ec + 20680500 20665 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100ff6d0 PA:100ff6d8 + 20682500 20667 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20683500 20668 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20684500 20669 1c001a78 00c004b3 add x9, x0, x12 x9=100ff6f4 x12:100ff6f4 + 20685500 20670 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100ff709 x15:100ff708 PA:100ff708 + 20687500 20672 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100ff6f4 PA:100ff6fc + 20699500 20684 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20702500 20687 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100ff6f4 PA:100ff6fc + 20800500 20785 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 20819500 20804 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20820500 20805 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100ff708 x9:100ff6f4 PA:100ff704 + 20863500 20848 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100ff709 x20:100ff708 PA:100ff708 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104030 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100ff70a x20:100ff709 PA:100ff709 + 20936500 20921 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20937500 20922 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 20939500 20924 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20940500 20925 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100ff6d0 PA:100ff6ec + 20965500 20950 1c001b02 01812403 lw x8, 24(x2) x8=100ff774 x2:100ff6d0 PA:100ff6e8 + 20966500 20951 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100ff6d0 PA:100ff6e4 + 20967500 20952 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100ff6d0 PA:100ff6e0 + 20968500 20953 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100ff6d0 PA:100ff6dc + 20969500 20954 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100ff6d0 PA:100ff6d8 + 20970500 20955 1c001b0c 02010113 addi x2, x2, 32 x2=100ff6f0 x2:100ff6d0 + 20971500 20956 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=100ff778 x24:100ff778 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21015500 21000 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21016500 21001 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21019500 21004 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21020500 21005 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21021500 21006 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21023500 21008 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21024500 21009 1c001778 fddff06f jal x0, -36 + 21026500 21011 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21027500 21012 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 21028500 21013 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21029500 21014 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 21030500 21015 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 21031500 21016 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 21032500 21017 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 21033500 21018 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 21034500 21019 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21035500 21020 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104030 + 21039500 21024 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21040500 21025 1c001bca 16a0006f jal x0, 362 + 21042500 21027 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21043500 21028 1c001d36 e69ff06f jal x0, -408 + 21046500 21031 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21063500 21048 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21064500 21049 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21067500 21052 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21068500 21053 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21069500 21054 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21071500 21056 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21072500 21057 1c001778 fddff06f jal x0, -36 + 21074500 21059 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21075500 21060 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 21076500 21061 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21077500 21062 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 21078500 21063 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 21079500 21064 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 21080500 21065 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 21081500 21066 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 21082500 21067 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21083500 21068 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104030 + 21087500 21072 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21088500 21073 1c001bca 16a0006f jal x0, 362 + 21090500 21075 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21091500 21076 1c001d36 e69ff06f jal x0, -408 + 21094500 21079 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21109500 21094 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21110500 21095 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21113500 21098 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21116500 21101 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100ff6f0 PA:100ff6f4 + 21119500 21104 1c001bd0 00012423 sw x0, 8(x2) x2:100ff6f0 PA:100ff6f8 + 21120500 21105 1c001bd2 00010623 sb x0, 12(x2) x2:100ff6f0 PA:100ff6fc + 21121500 21106 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21122500 21107 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21123500 21108 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21124500 21109 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100ff6f0 PA:100ff6f4 + 21125500 21110 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21126500 21111 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21127500 21112 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21128500 21113 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21129500 21114 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21130500 21115 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21131500 21116 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21132500 21117 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21153500 21138 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21154500 21139 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21157500 21142 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21158500 21143 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21159500 21144 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21162500 21147 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21165500 21150 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21168500 21153 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21171500 21156 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21172500 21157 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21173500 21158 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21174500 21159 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21177500 21162 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21178500 21163 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21181500 21166 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21182500 21167 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21185500 21170 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21187500 21172 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21190500 21175 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21191500 21176 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21194500 21179 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21195500 21180 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21196500 21181 1c001f42 e09ff06f jal x0, -504 + 21198500 21183 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21199500 21184 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100ff6f0 PA:100ff700 + 21200500 21185 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21203500 21188 1c001e34 00440c13 addi x24, x8, 4 x24=100ff77c x8:100ff778 + 21204500 21189 1c001e38 00042503 lw x10, 0(x8) x10=00000006 x8:100ff778 PA:100ff778 + 21205500 21190 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21208500 21193 1c001e54 00055863 bge x10, x0, 16 x10:00000006 + 21211500 21196 1c001e64 00410593 addi x11, x2, 4 x11=100ff6f4 x2:100ff6f0 + 21212500 21197 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21214500 21199 1c0019fe 0105a683 lw x13, 16(x11) x13=100ff708 x11:100ff6f4 PA:100ff704 + 21215500 21200 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ff6f4 PA:100ff700 + 21216500 21201 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21217500 21202 1c001a04 02f55633 divu x12, x10, x15 x12=00000006 x10:00000006 x15:00000001 + 21251500 21236 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000006 x14:0000000a + 21252500 21237 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21253500 21238 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21254500 21239 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21257500 21242 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ff6f4 PA:100ff700 + 21258500 21243 1c001a20 02f55833 divu x16, x10, x15 x16=00000006 x10:00000006 x15:00000001 + 21292500 21277 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000006 x15:00000001 + 21326500 21311 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21357500 21342 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21358500 21343 1c001a2e 01004663 blt x0, x16, 12 x16:00000006 + 21361500 21346 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21363500 21348 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000006 + 21366500 21351 1c001a56 01070733 add x14, x14, x16 x14=00000036 x14:00000030 x16:00000006 + 21367500 21352 1c001a58 00e68023 sb x14, 0(x13) x14:00000036 x13:100ff708 PA:100ff708 + 21369500 21354 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21370500 21355 1c001a5e 00168693 addi x13, x13, 1 x13=100ff709 x13:100ff708 + 21371500 21356 1c001a60 fb1ff06f jal x0, -80 + 21373500 21358 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21374500 21359 1c001a12 00068023 sb x0, 0(x13) x13:100ff709 PA:100ff709 + 21375500 21360 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21377500 21362 1c001e68 f17ff06f jal x0, -234 + 21379500 21364 1c001d7e 00410613 addi x12, x2, 4 x12=100ff6f4 x2:100ff6f0 + 21380500 21365 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21381500 21366 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21382500 21367 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21384500 21369 1c001a62 fe010113 addi x2, x2, -32 x2=100ff6d0 x2:100ff6f0 + 21385500 21370 1c001a64 00812c23 sw x8, 24(x2) x8:100ff778 x2:100ff6d0 PA:100ff6e8 + 21386500 21371 1c001a66 01062783 lw x15, 16(x12) x15=100ff708 x12:100ff6f4 PA:100ff704 + 21387500 21372 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100ff6f4 PA:100ff6f8 + 21388500 21373 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100ff6d0 PA:100ff6e4 + 21389500 21374 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100ff6d0 PA:100ff6e0 + 21390500 21375 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100ff6d0 PA:100ff6dc + 21391500 21376 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100ff6d0 PA:100ff6ec + 21392500 21377 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100ff6d0 PA:100ff6d8 + 21393500 21378 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21394500 21379 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21395500 21380 1c001a78 00c004b3 add x9, x0, x12 x9=100ff6f4 x12:100ff6f4 + 21396500 21381 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000036 x15=100ff709 x15:100ff708 PA:100ff708 + 21398500 21383 1c001a7e 00070363 beq x14, x0, 6 x14:00000036 + 21399500 21384 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21400500 21385 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100ff6f4 PA:100ff6fc + 21402500 21387 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21405500 21390 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 21407500 21392 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21408500 21393 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21411500 21396 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21412500 21397 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21413500 21398 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21416500 21401 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21417500 21402 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21418500 21403 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21419500 21404 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21420500 21405 1c001b36 f71ff06f jal x0, -144 + 21422500 21407 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100ff6f4 PA:100ff6fc + 21424500 21409 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21427500 21412 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 21429500 21414 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21430500 21415 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21433500 21418 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 21434500 21419 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21435500 21420 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21436500 21421 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21437500 21422 1c001ae8 0104aa03 lw x20, 16(x9) x20=100ff708 x9:100ff6f4 PA:100ff704 + 21439500 21424 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000036 x20=100ff709 x20:100ff708 PA:100ff708 + 21441500 21426 1c001af0 06059763 bne x11, x0, 110 x11:00000036 + 21444500 21429 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21445500 21430 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21447500 21432 1c001776 00b00533 add x10, x0, x11 x10=00000036 x11:00000036 + 21448500 21433 1c001778 fddff06f jal x0, -36 + 21450500 21435 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21451500 21436 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 21452500 21437 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21453500 21438 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 21454500 21439 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 21455500 21440 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 21456500 21441 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 21457500 21442 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 21458500 21443 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21459500 21444 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000036 x14:1a104000 PA:1a104030 + 21463500 21448 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21464500 21449 1c001b62 f8bff06f jal x0, -118 + 21466500 21451 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100ff70a x20:100ff709 PA:100ff709 + 21468500 21453 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21469500 21454 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ff6f4 PA:100ff6f4 + 21471500 21456 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21472500 21457 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21475500 21460 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100ff6d0 PA:100ff6ec + 21476500 21461 1c001b02 01812403 lw x8, 24(x2) x8=100ff778 x2:100ff6d0 PA:100ff6e8 + 21477500 21462 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100ff6d0 PA:100ff6e4 + 21478500 21463 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100ff6d0 PA:100ff6e0 + 21479500 21464 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100ff6d0 PA:100ff6dc + 21480500 21465 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100ff6d0 PA:100ff6d8 + 21481500 21466 1c001b0c 02010113 addi x2, x2, 32 x2=100ff6f0 x2:100ff6d0 + 21482500 21467 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21484500 21469 1c001d86 01800433 add x8, x0, x24 x8=100ff77c x24:100ff77c + 21485500 21470 1c001d88 fadff06f jal x0, -84 + 21487500 21472 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21488500 21473 1c001d36 e69ff06f jal x0, -408 + 21491500 21476 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21510500 21495 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21511500 21496 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21514500 21499 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21515500 21500 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21516500 21501 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21518500 21503 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21519500 21504 1c001778 fddff06f jal x0, -36 + 21521500 21506 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21522500 21507 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 21523500 21508 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21524500 21509 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 21525500 21510 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 21526500 21511 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 21527500 21512 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 21528500 21513 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 21529500 21514 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21530500 21515 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104030 + 21534500 21519 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21535500 21520 1c001bca 16a0006f jal x0, 362 + 21537500 21522 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21538500 21523 1c001d36 e69ff06f jal x0, -408 + 21541500 21526 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21556500 21541 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21557500 21542 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21560500 21545 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21561500 21546 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21562500 21547 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21564500 21549 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21565500 21550 1c001778 fddff06f jal x0, -36 + 21567500 21552 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21568500 21553 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 21569500 21554 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21570500 21555 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 21571500 21556 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 21572500 21557 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 21573500 21558 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 21574500 21559 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 21575500 21560 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21576500 21561 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104030 + 21580500 21565 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21581500 21566 1c001bca 16a0006f jal x0, 362 + 21583500 21568 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21584500 21569 1c001d36 e69ff06f jal x0, -408 + 21587500 21572 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21602500 21587 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21603500 21588 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21606500 21591 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21607500 21592 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21608500 21593 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21610500 21595 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21611500 21596 1c001778 fddff06f jal x0, -36 + 21613500 21598 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21614500 21599 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000006 + 21615500 21600 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21616500 21601 1c00175e 00379713 slli x14, x15, 0x3 x14=00000030 x15:00000006 + 21617500 21602 1c001762 00279793 slli x15, x15, 0x2 x15=00000018 x15:00000006 + 21618500 21603 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000030 + 21619500 21604 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:00000018 x13:00001f80 + 21620500 21605 1c00176a 00e787b3 add x15, x15, x14 x15=00000030 x15:00000000 x14:00000030 + 21621500 21606 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21622500 21607 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104030 + 21626500 21611 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21627500 21612 1c001bca 16a0006f jal x0, 362 + 21629500 21614 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21630500 21615 1c001d36 e69ff06f jal x0, -408 + 21633500 21618 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21648500 21633 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21649500 21634 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21650500 21635 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100ff6f0 PA:100ff74c + 21651500 21636 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100ff6f0 PA:100ff748 + 21652500 21637 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:100ff6f0 PA:100ff744 + 21653500 21638 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:100ff6f0 PA:100ff740 + 21654500 21639 1c001bb0 04c12983 lw x19, 76(x2) x19=00000006 x2:100ff6f0 PA:100ff73c + 21655500 21640 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:100ff6f0 PA:100ff738 + 21656500 21641 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:100ff6f0 PA:100ff734 + 21657500 21642 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100ff6f0 PA:100ff730 + 21658500 21643 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100ff6f0 PA:100ff72c + 21662500 21647 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100ff6f0 PA:100ff728 + 21663500 21648 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100ff6f0 PA:100ff724 + 21664500 21649 1c001bbe 06010113 addi x2, x2, 96 x2=100ff750 x2:100ff6f0 + 21665500 21650 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21667500 21652 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:100ff750 PA:100ff76c + 21668500 21653 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21669500 21654 1c001838 04010113 addi x2, x2, 64 x2=100ff790 x2:100ff750 + 21670500 21655 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21676500 21661 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_00_7.log b/sw/scripts/tracevis/example/traces/trace_core_00_7.log new file mode 100644 index 0000000..83e8ab7 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_00_7.log @@ -0,0 +1,847 @@ + Time Cycles PC Instr Mnemonic + 113500 98 1c000080 0180006f jal x0, 24 + 137500 122 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000007 + 138500 123 1c00009c 01f57593 andi x11, x10, 31 x11=00000007 x10:00000007 + 161500 146 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000000 x10:00000007 + 162500 147 1c0000a2 00058463 beq x11, x0, 8 x11:00000007 + 163500 148 1c0000a6 05a0206f jal x0, 8282 + 184500 169 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 185500 170 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 186500 171 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 187500 172 1c00210c 0e059163 bne x11, x0, 226 x11:00000007 + 256500 241 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 257500 242 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000007 + 258500 243 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000007 x19:00000007 + 259500 244 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 280500 265 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 281500 266 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 282500 267 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 283500 268 1c00220a 0060006f jal x0, 6 + 300500 285 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 9629500 9614 1c002214 08096503 p.elw x10, 128(x18) x10=00000800 x18:1b204000 PA:1b204080 + 9637500 9622 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 9638500 9623 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 9656500 9641 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 9657500 9642 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 9659500 9644 1c00222c 08096283 p.elw x5, 128(x18) x5=100fc790 x18:1b204000 PA:1b204080 + 9683500 9668 1c002230 02a98533 mul x10, x19, x10 x10=00003800 x19:00000007 x10:00000800 + 9684500 9669 1c002234 00550133 add x2, x10, x5 x2=100fff90 x10:00003800 x5:100fc790 + 9685500 9670 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 9705500 9690 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18829500 18814 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18837500 18822 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18838500 18823 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18839500 18824 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18840500 18825 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18863500 18848 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000007 + 18883500 18868 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18884500 18869 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000000 x12:00000007 + 18885500 18870 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000000 x11:00000000 + 18886500 18871 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000007 x12:00000007 + 18887500 18872 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18888500 18873 1c0009d4 63d0006f jal x0, 3644 + 18890500 18875 1c001810 fc010113 addi x2, x2, -64 x2=100fff50 x2:100fff90 + 18891500 18876 1c001812 02b12223 sw x11, 36(x2) x11:00000000 x2:100fff50 PA:100fff74 + 18894500 18879 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18895500 18880 1c001818 02c12423 sw x12, 40(x2) x12:00000007 x2:100fff50 PA:100fff78 + 18896500 18881 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:100fff50 PA:100fff7c + 18897500 18882 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18898500 18883 1c00181e 02410693 addi x13, x2, 36 x13=100fff74 x2:100fff50 + 18912500 18897 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18913500 18898 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18914500 18899 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:100fff50 PA:100fff6c + 18920500 18905 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:100fff50 PA:100fff80 + 18921500 18906 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:100fff50 PA:100fff84 + 18922500 18907 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:100fff50 PA:100fff88 + 18923500 18908 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:100fff50 PA:100fff8c + 18936500 18921 1c001830 00d12623 sw x13, 12(x2) x13:100fff74 x2:100fff50 PA:100fff5c + 18943500 18928 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18955500 18940 1c001b70 fa010113 addi x2, x2, -96 x2=100ffef0 x2:100fff50 + 18956500 18941 1c001b72 01810793 addi x15, x2, 24 x15=100fff08 x2:100ffef0 + 18957500 18942 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:100ffef0 PA:100fff48 + 18958500 18943 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:100ffef0 PA:100fff40 + 18959500 18944 1c001b78 05312623 sw x19, 76(x2) x19:00000007 x2:100ffef0 PA:100fff3c + 18960500 18945 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:100ffef0 PA:100fff38 + 18961500 18946 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:100ffef0 PA:100fff34 + 18962500 18947 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:100ffef0 PA:100fff30 + 18982500 18967 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:100ffef0 PA:100fff2c + 18984500 18969 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:100ffef0 PA:100fff4c + 18985500 18970 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:100ffef0 PA:100fff44 + 18986500 18971 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:100ffef0 PA:100fff28 + 18987500 18972 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:100ffef0 PA:100fff24 + 18988500 18973 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18989500 18974 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18990500 18975 1c001b8e 00d00433 add x8, x0, x13 x8=100fff74 x13:100fff74 + 19012500 18997 1c001b90 00f12a23 sw x15, 20(x2) x15:100fff08 x2:100ffef0 PA:100fff04 + 19019500 19004 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19020500 19005 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19021500 19006 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19022500 19007 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19036500 19021 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19065500 19050 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19066500 19051 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19078500 19063 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19079500 19064 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19080500 19065 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19098500 19083 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19099500 19084 1c001778 fddff06f jal x0, -36 + 19101500 19086 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19102500 19087 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19103500 19088 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19121500 19106 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19122500 19107 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19123500 19108 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19124500 19109 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19125500 19110 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19126500 19111 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19127500 19112 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104038 + 19131500 19116 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19132500 19117 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19195500 19180 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19196500 19181 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19199500 19184 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19200500 19185 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19201500 19186 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19203500 19188 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19204500 19189 1c001778 fddff06f jal x0, -36 + 19206500 19191 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19207500 19192 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19208500 19193 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19209500 19194 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19210500 19195 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19211500 19196 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19212500 19197 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19213500 19198 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19214500 19199 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19215500 19200 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104038 + 19219500 19204 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19220500 19205 1c001bca 16a0006f jal x0, 362 + 19222500 19207 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19223500 19208 1c001d36 e69ff06f jal x0, -408 + 19226500 19211 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19245500 19230 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19246500 19231 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19249500 19234 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19250500 19235 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19251500 19236 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19253500 19238 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19254500 19239 1c001778 fddff06f jal x0, -36 + 19256500 19241 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19257500 19242 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19258500 19243 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19259500 19244 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19260500 19245 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19261500 19246 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19262500 19247 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19263500 19248 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19264500 19249 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19265500 19250 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104038 + 19269500 19254 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19270500 19255 1c001bca 16a0006f jal x0, 362 + 19272500 19257 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19273500 19258 1c001d36 e69ff06f jal x0, -408 + 19276500 19261 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19292500 19277 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19293500 19278 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19296500 19281 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19297500 19282 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19298500 19283 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19300500 19285 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19301500 19286 1c001778 fddff06f jal x0, -36 + 19303500 19288 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19304500 19289 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19305500 19290 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19306500 19291 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19307500 19292 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19308500 19293 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19309500 19294 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19310500 19295 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19311500 19296 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19312500 19297 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104038 + 19316500 19301 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19317500 19302 1c001bca 16a0006f jal x0, 362 + 19319500 19304 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19320500 19305 1c001d36 e69ff06f jal x0, -408 + 19323500 19308 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19340500 19325 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19341500 19326 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19344500 19329 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19345500 19330 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19346500 19331 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19348500 19333 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19349500 19334 1c001778 fddff06f jal x0, -36 + 19351500 19336 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19352500 19337 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19353500 19338 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19354500 19339 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19355500 19340 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19356500 19341 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19357500 19342 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19358500 19343 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19359500 19344 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19360500 19345 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104038 + 19364500 19349 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19365500 19350 1c001bca 16a0006f jal x0, 362 + 19367500 19352 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19368500 19353 1c001d36 e69ff06f jal x0, -408 + 19371500 19356 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19392500 19377 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19393500 19378 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19396500 19381 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19397500 19382 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19398500 19383 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19400500 19385 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19401500 19386 1c001778 fddff06f jal x0, -36 + 19403500 19388 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19404500 19389 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19405500 19390 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19406500 19391 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19407500 19392 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19408500 19393 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19409500 19394 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19410500 19395 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19411500 19396 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19412500 19397 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104038 + 19416500 19401 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19417500 19402 1c001bca 16a0006f jal x0, 362 + 19419500 19404 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19420500 19405 1c001d36 e69ff06f jal x0, -408 + 19423500 19408 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19442500 19427 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19443500 19428 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19446500 19431 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19447500 19432 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19448500 19433 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19450500 19435 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19451500 19436 1c001778 fddff06f jal x0, -36 + 19453500 19438 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19454500 19439 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19455500 19440 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19456500 19441 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19457500 19442 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19458500 19443 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19459500 19444 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19460500 19445 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19461500 19446 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19462500 19447 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104038 + 19466500 19451 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19467500 19452 1c001bca 16a0006f jal x0, 362 + 19469500 19454 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19470500 19455 1c001d36 e69ff06f jal x0, -408 + 19473500 19458 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19494500 19479 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19495500 19480 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19498500 19483 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19499500 19484 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19500500 19485 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19502500 19487 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19503500 19488 1c001778 fddff06f jal x0, -36 + 19505500 19490 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19506500 19491 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19507500 19492 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19508500 19493 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19509500 19494 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19510500 19495 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19511500 19496 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19512500 19497 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19513500 19498 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19514500 19499 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104038 + 19518500 19503 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19519500 19504 1c001bca 16a0006f jal x0, 362 + 19521500 19506 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19522500 19507 1c001d36 e69ff06f jal x0, -408 + 19525500 19510 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19541500 19526 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19542500 19527 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19545500 19530 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19546500 19531 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19547500 19532 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19549500 19534 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19550500 19535 1c001778 fddff06f jal x0, -36 + 19552500 19537 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19553500 19538 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19554500 19539 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19555500 19540 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19556500 19541 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19557500 19542 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19558500 19543 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19559500 19544 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19560500 19545 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19561500 19546 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104038 + 19565500 19550 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19566500 19551 1c001bca 16a0006f jal x0, 362 + 19568500 19553 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19569500 19554 1c001d36 e69ff06f jal x0, -408 + 19572500 19557 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19597500 19582 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19598500 19583 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19601500 19586 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19602500 19587 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19603500 19588 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19605500 19590 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19606500 19591 1c001778 fddff06f jal x0, -36 + 19608500 19593 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19609500 19594 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19610500 19595 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19611500 19596 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19612500 19597 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19613500 19598 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19614500 19599 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19615500 19600 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19616500 19601 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19617500 19602 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104038 + 19621500 19606 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19622500 19607 1c001bca 16a0006f jal x0, 362 + 19624500 19609 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19625500 19610 1c001d36 e69ff06f jal x0, -408 + 19628500 19613 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19644500 19629 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19645500 19630 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19648500 19633 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19649500 19634 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19650500 19635 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19652500 19637 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19653500 19638 1c001778 fddff06f jal x0, -36 + 19655500 19640 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19656500 19641 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19657500 19642 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19658500 19643 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19659500 19644 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19660500 19645 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19661500 19646 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19662500 19647 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19663500 19648 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19664500 19649 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104038 + 19668500 19653 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19669500 19654 1c001bca 16a0006f jal x0, 362 + 19671500 19656 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19672500 19657 1c001d36 e69ff06f jal x0, -408 + 19675500 19660 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19689500 19674 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19690500 19675 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19693500 19678 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19694500 19679 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19695500 19680 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19697500 19682 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19698500 19683 1c001778 fddff06f jal x0, -36 + 19700500 19685 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19701500 19686 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19702500 19687 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19703500 19688 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19704500 19689 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19705500 19690 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19706500 19691 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19707500 19692 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19708500 19693 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19709500 19694 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104038 + 19713500 19698 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19714500 19699 1c001bca 16a0006f jal x0, 362 + 19716500 19701 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19717500 19702 1c001d36 e69ff06f jal x0, -408 + 19720500 19705 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19735500 19720 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19736500 19721 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19739500 19724 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19740500 19725 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19741500 19726 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19743500 19728 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19744500 19729 1c001778 fddff06f jal x0, -36 + 19746500 19731 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19747500 19732 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19748500 19733 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19749500 19734 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19750500 19735 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19751500 19736 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19752500 19737 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19753500 19738 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19754500 19739 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19755500 19740 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104038 + 19759500 19744 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19760500 19745 1c001bca 16a0006f jal x0, 362 + 19762500 19747 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19763500 19748 1c001d36 e69ff06f jal x0, -408 + 19766500 19751 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19781500 19766 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19782500 19767 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19785500 19770 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19786500 19771 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19787500 19772 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19789500 19774 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19790500 19775 1c001778 fddff06f jal x0, -36 + 19792500 19777 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19793500 19778 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19794500 19779 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19795500 19780 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19796500 19781 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19797500 19782 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19798500 19783 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19799500 19784 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19800500 19785 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19801500 19786 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104038 + 19805500 19790 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19806500 19791 1c001bca 16a0006f jal x0, 362 + 19808500 19793 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19809500 19794 1c001d36 e69ff06f jal x0, -408 + 19812500 19797 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19826500 19811 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19827500 19812 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19830500 19815 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19831500 19816 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19832500 19817 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19834500 19819 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19835500 19820 1c001778 fddff06f jal x0, -36 + 19837500 19822 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19838500 19823 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 19839500 19824 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19840500 19825 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 19841500 19826 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 19842500 19827 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 19843500 19828 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 19844500 19829 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 19845500 19830 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19846500 19831 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104038 + 19850500 19835 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19851500 19836 1c001bca 16a0006f jal x0, 362 + 19853500 19838 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19854500 19839 1c001d36 e69ff06f jal x0, -408 + 19857500 19842 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19875500 19860 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19876500 19861 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19879500 19864 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19882500 19867 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:100ffef0 PA:100ffef4 + 19883500 19868 1c001bd0 00012423 sw x0, 8(x2) x2:100ffef0 PA:100ffef8 + 19884500 19869 1c001bd2 00010623 sb x0, 12(x2) x2:100ffef0 PA:100ffefc + 19885500 19870 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19886500 19871 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19896500 19881 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19897500 19882 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100ffef0 PA:100ffef4 + 19902500 19887 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19903500 19888 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19904500 19889 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19905500 19890 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19906500 19891 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19919500 19904 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19920500 19905 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19921500 19906 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19958500 19943 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19959500 19944 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19971500 19956 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19972500 19957 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19973500 19958 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19993500 19978 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20012500 19997 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20015500 20000 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20033500 20018 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20050500 20035 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20051500 20036 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20052500 20037 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20072500 20057 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20090500 20075 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20109500 20094 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20110500 20095 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20149500 20134 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20167500 20152 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20191500 20176 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20192500 20177 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20229500 20214 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20246500 20231 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20247500 20232 1c001f42 e09ff06f jal x0, -504 + 20265500 20250 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20266500 20251 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100ffef0 PA:100fff00 + 20288500 20273 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20307500 20292 1c001e34 00440c13 addi x24, x8, 4 x24=100fff78 x8:100fff74 + 20308500 20293 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:100fff74 PA:100fff74 + 20310500 20295 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20345500 20330 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20364500 20349 1c001e64 00410593 addi x11, x2, 4 x11=100ffef4 x2:100ffef0 + 20365500 20350 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20385500 20370 1c0019fe 0105a683 lw x13, 16(x11) x13=100fff08 x11:100ffef4 PA:100fff04 + 20402500 20387 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ffef4 PA:100fff00 + 20406500 20391 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20407500 20392 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20441500 20426 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20442500 20427 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20443500 20428 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20444500 20429 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20447500 20432 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ffef4 PA:100fff00 + 20461500 20446 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20495500 20480 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20529500 20514 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20560500 20545 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20561500 20546 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20562500 20547 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20563500 20548 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20564500 20549 1c001a38 01e0006f jal x0, 30 + 20582500 20567 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20583500 20568 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:100fff08 PA:100fff08 + 20589500 20574 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20590500 20575 1c001a5e 00168693 addi x13, x13, 1 x13=100fff09 x13:100fff08 + 20601500 20586 1c001a60 fb1ff06f jal x0, -80 + 20603500 20588 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20604500 20589 1c001a12 00068023 sb x0, 0(x13) x13:100fff09 PA:100fff09 + 20611500 20596 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20612500 20597 1c001e68 f17ff06f jal x0, -234 + 20625500 20610 1c001d7e 00410613 addi x12, x2, 4 x12=100ffef4 x2:100ffef0 + 20642500 20627 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20643500 20628 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20644500 20629 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20646500 20631 1c001a62 fe010113 addi x2, x2, -32 x2=100ffed0 x2:100ffef0 + 20647500 20632 1c001a64 00812c23 sw x8, 24(x2) x8:100fff74 x2:100ffed0 PA:100ffee8 + 20652500 20637 1c001a66 01062783 lw x15, 16(x12) x15=100fff08 x12:100ffef4 PA:100fff04 + 20653500 20638 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100ffef4 PA:100ffef8 + 20654500 20639 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:100ffed0 PA:100ffee4 + 20655500 20640 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100ffed0 PA:100ffee0 + 20656500 20641 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100ffed0 PA:100ffedc + 20673500 20658 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100ffed0 PA:100ffeec + 20677500 20662 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100ffed0 PA:100ffed8 + 20678500 20663 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20679500 20664 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20680500 20665 1c001a78 00c004b3 add x9, x0, x12 x9=100ffef4 x12:100ffef4 + 20681500 20666 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=100fff09 x15:100fff08 PA:100fff08 + 20683500 20668 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20696500 20681 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20697500 20682 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100ffef4 PA:100ffefc + 20700500 20685 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20703500 20688 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 20720500 20705 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20721500 20706 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20740500 20725 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20741500 20726 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20742500 20727 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20764500 20749 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20765500 20750 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20788500 20773 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20789500 20774 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20790500 20775 1c001b36 f71ff06f jal x0, -144 + 20792500 20777 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100ffef4 PA:100ffefc + 20798500 20783 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20813500 20798 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 20815500 20800 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20816500 20801 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20835500 20820 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 20852500 20837 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20853500 20838 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20854500 20839 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20855500 20840 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fff08 x9:100ffef4 PA:100fff04 + 20860500 20845 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=100fff09 x20:100fff08 PA:100fff08 + 20873500 20858 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20893500 20878 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20910500 20895 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20912500 20897 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20913500 20898 1c001778 fddff06f jal x0, -36 + 20915500 20900 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20916500 20901 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 20917500 20902 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20918500 20903 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 20919500 20904 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 20920500 20905 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 20921500 20906 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 20922500 20907 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 20923500 20908 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20924500 20909 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104038 + 20928500 20913 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20929500 20914 1c001b62 f8bff06f jal x0, -118 + 20931500 20916 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fff0a x20:100fff09 PA:100fff09 + 20937500 20922 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20938500 20923 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 20940500 20925 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20941500 20926 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20957500 20942 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100ffed0 PA:100ffeec + 20958500 20943 1c001b02 01812403 lw x8, 24(x2) x8=100fff74 x2:100ffed0 PA:100ffee8 + 20959500 20944 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:100ffed0 PA:100ffee4 + 20960500 20945 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100ffed0 PA:100ffee0 + 20961500 20946 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100ffed0 PA:100ffedc + 20962500 20947 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100ffed0 PA:100ffed8 + 20963500 20948 1c001b0c 02010113 addi x2, x2, 32 x2=100ffef0 x2:100ffed0 + 20964500 20949 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20981500 20966 1c001d86 01800433 add x8, x0, x24 x8=100fff78 x24:100fff78 + 20982500 20967 1c001d88 fadff06f jal x0, -84 + 20984500 20969 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20985500 20970 1c001d36 e69ff06f jal x0, -408 + 20988500 20973 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21016500 21001 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21017500 21002 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21020500 21005 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21021500 21006 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21022500 21007 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21024500 21009 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21025500 21010 1c001778 fddff06f jal x0, -36 + 21027500 21012 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21028500 21013 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 21029500 21014 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21030500 21015 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 21031500 21016 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 21032500 21017 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 21033500 21018 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 21034500 21019 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 21035500 21020 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21036500 21021 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104038 + 21040500 21025 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21041500 21026 1c001bca 16a0006f jal x0, 362 + 21043500 21028 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21044500 21029 1c001d36 e69ff06f jal x0, -408 + 21047500 21032 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21064500 21049 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21065500 21050 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21068500 21053 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21069500 21054 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21070500 21055 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21072500 21057 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21073500 21058 1c001778 fddff06f jal x0, -36 + 21075500 21060 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21076500 21061 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 21077500 21062 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21078500 21063 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 21079500 21064 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 21080500 21065 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 21081500 21066 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 21082500 21067 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 21083500 21068 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21084500 21069 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104038 + 21088500 21073 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21089500 21074 1c001bca 16a0006f jal x0, 362 + 21091500 21076 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21092500 21077 1c001d36 e69ff06f jal x0, -408 + 21095500 21080 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21110500 21095 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21111500 21096 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21114500 21099 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21117500 21102 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:100ffef0 PA:100ffef4 + 21120500 21105 1c001bd0 00012423 sw x0, 8(x2) x2:100ffef0 PA:100ffef8 + 21121500 21106 1c001bd2 00010623 sb x0, 12(x2) x2:100ffef0 PA:100ffefc + 21122500 21107 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21123500 21108 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21124500 21109 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21125500 21110 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:100ffef0 PA:100ffef4 + 21126500 21111 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21127500 21112 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21128500 21113 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21129500 21114 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21130500 21115 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21131500 21116 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21132500 21117 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21133500 21118 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21155500 21140 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21156500 21141 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21159500 21144 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21160500 21145 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21161500 21146 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21164500 21149 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21167500 21152 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21170500 21155 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21173500 21158 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21174500 21159 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21175500 21160 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21176500 21161 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21179500 21164 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21180500 21165 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21183500 21168 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21184500 21169 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21187500 21172 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21189500 21174 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21192500 21177 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21193500 21178 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21196500 21181 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21197500 21182 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21198500 21183 1c001f42 e09ff06f jal x0, -504 + 21200500 21185 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21201500 21186 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:100ffef0 PA:100fff00 + 21202500 21187 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21205500 21190 1c001e34 00440c13 addi x24, x8, 4 x24=100fff7c x8:100fff78 + 21206500 21191 1c001e38 00042503 lw x10, 0(x8) x10=00000007 x8:100fff78 PA:100fff78 + 21207500 21192 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21210500 21195 1c001e54 00055863 bge x10, x0, 16 x10:00000007 + 21213500 21198 1c001e64 00410593 addi x11, x2, 4 x11=100ffef4 x2:100ffef0 + 21214500 21199 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21216500 21201 1c0019fe 0105a683 lw x13, 16(x11) x13=100fff08 x11:100ffef4 PA:100fff04 + 21217500 21202 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ffef4 PA:100fff00 + 21218500 21203 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21219500 21204 1c001a04 02f55633 divu x12, x10, x15 x12=00000007 x10:00000007 x15:00000001 + 21253500 21238 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000007 x14:0000000a + 21254500 21239 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21255500 21240 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21256500 21241 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21259500 21244 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:100ffef4 PA:100fff00 + 21260500 21245 1c001a20 02f55833 divu x16, x10, x15 x16=00000007 x10:00000007 x15:00000001 + 21294500 21279 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000007 x15:00000001 + 21328500 21313 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21359500 21344 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21360500 21345 1c001a2e 01004663 blt x0, x16, 12 x16:00000007 + 21363500 21348 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21365500 21350 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000007 + 21368500 21353 1c001a56 01070733 add x14, x14, x16 x14=00000037 x14:00000030 x16:00000007 + 21369500 21354 1c001a58 00e68023 sb x14, 0(x13) x14:00000037 x13:100fff08 PA:100fff08 + 21370500 21355 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21371500 21356 1c001a5e 00168693 addi x13, x13, 1 x13=100fff09 x13:100fff08 + 21372500 21357 1c001a60 fb1ff06f jal x0, -80 + 21374500 21359 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21375500 21360 1c001a12 00068023 sb x0, 0(x13) x13:100fff09 PA:100fff09 + 21376500 21361 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21378500 21363 1c001e68 f17ff06f jal x0, -234 + 21380500 21365 1c001d7e 00410613 addi x12, x2, 4 x12=100ffef4 x2:100ffef0 + 21381500 21366 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21382500 21367 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21383500 21368 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21385500 21370 1c001a62 fe010113 addi x2, x2, -32 x2=100ffed0 x2:100ffef0 + 21386500 21371 1c001a64 00812c23 sw x8, 24(x2) x8:100fff78 x2:100ffed0 PA:100ffee8 + 21387500 21372 1c001a66 01062783 lw x15, 16(x12) x15=100fff08 x12:100ffef4 PA:100fff04 + 21388500 21373 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:100ffef4 PA:100ffef8 + 21389500 21374 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:100ffed0 PA:100ffee4 + 21390500 21375 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:100ffed0 PA:100ffee0 + 21391500 21376 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:100ffed0 PA:100ffedc + 21392500 21377 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:100ffed0 PA:100ffeec + 21393500 21378 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:100ffed0 PA:100ffed8 + 21394500 21379 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21395500 21380 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21396500 21381 1c001a78 00c004b3 add x9, x0, x12 x9=100ffef4 x12:100ffef4 + 21397500 21382 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000037 x15=100fff09 x15:100fff08 PA:100fff08 + 21399500 21384 1c001a7e 00070363 beq x14, x0, 6 x14:00000037 + 21400500 21385 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21401500 21386 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:100ffef4 PA:100ffefc + 21403500 21388 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21406500 21391 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 21408500 21393 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21409500 21394 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21412500 21397 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21413500 21398 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21414500 21399 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21417500 21402 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21418500 21403 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21419500 21404 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21420500 21405 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21421500 21406 1c001b36 f71ff06f jal x0, -144 + 21423500 21408 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:100ffef4 PA:100ffefc + 21425500 21410 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21428500 21413 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 21430500 21415 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21431500 21416 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21434500 21419 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 21435500 21420 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21436500 21421 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21437500 21422 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21438500 21423 1c001ae8 0104aa03 lw x20, 16(x9) x20=100fff08 x9:100ffef4 PA:100fff04 + 21440500 21425 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000037 x20=100fff09 x20:100fff08 PA:100fff08 + 21442500 21427 1c001af0 06059763 bne x11, x0, 110 x11:00000037 + 21445500 21430 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21446500 21431 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21448500 21433 1c001776 00b00533 add x10, x0, x11 x10=00000037 x11:00000037 + 21449500 21434 1c001778 fddff06f jal x0, -36 + 21451500 21436 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21452500 21437 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 21453500 21438 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21454500 21439 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 21455500 21440 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 21456500 21441 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 21457500 21442 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 21458500 21443 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 21459500 21444 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21460500 21445 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000037 x14:1a104000 PA:1a104038 + 21464500 21449 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21465500 21450 1c001b62 f8bff06f jal x0, -118 + 21467500 21452 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=100fff0a x20:100fff09 PA:100fff09 + 21469500 21454 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21470500 21455 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:100ffef4 PA:100ffef4 + 21472500 21457 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21473500 21458 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21476500 21461 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:100ffed0 PA:100ffeec + 21477500 21462 1c001b02 01812403 lw x8, 24(x2) x8=100fff78 x2:100ffed0 PA:100ffee8 + 21478500 21463 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:100ffed0 PA:100ffee4 + 21479500 21464 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:100ffed0 PA:100ffee0 + 21480500 21465 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:100ffed0 PA:100ffedc + 21481500 21466 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:100ffed0 PA:100ffed8 + 21482500 21467 1c001b0c 02010113 addi x2, x2, 32 x2=100ffef0 x2:100ffed0 + 21483500 21468 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21485500 21470 1c001d86 01800433 add x8, x0, x24 x8=100fff7c x24:100fff7c + 21486500 21471 1c001d88 fadff06f jal x0, -84 + 21488500 21473 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21489500 21474 1c001d36 e69ff06f jal x0, -408 + 21492500 21477 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21511500 21496 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21512500 21497 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21515500 21500 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21516500 21501 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21517500 21502 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21519500 21504 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21520500 21505 1c001778 fddff06f jal x0, -36 + 21522500 21507 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21523500 21508 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 21524500 21509 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21525500 21510 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 21526500 21511 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 21527500 21512 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 21528500 21513 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 21529500 21514 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 21530500 21515 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21531500 21516 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104038 + 21535500 21520 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21536500 21521 1c001bca 16a0006f jal x0, 362 + 21538500 21523 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21539500 21524 1c001d36 e69ff06f jal x0, -408 + 21542500 21527 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21557500 21542 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21558500 21543 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21561500 21546 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21562500 21547 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21563500 21548 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21565500 21550 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21566500 21551 1c001778 fddff06f jal x0, -36 + 21568500 21553 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21569500 21554 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 21570500 21555 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21571500 21556 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 21572500 21557 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 21573500 21558 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 21574500 21559 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 21575500 21560 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 21576500 21561 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21577500 21562 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104038 + 21581500 21566 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21582500 21567 1c001bca 16a0006f jal x0, 362 + 21584500 21569 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21585500 21570 1c001d36 e69ff06f jal x0, -408 + 21588500 21573 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21603500 21588 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21604500 21589 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21607500 21592 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21608500 21593 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21609500 21594 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21611500 21596 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21612500 21597 1c001778 fddff06f jal x0, -36 + 21614500 21599 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21615500 21600 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000007 + 21616500 21601 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21617500 21602 1c00175e 00379713 slli x14, x15, 0x3 x14=00000038 x15:00000007 + 21618500 21603 1c001762 00279793 slli x15, x15, 0x2 x15=0000001c x15:00000007 + 21619500 21604 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000038 + 21620500 21605 1c001768 00d7f7b3 and x15, x15, x13 x15=00000000 x15:0000001c x13:00001f80 + 21621500 21606 1c00176a 00e787b3 add x15, x15, x14 x15=00000038 x15:00000000 x14:00000038 + 21622500 21607 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21623500 21608 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104038 + 21627500 21612 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21628500 21613 1c001bca 16a0006f jal x0, 362 + 21630500 21615 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21631500 21616 1c001d36 e69ff06f jal x0, -408 + 21634500 21619 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21649500 21634 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21650500 21635 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21651500 21636 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:100ffef0 PA:100fff4c + 21652500 21637 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:100ffef0 PA:100fff48 + 21653500 21638 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:100ffef0 PA:100fff44 + 21654500 21639 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:100ffef0 PA:100fff40 + 21655500 21640 1c001bb0 04c12983 lw x19, 76(x2) x19=00000007 x2:100ffef0 PA:100fff3c + 21656500 21641 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:100ffef0 PA:100fff38 + 21657500 21642 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:100ffef0 PA:100fff34 + 21658500 21643 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:100ffef0 PA:100fff30 + 21659500 21644 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:100ffef0 PA:100fff2c + 21660500 21645 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:100ffef0 PA:100fff28 + 21661500 21646 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:100ffef0 PA:100fff24 + 21662500 21647 1c001bbe 06010113 addi x2, x2, 96 x2=100fff50 x2:100ffef0 + 21663500 21648 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21665500 21650 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:100fff50 PA:100fff6c + 21666500 21651 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21667500 21652 1c001838 04010113 addi x2, x2, 64 x2=100fff90 x2:100fff50 + 21668500 21653 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21676500 21661 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_0.log b/sw/scripts/tracevis/example/traces/trace_core_01_0.log new file mode 100644 index 0000000..155f3c9 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_0.log @@ -0,0 +1,921 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000020 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000000 x10:00000020 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000020 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000000 + 12643500 12628 1c0000aa 00050463 beq x10, x0, 8 x10:00000001 + 12662500 12647 1c0000ae 0520206f jal x0, 8274 + 12664500 12649 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12665500 12650 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12666500 12651 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12667500 12652 1c00210c 0e059163 bne x11, x0, 226 x11:00000000 + 12679500 12664 1c002110 feffe417 auipc x8, 0xfeffe000 x8=1b000110 + 12680500 12665 1c002114 ef840413 addi x8, x8, -264 x8=1b000008 x8:1b000110 + 12681500 12666 1c002118 04040493 addi x9, x8, 64 x9=1b000048 x8:1b000008 + 12682500 12667 1c00211c 00800933 add x18, x0, x8 x18=1b000008 x8:1b000008 + 12699500 12684 1c00211e 1b2049b7 lui x19, 0x1b204000 x19=1b204000 + 12700500 12685 1c002122 00200a13 addi x20, x0, 2 x20=00000002 + 12701500 12686 1c002124 00000a97 auipc x21, 0x0 x21=1c002124 + 12702500 12687 1c002128 036a8a93 addi x21, x21, 54 x21=1c00215a x21:1c002124 + 12703500 12688 1c00212c 00000b97 auipc x23, 0x0 x23=1c00212c + 12720500 12705 1c002130 57cb8b93 addi x23, x23, 1404 x23=1c0026a8 x23:1c00212c + 12721500 12706 1c002134 000bab83 lw x23, 0(x23) x23=1c2fff50 x23:1c0026a8 PA:1c0026a8 + 12736500 12721 1c002138 01800393 addi x7, x0, 24 x7=00000018 + 12737500 12722 1c00213a 02a383b3 mul x7, x7, x10 x7=00000018 x7:00000018 x10:00000001 + 12738500 12723 1c00213e 007b8bb3 add x23, x23, x7 x23=1c2fff68 x23:1c2fff50 x7:00000018 + 12759500 12744 1c002140 008b8b93 addi x23, x23, 8 x23=1c2fff70 x23:1c2fff68 + 12760500 12745 1c002142 10201cb7 lui x25, 0x10201000 x25=10201000 + 12761500 12746 1c002146 e04c8c93 addi x25, x25, -508 x25=10200e04 x25:10201000 + 12762500 12747 1c00214a 00100c13 addi x24, x0, 1 x24=00000001 + 12763500 12748 1c00214c 00000d17 auipc x26, 0x0 x26=1c00214c + 12780500 12765 1c002150 0e0d0d13 addi x26, x26, 224 x26=1c00222c x26:1c00214c + 12781500 12766 1c002154 001d6d13 ori x26, x26, 1 x26=1c00222d x26:1c00222c + 12782500 12767 1c002158 0160006f jal x0, 22 + 12817500 12802 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000008 PA:1b000008 + 12819500 12804 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 12838500 12823 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 + 12839500 12824 1c0021d6 03c9e003 p.elw x0, 60(x19) x19:1b204000 PA:1b20403c + 17709500 17694 1c0021da 0149a223 sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004 + 17710500 17695 1c0021de f91ff06f jal x0, -112 + 17713500 17698 1c00216e 00042e03 lw x28, 0(x8) x28=00000008 x8:1b000008 PA:1b000008 + 17715500 17700 1c002172 060e0063 beq x28, x0, 96 x28:00000008 + 17716500 17701 1c002176 00842503 lw x10, 8(x8) x10=00000000 x8:1b000008 PA:1b000010 + 17717500 17702 1c002178 00442283 lw x5, 4(x8) x5=1c0009d8 x8:1b000008 PA:1b00000c + 17718500 17703 1c00217c 00c42103 lw x2, 12(x8) x2=104fe400 x8:1b000008 PA:1b000014 + 17735500 17720 1c002180 01042303 lw x6, 16(x8) x6=00000400 x8:1b000008 PA:1b000018 + 17736500 17721 1c002184 01442383 lw x7, 20(x8) x7=00000400 x8:1b000008 PA:1b00001c + 17737500 17722 1c002188 01842b03 lw x22, 24(x8) x22=100fc720 x8:1b000008 PA:1b000020 + 17738500 17723 1c00218c 01c42e83 lw x29, 28(x8) x29=1000013c x8:1b000008 PA:1b000024 + 17755500 17740 1c002190 00042023 sw x0, 0(x8) x8:1b000008 PA:1b000008 + 17756500 17741 1c002194 feffef17 auipc x30, 0xfeffe000 x30=1b000194 + 17757500 17742 1c002198 eb4f0f13 addi x30, x30, -332 x30=1b000048 x30:1b000194 + 17758500 17743 1c00219c 01df2023 sw x29, 0(x30) x29:1000013c x30:1b000048 PA:1b000048 + 17775500 17760 1c0021a0 015000b3 add x1, x0, x21 x1=1c00215a x21:1c00215a + 17776500 17761 1c0021a2 00100e93 addi x29, x0, 1 x29=00000001 + 17777500 17762 1c0021a4 01ce9e33 sll x28, x29, x28 x28=00000100 x29:00000001 x28:00000008 + 17778500 17763 1c0021a8 fffe0e13 addi x28, x28, -1 x28=000000ff x28:00000100 + 17779500 17764 1c0021aa 21c9a023 sw x28, 512(x19) x28:000000ff x19:1b204000 PA:1b204200 + 17796500 17781 1c0021ae 21c9a623 sw x28, 524(x19) x28:000000ff x19:1b204000 PA:1b20420c + 17797500 17782 1c0021b2 09c9a223 sw x28, 132(x19) x28:000000ff x19:1b204000 PA:1b204084 + 17798500 17783 1c0021b6 001e2863 p.beqimm x28, 16 x28:000000ff + 17799500 17784 1c0021ba 09a9a023 sw x26, 128(x19) x26:1c00222d x19:1b204000 PA:1b204080 + 17817500 17802 1c0021be 0879a023 sw x7, 128(x19) x7:00000400 x19:1b204000 PA:1b204080 + 17818500 17803 1c0021c2 0829a023 sw x2, 128(x19) x2:104fe400 x19:1b204000 PA:1b204080 + 17819500 17804 1c0021c6 02040413 addi x8, x8, 32 x8=1b000028 x8:1b000008 + 17820500 17805 1c0021ca 00941363 bne x8, x9, 6 x8:1b000028 x9:1b000048 + 17823500 17808 1c0021d0 00028067 jalr x0, x5, 0 x5:1c0009d8 + 17841500 17826 1c0009d8 ff010113 addi x2, x2, -16 x2=104fe3f0 x2:104fe400 + 17842500 17827 1c0009da 0ff00713 addi x14, x0, 255 x14=000000ff + 17859500 17844 1c0009de 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 17860500 17845 1c0009e2 00112623 sw x1, 12(x2) x1:1c00215a x2:104fe3f0 PA:104fe3fc + 17861500 17846 1c0009e4 00812423 sw x8, 8(x2) x8:1b000028 x2:104fe3f0 PA:104fe3f8 + 17862500 17847 1c0009e6 00912223 sw x9, 4(x2) x9:1b000048 x2:104fe3f0 PA:104fe3f4 + 17863500 17848 1c0009e8 08e7a223 sw x14, 132(x15) x14:000000ff x15:1b204000 PA:1b204084 + 17864500 17849 1c0009ec 20078493 addi x9, x15, 512 x9=1b204200 x15:1b204000 + 17881500 17866 1c0009f0 00e4a023 sw x14, 0(x9) x14:000000ff x9:1b204200 PA:1b204200 + 17882500 17867 1c0009f2 20c78793 addi x15, x15, 524 x15=1b20420c x15:1b204000 + 17883500 17868 1c0009f6 00e7a023 sw x14, 0(x15) x14:000000ff x15:1b20420c PA:1b20420c + 17884500 17869 1c0009f8 1c0017b7 lui x15, 0x1c001000 x15=1c001000 + 17885500 17870 1c0009fc 9bc78793 addi x15, x15, -1604 x15=1c0009bc x15:1c001000 + 17902500 17887 1c000a00 1b204737 lui x14, 0x1b204000 x14=1b204000 + 17903500 17888 1c000a04 08f72023 sw x15, 128(x14) x15:1c0009bc x14:1b204000 PA:1b204080 + 17904500 17889 1c000a08 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 17905500 17890 1c000a0c 08a7a023 sw x10, 128(x15) x10:00000000 x15:1b204000 PA:1b204080 + 17922500 17907 1c000a10 f1402673 csrrs x12, x0, 0xf14 x12=00000020 + 17923500 17908 1c000a14 40565413 srai x8, x12, 0x405 x8=00000001 x12:00000020 + 17924500 17909 1c000a18 f2643433 p.bclr x8, x8, 25, 6 x8=00000001 x8:00000001 + 17925500 17910 1c000a1c 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17946500 17931 1c000a20 f4563633 p.bclr x12, x12, 26, 5 x12=00000000 x12:00000020 + 17947500 17932 1c000a24 008005b3 add x11, x0, x8 x11=00000001 x8:00000001 + 17948500 17933 1c000a26 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17949500 17934 1c000a2a 5e7000ef jal x1, 3558 x1=1c000a2e + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104fe3b0 x2:104fe3f0 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104fe3b0 PA:104fe3d4 + 17982500 17967 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17983500 17968 1c001818 02c12423 sw x12, 40(x2) x12:00000000 x2:104fe3b0 PA:104fe3d8 + 17984500 17969 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104fe3b0 PA:104fe3dc + 17985500 17970 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17986500 17971 1c00181e 02410693 addi x13, x2, 36 x13=104fe3d4 x2:104fe3b0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c000a2e x2:104fe3b0 PA:104fe3cc + 18005500 17990 1c001828 02e12823 sw x14, 48(x2) x14:1b204000 x2:104fe3b0 PA:104fe3e0 + 18006500 17991 1c00182a 02f12a23 sw x15, 52(x2) x15:1b204000 x2:104fe3b0 PA:104fe3e4 + 18007500 17992 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104fe3b0 PA:104fe3e8 + 18008500 17993 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104fe3b0 PA:104fe3ec + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104fe3d4 x2:104fe3b0 PA:104fe3bc + 18025500 18010 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104fe350 x2:104fe3b0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104fe368 x2:104fe350 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000001 x2:104fe350 PA:104fe3a8 + 18046500 18031 1c001b76 05212823 sw x18, 80(x2) x18:1b000008 x2:104fe350 PA:104fe3a0 + 18047500 18032 1c001b78 05312623 sw x19, 76(x2) x19:1b204000 x2:104fe350 PA:104fe39c + 18048500 18033 1c001b7a 05412423 sw x20, 72(x2) x20:00000002 x2:104fe350 PA:104fe398 + 18049500 18034 1c001b7c 05512223 sw x21, 68(x2) x21:1c00215a x2:104fe350 PA:104fe394 + 18050500 18035 1c001b7e 05612023 sw x22, 64(x2) x22:100fc720 x2:104fe350 PA:104fe390 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:1c2fff70 x2:104fe350 PA:104fe38c + 18067500 18052 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104fe350 PA:104fe3ac + 18068500 18053 1c001b84 04912a23 sw x9, 84(x2) x9:1b204200 x2:104fe350 PA:104fe3a4 + 18069500 18054 1c001b86 03812c23 sw x24, 56(x2) x24:00000001 x2:104fe350 PA:104fe388 + 18070500 18055 1c001b88 03912a23 sw x25, 52(x2) x25:10200e04 x2:104fe350 PA:104fe384 + 18071500 18056 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18072500 18057 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18073500 18058 1c001b8e 00d00433 add x8, x0, x13 x8=104fe3d4 x13:104fe3d4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104fe368 x2:104fe350 PA:104fe364 + 18090500 18075 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18091500 18076 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18092500 18077 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18093500 18078 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18137500 18122 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18138500 18123 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18145500 18130 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18146500 18131 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18147500 18132 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104080 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18266500 18251 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18267500 18252 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18270500 18255 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18271500 18256 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18272500 18257 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18274500 18259 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18275500 18260 1c001778 fddff06f jal x0, -36 + 18277500 18262 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18278500 18263 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18279500 18264 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18280500 18265 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18281500 18266 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18282500 18267 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18283500 18268 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18284500 18269 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18285500 18270 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18286500 18271 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104080 + 18290500 18275 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18291500 18276 1c001bca 16a0006f jal x0, 362 + 18293500 18278 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18294500 18279 1c001d36 e69ff06f jal x0, -408 + 18297500 18282 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18314500 18299 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18315500 18300 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18318500 18303 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18319500 18304 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18320500 18305 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18322500 18307 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18323500 18308 1c001778 fddff06f jal x0, -36 + 18325500 18310 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18326500 18311 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18327500 18312 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18328500 18313 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18329500 18314 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18330500 18315 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18331500 18316 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18332500 18317 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18333500 18318 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18334500 18319 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104080 + 18338500 18323 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18339500 18324 1c001bca 16a0006f jal x0, 362 + 18341500 18326 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18342500 18327 1c001d36 e69ff06f jal x0, -408 + 18345500 18330 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18365500 18350 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18366500 18351 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18369500 18354 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18370500 18355 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18371500 18356 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18373500 18358 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18374500 18359 1c001778 fddff06f jal x0, -36 + 18376500 18361 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18377500 18362 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18378500 18363 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18379500 18364 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18380500 18365 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18381500 18366 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18382500 18367 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18383500 18368 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18384500 18369 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18385500 18370 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104080 + 18389500 18374 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18390500 18375 1c001bca 16a0006f jal x0, 362 + 18392500 18377 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18393500 18378 1c001d36 e69ff06f jal x0, -408 + 18396500 18381 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18410500 18395 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18411500 18396 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18414500 18399 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18415500 18400 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18416500 18401 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18418500 18403 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18419500 18404 1c001778 fddff06f jal x0, -36 + 18421500 18406 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18422500 18407 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18423500 18408 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18424500 18409 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18425500 18410 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18426500 18411 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18427500 18412 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18428500 18413 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18429500 18414 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18430500 18415 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104080 + 18434500 18419 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18435500 18420 1c001bca 16a0006f jal x0, 362 + 18437500 18422 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18438500 18423 1c001d36 e69ff06f jal x0, -408 + 18441500 18426 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18458500 18443 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18459500 18444 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18462500 18447 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18463500 18448 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18464500 18449 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18466500 18451 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18467500 18452 1c001778 fddff06f jal x0, -36 + 18469500 18454 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18470500 18455 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18471500 18456 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18472500 18457 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18473500 18458 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18474500 18459 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18475500 18460 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18476500 18461 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18477500 18462 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18478500 18463 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104080 + 18482500 18467 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18483500 18468 1c001bca 16a0006f jal x0, 362 + 18485500 18470 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18486500 18471 1c001d36 e69ff06f jal x0, -408 + 18489500 18474 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18503500 18488 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18504500 18489 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18507500 18492 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18508500 18493 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18509500 18494 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18511500 18496 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18512500 18497 1c001778 fddff06f jal x0, -36 + 18514500 18499 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18515500 18500 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18516500 18501 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18517500 18502 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18518500 18503 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18519500 18504 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18520500 18505 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18521500 18506 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18522500 18507 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18523500 18508 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104080 + 18527500 18512 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18528500 18513 1c001bca 16a0006f jal x0, 362 + 18530500 18515 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18531500 18516 1c001d36 e69ff06f jal x0, -408 + 18534500 18519 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18549500 18534 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18550500 18535 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18553500 18538 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18554500 18539 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18555500 18540 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18557500 18542 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18558500 18543 1c001778 fddff06f jal x0, -36 + 18560500 18545 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18561500 18546 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18562500 18547 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18563500 18548 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18564500 18549 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18565500 18550 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18566500 18551 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18567500 18552 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18568500 18553 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18569500 18554 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104080 + 18573500 18558 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18574500 18559 1c001bca 16a0006f jal x0, 362 + 18576500 18561 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18577500 18562 1c001d36 e69ff06f jal x0, -408 + 18580500 18565 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18595500 18580 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18596500 18581 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18599500 18584 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18600500 18585 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18601500 18586 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18603500 18588 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18604500 18589 1c001778 fddff06f jal x0, -36 + 18606500 18591 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18607500 18592 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18608500 18593 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18609500 18594 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18610500 18595 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18611500 18596 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18612500 18597 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18613500 18598 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18614500 18599 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18615500 18600 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104080 + 18619500 18604 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18620500 18605 1c001bca 16a0006f jal x0, 362 + 18622500 18607 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18623500 18608 1c001d36 e69ff06f jal x0, -408 + 18626500 18611 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18641500 18626 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18642500 18627 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18645500 18630 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18646500 18631 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18647500 18632 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18649500 18634 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18650500 18635 1c001778 fddff06f jal x0, -36 + 18652500 18637 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18653500 18638 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18654500 18639 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18655500 18640 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18656500 18641 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18657500 18642 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18658500 18643 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18659500 18644 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18660500 18645 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18661500 18646 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104080 + 18665500 18650 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18666500 18651 1c001bca 16a0006f jal x0, 362 + 18668500 18653 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18669500 18654 1c001d36 e69ff06f jal x0, -408 + 18672500 18657 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18687500 18672 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18688500 18673 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18691500 18676 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18692500 18677 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18693500 18678 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18695500 18680 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18696500 18681 1c001778 fddff06f jal x0, -36 + 18698500 18683 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18699500 18684 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18700500 18685 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18701500 18686 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18702500 18687 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18703500 18688 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18704500 18689 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18705500 18690 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18706500 18691 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18707500 18692 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104080 + 18711500 18696 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18712500 18697 1c001bca 16a0006f jal x0, 362 + 18714500 18699 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18715500 18700 1c001d36 e69ff06f jal x0, -408 + 18718500 18703 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18734500 18719 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18735500 18720 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18738500 18723 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18739500 18724 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18740500 18725 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18742500 18727 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18743500 18728 1c001778 fddff06f jal x0, -36 + 18745500 18730 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18746500 18731 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18747500 18732 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18748500 18733 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18749500 18734 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18750500 18735 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18751500 18736 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18752500 18737 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18753500 18738 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18754500 18739 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104080 + 18758500 18743 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18759500 18744 1c001bca 16a0006f jal x0, 362 + 18761500 18746 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18762500 18747 1c001d36 e69ff06f jal x0, -408 + 18765500 18750 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18780500 18765 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18781500 18766 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18784500 18769 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18785500 18770 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18786500 18771 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18788500 18773 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18789500 18774 1c001778 fddff06f jal x0, -36 + 18791500 18776 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18792500 18777 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18793500 18778 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18794500 18779 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18795500 18780 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18796500 18781 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18797500 18782 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18798500 18783 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18799500 18784 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18800500 18785 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104080 + 18804500 18789 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18805500 18790 1c001bca 16a0006f jal x0, 362 + 18807500 18792 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18808500 18793 1c001d36 e69ff06f jal x0, -408 + 18811500 18796 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18828500 18813 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18829500 18814 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18832500 18817 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18833500 18818 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18834500 18819 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18836500 18821 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18837500 18822 1c001778 fddff06f jal x0, -36 + 18839500 18824 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18840500 18825 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18841500 18826 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18842500 18827 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18843500 18828 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18844500 18829 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18845500 18830 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18846500 18831 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18847500 18832 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18848500 18833 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104080 + 18852500 18837 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18853500 18838 1c001bca 16a0006f jal x0, 362 + 18855500 18840 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18856500 18841 1c001d36 e69ff06f jal x0, -408 + 18859500 18844 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18875500 18860 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18876500 18861 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18879500 18864 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18880500 18865 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18881500 18866 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18883500 18868 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18884500 18869 1c001778 fddff06f jal x0, -36 + 18886500 18871 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18887500 18872 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 18888500 18873 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18889500 18874 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 18890500 18875 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 18891500 18876 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 18892500 18877 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 18893500 18878 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 18894500 18879 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18895500 18880 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104080 + 18899500 18884 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18900500 18885 1c001bca 16a0006f jal x0, 362 + 18902500 18887 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18903500 18888 1c001d36 e69ff06f jal x0, -408 + 18906500 18891 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18922500 18907 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18923500 18908 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18926500 18911 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18929500 18914 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104fe350 PA:104fe354 + 18930500 18915 1c001bd0 00012423 sw x0, 8(x2) x2:104fe350 PA:104fe358 + 18931500 18916 1c001bd2 00010623 sb x0, 12(x2) x2:104fe350 PA:104fe35c + 18932500 18917 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18933500 18918 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fe350 PA:104fe354 + 18954500 18939 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18955500 18940 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18956500 18941 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18957500 18942 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18958500 18943 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19013500 18998 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19014500 18999 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19021500 19006 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19022500 19007 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19023500 19008 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fe350 PA:104fe360 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104fe3d8 x8:104fe3d4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104fe3d4 PA:104fe3d4 + 19399500 19384 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104fe354 x2:104fe350 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104fe368 x11:104fe354 PA:104fe364 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe354 PA:104fe360 + 19528500 19513 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19529500 19514 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19563500 19548 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19564500 19549 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19565500 19550 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19566500 19551 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19569500 19554 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe354 PA:104fe360 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104fe368 PA:104fe368 + 19742500 19727 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19743500 19728 1c001a5e 00168693 addi x13, x13, 1 x13=104fe369 x13:104fe368 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104fe369 PA:104fe369 + 19764500 19749 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19766500 19751 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104fe354 x2:104fe350 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104fe330 x2:104fe350 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104fe3d4 x2:104fe330 PA:104fe348 + 19812500 19797 1c001a66 01062783 lw x15, 16(x12) x15=104fe368 x12:104fe354 PA:104fe364 + 19813500 19798 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fe354 PA:104fe358 + 19814500 19799 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104fe330 PA:104fe344 + 19815500 19800 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fe330 PA:104fe340 + 19816500 19801 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fe330 PA:104fe33c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fe330 PA:104fe34c + 19836500 19821 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fe330 PA:104fe338 + 19837500 19822 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19838500 19823 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19839500 19824 1c001a78 00c004b3 add x9, x0, x12 x9=104fe354 x12:104fe354 + 19840500 19825 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104fe369 x15:104fe368 PA:104fe368 + 19842500 19827 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fe354 PA:104fe35c + 19865500 19850 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19868500 19853 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fe354 PA:104fe35c + 19957500 19942 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 19979500 19964 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19980500 19965 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fe368 x9:104fe354 PA:104fe364 + 20023500 20008 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104fe369 x20:104fe368 PA:104fe368 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104080 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fe36a x20:104fe369 PA:104fe369 + 20100500 20085 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20101500 20086 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 20103500 20088 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20104500 20089 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fe330 PA:104fe34c + 20124500 20109 1c001b02 01812403 lw x8, 24(x2) x8=104fe3d4 x2:104fe330 PA:104fe348 + 20125500 20110 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104fe330 PA:104fe344 + 20126500 20111 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fe330 PA:104fe340 + 20127500 20112 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fe330 PA:104fe33c + 20128500 20113 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fe330 PA:104fe338 + 20129500 20114 1c001b0c 02010113 addi x2, x2, 32 x2=104fe350 x2:104fe330 + 20130500 20115 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104fe3d8 x24:104fe3d8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20191500 20176 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20192500 20177 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20195500 20180 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20196500 20181 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20197500 20182 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20199500 20184 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20200500 20185 1c001778 fddff06f jal x0, -36 + 20202500 20187 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20203500 20188 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 20204500 20189 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20205500 20190 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 20206500 20191 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 20207500 20192 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 20208500 20193 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 20209500 20194 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 20210500 20195 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20211500 20196 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104080 + 20215500 20200 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20216500 20201 1c001bca 16a0006f jal x0, 362 + 20218500 20203 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20219500 20204 1c001d36 e69ff06f jal x0, -408 + 20222500 20207 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20240500 20225 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20241500 20226 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20244500 20229 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20245500 20230 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20246500 20231 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20248500 20233 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20249500 20234 1c001778 fddff06f jal x0, -36 + 20251500 20236 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20252500 20237 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 20253500 20238 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20254500 20239 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 20255500 20240 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 20256500 20241 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 20257500 20242 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 20258500 20243 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 20259500 20244 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20260500 20245 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104080 + 20264500 20249 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20265500 20250 1c001bca 16a0006f jal x0, 362 + 20267500 20252 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20268500 20253 1c001d36 e69ff06f jal x0, -408 + 20271500 20256 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20290500 20275 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20291500 20276 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20294500 20279 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20297500 20282 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104fe350 PA:104fe354 + 20298500 20283 1c001bd0 00012423 sw x0, 8(x2) x2:104fe350 PA:104fe358 + 20299500 20284 1c001bd2 00010623 sb x0, 12(x2) x2:104fe350 PA:104fe35c + 20300500 20285 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20301500 20286 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20302500 20287 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20303500 20288 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fe350 PA:104fe354 + 20304500 20289 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20305500 20290 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20306500 20291 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20307500 20292 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20308500 20293 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20309500 20294 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20310500 20295 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20311500 20296 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20326500 20311 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20327500 20312 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20330500 20315 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20331500 20316 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20332500 20317 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20335500 20320 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20338500 20323 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20341500 20326 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20344500 20329 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20345500 20330 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20346500 20331 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20347500 20332 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20350500 20335 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20351500 20336 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20354500 20339 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20355500 20340 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20358500 20343 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20360500 20345 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20363500 20348 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20364500 20349 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20367500 20352 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20368500 20353 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20369500 20354 1c001f42 e09ff06f jal x0, -504 + 20371500 20356 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20372500 20357 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fe350 PA:104fe360 + 20373500 20358 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20376500 20361 1c001e34 00440c13 addi x24, x8, 4 x24=104fe3dc x8:104fe3d8 + 20377500 20362 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:104fe3d8 PA:104fe3d8 + 20378500 20363 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20381500 20366 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20384500 20369 1c001e64 00410593 addi x11, x2, 4 x11=104fe354 x2:104fe350 + 20385500 20370 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20387500 20372 1c0019fe 0105a683 lw x13, 16(x11) x13=104fe368 x11:104fe354 PA:104fe364 + 20388500 20373 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe354 PA:104fe360 + 20389500 20374 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20390500 20375 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20424500 20409 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20425500 20410 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20426500 20411 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20427500 20412 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20430500 20415 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe354 PA:104fe360 + 20431500 20416 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20465500 20450 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20499500 20484 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20530500 20515 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20531500 20516 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 20532500 20517 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 20533500 20518 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 20534500 20519 1c001a38 01e0006f jal x0, 30 + 20536500 20521 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 20537500 20522 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:104fe368 PA:104fe368 + 20538500 20523 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20539500 20524 1c001a5e 00168693 addi x13, x13, 1 x13=104fe369 x13:104fe368 + 20540500 20525 1c001a60 fb1ff06f jal x0, -80 + 20542500 20527 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20543500 20528 1c001a12 00068023 sb x0, 0(x13) x13:104fe369 PA:104fe369 + 20544500 20529 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20546500 20531 1c001e68 f17ff06f jal x0, -234 + 20548500 20533 1c001d7e 00410613 addi x12, x2, 4 x12=104fe354 x2:104fe350 + 20549500 20534 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20550500 20535 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20551500 20536 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20553500 20538 1c001a62 fe010113 addi x2, x2, -32 x2=104fe330 x2:104fe350 + 20554500 20539 1c001a64 00812c23 sw x8, 24(x2) x8:104fe3d8 x2:104fe330 PA:104fe348 + 20555500 20540 1c001a66 01062783 lw x15, 16(x12) x15=104fe368 x12:104fe354 PA:104fe364 + 20556500 20541 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fe354 PA:104fe358 + 20557500 20542 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104fe330 PA:104fe344 + 20558500 20543 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fe330 PA:104fe340 + 20559500 20544 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fe330 PA:104fe33c + 20560500 20545 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fe330 PA:104fe34c + 20561500 20546 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fe330 PA:104fe338 + 20562500 20547 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20563500 20548 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20564500 20549 1c001a78 00c004b3 add x9, x0, x12 x9=104fe354 x12:104fe354 + 20565500 20550 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=104fe369 x15:104fe368 PA:104fe368 + 20567500 20552 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 20568500 20553 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20569500 20554 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fe354 PA:104fe35c + 20571500 20556 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20574500 20559 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 20576500 20561 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20577500 20562 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20580500 20565 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20581500 20566 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20582500 20567 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20585500 20570 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20586500 20571 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20587500 20572 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20588500 20573 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20589500 20574 1c001b36 f71ff06f jal x0, -144 + 20591500 20576 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fe354 PA:104fe35c + 20593500 20578 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20596500 20581 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 20598500 20583 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20599500 20584 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20602500 20587 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 20603500 20588 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20604500 20589 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20605500 20590 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20606500 20591 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fe368 x9:104fe354 PA:104fe364 + 20608500 20593 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=104fe369 x20:104fe368 PA:104fe368 + 20610500 20595 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 20613500 20598 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20614500 20599 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20616500 20601 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 20617500 20602 1c001778 fddff06f jal x0, -36 + 20619500 20604 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20620500 20605 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 20621500 20606 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20622500 20607 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 20623500 20608 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 20624500 20609 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 20625500 20610 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 20626500 20611 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 20627500 20612 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20628500 20613 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104080 + 20632500 20617 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20633500 20618 1c001b62 f8bff06f jal x0, -118 + 20635500 20620 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fe36a x20:104fe369 PA:104fe369 + 20637500 20622 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20638500 20623 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe354 PA:104fe354 + 20640500 20625 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20641500 20626 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20644500 20629 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fe330 PA:104fe34c + 20645500 20630 1c001b02 01812403 lw x8, 24(x2) x8=104fe3d8 x2:104fe330 PA:104fe348 + 20646500 20631 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104fe330 PA:104fe344 + 20647500 20632 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fe330 PA:104fe340 + 20648500 20633 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fe330 PA:104fe33c + 20649500 20634 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fe330 PA:104fe338 + 20650500 20635 1c001b0c 02010113 addi x2, x2, 32 x2=104fe350 x2:104fe330 + 20651500 20636 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20653500 20638 1c001d86 01800433 add x8, x0, x24 x8=104fe3dc x24:104fe3dc + 20654500 20639 1c001d88 fadff06f jal x0, -84 + 20656500 20641 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20657500 20642 1c001d36 e69ff06f jal x0, -408 + 20660500 20645 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20688500 20673 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20689500 20674 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20692500 20677 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20693500 20678 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20694500 20679 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20696500 20681 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20697500 20682 1c001778 fddff06f jal x0, -36 + 20699500 20684 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20700500 20685 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 20701500 20686 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20702500 20687 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 20703500 20688 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 20704500 20689 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 20705500 20690 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 20706500 20691 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 20707500 20692 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20708500 20693 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104080 + 20712500 20697 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20713500 20698 1c001bca 16a0006f jal x0, 362 + 20715500 20700 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20716500 20701 1c001d36 e69ff06f jal x0, -408 + 20719500 20704 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20734500 20719 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20735500 20720 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20738500 20723 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20739500 20724 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20740500 20725 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20742500 20727 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20743500 20728 1c001778 fddff06f jal x0, -36 + 20745500 20730 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20746500 20731 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 20747500 20732 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20748500 20733 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 20749500 20734 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 20750500 20735 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 20751500 20736 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 20752500 20737 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 20753500 20738 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20754500 20739 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104080 + 20758500 20743 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20759500 20744 1c001bca 16a0006f jal x0, 362 + 20761500 20746 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20762500 20747 1c001d36 e69ff06f jal x0, -408 + 20765500 20750 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20783500 20768 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20784500 20769 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20787500 20772 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20788500 20773 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20789500 20774 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20791500 20776 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20792500 20777 1c001778 fddff06f jal x0, -36 + 20794500 20779 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20795500 20780 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000020 + 20796500 20781 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20797500 20782 1c00175e 00379713 slli x14, x15, 0x3 x14=00000100 x15:00000020 + 20798500 20783 1c001762 00279793 slli x15, x15, 0x2 x15=00000080 x15:00000020 + 20799500 20784 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000100 + 20800500 20785 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000080 x13:00001f80 + 20801500 20786 1c00176a 00e787b3 add x15, x15, x14 x15=00000080 x15:00000080 x14:00000000 + 20802500 20787 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20803500 20788 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104080 + 20807500 20792 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20808500 20793 1c001bca 16a0006f jal x0, 362 + 20810500 20795 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20811500 20796 1c001d36 e69ff06f jal x0, -408 + 20814500 20799 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20828500 20813 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20829500 20814 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20830500 20815 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104fe350 PA:104fe3ac + 20831500 20816 1c001baa 05812403 lw x8, 88(x2) x8=00000001 x2:104fe350 PA:104fe3a8 + 20832500 20817 1c001bac 05412483 lw x9, 84(x2) x9=1b204200 x2:104fe350 PA:104fe3a4 + 20833500 20818 1c001bae 05012903 lw x18, 80(x2) x18=1b000008 x2:104fe350 PA:104fe3a0 + 20834500 20819 1c001bb0 04c12983 lw x19, 76(x2) x19=1b204000 x2:104fe350 PA:104fe39c + 20835500 20820 1c001bb2 04812a03 lw x20, 72(x2) x20=00000002 x2:104fe350 PA:104fe398 + 20836500 20821 1c001bb4 04412a83 lw x21, 68(x2) x21=1c00215a x2:104fe350 PA:104fe394 + 20837500 20822 1c001bb6 04012b03 lw x22, 64(x2) x22=100fc720 x2:104fe350 PA:104fe390 + 20838500 20823 1c001bb8 03c12b83 lw x23, 60(x2) x23=1c2fff70 x2:104fe350 PA:104fe38c + 20839500 20824 1c001bba 03812c03 lw x24, 56(x2) x24=00000001 x2:104fe350 PA:104fe388 + 20840500 20825 1c001bbc 03412c83 lw x25, 52(x2) x25=10200e04 x2:104fe350 PA:104fe384 + 20841500 20826 1c001bbe 06010113 addi x2, x2, 96 x2=104fe3b0 x2:104fe350 + 20842500 20827 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20844500 20829 1c001834 01c12083 lw x1, 28(x2) x1=1c000a2e x2:104fe3b0 PA:104fe3cc + 20845500 20830 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20846500 20831 1c001838 04010113 addi x2, x2, 64 x2=104fe3f0 x2:104fe3b0 + 20847500 20832 1c00183a 00008067 jalr x0, x1, 0 x1:1c000a2e + 20850500 20835 1c000a2e 01c4e783 p.elw x15, 28(x9) x15=00000000 x9:1b204200 PA:1b20421c + 20859500 20844 1c000a32 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 20860500 20845 1c000a36 00241413 slli x8, x8, 0x2 x8=00000004 x8:00000001 + 20861500 20846 1c000a38 68478793 addi x15, x15, 1668 x15=1c002684 x15:1c002000 + 20862500 20847 1c000a3c 00100713 addi x14, x0, 1 x14=00000001 + 20879500 20864 1c000a3e 00e7e423 p.sw x14, x0(x15) x14:00000001 x15:1c002684 PA:1c002688 + 20897500 20882 1c000a42 00c12083 lw x1, 12(x2) x1=1c00215a x2:104fe3f0 PA:104fe3fc + 20898500 20883 1c000a44 00812403 lw x8, 8(x2) x8=1b000028 x2:104fe3f0 PA:104fe3f8 + 20899500 20884 1c000a46 00412483 lw x9, 4(x2) x9=1b000048 x2:104fe3f0 PA:104fe3f4 + 20900500 20885 1c000a48 01010113 addi x2, x2, 16 x2=104fe400 x2:104fe3f0 + 20901500 20886 1c000a4a 00008067 jalr x0, x1, 0 x1:1c00215a + 20903500 20888 1c00215a 000b0a63 beq x22, x0, 20 x22:100fc720 + 20905500 20890 1c00215e 000ba283 lw x5, 0(x23) x5=00000000 x23:1c2fff70 PA:1c2fff70 + 20920500 20905 1c002162 06029f63 bne x5, x0, 126 x5:00000000 + 20921500 20906 1c002166 016ba023 sw x22, 0(x23) x22:100fc720 x23:1c2fff70 PA:1c2fff70 + 20939500 20924 1c00216a 018ca023 sw x24, 0(x25) x24:00000001 x25:10200e04 PA:10200e04 + 20943500 20928 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028 + 20945500 20930 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 20948500 20933 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 + 20949500 20934 1c0021d6 03c9e003 p.elw x0, 60(x19) x19:1b204000 PA:1b20403c + 20954500 20939 1c0021da 0149a223 sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004 + 20955500 20940 1c0021de f91ff06f jal x0, -112 + 20958500 20943 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028 + 20960500 20945 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 20963500 20948 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_1.log b/sw/scripts/tracevis/example/traces/trace_core_01_1.log new file mode 100644 index 0000000..196502f --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_1.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000021 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000001 x10:00000021 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000021 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000001 + 12641500 12626 1c0000a6 05a0206f jal x0, 8282 + 12659500 12644 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12660500 12645 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12661500 12646 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12662500 12647 1c00210c 0e059163 bne x11, x0, 226 x11:00000001 + 12714500 12699 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 12715500 12700 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000021 + 12716500 12701 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000001 x19:00000021 + 12717500 12702 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 12734500 12719 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 12735500 12720 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 12736500 12721 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 12737500 12722 1c00220a 0060006f jal x0, 6 + 12757500 12742 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 17807500 17792 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 17825500 17810 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 17826500 17811 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 17844500 17829 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 17845500 17830 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 17847500 17832 1c00222c 08096283 p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080 + 17871500 17856 1c002230 02a98533 mul x10, x19, x10 x10=00000400 x19:00000001 x10:00000400 + 17872500 17857 1c002234 00550133 add x2, x10, x5 x2=104fe800 x10:00000400 x5:104fe400 + 17873500 17858 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 17875500 17860 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 17911500 17896 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 17919500 17904 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 17920500 17905 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 17921500 17906 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 17922500 17907 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 17940500 17925 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000021 + 17957500 17942 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17958500 17943 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000001 x12:00000021 + 17959500 17944 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001 + 17960500 17945 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000001 x12:00000021 + 17961500 17946 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17962500 17947 1c0009d4 63d0006f jal x0, 3644 + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104fe7c0 x2:104fe800 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104fe7c0 PA:104fe7e4 + 17985500 17970 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17986500 17971 1c001818 02c12423 sw x12, 40(x2) x12:00000001 x2:104fe7c0 PA:104fe7e8 + 17987500 17972 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104fe7c0 PA:104fe7ec + 17988500 17973 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17989500 17974 1c00181e 02410693 addi x13, x2, 36 x13=104fe7e4 x2:104fe7c0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:104fe7c0 PA:104fe7dc + 18007500 17992 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:104fe7c0 PA:104fe7f0 + 18008500 17993 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:104fe7c0 PA:104fe7f4 + 18009500 17994 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104fe7c0 PA:104fe7f8 + 18010500 17995 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104fe7c0 PA:104fe7fc + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104fe7e4 x2:104fe7c0 PA:104fe7cc + 18026500 18011 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104fe760 x2:104fe7c0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104fe778 x2:104fe760 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:104fe760 PA:104fe7b8 + 18052500 18037 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:104fe760 PA:104fe7b0 + 18053500 18038 1c001b78 05312623 sw x19, 76(x2) x19:00000001 x2:104fe760 PA:104fe7ac + 18054500 18039 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:104fe760 PA:104fe7a8 + 18055500 18040 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:104fe760 PA:104fe7a4 + 18056500 18041 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:104fe760 PA:104fe7a0 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:104fe760 PA:104fe79c + 18069500 18054 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104fe760 PA:104fe7bc + 18070500 18055 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:104fe760 PA:104fe7b4 + 18071500 18056 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:104fe760 PA:104fe798 + 18072500 18057 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:104fe760 PA:104fe794 + 18073500 18058 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18074500 18059 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18075500 18060 1c001b8e 00d00433 add x8, x0, x13 x8=104fe7e4 x13:104fe7e4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104fe778 x2:104fe760 PA:104fe774 + 18090500 18075 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18091500 18076 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18092500 18077 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18093500 18078 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18125500 18110 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18126500 18111 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18145500 18130 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18146500 18131 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18147500 18132 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104088 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18251500 18236 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18252500 18237 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18255500 18240 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18256500 18241 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18257500 18242 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18259500 18244 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18260500 18245 1c001778 fddff06f jal x0, -36 + 18262500 18247 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18263500 18248 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18264500 18249 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18265500 18250 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18266500 18251 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18267500 18252 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18268500 18253 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18269500 18254 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18270500 18255 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18271500 18256 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104088 + 18275500 18260 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18276500 18261 1c001bca 16a0006f jal x0, 362 + 18278500 18263 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18279500 18264 1c001d36 e69ff06f jal x0, -408 + 18282500 18267 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18296500 18281 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18297500 18282 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18300500 18285 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18301500 18286 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18302500 18287 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18304500 18289 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18305500 18290 1c001778 fddff06f jal x0, -36 + 18307500 18292 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18308500 18293 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18309500 18294 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18310500 18295 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18311500 18296 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18312500 18297 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18313500 18298 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18314500 18299 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18315500 18300 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18316500 18301 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104088 + 18320500 18305 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18321500 18306 1c001bca 16a0006f jal x0, 362 + 18323500 18308 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18324500 18309 1c001d36 e69ff06f jal x0, -408 + 18327500 18312 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18341500 18326 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18342500 18327 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18345500 18330 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18346500 18331 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18347500 18332 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18349500 18334 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18350500 18335 1c001778 fddff06f jal x0, -36 + 18352500 18337 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18353500 18338 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18354500 18339 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18355500 18340 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18356500 18341 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18357500 18342 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18358500 18343 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18359500 18344 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18360500 18345 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18361500 18346 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104088 + 18365500 18350 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18366500 18351 1c001bca 16a0006f jal x0, 362 + 18368500 18353 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18369500 18354 1c001d36 e69ff06f jal x0, -408 + 18372500 18357 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18386500 18371 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18387500 18372 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18390500 18375 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18391500 18376 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18392500 18377 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18394500 18379 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18395500 18380 1c001778 fddff06f jal x0, -36 + 18397500 18382 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18398500 18383 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18399500 18384 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18400500 18385 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18401500 18386 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18402500 18387 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18403500 18388 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18404500 18389 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18405500 18390 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18406500 18391 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104088 + 18410500 18395 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18411500 18396 1c001bca 16a0006f jal x0, 362 + 18413500 18398 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18414500 18399 1c001d36 e69ff06f jal x0, -408 + 18417500 18402 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18431500 18416 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18432500 18417 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18435500 18420 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18436500 18421 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18437500 18422 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18439500 18424 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18440500 18425 1c001778 fddff06f jal x0, -36 + 18442500 18427 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18443500 18428 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18444500 18429 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18445500 18430 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18446500 18431 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18447500 18432 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18448500 18433 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18449500 18434 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18450500 18435 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18451500 18436 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104088 + 18455500 18440 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18456500 18441 1c001bca 16a0006f jal x0, 362 + 18458500 18443 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18459500 18444 1c001d36 e69ff06f jal x0, -408 + 18462500 18447 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18476500 18461 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18477500 18462 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18480500 18465 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18481500 18466 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18482500 18467 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18484500 18469 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18485500 18470 1c001778 fddff06f jal x0, -36 + 18487500 18472 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18488500 18473 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18489500 18474 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18490500 18475 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18491500 18476 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18492500 18477 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18493500 18478 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18494500 18479 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18495500 18480 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18496500 18481 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104088 + 18500500 18485 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18501500 18486 1c001bca 16a0006f jal x0, 362 + 18503500 18488 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18504500 18489 1c001d36 e69ff06f jal x0, -408 + 18507500 18492 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18523500 18508 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18524500 18509 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18527500 18512 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18528500 18513 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18529500 18514 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18531500 18516 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18532500 18517 1c001778 fddff06f jal x0, -36 + 18534500 18519 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18535500 18520 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18536500 18521 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18537500 18522 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18538500 18523 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18539500 18524 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18540500 18525 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18541500 18526 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18542500 18527 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18543500 18528 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104088 + 18547500 18532 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18548500 18533 1c001bca 16a0006f jal x0, 362 + 18550500 18535 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18551500 18536 1c001d36 e69ff06f jal x0, -408 + 18554500 18539 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18568500 18553 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18569500 18554 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18572500 18557 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18573500 18558 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18574500 18559 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18576500 18561 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18577500 18562 1c001778 fddff06f jal x0, -36 + 18579500 18564 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18580500 18565 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18581500 18566 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18582500 18567 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18583500 18568 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18584500 18569 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18585500 18570 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18586500 18571 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18587500 18572 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18588500 18573 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104088 + 18592500 18577 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18593500 18578 1c001bca 16a0006f jal x0, 362 + 18595500 18580 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18596500 18581 1c001d36 e69ff06f jal x0, -408 + 18599500 18584 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18614500 18599 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18615500 18600 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18618500 18603 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18619500 18604 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18620500 18605 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18622500 18607 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18623500 18608 1c001778 fddff06f jal x0, -36 + 18625500 18610 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18626500 18611 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18627500 18612 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18628500 18613 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18629500 18614 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18630500 18615 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18631500 18616 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18632500 18617 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18633500 18618 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18634500 18619 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104088 + 18638500 18623 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18639500 18624 1c001bca 16a0006f jal x0, 362 + 18641500 18626 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18642500 18627 1c001d36 e69ff06f jal x0, -408 + 18645500 18630 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18663500 18648 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18664500 18649 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18667500 18652 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18668500 18653 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18669500 18654 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18671500 18656 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18672500 18657 1c001778 fddff06f jal x0, -36 + 18674500 18659 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18675500 18660 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18676500 18661 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18677500 18662 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18678500 18663 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18679500 18664 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18680500 18665 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18681500 18666 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18682500 18667 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18683500 18668 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104088 + 18687500 18672 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18688500 18673 1c001bca 16a0006f jal x0, 362 + 18690500 18675 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18691500 18676 1c001d36 e69ff06f jal x0, -408 + 18694500 18679 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18708500 18693 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18709500 18694 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18712500 18697 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18713500 18698 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18714500 18699 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18716500 18701 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18717500 18702 1c001778 fddff06f jal x0, -36 + 18719500 18704 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18720500 18705 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18721500 18706 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18722500 18707 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18723500 18708 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18724500 18709 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18725500 18710 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18726500 18711 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18727500 18712 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18728500 18713 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104088 + 18732500 18717 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18733500 18718 1c001bca 16a0006f jal x0, 362 + 18735500 18720 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18736500 18721 1c001d36 e69ff06f jal x0, -408 + 18739500 18724 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18753500 18738 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18754500 18739 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18757500 18742 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18758500 18743 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18759500 18744 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18761500 18746 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18762500 18747 1c001778 fddff06f jal x0, -36 + 18764500 18749 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18765500 18750 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18766500 18751 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18767500 18752 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18768500 18753 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18769500 18754 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18770500 18755 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18771500 18756 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18772500 18757 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18773500 18758 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104088 + 18777500 18762 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18778500 18763 1c001bca 16a0006f jal x0, 362 + 18780500 18765 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18781500 18766 1c001d36 e69ff06f jal x0, -408 + 18784500 18769 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18806500 18791 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18807500 18792 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18810500 18795 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18811500 18796 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18812500 18797 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18814500 18799 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18815500 18800 1c001778 fddff06f jal x0, -36 + 18817500 18802 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18818500 18803 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18819500 18804 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18820500 18805 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18821500 18806 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18822500 18807 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18823500 18808 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18824500 18809 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18825500 18810 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18826500 18811 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104088 + 18830500 18815 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18831500 18816 1c001bca 16a0006f jal x0, 362 + 18833500 18818 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18834500 18819 1c001d36 e69ff06f jal x0, -408 + 18837500 18822 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18852500 18837 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18853500 18838 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18856500 18841 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18857500 18842 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18858500 18843 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18860500 18845 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18861500 18846 1c001778 fddff06f jal x0, -36 + 18863500 18848 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18864500 18849 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 18865500 18850 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18866500 18851 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 18867500 18852 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 18868500 18853 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 18869500 18854 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 18870500 18855 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 18871500 18856 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18872500 18857 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104088 + 18876500 18861 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18877500 18862 1c001bca 16a0006f jal x0, 362 + 18879500 18864 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18880500 18865 1c001d36 e69ff06f jal x0, -408 + 18883500 18868 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18901500 18886 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18902500 18887 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18905500 18890 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18908500 18893 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104fe760 PA:104fe764 + 18929500 18914 1c001bd0 00012423 sw x0, 8(x2) x2:104fe760 PA:104fe768 + 18934500 18919 1c001bd2 00010623 sb x0, 12(x2) x2:104fe760 PA:104fe76c + 18935500 18920 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18936500 18921 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fe760 PA:104fe764 + 18955500 18940 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18956500 18941 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18957500 18942 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18958500 18943 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18959500 18944 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 18995500 18980 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19000500 18985 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19021500 19006 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19022500 19007 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19023500 19008 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fe760 PA:104fe770 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104fe7e8 x8:104fe7e4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104fe7e4 PA:104fe7e4 + 19399500 19384 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104fe764 x2:104fe760 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104fe778 x11:104fe764 PA:104fe774 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe764 PA:104fe770 + 19528500 19513 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19529500 19514 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19563500 19548 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19564500 19549 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19565500 19550 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19566500 19551 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19569500 19554 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe764 PA:104fe770 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104fe778 PA:104fe778 + 19742500 19727 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19743500 19728 1c001a5e 00168693 addi x13, x13, 1 x13=104fe779 x13:104fe778 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104fe779 PA:104fe779 + 19770500 19755 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19771500 19756 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104fe764 x2:104fe760 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104fe740 x2:104fe760 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104fe7e4 x2:104fe740 PA:104fe758 + 19813500 19798 1c001a66 01062783 lw x15, 16(x12) x15=104fe778 x12:104fe764 PA:104fe774 + 19814500 19799 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fe764 PA:104fe768 + 19815500 19800 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104fe740 PA:104fe754 + 19816500 19801 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fe740 PA:104fe750 + 19817500 19802 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fe740 PA:104fe74c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fe740 PA:104fe75c + 19836500 19821 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fe740 PA:104fe748 + 19837500 19822 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19838500 19823 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19839500 19824 1c001a78 00c004b3 add x9, x0, x12 x9=104fe764 x12:104fe764 + 19840500 19825 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104fe779 x15:104fe778 PA:104fe778 + 19842500 19827 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fe764 PA:104fe76c + 19870500 19855 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19873500 19858 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fe764 PA:104fe76c + 19961500 19946 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 19985500 19970 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19986500 19971 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fe778 x9:104fe764 PA:104fe774 + 20029500 20014 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104fe779 x20:104fe778 PA:104fe778 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104088 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fe77a x20:104fe779 PA:104fe779 + 20104500 20089 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20105500 20090 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 20107500 20092 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20108500 20093 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fe740 PA:104fe75c + 20124500 20109 1c001b02 01812403 lw x8, 24(x2) x8=104fe7e4 x2:104fe740 PA:104fe758 + 20125500 20110 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104fe740 PA:104fe754 + 20126500 20111 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fe740 PA:104fe750 + 20127500 20112 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fe740 PA:104fe74c + 20128500 20113 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fe740 PA:104fe748 + 20129500 20114 1c001b0c 02010113 addi x2, x2, 32 x2=104fe760 x2:104fe740 + 20130500 20115 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104fe7e8 x24:104fe7e8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20174500 20159 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20175500 20160 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20178500 20163 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20179500 20164 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20180500 20165 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20182500 20167 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20183500 20168 1c001778 fddff06f jal x0, -36 + 20185500 20170 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20186500 20171 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 20187500 20172 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20188500 20173 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 20189500 20174 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 20190500 20175 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 20191500 20176 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 20192500 20177 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 20193500 20178 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20194500 20179 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104088 + 20198500 20183 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20199500 20184 1c001bca 16a0006f jal x0, 362 + 20201500 20186 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20202500 20187 1c001d36 e69ff06f jal x0, -408 + 20205500 20190 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20221500 20206 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20222500 20207 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20225500 20210 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20226500 20211 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20227500 20212 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20229500 20214 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20230500 20215 1c001778 fddff06f jal x0, -36 + 20232500 20217 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20233500 20218 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 20234500 20219 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20235500 20220 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 20236500 20221 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 20237500 20222 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 20238500 20223 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 20239500 20224 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 20240500 20225 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20241500 20226 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104088 + 20245500 20230 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20246500 20231 1c001bca 16a0006f jal x0, 362 + 20248500 20233 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20249500 20234 1c001d36 e69ff06f jal x0, -408 + 20252500 20237 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20266500 20251 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20267500 20252 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20270500 20255 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20273500 20258 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104fe760 PA:104fe764 + 20274500 20259 1c001bd0 00012423 sw x0, 8(x2) x2:104fe760 PA:104fe768 + 20275500 20260 1c001bd2 00010623 sb x0, 12(x2) x2:104fe760 PA:104fe76c + 20276500 20261 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20277500 20262 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20278500 20263 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20279500 20264 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fe760 PA:104fe764 + 20280500 20265 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20281500 20266 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20282500 20267 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20283500 20268 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20284500 20269 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20285500 20270 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20286500 20271 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20287500 20272 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20301500 20286 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20302500 20287 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20305500 20290 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20306500 20291 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20307500 20292 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20310500 20295 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20313500 20298 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20316500 20301 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20319500 20304 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20320500 20305 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20321500 20306 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20322500 20307 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20325500 20310 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20326500 20311 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20329500 20314 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20330500 20315 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20333500 20318 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20335500 20320 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20338500 20323 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20339500 20324 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20342500 20327 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20343500 20328 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20344500 20329 1c001f42 e09ff06f jal x0, -504 + 20346500 20331 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20347500 20332 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fe760 PA:104fe770 + 20348500 20333 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20351500 20336 1c001e34 00440c13 addi x24, x8, 4 x24=104fe7ec x8:104fe7e8 + 20352500 20337 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104fe7e8 PA:104fe7e8 + 20353500 20338 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20356500 20341 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 20359500 20344 1c001e64 00410593 addi x11, x2, 4 x11=104fe764 x2:104fe760 + 20360500 20345 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20362500 20347 1c0019fe 0105a683 lw x13, 16(x11) x13=104fe778 x11:104fe764 PA:104fe774 + 20363500 20348 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe764 PA:104fe770 + 20365500 20350 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20366500 20351 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 20400500 20385 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 20401500 20386 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20402500 20387 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20403500 20388 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20406500 20391 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fe764 PA:104fe770 + 20407500 20392 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 20441500 20426 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 20475500 20460 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20506500 20491 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20507500 20492 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 20510500 20495 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20512500 20497 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 20515500 20500 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 20516500 20501 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104fe778 PA:104fe778 + 20517500 20502 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20518500 20503 1c001a5e 00168693 addi x13, x13, 1 x13=104fe779 x13:104fe778 + 20519500 20504 1c001a60 fb1ff06f jal x0, -80 + 20521500 20506 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20522500 20507 1c001a12 00068023 sb x0, 0(x13) x13:104fe779 PA:104fe779 + 20523500 20508 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20525500 20510 1c001e68 f17ff06f jal x0, -234 + 20527500 20512 1c001d7e 00410613 addi x12, x2, 4 x12=104fe764 x2:104fe760 + 20528500 20513 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20529500 20514 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20530500 20515 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20532500 20517 1c001a62 fe010113 addi x2, x2, -32 x2=104fe740 x2:104fe760 + 20533500 20518 1c001a64 00812c23 sw x8, 24(x2) x8:104fe7e8 x2:104fe740 PA:104fe758 + 20534500 20519 1c001a66 01062783 lw x15, 16(x12) x15=104fe778 x12:104fe764 PA:104fe774 + 20535500 20520 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fe764 PA:104fe768 + 20536500 20521 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104fe740 PA:104fe754 + 20537500 20522 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fe740 PA:104fe750 + 20538500 20523 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fe740 PA:104fe74c + 20539500 20524 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fe740 PA:104fe75c + 20540500 20525 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fe740 PA:104fe748 + 20541500 20526 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20542500 20527 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20543500 20528 1c001a78 00c004b3 add x9, x0, x12 x9=104fe764 x12:104fe764 + 20544500 20529 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104fe779 x15:104fe778 PA:104fe778 + 20546500 20531 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 20547500 20532 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20548500 20533 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fe764 PA:104fe76c + 20550500 20535 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20553500 20538 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 20555500 20540 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20556500 20541 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20559500 20544 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20560500 20545 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20561500 20546 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20564500 20549 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20565500 20550 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20566500 20551 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20567500 20552 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20568500 20553 1c001b36 f71ff06f jal x0, -144 + 20570500 20555 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fe764 PA:104fe76c + 20572500 20557 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20575500 20560 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 20577500 20562 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20578500 20563 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20581500 20566 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 20582500 20567 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20583500 20568 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20584500 20569 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20585500 20570 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fe778 x9:104fe764 PA:104fe774 + 20587500 20572 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104fe779 x20:104fe778 PA:104fe778 + 20589500 20574 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20592500 20577 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20593500 20578 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20595500 20580 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20596500 20581 1c001778 fddff06f jal x0, -36 + 20598500 20583 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20599500 20584 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 20600500 20585 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20601500 20586 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 20602500 20587 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 20603500 20588 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 20604500 20589 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 20605500 20590 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 20606500 20591 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20607500 20592 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104088 + 20611500 20596 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20612500 20597 1c001b62 f8bff06f jal x0, -118 + 20614500 20599 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fe77a x20:104fe779 PA:104fe779 + 20616500 20601 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20617500 20602 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fe764 PA:104fe764 + 20619500 20604 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20620500 20605 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20623500 20608 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fe740 PA:104fe75c + 20624500 20609 1c001b02 01812403 lw x8, 24(x2) x8=104fe7e8 x2:104fe740 PA:104fe758 + 20625500 20610 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104fe740 PA:104fe754 + 20626500 20611 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fe740 PA:104fe750 + 20627500 20612 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fe740 PA:104fe74c + 20628500 20613 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fe740 PA:104fe748 + 20629500 20614 1c001b0c 02010113 addi x2, x2, 32 x2=104fe760 x2:104fe740 + 20630500 20615 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20632500 20617 1c001d86 01800433 add x8, x0, x24 x8=104fe7ec x24:104fe7ec + 20633500 20618 1c001d88 fadff06f jal x0, -84 + 20635500 20620 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20636500 20621 1c001d36 e69ff06f jal x0, -408 + 20639500 20624 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20654500 20639 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20655500 20640 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20658500 20643 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20659500 20644 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20660500 20645 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20662500 20647 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20663500 20648 1c001778 fddff06f jal x0, -36 + 20665500 20650 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20666500 20651 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 20667500 20652 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20668500 20653 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 20669500 20654 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 20670500 20655 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 20671500 20656 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 20672500 20657 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 20673500 20658 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20674500 20659 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104088 + 20678500 20663 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20679500 20664 1c001bca 16a0006f jal x0, 362 + 20681500 20666 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20682500 20667 1c001d36 e69ff06f jal x0, -408 + 20685500 20670 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20699500 20684 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20700500 20685 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20703500 20688 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20704500 20689 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20705500 20690 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20707500 20692 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20708500 20693 1c001778 fddff06f jal x0, -36 + 20710500 20695 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20711500 20696 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 20712500 20697 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20713500 20698 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 20714500 20699 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 20715500 20700 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 20716500 20701 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 20717500 20702 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 20718500 20703 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20719500 20704 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104088 + 20723500 20708 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20724500 20709 1c001bca 16a0006f jal x0, 362 + 20726500 20711 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20727500 20712 1c001d36 e69ff06f jal x0, -408 + 20730500 20715 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20744500 20729 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20745500 20730 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20748500 20733 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20749500 20734 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20750500 20735 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20752500 20737 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20753500 20738 1c001778 fddff06f jal x0, -36 + 20755500 20740 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20756500 20741 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000021 + 20757500 20742 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20758500 20743 1c00175e 00379713 slli x14, x15, 0x3 x14=00000108 x15:00000021 + 20759500 20744 1c001762 00279793 slli x15, x15, 0x2 x15=00000084 x15:00000021 + 20760500 20745 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000108 + 20761500 20746 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000084 x13:00001f80 + 20762500 20747 1c00176a 00e787b3 add x15, x15, x14 x15=00000088 x15:00000080 x14:00000008 + 20763500 20748 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20764500 20749 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104088 + 20768500 20753 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20769500 20754 1c001bca 16a0006f jal x0, 362 + 20771500 20756 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20772500 20757 1c001d36 e69ff06f jal x0, -408 + 20775500 20760 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20793500 20778 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20794500 20779 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20795500 20780 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104fe760 PA:104fe7bc + 20796500 20781 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:104fe760 PA:104fe7b8 + 20797500 20782 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:104fe760 PA:104fe7b4 + 20798500 20783 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:104fe760 PA:104fe7b0 + 20817500 20802 1c001bb0 04c12983 lw x19, 76(x2) x19=00000001 x2:104fe760 PA:104fe7ac + 20820500 20805 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:104fe760 PA:104fe7a8 + 20821500 20806 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:104fe760 PA:104fe7a4 + 20822500 20807 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:104fe760 PA:104fe7a0 + 20823500 20808 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:104fe760 PA:104fe79c + 20824500 20809 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:104fe760 PA:104fe798 + 20825500 20810 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:104fe760 PA:104fe794 + 20826500 20811 1c001bbe 06010113 addi x2, x2, 96 x2=104fe7c0 x2:104fe760 + 20827500 20812 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20829500 20814 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:104fe7c0 PA:104fe7dc + 20830500 20815 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20831500 20816 1c001838 04010113 addi x2, x2, 64 x2=104fe800 x2:104fe7c0 + 20832500 20817 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 20834500 20819 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_2.log b/sw/scripts/tracevis/example/traces/trace_core_01_2.log new file mode 100644 index 0000000..c7a70a0 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_2.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000022 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000002 x10:00000022 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000022 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000002 + 12641500 12626 1c0000a6 05a0206f jal x0, 8282 + 12659500 12644 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12660500 12645 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12661500 12646 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12662500 12647 1c00210c 0e059163 bne x11, x0, 226 x11:00000002 + 12714500 12699 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 12715500 12700 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000022 + 12716500 12701 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000002 x19:00000022 + 12717500 12702 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 12734500 12719 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 12735500 12720 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 12736500 12721 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 12737500 12722 1c00220a 0060006f jal x0, 6 + 12757500 12742 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 17807500 17792 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 17825500 17810 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 17826500 17811 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 17844500 17829 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 17845500 17830 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 17847500 17832 1c00222c 08096283 p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080 + 17871500 17856 1c002230 02a98533 mul x10, x19, x10 x10=00000800 x19:00000002 x10:00000400 + 17872500 17857 1c002234 00550133 add x2, x10, x5 x2=104fec00 x10:00000800 x5:104fe400 + 17873500 17858 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 17875500 17860 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 17911500 17896 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 17919500 17904 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 17920500 17905 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 17921500 17906 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 17922500 17907 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 17940500 17925 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000022 + 17957500 17942 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17958500 17943 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000001 x12:00000022 + 17959500 17944 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001 + 17960500 17945 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000002 x12:00000022 + 17961500 17946 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17962500 17947 1c0009d4 63d0006f jal x0, 3644 + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104febc0 x2:104fec00 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104febc0 PA:104febe4 + 17986500 17971 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17987500 17972 1c001818 02c12423 sw x12, 40(x2) x12:00000002 x2:104febc0 PA:104febe8 + 17988500 17973 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104febc0 PA:104febec + 17989500 17974 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17990500 17975 1c00181e 02410693 addi x13, x2, 36 x13=104febe4 x2:104febc0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:104febc0 PA:104febdc + 18009500 17994 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:104febc0 PA:104febf0 + 18010500 17995 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:104febc0 PA:104febf4 + 18011500 17996 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104febc0 PA:104febf8 + 18012500 17997 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104febc0 PA:104febfc + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104febe4 x2:104febc0 PA:104febcc + 18028500 18013 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104feb60 x2:104febc0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104feb78 x2:104feb60 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:104feb60 PA:104febb8 + 18046500 18031 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:104feb60 PA:104febb0 + 18047500 18032 1c001b78 05312623 sw x19, 76(x2) x19:00000002 x2:104feb60 PA:104febac + 18048500 18033 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:104feb60 PA:104feba8 + 18049500 18034 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:104feb60 PA:104feba4 + 18050500 18035 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:104feb60 PA:104feba0 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:104feb60 PA:104feb9c + 18071500 18056 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104feb60 PA:104febbc + 18072500 18057 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:104feb60 PA:104febb4 + 18073500 18058 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:104feb60 PA:104feb98 + 18074500 18059 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:104feb60 PA:104feb94 + 18075500 18060 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18076500 18061 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18077500 18062 1c001b8e 00d00433 add x8, x0, x13 x8=104febe4 x13:104febe4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104feb78 x2:104feb60 PA:104feb74 + 18091500 18076 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18092500 18077 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18093500 18078 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18094500 18079 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18127500 18112 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18128500 18113 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18145500 18130 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18146500 18131 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18147500 18132 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104090 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18253500 18238 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18254500 18239 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18257500 18242 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18258500 18243 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18259500 18244 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18261500 18246 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18262500 18247 1c001778 fddff06f jal x0, -36 + 18264500 18249 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18265500 18250 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18266500 18251 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18267500 18252 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18268500 18253 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18269500 18254 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18270500 18255 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18271500 18256 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18272500 18257 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18273500 18258 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104090 + 18277500 18262 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18278500 18263 1c001bca 16a0006f jal x0, 362 + 18280500 18265 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18281500 18266 1c001d36 e69ff06f jal x0, -408 + 18284500 18269 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18299500 18284 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18300500 18285 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18303500 18288 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18304500 18289 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18305500 18290 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18307500 18292 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18308500 18293 1c001778 fddff06f jal x0, -36 + 18310500 18295 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18311500 18296 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18312500 18297 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18313500 18298 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18314500 18299 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18315500 18300 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18316500 18301 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18317500 18302 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18318500 18303 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18319500 18304 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104090 + 18323500 18308 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18324500 18309 1c001bca 16a0006f jal x0, 362 + 18326500 18311 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18327500 18312 1c001d36 e69ff06f jal x0, -408 + 18330500 18315 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18345500 18330 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18346500 18331 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18349500 18334 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18350500 18335 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18351500 18336 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18353500 18338 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18354500 18339 1c001778 fddff06f jal x0, -36 + 18356500 18341 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18357500 18342 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18358500 18343 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18359500 18344 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18360500 18345 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18361500 18346 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18362500 18347 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18363500 18348 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18364500 18349 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18365500 18350 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104090 + 18369500 18354 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18370500 18355 1c001bca 16a0006f jal x0, 362 + 18372500 18357 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18373500 18358 1c001d36 e69ff06f jal x0, -408 + 18376500 18361 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18390500 18375 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18391500 18376 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18394500 18379 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18395500 18380 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18396500 18381 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18398500 18383 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18399500 18384 1c001778 fddff06f jal x0, -36 + 18401500 18386 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18402500 18387 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18403500 18388 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18404500 18389 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18405500 18390 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18406500 18391 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18407500 18392 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18408500 18393 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18409500 18394 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18410500 18395 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104090 + 18414500 18399 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18415500 18400 1c001bca 16a0006f jal x0, 362 + 18417500 18402 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18418500 18403 1c001d36 e69ff06f jal x0, -408 + 18421500 18406 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18439500 18424 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18440500 18425 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18443500 18428 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18444500 18429 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18445500 18430 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18447500 18432 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18448500 18433 1c001778 fddff06f jal x0, -36 + 18450500 18435 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18451500 18436 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18452500 18437 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18453500 18438 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18454500 18439 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18455500 18440 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18456500 18441 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18457500 18442 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18458500 18443 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18459500 18444 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104090 + 18463500 18448 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18464500 18449 1c001bca 16a0006f jal x0, 362 + 18466500 18451 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18467500 18452 1c001d36 e69ff06f jal x0, -408 + 18470500 18455 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18484500 18469 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18485500 18470 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18488500 18473 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18489500 18474 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18490500 18475 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18492500 18477 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18493500 18478 1c001778 fddff06f jal x0, -36 + 18495500 18480 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18496500 18481 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18497500 18482 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18498500 18483 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18499500 18484 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18500500 18485 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18501500 18486 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18502500 18487 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18503500 18488 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18504500 18489 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104090 + 18508500 18493 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18509500 18494 1c001bca 16a0006f jal x0, 362 + 18511500 18496 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18512500 18497 1c001d36 e69ff06f jal x0, -408 + 18515500 18500 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18529500 18514 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18530500 18515 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18533500 18518 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18534500 18519 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18535500 18520 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18537500 18522 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18538500 18523 1c001778 fddff06f jal x0, -36 + 18540500 18525 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18541500 18526 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18542500 18527 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18543500 18528 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18544500 18529 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18545500 18530 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18546500 18531 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18547500 18532 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18548500 18533 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18549500 18534 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104090 + 18553500 18538 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18554500 18539 1c001bca 16a0006f jal x0, 362 + 18556500 18541 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18557500 18542 1c001d36 e69ff06f jal x0, -408 + 18560500 18545 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18575500 18560 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18576500 18561 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18579500 18564 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18580500 18565 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18581500 18566 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18583500 18568 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18584500 18569 1c001778 fddff06f jal x0, -36 + 18586500 18571 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18587500 18572 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18588500 18573 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18589500 18574 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18590500 18575 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18591500 18576 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18592500 18577 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18593500 18578 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18594500 18579 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18595500 18580 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104090 + 18599500 18584 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18600500 18585 1c001bca 16a0006f jal x0, 362 + 18602500 18587 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18603500 18588 1c001d36 e69ff06f jal x0, -408 + 18606500 18591 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18620500 18605 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18621500 18606 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18624500 18609 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18625500 18610 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18626500 18611 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18628500 18613 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18629500 18614 1c001778 fddff06f jal x0, -36 + 18631500 18616 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18632500 18617 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18633500 18618 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18634500 18619 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18635500 18620 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18636500 18621 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18637500 18622 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18638500 18623 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18639500 18624 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18640500 18625 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104090 + 18644500 18629 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18645500 18630 1c001bca 16a0006f jal x0, 362 + 18647500 18632 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18648500 18633 1c001d36 e69ff06f jal x0, -408 + 18651500 18636 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18669500 18654 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18670500 18655 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18673500 18658 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18674500 18659 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18675500 18660 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18677500 18662 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18678500 18663 1c001778 fddff06f jal x0, -36 + 18680500 18665 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18681500 18666 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18682500 18667 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18683500 18668 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18684500 18669 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18685500 18670 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18686500 18671 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18687500 18672 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18688500 18673 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18689500 18674 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104090 + 18693500 18678 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18694500 18679 1c001bca 16a0006f jal x0, 362 + 18696500 18681 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18697500 18682 1c001d36 e69ff06f jal x0, -408 + 18700500 18685 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18716500 18701 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18717500 18702 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18720500 18705 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18721500 18706 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18722500 18707 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18724500 18709 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18725500 18710 1c001778 fddff06f jal x0, -36 + 18727500 18712 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18728500 18713 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18729500 18714 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18730500 18715 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18731500 18716 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18732500 18717 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18733500 18718 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18734500 18719 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18735500 18720 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18736500 18721 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104090 + 18740500 18725 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18741500 18726 1c001bca 16a0006f jal x0, 362 + 18743500 18728 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18744500 18729 1c001d36 e69ff06f jal x0, -408 + 18747500 18732 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18761500 18746 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18762500 18747 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18765500 18750 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18766500 18751 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18767500 18752 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18769500 18754 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18770500 18755 1c001778 fddff06f jal x0, -36 + 18772500 18757 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18773500 18758 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18774500 18759 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18775500 18760 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18776500 18761 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18777500 18762 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18778500 18763 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18779500 18764 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18780500 18765 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18781500 18766 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104090 + 18785500 18770 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18786500 18771 1c001bca 16a0006f jal x0, 362 + 18788500 18773 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18789500 18774 1c001d36 e69ff06f jal x0, -408 + 18792500 18777 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18808500 18793 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18809500 18794 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18812500 18797 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18813500 18798 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18814500 18799 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18816500 18801 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18817500 18802 1c001778 fddff06f jal x0, -36 + 18819500 18804 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18820500 18805 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18821500 18806 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18822500 18807 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18823500 18808 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18824500 18809 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18825500 18810 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18826500 18811 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18827500 18812 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18828500 18813 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104090 + 18832500 18817 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18833500 18818 1c001bca 16a0006f jal x0, 362 + 18835500 18820 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18836500 18821 1c001d36 e69ff06f jal x0, -408 + 18839500 18824 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18856500 18841 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18857500 18842 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18860500 18845 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18861500 18846 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18862500 18847 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18864500 18849 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18865500 18850 1c001778 fddff06f jal x0, -36 + 18867500 18852 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18868500 18853 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 18869500 18854 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18870500 18855 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 18871500 18856 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 18872500 18857 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 18873500 18858 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 18874500 18859 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 18875500 18860 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18876500 18861 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104090 + 18880500 18865 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18881500 18866 1c001bca 16a0006f jal x0, 362 + 18883500 18868 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18884500 18869 1c001d36 e69ff06f jal x0, -408 + 18887500 18872 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18903500 18888 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18904500 18889 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18907500 18892 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18910500 18895 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104feb60 PA:104feb64 + 18929500 18914 1c001bd0 00012423 sw x0, 8(x2) x2:104feb60 PA:104feb68 + 18930500 18915 1c001bd2 00010623 sb x0, 12(x2) x2:104feb60 PA:104feb6c + 18931500 18916 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18932500 18917 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104feb60 PA:104feb64 + 18957500 18942 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18958500 18943 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18959500 18944 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18960500 18945 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18961500 18946 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 18999500 18984 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19000500 18985 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19021500 19006 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19022500 19007 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19023500 19008 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104feb60 PA:104feb70 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104febe8 x8:104febe4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104febe4 PA:104febe4 + 19401500 19386 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104feb64 x2:104feb60 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104feb78 x11:104feb64 PA:104feb74 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104feb64 PA:104feb70 + 19529500 19514 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19530500 19515 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19564500 19549 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19565500 19550 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19566500 19551 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19567500 19552 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19570500 19555 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104feb64 PA:104feb70 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104feb78 PA:104feb78 + 19743500 19728 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19744500 19729 1c001a5e 00168693 addi x13, x13, 1 x13=104feb79 x13:104feb78 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104feb79 PA:104feb79 + 19764500 19749 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19766500 19751 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104feb64 x2:104feb60 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104feb40 x2:104feb60 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104febe4 x2:104feb40 PA:104feb58 + 19815500 19800 1c001a66 01062783 lw x15, 16(x12) x15=104feb78 x12:104feb64 PA:104feb74 + 19816500 19801 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104feb64 PA:104feb68 + 19817500 19802 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104feb40 PA:104feb54 + 19818500 19803 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104feb40 PA:104feb50 + 19819500 19804 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104feb40 PA:104feb4c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104feb40 PA:104feb5c + 19838500 19823 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104feb40 PA:104feb48 + 19839500 19824 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19840500 19825 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19841500 19826 1c001a78 00c004b3 add x9, x0, x12 x9=104feb64 x12:104feb64 + 19842500 19827 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104feb79 x15:104feb78 PA:104feb78 + 19844500 19829 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104feb64 PA:104feb6c + 19871500 19856 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19874500 19859 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104feb64 PA:104feb6c + 19957500 19942 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 19979500 19964 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19980500 19965 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104feb78 x9:104feb64 PA:104feb74 + 20023500 20008 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104feb79 x20:104feb78 PA:104feb78 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104090 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104feb7a x20:104feb79 PA:104feb79 + 20100500 20085 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20101500 20086 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 20103500 20088 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20104500 20089 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104feb40 PA:104feb5c + 20125500 20110 1c001b02 01812403 lw x8, 24(x2) x8=104febe4 x2:104feb40 PA:104feb58 + 20126500 20111 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104feb40 PA:104feb54 + 20127500 20112 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104feb40 PA:104feb50 + 20128500 20113 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104feb40 PA:104feb4c + 20129500 20114 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104feb40 PA:104feb48 + 20130500 20115 1c001b0c 02010113 addi x2, x2, 32 x2=104feb60 x2:104feb40 + 20131500 20116 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104febe8 x24:104febe8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20178500 20163 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20179500 20164 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20182500 20167 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20183500 20168 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20184500 20169 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20186500 20171 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20187500 20172 1c001778 fddff06f jal x0, -36 + 20189500 20174 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20190500 20175 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 20191500 20176 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20192500 20177 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 20193500 20178 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 20194500 20179 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 20195500 20180 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 20196500 20181 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 20197500 20182 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20198500 20183 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104090 + 20202500 20187 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20203500 20188 1c001bca 16a0006f jal x0, 362 + 20205500 20190 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20206500 20191 1c001d36 e69ff06f jal x0, -408 + 20209500 20194 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20225500 20210 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20226500 20211 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20229500 20214 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20230500 20215 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20231500 20216 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20233500 20218 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20234500 20219 1c001778 fddff06f jal x0, -36 + 20236500 20221 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20237500 20222 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 20238500 20223 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20239500 20224 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 20240500 20225 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 20241500 20226 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 20242500 20227 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 20243500 20228 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 20244500 20229 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20245500 20230 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104090 + 20249500 20234 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20250500 20235 1c001bca 16a0006f jal x0, 362 + 20252500 20237 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20253500 20238 1c001d36 e69ff06f jal x0, -408 + 20256500 20241 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20271500 20256 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20272500 20257 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20275500 20260 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20278500 20263 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104feb60 PA:104feb64 + 20279500 20264 1c001bd0 00012423 sw x0, 8(x2) x2:104feb60 PA:104feb68 + 20280500 20265 1c001bd2 00010623 sb x0, 12(x2) x2:104feb60 PA:104feb6c + 20281500 20266 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20282500 20267 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20283500 20268 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20284500 20269 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104feb60 PA:104feb64 + 20286500 20271 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20287500 20272 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20288500 20273 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20289500 20274 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20290500 20275 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20291500 20276 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20292500 20277 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20293500 20278 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20308500 20293 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20309500 20294 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20312500 20297 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20313500 20298 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20314500 20299 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20317500 20302 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20320500 20305 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20323500 20308 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20326500 20311 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20327500 20312 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20328500 20313 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20329500 20314 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20332500 20317 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20333500 20318 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20336500 20321 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20337500 20322 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20340500 20325 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20342500 20327 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20345500 20330 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20346500 20331 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20349500 20334 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20350500 20335 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20351500 20336 1c001f42 e09ff06f jal x0, -504 + 20353500 20338 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20354500 20339 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104feb60 PA:104feb70 + 20355500 20340 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20358500 20343 1c001e34 00440c13 addi x24, x8, 4 x24=104febec x8:104febe8 + 20359500 20344 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:104febe8 PA:104febe8 + 20360500 20345 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20363500 20348 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20366500 20351 1c001e64 00410593 addi x11, x2, 4 x11=104feb64 x2:104feb60 + 20367500 20352 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20369500 20354 1c0019fe 0105a683 lw x13, 16(x11) x13=104feb78 x11:104feb64 PA:104feb74 + 20370500 20355 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104feb64 PA:104feb70 + 20371500 20356 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20372500 20357 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20406500 20391 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20407500 20392 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20408500 20393 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20409500 20394 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20412500 20397 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104feb64 PA:104feb70 + 20413500 20398 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20447500 20432 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20481500 20466 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20512500 20497 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20513500 20498 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20516500 20501 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20518500 20503 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20521500 20506 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20522500 20507 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:104feb78 PA:104feb78 + 20524500 20509 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20525500 20510 1c001a5e 00168693 addi x13, x13, 1 x13=104feb79 x13:104feb78 + 20526500 20511 1c001a60 fb1ff06f jal x0, -80 + 20528500 20513 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20529500 20514 1c001a12 00068023 sb x0, 0(x13) x13:104feb79 PA:104feb79 + 20530500 20515 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20532500 20517 1c001e68 f17ff06f jal x0, -234 + 20534500 20519 1c001d7e 00410613 addi x12, x2, 4 x12=104feb64 x2:104feb60 + 20535500 20520 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20536500 20521 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20537500 20522 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20539500 20524 1c001a62 fe010113 addi x2, x2, -32 x2=104feb40 x2:104feb60 + 20540500 20525 1c001a64 00812c23 sw x8, 24(x2) x8:104febe8 x2:104feb40 PA:104feb58 + 20541500 20526 1c001a66 01062783 lw x15, 16(x12) x15=104feb78 x12:104feb64 PA:104feb74 + 20542500 20527 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104feb64 PA:104feb68 + 20543500 20528 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104feb40 PA:104feb54 + 20544500 20529 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104feb40 PA:104feb50 + 20545500 20530 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104feb40 PA:104feb4c + 20546500 20531 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104feb40 PA:104feb5c + 20547500 20532 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104feb40 PA:104feb48 + 20548500 20533 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20549500 20534 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20550500 20535 1c001a78 00c004b3 add x9, x0, x12 x9=104feb64 x12:104feb64 + 20551500 20536 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=104feb79 x15:104feb78 PA:104feb78 + 20553500 20538 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20554500 20539 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20555500 20540 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104feb64 PA:104feb6c + 20557500 20542 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20560500 20545 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 20562500 20547 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20563500 20548 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20566500 20551 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20567500 20552 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20568500 20553 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20571500 20556 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20572500 20557 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20573500 20558 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20574500 20559 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20575500 20560 1c001b36 f71ff06f jal x0, -144 + 20577500 20562 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104feb64 PA:104feb6c + 20579500 20564 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20582500 20567 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 20584500 20569 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20585500 20570 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20588500 20573 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 20589500 20574 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20590500 20575 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20591500 20576 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20592500 20577 1c001ae8 0104aa03 lw x20, 16(x9) x20=104feb78 x9:104feb64 PA:104feb74 + 20594500 20579 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=104feb79 x20:104feb78 PA:104feb78 + 20596500 20581 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20599500 20584 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20600500 20585 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20602500 20587 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20603500 20588 1c001778 fddff06f jal x0, -36 + 20605500 20590 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20606500 20591 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 20607500 20592 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20608500 20593 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 20609500 20594 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 20610500 20595 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 20611500 20596 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 20612500 20597 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 20613500 20598 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20614500 20599 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104090 + 20618500 20603 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20619500 20604 1c001b62 f8bff06f jal x0, -118 + 20621500 20606 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104feb7a x20:104feb79 PA:104feb79 + 20623500 20608 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20624500 20609 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104feb64 PA:104feb64 + 20626500 20611 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20627500 20612 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20630500 20615 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104feb40 PA:104feb5c + 20631500 20616 1c001b02 01812403 lw x8, 24(x2) x8=104febe8 x2:104feb40 PA:104feb58 + 20632500 20617 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104feb40 PA:104feb54 + 20633500 20618 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104feb40 PA:104feb50 + 20634500 20619 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104feb40 PA:104feb4c + 20635500 20620 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104feb40 PA:104feb48 + 20636500 20621 1c001b0c 02010113 addi x2, x2, 32 x2=104feb60 x2:104feb40 + 20637500 20622 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20639500 20624 1c001d86 01800433 add x8, x0, x24 x8=104febec x24:104febec + 20640500 20625 1c001d88 fadff06f jal x0, -84 + 20642500 20627 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20643500 20628 1c001d36 e69ff06f jal x0, -408 + 20646500 20631 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20666500 20651 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20667500 20652 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20670500 20655 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20671500 20656 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20672500 20657 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20674500 20659 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20675500 20660 1c001778 fddff06f jal x0, -36 + 20677500 20662 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20678500 20663 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 20679500 20664 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20680500 20665 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 20681500 20666 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 20682500 20667 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 20683500 20668 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 20684500 20669 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 20685500 20670 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20686500 20671 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104090 + 20690500 20675 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20691500 20676 1c001bca 16a0006f jal x0, 362 + 20693500 20678 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20694500 20679 1c001d36 e69ff06f jal x0, -408 + 20697500 20682 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20711500 20696 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20712500 20697 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20715500 20700 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20716500 20701 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20717500 20702 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20719500 20704 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20720500 20705 1c001778 fddff06f jal x0, -36 + 20722500 20707 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20723500 20708 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 20724500 20709 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20725500 20710 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 20726500 20711 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 20727500 20712 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 20728500 20713 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 20729500 20714 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 20730500 20715 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20731500 20716 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104090 + 20735500 20720 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20736500 20721 1c001bca 16a0006f jal x0, 362 + 20738500 20723 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20739500 20724 1c001d36 e69ff06f jal x0, -408 + 20742500 20727 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20759500 20744 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20760500 20745 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20763500 20748 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20764500 20749 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20765500 20750 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20767500 20752 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20768500 20753 1c001778 fddff06f jal x0, -36 + 20770500 20755 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20771500 20756 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000022 + 20772500 20757 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20773500 20758 1c00175e 00379713 slli x14, x15, 0x3 x14=00000110 x15:00000022 + 20774500 20759 1c001762 00279793 slli x15, x15, 0x2 x15=00000088 x15:00000022 + 20775500 20760 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000110 + 20776500 20761 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000088 x13:00001f80 + 20777500 20762 1c00176a 00e787b3 add x15, x15, x14 x15=00000090 x15:00000080 x14:00000010 + 20778500 20763 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20779500 20764 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104090 + 20783500 20768 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20784500 20769 1c001bca 16a0006f jal x0, 362 + 20786500 20771 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20787500 20772 1c001d36 e69ff06f jal x0, -408 + 20790500 20775 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20805500 20790 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20806500 20791 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20807500 20792 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104feb60 PA:104febbc + 20808500 20793 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:104feb60 PA:104febb8 + 20809500 20794 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:104feb60 PA:104febb4 + 20810500 20795 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:104feb60 PA:104febb0 + 20817500 20802 1c001bb0 04c12983 lw x19, 76(x2) x19=00000002 x2:104feb60 PA:104febac + 20818500 20803 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:104feb60 PA:104feba8 + 20819500 20804 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:104feb60 PA:104feba4 + 20820500 20805 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:104feb60 PA:104feba0 + 20821500 20806 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:104feb60 PA:104feb9c + 20822500 20807 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:104feb60 PA:104feb98 + 20823500 20808 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:104feb60 PA:104feb94 + 20824500 20809 1c001bbe 06010113 addi x2, x2, 96 x2=104febc0 x2:104feb60 + 20825500 20810 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20827500 20812 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:104febc0 PA:104febdc + 20828500 20813 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20829500 20814 1c001838 04010113 addi x2, x2, 64 x2=104fec00 x2:104febc0 + 20830500 20815 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 20832500 20817 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_3.log b/sw/scripts/tracevis/example/traces/trace_core_01_3.log new file mode 100644 index 0000000..922c3bd --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_3.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000023 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000003 x10:00000023 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000023 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000003 + 12641500 12626 1c0000a6 05a0206f jal x0, 8282 + 12659500 12644 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12660500 12645 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12661500 12646 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12662500 12647 1c00210c 0e059163 bne x11, x0, 226 x11:00000003 + 12714500 12699 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 12715500 12700 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000023 + 12716500 12701 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000003 x19:00000023 + 12717500 12702 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 12734500 12719 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 12735500 12720 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 12736500 12721 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 12737500 12722 1c00220a 0060006f jal x0, 6 + 12757500 12742 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 17807500 17792 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 17825500 17810 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 17826500 17811 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 17844500 17829 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 17845500 17830 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 17847500 17832 1c00222c 08096283 p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080 + 17871500 17856 1c002230 02a98533 mul x10, x19, x10 x10=00000c00 x19:00000003 x10:00000400 + 17872500 17857 1c002234 00550133 add x2, x10, x5 x2=104ff000 x10:00000c00 x5:104fe400 + 17873500 17858 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 17875500 17860 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 17911500 17896 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 17919500 17904 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 17920500 17905 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 17921500 17906 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 17922500 17907 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 17940500 17925 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000023 + 17957500 17942 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17958500 17943 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000001 x12:00000023 + 17959500 17944 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001 + 17960500 17945 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000003 x12:00000023 + 17961500 17946 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17962500 17947 1c0009d4 63d0006f jal x0, 3644 + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104fefc0 x2:104ff000 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104fefc0 PA:104fefe4 + 17982500 17967 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17983500 17968 1c001818 02c12423 sw x12, 40(x2) x12:00000003 x2:104fefc0 PA:104fefe8 + 17984500 17969 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104fefc0 PA:104fefec + 17985500 17970 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17986500 17971 1c00181e 02410693 addi x13, x2, 36 x13=104fefe4 x2:104fefc0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:104fefc0 PA:104fefdc + 18008500 17993 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:104fefc0 PA:104feff0 + 18009500 17994 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:104fefc0 PA:104feff4 + 18010500 17995 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104fefc0 PA:104feff8 + 18011500 17996 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104fefc0 PA:104feffc + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104fefe4 x2:104fefc0 PA:104fefcc + 18027500 18012 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104fef60 x2:104fefc0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104fef78 x2:104fef60 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:104fef60 PA:104fefb8 + 18047500 18032 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:104fef60 PA:104fefb0 + 18048500 18033 1c001b78 05312623 sw x19, 76(x2) x19:00000003 x2:104fef60 PA:104fefac + 18049500 18034 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:104fef60 PA:104fefa8 + 18050500 18035 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:104fef60 PA:104fefa4 + 18051500 18036 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:104fef60 PA:104fefa0 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:104fef60 PA:104fef9c + 18070500 18055 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104fef60 PA:104fefbc + 18071500 18056 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:104fef60 PA:104fefb4 + 18072500 18057 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:104fef60 PA:104fef98 + 18073500 18058 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:104fef60 PA:104fef94 + 18074500 18059 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18075500 18060 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18076500 18061 1c001b8e 00d00433 add x8, x0, x13 x8=104fefe4 x13:104fefe4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104fef78 x2:104fef60 PA:104fef74 + 18092500 18077 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18093500 18078 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18094500 18079 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18095500 18080 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18129500 18114 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18130500 18115 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18145500 18130 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18146500 18131 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18147500 18132 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104098 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18255500 18240 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18256500 18241 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18259500 18244 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18260500 18245 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18261500 18246 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18263500 18248 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18264500 18249 1c001778 fddff06f jal x0, -36 + 18266500 18251 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18267500 18252 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18268500 18253 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18269500 18254 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18270500 18255 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18271500 18256 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18272500 18257 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18273500 18258 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18274500 18259 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18275500 18260 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104098 + 18279500 18264 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18280500 18265 1c001bca 16a0006f jal x0, 362 + 18282500 18267 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18283500 18268 1c001d36 e69ff06f jal x0, -408 + 18286500 18271 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18305500 18290 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18306500 18291 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18309500 18294 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18310500 18295 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18311500 18296 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18313500 18298 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18314500 18299 1c001778 fddff06f jal x0, -36 + 18316500 18301 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18317500 18302 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18318500 18303 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18319500 18304 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18320500 18305 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18321500 18306 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18322500 18307 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18323500 18308 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18324500 18309 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18325500 18310 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104098 + 18329500 18314 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18330500 18315 1c001bca 16a0006f jal x0, 362 + 18332500 18317 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18333500 18318 1c001d36 e69ff06f jal x0, -408 + 18336500 18321 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18353500 18338 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18354500 18339 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18357500 18342 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18358500 18343 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18359500 18344 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18361500 18346 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18362500 18347 1c001778 fddff06f jal x0, -36 + 18364500 18349 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18365500 18350 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18366500 18351 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18367500 18352 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18368500 18353 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18369500 18354 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18370500 18355 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18371500 18356 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18372500 18357 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18373500 18358 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104098 + 18377500 18362 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18378500 18363 1c001bca 16a0006f jal x0, 362 + 18380500 18365 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18381500 18366 1c001d36 e69ff06f jal x0, -408 + 18384500 18369 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18398500 18383 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18399500 18384 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18402500 18387 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18403500 18388 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18404500 18389 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18406500 18391 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18407500 18392 1c001778 fddff06f jal x0, -36 + 18409500 18394 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18410500 18395 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18411500 18396 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18412500 18397 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18413500 18398 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18414500 18399 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18415500 18400 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18416500 18401 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18417500 18402 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18418500 18403 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104098 + 18422500 18407 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18423500 18408 1c001bca 16a0006f jal x0, 362 + 18425500 18410 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18426500 18411 1c001d36 e69ff06f jal x0, -408 + 18429500 18414 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18443500 18428 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18444500 18429 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18447500 18432 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18448500 18433 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18449500 18434 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18451500 18436 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18452500 18437 1c001778 fddff06f jal x0, -36 + 18454500 18439 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18455500 18440 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18456500 18441 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18457500 18442 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18458500 18443 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18459500 18444 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18460500 18445 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18461500 18446 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18462500 18447 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18463500 18448 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104098 + 18467500 18452 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18468500 18453 1c001bca 16a0006f jal x0, 362 + 18470500 18455 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18471500 18456 1c001d36 e69ff06f jal x0, -408 + 18474500 18459 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18488500 18473 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18489500 18474 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18492500 18477 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18493500 18478 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18494500 18479 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18496500 18481 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18497500 18482 1c001778 fddff06f jal x0, -36 + 18499500 18484 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18500500 18485 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18501500 18486 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18502500 18487 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18503500 18488 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18504500 18489 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18505500 18490 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18506500 18491 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18507500 18492 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18508500 18493 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104098 + 18512500 18497 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18513500 18498 1c001bca 16a0006f jal x0, 362 + 18515500 18500 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18516500 18501 1c001d36 e69ff06f jal x0, -408 + 18519500 18504 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18533500 18518 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18534500 18519 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18537500 18522 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18538500 18523 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18539500 18524 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18541500 18526 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18542500 18527 1c001778 fddff06f jal x0, -36 + 18544500 18529 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18545500 18530 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18546500 18531 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18547500 18532 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18548500 18533 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18549500 18534 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18550500 18535 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18551500 18536 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18552500 18537 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18553500 18538 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104098 + 18557500 18542 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18558500 18543 1c001bca 16a0006f jal x0, 362 + 18560500 18545 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18561500 18546 1c001d36 e69ff06f jal x0, -408 + 18564500 18549 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18578500 18563 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18579500 18564 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18582500 18567 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18583500 18568 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18584500 18569 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18586500 18571 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18587500 18572 1c001778 fddff06f jal x0, -36 + 18589500 18574 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18590500 18575 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18591500 18576 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18592500 18577 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18593500 18578 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18594500 18579 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18595500 18580 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18596500 18581 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18597500 18582 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18598500 18583 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104098 + 18602500 18587 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18603500 18588 1c001bca 16a0006f jal x0, 362 + 18605500 18590 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18606500 18591 1c001d36 e69ff06f jal x0, -408 + 18609500 18594 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18623500 18608 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18624500 18609 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18627500 18612 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18628500 18613 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18629500 18614 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18631500 18616 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18632500 18617 1c001778 fddff06f jal x0, -36 + 18634500 18619 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18635500 18620 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18636500 18621 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18637500 18622 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18638500 18623 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18639500 18624 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18640500 18625 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18641500 18626 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18642500 18627 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18643500 18628 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104098 + 18647500 18632 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18648500 18633 1c001bca 16a0006f jal x0, 362 + 18650500 18635 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18651500 18636 1c001d36 e69ff06f jal x0, -408 + 18654500 18639 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18673500 18658 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18674500 18659 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18677500 18662 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18678500 18663 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18679500 18664 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18681500 18666 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18682500 18667 1c001778 fddff06f jal x0, -36 + 18684500 18669 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18685500 18670 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18686500 18671 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18687500 18672 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18688500 18673 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18689500 18674 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18690500 18675 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18691500 18676 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18692500 18677 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18693500 18678 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104098 + 18697500 18682 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18698500 18683 1c001bca 16a0006f jal x0, 362 + 18700500 18685 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18701500 18686 1c001d36 e69ff06f jal x0, -408 + 18704500 18689 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18720500 18705 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18721500 18706 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18724500 18709 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18725500 18710 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18726500 18711 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18728500 18713 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18729500 18714 1c001778 fddff06f jal x0, -36 + 18731500 18716 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18732500 18717 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18733500 18718 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18734500 18719 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18735500 18720 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18736500 18721 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18737500 18722 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18738500 18723 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18739500 18724 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18740500 18725 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104098 + 18744500 18729 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18745500 18730 1c001bca 16a0006f jal x0, 362 + 18747500 18732 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18748500 18733 1c001d36 e69ff06f jal x0, -408 + 18751500 18736 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18767500 18752 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18768500 18753 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18771500 18756 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18772500 18757 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18773500 18758 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18775500 18760 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18776500 18761 1c001778 fddff06f jal x0, -36 + 18778500 18763 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18779500 18764 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18780500 18765 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18781500 18766 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18782500 18767 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18783500 18768 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18784500 18769 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18785500 18770 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18786500 18771 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18787500 18772 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104098 + 18791500 18776 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18792500 18777 1c001bca 16a0006f jal x0, 362 + 18794500 18779 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18795500 18780 1c001d36 e69ff06f jal x0, -408 + 18798500 18783 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18812500 18797 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18813500 18798 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18816500 18801 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18817500 18802 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18818500 18803 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18820500 18805 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18821500 18806 1c001778 fddff06f jal x0, -36 + 18823500 18808 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18824500 18809 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18825500 18810 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18826500 18811 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18827500 18812 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18828500 18813 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18829500 18814 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18830500 18815 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18831500 18816 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18832500 18817 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104098 + 18836500 18821 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18837500 18822 1c001bca 16a0006f jal x0, 362 + 18839500 18824 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18840500 18825 1c001d36 e69ff06f jal x0, -408 + 18843500 18828 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18862500 18847 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18863500 18848 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18866500 18851 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18867500 18852 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18868500 18853 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18870500 18855 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18871500 18856 1c001778 fddff06f jal x0, -36 + 18873500 18858 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18874500 18859 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 18875500 18860 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18876500 18861 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 18877500 18862 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 18878500 18863 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 18879500 18864 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 18880500 18865 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 18881500 18866 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18882500 18867 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104098 + 18886500 18871 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18887500 18872 1c001bca 16a0006f jal x0, 362 + 18889500 18874 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18890500 18875 1c001d36 e69ff06f jal x0, -408 + 18893500 18878 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18907500 18892 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18908500 18893 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18911500 18896 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18914500 18899 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104fef60 PA:104fef64 + 18929500 18914 1c001bd0 00012423 sw x0, 8(x2) x2:104fef60 PA:104fef68 + 18931500 18916 1c001bd2 00010623 sb x0, 12(x2) x2:104fef60 PA:104fef6c + 18932500 18917 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18933500 18918 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fef60 PA:104fef64 + 18956500 18941 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18957500 18942 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18958500 18943 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18959500 18944 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18960500 18945 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19011500 18996 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19012500 18997 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19021500 19006 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19022500 19007 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19023500 19008 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fef60 PA:104fef70 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104fefe8 x8:104fefe4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104fefe4 PA:104fefe4 + 19400500 19385 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104fef64 x2:104fef60 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104fef78 x11:104fef64 PA:104fef74 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fef64 PA:104fef70 + 19530500 19515 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19531500 19516 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19565500 19550 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19566500 19551 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19567500 19552 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19568500 19553 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19571500 19556 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fef64 PA:104fef70 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104fef78 PA:104fef78 + 19744500 19729 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19745500 19730 1c001a5e 00168693 addi x13, x13, 1 x13=104fef79 x13:104fef78 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104fef79 PA:104fef79 + 19765500 19750 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19766500 19751 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104fef64 x2:104fef60 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104fef40 x2:104fef60 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104fefe4 x2:104fef40 PA:104fef58 + 19816500 19801 1c001a66 01062783 lw x15, 16(x12) x15=104fef78 x12:104fef64 PA:104fef74 + 19817500 19802 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fef64 PA:104fef68 + 19818500 19803 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104fef40 PA:104fef54 + 19819500 19804 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fef40 PA:104fef50 + 19820500 19805 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fef40 PA:104fef4c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fef40 PA:104fef5c + 19837500 19822 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fef40 PA:104fef48 + 19838500 19823 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19839500 19824 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19840500 19825 1c001a78 00c004b3 add x9, x0, x12 x9=104fef64 x12:104fef64 + 19841500 19826 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104fef79 x15:104fef78 PA:104fef78 + 19843500 19828 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fef64 PA:104fef6c + 19865500 19850 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19868500 19853 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fef64 PA:104fef6c + 19958500 19943 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 19980500 19965 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19981500 19966 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fef78 x9:104fef64 PA:104fef74 + 20024500 20009 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104fef79 x20:104fef78 PA:104fef78 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104098 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fef7a x20:104fef79 PA:104fef79 + 20101500 20086 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20102500 20087 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 20104500 20089 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20105500 20090 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fef40 PA:104fef5c + 20126500 20111 1c001b02 01812403 lw x8, 24(x2) x8=104fefe4 x2:104fef40 PA:104fef58 + 20127500 20112 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104fef40 PA:104fef54 + 20128500 20113 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fef40 PA:104fef50 + 20129500 20114 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fef40 PA:104fef4c + 20130500 20115 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fef40 PA:104fef48 + 20131500 20116 1c001b0c 02010113 addi x2, x2, 32 x2=104fef60 x2:104fef40 + 20132500 20117 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104fefe8 x24:104fefe8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20180500 20165 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20181500 20166 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20184500 20169 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20185500 20170 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20186500 20171 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20188500 20173 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20189500 20174 1c001778 fddff06f jal x0, -36 + 20191500 20176 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20192500 20177 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 20193500 20178 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20194500 20179 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 20195500 20180 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 20196500 20181 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 20197500 20182 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 20198500 20183 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 20199500 20184 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20200500 20185 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104098 + 20204500 20189 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20205500 20190 1c001bca 16a0006f jal x0, 362 + 20207500 20192 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20208500 20193 1c001d36 e69ff06f jal x0, -408 + 20211500 20196 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20230500 20215 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20231500 20216 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20234500 20219 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20235500 20220 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20236500 20221 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20238500 20223 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20239500 20224 1c001778 fddff06f jal x0, -36 + 20241500 20226 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20242500 20227 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 20243500 20228 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20244500 20229 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 20245500 20230 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 20246500 20231 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 20247500 20232 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 20248500 20233 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 20249500 20234 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20250500 20235 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104098 + 20254500 20239 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20255500 20240 1c001bca 16a0006f jal x0, 362 + 20257500 20242 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20258500 20243 1c001d36 e69ff06f jal x0, -408 + 20261500 20246 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20277500 20262 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20278500 20263 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20281500 20266 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20284500 20269 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104fef60 PA:104fef64 + 20285500 20270 1c001bd0 00012423 sw x0, 8(x2) x2:104fef60 PA:104fef68 + 20286500 20271 1c001bd2 00010623 sb x0, 12(x2) x2:104fef60 PA:104fef6c + 20287500 20272 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20288500 20273 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20289500 20274 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20290500 20275 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fef60 PA:104fef64 + 20291500 20276 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20292500 20277 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20293500 20278 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20294500 20279 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20295500 20280 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20296500 20281 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20297500 20282 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20298500 20283 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20313500 20298 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20314500 20299 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20317500 20302 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20318500 20303 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20319500 20304 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20322500 20307 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20325500 20310 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20328500 20313 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20331500 20316 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20332500 20317 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20333500 20318 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20334500 20319 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20337500 20322 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20338500 20323 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20341500 20326 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20342500 20327 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20345500 20330 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20347500 20332 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20350500 20335 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20351500 20336 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20354500 20339 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20355500 20340 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20356500 20341 1c001f42 e09ff06f jal x0, -504 + 20358500 20343 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20359500 20344 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fef60 PA:104fef70 + 20360500 20345 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20363500 20348 1c001e34 00440c13 addi x24, x8, 4 x24=104fefec x8:104fefe8 + 20364500 20349 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:104fefe8 PA:104fefe8 + 20365500 20350 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20368500 20353 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20371500 20356 1c001e64 00410593 addi x11, x2, 4 x11=104fef64 x2:104fef60 + 20372500 20357 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20374500 20359 1c0019fe 0105a683 lw x13, 16(x11) x13=104fef78 x11:104fef64 PA:104fef74 + 20375500 20360 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fef64 PA:104fef70 + 20376500 20361 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20377500 20362 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20411500 20396 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20412500 20397 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20413500 20398 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20414500 20399 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20417500 20402 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fef64 PA:104fef70 + 20418500 20403 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20452500 20437 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20486500 20471 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20517500 20502 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20518500 20503 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20521500 20506 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20523500 20508 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20526500 20511 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20527500 20512 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:104fef78 PA:104fef78 + 20528500 20513 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20529500 20514 1c001a5e 00168693 addi x13, x13, 1 x13=104fef79 x13:104fef78 + 20530500 20515 1c001a60 fb1ff06f jal x0, -80 + 20532500 20517 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20533500 20518 1c001a12 00068023 sb x0, 0(x13) x13:104fef79 PA:104fef79 + 20534500 20519 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20536500 20521 1c001e68 f17ff06f jal x0, -234 + 20538500 20523 1c001d7e 00410613 addi x12, x2, 4 x12=104fef64 x2:104fef60 + 20539500 20524 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20540500 20525 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20541500 20526 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20543500 20528 1c001a62 fe010113 addi x2, x2, -32 x2=104fef40 x2:104fef60 + 20544500 20529 1c001a64 00812c23 sw x8, 24(x2) x8:104fefe8 x2:104fef40 PA:104fef58 + 20545500 20530 1c001a66 01062783 lw x15, 16(x12) x15=104fef78 x12:104fef64 PA:104fef74 + 20546500 20531 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fef64 PA:104fef68 + 20547500 20532 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104fef40 PA:104fef54 + 20548500 20533 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fef40 PA:104fef50 + 20549500 20534 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fef40 PA:104fef4c + 20550500 20535 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fef40 PA:104fef5c + 20551500 20536 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fef40 PA:104fef48 + 20552500 20537 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20553500 20538 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20554500 20539 1c001a78 00c004b3 add x9, x0, x12 x9=104fef64 x12:104fef64 + 20555500 20540 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=104fef79 x15:104fef78 PA:104fef78 + 20557500 20542 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20558500 20543 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20559500 20544 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fef64 PA:104fef6c + 20561500 20546 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20564500 20549 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 20566500 20551 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20567500 20552 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20570500 20555 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20571500 20556 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20572500 20557 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20575500 20560 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20576500 20561 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20577500 20562 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20578500 20563 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20579500 20564 1c001b36 f71ff06f jal x0, -144 + 20581500 20566 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fef64 PA:104fef6c + 20583500 20568 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20586500 20571 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 20588500 20573 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20589500 20574 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20592500 20577 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 20593500 20578 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20594500 20579 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20595500 20580 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20596500 20581 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fef78 x9:104fef64 PA:104fef74 + 20598500 20583 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=104fef79 x20:104fef78 PA:104fef78 + 20600500 20585 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 20603500 20588 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20604500 20589 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20606500 20591 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 20607500 20592 1c001778 fddff06f jal x0, -36 + 20609500 20594 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20610500 20595 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 20611500 20596 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20612500 20597 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 20613500 20598 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 20614500 20599 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 20615500 20600 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 20616500 20601 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 20617500 20602 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20618500 20603 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104098 + 20622500 20607 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20623500 20608 1c001b62 f8bff06f jal x0, -118 + 20625500 20610 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fef7a x20:104fef79 PA:104fef79 + 20627500 20612 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20628500 20613 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fef64 PA:104fef64 + 20630500 20615 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20631500 20616 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20634500 20619 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fef40 PA:104fef5c + 20635500 20620 1c001b02 01812403 lw x8, 24(x2) x8=104fefe8 x2:104fef40 PA:104fef58 + 20636500 20621 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104fef40 PA:104fef54 + 20637500 20622 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fef40 PA:104fef50 + 20638500 20623 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fef40 PA:104fef4c + 20639500 20624 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fef40 PA:104fef48 + 20640500 20625 1c001b0c 02010113 addi x2, x2, 32 x2=104fef60 x2:104fef40 + 20641500 20626 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20643500 20628 1c001d86 01800433 add x8, x0, x24 x8=104fefec x24:104fefec + 20644500 20629 1c001d88 fadff06f jal x0, -84 + 20646500 20631 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20647500 20632 1c001d36 e69ff06f jal x0, -408 + 20650500 20635 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20672500 20657 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20673500 20658 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20676500 20661 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20677500 20662 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20678500 20663 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20680500 20665 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20681500 20666 1c001778 fddff06f jal x0, -36 + 20683500 20668 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20684500 20669 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 20685500 20670 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20686500 20671 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 20687500 20672 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 20688500 20673 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 20689500 20674 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 20690500 20675 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 20691500 20676 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20692500 20677 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104098 + 20696500 20681 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20697500 20682 1c001bca 16a0006f jal x0, 362 + 20699500 20684 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20700500 20685 1c001d36 e69ff06f jal x0, -408 + 20703500 20688 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20719500 20704 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20720500 20705 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20723500 20708 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20724500 20709 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20725500 20710 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20727500 20712 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20728500 20713 1c001778 fddff06f jal x0, -36 + 20730500 20715 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20731500 20716 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 20732500 20717 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20733500 20718 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 20734500 20719 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 20735500 20720 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 20736500 20721 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 20737500 20722 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 20738500 20723 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20739500 20724 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104098 + 20743500 20728 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20744500 20729 1c001bca 16a0006f jal x0, 362 + 20746500 20731 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20747500 20732 1c001d36 e69ff06f jal x0, -408 + 20750500 20735 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20764500 20749 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20765500 20750 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20768500 20753 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20769500 20754 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20770500 20755 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20772500 20757 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20773500 20758 1c001778 fddff06f jal x0, -36 + 20775500 20760 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20776500 20761 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000023 + 20777500 20762 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20778500 20763 1c00175e 00379713 slli x14, x15, 0x3 x14=00000118 x15:00000023 + 20779500 20764 1c001762 00279793 slli x15, x15, 0x2 x15=0000008c x15:00000023 + 20780500 20765 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000118 + 20781500 20766 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000008c x13:00001f80 + 20782500 20767 1c00176a 00e787b3 add x15, x15, x14 x15=00000098 x15:00000080 x14:00000018 + 20783500 20768 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20784500 20769 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104098 + 20788500 20773 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20789500 20774 1c001bca 16a0006f jal x0, 362 + 20791500 20776 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20792500 20777 1c001d36 e69ff06f jal x0, -408 + 20795500 20780 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20812500 20797 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20813500 20798 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20814500 20799 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104fef60 PA:104fefbc + 20815500 20800 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:104fef60 PA:104fefb8 + 20816500 20801 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:104fef60 PA:104fefb4 + 20817500 20802 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:104fef60 PA:104fefb0 + 20818500 20803 1c001bb0 04c12983 lw x19, 76(x2) x19=00000003 x2:104fef60 PA:104fefac + 20819500 20804 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:104fef60 PA:104fefa8 + 20820500 20805 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:104fef60 PA:104fefa4 + 20821500 20806 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:104fef60 PA:104fefa0 + 20822500 20807 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:104fef60 PA:104fef9c + 20823500 20808 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:104fef60 PA:104fef98 + 20824500 20809 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:104fef60 PA:104fef94 + 20825500 20810 1c001bbe 06010113 addi x2, x2, 96 x2=104fefc0 x2:104fef60 + 20826500 20811 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20828500 20813 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:104fefc0 PA:104fefdc + 20829500 20814 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20830500 20815 1c001838 04010113 addi x2, x2, 64 x2=104ff000 x2:104fefc0 + 20831500 20816 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 20833500 20818 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_4.log b/sw/scripts/tracevis/example/traces/trace_core_01_4.log new file mode 100644 index 0000000..3f4b78e --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_4.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000024 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000004 x10:00000024 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000024 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000004 + 12641500 12626 1c0000a6 05a0206f jal x0, 8282 + 12659500 12644 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12660500 12645 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12661500 12646 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12662500 12647 1c00210c 0e059163 bne x11, x0, 226 x11:00000004 + 12714500 12699 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 12715500 12700 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000024 + 12716500 12701 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000004 x19:00000024 + 12717500 12702 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 12734500 12719 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 12735500 12720 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 12736500 12721 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 12737500 12722 1c00220a 0060006f jal x0, 6 + 12757500 12742 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 17807500 17792 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 17825500 17810 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 17826500 17811 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 17844500 17829 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 17845500 17830 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 17847500 17832 1c00222c 08096283 p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080 + 17871500 17856 1c002230 02a98533 mul x10, x19, x10 x10=00001000 x19:00000004 x10:00000400 + 17872500 17857 1c002234 00550133 add x2, x10, x5 x2=104ff400 x10:00001000 x5:104fe400 + 17873500 17858 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 17875500 17860 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 17911500 17896 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 17919500 17904 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 17920500 17905 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 17921500 17906 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 17922500 17907 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 17940500 17925 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000024 + 17957500 17942 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17958500 17943 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000001 x12:00000024 + 17959500 17944 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001 + 17960500 17945 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000004 x12:00000024 + 17961500 17946 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17962500 17947 1c0009d4 63d0006f jal x0, 3644 + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104ff3c0 x2:104ff400 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104ff3c0 PA:104ff3e4 + 17983500 17968 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17984500 17969 1c001818 02c12423 sw x12, 40(x2) x12:00000004 x2:104ff3c0 PA:104ff3e8 + 17985500 17970 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104ff3c0 PA:104ff3ec + 17986500 17971 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17987500 17972 1c00181e 02410693 addi x13, x2, 36 x13=104ff3e4 x2:104ff3c0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:104ff3c0 PA:104ff3dc + 18005500 17990 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:104ff3c0 PA:104ff3f0 + 18006500 17991 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:104ff3c0 PA:104ff3f4 + 18007500 17992 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104ff3c0 PA:104ff3f8 + 18008500 17993 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104ff3c0 PA:104ff3fc + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104ff3e4 x2:104ff3c0 PA:104ff3cc + 18030500 18015 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104ff360 x2:104ff3c0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104ff378 x2:104ff360 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:104ff360 PA:104ff3b8 + 18048500 18033 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:104ff360 PA:104ff3b0 + 18049500 18034 1c001b78 05312623 sw x19, 76(x2) x19:00000004 x2:104ff360 PA:104ff3ac + 18050500 18035 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:104ff360 PA:104ff3a8 + 18051500 18036 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:104ff360 PA:104ff3a4 + 18052500 18037 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:104ff360 PA:104ff3a0 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:104ff360 PA:104ff39c + 18073500 18058 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104ff360 PA:104ff3bc + 18074500 18059 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:104ff360 PA:104ff3b4 + 18075500 18060 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:104ff360 PA:104ff398 + 18076500 18061 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:104ff360 PA:104ff394 + 18077500 18062 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18078500 18063 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18079500 18064 1c001b8e 00d00433 add x8, x0, x13 x8=104ff3e4 x13:104ff3e4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104ff378 x2:104ff360 PA:104ff374 + 18093500 18078 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18094500 18079 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18095500 18080 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18096500 18081 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18131500 18116 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18132500 18117 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18145500 18130 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18146500 18131 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18147500 18132 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1040a0 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18257500 18242 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18258500 18243 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18261500 18246 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18262500 18247 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18263500 18248 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18265500 18250 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18266500 18251 1c001778 fddff06f jal x0, -36 + 18268500 18253 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18269500 18254 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18270500 18255 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18271500 18256 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18272500 18257 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18273500 18258 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18274500 18259 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18275500 18260 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18276500 18261 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18277500 18262 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040a0 + 18281500 18266 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18282500 18267 1c001bca 16a0006f jal x0, 362 + 18284500 18269 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18285500 18270 1c001d36 e69ff06f jal x0, -408 + 18288500 18273 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18306500 18291 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18307500 18292 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18310500 18295 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18311500 18296 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18312500 18297 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18314500 18299 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18315500 18300 1c001778 fddff06f jal x0, -36 + 18317500 18302 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18318500 18303 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18319500 18304 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18320500 18305 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18321500 18306 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18322500 18307 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18323500 18308 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18324500 18309 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18325500 18310 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18326500 18311 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1040a0 + 18330500 18315 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18331500 18316 1c001bca 16a0006f jal x0, 362 + 18333500 18318 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18334500 18319 1c001d36 e69ff06f jal x0, -408 + 18337500 18322 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18355500 18340 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18356500 18341 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18359500 18344 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18360500 18345 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18361500 18346 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18363500 18348 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18364500 18349 1c001778 fddff06f jal x0, -36 + 18366500 18351 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18367500 18352 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18368500 18353 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18369500 18354 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18370500 18355 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18371500 18356 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18372500 18357 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18373500 18358 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18374500 18359 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18375500 18360 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040a0 + 18379500 18364 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18380500 18365 1c001bca 16a0006f jal x0, 362 + 18382500 18367 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18383500 18368 1c001d36 e69ff06f jal x0, -408 + 18386500 18371 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18400500 18385 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18401500 18386 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18404500 18389 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18405500 18390 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18406500 18391 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18408500 18393 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18409500 18394 1c001778 fddff06f jal x0, -36 + 18411500 18396 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18412500 18397 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18413500 18398 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18414500 18399 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18415500 18400 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18416500 18401 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18417500 18402 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18418500 18403 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18419500 18404 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18420500 18405 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a0 + 18424500 18409 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18425500 18410 1c001bca 16a0006f jal x0, 362 + 18427500 18412 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18428500 18413 1c001d36 e69ff06f jal x0, -408 + 18431500 18416 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18445500 18430 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18446500 18431 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18449500 18434 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18450500 18435 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18451500 18436 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18453500 18438 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18454500 18439 1c001778 fddff06f jal x0, -36 + 18456500 18441 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18457500 18442 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18458500 18443 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18459500 18444 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18460500 18445 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18461500 18446 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18462500 18447 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18463500 18448 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18464500 18449 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18465500 18450 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1040a0 + 18469500 18454 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18470500 18455 1c001bca 16a0006f jal x0, 362 + 18472500 18457 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18473500 18458 1c001d36 e69ff06f jal x0, -408 + 18476500 18461 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18490500 18475 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18491500 18476 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18494500 18479 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18495500 18480 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18496500 18481 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18498500 18483 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18499500 18484 1c001778 fddff06f jal x0, -36 + 18501500 18486 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18502500 18487 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18503500 18488 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18504500 18489 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18505500 18490 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18506500 18491 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18507500 18492 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18508500 18493 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18509500 18494 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18510500 18495 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1040a0 + 18514500 18499 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18515500 18500 1c001bca 16a0006f jal x0, 362 + 18517500 18502 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18518500 18503 1c001d36 e69ff06f jal x0, -408 + 18521500 18506 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18536500 18521 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18537500 18522 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18540500 18525 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18541500 18526 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18542500 18527 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18544500 18529 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18545500 18530 1c001778 fddff06f jal x0, -36 + 18547500 18532 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18548500 18533 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18549500 18534 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18550500 18535 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18551500 18536 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18552500 18537 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18553500 18538 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18554500 18539 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18555500 18540 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18556500 18541 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1040a0 + 18560500 18545 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18561500 18546 1c001bca 16a0006f jal x0, 362 + 18563500 18548 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18564500 18549 1c001d36 e69ff06f jal x0, -408 + 18567500 18552 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18581500 18566 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18582500 18567 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18585500 18570 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18586500 18571 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18587500 18572 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18589500 18574 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18590500 18575 1c001778 fddff06f jal x0, -36 + 18592500 18577 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18593500 18578 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18594500 18579 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18595500 18580 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18596500 18581 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18597500 18582 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18598500 18583 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18599500 18584 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18600500 18585 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18601500 18586 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a0 + 18605500 18590 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18606500 18591 1c001bca 16a0006f jal x0, 362 + 18608500 18593 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18609500 18594 1c001d36 e69ff06f jal x0, -408 + 18612500 18597 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18627500 18612 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18628500 18613 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18631500 18616 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18632500 18617 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18633500 18618 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18635500 18620 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18636500 18621 1c001778 fddff06f jal x0, -36 + 18638500 18623 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18639500 18624 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18640500 18625 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18641500 18626 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18642500 18627 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18643500 18628 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18644500 18629 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18645500 18630 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18646500 18631 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18647500 18632 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1040a0 + 18651500 18636 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18652500 18637 1c001bca 16a0006f jal x0, 362 + 18654500 18639 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18655500 18640 1c001d36 e69ff06f jal x0, -408 + 18658500 18643 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18677500 18662 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18678500 18663 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18681500 18666 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18682500 18667 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18683500 18668 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18685500 18670 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18686500 18671 1c001778 fddff06f jal x0, -36 + 18688500 18673 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18689500 18674 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18690500 18675 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18691500 18676 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18692500 18677 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18693500 18678 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18694500 18679 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18695500 18680 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18696500 18681 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18697500 18682 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1040a0 + 18701500 18686 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18702500 18687 1c001bca 16a0006f jal x0, 362 + 18704500 18689 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18705500 18690 1c001d36 e69ff06f jal x0, -408 + 18708500 18693 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18722500 18707 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18723500 18708 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18726500 18711 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18727500 18712 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18728500 18713 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18730500 18715 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18731500 18716 1c001778 fddff06f jal x0, -36 + 18733500 18718 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18734500 18719 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18735500 18720 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18736500 18721 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18737500 18722 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18738500 18723 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18739500 18724 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18740500 18725 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18741500 18726 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18742500 18727 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1040a0 + 18746500 18731 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18747500 18732 1c001bca 16a0006f jal x0, 362 + 18749500 18734 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18750500 18735 1c001d36 e69ff06f jal x0, -408 + 18753500 18738 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18771500 18756 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18772500 18757 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18775500 18760 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18776500 18761 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18777500 18762 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18779500 18764 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18780500 18765 1c001778 fddff06f jal x0, -36 + 18782500 18767 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18783500 18768 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18784500 18769 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18785500 18770 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18786500 18771 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18787500 18772 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18788500 18773 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18789500 18774 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18790500 18775 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18791500 18776 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040a0 + 18795500 18780 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18796500 18781 1c001bca 16a0006f jal x0, 362 + 18798500 18783 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18799500 18784 1c001d36 e69ff06f jal x0, -408 + 18802500 18787 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18819500 18804 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18820500 18805 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18823500 18808 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18824500 18809 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18825500 18810 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18827500 18812 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18828500 18813 1c001778 fddff06f jal x0, -36 + 18830500 18815 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18831500 18816 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18832500 18817 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18833500 18818 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18834500 18819 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18835500 18820 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18836500 18821 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18837500 18822 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18838500 18823 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18839500 18824 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a0 + 18843500 18828 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18844500 18829 1c001bca 16a0006f jal x0, 362 + 18846500 18831 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18847500 18832 1c001d36 e69ff06f jal x0, -408 + 18850500 18835 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18867500 18852 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18868500 18853 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18871500 18856 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18872500 18857 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18873500 18858 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18875500 18860 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18876500 18861 1c001778 fddff06f jal x0, -36 + 18878500 18863 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18879500 18864 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 18880500 18865 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18881500 18866 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 18882500 18867 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 18883500 18868 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 18884500 18869 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 18885500 18870 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 18886500 18871 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18887500 18872 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1040a0 + 18891500 18876 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18892500 18877 1c001bca 16a0006f jal x0, 362 + 18894500 18879 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18895500 18880 1c001d36 e69ff06f jal x0, -408 + 18898500 18883 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18914500 18899 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18915500 18900 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18918500 18903 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18921500 18906 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104ff360 PA:104ff364 + 18929500 18914 1c001bd0 00012423 sw x0, 8(x2) x2:104ff360 PA:104ff368 + 18932500 18917 1c001bd2 00010623 sb x0, 12(x2) x2:104ff360 PA:104ff36c + 18933500 18918 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18934500 18919 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104ff360 PA:104ff364 + 18959500 18944 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18960500 18945 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18961500 18946 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18962500 18947 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18963500 18948 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19015500 19000 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19016500 19001 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19023500 19008 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19024500 19009 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19025500 19010 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104ff360 PA:104ff370 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104ff3e8 x8:104ff3e4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104ff3e4 PA:104ff3e4 + 19403500 19388 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104ff364 x2:104ff360 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104ff378 x11:104ff364 PA:104ff374 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff364 PA:104ff370 + 19531500 19516 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19532500 19517 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19566500 19551 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19567500 19552 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19568500 19553 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19569500 19554 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19572500 19557 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff364 PA:104ff370 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104ff378 PA:104ff378 + 19745500 19730 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19746500 19731 1c001a5e 00168693 addi x13, x13, 1 x13=104ff379 x13:104ff378 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104ff379 PA:104ff379 + 19766500 19751 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19767500 19752 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104ff364 x2:104ff360 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104ff340 x2:104ff360 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104ff3e4 x2:104ff340 PA:104ff358 + 19817500 19802 1c001a66 01062783 lw x15, 16(x12) x15=104ff378 x12:104ff364 PA:104ff374 + 19818500 19803 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104ff364 PA:104ff368 + 19819500 19804 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104ff340 PA:104ff354 + 19820500 19805 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104ff340 PA:104ff350 + 19821500 19806 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104ff340 PA:104ff34c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104ff340 PA:104ff35c + 19840500 19825 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104ff340 PA:104ff348 + 19841500 19826 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19842500 19827 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19843500 19828 1c001a78 00c004b3 add x9, x0, x12 x9=104ff364 x12:104ff364 + 19844500 19829 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104ff379 x15:104ff378 PA:104ff378 + 19846500 19831 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104ff364 PA:104ff36c + 19866500 19851 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19869500 19854 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104ff364 PA:104ff36c + 19959500 19944 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 19981500 19966 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19982500 19967 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104ff378 x9:104ff364 PA:104ff374 + 20025500 20010 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104ff379 x20:104ff378 PA:104ff378 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a1040a0 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104ff37a x20:104ff379 PA:104ff379 + 20102500 20087 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20103500 20088 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 20105500 20090 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20106500 20091 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104ff340 PA:104ff35c + 20127500 20112 1c001b02 01812403 lw x8, 24(x2) x8=104ff3e4 x2:104ff340 PA:104ff358 + 20128500 20113 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104ff340 PA:104ff354 + 20129500 20114 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104ff340 PA:104ff350 + 20130500 20115 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104ff340 PA:104ff34c + 20131500 20116 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104ff340 PA:104ff348 + 20132500 20117 1c001b0c 02010113 addi x2, x2, 32 x2=104ff360 x2:104ff340 + 20133500 20118 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104ff3e8 x24:104ff3e8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20182500 20167 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20183500 20168 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20186500 20171 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20187500 20172 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20188500 20173 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20190500 20175 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20191500 20176 1c001778 fddff06f jal x0, -36 + 20193500 20178 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20194500 20179 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 20195500 20180 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20196500 20181 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 20197500 20182 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 20198500 20183 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 20199500 20184 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 20200500 20185 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 20201500 20186 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20202500 20187 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040a0 + 20206500 20191 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20207500 20192 1c001bca 16a0006f jal x0, 362 + 20209500 20194 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20210500 20195 1c001d36 e69ff06f jal x0, -408 + 20213500 20198 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20231500 20216 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20232500 20217 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20235500 20220 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20236500 20221 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20237500 20222 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20239500 20224 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20240500 20225 1c001778 fddff06f jal x0, -36 + 20242500 20227 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20243500 20228 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 20244500 20229 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20245500 20230 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 20246500 20231 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 20247500 20232 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 20248500 20233 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 20249500 20234 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 20250500 20235 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20251500 20236 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a0 + 20255500 20240 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20256500 20241 1c001bca 16a0006f jal x0, 362 + 20258500 20243 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20259500 20244 1c001d36 e69ff06f jal x0, -408 + 20262500 20247 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20279500 20264 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20280500 20265 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20283500 20268 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20286500 20271 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104ff360 PA:104ff364 + 20287500 20272 1c001bd0 00012423 sw x0, 8(x2) x2:104ff360 PA:104ff368 + 20288500 20273 1c001bd2 00010623 sb x0, 12(x2) x2:104ff360 PA:104ff36c + 20289500 20274 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20290500 20275 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20291500 20276 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20292500 20277 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104ff360 PA:104ff364 + 20293500 20278 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20294500 20279 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20295500 20280 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20296500 20281 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20297500 20282 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20298500 20283 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20299500 20284 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20300500 20285 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20317500 20302 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20318500 20303 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20321500 20306 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20322500 20307 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20323500 20308 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20326500 20311 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20329500 20314 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20332500 20317 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20335500 20320 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20336500 20321 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20337500 20322 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20338500 20323 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20341500 20326 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20342500 20327 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20345500 20330 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20346500 20331 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20349500 20334 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20351500 20336 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20354500 20339 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20355500 20340 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20358500 20343 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20359500 20344 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20360500 20345 1c001f42 e09ff06f jal x0, -504 + 20362500 20347 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20363500 20348 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104ff360 PA:104ff370 + 20364500 20349 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20367500 20352 1c001e34 00440c13 addi x24, x8, 4 x24=104ff3ec x8:104ff3e8 + 20368500 20353 1c001e38 00042503 lw x10, 0(x8) x10=00000004 x8:104ff3e8 PA:104ff3e8 + 20369500 20354 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20372500 20357 1c001e54 00055863 bge x10, x0, 16 x10:00000004 + 20375500 20360 1c001e64 00410593 addi x11, x2, 4 x11=104ff364 x2:104ff360 + 20376500 20361 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20378500 20363 1c0019fe 0105a683 lw x13, 16(x11) x13=104ff378 x11:104ff364 PA:104ff374 + 20379500 20364 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff364 PA:104ff370 + 20380500 20365 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20381500 20366 1c001a04 02f55633 divu x12, x10, x15 x12=00000004 x10:00000004 x15:00000001 + 20415500 20400 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000004 x14:0000000a + 20416500 20401 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20417500 20402 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20418500 20403 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20421500 20406 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff364 PA:104ff370 + 20422500 20407 1c001a20 02f55833 divu x16, x10, x15 x16=00000004 x10:00000004 x15:00000001 + 20456500 20441 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000004 x15:00000001 + 20490500 20475 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20521500 20506 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20522500 20507 1c001a2e 01004663 blt x0, x16, 12 x16:00000004 + 20525500 20510 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20527500 20512 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000004 + 20530500 20515 1c001a56 01070733 add x14, x14, x16 x14=00000034 x14:00000030 x16:00000004 + 20531500 20516 1c001a58 00e68023 sb x14, 0(x13) x14:00000034 x13:104ff378 PA:104ff378 + 20532500 20517 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20533500 20518 1c001a5e 00168693 addi x13, x13, 1 x13=104ff379 x13:104ff378 + 20534500 20519 1c001a60 fb1ff06f jal x0, -80 + 20536500 20521 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20537500 20522 1c001a12 00068023 sb x0, 0(x13) x13:104ff379 PA:104ff379 + 20538500 20523 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20540500 20525 1c001e68 f17ff06f jal x0, -234 + 20542500 20527 1c001d7e 00410613 addi x12, x2, 4 x12=104ff364 x2:104ff360 + 20543500 20528 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20544500 20529 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20545500 20530 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20547500 20532 1c001a62 fe010113 addi x2, x2, -32 x2=104ff340 x2:104ff360 + 20548500 20533 1c001a64 00812c23 sw x8, 24(x2) x8:104ff3e8 x2:104ff340 PA:104ff358 + 20549500 20534 1c001a66 01062783 lw x15, 16(x12) x15=104ff378 x12:104ff364 PA:104ff374 + 20550500 20535 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104ff364 PA:104ff368 + 20551500 20536 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104ff340 PA:104ff354 + 20552500 20537 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104ff340 PA:104ff350 + 20553500 20538 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104ff340 PA:104ff34c + 20554500 20539 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104ff340 PA:104ff35c + 20555500 20540 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104ff340 PA:104ff348 + 20556500 20541 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20557500 20542 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20558500 20543 1c001a78 00c004b3 add x9, x0, x12 x9=104ff364 x12:104ff364 + 20559500 20544 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000034 x15=104ff379 x15:104ff378 PA:104ff378 + 20561500 20546 1c001a7e 00070363 beq x14, x0, 6 x14:00000034 + 20562500 20547 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20563500 20548 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104ff364 PA:104ff36c + 20565500 20550 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20568500 20553 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 20570500 20555 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20571500 20556 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20574500 20559 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20575500 20560 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20576500 20561 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20579500 20564 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20580500 20565 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20581500 20566 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20582500 20567 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20583500 20568 1c001b36 f71ff06f jal x0, -144 + 20585500 20570 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104ff364 PA:104ff36c + 20587500 20572 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20590500 20575 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 20592500 20577 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20593500 20578 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20596500 20581 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 20597500 20582 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20598500 20583 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20599500 20584 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20600500 20585 1c001ae8 0104aa03 lw x20, 16(x9) x20=104ff378 x9:104ff364 PA:104ff374 + 20602500 20587 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000034 x20=104ff379 x20:104ff378 PA:104ff378 + 20604500 20589 1c001af0 06059763 bne x11, x0, 110 x11:00000034 + 20607500 20592 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20608500 20593 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20610500 20595 1c001776 00b00533 add x10, x0, x11 x10=00000034 x11:00000034 + 20611500 20596 1c001778 fddff06f jal x0, -36 + 20613500 20598 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20614500 20599 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 20615500 20600 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20616500 20601 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 20617500 20602 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 20618500 20603 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 20619500 20604 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 20620500 20605 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 20621500 20606 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20622500 20607 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000034 x14:1a104000 PA:1a1040a0 + 20626500 20611 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20627500 20612 1c001b62 f8bff06f jal x0, -118 + 20629500 20614 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104ff37a x20:104ff379 PA:104ff379 + 20631500 20616 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20632500 20617 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff364 PA:104ff364 + 20634500 20619 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20635500 20620 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20638500 20623 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104ff340 PA:104ff35c + 20639500 20624 1c001b02 01812403 lw x8, 24(x2) x8=104ff3e8 x2:104ff340 PA:104ff358 + 20640500 20625 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104ff340 PA:104ff354 + 20641500 20626 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104ff340 PA:104ff350 + 20642500 20627 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104ff340 PA:104ff34c + 20643500 20628 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104ff340 PA:104ff348 + 20644500 20629 1c001b0c 02010113 addi x2, x2, 32 x2=104ff360 x2:104ff340 + 20645500 20630 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20647500 20632 1c001d86 01800433 add x8, x0, x24 x8=104ff3ec x24:104ff3ec + 20648500 20633 1c001d88 fadff06f jal x0, -84 + 20650500 20635 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20651500 20636 1c001d36 e69ff06f jal x0, -408 + 20654500 20639 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20676500 20661 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20677500 20662 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20680500 20665 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20681500 20666 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20682500 20667 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20684500 20669 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20685500 20670 1c001778 fddff06f jal x0, -36 + 20687500 20672 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20688500 20673 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 20689500 20674 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20690500 20675 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 20691500 20676 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 20692500 20677 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 20693500 20678 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 20694500 20679 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 20695500 20680 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20696500 20681 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1040a0 + 20700500 20685 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20701500 20686 1c001bca 16a0006f jal x0, 362 + 20703500 20688 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20704500 20689 1c001d36 e69ff06f jal x0, -408 + 20707500 20692 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20723500 20708 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20724500 20709 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20727500 20712 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20728500 20713 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20729500 20714 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20731500 20716 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20732500 20717 1c001778 fddff06f jal x0, -36 + 20734500 20719 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20735500 20720 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 20736500 20721 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20737500 20722 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 20738500 20723 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 20739500 20724 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 20740500 20725 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 20741500 20726 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 20742500 20727 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20743500 20728 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1040a0 + 20747500 20732 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20748500 20733 1c001bca 16a0006f jal x0, 362 + 20750500 20735 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20751500 20736 1c001d36 e69ff06f jal x0, -408 + 20754500 20739 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20768500 20753 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20769500 20754 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20772500 20757 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20773500 20758 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20774500 20759 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20776500 20761 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20777500 20762 1c001778 fddff06f jal x0, -36 + 20779500 20764 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20780500 20765 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000024 + 20781500 20766 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20782500 20767 1c00175e 00379713 slli x14, x15, 0x3 x14=00000120 x15:00000024 + 20783500 20768 1c001762 00279793 slli x15, x15, 0x2 x15=00000090 x15:00000024 + 20784500 20769 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000120 + 20785500 20770 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000090 x13:00001f80 + 20786500 20771 1c00176a 00e787b3 add x15, x15, x14 x15=000000a0 x15:00000080 x14:00000020 + 20787500 20772 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20788500 20773 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1040a0 + 20792500 20777 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20793500 20778 1c001bca 16a0006f jal x0, 362 + 20795500 20780 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20796500 20781 1c001d36 e69ff06f jal x0, -408 + 20799500 20784 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20816500 20801 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20817500 20802 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20818500 20803 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104ff360 PA:104ff3bc + 20819500 20804 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:104ff360 PA:104ff3b8 + 20820500 20805 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:104ff360 PA:104ff3b4 + 20821500 20806 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:104ff360 PA:104ff3b0 + 20822500 20807 1c001bb0 04c12983 lw x19, 76(x2) x19=00000004 x2:104ff360 PA:104ff3ac + 20823500 20808 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:104ff360 PA:104ff3a8 + 20824500 20809 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:104ff360 PA:104ff3a4 + 20825500 20810 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:104ff360 PA:104ff3a0 + 20826500 20811 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:104ff360 PA:104ff39c + 20827500 20812 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:104ff360 PA:104ff398 + 20828500 20813 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:104ff360 PA:104ff394 + 20829500 20814 1c001bbe 06010113 addi x2, x2, 96 x2=104ff3c0 x2:104ff360 + 20830500 20815 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20832500 20817 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:104ff3c0 PA:104ff3dc + 20834500 20819 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20835500 20820 1c001838 04010113 addi x2, x2, 64 x2=104ff400 x2:104ff3c0 + 20836500 20821 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 20838500 20823 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_5.log b/sw/scripts/tracevis/example/traces/trace_core_01_5.log new file mode 100644 index 0000000..0c637e1 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_5.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000025 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000005 x10:00000025 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000025 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000005 + 12641500 12626 1c0000a6 05a0206f jal x0, 8282 + 12659500 12644 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12660500 12645 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12661500 12646 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12662500 12647 1c00210c 0e059163 bne x11, x0, 226 x11:00000005 + 12714500 12699 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 12715500 12700 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000025 + 12716500 12701 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000005 x19:00000025 + 12717500 12702 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 12734500 12719 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 12735500 12720 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 12736500 12721 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 12737500 12722 1c00220a 0060006f jal x0, 6 + 12757500 12742 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 17807500 17792 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 17825500 17810 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 17826500 17811 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 17844500 17829 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 17845500 17830 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 17847500 17832 1c00222c 08096283 p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080 + 17871500 17856 1c002230 02a98533 mul x10, x19, x10 x10=00001400 x19:00000005 x10:00000400 + 17872500 17857 1c002234 00550133 add x2, x10, x5 x2=104ff800 x10:00001400 x5:104fe400 + 17873500 17858 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 17875500 17860 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 17911500 17896 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 17919500 17904 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 17920500 17905 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 17921500 17906 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 17922500 17907 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 17940500 17925 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000025 + 17957500 17942 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17958500 17943 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000001 x12:00000025 + 17959500 17944 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001 + 17960500 17945 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000005 x12:00000025 + 17961500 17946 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17962500 17947 1c0009d4 63d0006f jal x0, 3644 + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104ff7c0 x2:104ff800 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104ff7c0 PA:104ff7e4 + 17984500 17969 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17985500 17970 1c001818 02c12423 sw x12, 40(x2) x12:00000005 x2:104ff7c0 PA:104ff7e8 + 17986500 17971 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104ff7c0 PA:104ff7ec + 17987500 17972 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17988500 17973 1c00181e 02410693 addi x13, x2, 36 x13=104ff7e4 x2:104ff7c0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:104ff7c0 PA:104ff7dc + 18006500 17991 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:104ff7c0 PA:104ff7f0 + 18007500 17992 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:104ff7c0 PA:104ff7f4 + 18008500 17993 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104ff7c0 PA:104ff7f8 + 18009500 17994 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104ff7c0 PA:104ff7fc + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104ff7e4 x2:104ff7c0 PA:104ff7cc + 18025500 18010 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104ff760 x2:104ff7c0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104ff778 x2:104ff760 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:104ff760 PA:104ff7b8 + 18049500 18034 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:104ff760 PA:104ff7b0 + 18050500 18035 1c001b78 05312623 sw x19, 76(x2) x19:00000005 x2:104ff760 PA:104ff7ac + 18051500 18036 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:104ff760 PA:104ff7a8 + 18052500 18037 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:104ff760 PA:104ff7a4 + 18053500 18038 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:104ff760 PA:104ff7a0 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:104ff760 PA:104ff79c + 18072500 18057 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104ff760 PA:104ff7bc + 18073500 18058 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:104ff760 PA:104ff7b4 + 18074500 18059 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:104ff760 PA:104ff798 + 18075500 18060 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:104ff760 PA:104ff794 + 18076500 18061 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18077500 18062 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18078500 18063 1c001b8e 00d00433 add x8, x0, x13 x8=104ff7e4 x13:104ff7e4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104ff778 x2:104ff760 PA:104ff774 + 18094500 18079 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18095500 18080 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18096500 18081 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18097500 18082 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18133500 18118 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18134500 18119 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18145500 18130 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18146500 18131 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18147500 18132 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1040a8 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18259500 18244 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18260500 18245 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18263500 18248 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18264500 18249 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18265500 18250 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18267500 18252 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18268500 18253 1c001778 fddff06f jal x0, -36 + 18270500 18255 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18271500 18256 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18272500 18257 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18273500 18258 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18274500 18259 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18275500 18260 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18276500 18261 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18277500 18262 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18278500 18263 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18279500 18264 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040a8 + 18283500 18268 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18284500 18269 1c001bca 16a0006f jal x0, 362 + 18286500 18271 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18287500 18272 1c001d36 e69ff06f jal x0, -408 + 18290500 18275 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18309500 18294 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18310500 18295 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18313500 18298 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18314500 18299 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18315500 18300 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18317500 18302 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18318500 18303 1c001778 fddff06f jal x0, -36 + 18320500 18305 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18321500 18306 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18322500 18307 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18323500 18308 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18324500 18309 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18325500 18310 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18326500 18311 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18327500 18312 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18328500 18313 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18329500 18314 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1040a8 + 18333500 18318 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18334500 18319 1c001bca 16a0006f jal x0, 362 + 18336500 18321 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18337500 18322 1c001d36 e69ff06f jal x0, -408 + 18340500 18325 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18359500 18344 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18360500 18345 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18363500 18348 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18364500 18349 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18365500 18350 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18367500 18352 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18368500 18353 1c001778 fddff06f jal x0, -36 + 18370500 18355 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18371500 18356 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18372500 18357 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18373500 18358 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18374500 18359 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18375500 18360 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18376500 18361 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18377500 18362 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18378500 18363 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18379500 18364 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040a8 + 18383500 18368 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18384500 18369 1c001bca 16a0006f jal x0, 362 + 18386500 18371 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18387500 18372 1c001d36 e69ff06f jal x0, -408 + 18390500 18375 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18404500 18389 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18405500 18390 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18408500 18393 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18409500 18394 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18410500 18395 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18412500 18397 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18413500 18398 1c001778 fddff06f jal x0, -36 + 18415500 18400 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18416500 18401 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18417500 18402 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18418500 18403 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18419500 18404 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18420500 18405 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18421500 18406 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18422500 18407 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18423500 18408 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18424500 18409 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a8 + 18428500 18413 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18429500 18414 1c001bca 16a0006f jal x0, 362 + 18431500 18416 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18432500 18417 1c001d36 e69ff06f jal x0, -408 + 18435500 18420 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18449500 18434 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18450500 18435 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18453500 18438 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18454500 18439 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18455500 18440 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18457500 18442 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18458500 18443 1c001778 fddff06f jal x0, -36 + 18460500 18445 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18461500 18446 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18462500 18447 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18463500 18448 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18464500 18449 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18465500 18450 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18466500 18451 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18467500 18452 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18468500 18453 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18469500 18454 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1040a8 + 18473500 18458 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18474500 18459 1c001bca 16a0006f jal x0, 362 + 18476500 18461 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18477500 18462 1c001d36 e69ff06f jal x0, -408 + 18480500 18465 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18494500 18479 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18495500 18480 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18498500 18483 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18499500 18484 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18500500 18485 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18502500 18487 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18503500 18488 1c001778 fddff06f jal x0, -36 + 18505500 18490 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18506500 18491 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18507500 18492 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18508500 18493 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18509500 18494 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18510500 18495 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18511500 18496 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18512500 18497 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18513500 18498 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18514500 18499 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1040a8 + 18518500 18503 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18519500 18504 1c001bca 16a0006f jal x0, 362 + 18521500 18506 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18522500 18507 1c001d36 e69ff06f jal x0, -408 + 18525500 18510 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18539500 18524 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18540500 18525 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18543500 18528 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18544500 18529 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18545500 18530 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18547500 18532 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18548500 18533 1c001778 fddff06f jal x0, -36 + 18550500 18535 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18551500 18536 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18552500 18537 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18553500 18538 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18554500 18539 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18555500 18540 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18556500 18541 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18557500 18542 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18558500 18543 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18559500 18544 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1040a8 + 18563500 18548 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18564500 18549 1c001bca 16a0006f jal x0, 362 + 18566500 18551 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18567500 18552 1c001d36 e69ff06f jal x0, -408 + 18570500 18555 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18584500 18569 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18585500 18570 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18588500 18573 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18589500 18574 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18590500 18575 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18592500 18577 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18593500 18578 1c001778 fddff06f jal x0, -36 + 18595500 18580 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18596500 18581 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18597500 18582 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18598500 18583 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18599500 18584 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18600500 18585 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18601500 18586 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18602500 18587 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18603500 18588 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18604500 18589 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a8 + 18608500 18593 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18609500 18594 1c001bca 16a0006f jal x0, 362 + 18611500 18596 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18612500 18597 1c001d36 e69ff06f jal x0, -408 + 18615500 18600 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18629500 18614 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18630500 18615 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18633500 18618 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18634500 18619 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18635500 18620 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18637500 18622 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18638500 18623 1c001778 fddff06f jal x0, -36 + 18640500 18625 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18641500 18626 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18642500 18627 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18643500 18628 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18644500 18629 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18645500 18630 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18646500 18631 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18647500 18632 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18648500 18633 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18649500 18634 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1040a8 + 18653500 18638 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18654500 18639 1c001bca 16a0006f jal x0, 362 + 18656500 18641 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18657500 18642 1c001d36 e69ff06f jal x0, -408 + 18660500 18645 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18680500 18665 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18681500 18666 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18684500 18669 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18685500 18670 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18686500 18671 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18688500 18673 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18689500 18674 1c001778 fddff06f jal x0, -36 + 18691500 18676 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18692500 18677 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18693500 18678 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18694500 18679 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18695500 18680 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18696500 18681 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18697500 18682 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18698500 18683 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18699500 18684 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18700500 18685 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1040a8 + 18704500 18689 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18705500 18690 1c001bca 16a0006f jal x0, 362 + 18707500 18692 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18708500 18693 1c001d36 e69ff06f jal x0, -408 + 18711500 18696 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18726500 18711 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18727500 18712 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18730500 18715 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18731500 18716 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18732500 18717 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18734500 18719 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18735500 18720 1c001778 fddff06f jal x0, -36 + 18737500 18722 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18738500 18723 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18739500 18724 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18740500 18725 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18741500 18726 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18742500 18727 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18743500 18728 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18744500 18729 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18745500 18730 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18746500 18731 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1040a8 + 18750500 18735 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18751500 18736 1c001bca 16a0006f jal x0, 362 + 18753500 18738 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18754500 18739 1c001d36 e69ff06f jal x0, -408 + 18757500 18742 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18775500 18760 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18776500 18761 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18779500 18764 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18780500 18765 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18781500 18766 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18783500 18768 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18784500 18769 1c001778 fddff06f jal x0, -36 + 18786500 18771 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18787500 18772 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18788500 18773 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18789500 18774 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18790500 18775 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18791500 18776 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18792500 18777 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18793500 18778 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18794500 18779 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18795500 18780 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040a8 + 18799500 18784 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18800500 18785 1c001bca 16a0006f jal x0, 362 + 18802500 18787 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18803500 18788 1c001d36 e69ff06f jal x0, -408 + 18806500 18791 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18820500 18805 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18821500 18806 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18824500 18809 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18825500 18810 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18826500 18811 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18828500 18813 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18829500 18814 1c001778 fddff06f jal x0, -36 + 18831500 18816 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18832500 18817 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18833500 18818 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18834500 18819 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18835500 18820 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18836500 18821 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18837500 18822 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18838500 18823 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18839500 18824 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18840500 18825 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a8 + 18844500 18829 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18845500 18830 1c001bca 16a0006f jal x0, 362 + 18847500 18832 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18848500 18833 1c001d36 e69ff06f jal x0, -408 + 18851500 18836 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18868500 18853 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18869500 18854 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18872500 18857 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18873500 18858 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18874500 18859 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18876500 18861 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18877500 18862 1c001778 fddff06f jal x0, -36 + 18879500 18864 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18880500 18865 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 18881500 18866 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18882500 18867 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 18883500 18868 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 18884500 18869 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 18885500 18870 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 18886500 18871 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 18887500 18872 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18888500 18873 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1040a8 + 18892500 18877 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18893500 18878 1c001bca 16a0006f jal x0, 362 + 18895500 18880 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18896500 18881 1c001d36 e69ff06f jal x0, -408 + 18899500 18884 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18916500 18901 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18917500 18902 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18920500 18905 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18923500 18908 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104ff760 PA:104ff764 + 18929500 18914 1c001bd0 00012423 sw x0, 8(x2) x2:104ff760 PA:104ff768 + 18933500 18918 1c001bd2 00010623 sb x0, 12(x2) x2:104ff760 PA:104ff76c + 18934500 18919 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18935500 18920 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104ff760 PA:104ff764 + 18960500 18945 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18961500 18946 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18962500 18947 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18963500 18948 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18964500 18949 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19001500 18986 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19002500 18987 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19021500 19006 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19022500 19007 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19023500 19008 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104ff760 PA:104ff770 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104ff7e8 x8:104ff7e4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104ff7e4 PA:104ff7e4 + 19404500 19389 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104ff764 x2:104ff760 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104ff778 x11:104ff764 PA:104ff774 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff764 PA:104ff770 + 19532500 19517 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19533500 19518 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19567500 19552 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19568500 19553 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19569500 19554 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19570500 19555 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19573500 19558 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff764 PA:104ff770 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104ff778 PA:104ff778 + 19746500 19731 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19747500 19732 1c001a5e 00168693 addi x13, x13, 1 x13=104ff779 x13:104ff778 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104ff779 PA:104ff779 + 19767500 19752 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19768500 19753 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104ff764 x2:104ff760 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104ff740 x2:104ff760 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104ff7e4 x2:104ff740 PA:104ff758 + 19818500 19803 1c001a66 01062783 lw x15, 16(x12) x15=104ff778 x12:104ff764 PA:104ff774 + 19819500 19804 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104ff764 PA:104ff768 + 19820500 19805 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104ff740 PA:104ff754 + 19821500 19806 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104ff740 PA:104ff750 + 19822500 19807 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104ff740 PA:104ff74c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104ff740 PA:104ff75c + 19841500 19826 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104ff740 PA:104ff748 + 19842500 19827 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19843500 19828 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19844500 19829 1c001a78 00c004b3 add x9, x0, x12 x9=104ff764 x12:104ff764 + 19845500 19830 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104ff779 x15:104ff778 PA:104ff778 + 19847500 19832 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104ff764 PA:104ff76c + 19867500 19852 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19870500 19855 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104ff764 PA:104ff76c + 19960500 19945 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 19982500 19967 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19983500 19968 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104ff778 x9:104ff764 PA:104ff774 + 20026500 20011 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104ff779 x20:104ff778 PA:104ff778 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a1040a8 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104ff77a x20:104ff779 PA:104ff779 + 20103500 20088 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20104500 20089 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 20106500 20091 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20107500 20092 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104ff740 PA:104ff75c + 20128500 20113 1c001b02 01812403 lw x8, 24(x2) x8=104ff7e4 x2:104ff740 PA:104ff758 + 20129500 20114 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104ff740 PA:104ff754 + 20130500 20115 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104ff740 PA:104ff750 + 20131500 20116 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104ff740 PA:104ff74c + 20132500 20117 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104ff740 PA:104ff748 + 20133500 20118 1c001b0c 02010113 addi x2, x2, 32 x2=104ff760 x2:104ff740 + 20134500 20119 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104ff7e8 x24:104ff7e8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20184500 20169 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20185500 20170 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20188500 20173 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20189500 20174 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20190500 20175 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20192500 20177 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20193500 20178 1c001778 fddff06f jal x0, -36 + 20195500 20180 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20196500 20181 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 20197500 20182 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20198500 20183 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 20199500 20184 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 20200500 20185 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 20201500 20186 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 20202500 20187 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 20203500 20188 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20204500 20189 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040a8 + 20208500 20193 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20209500 20194 1c001bca 16a0006f jal x0, 362 + 20211500 20196 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20212500 20197 1c001d36 e69ff06f jal x0, -408 + 20215500 20200 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20232500 20217 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20233500 20218 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20236500 20221 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20237500 20222 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20238500 20223 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20240500 20225 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20241500 20226 1c001778 fddff06f jal x0, -36 + 20243500 20228 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20244500 20229 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 20245500 20230 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20246500 20231 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 20247500 20232 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 20248500 20233 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 20249500 20234 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 20250500 20235 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 20251500 20236 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20252500 20237 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040a8 + 20256500 20241 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20257500 20242 1c001bca 16a0006f jal x0, 362 + 20259500 20244 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20260500 20245 1c001d36 e69ff06f jal x0, -408 + 20263500 20248 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20281500 20266 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20282500 20267 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20285500 20270 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20288500 20273 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104ff760 PA:104ff764 + 20289500 20274 1c001bd0 00012423 sw x0, 8(x2) x2:104ff760 PA:104ff768 + 20290500 20275 1c001bd2 00010623 sb x0, 12(x2) x2:104ff760 PA:104ff76c + 20291500 20276 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20292500 20277 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20293500 20278 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20294500 20279 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104ff760 PA:104ff764 + 20296500 20281 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20297500 20282 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20298500 20283 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20299500 20284 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20300500 20285 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20301500 20286 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20302500 20287 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20303500 20288 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20319500 20304 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20320500 20305 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20323500 20308 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20324500 20309 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20325500 20310 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20328500 20313 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20331500 20316 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20334500 20319 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20337500 20322 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20338500 20323 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20339500 20324 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20340500 20325 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20343500 20328 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20344500 20329 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20347500 20332 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20348500 20333 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20351500 20336 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20353500 20338 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20356500 20341 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20357500 20342 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20360500 20345 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20361500 20346 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20362500 20347 1c001f42 e09ff06f jal x0, -504 + 20364500 20349 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20365500 20350 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104ff760 PA:104ff770 + 20366500 20351 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20369500 20354 1c001e34 00440c13 addi x24, x8, 4 x24=104ff7ec x8:104ff7e8 + 20370500 20355 1c001e38 00042503 lw x10, 0(x8) x10=00000005 x8:104ff7e8 PA:104ff7e8 + 20371500 20356 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20374500 20359 1c001e54 00055863 bge x10, x0, 16 x10:00000005 + 20377500 20362 1c001e64 00410593 addi x11, x2, 4 x11=104ff764 x2:104ff760 + 20378500 20363 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20380500 20365 1c0019fe 0105a683 lw x13, 16(x11) x13=104ff778 x11:104ff764 PA:104ff774 + 20381500 20366 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff764 PA:104ff770 + 20382500 20367 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20383500 20368 1c001a04 02f55633 divu x12, x10, x15 x12=00000005 x10:00000005 x15:00000001 + 20417500 20402 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000005 x14:0000000a + 20418500 20403 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20419500 20404 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20420500 20405 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20423500 20408 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ff764 PA:104ff770 + 20424500 20409 1c001a20 02f55833 divu x16, x10, x15 x16=00000005 x10:00000005 x15:00000001 + 20458500 20443 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000005 x15:00000001 + 20492500 20477 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20523500 20508 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20524500 20509 1c001a2e 01004663 blt x0, x16, 12 x16:00000005 + 20527500 20512 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20529500 20514 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000005 + 20532500 20517 1c001a56 01070733 add x14, x14, x16 x14=00000035 x14:00000030 x16:00000005 + 20533500 20518 1c001a58 00e68023 sb x14, 0(x13) x14:00000035 x13:104ff778 PA:104ff778 + 20536500 20521 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20537500 20522 1c001a5e 00168693 addi x13, x13, 1 x13=104ff779 x13:104ff778 + 20538500 20523 1c001a60 fb1ff06f jal x0, -80 + 20540500 20525 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20541500 20526 1c001a12 00068023 sb x0, 0(x13) x13:104ff779 PA:104ff779 + 20542500 20527 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20544500 20529 1c001e68 f17ff06f jal x0, -234 + 20546500 20531 1c001d7e 00410613 addi x12, x2, 4 x12=104ff764 x2:104ff760 + 20547500 20532 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20548500 20533 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20549500 20534 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20551500 20536 1c001a62 fe010113 addi x2, x2, -32 x2=104ff740 x2:104ff760 + 20552500 20537 1c001a64 00812c23 sw x8, 24(x2) x8:104ff7e8 x2:104ff740 PA:104ff758 + 20553500 20538 1c001a66 01062783 lw x15, 16(x12) x15=104ff778 x12:104ff764 PA:104ff774 + 20554500 20539 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104ff764 PA:104ff768 + 20555500 20540 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104ff740 PA:104ff754 + 20556500 20541 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104ff740 PA:104ff750 + 20557500 20542 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104ff740 PA:104ff74c + 20558500 20543 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104ff740 PA:104ff75c + 20559500 20544 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104ff740 PA:104ff748 + 20560500 20545 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20561500 20546 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20562500 20547 1c001a78 00c004b3 add x9, x0, x12 x9=104ff764 x12:104ff764 + 20563500 20548 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000035 x15=104ff779 x15:104ff778 PA:104ff778 + 20565500 20550 1c001a7e 00070363 beq x14, x0, 6 x14:00000035 + 20566500 20551 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20567500 20552 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104ff764 PA:104ff76c + 20569500 20554 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20572500 20557 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 20574500 20559 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20575500 20560 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20578500 20563 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20579500 20564 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20580500 20565 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20583500 20568 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20584500 20569 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20585500 20570 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20586500 20571 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20587500 20572 1c001b36 f71ff06f jal x0, -144 + 20589500 20574 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104ff764 PA:104ff76c + 20591500 20576 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20594500 20579 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 20596500 20581 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20597500 20582 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20600500 20585 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 20601500 20586 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20602500 20587 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20603500 20588 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20604500 20589 1c001ae8 0104aa03 lw x20, 16(x9) x20=104ff778 x9:104ff764 PA:104ff774 + 20606500 20591 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000035 x20=104ff779 x20:104ff778 PA:104ff778 + 20608500 20593 1c001af0 06059763 bne x11, x0, 110 x11:00000035 + 20611500 20596 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20612500 20597 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20614500 20599 1c001776 00b00533 add x10, x0, x11 x10=00000035 x11:00000035 + 20615500 20600 1c001778 fddff06f jal x0, -36 + 20617500 20602 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20618500 20603 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 20619500 20604 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20620500 20605 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 20621500 20606 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 20622500 20607 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 20623500 20608 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 20624500 20609 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 20625500 20610 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20626500 20611 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000035 x14:1a104000 PA:1a1040a8 + 20630500 20615 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20631500 20616 1c001b62 f8bff06f jal x0, -118 + 20633500 20618 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104ff77a x20:104ff779 PA:104ff779 + 20635500 20620 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20636500 20621 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ff764 PA:104ff764 + 20638500 20623 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20639500 20624 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20642500 20627 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104ff740 PA:104ff75c + 20643500 20628 1c001b02 01812403 lw x8, 24(x2) x8=104ff7e8 x2:104ff740 PA:104ff758 + 20644500 20629 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104ff740 PA:104ff754 + 20645500 20630 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104ff740 PA:104ff750 + 20646500 20631 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104ff740 PA:104ff74c + 20647500 20632 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104ff740 PA:104ff748 + 20648500 20633 1c001b0c 02010113 addi x2, x2, 32 x2=104ff760 x2:104ff740 + 20649500 20634 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20651500 20636 1c001d86 01800433 add x8, x0, x24 x8=104ff7ec x24:104ff7ec + 20652500 20637 1c001d88 fadff06f jal x0, -84 + 20654500 20639 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20655500 20640 1c001d36 e69ff06f jal x0, -408 + 20658500 20643 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20682500 20667 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20683500 20668 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20686500 20671 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20687500 20672 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20688500 20673 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20690500 20675 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20691500 20676 1c001778 fddff06f jal x0, -36 + 20693500 20678 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20694500 20679 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 20695500 20680 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20696500 20681 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 20697500 20682 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 20698500 20683 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 20699500 20684 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 20700500 20685 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 20701500 20686 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20702500 20687 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1040a8 + 20706500 20691 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20707500 20692 1c001bca 16a0006f jal x0, 362 + 20709500 20694 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20710500 20695 1c001d36 e69ff06f jal x0, -408 + 20713500 20698 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20729500 20714 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20730500 20715 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20733500 20718 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20734500 20719 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20735500 20720 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20737500 20722 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20738500 20723 1c001778 fddff06f jal x0, -36 + 20740500 20725 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20741500 20726 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 20742500 20727 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20743500 20728 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 20744500 20729 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 20745500 20730 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 20746500 20731 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 20747500 20732 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 20748500 20733 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20749500 20734 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1040a8 + 20753500 20738 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20754500 20739 1c001bca 16a0006f jal x0, 362 + 20756500 20741 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20757500 20742 1c001d36 e69ff06f jal x0, -408 + 20760500 20745 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20775500 20760 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20776500 20761 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20779500 20764 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20780500 20765 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20781500 20766 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20783500 20768 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20784500 20769 1c001778 fddff06f jal x0, -36 + 20786500 20771 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20787500 20772 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000025 + 20788500 20773 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20789500 20774 1c00175e 00379713 slli x14, x15, 0x3 x14=00000128 x15:00000025 + 20790500 20775 1c001762 00279793 slli x15, x15, 0x2 x15=00000094 x15:00000025 + 20791500 20776 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000128 + 20792500 20777 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000094 x13:00001f80 + 20793500 20778 1c00176a 00e787b3 add x15, x15, x14 x15=000000a8 x15:00000080 x14:00000028 + 20794500 20779 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20795500 20780 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1040a8 + 20799500 20784 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20800500 20785 1c001bca 16a0006f jal x0, 362 + 20802500 20787 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20803500 20788 1c001d36 e69ff06f jal x0, -408 + 20806500 20791 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20822500 20807 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20823500 20808 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20824500 20809 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104ff760 PA:104ff7bc + 20825500 20810 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:104ff760 PA:104ff7b8 + 20826500 20811 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:104ff760 PA:104ff7b4 + 20827500 20812 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:104ff760 PA:104ff7b0 + 20828500 20813 1c001bb0 04c12983 lw x19, 76(x2) x19=00000005 x2:104ff760 PA:104ff7ac + 20829500 20814 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:104ff760 PA:104ff7a8 + 20830500 20815 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:104ff760 PA:104ff7a4 + 20831500 20816 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:104ff760 PA:104ff7a0 + 20832500 20817 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:104ff760 PA:104ff79c + 20833500 20818 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:104ff760 PA:104ff798 + 20834500 20819 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:104ff760 PA:104ff794 + 20835500 20820 1c001bbe 06010113 addi x2, x2, 96 x2=104ff7c0 x2:104ff760 + 20836500 20821 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20838500 20823 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:104ff7c0 PA:104ff7dc + 20839500 20824 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20840500 20825 1c001838 04010113 addi x2, x2, 64 x2=104ff800 x2:104ff7c0 + 20841500 20826 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 20843500 20828 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_6.log b/sw/scripts/tracevis/example/traces/trace_core_01_6.log new file mode 100644 index 0000000..05121da --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_6.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000026 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000006 x10:00000026 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000026 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000006 + 12641500 12626 1c0000a6 05a0206f jal x0, 8282 + 12659500 12644 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12660500 12645 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12661500 12646 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12662500 12647 1c00210c 0e059163 bne x11, x0, 226 x11:00000006 + 12714500 12699 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 12715500 12700 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000026 + 12716500 12701 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000006 x19:00000026 + 12717500 12702 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 12734500 12719 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 12735500 12720 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 12736500 12721 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 12737500 12722 1c00220a 0060006f jal x0, 6 + 12757500 12742 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 17807500 17792 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 17825500 17810 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 17826500 17811 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 17844500 17829 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 17845500 17830 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 17847500 17832 1c00222c 08096283 p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080 + 17871500 17856 1c002230 02a98533 mul x10, x19, x10 x10=00001800 x19:00000006 x10:00000400 + 17872500 17857 1c002234 00550133 add x2, x10, x5 x2=104ffc00 x10:00001800 x5:104fe400 + 17873500 17858 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 17875500 17860 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 17911500 17896 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 17919500 17904 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 17920500 17905 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 17921500 17906 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 17922500 17907 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 17940500 17925 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000026 + 17957500 17942 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17958500 17943 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000001 x12:00000026 + 17959500 17944 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001 + 17960500 17945 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000006 x12:00000026 + 17961500 17946 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17962500 17947 1c0009d4 63d0006f jal x0, 3644 + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104ffbc0 x2:104ffc00 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104ffbc0 PA:104ffbe4 + 17987500 17972 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17988500 17973 1c001818 02c12423 sw x12, 40(x2) x12:00000006 x2:104ffbc0 PA:104ffbe8 + 17989500 17974 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104ffbc0 PA:104ffbec + 17990500 17975 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17991500 17976 1c00181e 02410693 addi x13, x2, 36 x13=104ffbe4 x2:104ffbc0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:104ffbc0 PA:104ffbdc + 18011500 17996 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:104ffbc0 PA:104ffbf0 + 18012500 17997 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:104ffbc0 PA:104ffbf4 + 18013500 17998 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104ffbc0 PA:104ffbf8 + 18014500 17999 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104ffbc0 PA:104ffbfc + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104ffbe4 x2:104ffbc0 PA:104ffbcc + 18031500 18016 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104ffb60 x2:104ffbc0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104ffb78 x2:104ffb60 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:104ffb60 PA:104ffbb8 + 18050500 18035 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:104ffb60 PA:104ffbb0 + 18051500 18036 1c001b78 05312623 sw x19, 76(x2) x19:00000006 x2:104ffb60 PA:104ffbac + 18052500 18037 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:104ffb60 PA:104ffba8 + 18053500 18038 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:104ffb60 PA:104ffba4 + 18054500 18039 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:104ffb60 PA:104ffba0 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:104ffb60 PA:104ffb9c + 18067500 18052 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104ffb60 PA:104ffbbc + 18068500 18053 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:104ffb60 PA:104ffbb4 + 18069500 18054 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:104ffb60 PA:104ffb98 + 18070500 18055 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:104ffb60 PA:104ffb94 + 18071500 18056 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18072500 18057 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18073500 18058 1c001b8e 00d00433 add x8, x0, x13 x8=104ffbe4 x13:104ffbe4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104ffb78 x2:104ffb60 PA:104ffb74 + 18095500 18080 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18096500 18081 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18097500 18082 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18098500 18083 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18136500 18121 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18137500 18122 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18145500 18130 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18146500 18131 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18147500 18132 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1040b0 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18263500 18248 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18264500 18249 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18267500 18252 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18268500 18253 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18269500 18254 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18271500 18256 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18272500 18257 1c001778 fddff06f jal x0, -36 + 18274500 18259 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18275500 18260 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18276500 18261 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18277500 18262 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18278500 18263 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18279500 18264 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18280500 18265 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18281500 18266 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18282500 18267 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18283500 18268 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040b0 + 18287500 18272 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18288500 18273 1c001bca 16a0006f jal x0, 362 + 18290500 18275 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18291500 18276 1c001d36 e69ff06f jal x0, -408 + 18294500 18279 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18311500 18296 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18312500 18297 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18315500 18300 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18316500 18301 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18317500 18302 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18319500 18304 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18320500 18305 1c001778 fddff06f jal x0, -36 + 18322500 18307 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18323500 18308 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18324500 18309 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18325500 18310 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18326500 18311 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18327500 18312 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18328500 18313 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18329500 18314 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18330500 18315 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18331500 18316 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1040b0 + 18335500 18320 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18336500 18321 1c001bca 16a0006f jal x0, 362 + 18338500 18323 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18339500 18324 1c001d36 e69ff06f jal x0, -408 + 18342500 18327 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18361500 18346 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18362500 18347 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18365500 18350 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18366500 18351 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18367500 18352 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18369500 18354 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18370500 18355 1c001778 fddff06f jal x0, -36 + 18372500 18357 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18373500 18358 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18374500 18359 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18375500 18360 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18376500 18361 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18377500 18362 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18378500 18363 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18379500 18364 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18380500 18365 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18381500 18366 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040b0 + 18385500 18370 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18386500 18371 1c001bca 16a0006f jal x0, 362 + 18388500 18373 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18389500 18374 1c001d36 e69ff06f jal x0, -408 + 18392500 18377 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18406500 18391 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18407500 18392 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18410500 18395 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18411500 18396 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18412500 18397 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18414500 18399 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18415500 18400 1c001778 fddff06f jal x0, -36 + 18417500 18402 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18418500 18403 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18419500 18404 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18420500 18405 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18421500 18406 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18422500 18407 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18423500 18408 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18424500 18409 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18425500 18410 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18426500 18411 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b0 + 18430500 18415 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18431500 18416 1c001bca 16a0006f jal x0, 362 + 18433500 18418 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18434500 18419 1c001d36 e69ff06f jal x0, -408 + 18437500 18422 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18451500 18436 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18452500 18437 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18455500 18440 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18456500 18441 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18457500 18442 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18459500 18444 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18460500 18445 1c001778 fddff06f jal x0, -36 + 18462500 18447 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18463500 18448 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18464500 18449 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18465500 18450 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18466500 18451 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18467500 18452 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18468500 18453 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18469500 18454 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18470500 18455 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18471500 18456 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1040b0 + 18475500 18460 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18476500 18461 1c001bca 16a0006f jal x0, 362 + 18478500 18463 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18479500 18464 1c001d36 e69ff06f jal x0, -408 + 18482500 18467 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18497500 18482 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18498500 18483 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18501500 18486 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18502500 18487 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18503500 18488 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18505500 18490 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18506500 18491 1c001778 fddff06f jal x0, -36 + 18508500 18493 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18509500 18494 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18510500 18495 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18511500 18496 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18512500 18497 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18513500 18498 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18514500 18499 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18515500 18500 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18516500 18501 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18517500 18502 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1040b0 + 18521500 18506 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18522500 18507 1c001bca 16a0006f jal x0, 362 + 18524500 18509 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18525500 18510 1c001d36 e69ff06f jal x0, -408 + 18528500 18513 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18542500 18527 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18543500 18528 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18546500 18531 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18547500 18532 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18548500 18533 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18550500 18535 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18551500 18536 1c001778 fddff06f jal x0, -36 + 18553500 18538 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18554500 18539 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18555500 18540 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18556500 18541 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18557500 18542 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18558500 18543 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18559500 18544 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18560500 18545 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18561500 18546 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18562500 18547 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1040b0 + 18566500 18551 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18567500 18552 1c001bca 16a0006f jal x0, 362 + 18569500 18554 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18570500 18555 1c001d36 e69ff06f jal x0, -408 + 18573500 18558 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18588500 18573 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18589500 18574 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18592500 18577 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18593500 18578 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18594500 18579 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18596500 18581 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18597500 18582 1c001778 fddff06f jal x0, -36 + 18599500 18584 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18600500 18585 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18601500 18586 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18602500 18587 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18603500 18588 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18604500 18589 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18605500 18590 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18606500 18591 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18607500 18592 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18608500 18593 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b0 + 18612500 18597 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18613500 18598 1c001bca 16a0006f jal x0, 362 + 18615500 18600 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18616500 18601 1c001d36 e69ff06f jal x0, -408 + 18619500 18604 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18634500 18619 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18635500 18620 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18638500 18623 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18639500 18624 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18640500 18625 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18642500 18627 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18643500 18628 1c001778 fddff06f jal x0, -36 + 18645500 18630 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18646500 18631 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18647500 18632 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18648500 18633 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18649500 18634 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18650500 18635 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18651500 18636 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18652500 18637 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18653500 18638 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18654500 18639 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1040b0 + 18658500 18643 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18659500 18644 1c001bca 16a0006f jal x0, 362 + 18661500 18646 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18662500 18647 1c001d36 e69ff06f jal x0, -408 + 18665500 18650 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18681500 18666 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18682500 18667 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18685500 18670 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18686500 18671 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18687500 18672 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18689500 18674 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18690500 18675 1c001778 fddff06f jal x0, -36 + 18692500 18677 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18693500 18678 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18694500 18679 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18695500 18680 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18696500 18681 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18697500 18682 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18698500 18683 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18699500 18684 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18700500 18685 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18701500 18686 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1040b0 + 18705500 18690 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18706500 18691 1c001bca 16a0006f jal x0, 362 + 18708500 18693 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18709500 18694 1c001d36 e69ff06f jal x0, -408 + 18712500 18697 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18728500 18713 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18729500 18714 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18732500 18717 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18733500 18718 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18734500 18719 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18736500 18721 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18737500 18722 1c001778 fddff06f jal x0, -36 + 18739500 18724 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18740500 18725 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18741500 18726 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18742500 18727 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18743500 18728 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18744500 18729 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18745500 18730 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18746500 18731 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18747500 18732 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18748500 18733 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1040b0 + 18752500 18737 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18753500 18738 1c001bca 16a0006f jal x0, 362 + 18755500 18740 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18756500 18741 1c001d36 e69ff06f jal x0, -408 + 18759500 18744 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18777500 18762 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18778500 18763 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18781500 18766 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18782500 18767 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18783500 18768 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18785500 18770 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18786500 18771 1c001778 fddff06f jal x0, -36 + 18788500 18773 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18789500 18774 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18790500 18775 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18791500 18776 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18792500 18777 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18793500 18778 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18794500 18779 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18795500 18780 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18796500 18781 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18797500 18782 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040b0 + 18801500 18786 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18802500 18787 1c001bca 16a0006f jal x0, 362 + 18804500 18789 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18805500 18790 1c001d36 e69ff06f jal x0, -408 + 18808500 18793 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18823500 18808 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18824500 18809 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18827500 18812 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18828500 18813 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18829500 18814 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18831500 18816 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18832500 18817 1c001778 fddff06f jal x0, -36 + 18834500 18819 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18835500 18820 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18836500 18821 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18837500 18822 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18838500 18823 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18839500 18824 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18840500 18825 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18841500 18826 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18842500 18827 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18843500 18828 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b0 + 18847500 18832 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18848500 18833 1c001bca 16a0006f jal x0, 362 + 18850500 18835 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18851500 18836 1c001d36 e69ff06f jal x0, -408 + 18854500 18839 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18872500 18857 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18873500 18858 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18876500 18861 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18877500 18862 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18878500 18863 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18880500 18865 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18881500 18866 1c001778 fddff06f jal x0, -36 + 18883500 18868 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18884500 18869 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 18885500 18870 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18886500 18871 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 18887500 18872 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 18888500 18873 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 18889500 18874 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 18890500 18875 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 18891500 18876 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18892500 18877 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1040b0 + 18896500 18881 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18897500 18882 1c001bca 16a0006f jal x0, 362 + 18899500 18884 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18900500 18885 1c001d36 e69ff06f jal x0, -408 + 18903500 18888 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18917500 18902 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18918500 18903 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18921500 18906 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18924500 18909 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104ffb60 PA:104ffb64 + 18929500 18914 1c001bd0 00012423 sw x0, 8(x2) x2:104ffb60 PA:104ffb68 + 18935500 18920 1c001bd2 00010623 sb x0, 12(x2) x2:104ffb60 PA:104ffb6c + 18936500 18921 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18937500 18922 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104ffb60 PA:104ffb64 + 18958500 18943 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18959500 18944 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18960500 18945 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18961500 18946 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18962500 18947 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19005500 18990 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19006500 18991 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19021500 19006 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19022500 19007 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19023500 19008 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104ffb60 PA:104ffb70 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104ffbe8 x8:104ffbe4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104ffbe4 PA:104ffbe4 + 19405500 19390 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104ffb64 x2:104ffb60 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104ffb78 x11:104ffb64 PA:104ffb74 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ffb64 PA:104ffb70 + 19533500 19518 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19534500 19519 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19568500 19553 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19569500 19554 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19570500 19555 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19571500 19556 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19574500 19559 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ffb64 PA:104ffb70 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104ffb78 PA:104ffb78 + 19747500 19732 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19748500 19733 1c001a5e 00168693 addi x13, x13, 1 x13=104ffb79 x13:104ffb78 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104ffb79 PA:104ffb79 + 19768500 19753 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19769500 19754 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104ffb64 x2:104ffb60 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104ffb40 x2:104ffb60 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104ffbe4 x2:104ffb40 PA:104ffb58 + 19819500 19804 1c001a66 01062783 lw x15, 16(x12) x15=104ffb78 x12:104ffb64 PA:104ffb74 + 19820500 19805 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104ffb64 PA:104ffb68 + 19821500 19806 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104ffb40 PA:104ffb54 + 19822500 19807 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104ffb40 PA:104ffb50 + 19823500 19808 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104ffb40 PA:104ffb4c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104ffb40 PA:104ffb5c + 19842500 19827 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104ffb40 PA:104ffb48 + 19843500 19828 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19844500 19829 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19845500 19830 1c001a78 00c004b3 add x9, x0, x12 x9=104ffb64 x12:104ffb64 + 19846500 19831 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104ffb79 x15:104ffb78 PA:104ffb78 + 19848500 19833 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104ffb64 PA:104ffb6c + 19868500 19853 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19871500 19856 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104ffb64 PA:104ffb6c + 19963500 19948 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 19983500 19968 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19984500 19969 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104ffb78 x9:104ffb64 PA:104ffb74 + 20027500 20012 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104ffb79 x20:104ffb78 PA:104ffb78 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a1040b0 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104ffb7a x20:104ffb79 PA:104ffb79 + 20106500 20091 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20107500 20092 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 20109500 20094 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20110500 20095 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104ffb40 PA:104ffb5c + 20129500 20114 1c001b02 01812403 lw x8, 24(x2) x8=104ffbe4 x2:104ffb40 PA:104ffb58 + 20130500 20115 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104ffb40 PA:104ffb54 + 20131500 20116 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104ffb40 PA:104ffb50 + 20132500 20117 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104ffb40 PA:104ffb4c + 20133500 20118 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104ffb40 PA:104ffb48 + 20134500 20119 1c001b0c 02010113 addi x2, x2, 32 x2=104ffb60 x2:104ffb40 + 20135500 20120 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104ffbe8 x24:104ffbe8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20186500 20171 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20187500 20172 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20190500 20175 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20191500 20176 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20192500 20177 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20194500 20179 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20195500 20180 1c001778 fddff06f jal x0, -36 + 20197500 20182 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20198500 20183 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 20199500 20184 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20200500 20185 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 20201500 20186 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 20202500 20187 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 20203500 20188 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 20204500 20189 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 20205500 20190 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20206500 20191 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040b0 + 20210500 20195 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20211500 20196 1c001bca 16a0006f jal x0, 362 + 20213500 20198 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20214500 20199 1c001d36 e69ff06f jal x0, -408 + 20217500 20202 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20234500 20219 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20235500 20220 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20238500 20223 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20239500 20224 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20240500 20225 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20242500 20227 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20243500 20228 1c001778 fddff06f jal x0, -36 + 20245500 20230 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20246500 20231 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 20247500 20232 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20248500 20233 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 20249500 20234 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 20250500 20235 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 20251500 20236 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 20252500 20237 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 20253500 20238 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20254500 20239 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b0 + 20258500 20243 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20259500 20244 1c001bca 16a0006f jal x0, 362 + 20261500 20246 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20262500 20247 1c001d36 e69ff06f jal x0, -408 + 20265500 20250 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20283500 20268 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20284500 20269 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20287500 20272 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20290500 20275 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104ffb60 PA:104ffb64 + 20292500 20277 1c001bd0 00012423 sw x0, 8(x2) x2:104ffb60 PA:104ffb68 + 20293500 20278 1c001bd2 00010623 sb x0, 12(x2) x2:104ffb60 PA:104ffb6c + 20294500 20279 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20295500 20280 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20296500 20281 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20297500 20282 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104ffb60 PA:104ffb64 + 20298500 20283 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20299500 20284 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20300500 20285 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20301500 20286 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20302500 20287 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20303500 20288 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20304500 20289 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20305500 20290 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20320500 20305 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20321500 20306 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20324500 20309 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20325500 20310 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20326500 20311 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20329500 20314 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20332500 20317 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20335500 20320 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20338500 20323 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20339500 20324 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20340500 20325 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20341500 20326 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20344500 20329 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20345500 20330 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20348500 20333 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20349500 20334 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20352500 20337 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20357500 20342 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20358500 20343 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20361500 20346 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20362500 20347 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20363500 20348 1c001f42 e09ff06f jal x0, -504 + 20365500 20350 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20366500 20351 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104ffb60 PA:104ffb70 + 20367500 20352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20370500 20355 1c001e34 00440c13 addi x24, x8, 4 x24=104ffbec x8:104ffbe8 + 20371500 20356 1c001e38 00042503 lw x10, 0(x8) x10=00000006 x8:104ffbe8 PA:104ffbe8 + 20372500 20357 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20375500 20360 1c001e54 00055863 bge x10, x0, 16 x10:00000006 + 20378500 20363 1c001e64 00410593 addi x11, x2, 4 x11=104ffb64 x2:104ffb60 + 20379500 20364 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20381500 20366 1c0019fe 0105a683 lw x13, 16(x11) x13=104ffb78 x11:104ffb64 PA:104ffb74 + 20382500 20367 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ffb64 PA:104ffb70 + 20383500 20368 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20384500 20369 1c001a04 02f55633 divu x12, x10, x15 x12=00000006 x10:00000006 x15:00000001 + 20418500 20403 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000006 x14:0000000a + 20419500 20404 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20420500 20405 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20421500 20406 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20424500 20409 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104ffb64 PA:104ffb70 + 20425500 20410 1c001a20 02f55833 divu x16, x10, x15 x16=00000006 x10:00000006 x15:00000001 + 20459500 20444 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000006 x15:00000001 + 20493500 20478 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20524500 20509 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20525500 20510 1c001a2e 01004663 blt x0, x16, 12 x16:00000006 + 20528500 20513 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20530500 20515 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000006 + 20533500 20518 1c001a56 01070733 add x14, x14, x16 x14=00000036 x14:00000030 x16:00000006 + 20534500 20519 1c001a58 00e68023 sb x14, 0(x13) x14:00000036 x13:104ffb78 PA:104ffb78 + 20535500 20520 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20536500 20521 1c001a5e 00168693 addi x13, x13, 1 x13=104ffb79 x13:104ffb78 + 20537500 20522 1c001a60 fb1ff06f jal x0, -80 + 20539500 20524 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20540500 20525 1c001a12 00068023 sb x0, 0(x13) x13:104ffb79 PA:104ffb79 + 20541500 20526 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20543500 20528 1c001e68 f17ff06f jal x0, -234 + 20545500 20530 1c001d7e 00410613 addi x12, x2, 4 x12=104ffb64 x2:104ffb60 + 20546500 20531 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20547500 20532 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20548500 20533 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20550500 20535 1c001a62 fe010113 addi x2, x2, -32 x2=104ffb40 x2:104ffb60 + 20551500 20536 1c001a64 00812c23 sw x8, 24(x2) x8:104ffbe8 x2:104ffb40 PA:104ffb58 + 20552500 20537 1c001a66 01062783 lw x15, 16(x12) x15=104ffb78 x12:104ffb64 PA:104ffb74 + 20553500 20538 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104ffb64 PA:104ffb68 + 20554500 20539 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104ffb40 PA:104ffb54 + 20555500 20540 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104ffb40 PA:104ffb50 + 20556500 20541 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104ffb40 PA:104ffb4c + 20557500 20542 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104ffb40 PA:104ffb5c + 20558500 20543 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104ffb40 PA:104ffb48 + 20559500 20544 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20560500 20545 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20561500 20546 1c001a78 00c004b3 add x9, x0, x12 x9=104ffb64 x12:104ffb64 + 20562500 20547 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000036 x15=104ffb79 x15:104ffb78 PA:104ffb78 + 20564500 20549 1c001a7e 00070363 beq x14, x0, 6 x14:00000036 + 20565500 20550 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20566500 20551 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104ffb64 PA:104ffb6c + 20568500 20553 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20571500 20556 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 20573500 20558 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20574500 20559 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20577500 20562 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20578500 20563 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20579500 20564 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20582500 20567 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20583500 20568 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20584500 20569 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20585500 20570 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20586500 20571 1c001b36 f71ff06f jal x0, -144 + 20588500 20573 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104ffb64 PA:104ffb6c + 20590500 20575 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20593500 20578 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 20595500 20580 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20596500 20581 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20599500 20584 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 20600500 20585 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20601500 20586 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20602500 20587 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20603500 20588 1c001ae8 0104aa03 lw x20, 16(x9) x20=104ffb78 x9:104ffb64 PA:104ffb74 + 20605500 20590 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000036 x20=104ffb79 x20:104ffb78 PA:104ffb78 + 20607500 20592 1c001af0 06059763 bne x11, x0, 110 x11:00000036 + 20610500 20595 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20611500 20596 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20613500 20598 1c001776 00b00533 add x10, x0, x11 x10=00000036 x11:00000036 + 20614500 20599 1c001778 fddff06f jal x0, -36 + 20616500 20601 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20617500 20602 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 20618500 20603 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20619500 20604 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 20620500 20605 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 20621500 20606 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 20622500 20607 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 20623500 20608 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 20624500 20609 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20625500 20610 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000036 x14:1a104000 PA:1a1040b0 + 20629500 20614 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20630500 20615 1c001b62 f8bff06f jal x0, -118 + 20632500 20617 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104ffb7a x20:104ffb79 PA:104ffb79 + 20634500 20619 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20635500 20620 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104ffb64 PA:104ffb64 + 20637500 20622 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20638500 20623 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20641500 20626 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104ffb40 PA:104ffb5c + 20642500 20627 1c001b02 01812403 lw x8, 24(x2) x8=104ffbe8 x2:104ffb40 PA:104ffb58 + 20643500 20628 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104ffb40 PA:104ffb54 + 20644500 20629 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104ffb40 PA:104ffb50 + 20645500 20630 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104ffb40 PA:104ffb4c + 20646500 20631 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104ffb40 PA:104ffb48 + 20647500 20632 1c001b0c 02010113 addi x2, x2, 32 x2=104ffb60 x2:104ffb40 + 20648500 20633 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20650500 20635 1c001d86 01800433 add x8, x0, x24 x8=104ffbec x24:104ffbec + 20651500 20636 1c001d88 fadff06f jal x0, -84 + 20653500 20638 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20654500 20639 1c001d36 e69ff06f jal x0, -408 + 20657500 20642 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20680500 20665 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20681500 20666 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20684500 20669 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20685500 20670 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20686500 20671 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20688500 20673 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20689500 20674 1c001778 fddff06f jal x0, -36 + 20691500 20676 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20692500 20677 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 20693500 20678 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20694500 20679 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 20695500 20680 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 20696500 20681 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 20697500 20682 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 20698500 20683 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 20699500 20684 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20700500 20685 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1040b0 + 20704500 20689 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20705500 20690 1c001bca 16a0006f jal x0, 362 + 20707500 20692 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20708500 20693 1c001d36 e69ff06f jal x0, -408 + 20711500 20696 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20727500 20712 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20728500 20713 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20731500 20716 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20732500 20717 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20733500 20718 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20735500 20720 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20736500 20721 1c001778 fddff06f jal x0, -36 + 20738500 20723 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20739500 20724 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 20740500 20725 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20741500 20726 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 20742500 20727 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 20743500 20728 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 20744500 20729 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 20745500 20730 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 20746500 20731 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20747500 20732 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1040b0 + 20751500 20736 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20752500 20737 1c001bca 16a0006f jal x0, 362 + 20754500 20739 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20755500 20740 1c001d36 e69ff06f jal x0, -408 + 20758500 20743 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20773500 20758 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20774500 20759 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20777500 20762 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20778500 20763 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20779500 20764 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20781500 20766 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20782500 20767 1c001778 fddff06f jal x0, -36 + 20784500 20769 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20785500 20770 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000026 + 20786500 20771 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20787500 20772 1c00175e 00379713 slli x14, x15, 0x3 x14=00000130 x15:00000026 + 20788500 20773 1c001762 00279793 slli x15, x15, 0x2 x15=00000098 x15:00000026 + 20789500 20774 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000130 + 20790500 20775 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:00000098 x13:00001f80 + 20791500 20776 1c00176a 00e787b3 add x15, x15, x14 x15=000000b0 x15:00000080 x14:00000030 + 20792500 20777 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20793500 20778 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1040b0 + 20797500 20782 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20798500 20783 1c001bca 16a0006f jal x0, 362 + 20800500 20785 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20801500 20786 1c001d36 e69ff06f jal x0, -408 + 20804500 20789 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20818500 20803 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20819500 20804 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20820500 20805 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104ffb60 PA:104ffbbc + 20821500 20806 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:104ffb60 PA:104ffbb8 + 20822500 20807 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:104ffb60 PA:104ffbb4 + 20823500 20808 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:104ffb60 PA:104ffbb0 + 20824500 20809 1c001bb0 04c12983 lw x19, 76(x2) x19=00000006 x2:104ffb60 PA:104ffbac + 20825500 20810 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:104ffb60 PA:104ffba8 + 20826500 20811 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:104ffb60 PA:104ffba4 + 20827500 20812 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:104ffb60 PA:104ffba0 + 20828500 20813 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:104ffb60 PA:104ffb9c + 20831500 20816 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:104ffb60 PA:104ffb98 + 20832500 20817 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:104ffb60 PA:104ffb94 + 20833500 20818 1c001bbe 06010113 addi x2, x2, 96 x2=104ffbc0 x2:104ffb60 + 20834500 20819 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20836500 20821 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:104ffbc0 PA:104ffbdc + 20837500 20822 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20838500 20823 1c001838 04010113 addi x2, x2, 64 x2=104ffc00 x2:104ffbc0 + 20839500 20824 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 20841500 20826 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_01_7.log b/sw/scripts/tracevis/example/traces/trace_core_01_7.log new file mode 100644 index 0000000..4eb4dde --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_01_7.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 12603500 12588 1c000080 0180006f jal x0, 24 + 12621500 12606 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000027 + 12622500 12607 1c00009c 01f57593 andi x11, x10, 31 x11=00000007 x10:00000027 + 12639500 12624 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000001 x10:00000027 + 12640500 12625 1c0000a2 00058463 beq x11, x0, 8 x11:00000007 + 12641500 12626 1c0000a6 05a0206f jal x0, 8282 + 12659500 12644 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 12660500 12645 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 12661500 12646 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 12662500 12647 1c00210c 0e059163 bne x11, x0, 226 x11:00000007 + 12714500 12699 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 12715500 12700 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000027 + 12716500 12701 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000007 x19:00000027 + 12717500 12702 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 12734500 12719 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 12735500 12720 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 12736500 12721 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 12737500 12722 1c00220a 0060006f jal x0, 6 + 12757500 12742 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 17807500 17792 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 17825500 17810 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 17826500 17811 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 17844500 17829 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 17845500 17830 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 17847500 17832 1c00222c 08096283 p.elw x5, 128(x18) x5=104fe400 x18:1b204000 PA:1b204080 + 17871500 17856 1c002230 02a98533 mul x10, x19, x10 x10=00001c00 x19:00000007 x10:00000400 + 17872500 17857 1c002234 00550133 add x2, x10, x5 x2=10500000 x10:00001c00 x5:104fe400 + 17873500 17858 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 17875500 17860 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 17911500 17896 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 17919500 17904 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 17920500 17905 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 17921500 17906 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 17922500 17907 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 17940500 17925 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000027 + 17957500 17942 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 17958500 17943 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000001 x12:00000027 + 17959500 17944 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000001 x11:00000001 + 17960500 17945 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000007 x12:00000027 + 17961500 17946 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 17962500 17947 1c0009d4 63d0006f jal x0, 3644 + 17980500 17965 1c001810 fc010113 addi x2, x2, -64 x2=104fffc0 x2:10500000 + 17981500 17966 1c001812 02b12223 sw x11, 36(x2) x11:00000001 x2:104fffc0 PA:104fffe4 + 17988500 17973 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 17989500 17974 1c001818 02c12423 sw x12, 40(x2) x12:00000007 x2:104fffc0 PA:104fffe8 + 17990500 17975 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:104fffc0 PA:104fffec + 17991500 17976 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 17992500 17977 1c00181e 02410693 addi x13, x2, 36 x13=104fffe4 x2:104fffc0 + 18002500 17987 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18003500 17988 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18004500 17989 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:104fffc0 PA:104fffdc + 18010500 17995 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:104fffc0 PA:104ffff0 + 18011500 17996 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:104fffc0 PA:104ffff4 + 18012500 17997 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:104fffc0 PA:104ffff8 + 18013500 17998 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:104fffc0 PA:104ffffc + 18024500 18009 1c001830 00d12623 sw x13, 12(x2) x13:104fffe4 x2:104fffc0 PA:104fffcc + 18029500 18014 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18043500 18028 1c001b70 fa010113 addi x2, x2, -96 x2=104fff60 x2:104fffc0 + 18044500 18029 1c001b72 01810793 addi x15, x2, 24 x15=104fff78 x2:104fff60 + 18045500 18030 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:104fff60 PA:104fffb8 + 18051500 18036 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:104fff60 PA:104fffb0 + 18052500 18037 1c001b78 05312623 sw x19, 76(x2) x19:00000007 x2:104fff60 PA:104fffac + 18053500 18038 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:104fff60 PA:104fffa8 + 18054500 18039 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:104fff60 PA:104fffa4 + 18055500 18040 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:104fff60 PA:104fffa0 + 18066500 18051 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:104fff60 PA:104fff9c + 18068500 18053 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:104fff60 PA:104fffbc + 18069500 18054 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:104fff60 PA:104fffb4 + 18070500 18055 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:104fff60 PA:104fff98 + 18071500 18056 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:104fff60 PA:104fff94 + 18072500 18057 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18073500 18058 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18074500 18059 1c001b8e 00d00433 add x8, x0, x13 x8=104fffe4 x13:104fffe4 + 18089500 18074 1c001b90 00f12a23 sw x15, 20(x2) x15:104fff78 x2:104fff60 PA:104fff74 + 18096500 18081 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18097500 18082 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18098500 18083 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18099500 18084 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18110500 18095 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18138500 18123 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18139500 18124 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18146500 18131 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18147500 18132 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18148500 18133 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18165500 18150 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18166500 18151 1c001778 fddff06f jal x0, -36 + 18184500 18169 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18185500 18170 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18186500 18171 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18203500 18188 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18204500 18189 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18205500 18190 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18206500 18191 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18207500 18192 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18208500 18193 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18209500 18194 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1040b8 + 18213500 18198 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18214500 18199 1c001bca 16a0006f jal x0, 362 + 18232500 18217 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18233500 18218 1c001d36 e69ff06f jal x0, -408 + 18236500 18221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18265500 18250 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18266500 18251 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18269500 18254 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18270500 18255 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18271500 18256 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18273500 18258 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18274500 18259 1c001778 fddff06f jal x0, -36 + 18276500 18261 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18277500 18262 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18278500 18263 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18279500 18264 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18280500 18265 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18281500 18266 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18282500 18267 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18283500 18268 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18284500 18269 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18285500 18270 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040b8 + 18289500 18274 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18290500 18275 1c001bca 16a0006f jal x0, 362 + 18292500 18277 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18293500 18278 1c001d36 e69ff06f jal x0, -408 + 18296500 18281 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18313500 18298 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18314500 18299 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18317500 18302 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18318500 18303 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18319500 18304 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18321500 18306 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18322500 18307 1c001778 fddff06f jal x0, -36 + 18324500 18309 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18325500 18310 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18326500 18311 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18327500 18312 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18328500 18313 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18329500 18314 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18330500 18315 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18331500 18316 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18332500 18317 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18333500 18318 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1040b8 + 18337500 18322 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18338500 18323 1c001bca 16a0006f jal x0, 362 + 18340500 18325 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18341500 18326 1c001d36 e69ff06f jal x0, -408 + 18344500 18329 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18363500 18348 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18364500 18349 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18367500 18352 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18368500 18353 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18369500 18354 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18371500 18356 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18372500 18357 1c001778 fddff06f jal x0, -36 + 18374500 18359 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18375500 18360 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18376500 18361 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18377500 18362 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18378500 18363 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18379500 18364 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18380500 18365 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18381500 18366 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18382500 18367 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18383500 18368 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040b8 + 18387500 18372 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18388500 18373 1c001bca 16a0006f jal x0, 362 + 18390500 18375 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18391500 18376 1c001d36 e69ff06f jal x0, -408 + 18394500 18379 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18408500 18393 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18409500 18394 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18412500 18397 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18413500 18398 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18414500 18399 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18416500 18401 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18417500 18402 1c001778 fddff06f jal x0, -36 + 18419500 18404 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18420500 18405 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18421500 18406 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18422500 18407 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18423500 18408 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18424500 18409 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18425500 18410 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18426500 18411 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18427500 18412 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18428500 18413 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b8 + 18432500 18417 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18433500 18418 1c001bca 16a0006f jal x0, 362 + 18435500 18420 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18436500 18421 1c001d36 e69ff06f jal x0, -408 + 18439500 18424 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18454500 18439 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18455500 18440 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18458500 18443 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18459500 18444 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18460500 18445 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18462500 18447 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18463500 18448 1c001778 fddff06f jal x0, -36 + 18465500 18450 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18466500 18451 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18467500 18452 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18468500 18453 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18469500 18454 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18470500 18455 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18471500 18456 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18472500 18457 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18473500 18458 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18474500 18459 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1040b8 + 18478500 18463 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18479500 18464 1c001bca 16a0006f jal x0, 362 + 18481500 18466 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 18482500 18467 1c001d36 e69ff06f jal x0, -408 + 18485500 18470 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 18500500 18485 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 18501500 18486 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 18504500 18489 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 18505500 18490 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18506500 18491 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18508500 18493 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 18509500 18494 1c001778 fddff06f jal x0, -36 + 18511500 18496 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18512500 18497 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18513500 18498 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18514500 18499 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18515500 18500 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18516500 18501 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18517500 18502 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18518500 18503 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18519500 18504 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18520500 18505 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1040b8 + 18524500 18509 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18525500 18510 1c001bca 16a0006f jal x0, 362 + 18527500 18512 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 18528500 18513 1c001d36 e69ff06f jal x0, -408 + 18531500 18516 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 18548500 18533 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 18549500 18534 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 18552500 18537 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 18553500 18538 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18554500 18539 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18556500 18541 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 18557500 18542 1c001778 fddff06f jal x0, -36 + 18559500 18544 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18560500 18545 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18561500 18546 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18562500 18547 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18563500 18548 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18564500 18549 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18565500 18550 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18566500 18551 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18567500 18552 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18568500 18553 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1040b8 + 18572500 18557 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18573500 18558 1c001bca 16a0006f jal x0, 362 + 18575500 18560 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 18576500 18561 1c001d36 e69ff06f jal x0, -408 + 18579500 18564 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 18594500 18579 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 18595500 18580 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18598500 18583 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18599500 18584 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18600500 18585 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18602500 18587 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18603500 18588 1c001778 fddff06f jal x0, -36 + 18605500 18590 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18606500 18591 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18607500 18592 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18608500 18593 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18609500 18594 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18610500 18595 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18611500 18596 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18612500 18597 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18613500 18598 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18614500 18599 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b8 + 18618500 18603 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18619500 18604 1c001bca 16a0006f jal x0, 362 + 18621500 18606 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 18622500 18607 1c001d36 e69ff06f jal x0, -408 + 18625500 18610 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 18640500 18625 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 18641500 18626 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 18644500 18629 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 18645500 18630 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18646500 18631 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18648500 18633 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 18649500 18634 1c001778 fddff06f jal x0, -36 + 18651500 18636 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18652500 18637 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18653500 18638 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18654500 18639 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18655500 18640 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18656500 18641 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18657500 18642 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18658500 18643 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18659500 18644 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18660500 18645 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1040b8 + 18664500 18649 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18665500 18650 1c001bca 16a0006f jal x0, 362 + 18667500 18652 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 18668500 18653 1c001d36 e69ff06f jal x0, -408 + 18671500 18656 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 18686500 18671 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 18687500 18672 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 18690500 18675 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 18691500 18676 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18692500 18677 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18694500 18679 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 18695500 18680 1c001778 fddff06f jal x0, -36 + 18697500 18682 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18698500 18683 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18699500 18684 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18700500 18685 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18701500 18686 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18702500 18687 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18703500 18688 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18704500 18689 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18705500 18690 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18706500 18691 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1040b8 + 18710500 18695 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18711500 18696 1c001bca 16a0006f jal x0, 362 + 18713500 18698 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 18714500 18699 1c001d36 e69ff06f jal x0, -408 + 18717500 18702 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 18732500 18717 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 18733500 18718 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 18736500 18721 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 18737500 18722 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18738500 18723 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18740500 18725 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 18741500 18726 1c001778 fddff06f jal x0, -36 + 18743500 18728 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18744500 18729 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18745500 18730 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18746500 18731 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18747500 18732 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18748500 18733 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18749500 18734 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18750500 18735 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18751500 18736 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18752500 18737 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1040b8 + 18756500 18741 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18757500 18742 1c001bca 16a0006f jal x0, 362 + 18759500 18744 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 18760500 18745 1c001d36 e69ff06f jal x0, -408 + 18763500 18748 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 18779500 18764 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 18780500 18765 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18783500 18768 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18784500 18769 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18785500 18770 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18787500 18772 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18788500 18773 1c001778 fddff06f jal x0, -36 + 18790500 18775 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18791500 18776 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18792500 18777 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18793500 18778 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18794500 18779 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18795500 18780 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18796500 18781 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18797500 18782 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18798500 18783 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18799500 18784 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1040b8 + 18803500 18788 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18804500 18789 1c001bca 16a0006f jal x0, 362 + 18806500 18791 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 18807500 18792 1c001d36 e69ff06f jal x0, -408 + 18810500 18795 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 18827500 18812 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 18828500 18813 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18831500 18816 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18832500 18817 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18833500 18818 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18835500 18820 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18836500 18821 1c001778 fddff06f jal x0, -36 + 18838500 18823 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18839500 18824 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18840500 18825 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18841500 18826 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18842500 18827 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18843500 18828 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18844500 18829 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18845500 18830 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18846500 18831 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18847500 18832 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b8 + 18851500 18836 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18852500 18837 1c001bca 16a0006f jal x0, 362 + 18854500 18839 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 18855500 18840 1c001d36 e69ff06f jal x0, -408 + 18858500 18843 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 18874500 18859 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 18875500 18860 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 18878500 18863 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 18879500 18864 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18880500 18865 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18882500 18867 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 18883500 18868 1c001778 fddff06f jal x0, -36 + 18885500 18870 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18886500 18871 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 18887500 18872 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18888500 18873 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 18889500 18874 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 18890500 18875 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 18891500 18876 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 18892500 18877 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 18893500 18878 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18894500 18879 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1040b8 + 18898500 18883 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18899500 18884 1c001bca 16a0006f jal x0, 362 + 18901500 18886 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 18902500 18887 1c001d36 e69ff06f jal x0, -408 + 18905500 18890 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 18920500 18905 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 18921500 18906 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 18924500 18909 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 18927500 18912 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:104fff60 PA:104fff64 + 18948500 18933 1c001bd0 00012423 sw x0, 8(x2) x2:104fff60 PA:104fff68 + 18949500 18934 1c001bd2 00010623 sb x0, 12(x2) x2:104fff60 PA:104fff6c + 18950500 18935 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 18951500 18936 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 18952500 18937 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 18953500 18938 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fff60 PA:104fff64 + 18954500 18939 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 18955500 18940 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 18956500 18941 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 18957500 18942 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 18958500 18943 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 18974500 18959 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 18975500 18960 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 18976500 18961 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19007500 18992 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19008500 18993 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19021500 19006 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19022500 19007 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19023500 19008 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19043500 19028 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19066500 19051 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19069500 19054 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19088500 19073 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19105500 19090 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19106500 19091 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19107500 19092 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19128500 19113 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19145500 19130 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19165500 19150 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19166500 19151 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19214500 19199 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19242500 19227 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19261500 19246 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19262500 19247 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19304500 19289 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19322500 19307 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19323500 19308 1c001f42 e09ff06f jal x0, -504 + 19345500 19330 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19346500 19331 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fff60 PA:104fff70 + 19367500 19352 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19397500 19382 1c001e34 00440c13 addi x24, x8, 4 x24=104fffe8 x8:104fffe4 + 19398500 19383 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:104fffe4 PA:104fffe4 + 19402500 19387 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19453500 19438 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 19477500 19462 1c001e64 00410593 addi x11, x2, 4 x11=104fff64 x2:104fff60 + 19478500 19463 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 19507500 19492 1c0019fe 0105a683 lw x13, 16(x11) x13=104fff78 x11:104fff64 PA:104fff74 + 19527500 19512 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fff64 PA:104fff70 + 19534500 19519 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 19535500 19520 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 19569500 19554 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 19570500 19555 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 19571500 19556 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 19572500 19557 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 19575500 19560 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fff64 PA:104fff70 + 19594500 19579 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 19628500 19613 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 19662500 19647 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 19693500 19678 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 19694500 19679 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 19697500 19682 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 19719500 19704 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 19740500 19725 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 19741500 19726 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:104fff78 PA:104fff78 + 19748500 19733 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 19749500 19734 1c001a5e 00168693 addi x13, x13, 1 x13=104fff79 x13:104fff78 + 19760500 19745 1c001a60 fb1ff06f jal x0, -80 + 19762500 19747 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 19763500 19748 1c001a12 00068023 sb x0, 0(x13) x13:104fff79 PA:104fff79 + 19769500 19754 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 19770500 19755 1c001e68 f17ff06f jal x0, -234 + 19786500 19771 1c001d7e 00410613 addi x12, x2, 4 x12=104fff64 x2:104fff60 + 19806500 19791 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 19807500 19792 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19808500 19793 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 19810500 19795 1c001a62 fe010113 addi x2, x2, -32 x2=104fff40 x2:104fff60 + 19811500 19796 1c001a64 00812c23 sw x8, 24(x2) x8:104fffe4 x2:104fff40 PA:104fff58 + 19812500 19797 1c001a66 01062783 lw x15, 16(x12) x15=104fff78 x12:104fff64 PA:104fff74 + 19813500 19798 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fff64 PA:104fff68 + 19814500 19799 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:104fff40 PA:104fff54 + 19815500 19800 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fff40 PA:104fff50 + 19816500 19801 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fff40 PA:104fff4c + 19835500 19820 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fff40 PA:104fff5c + 19839500 19824 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fff40 PA:104fff48 + 19840500 19825 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19841500 19826 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19842500 19827 1c001a78 00c004b3 add x9, x0, x12 x9=104fff64 x12:104fff64 + 19843500 19828 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=104fff79 x15:104fff78 PA:104fff78 + 19845500 19830 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 19862500 19847 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 19863500 19848 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fff64 PA:104fff6c + 19869500 19854 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 19872500 19857 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 19886500 19871 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 19887500 19872 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 19906500 19891 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 19907500 19892 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 19908500 19893 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 19928500 19913 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 19929500 19914 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 19951500 19936 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 19952500 19937 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 19953500 19938 1c001b36 f71ff06f jal x0, -144 + 19955500 19940 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fff64 PA:104fff6c + 19962500 19947 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 19977500 19962 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 19984500 19969 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 19985500 19970 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20000500 19985 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 20018500 20003 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20019500 20004 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20020500 20005 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20021500 20006 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fff78 x9:104fff64 PA:104fff74 + 20028500 20013 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=104fff79 x20:104fff78 PA:104fff78 + 20039500 20024 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 20059500 20044 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20077500 20062 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20079500 20064 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 20080500 20065 1c001778 fddff06f jal x0, -36 + 20082500 20067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20083500 20068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 20084500 20069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20085500 20070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 20086500 20071 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 20087500 20072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 20088500 20073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 20089500 20074 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 20090500 20075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20091500 20076 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a1040b8 + 20095500 20080 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20096500 20081 1c001b62 f8bff06f jal x0, -118 + 20098500 20083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fff7a x20:104fff79 PA:104fff79 + 20105500 20090 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20106500 20091 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 20108500 20093 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20109500 20094 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20123500 20108 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fff40 PA:104fff5c + 20130500 20115 1c001b02 01812403 lw x8, 24(x2) x8=104fffe4 x2:104fff40 PA:104fff58 + 20131500 20116 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:104fff40 PA:104fff54 + 20132500 20117 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fff40 PA:104fff50 + 20133500 20118 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fff40 PA:104fff4c + 20134500 20119 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fff40 PA:104fff48 + 20135500 20120 1c001b0c 02010113 addi x2, x2, 32 x2=104fff60 x2:104fff40 + 20136500 20121 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20152500 20137 1c001d86 01800433 add x8, x0, x24 x8=104fffe8 x24:104fffe8 + 20153500 20138 1c001d88 fadff06f jal x0, -84 + 20155500 20140 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20156500 20141 1c001d36 e69ff06f jal x0, -408 + 20159500 20144 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20190500 20175 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20191500 20176 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20194500 20179 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20195500 20180 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20196500 20181 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20198500 20183 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20199500 20184 1c001778 fddff06f jal x0, -36 + 20201500 20186 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20202500 20187 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 20203500 20188 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20204500 20189 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 20205500 20190 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 20206500 20191 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 20207500 20192 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 20208500 20193 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 20209500 20194 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20210500 20195 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1040b8 + 20214500 20199 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20215500 20200 1c001bca 16a0006f jal x0, 362 + 20217500 20202 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20218500 20203 1c001d36 e69ff06f jal x0, -408 + 20221500 20206 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20238500 20223 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20239500 20224 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20242500 20227 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20243500 20228 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20244500 20229 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20246500 20231 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20247500 20232 1c001778 fddff06f jal x0, -36 + 20249500 20234 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20250500 20235 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 20251500 20236 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20252500 20237 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 20253500 20238 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 20254500 20239 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 20255500 20240 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 20256500 20241 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 20257500 20242 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20258500 20243 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1040b8 + 20262500 20247 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20263500 20248 1c001bca 16a0006f jal x0, 362 + 20265500 20250 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20266500 20251 1c001d36 e69ff06f jal x0, -408 + 20269500 20254 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20287500 20272 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20288500 20273 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20291500 20276 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20294500 20279 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:104fff60 PA:104fff64 + 20295500 20280 1c001bd0 00012423 sw x0, 8(x2) x2:104fff60 PA:104fff68 + 20296500 20281 1c001bd2 00010623 sb x0, 12(x2) x2:104fff60 PA:104fff6c + 20297500 20282 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20298500 20283 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20299500 20284 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20300500 20285 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:104fff60 PA:104fff64 + 20301500 20286 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20302500 20287 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20303500 20288 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20304500 20289 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20305500 20290 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20306500 20291 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20307500 20292 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20308500 20293 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20323500 20308 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20324500 20309 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20327500 20312 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20328500 20313 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20329500 20314 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20332500 20317 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20335500 20320 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20338500 20323 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20341500 20326 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20342500 20327 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20343500 20328 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20344500 20329 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20347500 20332 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20348500 20333 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20351500 20336 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20352500 20337 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20355500 20340 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20357500 20342 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20360500 20345 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20361500 20346 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20364500 20349 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20365500 20350 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20366500 20351 1c001f42 e09ff06f jal x0, -504 + 20368500 20353 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20369500 20354 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:104fff60 PA:104fff70 + 20370500 20355 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20373500 20358 1c001e34 00440c13 addi x24, x8, 4 x24=104fffec x8:104fffe8 + 20374500 20359 1c001e38 00042503 lw x10, 0(x8) x10=00000007 x8:104fffe8 PA:104fffe8 + 20375500 20360 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20378500 20363 1c001e54 00055863 bge x10, x0, 16 x10:00000007 + 20381500 20366 1c001e64 00410593 addi x11, x2, 4 x11=104fff64 x2:104fff60 + 20382500 20367 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20384500 20369 1c0019fe 0105a683 lw x13, 16(x11) x13=104fff78 x11:104fff64 PA:104fff74 + 20385500 20370 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fff64 PA:104fff70 + 20386500 20371 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20387500 20372 1c001a04 02f55633 divu x12, x10, x15 x12=00000007 x10:00000007 x15:00000001 + 20421500 20406 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000007 x14:0000000a + 20422500 20407 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20423500 20408 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20424500 20409 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20427500 20412 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:104fff64 PA:104fff70 + 20428500 20413 1c001a20 02f55833 divu x16, x10, x15 x16=00000007 x10:00000007 x15:00000001 + 20462500 20447 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000007 x15:00000001 + 20496500 20481 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20527500 20512 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20528500 20513 1c001a2e 01004663 blt x0, x16, 12 x16:00000007 + 20531500 20516 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20533500 20518 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000007 + 20536500 20521 1c001a56 01070733 add x14, x14, x16 x14=00000037 x14:00000030 x16:00000007 + 20537500 20522 1c001a58 00e68023 sb x14, 0(x13) x14:00000037 x13:104fff78 PA:104fff78 + 20539500 20524 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20540500 20525 1c001a5e 00168693 addi x13, x13, 1 x13=104fff79 x13:104fff78 + 20541500 20526 1c001a60 fb1ff06f jal x0, -80 + 20543500 20528 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20544500 20529 1c001a12 00068023 sb x0, 0(x13) x13:104fff79 PA:104fff79 + 20546500 20531 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20547500 20532 1c001e68 f17ff06f jal x0, -234 + 20549500 20534 1c001d7e 00410613 addi x12, x2, 4 x12=104fff64 x2:104fff60 + 20550500 20535 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20551500 20536 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20552500 20537 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20554500 20539 1c001a62 fe010113 addi x2, x2, -32 x2=104fff40 x2:104fff60 + 20555500 20540 1c001a64 00812c23 sw x8, 24(x2) x8:104fffe8 x2:104fff40 PA:104fff58 + 20556500 20541 1c001a66 01062783 lw x15, 16(x12) x15=104fff78 x12:104fff64 PA:104fff74 + 20557500 20542 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:104fff64 PA:104fff68 + 20558500 20543 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:104fff40 PA:104fff54 + 20559500 20544 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:104fff40 PA:104fff50 + 20560500 20545 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:104fff40 PA:104fff4c + 20562500 20547 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:104fff40 PA:104fff5c + 20563500 20548 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:104fff40 PA:104fff48 + 20564500 20549 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20565500 20550 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20566500 20551 1c001a78 00c004b3 add x9, x0, x12 x9=104fff64 x12:104fff64 + 20567500 20552 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000037 x15=104fff79 x15:104fff78 PA:104fff78 + 20569500 20554 1c001a7e 00070363 beq x14, x0, 6 x14:00000037 + 20570500 20555 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20571500 20556 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:104fff64 PA:104fff6c + 20573500 20558 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20576500 20561 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 20578500 20563 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20579500 20564 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20582500 20567 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20583500 20568 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20584500 20569 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20587500 20572 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20588500 20573 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20589500 20574 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20590500 20575 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20591500 20576 1c001b36 f71ff06f jal x0, -144 + 20593500 20578 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:104fff64 PA:104fff6c + 20595500 20580 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20598500 20583 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 20600500 20585 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20601500 20586 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20604500 20589 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 20605500 20590 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20606500 20591 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20607500 20592 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20608500 20593 1c001ae8 0104aa03 lw x20, 16(x9) x20=104fff78 x9:104fff64 PA:104fff74 + 20610500 20595 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000037 x20=104fff79 x20:104fff78 PA:104fff78 + 20612500 20597 1c001af0 06059763 bne x11, x0, 110 x11:00000037 + 20615500 20600 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20616500 20601 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20618500 20603 1c001776 00b00533 add x10, x0, x11 x10=00000037 x11:00000037 + 20619500 20604 1c001778 fddff06f jal x0, -36 + 20621500 20606 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20622500 20607 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 20623500 20608 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20624500 20609 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 20625500 20610 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 20626500 20611 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 20627500 20612 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 20628500 20613 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 20629500 20614 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20630500 20615 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000037 x14:1a104000 PA:1a1040b8 + 20634500 20619 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20635500 20620 1c001b62 f8bff06f jal x0, -118 + 20637500 20622 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=104fff7a x20:104fff79 PA:104fff79 + 20639500 20624 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20640500 20625 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:104fff64 PA:104fff64 + 20642500 20627 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20643500 20628 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20646500 20631 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:104fff40 PA:104fff5c + 20647500 20632 1c001b02 01812403 lw x8, 24(x2) x8=104fffe8 x2:104fff40 PA:104fff58 + 20648500 20633 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:104fff40 PA:104fff54 + 20649500 20634 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:104fff40 PA:104fff50 + 20650500 20635 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:104fff40 PA:104fff4c + 20651500 20636 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:104fff40 PA:104fff48 + 20652500 20637 1c001b0c 02010113 addi x2, x2, 32 x2=104fff60 x2:104fff40 + 20653500 20638 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20655500 20640 1c001d86 01800433 add x8, x0, x24 x8=104fffec x24:104fffec + 20656500 20641 1c001d88 fadff06f jal x0, -84 + 20658500 20643 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 20659500 20644 1c001d36 e69ff06f jal x0, -408 + 20662500 20647 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 20686500 20671 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 20687500 20672 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 20690500 20675 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 20691500 20676 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20692500 20677 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20694500 20679 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 20695500 20680 1c001778 fddff06f jal x0, -36 + 20697500 20682 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20698500 20683 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 20699500 20684 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20700500 20685 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 20701500 20686 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 20702500 20687 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 20703500 20688 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 20704500 20689 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 20705500 20690 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20706500 20691 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1040b8 + 20710500 20695 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20711500 20696 1c001bca 16a0006f jal x0, 362 + 20713500 20698 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 20714500 20699 1c001d36 e69ff06f jal x0, -408 + 20717500 20702 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 20733500 20718 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 20734500 20719 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 20737500 20722 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 20738500 20723 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20739500 20724 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20741500 20726 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 20742500 20727 1c001778 fddff06f jal x0, -36 + 20744500 20729 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20745500 20730 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 20746500 20731 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20747500 20732 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 20748500 20733 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 20749500 20734 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 20750500 20735 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 20751500 20736 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 20752500 20737 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20753500 20738 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1040b8 + 20757500 20742 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20758500 20743 1c001bca 16a0006f jal x0, 362 + 20760500 20745 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 20761500 20746 1c001d36 e69ff06f jal x0, -408 + 20764500 20749 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 20781500 20766 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 20782500 20767 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 20785500 20770 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 20786500 20771 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20787500 20772 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20789500 20774 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 20790500 20775 1c001778 fddff06f jal x0, -36 + 20792500 20777 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20793500 20778 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000027 + 20794500 20779 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20795500 20780 1c00175e 00379713 slli x14, x15, 0x3 x14=00000138 x15:00000027 + 20796500 20781 1c001762 00279793 slli x15, x15, 0x2 x15=0000009c x15:00000027 + 20797500 20782 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000138 + 20798500 20783 1c001768 00d7f7b3 and x15, x15, x13 x15=00000080 x15:0000009c x13:00001f80 + 20799500 20784 1c00176a 00e787b3 add x15, x15, x14 x15=000000b8 x15:00000080 x14:00000038 + 20800500 20785 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20801500 20786 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1040b8 + 20805500 20790 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20806500 20791 1c001bca 16a0006f jal x0, 362 + 20808500 20793 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 20809500 20794 1c001d36 e69ff06f jal x0, -408 + 20812500 20797 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 20826500 20811 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 20827500 20812 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 20828500 20813 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:104fff60 PA:104fffbc + 20829500 20814 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:104fff60 PA:104fffb8 + 20830500 20815 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:104fff60 PA:104fffb4 + 20831500 20816 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:104fff60 PA:104fffb0 + 20832500 20817 1c001bb0 04c12983 lw x19, 76(x2) x19=00000007 x2:104fff60 PA:104fffac + 20833500 20818 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:104fff60 PA:104fffa8 + 20834500 20819 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:104fff60 PA:104fffa4 + 20835500 20820 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:104fff60 PA:104fffa0 + 20836500 20821 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:104fff60 PA:104fff9c + 20838500 20823 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:104fff60 PA:104fff98 + 20839500 20824 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:104fff60 PA:104fff94 + 20840500 20825 1c001bbe 06010113 addi x2, x2, 96 x2=104fffc0 x2:104fff60 + 20841500 20826 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 20843500 20828 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:104fffc0 PA:104fffdc + 20844500 20829 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 20845500 20830 1c001838 04010113 addi x2, x2, 64 x2=10500000 x2:104fffc0 + 20846500 20831 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 20848500 20833 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_0.log b/sw/scripts/tracevis/example/traces/trace_core_02_0.log new file mode 100644 index 0000000..e8daea5 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_0.log @@ -0,0 +1,921 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000040 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000000 x10:00000040 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000040 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000000 + 14873500 14858 1c0000aa 00050463 beq x10, x0, 8 x10:00000002 + 14892500 14877 1c0000ae 0520206f jal x0, 8274 + 14894500 14879 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14895500 14880 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14896500 14881 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14897500 14882 1c00210c 0e059163 bne x11, x0, 226 x11:00000000 + 14909500 14894 1c002110 feffe417 auipc x8, 0xfeffe000 x8=1b000110 + 14910500 14895 1c002114 ef840413 addi x8, x8, -264 x8=1b000008 x8:1b000110 + 14911500 14896 1c002118 04040493 addi x9, x8, 64 x9=1b000048 x8:1b000008 + 14912500 14897 1c00211c 00800933 add x18, x0, x8 x18=1b000008 x8:1b000008 + 14929500 14914 1c00211e 1b2049b7 lui x19, 0x1b204000 x19=1b204000 + 14930500 14915 1c002122 00200a13 addi x20, x0, 2 x20=00000002 + 14931500 14916 1c002124 00000a97 auipc x21, 0x0 x21=1c002124 + 14932500 14917 1c002128 036a8a93 addi x21, x21, 54 x21=1c00215a x21:1c002124 + 14933500 14918 1c00212c 00000b97 auipc x23, 0x0 x23=1c00212c + 14950500 14935 1c002130 57cb8b93 addi x23, x23, 1404 x23=1c0026a8 x23:1c00212c + 14951500 14936 1c002134 000bab83 lw x23, 0(x23) x23=1c2fff50 x23:1c0026a8 PA:1c0026a8 + 14966500 14951 1c002138 01800393 addi x7, x0, 24 x7=00000018 + 14967500 14952 1c00213a 02a383b3 mul x7, x7, x10 x7=00000030 x7:00000018 x10:00000002 + 14968500 14953 1c00213e 007b8bb3 add x23, x23, x7 x23=1c2fff80 x23:1c2fff50 x7:00000030 + 14988500 14973 1c002140 008b8b93 addi x23, x23, 8 x23=1c2fff88 x23:1c2fff80 + 14989500 14974 1c002142 10201cb7 lui x25, 0x10201000 x25=10201000 + 14990500 14975 1c002146 e04c8c93 addi x25, x25, -508 x25=10200e04 x25:10201000 + 14991500 14976 1c00214a 00100c13 addi x24, x0, 1 x24=00000001 + 14992500 14977 1c00214c 00000d17 auipc x26, 0x0 x26=1c00214c + 15009500 14994 1c002150 0e0d0d13 addi x26, x26, 224 x26=1c00222c x26:1c00214c + 15010500 14995 1c002154 001d6d13 ori x26, x26, 1 x26=1c00222d x26:1c00222c + 15011500 14996 1c002158 0160006f jal x0, 22 + 15046500 15031 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000008 PA:1b000008 + 15048500 15033 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 15067500 15052 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 + 15068500 15053 1c0021d6 03c9e003 p.elw x0, 60(x19) x19:1b204000 PA:1b20403c + 18211500 18196 1c0021da 0149a223 sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004 + 18212500 18197 1c0021de f91ff06f jal x0, -112 + 18215500 18200 1c00216e 00042e03 lw x28, 0(x8) x28=00000008 x8:1b000008 PA:1b000008 + 18217500 18202 1c002172 060e0063 beq x28, x0, 96 x28:00000008 + 18218500 18203 1c002176 00842503 lw x10, 8(x8) x10=00000000 x8:1b000008 PA:1b000010 + 18219500 18204 1c002178 00442283 lw x5, 4(x8) x5=1c0009d8 x8:1b000008 PA:1b00000c + 18220500 18205 1c00217c 00c42103 lw x2, 12(x8) x2=108fe400 x8:1b000008 PA:1b000014 + 18237500 18222 1c002180 01042303 lw x6, 16(x8) x6=00000400 x8:1b000008 PA:1b000018 + 18238500 18223 1c002184 01442383 lw x7, 20(x8) x7=00000400 x8:1b000008 PA:1b00001c + 18239500 18224 1c002188 01842b03 lw x22, 24(x8) x22=100fc720 x8:1b000008 PA:1b000020 + 18240500 18225 1c00218c 01c42e83 lw x29, 28(x8) x29=1000013c x8:1b000008 PA:1b000024 + 18264500 18249 1c002190 00042023 sw x0, 0(x8) x8:1b000008 PA:1b000008 + 18265500 18250 1c002194 feffef17 auipc x30, 0xfeffe000 x30=1b000194 + 18266500 18251 1c002198 eb4f0f13 addi x30, x30, -332 x30=1b000048 x30:1b000194 + 18267500 18252 1c00219c 01df2023 sw x29, 0(x30) x29:1000013c x30:1b000048 PA:1b000048 + 18284500 18269 1c0021a0 015000b3 add x1, x0, x21 x1=1c00215a x21:1c00215a + 18285500 18270 1c0021a2 00100e93 addi x29, x0, 1 x29=00000001 + 18286500 18271 1c0021a4 01ce9e33 sll x28, x29, x28 x28=00000100 x29:00000001 x28:00000008 + 18287500 18272 1c0021a8 fffe0e13 addi x28, x28, -1 x28=000000ff x28:00000100 + 18288500 18273 1c0021aa 21c9a023 sw x28, 512(x19) x28:000000ff x19:1b204000 PA:1b204200 + 18310500 18295 1c0021ae 21c9a623 sw x28, 524(x19) x28:000000ff x19:1b204000 PA:1b20420c + 18311500 18296 1c0021b2 09c9a223 sw x28, 132(x19) x28:000000ff x19:1b204000 PA:1b204084 + 18312500 18297 1c0021b6 001e2863 p.beqimm x28, 16 x28:000000ff + 18313500 18298 1c0021ba 09a9a023 sw x26, 128(x19) x26:1c00222d x19:1b204000 PA:1b204080 + 18330500 18315 1c0021be 0879a023 sw x7, 128(x19) x7:00000400 x19:1b204000 PA:1b204080 + 18331500 18316 1c0021c2 0829a023 sw x2, 128(x19) x2:108fe400 x19:1b204000 PA:1b204080 + 18332500 18317 1c0021c6 02040413 addi x8, x8, 32 x8=1b000028 x8:1b000008 + 18333500 18318 1c0021ca 00941363 bne x8, x9, 6 x8:1b000028 x9:1b000048 + 18336500 18321 1c0021d0 00028067 jalr x0, x5, 0 x5:1c0009d8 + 18356500 18341 1c0009d8 ff010113 addi x2, x2, -16 x2=108fe3f0 x2:108fe400 + 18357500 18342 1c0009da 0ff00713 addi x14, x0, 255 x14=000000ff + 18375500 18360 1c0009de 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 18376500 18361 1c0009e2 00112623 sw x1, 12(x2) x1:1c00215a x2:108fe3f0 PA:108fe3fc + 18377500 18362 1c0009e4 00812423 sw x8, 8(x2) x8:1b000028 x2:108fe3f0 PA:108fe3f8 + 18378500 18363 1c0009e6 00912223 sw x9, 4(x2) x9:1b000048 x2:108fe3f0 PA:108fe3f4 + 18379500 18364 1c0009e8 08e7a223 sw x14, 132(x15) x14:000000ff x15:1b204000 PA:1b204084 + 18380500 18365 1c0009ec 20078493 addi x9, x15, 512 x9=1b204200 x15:1b204000 + 18397500 18382 1c0009f0 00e4a023 sw x14, 0(x9) x14:000000ff x9:1b204200 PA:1b204200 + 18398500 18383 1c0009f2 20c78793 addi x15, x15, 524 x15=1b20420c x15:1b204000 + 18399500 18384 1c0009f6 00e7a023 sw x14, 0(x15) x14:000000ff x15:1b20420c PA:1b20420c + 18400500 18385 1c0009f8 1c0017b7 lui x15, 0x1c001000 x15=1c001000 + 18401500 18386 1c0009fc 9bc78793 addi x15, x15, -1604 x15=1c0009bc x15:1c001000 + 18418500 18403 1c000a00 1b204737 lui x14, 0x1b204000 x14=1b204000 + 18419500 18404 1c000a04 08f72023 sw x15, 128(x14) x15:1c0009bc x14:1b204000 PA:1b204080 + 18420500 18405 1c000a08 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 18421500 18406 1c000a0c 08a7a023 sw x10, 128(x15) x10:00000000 x15:1b204000 PA:1b204080 + 18440500 18425 1c000a10 f1402673 csrrs x12, x0, 0xf14 x12=00000040 + 18441500 18426 1c000a14 40565413 srai x8, x12, 0x405 x8=00000002 x12:00000040 + 18442500 18427 1c000a18 f2643433 p.bclr x8, x8, 25, 6 x8=00000002 x8:00000002 + 18443500 18428 1c000a1c 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18462500 18447 1c000a20 f4563633 p.bclr x12, x12, 26, 5 x12=00000000 x12:00000040 + 18463500 18448 1c000a24 008005b3 add x11, x0, x8 x11=00000002 x8:00000002 + 18464500 18449 1c000a26 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18465500 18450 1c000a2a 5e7000ef jal x1, 3558 x1=1c000a2e + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108fe3b0 x2:108fe3f0 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108fe3b0 PA:108fe3d4 + 18504500 18489 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18505500 18490 1c001818 02c12423 sw x12, 40(x2) x12:00000000 x2:108fe3b0 PA:108fe3d8 + 18506500 18491 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108fe3b0 PA:108fe3dc + 18507500 18492 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18508500 18493 1c00181e 02410693 addi x13, x2, 36 x13=108fe3d4 x2:108fe3b0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c000a2e x2:108fe3b0 PA:108fe3cc + 18529500 18514 1c001828 02e12823 sw x14, 48(x2) x14:1b204000 x2:108fe3b0 PA:108fe3e0 + 18530500 18515 1c00182a 02f12a23 sw x15, 52(x2) x15:1b204000 x2:108fe3b0 PA:108fe3e4 + 18531500 18516 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108fe3b0 PA:108fe3e8 + 18532500 18517 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108fe3b0 PA:108fe3ec + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108fe3d4 x2:108fe3b0 PA:108fe3bc + 18550500 18535 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108fe350 x2:108fe3b0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108fe368 x2:108fe350 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000002 x2:108fe350 PA:108fe3a8 + 18571500 18556 1c001b76 05212823 sw x18, 80(x2) x18:1b000008 x2:108fe350 PA:108fe3a0 + 18572500 18557 1c001b78 05312623 sw x19, 76(x2) x19:1b204000 x2:108fe350 PA:108fe39c + 18573500 18558 1c001b7a 05412423 sw x20, 72(x2) x20:00000002 x2:108fe350 PA:108fe398 + 18574500 18559 1c001b7c 05512223 sw x21, 68(x2) x21:1c00215a x2:108fe350 PA:108fe394 + 18575500 18560 1c001b7e 05612023 sw x22, 64(x2) x22:100fc720 x2:108fe350 PA:108fe390 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:1c2fff88 x2:108fe350 PA:108fe38c + 18593500 18578 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108fe350 PA:108fe3ac + 18594500 18579 1c001b84 04912a23 sw x9, 84(x2) x9:1b204200 x2:108fe350 PA:108fe3a4 + 18595500 18580 1c001b86 03812c23 sw x24, 56(x2) x24:00000001 x2:108fe350 PA:108fe388 + 18596500 18581 1c001b88 03912a23 sw x25, 52(x2) x25:10200e04 x2:108fe350 PA:108fe384 + 18597500 18582 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18598500 18583 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18599500 18584 1c001b8e 00d00433 add x8, x0, x13 x8=108fe3d4 x13:108fe3d4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108fe368 x2:108fe350 PA:108fe364 + 18617500 18602 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18618500 18603 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18619500 18604 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18620500 18605 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18667500 18652 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18668500 18653 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18678500 18663 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18679500 18664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18680500 18665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104100 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18807500 18792 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18808500 18793 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18811500 18796 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18812500 18797 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18813500 18798 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18815500 18800 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18816500 18801 1c001778 fddff06f jal x0, -36 + 18818500 18803 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18819500 18804 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 18820500 18805 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18821500 18806 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 18822500 18807 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 18823500 18808 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 18824500 18809 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 18825500 18810 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 18826500 18811 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18827500 18812 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104100 + 18831500 18816 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18832500 18817 1c001bca 16a0006f jal x0, 362 + 18834500 18819 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18835500 18820 1c001d36 e69ff06f jal x0, -408 + 18838500 18823 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18854500 18839 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18855500 18840 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18858500 18843 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18859500 18844 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18860500 18845 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18862500 18847 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18863500 18848 1c001778 fddff06f jal x0, -36 + 18865500 18850 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18866500 18851 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 18867500 18852 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18868500 18853 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 18869500 18854 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 18870500 18855 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 18871500 18856 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 18872500 18857 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 18873500 18858 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18874500 18859 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104100 + 18878500 18863 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18879500 18864 1c001bca 16a0006f jal x0, 362 + 18881500 18866 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18882500 18867 1c001d36 e69ff06f jal x0, -408 + 18885500 18870 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18902500 18887 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18903500 18888 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18906500 18891 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18907500 18892 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18908500 18893 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18910500 18895 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18911500 18896 1c001778 fddff06f jal x0, -36 + 18913500 18898 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18914500 18899 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 18915500 18900 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18916500 18901 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 18917500 18902 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 18918500 18903 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 18919500 18904 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 18920500 18905 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 18921500 18906 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18922500 18907 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104100 + 18926500 18911 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18927500 18912 1c001bca 16a0006f jal x0, 362 + 18929500 18914 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18930500 18915 1c001d36 e69ff06f jal x0, -408 + 18933500 18918 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18950500 18935 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18951500 18936 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18954500 18939 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18955500 18940 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18956500 18941 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18958500 18943 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18959500 18944 1c001778 fddff06f jal x0, -36 + 18961500 18946 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18962500 18947 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 18963500 18948 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18964500 18949 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 18965500 18950 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 18966500 18951 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 18967500 18952 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 18968500 18953 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 18969500 18954 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18970500 18955 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104100 + 18974500 18959 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18975500 18960 1c001bca 16a0006f jal x0, 362 + 18977500 18962 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18978500 18963 1c001d36 e69ff06f jal x0, -408 + 18981500 18966 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19003500 18988 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19004500 18989 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19007500 18992 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19008500 18993 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19009500 18994 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19011500 18996 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19012500 18997 1c001778 fddff06f jal x0, -36 + 19014500 18999 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19015500 19000 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19016500 19001 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19017500 19002 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19018500 19003 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19019500 19004 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19020500 19005 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19021500 19006 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19022500 19007 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19023500 19008 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104100 + 19027500 19012 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19028500 19013 1c001bca 16a0006f jal x0, 362 + 19030500 19015 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19031500 19016 1c001d36 e69ff06f jal x0, -408 + 19034500 19019 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19048500 19033 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19049500 19034 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19052500 19037 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19053500 19038 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19054500 19039 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19056500 19041 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19057500 19042 1c001778 fddff06f jal x0, -36 + 19059500 19044 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19060500 19045 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19061500 19046 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19062500 19047 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19063500 19048 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19064500 19049 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19065500 19050 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19066500 19051 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19067500 19052 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19068500 19053 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104100 + 19072500 19057 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19073500 19058 1c001bca 16a0006f jal x0, 362 + 19075500 19060 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19076500 19061 1c001d36 e69ff06f jal x0, -408 + 19079500 19064 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19093500 19078 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19094500 19079 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19097500 19082 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19098500 19083 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19099500 19084 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19101500 19086 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19102500 19087 1c001778 fddff06f jal x0, -36 + 19104500 19089 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19105500 19090 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19106500 19091 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19107500 19092 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19108500 19093 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19109500 19094 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19110500 19095 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19111500 19096 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19112500 19097 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19113500 19098 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104100 + 19117500 19102 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19118500 19103 1c001bca 16a0006f jal x0, 362 + 19120500 19105 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19121500 19106 1c001d36 e69ff06f jal x0, -408 + 19124500 19109 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19138500 19123 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19139500 19124 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19142500 19127 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19143500 19128 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19144500 19129 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19146500 19131 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19147500 19132 1c001778 fddff06f jal x0, -36 + 19149500 19134 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19150500 19135 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19151500 19136 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19152500 19137 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19153500 19138 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19154500 19139 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19155500 19140 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19156500 19141 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19157500 19142 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19158500 19143 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104100 + 19162500 19147 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19163500 19148 1c001bca 16a0006f jal x0, 362 + 19165500 19150 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19166500 19151 1c001d36 e69ff06f jal x0, -408 + 19169500 19154 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19202500 19187 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19203500 19188 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19206500 19191 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19207500 19192 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19208500 19193 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19210500 19195 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19211500 19196 1c001778 fddff06f jal x0, -36 + 19213500 19198 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19214500 19199 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19215500 19200 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19216500 19201 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19217500 19202 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19218500 19203 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19219500 19204 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19220500 19205 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19221500 19206 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19222500 19207 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104100 + 19226500 19211 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19227500 19212 1c001bca 16a0006f jal x0, 362 + 19229500 19214 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19230500 19215 1c001d36 e69ff06f jal x0, -408 + 19233500 19218 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19251500 19236 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19252500 19237 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19255500 19240 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19256500 19241 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19257500 19242 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19259500 19244 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19260500 19245 1c001778 fddff06f jal x0, -36 + 19262500 19247 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19263500 19248 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19264500 19249 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19265500 19250 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19266500 19251 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19267500 19252 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19268500 19253 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19269500 19254 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19270500 19255 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19271500 19256 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104100 + 19275500 19260 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19276500 19261 1c001bca 16a0006f jal x0, 362 + 19278500 19263 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19279500 19264 1c001d36 e69ff06f jal x0, -408 + 19282500 19267 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19300500 19285 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19301500 19286 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19304500 19289 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19305500 19290 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19306500 19291 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19308500 19293 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19309500 19294 1c001778 fddff06f jal x0, -36 + 19311500 19296 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19312500 19297 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19313500 19298 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19314500 19299 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19315500 19300 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19316500 19301 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19317500 19302 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19318500 19303 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19319500 19304 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19320500 19305 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104100 + 19324500 19309 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19325500 19310 1c001bca 16a0006f jal x0, 362 + 19327500 19312 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19328500 19313 1c001d36 e69ff06f jal x0, -408 + 19331500 19316 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19348500 19333 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19349500 19334 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19352500 19337 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19353500 19338 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19354500 19339 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19356500 19341 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19357500 19342 1c001778 fddff06f jal x0, -36 + 19359500 19344 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19360500 19345 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19361500 19346 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19362500 19347 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19363500 19348 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19364500 19349 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19365500 19350 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19366500 19351 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19367500 19352 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19368500 19353 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104100 + 19372500 19357 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19373500 19358 1c001bca 16a0006f jal x0, 362 + 19375500 19360 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19376500 19361 1c001d36 e69ff06f jal x0, -408 + 19379500 19364 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19400500 19385 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19401500 19386 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19404500 19389 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19405500 19390 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19406500 19391 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19408500 19393 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19409500 19394 1c001778 fddff06f jal x0, -36 + 19411500 19396 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19412500 19397 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19413500 19398 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19414500 19399 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19415500 19400 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19416500 19401 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19417500 19402 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19418500 19403 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19419500 19404 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19420500 19405 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104100 + 19424500 19409 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19425500 19410 1c001bca 16a0006f jal x0, 362 + 19427500 19412 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19428500 19413 1c001d36 e69ff06f jal x0, -408 + 19431500 19416 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19452500 19437 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19453500 19438 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19456500 19441 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19457500 19442 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19458500 19443 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19460500 19445 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19461500 19446 1c001778 fddff06f jal x0, -36 + 19463500 19448 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19464500 19449 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 19465500 19450 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19466500 19451 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 19467500 19452 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 19468500 19453 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 19469500 19454 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 19470500 19455 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 19471500 19456 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19472500 19457 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104100 + 19476500 19461 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19477500 19462 1c001bca 16a0006f jal x0, 362 + 19479500 19464 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19480500 19465 1c001d36 e69ff06f jal x0, -408 + 19483500 19468 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19502500 19487 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19503500 19488 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19506500 19491 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19509500 19494 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108fe350 PA:108fe354 + 19510500 19495 1c001bd0 00012423 sw x0, 8(x2) x2:108fe350 PA:108fe358 + 19511500 19496 1c001bd2 00010623 sb x0, 12(x2) x2:108fe350 PA:108fe35c + 19512500 19497 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19513500 19498 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19514500 19499 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19515500 19500 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fe350 PA:108fe354 + 19516500 19501 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19517500 19502 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19518500 19503 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19519500 19504 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19520500 19505 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19573500 19558 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19574500 19559 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19586500 19571 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19587500 19572 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19588500 19573 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fe350 PA:108fe360 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108fe3d8 x8:108fe3d4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108fe3d4 PA:108fe3d4 + 19945500 19930 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108fe354 x2:108fe350 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108fe368 x11:108fe354 PA:108fe364 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe354 PA:108fe360 + 20042500 20027 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20043500 20028 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20077500 20062 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20078500 20063 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20079500 20064 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20080500 20065 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20083500 20068 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe354 PA:108fe360 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108fe368 PA:108fe368 + 20246500 20231 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20247500 20232 1c001a5e 00168693 addi x13, x13, 1 x13=108fe369 x13:108fe368 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108fe369 PA:108fe369 + 20267500 20252 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20269500 20254 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108fe354 x2:108fe350 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108fe330 x2:108fe350 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108fe3d4 x2:108fe330 PA:108fe348 + 20316500 20301 1c001a66 01062783 lw x15, 16(x12) x15=108fe368 x12:108fe354 PA:108fe364 + 20317500 20302 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fe354 PA:108fe358 + 20318500 20303 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108fe330 PA:108fe344 + 20319500 20304 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fe330 PA:108fe340 + 20320500 20305 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fe330 PA:108fe33c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fe330 PA:108fe34c + 20338500 20323 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fe330 PA:108fe338 + 20339500 20324 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20340500 20325 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20341500 20326 1c001a78 00c004b3 add x9, x0, x12 x9=108fe354 x12:108fe354 + 20342500 20327 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108fe369 x15:108fe368 PA:108fe368 + 20344500 20329 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fe354 PA:108fe35c + 20363500 20348 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20366500 20351 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fe354 PA:108fe35c + 20450500 20435 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 20470500 20455 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20471500 20456 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fe368 x9:108fe354 PA:108fe364 + 20512500 20497 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108fe369 x20:108fe368 PA:108fe368 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104100 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fe36a x20:108fe369 PA:108fe369 + 20587500 20572 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20588500 20573 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 20590500 20575 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20591500 20576 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fe330 PA:108fe34c + 20611500 20596 1c001b02 01812403 lw x8, 24(x2) x8=108fe3d4 x2:108fe330 PA:108fe348 + 20612500 20597 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108fe330 PA:108fe344 + 20613500 20598 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fe330 PA:108fe340 + 20614500 20599 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fe330 PA:108fe33c + 20615500 20600 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fe330 PA:108fe338 + 20616500 20601 1c001b0c 02010113 addi x2, x2, 32 x2=108fe350 x2:108fe330 + 20617500 20602 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108fe3d8 x24:108fe3d8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20684500 20669 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20685500 20670 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20688500 20673 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20689500 20674 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20690500 20675 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20692500 20677 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20693500 20678 1c001778 fddff06f jal x0, -36 + 20695500 20680 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20696500 20681 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 20697500 20682 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20698500 20683 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 20699500 20684 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 20700500 20685 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 20701500 20686 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 20702500 20687 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 20703500 20688 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20704500 20689 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104100 + 20708500 20693 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20709500 20694 1c001bca 16a0006f jal x0, 362 + 20711500 20696 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20712500 20697 1c001d36 e69ff06f jal x0, -408 + 20715500 20700 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20731500 20716 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20732500 20717 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20735500 20720 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20736500 20721 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20737500 20722 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20739500 20724 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20740500 20725 1c001778 fddff06f jal x0, -36 + 20742500 20727 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20743500 20728 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 20744500 20729 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20745500 20730 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 20746500 20731 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 20747500 20732 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 20748500 20733 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 20749500 20734 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 20750500 20735 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20751500 20736 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104100 + 20755500 20740 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20756500 20741 1c001bca 16a0006f jal x0, 362 + 20758500 20743 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20759500 20744 1c001d36 e69ff06f jal x0, -408 + 20762500 20747 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20779500 20764 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20780500 20765 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20783500 20768 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20786500 20771 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108fe350 PA:108fe354 + 20787500 20772 1c001bd0 00012423 sw x0, 8(x2) x2:108fe350 PA:108fe358 + 20788500 20773 1c001bd2 00010623 sb x0, 12(x2) x2:108fe350 PA:108fe35c + 20789500 20774 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20790500 20775 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20791500 20776 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20792500 20777 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fe350 PA:108fe354 + 20793500 20778 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20794500 20779 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20795500 20780 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20796500 20781 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20797500 20782 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20798500 20783 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20799500 20784 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20800500 20785 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20816500 20801 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20817500 20802 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20820500 20805 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20821500 20806 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20822500 20807 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20825500 20810 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20828500 20813 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20831500 20816 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20834500 20819 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20835500 20820 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20836500 20821 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20837500 20822 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20840500 20825 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20841500 20826 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20844500 20829 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20845500 20830 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20848500 20833 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20850500 20835 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20853500 20838 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20854500 20839 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20857500 20842 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20858500 20843 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20859500 20844 1c001f42 e09ff06f jal x0, -504 + 20861500 20846 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20862500 20847 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fe350 PA:108fe360 + 20863500 20848 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20866500 20851 1c001e34 00440c13 addi x24, x8, 4 x24=108fe3dc x8:108fe3d8 + 20867500 20852 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:108fe3d8 PA:108fe3d8 + 20868500 20853 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20871500 20856 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 20874500 20859 1c001e64 00410593 addi x11, x2, 4 x11=108fe354 x2:108fe350 + 20875500 20860 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20877500 20862 1c0019fe 0105a683 lw x13, 16(x11) x13=108fe368 x11:108fe354 PA:108fe364 + 20878500 20863 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe354 PA:108fe360 + 20879500 20864 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20880500 20865 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 20914500 20899 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 20915500 20900 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20916500 20901 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20917500 20902 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20920500 20905 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe354 PA:108fe360 + 20921500 20906 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 20955500 20940 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 20989500 20974 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21020500 21005 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21021500 21006 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 21022500 21007 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 21023500 21008 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 21024500 21009 1c001a38 01e0006f jal x0, 30 + 21026500 21011 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 21027500 21012 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:108fe368 PA:108fe368 + 21028500 21013 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21029500 21014 1c001a5e 00168693 addi x13, x13, 1 x13=108fe369 x13:108fe368 + 21030500 21015 1c001a60 fb1ff06f jal x0, -80 + 21032500 21017 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21033500 21018 1c001a12 00068023 sb x0, 0(x13) x13:108fe369 PA:108fe369 + 21034500 21019 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21036500 21021 1c001e68 f17ff06f jal x0, -234 + 21038500 21023 1c001d7e 00410613 addi x12, x2, 4 x12=108fe354 x2:108fe350 + 21039500 21024 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21040500 21025 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21041500 21026 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21043500 21028 1c001a62 fe010113 addi x2, x2, -32 x2=108fe330 x2:108fe350 + 21044500 21029 1c001a64 00812c23 sw x8, 24(x2) x8:108fe3d8 x2:108fe330 PA:108fe348 + 21045500 21030 1c001a66 01062783 lw x15, 16(x12) x15=108fe368 x12:108fe354 PA:108fe364 + 21046500 21031 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fe354 PA:108fe358 + 21047500 21032 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108fe330 PA:108fe344 + 21048500 21033 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fe330 PA:108fe340 + 21049500 21034 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fe330 PA:108fe33c + 21050500 21035 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fe330 PA:108fe34c + 21051500 21036 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fe330 PA:108fe338 + 21052500 21037 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21053500 21038 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21054500 21039 1c001a78 00c004b3 add x9, x0, x12 x9=108fe354 x12:108fe354 + 21055500 21040 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=108fe369 x15:108fe368 PA:108fe368 + 21057500 21042 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 21058500 21043 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21059500 21044 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fe354 PA:108fe35c + 21061500 21046 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21064500 21049 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 21066500 21051 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21067500 21052 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21070500 21055 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21071500 21056 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21072500 21057 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21075500 21060 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21076500 21061 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21077500 21062 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21078500 21063 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21079500 21064 1c001b36 f71ff06f jal x0, -144 + 21081500 21066 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fe354 PA:108fe35c + 21083500 21068 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21086500 21071 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 21088500 21073 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21089500 21074 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21092500 21077 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 21093500 21078 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21094500 21079 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21095500 21080 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21096500 21081 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fe368 x9:108fe354 PA:108fe364 + 21098500 21083 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=108fe369 x20:108fe368 PA:108fe368 + 21100500 21085 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 21103500 21088 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21104500 21089 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21106500 21091 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 21107500 21092 1c001778 fddff06f jal x0, -36 + 21109500 21094 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21110500 21095 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 21111500 21096 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21112500 21097 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 21113500 21098 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 21114500 21099 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 21115500 21100 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 21116500 21101 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 21117500 21102 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21118500 21103 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104100 + 21122500 21107 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21123500 21108 1c001b62 f8bff06f jal x0, -118 + 21125500 21110 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fe36a x20:108fe369 PA:108fe369 + 21127500 21112 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21128500 21113 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe354 PA:108fe354 + 21130500 21115 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21131500 21116 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21134500 21119 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fe330 PA:108fe34c + 21135500 21120 1c001b02 01812403 lw x8, 24(x2) x8=108fe3d8 x2:108fe330 PA:108fe348 + 21136500 21121 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108fe330 PA:108fe344 + 21137500 21122 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fe330 PA:108fe340 + 21138500 21123 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fe330 PA:108fe33c + 21139500 21124 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fe330 PA:108fe338 + 21140500 21125 1c001b0c 02010113 addi x2, x2, 32 x2=108fe350 x2:108fe330 + 21141500 21126 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21143500 21128 1c001d86 01800433 add x8, x0, x24 x8=108fe3dc x24:108fe3dc + 21144500 21129 1c001d88 fadff06f jal x0, -84 + 21146500 21131 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21147500 21132 1c001d36 e69ff06f jal x0, -408 + 21150500 21135 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21164500 21149 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21165500 21150 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21168500 21153 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21169500 21154 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21170500 21155 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21172500 21157 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21173500 21158 1c001778 fddff06f jal x0, -36 + 21175500 21160 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21176500 21161 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 21177500 21162 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21178500 21163 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 21179500 21164 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 21180500 21165 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 21181500 21166 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 21182500 21167 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 21183500 21168 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21184500 21169 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104100 + 21188500 21173 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21189500 21174 1c001bca 16a0006f jal x0, 362 + 21191500 21176 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21192500 21177 1c001d36 e69ff06f jal x0, -408 + 21195500 21180 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21215500 21200 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21216500 21201 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21219500 21204 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21220500 21205 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21221500 21206 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21223500 21208 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21224500 21209 1c001778 fddff06f jal x0, -36 + 21226500 21211 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21227500 21212 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 21228500 21213 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21229500 21214 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 21230500 21215 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 21231500 21216 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 21232500 21217 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 21233500 21218 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 21234500 21219 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21235500 21220 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104100 + 21239500 21224 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21240500 21225 1c001bca 16a0006f jal x0, 362 + 21242500 21227 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21243500 21228 1c001d36 e69ff06f jal x0, -408 + 21246500 21231 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21260500 21245 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21261500 21246 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21264500 21249 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21265500 21250 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21266500 21251 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21268500 21253 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21269500 21254 1c001778 fddff06f jal x0, -36 + 21271500 21256 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21272500 21257 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000040 + 21273500 21258 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21274500 21259 1c00175e 00379713 slli x14, x15, 0x3 x14=00000200 x15:00000040 + 21275500 21260 1c001762 00279793 slli x15, x15, 0x2 x15=00000100 x15:00000040 + 21276500 21261 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000200 + 21277500 21262 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000100 x13:00001f80 + 21278500 21263 1c00176a 00e787b3 add x15, x15, x14 x15=00000100 x15:00000100 x14:00000000 + 21279500 21264 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21280500 21265 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104100 + 21284500 21269 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21285500 21270 1c001bca 16a0006f jal x0, 362 + 21287500 21272 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21288500 21273 1c001d36 e69ff06f jal x0, -408 + 21291500 21276 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21308500 21293 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21309500 21294 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21310500 21295 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108fe350 PA:108fe3ac + 21311500 21296 1c001baa 05812403 lw x8, 88(x2) x8=00000002 x2:108fe350 PA:108fe3a8 + 21312500 21297 1c001bac 05412483 lw x9, 84(x2) x9=1b204200 x2:108fe350 PA:108fe3a4 + 21313500 21298 1c001bae 05012903 lw x18, 80(x2) x18=1b000008 x2:108fe350 PA:108fe3a0 + 21314500 21299 1c001bb0 04c12983 lw x19, 76(x2) x19=1b204000 x2:108fe350 PA:108fe39c + 21315500 21300 1c001bb2 04812a03 lw x20, 72(x2) x20=00000002 x2:108fe350 PA:108fe398 + 21316500 21301 1c001bb4 04412a83 lw x21, 68(x2) x21=1c00215a x2:108fe350 PA:108fe394 + 21317500 21302 1c001bb6 04012b03 lw x22, 64(x2) x22=100fc720 x2:108fe350 PA:108fe390 + 21318500 21303 1c001bb8 03c12b83 lw x23, 60(x2) x23=1c2fff88 x2:108fe350 PA:108fe38c + 21319500 21304 1c001bba 03812c03 lw x24, 56(x2) x24=00000001 x2:108fe350 PA:108fe388 + 21320500 21305 1c001bbc 03412c83 lw x25, 52(x2) x25=10200e04 x2:108fe350 PA:108fe384 + 21321500 21306 1c001bbe 06010113 addi x2, x2, 96 x2=108fe3b0 x2:108fe350 + 21322500 21307 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21324500 21309 1c001834 01c12083 lw x1, 28(x2) x1=1c000a2e x2:108fe3b0 PA:108fe3cc + 21325500 21310 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21326500 21311 1c001838 04010113 addi x2, x2, 64 x2=108fe3f0 x2:108fe3b0 + 21327500 21312 1c00183a 00008067 jalr x0, x1, 0 x1:1c000a2e + 21330500 21315 1c000a2e 01c4e783 p.elw x15, 28(x9) x15=00000000 x9:1b204200 PA:1b20421c + 21343500 21328 1c000a32 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 21344500 21329 1c000a36 00241413 slli x8, x8, 0x2 x8=00000008 x8:00000002 + 21345500 21330 1c000a38 68478793 addi x15, x15, 1668 x15=1c002684 x15:1c002000 + 21346500 21331 1c000a3c 00100713 addi x14, x0, 1 x14=00000001 + 21363500 21348 1c000a3e 00e7e423 p.sw x14, x0(x15) x14:00000001 x15:1c002684 PA:1c00268c + 21381500 21366 1c000a42 00c12083 lw x1, 12(x2) x1=1c00215a x2:108fe3f0 PA:108fe3fc + 21382500 21367 1c000a44 00812403 lw x8, 8(x2) x8=1b000028 x2:108fe3f0 PA:108fe3f8 + 21383500 21368 1c000a46 00412483 lw x9, 4(x2) x9=1b000048 x2:108fe3f0 PA:108fe3f4 + 21384500 21369 1c000a48 01010113 addi x2, x2, 16 x2=108fe400 x2:108fe3f0 + 21385500 21370 1c000a4a 00008067 jalr x0, x1, 0 x1:1c00215a + 21387500 21372 1c00215a 000b0a63 beq x22, x0, 20 x22:100fc720 + 21389500 21374 1c00215e 000ba283 lw x5, 0(x23) x5=00000000 x23:1c2fff88 PA:1c2fff88 + 21404500 21389 1c002162 06029f63 bne x5, x0, 126 x5:00000000 + 21405500 21390 1c002166 016ba023 sw x22, 0(x23) x22:100fc720 x23:1c2fff88 PA:1c2fff88 + 21423500 21408 1c00216a 018ca023 sw x24, 0(x25) x24:00000001 x25:10200e04 PA:10200e04 + 21427500 21412 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028 + 21429500 21414 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 21432500 21417 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 + 21433500 21418 1c0021d6 03c9e003 p.elw x0, 60(x19) x19:1b204000 PA:1b20403c + 21438500 21423 1c0021da 0149a223 sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004 + 21439500 21424 1c0021de f91ff06f jal x0, -112 + 21442500 21427 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028 + 21444500 21429 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 21447500 21432 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_1.log b/sw/scripts/tracevis/example/traces/trace_core_02_1.log new file mode 100644 index 0000000..3dfe2a4 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_1.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000041 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000001 x10:00000041 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000041 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000001 + 14871500 14856 1c0000a6 05a0206f jal x0, 8282 + 14889500 14874 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14890500 14875 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14891500 14876 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14892500 14877 1c00210c 0e059163 bne x11, x0, 226 x11:00000001 + 14944500 14929 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 14945500 14930 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000041 + 14946500 14931 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000001 x19:00000041 + 14947500 14932 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 14964500 14949 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 14965500 14950 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 14966500 14951 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 14967500 14952 1c00220a 0060006f jal x0, 6 + 14986500 14971 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18321500 18306 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18338500 18323 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18339500 18324 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18361500 18346 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18362500 18347 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18364500 18349 1c00222c 08096283 p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080 + 18388500 18373 1c002230 02a98533 mul x10, x19, x10 x10=00000400 x19:00000001 x10:00000400 + 18389500 18374 1c002234 00550133 add x2, x10, x5 x2=108fe800 x10:00000400 x5:108fe400 + 18390500 18375 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18392500 18377 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18427500 18412 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18435500 18420 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18436500 18421 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18437500 18422 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18438500 18423 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18459500 18444 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000041 + 18476500 18461 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18477500 18462 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000002 x12:00000041 + 18478500 18463 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002 + 18479500 18464 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000001 x12:00000041 + 18480500 18465 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18481500 18466 1c0009d4 63d0006f jal x0, 3644 + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108fe7c0 x2:108fe800 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108fe7c0 PA:108fe7e4 + 18507500 18492 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18508500 18493 1c001818 02c12423 sw x12, 40(x2) x12:00000001 x2:108fe7c0 PA:108fe7e8 + 18509500 18494 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108fe7c0 PA:108fe7ec + 18510500 18495 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18511500 18496 1c00181e 02410693 addi x13, x2, 36 x13=108fe7e4 x2:108fe7c0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:108fe7c0 PA:108fe7dc + 18531500 18516 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:108fe7c0 PA:108fe7f0 + 18532500 18517 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:108fe7c0 PA:108fe7f4 + 18533500 18518 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108fe7c0 PA:108fe7f8 + 18534500 18519 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108fe7c0 PA:108fe7fc + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108fe7e4 x2:108fe7c0 PA:108fe7cc + 18551500 18536 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108fe760 x2:108fe7c0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108fe778 x2:108fe760 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:108fe760 PA:108fe7b8 + 18577500 18562 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:108fe760 PA:108fe7b0 + 18578500 18563 1c001b78 05312623 sw x19, 76(x2) x19:00000001 x2:108fe760 PA:108fe7ac + 18579500 18564 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:108fe760 PA:108fe7a8 + 18580500 18565 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:108fe760 PA:108fe7a4 + 18581500 18566 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:108fe760 PA:108fe7a0 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:108fe760 PA:108fe79c + 18595500 18580 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108fe760 PA:108fe7bc + 18596500 18581 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:108fe760 PA:108fe7b4 + 18597500 18582 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:108fe760 PA:108fe798 + 18598500 18583 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:108fe760 PA:108fe794 + 18599500 18584 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18600500 18585 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18601500 18586 1c001b8e 00d00433 add x8, x0, x13 x8=108fe7e4 x13:108fe7e4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108fe778 x2:108fe760 PA:108fe774 + 18617500 18602 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18618500 18603 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18619500 18604 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18620500 18605 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18653500 18638 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18654500 18639 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18678500 18663 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18679500 18664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18680500 18665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104108 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18787500 18772 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18788500 18773 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18791500 18776 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18792500 18777 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18793500 18778 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18795500 18780 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18796500 18781 1c001778 fddff06f jal x0, -36 + 18798500 18783 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18799500 18784 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 18800500 18785 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18801500 18786 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 18802500 18787 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 18803500 18788 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 18804500 18789 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 18805500 18790 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 18806500 18791 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18807500 18792 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104108 + 18811500 18796 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18812500 18797 1c001bca 16a0006f jal x0, 362 + 18814500 18799 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18815500 18800 1c001d36 e69ff06f jal x0, -408 + 18818500 18803 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18832500 18817 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18833500 18818 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18836500 18821 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18837500 18822 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18838500 18823 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18840500 18825 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18841500 18826 1c001778 fddff06f jal x0, -36 + 18843500 18828 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18844500 18829 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 18845500 18830 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18846500 18831 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 18847500 18832 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 18848500 18833 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 18849500 18834 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 18850500 18835 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 18851500 18836 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18852500 18837 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104108 + 18856500 18841 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18857500 18842 1c001bca 16a0006f jal x0, 362 + 18859500 18844 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18860500 18845 1c001d36 e69ff06f jal x0, -408 + 18863500 18848 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18879500 18864 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18880500 18865 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18883500 18868 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18884500 18869 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18885500 18870 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18887500 18872 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18888500 18873 1c001778 fddff06f jal x0, -36 + 18890500 18875 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18891500 18876 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 18892500 18877 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18893500 18878 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 18894500 18879 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 18895500 18880 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 18896500 18881 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 18897500 18882 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 18898500 18883 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18899500 18884 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104108 + 18903500 18888 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18904500 18889 1c001bca 16a0006f jal x0, 362 + 18906500 18891 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18907500 18892 1c001d36 e69ff06f jal x0, -408 + 18910500 18895 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18929500 18914 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18930500 18915 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18933500 18918 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18934500 18919 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18935500 18920 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18937500 18922 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18938500 18923 1c001778 fddff06f jal x0, -36 + 18940500 18925 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18941500 18926 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 18942500 18927 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18943500 18928 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 18944500 18929 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 18945500 18930 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 18946500 18931 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 18947500 18932 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 18948500 18933 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18949500 18934 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104108 + 18953500 18938 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18954500 18939 1c001bca 16a0006f jal x0, 362 + 18956500 18941 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18957500 18942 1c001d36 e69ff06f jal x0, -408 + 18960500 18945 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18975500 18960 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18976500 18961 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18979500 18964 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18980500 18965 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18981500 18966 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18983500 18968 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18984500 18969 1c001778 fddff06f jal x0, -36 + 18986500 18971 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18987500 18972 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 18988500 18973 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18989500 18974 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 18990500 18975 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 18991500 18976 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 18992500 18977 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 18993500 18978 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 18994500 18979 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18995500 18980 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104108 + 18999500 18984 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19000500 18985 1c001bca 16a0006f jal x0, 362 + 19002500 18987 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19003500 18988 1c001d36 e69ff06f jal x0, -408 + 19006500 18991 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19021500 19006 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19022500 19007 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19025500 19010 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19026500 19011 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19027500 19012 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19029500 19014 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19030500 19015 1c001778 fddff06f jal x0, -36 + 19032500 19017 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19033500 19018 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19034500 19019 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19035500 19020 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19036500 19021 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19037500 19022 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19038500 19023 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19039500 19024 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19040500 19025 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19041500 19026 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104108 + 19045500 19030 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19046500 19031 1c001bca 16a0006f jal x0, 362 + 19048500 19033 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19049500 19034 1c001d36 e69ff06f jal x0, -408 + 19052500 19037 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19071500 19056 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19072500 19057 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19075500 19060 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19076500 19061 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19077500 19062 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19079500 19064 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19080500 19065 1c001778 fddff06f jal x0, -36 + 19082500 19067 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19083500 19068 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19084500 19069 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19085500 19070 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19086500 19071 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19087500 19072 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19088500 19073 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19089500 19074 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19090500 19075 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19091500 19076 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104108 + 19095500 19080 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19096500 19081 1c001bca 16a0006f jal x0, 362 + 19098500 19083 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19099500 19084 1c001d36 e69ff06f jal x0, -408 + 19102500 19087 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19117500 19102 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19118500 19103 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19121500 19106 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19122500 19107 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19123500 19108 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19125500 19110 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19126500 19111 1c001778 fddff06f jal x0, -36 + 19128500 19113 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19129500 19114 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19130500 19115 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19131500 19116 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19132500 19117 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19133500 19118 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19134500 19119 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19135500 19120 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19136500 19121 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19137500 19122 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104108 + 19141500 19126 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19142500 19127 1c001bca 16a0006f jal x0, 362 + 19144500 19129 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19145500 19130 1c001d36 e69ff06f jal x0, -408 + 19148500 19133 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19163500 19148 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19164500 19149 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19167500 19152 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19168500 19153 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19169500 19154 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19171500 19156 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19172500 19157 1c001778 fddff06f jal x0, -36 + 19174500 19159 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19175500 19160 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19176500 19161 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19177500 19162 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19178500 19163 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19179500 19164 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19180500 19165 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19181500 19166 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19182500 19167 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19183500 19168 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104108 + 19187500 19172 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19188500 19173 1c001bca 16a0006f jal x0, 362 + 19190500 19175 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19191500 19176 1c001d36 e69ff06f jal x0, -408 + 19194500 19179 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19215500 19200 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19216500 19201 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19219500 19204 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19220500 19205 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19221500 19206 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19223500 19208 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19224500 19209 1c001778 fddff06f jal x0, -36 + 19226500 19211 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19227500 19212 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19228500 19213 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19229500 19214 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19230500 19215 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19231500 19216 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19232500 19217 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19233500 19218 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19234500 19219 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19235500 19220 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104108 + 19239500 19224 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19240500 19225 1c001bca 16a0006f jal x0, 362 + 19242500 19227 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19243500 19228 1c001d36 e69ff06f jal x0, -408 + 19246500 19231 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19260500 19245 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19261500 19246 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19264500 19249 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19265500 19250 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19266500 19251 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19268500 19253 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19269500 19254 1c001778 fddff06f jal x0, -36 + 19271500 19256 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19272500 19257 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19273500 19258 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19274500 19259 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19275500 19260 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19276500 19261 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19277500 19262 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19278500 19263 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19279500 19264 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19280500 19265 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104108 + 19284500 19269 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19285500 19270 1c001bca 16a0006f jal x0, 362 + 19287500 19272 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19288500 19273 1c001d36 e69ff06f jal x0, -408 + 19291500 19276 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19305500 19290 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19306500 19291 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19309500 19294 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19310500 19295 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19311500 19296 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19313500 19298 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19314500 19299 1c001778 fddff06f jal x0, -36 + 19316500 19301 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19317500 19302 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19318500 19303 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19319500 19304 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19320500 19305 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19321500 19306 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19322500 19307 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19323500 19308 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19324500 19309 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19325500 19310 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104108 + 19329500 19314 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19330500 19315 1c001bca 16a0006f jal x0, 362 + 19332500 19317 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19333500 19318 1c001d36 e69ff06f jal x0, -408 + 19336500 19321 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19352500 19337 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19353500 19338 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19356500 19341 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19357500 19342 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19358500 19343 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19360500 19345 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19361500 19346 1c001778 fddff06f jal x0, -36 + 19363500 19348 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19364500 19349 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19365500 19350 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19366500 19351 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19367500 19352 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19368500 19353 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19369500 19354 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19370500 19355 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19371500 19356 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19372500 19357 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104108 + 19376500 19361 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19377500 19362 1c001bca 16a0006f jal x0, 362 + 19379500 19364 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19380500 19365 1c001d36 e69ff06f jal x0, -408 + 19383500 19368 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19402500 19387 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19403500 19388 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19406500 19391 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19407500 19392 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19408500 19393 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19410500 19395 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19411500 19396 1c001778 fddff06f jal x0, -36 + 19413500 19398 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19414500 19399 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 19415500 19400 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19416500 19401 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 19417500 19402 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 19418500 19403 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 19419500 19404 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 19420500 19405 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 19421500 19406 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19422500 19407 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104108 + 19426500 19411 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19427500 19412 1c001bca 16a0006f jal x0, 362 + 19429500 19414 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19430500 19415 1c001d36 e69ff06f jal x0, -408 + 19433500 19418 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19455500 19440 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19456500 19441 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19459500 19444 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19462500 19447 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108fe760 PA:108fe764 + 19488500 19473 1c001bd0 00012423 sw x0, 8(x2) x2:108fe760 PA:108fe768 + 19493500 19478 1c001bd2 00010623 sb x0, 12(x2) x2:108fe760 PA:108fe76c + 19494500 19479 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19495500 19480 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19513500 19498 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19514500 19499 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fe760 PA:108fe764 + 19516500 19501 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19517500 19502 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19518500 19503 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19519500 19504 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19520500 19505 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19553500 19538 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19562500 19547 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19586500 19571 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19587500 19572 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19588500 19573 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fe760 PA:108fe770 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108fe7e8 x8:108fe7e4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108fe7e4 PA:108fe7e4 + 19945500 19930 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108fe764 x2:108fe760 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108fe778 x11:108fe764 PA:108fe774 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe764 PA:108fe770 + 20042500 20027 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20043500 20028 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20077500 20062 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20078500 20063 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20079500 20064 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20080500 20065 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20083500 20068 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe764 PA:108fe770 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108fe778 PA:108fe778 + 20246500 20231 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20247500 20232 1c001a5e 00168693 addi x13, x13, 1 x13=108fe779 x13:108fe778 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108fe779 PA:108fe779 + 20273500 20258 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20274500 20259 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108fe764 x2:108fe760 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108fe740 x2:108fe760 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108fe7e4 x2:108fe740 PA:108fe758 + 20317500 20302 1c001a66 01062783 lw x15, 16(x12) x15=108fe778 x12:108fe764 PA:108fe774 + 20318500 20303 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fe764 PA:108fe768 + 20319500 20304 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108fe740 PA:108fe754 + 20320500 20305 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fe740 PA:108fe750 + 20321500 20306 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fe740 PA:108fe74c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fe740 PA:108fe75c + 20338500 20323 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fe740 PA:108fe748 + 20339500 20324 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20340500 20325 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20341500 20326 1c001a78 00c004b3 add x9, x0, x12 x9=108fe764 x12:108fe764 + 20342500 20327 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108fe779 x15:108fe778 PA:108fe778 + 20344500 20329 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fe764 PA:108fe76c + 20368500 20353 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20371500 20356 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fe764 PA:108fe76c + 20454500 20439 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 20476500 20461 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20477500 20462 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fe778 x9:108fe764 PA:108fe774 + 20518500 20503 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108fe779 x20:108fe778 PA:108fe778 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104108 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fe77a x20:108fe779 PA:108fe779 + 20591500 20576 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20592500 20577 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 20594500 20579 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20595500 20580 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fe740 PA:108fe75c + 20611500 20596 1c001b02 01812403 lw x8, 24(x2) x8=108fe7e4 x2:108fe740 PA:108fe758 + 20612500 20597 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108fe740 PA:108fe754 + 20613500 20598 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fe740 PA:108fe750 + 20614500 20599 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fe740 PA:108fe74c + 20615500 20600 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fe740 PA:108fe748 + 20616500 20601 1c001b0c 02010113 addi x2, x2, 32 x2=108fe760 x2:108fe740 + 20617500 20602 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108fe7e8 x24:108fe7e8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20658500 20643 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20659500 20644 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20662500 20647 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20663500 20648 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20664500 20649 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20666500 20651 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20667500 20652 1c001778 fddff06f jal x0, -36 + 20669500 20654 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20670500 20655 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 20671500 20656 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20672500 20657 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 20673500 20658 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 20674500 20659 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 20675500 20660 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 20676500 20661 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 20677500 20662 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20678500 20663 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104108 + 20682500 20667 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20683500 20668 1c001bca 16a0006f jal x0, 362 + 20685500 20670 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20686500 20671 1c001d36 e69ff06f jal x0, -408 + 20689500 20674 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20703500 20688 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20704500 20689 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20707500 20692 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20708500 20693 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20709500 20694 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20711500 20696 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20712500 20697 1c001778 fddff06f jal x0, -36 + 20714500 20699 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20715500 20700 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 20716500 20701 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20717500 20702 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 20718500 20703 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 20719500 20704 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 20720500 20705 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 20721500 20706 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 20722500 20707 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20723500 20708 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104108 + 20727500 20712 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20728500 20713 1c001bca 16a0006f jal x0, 362 + 20730500 20715 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20731500 20716 1c001d36 e69ff06f jal x0, -408 + 20734500 20719 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20748500 20733 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20749500 20734 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20752500 20737 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20755500 20740 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108fe760 PA:108fe764 + 20756500 20741 1c001bd0 00012423 sw x0, 8(x2) x2:108fe760 PA:108fe768 + 20757500 20742 1c001bd2 00010623 sb x0, 12(x2) x2:108fe760 PA:108fe76c + 20758500 20743 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20759500 20744 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20760500 20745 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20761500 20746 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fe760 PA:108fe764 + 20762500 20747 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20763500 20748 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20764500 20749 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20765500 20750 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20766500 20751 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20767500 20752 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20768500 20753 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20769500 20754 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20787500 20772 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20788500 20773 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20791500 20776 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20792500 20777 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20793500 20778 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20796500 20781 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20799500 20784 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20802500 20787 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20805500 20790 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20806500 20791 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20807500 20792 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20808500 20793 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20811500 20796 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20812500 20797 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20815500 20800 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20816500 20801 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20819500 20804 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20821500 20806 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20824500 20809 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20825500 20810 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20828500 20813 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20829500 20814 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20830500 20815 1c001f42 e09ff06f jal x0, -504 + 20832500 20817 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20833500 20818 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fe760 PA:108fe770 + 20834500 20819 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20837500 20822 1c001e34 00440c13 addi x24, x8, 4 x24=108fe7ec x8:108fe7e8 + 20838500 20823 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:108fe7e8 PA:108fe7e8 + 20839500 20824 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20842500 20827 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 20845500 20830 1c001e64 00410593 addi x11, x2, 4 x11=108fe764 x2:108fe760 + 20846500 20831 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20848500 20833 1c0019fe 0105a683 lw x13, 16(x11) x13=108fe778 x11:108fe764 PA:108fe774 + 20849500 20834 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe764 PA:108fe770 + 20850500 20835 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20851500 20836 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 20885500 20870 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 20886500 20871 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20887500 20872 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20888500 20873 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20891500 20876 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fe764 PA:108fe770 + 20892500 20877 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 20926500 20911 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 20960500 20945 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20991500 20976 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20992500 20977 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 20995500 20980 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20997500 20982 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 21000500 20985 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 21001500 20986 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:108fe778 PA:108fe778 + 21002500 20987 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21003500 20988 1c001a5e 00168693 addi x13, x13, 1 x13=108fe779 x13:108fe778 + 21004500 20989 1c001a60 fb1ff06f jal x0, -80 + 21006500 20991 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21007500 20992 1c001a12 00068023 sb x0, 0(x13) x13:108fe779 PA:108fe779 + 21008500 20993 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21010500 20995 1c001e68 f17ff06f jal x0, -234 + 21012500 20997 1c001d7e 00410613 addi x12, x2, 4 x12=108fe764 x2:108fe760 + 21013500 20998 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21014500 20999 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21015500 21000 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21017500 21002 1c001a62 fe010113 addi x2, x2, -32 x2=108fe740 x2:108fe760 + 21018500 21003 1c001a64 00812c23 sw x8, 24(x2) x8:108fe7e8 x2:108fe740 PA:108fe758 + 21019500 21004 1c001a66 01062783 lw x15, 16(x12) x15=108fe778 x12:108fe764 PA:108fe774 + 21020500 21005 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fe764 PA:108fe768 + 21021500 21006 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108fe740 PA:108fe754 + 21022500 21007 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fe740 PA:108fe750 + 21023500 21008 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fe740 PA:108fe74c + 21024500 21009 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fe740 PA:108fe75c + 21025500 21010 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fe740 PA:108fe748 + 21026500 21011 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21027500 21012 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21028500 21013 1c001a78 00c004b3 add x9, x0, x12 x9=108fe764 x12:108fe764 + 21029500 21014 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=108fe779 x15:108fe778 PA:108fe778 + 21031500 21016 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 21032500 21017 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21033500 21018 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fe764 PA:108fe76c + 21035500 21020 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21038500 21023 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 21040500 21025 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21041500 21026 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21044500 21029 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21045500 21030 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21046500 21031 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21049500 21034 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21050500 21035 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21051500 21036 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21052500 21037 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21053500 21038 1c001b36 f71ff06f jal x0, -144 + 21055500 21040 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fe764 PA:108fe76c + 21057500 21042 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21060500 21045 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 21062500 21047 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21063500 21048 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21066500 21051 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 21067500 21052 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21068500 21053 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21069500 21054 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21070500 21055 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fe778 x9:108fe764 PA:108fe774 + 21072500 21057 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=108fe779 x20:108fe778 PA:108fe778 + 21074500 21059 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 21077500 21062 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21078500 21063 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21080500 21065 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 21081500 21066 1c001778 fddff06f jal x0, -36 + 21083500 21068 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21084500 21069 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 21085500 21070 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21086500 21071 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 21087500 21072 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 21088500 21073 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 21089500 21074 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 21090500 21075 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 21091500 21076 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21092500 21077 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104108 + 21096500 21081 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21097500 21082 1c001b62 f8bff06f jal x0, -118 + 21099500 21084 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fe77a x20:108fe779 PA:108fe779 + 21101500 21086 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21102500 21087 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fe764 PA:108fe764 + 21104500 21089 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21105500 21090 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21108500 21093 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fe740 PA:108fe75c + 21109500 21094 1c001b02 01812403 lw x8, 24(x2) x8=108fe7e8 x2:108fe740 PA:108fe758 + 21110500 21095 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108fe740 PA:108fe754 + 21111500 21096 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fe740 PA:108fe750 + 21112500 21097 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fe740 PA:108fe74c + 21113500 21098 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fe740 PA:108fe748 + 21114500 21099 1c001b0c 02010113 addi x2, x2, 32 x2=108fe760 x2:108fe740 + 21115500 21100 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21117500 21102 1c001d86 01800433 add x8, x0, x24 x8=108fe7ec x24:108fe7ec + 21118500 21103 1c001d88 fadff06f jal x0, -84 + 21120500 21105 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21121500 21106 1c001d36 e69ff06f jal x0, -408 + 21124500 21109 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21139500 21124 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21140500 21125 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21143500 21128 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21144500 21129 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21145500 21130 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21147500 21132 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21148500 21133 1c001778 fddff06f jal x0, -36 + 21150500 21135 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21151500 21136 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 21152500 21137 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21153500 21138 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 21154500 21139 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 21155500 21140 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 21156500 21141 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 21157500 21142 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 21158500 21143 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21159500 21144 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104108 + 21163500 21148 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21164500 21149 1c001bca 16a0006f jal x0, 362 + 21166500 21151 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21167500 21152 1c001d36 e69ff06f jal x0, -408 + 21170500 21155 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21186500 21171 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21187500 21172 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21190500 21175 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21191500 21176 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21192500 21177 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21194500 21179 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21195500 21180 1c001778 fddff06f jal x0, -36 + 21197500 21182 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21198500 21183 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 21199500 21184 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21200500 21185 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 21201500 21186 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 21202500 21187 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 21203500 21188 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 21204500 21189 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 21205500 21190 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21206500 21191 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104108 + 21210500 21195 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21211500 21196 1c001bca 16a0006f jal x0, 362 + 21213500 21198 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21214500 21199 1c001d36 e69ff06f jal x0, -408 + 21217500 21202 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21232500 21217 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21233500 21218 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21236500 21221 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21237500 21222 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21238500 21223 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21240500 21225 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21241500 21226 1c001778 fddff06f jal x0, -36 + 21243500 21228 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21244500 21229 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000041 + 21245500 21230 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21246500 21231 1c00175e 00379713 slli x14, x15, 0x3 x14=00000208 x15:00000041 + 21247500 21232 1c001762 00279793 slli x15, x15, 0x2 x15=00000104 x15:00000041 + 21248500 21233 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000208 + 21249500 21234 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000104 x13:00001f80 + 21250500 21235 1c00176a 00e787b3 add x15, x15, x14 x15=00000108 x15:00000100 x14:00000008 + 21251500 21236 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21252500 21237 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104108 + 21256500 21241 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21257500 21242 1c001bca 16a0006f jal x0, 362 + 21259500 21244 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21260500 21245 1c001d36 e69ff06f jal x0, -408 + 21263500 21248 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21278500 21263 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21279500 21264 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21280500 21265 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108fe760 PA:108fe7bc + 21281500 21266 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:108fe760 PA:108fe7b8 + 21282500 21267 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:108fe760 PA:108fe7b4 + 21283500 21268 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:108fe760 PA:108fe7b0 + 21302500 21287 1c001bb0 04c12983 lw x19, 76(x2) x19=00000001 x2:108fe760 PA:108fe7ac + 21305500 21290 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:108fe760 PA:108fe7a8 + 21306500 21291 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:108fe760 PA:108fe7a4 + 21307500 21292 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:108fe760 PA:108fe7a0 + 21308500 21293 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:108fe760 PA:108fe79c + 21309500 21294 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:108fe760 PA:108fe798 + 21310500 21295 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:108fe760 PA:108fe794 + 21311500 21296 1c001bbe 06010113 addi x2, x2, 96 x2=108fe7c0 x2:108fe760 + 21312500 21297 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21314500 21299 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:108fe7c0 PA:108fe7dc + 21316500 21301 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21317500 21302 1c001838 04010113 addi x2, x2, 64 x2=108fe800 x2:108fe7c0 + 21318500 21303 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21320500 21305 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_2.log b/sw/scripts/tracevis/example/traces/trace_core_02_2.log new file mode 100644 index 0000000..86333d9 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_2.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000042 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000002 x10:00000042 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000042 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000002 + 14871500 14856 1c0000a6 05a0206f jal x0, 8282 + 14889500 14874 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14890500 14875 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14891500 14876 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14892500 14877 1c00210c 0e059163 bne x11, x0, 226 x11:00000002 + 14944500 14929 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 14945500 14930 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000042 + 14946500 14931 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000002 x19:00000042 + 14947500 14932 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 14964500 14949 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 14965500 14950 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 14966500 14951 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 14967500 14952 1c00220a 0060006f jal x0, 6 + 14986500 14971 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18321500 18306 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18338500 18323 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18339500 18324 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18361500 18346 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18362500 18347 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18364500 18349 1c00222c 08096283 p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080 + 18388500 18373 1c002230 02a98533 mul x10, x19, x10 x10=00000800 x19:00000002 x10:00000400 + 18389500 18374 1c002234 00550133 add x2, x10, x5 x2=108fec00 x10:00000800 x5:108fe400 + 18390500 18375 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18392500 18377 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18427500 18412 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18435500 18420 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18436500 18421 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18437500 18422 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18438500 18423 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18459500 18444 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000042 + 18476500 18461 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18477500 18462 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000002 x12:00000042 + 18478500 18463 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002 + 18479500 18464 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000002 x12:00000042 + 18480500 18465 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18481500 18466 1c0009d4 63d0006f jal x0, 3644 + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108febc0 x2:108fec00 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108febc0 PA:108febe4 + 18508500 18493 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18509500 18494 1c001818 02c12423 sw x12, 40(x2) x12:00000002 x2:108febc0 PA:108febe8 + 18510500 18495 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108febc0 PA:108febec + 18511500 18496 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18512500 18497 1c00181e 02410693 addi x13, x2, 36 x13=108febe4 x2:108febc0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:108febc0 PA:108febdc + 18533500 18518 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:108febc0 PA:108febf0 + 18534500 18519 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:108febc0 PA:108febf4 + 18535500 18520 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108febc0 PA:108febf8 + 18536500 18521 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108febc0 PA:108febfc + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108febe4 x2:108febc0 PA:108febcc + 18553500 18538 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108feb60 x2:108febc0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108feb78 x2:108feb60 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:108feb60 PA:108febb8 + 18571500 18556 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:108feb60 PA:108febb0 + 18572500 18557 1c001b78 05312623 sw x19, 76(x2) x19:00000002 x2:108feb60 PA:108febac + 18573500 18558 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:108feb60 PA:108feba8 + 18574500 18559 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:108feb60 PA:108feba4 + 18575500 18560 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:108feb60 PA:108feba0 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:108feb60 PA:108feb9c + 18597500 18582 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108feb60 PA:108febbc + 18598500 18583 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:108feb60 PA:108febb4 + 18599500 18584 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:108feb60 PA:108feb98 + 18600500 18585 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:108feb60 PA:108feb94 + 18601500 18586 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18602500 18587 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18603500 18588 1c001b8e 00d00433 add x8, x0, x13 x8=108febe4 x13:108febe4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108feb78 x2:108feb60 PA:108feb74 + 18618500 18603 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18619500 18604 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18620500 18605 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18621500 18606 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18655500 18640 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18656500 18641 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18678500 18663 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18679500 18664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18680500 18665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104110 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18789500 18774 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18790500 18775 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18793500 18778 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18794500 18779 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18795500 18780 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18797500 18782 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18798500 18783 1c001778 fddff06f jal x0, -36 + 18800500 18785 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18801500 18786 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 18802500 18787 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18803500 18788 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 18804500 18789 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 18805500 18790 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 18806500 18791 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 18807500 18792 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 18808500 18793 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18809500 18794 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104110 + 18813500 18798 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18814500 18799 1c001bca 16a0006f jal x0, 362 + 18816500 18801 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18817500 18802 1c001d36 e69ff06f jal x0, -408 + 18820500 18805 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18834500 18819 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18835500 18820 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18838500 18823 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18839500 18824 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18840500 18825 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18842500 18827 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18843500 18828 1c001778 fddff06f jal x0, -36 + 18845500 18830 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18846500 18831 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 18847500 18832 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18848500 18833 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 18849500 18834 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 18850500 18835 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 18851500 18836 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 18852500 18837 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 18853500 18838 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18854500 18839 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104110 + 18858500 18843 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18859500 18844 1c001bca 16a0006f jal x0, 362 + 18861500 18846 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18862500 18847 1c001d36 e69ff06f jal x0, -408 + 18865500 18850 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18883500 18868 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18884500 18869 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18887500 18872 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18888500 18873 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18889500 18874 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18891500 18876 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18892500 18877 1c001778 fddff06f jal x0, -36 + 18894500 18879 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18895500 18880 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 18896500 18881 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18897500 18882 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 18898500 18883 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 18899500 18884 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 18900500 18885 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 18901500 18886 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 18902500 18887 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18903500 18888 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104110 + 18907500 18892 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18908500 18893 1c001bca 16a0006f jal x0, 362 + 18910500 18895 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18911500 18896 1c001d36 e69ff06f jal x0, -408 + 18914500 18899 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18930500 18915 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18931500 18916 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18934500 18919 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18935500 18920 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18936500 18921 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18938500 18923 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18939500 18924 1c001778 fddff06f jal x0, -36 + 18941500 18926 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18942500 18927 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 18943500 18928 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18944500 18929 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 18945500 18930 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 18946500 18931 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 18947500 18932 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 18948500 18933 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 18949500 18934 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18950500 18935 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104110 + 18954500 18939 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18955500 18940 1c001bca 16a0006f jal x0, 362 + 18957500 18942 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18958500 18943 1c001d36 e69ff06f jal x0, -408 + 18961500 18946 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18978500 18963 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18979500 18964 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18982500 18967 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18983500 18968 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18984500 18969 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18986500 18971 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18987500 18972 1c001778 fddff06f jal x0, -36 + 18989500 18974 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18990500 18975 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 18991500 18976 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18992500 18977 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 18993500 18978 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 18994500 18979 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 18995500 18980 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 18996500 18981 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 18997500 18982 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18998500 18983 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104110 + 19002500 18987 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19003500 18988 1c001bca 16a0006f jal x0, 362 + 19005500 18990 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19006500 18991 1c001d36 e69ff06f jal x0, -408 + 19009500 18994 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19024500 19009 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19025500 19010 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19028500 19013 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19029500 19014 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19030500 19015 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19032500 19017 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19033500 19018 1c001778 fddff06f jal x0, -36 + 19035500 19020 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19036500 19021 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19037500 19022 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19038500 19023 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19039500 19024 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19040500 19025 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19041500 19026 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19042500 19027 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19043500 19028 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19044500 19029 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104110 + 19048500 19033 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19049500 19034 1c001bca 16a0006f jal x0, 362 + 19051500 19036 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19052500 19037 1c001d36 e69ff06f jal x0, -408 + 19055500 19040 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19075500 19060 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19076500 19061 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19079500 19064 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19080500 19065 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19081500 19066 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19083500 19068 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19084500 19069 1c001778 fddff06f jal x0, -36 + 19086500 19071 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19087500 19072 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19088500 19073 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19089500 19074 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19090500 19075 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19091500 19076 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19092500 19077 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19093500 19078 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19094500 19079 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19095500 19080 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104110 + 19099500 19084 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19100500 19085 1c001bca 16a0006f jal x0, 362 + 19102500 19087 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19103500 19088 1c001d36 e69ff06f jal x0, -408 + 19106500 19091 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19120500 19105 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19121500 19106 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19124500 19109 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19125500 19110 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19126500 19111 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19128500 19113 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19129500 19114 1c001778 fddff06f jal x0, -36 + 19131500 19116 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19132500 19117 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19133500 19118 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19134500 19119 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19135500 19120 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19136500 19121 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19137500 19122 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19138500 19123 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19139500 19124 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19140500 19125 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104110 + 19144500 19129 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19145500 19130 1c001bca 16a0006f jal x0, 362 + 19147500 19132 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19148500 19133 1c001d36 e69ff06f jal x0, -408 + 19151500 19136 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19166500 19151 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19167500 19152 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19170500 19155 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19171500 19156 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19172500 19157 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19174500 19159 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19175500 19160 1c001778 fddff06f jal x0, -36 + 19177500 19162 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19178500 19163 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19179500 19164 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19180500 19165 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19181500 19166 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19182500 19167 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19183500 19168 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19184500 19169 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19185500 19170 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19186500 19171 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104110 + 19190500 19175 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19191500 19176 1c001bca 16a0006f jal x0, 362 + 19193500 19178 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19194500 19179 1c001d36 e69ff06f jal x0, -408 + 19197500 19182 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19218500 19203 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19219500 19204 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19222500 19207 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19223500 19208 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19224500 19209 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19226500 19211 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19227500 19212 1c001778 fddff06f jal x0, -36 + 19229500 19214 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19230500 19215 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19231500 19216 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19232500 19217 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19233500 19218 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19234500 19219 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19235500 19220 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19236500 19221 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19237500 19222 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19238500 19223 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104110 + 19242500 19227 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19243500 19228 1c001bca 16a0006f jal x0, 362 + 19245500 19230 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19246500 19231 1c001d36 e69ff06f jal x0, -408 + 19249500 19234 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19263500 19248 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19264500 19249 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19267500 19252 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19268500 19253 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19269500 19254 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19271500 19256 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19272500 19257 1c001778 fddff06f jal x0, -36 + 19274500 19259 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19275500 19260 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19276500 19261 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19277500 19262 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19278500 19263 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19279500 19264 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19280500 19265 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19281500 19266 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19282500 19267 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19283500 19268 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104110 + 19287500 19272 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19288500 19273 1c001bca 16a0006f jal x0, 362 + 19290500 19275 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19291500 19276 1c001d36 e69ff06f jal x0, -408 + 19294500 19279 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19308500 19293 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19309500 19294 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19312500 19297 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19313500 19298 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19314500 19299 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19316500 19301 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19317500 19302 1c001778 fddff06f jal x0, -36 + 19319500 19304 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19320500 19305 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19321500 19306 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19322500 19307 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19323500 19308 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19324500 19309 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19325500 19310 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19326500 19311 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19327500 19312 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19328500 19313 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104110 + 19332500 19317 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19333500 19318 1c001bca 16a0006f jal x0, 362 + 19335500 19320 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19336500 19321 1c001d36 e69ff06f jal x0, -408 + 19339500 19324 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19360500 19345 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19361500 19346 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19364500 19349 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19365500 19350 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19366500 19351 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19368500 19353 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19369500 19354 1c001778 fddff06f jal x0, -36 + 19371500 19356 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19372500 19357 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19373500 19358 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19374500 19359 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19375500 19360 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19376500 19361 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19377500 19362 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19378500 19363 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19379500 19364 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19380500 19365 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104110 + 19384500 19369 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19385500 19370 1c001bca 16a0006f jal x0, 362 + 19387500 19372 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19388500 19373 1c001d36 e69ff06f jal x0, -408 + 19391500 19376 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19410500 19395 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19411500 19396 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19414500 19399 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19415500 19400 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19416500 19401 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19418500 19403 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19419500 19404 1c001778 fddff06f jal x0, -36 + 19421500 19406 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19422500 19407 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 19423500 19408 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19424500 19409 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 19425500 19410 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 19426500 19411 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 19427500 19412 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 19428500 19413 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 19429500 19414 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19430500 19415 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104110 + 19434500 19419 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19435500 19420 1c001bca 16a0006f jal x0, 362 + 19437500 19422 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19438500 19423 1c001d36 e69ff06f jal x0, -408 + 19441500 19426 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19460500 19445 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19461500 19446 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19464500 19449 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19467500 19452 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108feb60 PA:108feb64 + 19488500 19473 1c001bd0 00012423 sw x0, 8(x2) x2:108feb60 PA:108feb68 + 19489500 19474 1c001bd2 00010623 sb x0, 12(x2) x2:108feb60 PA:108feb6c + 19490500 19475 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19491500 19476 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19513500 19498 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19514500 19499 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108feb60 PA:108feb64 + 19518500 19503 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19519500 19504 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19520500 19505 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19521500 19506 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19522500 19507 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19557500 19542 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19562500 19547 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19586500 19571 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19587500 19572 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19588500 19573 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108feb60 PA:108feb70 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108febe8 x8:108febe4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108febe4 PA:108febe4 + 19947500 19932 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108feb64 x2:108feb60 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108feb78 x11:108feb64 PA:108feb74 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108feb64 PA:108feb70 + 20043500 20028 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20044500 20029 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20078500 20063 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20079500 20064 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20080500 20065 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20081500 20066 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20084500 20069 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108feb64 PA:108feb70 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108feb78 PA:108feb78 + 20247500 20232 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20248500 20233 1c001a5e 00168693 addi x13, x13, 1 x13=108feb79 x13:108feb78 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108feb79 PA:108feb79 + 20267500 20252 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20269500 20254 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108feb64 x2:108feb60 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108feb40 x2:108feb60 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108febe4 x2:108feb40 PA:108feb58 + 20319500 20304 1c001a66 01062783 lw x15, 16(x12) x15=108feb78 x12:108feb64 PA:108feb74 + 20320500 20305 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108feb64 PA:108feb68 + 20321500 20306 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108feb40 PA:108feb54 + 20322500 20307 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108feb40 PA:108feb50 + 20323500 20308 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108feb40 PA:108feb4c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108feb40 PA:108feb5c + 20340500 20325 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108feb40 PA:108feb48 + 20341500 20326 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20342500 20327 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20343500 20328 1c001a78 00c004b3 add x9, x0, x12 x9=108feb64 x12:108feb64 + 20344500 20329 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108feb79 x15:108feb78 PA:108feb78 + 20346500 20331 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108feb64 PA:108feb6c + 20369500 20354 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20372500 20357 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108feb64 PA:108feb6c + 20450500 20435 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 20470500 20455 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20471500 20456 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108feb78 x9:108feb64 PA:108feb74 + 20512500 20497 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108feb79 x20:108feb78 PA:108feb78 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104110 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108feb7a x20:108feb79 PA:108feb79 + 20587500 20572 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20588500 20573 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 20590500 20575 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20591500 20576 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108feb40 PA:108feb5c + 20612500 20597 1c001b02 01812403 lw x8, 24(x2) x8=108febe4 x2:108feb40 PA:108feb58 + 20613500 20598 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108feb40 PA:108feb54 + 20614500 20599 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108feb40 PA:108feb50 + 20615500 20600 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108feb40 PA:108feb4c + 20616500 20601 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108feb40 PA:108feb48 + 20617500 20602 1c001b0c 02010113 addi x2, x2, 32 x2=108feb60 x2:108feb40 + 20618500 20603 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108febe8 x24:108febe8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20660500 20645 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20661500 20646 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20664500 20649 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20665500 20650 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20666500 20651 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20668500 20653 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20669500 20654 1c001778 fddff06f jal x0, -36 + 20671500 20656 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20672500 20657 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 20673500 20658 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20674500 20659 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 20675500 20660 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 20676500 20661 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 20677500 20662 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 20678500 20663 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 20679500 20664 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20680500 20665 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104110 + 20684500 20669 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20685500 20670 1c001bca 16a0006f jal x0, 362 + 20687500 20672 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20688500 20673 1c001d36 e69ff06f jal x0, -408 + 20691500 20676 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20705500 20690 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20706500 20691 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20709500 20694 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20710500 20695 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20711500 20696 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20713500 20698 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20714500 20699 1c001778 fddff06f jal x0, -36 + 20716500 20701 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20717500 20702 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 20718500 20703 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20719500 20704 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 20720500 20705 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 20721500 20706 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 20722500 20707 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 20723500 20708 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 20724500 20709 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20725500 20710 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104110 + 20729500 20714 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20730500 20715 1c001bca 16a0006f jal x0, 362 + 20732500 20717 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20733500 20718 1c001d36 e69ff06f jal x0, -408 + 20736500 20721 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20750500 20735 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20751500 20736 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20754500 20739 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20757500 20742 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108feb60 PA:108feb64 + 20758500 20743 1c001bd0 00012423 sw x0, 8(x2) x2:108feb60 PA:108feb68 + 20759500 20744 1c001bd2 00010623 sb x0, 12(x2) x2:108feb60 PA:108feb6c + 20760500 20745 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20761500 20746 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20762500 20747 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20763500 20748 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108feb60 PA:108feb64 + 20764500 20749 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20765500 20750 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20766500 20751 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20767500 20752 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20768500 20753 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20769500 20754 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20770500 20755 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20771500 20756 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20789500 20774 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20790500 20775 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20793500 20778 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20794500 20779 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20795500 20780 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20798500 20783 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20801500 20786 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20804500 20789 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20807500 20792 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20808500 20793 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20809500 20794 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20810500 20795 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20813500 20798 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20814500 20799 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20817500 20802 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20818500 20803 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20821500 20806 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20823500 20808 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20826500 20811 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20827500 20812 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20830500 20815 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20831500 20816 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20832500 20817 1c001f42 e09ff06f jal x0, -504 + 20834500 20819 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20835500 20820 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108feb60 PA:108feb70 + 20836500 20821 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20839500 20824 1c001e34 00440c13 addi x24, x8, 4 x24=108febec x8:108febe8 + 20840500 20825 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108febe8 PA:108febe8 + 20841500 20826 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20844500 20829 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20847500 20832 1c001e64 00410593 addi x11, x2, 4 x11=108feb64 x2:108feb60 + 20848500 20833 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20850500 20835 1c0019fe 0105a683 lw x13, 16(x11) x13=108feb78 x11:108feb64 PA:108feb74 + 20851500 20836 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108feb64 PA:108feb70 + 20852500 20837 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20853500 20838 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20887500 20872 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20888500 20873 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20889500 20874 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20890500 20875 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20893500 20878 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108feb64 PA:108feb70 + 20894500 20879 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20928500 20913 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20962500 20947 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20993500 20978 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20994500 20979 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20997500 20982 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20999500 20984 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 21002500 20987 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 21003500 20988 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108feb78 PA:108feb78 + 21004500 20989 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21005500 20990 1c001a5e 00168693 addi x13, x13, 1 x13=108feb79 x13:108feb78 + 21006500 20991 1c001a60 fb1ff06f jal x0, -80 + 21008500 20993 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21009500 20994 1c001a12 00068023 sb x0, 0(x13) x13:108feb79 PA:108feb79 + 21010500 20995 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21012500 20997 1c001e68 f17ff06f jal x0, -234 + 21014500 20999 1c001d7e 00410613 addi x12, x2, 4 x12=108feb64 x2:108feb60 + 21015500 21000 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21016500 21001 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21017500 21002 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21019500 21004 1c001a62 fe010113 addi x2, x2, -32 x2=108feb40 x2:108feb60 + 21020500 21005 1c001a64 00812c23 sw x8, 24(x2) x8:108febe8 x2:108feb40 PA:108feb58 + 21021500 21006 1c001a66 01062783 lw x15, 16(x12) x15=108feb78 x12:108feb64 PA:108feb74 + 21022500 21007 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108feb64 PA:108feb68 + 21023500 21008 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108feb40 PA:108feb54 + 21024500 21009 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108feb40 PA:108feb50 + 21025500 21010 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108feb40 PA:108feb4c + 21026500 21011 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108feb40 PA:108feb5c + 21027500 21012 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108feb40 PA:108feb48 + 21028500 21013 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21029500 21014 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21030500 21015 1c001a78 00c004b3 add x9, x0, x12 x9=108feb64 x12:108feb64 + 21031500 21016 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108feb79 x15:108feb78 PA:108feb78 + 21033500 21018 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 21034500 21019 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21035500 21020 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108feb64 PA:108feb6c + 21037500 21022 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21040500 21025 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 21042500 21027 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21043500 21028 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21046500 21031 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21047500 21032 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21048500 21033 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21051500 21036 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21052500 21037 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21053500 21038 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21054500 21039 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21055500 21040 1c001b36 f71ff06f jal x0, -144 + 21057500 21042 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108feb64 PA:108feb6c + 21059500 21044 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21062500 21047 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 21064500 21049 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21065500 21050 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21068500 21053 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 21069500 21054 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21070500 21055 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21071500 21056 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21072500 21057 1c001ae8 0104aa03 lw x20, 16(x9) x20=108feb78 x9:108feb64 PA:108feb74 + 21074500 21059 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108feb79 x20:108feb78 PA:108feb78 + 21076500 21061 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 21079500 21064 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21080500 21065 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21082500 21067 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 21083500 21068 1c001778 fddff06f jal x0, -36 + 21085500 21070 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21086500 21071 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 21087500 21072 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21088500 21073 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 21089500 21074 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 21090500 21075 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 21091500 21076 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 21092500 21077 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 21093500 21078 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21094500 21079 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104110 + 21098500 21083 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21099500 21084 1c001b62 f8bff06f jal x0, -118 + 21101500 21086 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108feb7a x20:108feb79 PA:108feb79 + 21103500 21088 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21104500 21089 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108feb64 PA:108feb64 + 21106500 21091 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21107500 21092 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21110500 21095 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108feb40 PA:108feb5c + 21111500 21096 1c001b02 01812403 lw x8, 24(x2) x8=108febe8 x2:108feb40 PA:108feb58 + 21112500 21097 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108feb40 PA:108feb54 + 21113500 21098 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108feb40 PA:108feb50 + 21114500 21099 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108feb40 PA:108feb4c + 21115500 21100 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108feb40 PA:108feb48 + 21116500 21101 1c001b0c 02010113 addi x2, x2, 32 x2=108feb60 x2:108feb40 + 21117500 21102 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21119500 21104 1c001d86 01800433 add x8, x0, x24 x8=108febec x24:108febec + 21120500 21105 1c001d88 fadff06f jal x0, -84 + 21122500 21107 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21123500 21108 1c001d36 e69ff06f jal x0, -408 + 21126500 21111 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21146500 21131 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21147500 21132 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21150500 21135 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21151500 21136 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21152500 21137 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21154500 21139 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21155500 21140 1c001778 fddff06f jal x0, -36 + 21157500 21142 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21158500 21143 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 21159500 21144 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21160500 21145 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 21161500 21146 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 21162500 21147 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 21163500 21148 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 21164500 21149 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 21165500 21150 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21166500 21151 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104110 + 21170500 21155 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21171500 21156 1c001bca 16a0006f jal x0, 362 + 21173500 21158 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21174500 21159 1c001d36 e69ff06f jal x0, -408 + 21177500 21162 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21192500 21177 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21193500 21178 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21196500 21181 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21197500 21182 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21198500 21183 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21200500 21185 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21201500 21186 1c001778 fddff06f jal x0, -36 + 21203500 21188 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21204500 21189 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 21205500 21190 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21206500 21191 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 21207500 21192 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 21208500 21193 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 21209500 21194 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 21210500 21195 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 21211500 21196 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21212500 21197 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104110 + 21216500 21201 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21217500 21202 1c001bca 16a0006f jal x0, 362 + 21219500 21204 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21220500 21205 1c001d36 e69ff06f jal x0, -408 + 21223500 21208 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21238500 21223 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21239500 21224 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21242500 21227 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21243500 21228 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21244500 21229 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21246500 21231 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21247500 21232 1c001778 fddff06f jal x0, -36 + 21249500 21234 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21250500 21235 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000042 + 21251500 21236 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21252500 21237 1c00175e 00379713 slli x14, x15, 0x3 x14=00000210 x15:00000042 + 21253500 21238 1c001762 00279793 slli x15, x15, 0x2 x15=00000108 x15:00000042 + 21254500 21239 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000210 + 21255500 21240 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000108 x13:00001f80 + 21256500 21241 1c00176a 00e787b3 add x15, x15, x14 x15=00000110 x15:00000100 x14:00000010 + 21257500 21242 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21258500 21243 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104110 + 21262500 21247 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21263500 21248 1c001bca 16a0006f jal x0, 362 + 21265500 21250 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21266500 21251 1c001d36 e69ff06f jal x0, -408 + 21269500 21254 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21284500 21269 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21285500 21270 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21286500 21271 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108feb60 PA:108febbc + 21287500 21272 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:108feb60 PA:108febb8 + 21288500 21273 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:108feb60 PA:108febb4 + 21289500 21274 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:108feb60 PA:108febb0 + 21302500 21287 1c001bb0 04c12983 lw x19, 76(x2) x19=00000002 x2:108feb60 PA:108febac + 21303500 21288 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:108feb60 PA:108feba8 + 21304500 21289 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:108feb60 PA:108feba4 + 21305500 21290 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:108feb60 PA:108feba0 + 21306500 21291 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:108feb60 PA:108feb9c + 21307500 21292 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:108feb60 PA:108feb98 + 21308500 21293 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:108feb60 PA:108feb94 + 21309500 21294 1c001bbe 06010113 addi x2, x2, 96 x2=108febc0 x2:108feb60 + 21310500 21295 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21312500 21297 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:108febc0 PA:108febdc + 21313500 21298 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21314500 21299 1c001838 04010113 addi x2, x2, 64 x2=108fec00 x2:108febc0 + 21315500 21300 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21317500 21302 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_3.log b/sw/scripts/tracevis/example/traces/trace_core_02_3.log new file mode 100644 index 0000000..dbfaf7a --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_3.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000043 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000003 x10:00000043 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000043 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000003 + 14871500 14856 1c0000a6 05a0206f jal x0, 8282 + 14889500 14874 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14890500 14875 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14891500 14876 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14892500 14877 1c00210c 0e059163 bne x11, x0, 226 x11:00000003 + 14944500 14929 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 14945500 14930 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000043 + 14946500 14931 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000003 x19:00000043 + 14947500 14932 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 14964500 14949 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 14965500 14950 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 14966500 14951 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 14967500 14952 1c00220a 0060006f jal x0, 6 + 14986500 14971 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18321500 18306 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18338500 18323 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18339500 18324 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18361500 18346 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18362500 18347 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18364500 18349 1c00222c 08096283 p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080 + 18388500 18373 1c002230 02a98533 mul x10, x19, x10 x10=00000c00 x19:00000003 x10:00000400 + 18389500 18374 1c002234 00550133 add x2, x10, x5 x2=108ff000 x10:00000c00 x5:108fe400 + 18390500 18375 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18392500 18377 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18427500 18412 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18435500 18420 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18436500 18421 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18437500 18422 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18438500 18423 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18459500 18444 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000043 + 18476500 18461 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18477500 18462 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000002 x12:00000043 + 18478500 18463 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002 + 18479500 18464 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000003 x12:00000043 + 18480500 18465 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18481500 18466 1c0009d4 63d0006f jal x0, 3644 + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108fefc0 x2:108ff000 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108fefc0 PA:108fefe4 + 18504500 18489 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18505500 18490 1c001818 02c12423 sw x12, 40(x2) x12:00000003 x2:108fefc0 PA:108fefe8 + 18506500 18491 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108fefc0 PA:108fefec + 18507500 18492 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18508500 18493 1c00181e 02410693 addi x13, x2, 36 x13=108fefe4 x2:108fefc0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:108fefc0 PA:108fefdc + 18532500 18517 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:108fefc0 PA:108feff0 + 18533500 18518 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:108fefc0 PA:108feff4 + 18534500 18519 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108fefc0 PA:108feff8 + 18535500 18520 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108fefc0 PA:108feffc + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108fefe4 x2:108fefc0 PA:108fefcc + 18552500 18537 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108fef60 x2:108fefc0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108fef78 x2:108fef60 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:108fef60 PA:108fefb8 + 18572500 18557 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:108fef60 PA:108fefb0 + 18573500 18558 1c001b78 05312623 sw x19, 76(x2) x19:00000003 x2:108fef60 PA:108fefac + 18574500 18559 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:108fef60 PA:108fefa8 + 18575500 18560 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:108fef60 PA:108fefa4 + 18576500 18561 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:108fef60 PA:108fefa0 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:108fef60 PA:108fef9c + 18596500 18581 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108fef60 PA:108fefbc + 18597500 18582 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:108fef60 PA:108fefb4 + 18598500 18583 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:108fef60 PA:108fef98 + 18599500 18584 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:108fef60 PA:108fef94 + 18600500 18585 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18601500 18586 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18602500 18587 1c001b8e 00d00433 add x8, x0, x13 x8=108fefe4 x13:108fefe4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108fef78 x2:108fef60 PA:108fef74 + 18619500 18604 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18620500 18605 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18621500 18606 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18622500 18607 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18657500 18642 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18658500 18643 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18678500 18663 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18679500 18664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18680500 18665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104118 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18791500 18776 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18792500 18777 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18795500 18780 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18796500 18781 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18797500 18782 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18799500 18784 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18800500 18785 1c001778 fddff06f jal x0, -36 + 18802500 18787 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18803500 18788 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 18804500 18789 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18805500 18790 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 18806500 18791 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 18807500 18792 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 18808500 18793 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 18809500 18794 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 18810500 18795 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18811500 18796 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104118 + 18815500 18800 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18816500 18801 1c001bca 16a0006f jal x0, 362 + 18818500 18803 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18819500 18804 1c001d36 e69ff06f jal x0, -408 + 18822500 18807 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18838500 18823 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18839500 18824 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18842500 18827 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18843500 18828 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18844500 18829 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18846500 18831 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18847500 18832 1c001778 fddff06f jal x0, -36 + 18849500 18834 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18850500 18835 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 18851500 18836 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18852500 18837 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 18853500 18838 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 18854500 18839 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 18855500 18840 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 18856500 18841 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 18857500 18842 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18858500 18843 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104118 + 18862500 18847 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18863500 18848 1c001bca 16a0006f jal x0, 362 + 18865500 18850 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18866500 18851 1c001d36 e69ff06f jal x0, -408 + 18869500 18854 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18886500 18871 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18887500 18872 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18890500 18875 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18891500 18876 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18892500 18877 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18894500 18879 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18895500 18880 1c001778 fddff06f jal x0, -36 + 18897500 18882 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18898500 18883 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 18899500 18884 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18900500 18885 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 18901500 18886 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 18902500 18887 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 18903500 18888 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 18904500 18889 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 18905500 18890 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18906500 18891 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104118 + 18910500 18895 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18911500 18896 1c001bca 16a0006f jal x0, 362 + 18913500 18898 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18914500 18899 1c001d36 e69ff06f jal x0, -408 + 18917500 18902 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18933500 18918 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18934500 18919 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18937500 18922 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18938500 18923 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18939500 18924 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18941500 18926 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18942500 18927 1c001778 fddff06f jal x0, -36 + 18944500 18929 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18945500 18930 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 18946500 18931 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18947500 18932 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 18948500 18933 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 18949500 18934 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 18950500 18935 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 18951500 18936 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 18952500 18937 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18953500 18938 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104118 + 18957500 18942 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18958500 18943 1c001bca 16a0006f jal x0, 362 + 18960500 18945 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18961500 18946 1c001d36 e69ff06f jal x0, -408 + 18964500 18949 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18982500 18967 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18983500 18968 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18986500 18971 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18987500 18972 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18988500 18973 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18990500 18975 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18991500 18976 1c001778 fddff06f jal x0, -36 + 18993500 18978 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18994500 18979 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 18995500 18980 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18996500 18981 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 18997500 18982 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 18998500 18983 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 18999500 18984 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19000500 18985 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19001500 18986 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19002500 18987 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104118 + 19006500 18991 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19007500 18992 1c001bca 16a0006f jal x0, 362 + 19009500 18994 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19010500 18995 1c001d36 e69ff06f jal x0, -408 + 19013500 18998 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19028500 19013 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19029500 19014 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19032500 19017 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19033500 19018 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19034500 19019 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19036500 19021 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19037500 19022 1c001778 fddff06f jal x0, -36 + 19039500 19024 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19040500 19025 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19041500 19026 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19042500 19027 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19043500 19028 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19044500 19029 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19045500 19030 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19046500 19031 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19047500 19032 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19048500 19033 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104118 + 19052500 19037 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19053500 19038 1c001bca 16a0006f jal x0, 362 + 19055500 19040 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19056500 19041 1c001d36 e69ff06f jal x0, -408 + 19059500 19044 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19077500 19062 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19078500 19063 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19081500 19066 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19082500 19067 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19083500 19068 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19085500 19070 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19086500 19071 1c001778 fddff06f jal x0, -36 + 19088500 19073 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19089500 19074 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19090500 19075 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19091500 19076 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19092500 19077 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19093500 19078 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19094500 19079 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19095500 19080 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19096500 19081 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19097500 19082 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104118 + 19101500 19086 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19102500 19087 1c001bca 16a0006f jal x0, 362 + 19104500 19089 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19105500 19090 1c001d36 e69ff06f jal x0, -408 + 19108500 19093 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19123500 19108 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19124500 19109 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19127500 19112 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19128500 19113 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19129500 19114 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19131500 19116 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19132500 19117 1c001778 fddff06f jal x0, -36 + 19134500 19119 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19135500 19120 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19136500 19121 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19137500 19122 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19138500 19123 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19139500 19124 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19140500 19125 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19141500 19126 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19142500 19127 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19143500 19128 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104118 + 19147500 19132 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19148500 19133 1c001bca 16a0006f jal x0, 362 + 19150500 19135 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19151500 19136 1c001d36 e69ff06f jal x0, -408 + 19154500 19139 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19169500 19154 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19170500 19155 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19173500 19158 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19174500 19159 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19175500 19160 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19177500 19162 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19178500 19163 1c001778 fddff06f jal x0, -36 + 19180500 19165 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19181500 19166 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19182500 19167 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19183500 19168 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19184500 19169 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19185500 19170 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19186500 19171 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19187500 19172 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19188500 19173 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19189500 19174 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104118 + 19193500 19178 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19194500 19179 1c001bca 16a0006f jal x0, 362 + 19196500 19181 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19197500 19182 1c001d36 e69ff06f jal x0, -408 + 19200500 19185 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19220500 19205 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19221500 19206 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19224500 19209 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19225500 19210 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19226500 19211 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19228500 19213 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19229500 19214 1c001778 fddff06f jal x0, -36 + 19231500 19216 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19232500 19217 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19233500 19218 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19234500 19219 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19235500 19220 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19236500 19221 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19237500 19222 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19238500 19223 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19239500 19224 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19240500 19225 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104118 + 19244500 19229 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19245500 19230 1c001bca 16a0006f jal x0, 362 + 19247500 19232 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19248500 19233 1c001d36 e69ff06f jal x0, -408 + 19251500 19236 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19266500 19251 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19267500 19252 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19270500 19255 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19271500 19256 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19272500 19257 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19274500 19259 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19275500 19260 1c001778 fddff06f jal x0, -36 + 19277500 19262 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19278500 19263 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19279500 19264 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19280500 19265 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19281500 19266 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19282500 19267 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19283500 19268 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19284500 19269 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19285500 19270 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19286500 19271 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104118 + 19290500 19275 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19291500 19276 1c001bca 16a0006f jal x0, 362 + 19293500 19278 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19294500 19279 1c001d36 e69ff06f jal x0, -408 + 19297500 19282 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19312500 19297 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19313500 19298 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19316500 19301 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19317500 19302 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19318500 19303 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19320500 19305 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19321500 19306 1c001778 fddff06f jal x0, -36 + 19323500 19308 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19324500 19309 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19325500 19310 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19326500 19311 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19327500 19312 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19328500 19313 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19329500 19314 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19330500 19315 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19331500 19316 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19332500 19317 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104118 + 19336500 19321 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19337500 19322 1c001bca 16a0006f jal x0, 362 + 19339500 19324 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19340500 19325 1c001d36 e69ff06f jal x0, -408 + 19343500 19328 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19366500 19351 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19367500 19352 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19370500 19355 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19371500 19356 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19372500 19357 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19374500 19359 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19375500 19360 1c001778 fddff06f jal x0, -36 + 19377500 19362 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19378500 19363 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19379500 19364 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19380500 19365 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19381500 19366 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19382500 19367 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19383500 19368 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19384500 19369 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19385500 19370 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19386500 19371 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104118 + 19390500 19375 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19391500 19376 1c001bca 16a0006f jal x0, 362 + 19393500 19378 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19394500 19379 1c001d36 e69ff06f jal x0, -408 + 19397500 19382 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19416500 19401 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19417500 19402 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19420500 19405 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19421500 19406 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19422500 19407 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19424500 19409 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19425500 19410 1c001778 fddff06f jal x0, -36 + 19427500 19412 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19428500 19413 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 19429500 19414 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19430500 19415 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 19431500 19416 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 19432500 19417 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 19433500 19418 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 19434500 19419 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 19435500 19420 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19436500 19421 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104118 + 19440500 19425 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19441500 19426 1c001bca 16a0006f jal x0, 362 + 19443500 19428 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19444500 19429 1c001d36 e69ff06f jal x0, -408 + 19447500 19432 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19466500 19451 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19467500 19452 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19470500 19455 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19473500 19458 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108fef60 PA:108fef64 + 19488500 19473 1c001bd0 00012423 sw x0, 8(x2) x2:108fef60 PA:108fef68 + 19490500 19475 1c001bd2 00010623 sb x0, 12(x2) x2:108fef60 PA:108fef6c + 19491500 19476 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19492500 19477 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19513500 19498 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19514500 19499 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fef60 PA:108fef64 + 19517500 19502 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19518500 19503 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19519500 19504 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19520500 19505 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19521500 19506 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19561500 19546 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19562500 19547 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19586500 19571 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19587500 19572 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19588500 19573 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fef60 PA:108fef70 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108fefe8 x8:108fefe4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108fefe4 PA:108fefe4 + 19946500 19931 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108fef64 x2:108fef60 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108fef78 x11:108fef64 PA:108fef74 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fef64 PA:108fef70 + 20044500 20029 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20045500 20030 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20079500 20064 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20080500 20065 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20081500 20066 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20082500 20067 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20085500 20070 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fef64 PA:108fef70 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108fef78 PA:108fef78 + 20248500 20233 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20249500 20234 1c001a5e 00168693 addi x13, x13, 1 x13=108fef79 x13:108fef78 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108fef79 PA:108fef79 + 20268500 20253 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20269500 20254 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108fef64 x2:108fef60 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108fef40 x2:108fef60 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108fefe4 x2:108fef40 PA:108fef58 + 20320500 20305 1c001a66 01062783 lw x15, 16(x12) x15=108fef78 x12:108fef64 PA:108fef74 + 20321500 20306 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fef64 PA:108fef68 + 20322500 20307 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108fef40 PA:108fef54 + 20323500 20308 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fef40 PA:108fef50 + 20324500 20309 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fef40 PA:108fef4c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fef40 PA:108fef5c + 20339500 20324 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fef40 PA:108fef48 + 20340500 20325 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20341500 20326 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20342500 20327 1c001a78 00c004b3 add x9, x0, x12 x9=108fef64 x12:108fef64 + 20343500 20328 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108fef79 x15:108fef78 PA:108fef78 + 20345500 20330 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fef64 PA:108fef6c + 20363500 20348 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20366500 20351 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fef64 PA:108fef6c + 20451500 20436 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 20471500 20456 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20472500 20457 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fef78 x9:108fef64 PA:108fef74 + 20513500 20498 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108fef79 x20:108fef78 PA:108fef78 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104118 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fef7a x20:108fef79 PA:108fef79 + 20588500 20573 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20589500 20574 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 20591500 20576 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20592500 20577 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fef40 PA:108fef5c + 20613500 20598 1c001b02 01812403 lw x8, 24(x2) x8=108fefe4 x2:108fef40 PA:108fef58 + 20614500 20599 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108fef40 PA:108fef54 + 20615500 20600 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fef40 PA:108fef50 + 20616500 20601 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fef40 PA:108fef4c + 20617500 20602 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fef40 PA:108fef48 + 20618500 20603 1c001b0c 02010113 addi x2, x2, 32 x2=108fef60 x2:108fef40 + 20619500 20604 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108fefe8 x24:108fefe8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20662500 20647 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20663500 20648 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20666500 20651 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20667500 20652 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20668500 20653 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20670500 20655 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20671500 20656 1c001778 fddff06f jal x0, -36 + 20673500 20658 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20674500 20659 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 20675500 20660 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20676500 20661 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 20677500 20662 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 20678500 20663 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 20679500 20664 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 20680500 20665 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 20681500 20666 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20682500 20667 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104118 + 20686500 20671 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20687500 20672 1c001bca 16a0006f jal x0, 362 + 20689500 20674 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20690500 20675 1c001d36 e69ff06f jal x0, -408 + 20693500 20678 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20707500 20692 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20708500 20693 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20711500 20696 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20712500 20697 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20713500 20698 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20715500 20700 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20716500 20701 1c001778 fddff06f jal x0, -36 + 20718500 20703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20719500 20704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 20720500 20705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20721500 20706 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 20722500 20707 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 20723500 20708 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 20724500 20709 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 20725500 20710 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 20726500 20711 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20727500 20712 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104118 + 20731500 20716 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20732500 20717 1c001bca 16a0006f jal x0, 362 + 20734500 20719 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20735500 20720 1c001d36 e69ff06f jal x0, -408 + 20738500 20723 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20753500 20738 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20754500 20739 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20757500 20742 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20760500 20745 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108fef60 PA:108fef64 + 20761500 20746 1c001bd0 00012423 sw x0, 8(x2) x2:108fef60 PA:108fef68 + 20762500 20747 1c001bd2 00010623 sb x0, 12(x2) x2:108fef60 PA:108fef6c + 20763500 20748 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20764500 20749 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20765500 20750 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20766500 20751 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fef60 PA:108fef64 + 20767500 20752 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20768500 20753 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20769500 20754 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20770500 20755 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20771500 20756 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20772500 20757 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20773500 20758 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20774500 20759 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20791500 20776 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20792500 20777 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20795500 20780 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20796500 20781 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20797500 20782 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20800500 20785 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20803500 20788 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20806500 20791 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20809500 20794 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20810500 20795 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20811500 20796 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20812500 20797 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20815500 20800 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20816500 20801 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20819500 20804 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20820500 20805 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20823500 20808 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20825500 20810 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20828500 20813 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20829500 20814 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20832500 20817 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20833500 20818 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20834500 20819 1c001f42 e09ff06f jal x0, -504 + 20836500 20821 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20837500 20822 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fef60 PA:108fef70 + 20838500 20823 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20841500 20826 1c001e34 00440c13 addi x24, x8, 4 x24=108fefec x8:108fefe8 + 20842500 20827 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:108fefe8 PA:108fefe8 + 20843500 20828 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20846500 20831 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20849500 20834 1c001e64 00410593 addi x11, x2, 4 x11=108fef64 x2:108fef60 + 20850500 20835 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20852500 20837 1c0019fe 0105a683 lw x13, 16(x11) x13=108fef78 x11:108fef64 PA:108fef74 + 20853500 20838 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fef64 PA:108fef70 + 20854500 20839 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20855500 20840 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20889500 20874 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20890500 20875 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20891500 20876 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20892500 20877 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20895500 20880 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fef64 PA:108fef70 + 20896500 20881 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20930500 20915 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20964500 20949 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20995500 20980 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20996500 20981 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20999500 20984 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21001500 20986 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 21004500 20989 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 21005500 20990 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:108fef78 PA:108fef78 + 21006500 20991 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21007500 20992 1c001a5e 00168693 addi x13, x13, 1 x13=108fef79 x13:108fef78 + 21008500 20993 1c001a60 fb1ff06f jal x0, -80 + 21010500 20995 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21011500 20996 1c001a12 00068023 sb x0, 0(x13) x13:108fef79 PA:108fef79 + 21012500 20997 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21014500 20999 1c001e68 f17ff06f jal x0, -234 + 21016500 21001 1c001d7e 00410613 addi x12, x2, 4 x12=108fef64 x2:108fef60 + 21017500 21002 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21018500 21003 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21019500 21004 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21021500 21006 1c001a62 fe010113 addi x2, x2, -32 x2=108fef40 x2:108fef60 + 21022500 21007 1c001a64 00812c23 sw x8, 24(x2) x8:108fefe8 x2:108fef40 PA:108fef58 + 21023500 21008 1c001a66 01062783 lw x15, 16(x12) x15=108fef78 x12:108fef64 PA:108fef74 + 21024500 21009 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fef64 PA:108fef68 + 21025500 21010 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108fef40 PA:108fef54 + 21026500 21011 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fef40 PA:108fef50 + 21027500 21012 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fef40 PA:108fef4c + 21028500 21013 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fef40 PA:108fef5c + 21029500 21014 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fef40 PA:108fef48 + 21030500 21015 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21031500 21016 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21032500 21017 1c001a78 00c004b3 add x9, x0, x12 x9=108fef64 x12:108fef64 + 21033500 21018 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=108fef79 x15:108fef78 PA:108fef78 + 21035500 21020 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 21036500 21021 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21037500 21022 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fef64 PA:108fef6c + 21039500 21024 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21042500 21027 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 21044500 21029 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21045500 21030 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21048500 21033 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21049500 21034 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21050500 21035 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21053500 21038 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21054500 21039 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21055500 21040 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21056500 21041 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21057500 21042 1c001b36 f71ff06f jal x0, -144 + 21059500 21044 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fef64 PA:108fef6c + 21061500 21046 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21064500 21049 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 21066500 21051 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21067500 21052 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21070500 21055 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 21071500 21056 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21072500 21057 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21073500 21058 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21074500 21059 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fef78 x9:108fef64 PA:108fef74 + 21076500 21061 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=108fef79 x20:108fef78 PA:108fef78 + 21078500 21063 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21082500 21067 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21084500 21069 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21085500 21070 1c001778 fddff06f jal x0, -36 + 21087500 21072 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21088500 21073 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 21089500 21074 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21090500 21075 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 21091500 21076 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 21092500 21077 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 21093500 21078 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 21094500 21079 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 21095500 21080 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21096500 21081 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104118 + 21100500 21085 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21101500 21086 1c001b62 f8bff06f jal x0, -118 + 21103500 21088 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fef7a x20:108fef79 PA:108fef79 + 21105500 21090 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21106500 21091 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fef64 PA:108fef64 + 21108500 21093 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21109500 21094 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21112500 21097 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fef40 PA:108fef5c + 21113500 21098 1c001b02 01812403 lw x8, 24(x2) x8=108fefe8 x2:108fef40 PA:108fef58 + 21114500 21099 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108fef40 PA:108fef54 + 21115500 21100 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fef40 PA:108fef50 + 21116500 21101 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fef40 PA:108fef4c + 21117500 21102 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fef40 PA:108fef48 + 21118500 21103 1c001b0c 02010113 addi x2, x2, 32 x2=108fef60 x2:108fef40 + 21119500 21104 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21121500 21106 1c001d86 01800433 add x8, x0, x24 x8=108fefec x24:108fefec + 21122500 21107 1c001d88 fadff06f jal x0, -84 + 21124500 21109 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21125500 21110 1c001d36 e69ff06f jal x0, -408 + 21128500 21113 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21147500 21132 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21148500 21133 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21151500 21136 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21152500 21137 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21153500 21138 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21155500 21140 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21156500 21141 1c001778 fddff06f jal x0, -36 + 21158500 21143 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21159500 21144 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 21160500 21145 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21161500 21146 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 21162500 21147 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 21163500 21148 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 21164500 21149 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 21165500 21150 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 21166500 21151 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21167500 21152 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104118 + 21171500 21156 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21172500 21157 1c001bca 16a0006f jal x0, 362 + 21174500 21159 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21175500 21160 1c001d36 e69ff06f jal x0, -408 + 21178500 21163 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21193500 21178 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21194500 21179 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21197500 21182 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21198500 21183 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21199500 21184 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21201500 21186 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21202500 21187 1c001778 fddff06f jal x0, -36 + 21204500 21189 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21205500 21190 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 21206500 21191 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21207500 21192 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 21208500 21193 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 21209500 21194 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 21210500 21195 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 21211500 21196 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 21212500 21197 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21213500 21198 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104118 + 21217500 21202 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21218500 21203 1c001bca 16a0006f jal x0, 362 + 21220500 21205 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21221500 21206 1c001d36 e69ff06f jal x0, -408 + 21224500 21209 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21239500 21224 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21240500 21225 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21243500 21228 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21244500 21229 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21245500 21230 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21247500 21232 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21248500 21233 1c001778 fddff06f jal x0, -36 + 21250500 21235 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21251500 21236 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000043 + 21252500 21237 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21253500 21238 1c00175e 00379713 slli x14, x15, 0x3 x14=00000218 x15:00000043 + 21254500 21239 1c001762 00279793 slli x15, x15, 0x2 x15=0000010c x15:00000043 + 21255500 21240 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000218 + 21256500 21241 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000010c x13:00001f80 + 21257500 21242 1c00176a 00e787b3 add x15, x15, x14 x15=00000118 x15:00000100 x14:00000018 + 21258500 21243 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21259500 21244 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104118 + 21263500 21248 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21264500 21249 1c001bca 16a0006f jal x0, 362 + 21266500 21251 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21267500 21252 1c001d36 e69ff06f jal x0, -408 + 21270500 21255 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21285500 21270 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21286500 21271 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21287500 21272 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108fef60 PA:108fefbc + 21288500 21273 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:108fef60 PA:108fefb8 + 21289500 21274 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:108fef60 PA:108fefb4 + 21290500 21275 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:108fef60 PA:108fefb0 + 21302500 21287 1c001bb0 04c12983 lw x19, 76(x2) x19=00000003 x2:108fef60 PA:108fefac + 21304500 21289 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:108fef60 PA:108fefa8 + 21305500 21290 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:108fef60 PA:108fefa4 + 21306500 21291 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:108fef60 PA:108fefa0 + 21307500 21292 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:108fef60 PA:108fef9c + 21308500 21293 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:108fef60 PA:108fef98 + 21309500 21294 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:108fef60 PA:108fef94 + 21310500 21295 1c001bbe 06010113 addi x2, x2, 96 x2=108fefc0 x2:108fef60 + 21311500 21296 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21313500 21298 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:108fefc0 PA:108fefdc + 21314500 21299 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21315500 21300 1c001838 04010113 addi x2, x2, 64 x2=108ff000 x2:108fefc0 + 21316500 21301 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21318500 21303 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_4.log b/sw/scripts/tracevis/example/traces/trace_core_02_4.log new file mode 100644 index 0000000..b4be6f9 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_4.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000044 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000004 x10:00000044 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000044 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000004 + 14871500 14856 1c0000a6 05a0206f jal x0, 8282 + 14889500 14874 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14890500 14875 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14891500 14876 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14892500 14877 1c00210c 0e059163 bne x11, x0, 226 x11:00000004 + 14944500 14929 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 14945500 14930 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000044 + 14946500 14931 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000004 x19:00000044 + 14947500 14932 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 14964500 14949 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 14965500 14950 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 14966500 14951 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 14967500 14952 1c00220a 0060006f jal x0, 6 + 14986500 14971 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18321500 18306 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18338500 18323 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18339500 18324 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18361500 18346 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18362500 18347 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18364500 18349 1c00222c 08096283 p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080 + 18388500 18373 1c002230 02a98533 mul x10, x19, x10 x10=00001000 x19:00000004 x10:00000400 + 18389500 18374 1c002234 00550133 add x2, x10, x5 x2=108ff400 x10:00001000 x5:108fe400 + 18390500 18375 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18392500 18377 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18427500 18412 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18435500 18420 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18436500 18421 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18437500 18422 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18438500 18423 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18459500 18444 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000044 + 18476500 18461 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18477500 18462 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000002 x12:00000044 + 18478500 18463 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002 + 18479500 18464 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000004 x12:00000044 + 18480500 18465 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18481500 18466 1c0009d4 63d0006f jal x0, 3644 + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108ff3c0 x2:108ff400 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108ff3c0 PA:108ff3e4 + 18505500 18490 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18506500 18491 1c001818 02c12423 sw x12, 40(x2) x12:00000004 x2:108ff3c0 PA:108ff3e8 + 18507500 18492 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108ff3c0 PA:108ff3ec + 18508500 18493 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18509500 18494 1c00181e 02410693 addi x13, x2, 36 x13=108ff3e4 x2:108ff3c0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:108ff3c0 PA:108ff3dc + 18529500 18514 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:108ff3c0 PA:108ff3f0 + 18530500 18515 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:108ff3c0 PA:108ff3f4 + 18531500 18516 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108ff3c0 PA:108ff3f8 + 18532500 18517 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108ff3c0 PA:108ff3fc + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108ff3e4 x2:108ff3c0 PA:108ff3cc + 18555500 18540 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108ff360 x2:108ff3c0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108ff378 x2:108ff360 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:108ff360 PA:108ff3b8 + 18573500 18558 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:108ff360 PA:108ff3b0 + 18574500 18559 1c001b78 05312623 sw x19, 76(x2) x19:00000004 x2:108ff360 PA:108ff3ac + 18575500 18560 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:108ff360 PA:108ff3a8 + 18576500 18561 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:108ff360 PA:108ff3a4 + 18577500 18562 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:108ff360 PA:108ff3a0 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:108ff360 PA:108ff39c + 18599500 18584 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108ff360 PA:108ff3bc + 18600500 18585 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:108ff360 PA:108ff3b4 + 18601500 18586 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:108ff360 PA:108ff398 + 18602500 18587 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:108ff360 PA:108ff394 + 18603500 18588 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18604500 18589 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18605500 18590 1c001b8e 00d00433 add x8, x0, x13 x8=108ff3e4 x13:108ff3e4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108ff378 x2:108ff360 PA:108ff374 + 18620500 18605 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18621500 18606 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18622500 18607 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18623500 18608 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18659500 18644 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18660500 18645 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18678500 18663 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18679500 18664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18680500 18665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104120 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18793500 18778 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18794500 18779 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18797500 18782 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18798500 18783 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18799500 18784 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18801500 18786 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18802500 18787 1c001778 fddff06f jal x0, -36 + 18804500 18789 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18805500 18790 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 18806500 18791 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18807500 18792 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 18808500 18793 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 18809500 18794 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 18810500 18795 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 18811500 18796 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 18812500 18797 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18813500 18798 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104120 + 18817500 18802 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18818500 18803 1c001bca 16a0006f jal x0, 362 + 18820500 18805 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18821500 18806 1c001d36 e69ff06f jal x0, -408 + 18824500 18809 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18840500 18825 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18841500 18826 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18844500 18829 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18845500 18830 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18846500 18831 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18848500 18833 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18849500 18834 1c001778 fddff06f jal x0, -36 + 18851500 18836 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18852500 18837 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 18853500 18838 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18854500 18839 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 18855500 18840 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 18856500 18841 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 18857500 18842 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 18858500 18843 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 18859500 18844 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18860500 18845 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104120 + 18864500 18849 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18865500 18850 1c001bca 16a0006f jal x0, 362 + 18867500 18852 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18868500 18853 1c001d36 e69ff06f jal x0, -408 + 18871500 18856 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18890500 18875 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18891500 18876 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18894500 18879 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18895500 18880 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18896500 18881 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18898500 18883 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18899500 18884 1c001778 fddff06f jal x0, -36 + 18901500 18886 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18902500 18887 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 18903500 18888 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18904500 18889 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 18905500 18890 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 18906500 18891 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 18907500 18892 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 18908500 18893 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 18909500 18894 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18910500 18895 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104120 + 18914500 18899 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18915500 18900 1c001bca 16a0006f jal x0, 362 + 18917500 18902 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18918500 18903 1c001d36 e69ff06f jal x0, -408 + 18921500 18906 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18935500 18920 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18936500 18921 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18939500 18924 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18940500 18925 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18941500 18926 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18943500 18928 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18944500 18929 1c001778 fddff06f jal x0, -36 + 18946500 18931 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18947500 18932 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 18948500 18933 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18949500 18934 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 18950500 18935 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 18951500 18936 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 18952500 18937 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 18953500 18938 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 18954500 18939 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18955500 18940 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104120 + 18959500 18944 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18960500 18945 1c001bca 16a0006f jal x0, 362 + 18962500 18947 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18963500 18948 1c001d36 e69ff06f jal x0, -408 + 18966500 18951 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18985500 18970 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18986500 18971 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18989500 18974 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18990500 18975 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18991500 18976 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18993500 18978 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18994500 18979 1c001778 fddff06f jal x0, -36 + 18996500 18981 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18997500 18982 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 18998500 18983 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18999500 18984 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19000500 18985 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19001500 18986 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19002500 18987 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19003500 18988 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19004500 18989 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19005500 18990 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104120 + 19009500 18994 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19010500 18995 1c001bca 16a0006f jal x0, 362 + 19012500 18997 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19013500 18998 1c001d36 e69ff06f jal x0, -408 + 19016500 19001 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19032500 19017 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19033500 19018 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19036500 19021 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19037500 19022 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19038500 19023 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19040500 19025 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19041500 19026 1c001778 fddff06f jal x0, -36 + 19043500 19028 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19044500 19029 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19045500 19030 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19046500 19031 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19047500 19032 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19048500 19033 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19049500 19034 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19050500 19035 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19051500 19036 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19052500 19037 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104120 + 19056500 19041 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19057500 19042 1c001bca 16a0006f jal x0, 362 + 19059500 19044 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19060500 19045 1c001d36 e69ff06f jal x0, -408 + 19063500 19048 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19078500 19063 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19079500 19064 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19082500 19067 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19083500 19068 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19084500 19069 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19086500 19071 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19087500 19072 1c001778 fddff06f jal x0, -36 + 19089500 19074 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19090500 19075 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19091500 19076 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19092500 19077 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19093500 19078 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19094500 19079 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19095500 19080 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19096500 19081 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19097500 19082 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19098500 19083 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104120 + 19102500 19087 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19103500 19088 1c001bca 16a0006f jal x0, 362 + 19105500 19090 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19106500 19091 1c001d36 e69ff06f jal x0, -408 + 19109500 19094 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19127500 19112 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19128500 19113 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19131500 19116 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19132500 19117 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19133500 19118 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19135500 19120 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19136500 19121 1c001778 fddff06f jal x0, -36 + 19138500 19123 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19139500 19124 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19140500 19125 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19141500 19126 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19142500 19127 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19143500 19128 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19144500 19129 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19145500 19130 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19146500 19131 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19147500 19132 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104120 + 19151500 19136 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19152500 19137 1c001bca 16a0006f jal x0, 362 + 19154500 19139 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19155500 19140 1c001d36 e69ff06f jal x0, -408 + 19158500 19143 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19179500 19164 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19180500 19165 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19183500 19168 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19184500 19169 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19185500 19170 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19187500 19172 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19188500 19173 1c001778 fddff06f jal x0, -36 + 19190500 19175 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19191500 19176 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19192500 19177 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19193500 19178 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19194500 19179 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19195500 19180 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19196500 19181 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19197500 19182 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19198500 19183 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19199500 19184 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104120 + 19203500 19188 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19204500 19189 1c001bca 16a0006f jal x0, 362 + 19206500 19191 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19207500 19192 1c001d36 e69ff06f jal x0, -408 + 19210500 19195 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19230500 19215 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19231500 19216 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19234500 19219 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19235500 19220 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19236500 19221 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19238500 19223 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19239500 19224 1c001778 fddff06f jal x0, -36 + 19241500 19226 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19242500 19227 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19243500 19228 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19244500 19229 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19245500 19230 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19246500 19231 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19247500 19232 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19248500 19233 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19249500 19234 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19250500 19235 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104120 + 19254500 19239 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19255500 19240 1c001bca 16a0006f jal x0, 362 + 19257500 19242 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19258500 19243 1c001d36 e69ff06f jal x0, -408 + 19261500 19246 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19278500 19263 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19279500 19264 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19282500 19267 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19283500 19268 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19284500 19269 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19286500 19271 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19287500 19272 1c001778 fddff06f jal x0, -36 + 19289500 19274 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19290500 19275 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19291500 19276 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19292500 19277 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19293500 19278 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19294500 19279 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19295500 19280 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19296500 19281 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19297500 19282 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19298500 19283 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104120 + 19302500 19287 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19303500 19288 1c001bca 16a0006f jal x0, 362 + 19305500 19290 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19306500 19291 1c001d36 e69ff06f jal x0, -408 + 19309500 19294 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19323500 19308 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19324500 19309 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19327500 19312 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19328500 19313 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19329500 19314 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19331500 19316 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19332500 19317 1c001778 fddff06f jal x0, -36 + 19334500 19319 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19335500 19320 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19336500 19321 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19337500 19322 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19338500 19323 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19339500 19324 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19340500 19325 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19341500 19326 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19342500 19327 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19343500 19328 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104120 + 19347500 19332 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19348500 19333 1c001bca 16a0006f jal x0, 362 + 19350500 19335 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19351500 19336 1c001d36 e69ff06f jal x0, -408 + 19354500 19339 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19375500 19360 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19376500 19361 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19379500 19364 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19380500 19365 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19381500 19366 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19383500 19368 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19384500 19369 1c001778 fddff06f jal x0, -36 + 19386500 19371 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19387500 19372 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19388500 19373 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19389500 19374 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19390500 19375 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19391500 19376 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19392500 19377 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19393500 19378 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19394500 19379 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19395500 19380 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104120 + 19399500 19384 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19400500 19385 1c001bca 16a0006f jal x0, 362 + 19402500 19387 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19403500 19388 1c001d36 e69ff06f jal x0, -408 + 19406500 19391 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19426500 19411 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19427500 19412 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19430500 19415 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19431500 19416 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19432500 19417 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19434500 19419 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19435500 19420 1c001778 fddff06f jal x0, -36 + 19437500 19422 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19438500 19423 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 19439500 19424 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19440500 19425 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 19441500 19426 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 19442500 19427 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 19443500 19428 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 19444500 19429 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 19445500 19430 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19446500 19431 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104120 + 19450500 19435 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19451500 19436 1c001bca 16a0006f jal x0, 362 + 19453500 19438 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19454500 19439 1c001d36 e69ff06f jal x0, -408 + 19457500 19442 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19476500 19461 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19477500 19462 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19480500 19465 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19483500 19468 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108ff360 PA:108ff364 + 19488500 19473 1c001bd0 00012423 sw x0, 8(x2) x2:108ff360 PA:108ff368 + 19491500 19476 1c001bd2 00010623 sb x0, 12(x2) x2:108ff360 PA:108ff36c + 19492500 19477 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19493500 19478 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19513500 19498 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19514500 19499 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108ff360 PA:108ff364 + 19520500 19505 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19521500 19506 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19522500 19507 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19523500 19508 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19524500 19509 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19581500 19566 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19582500 19567 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19606500 19591 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19607500 19592 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19608500 19593 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108ff360 PA:108ff370 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108ff3e8 x8:108ff3e4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108ff3e4 PA:108ff3e4 + 19949500 19934 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108ff364 x2:108ff360 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108ff378 x11:108ff364 PA:108ff374 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff364 PA:108ff370 + 20045500 20030 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20046500 20031 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20080500 20065 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20081500 20066 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20082500 20067 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20083500 20068 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20086500 20071 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff364 PA:108ff370 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108ff378 PA:108ff378 + 20249500 20234 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20250500 20235 1c001a5e 00168693 addi x13, x13, 1 x13=108ff379 x13:108ff378 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108ff379 PA:108ff379 + 20269500 20254 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20270500 20255 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108ff364 x2:108ff360 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108ff340 x2:108ff360 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108ff3e4 x2:108ff340 PA:108ff358 + 20321500 20306 1c001a66 01062783 lw x15, 16(x12) x15=108ff378 x12:108ff364 PA:108ff374 + 20322500 20307 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108ff364 PA:108ff368 + 20323500 20308 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108ff340 PA:108ff354 + 20324500 20309 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108ff340 PA:108ff350 + 20325500 20310 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108ff340 PA:108ff34c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108ff340 PA:108ff35c + 20342500 20327 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108ff340 PA:108ff348 + 20343500 20328 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20344500 20329 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20345500 20330 1c001a78 00c004b3 add x9, x0, x12 x9=108ff364 x12:108ff364 + 20346500 20331 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108ff379 x15:108ff378 PA:108ff378 + 20348500 20333 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108ff364 PA:108ff36c + 20364500 20349 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20367500 20352 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108ff364 PA:108ff36c + 20452500 20437 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 20472500 20457 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20473500 20458 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108ff378 x9:108ff364 PA:108ff374 + 20514500 20499 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108ff379 x20:108ff378 PA:108ff378 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104120 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108ff37a x20:108ff379 PA:108ff379 + 20589500 20574 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20590500 20575 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 20592500 20577 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20593500 20578 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108ff340 PA:108ff35c + 20614500 20599 1c001b02 01812403 lw x8, 24(x2) x8=108ff3e4 x2:108ff340 PA:108ff358 + 20615500 20600 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108ff340 PA:108ff354 + 20616500 20601 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108ff340 PA:108ff350 + 20617500 20602 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108ff340 PA:108ff34c + 20618500 20603 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108ff340 PA:108ff348 + 20619500 20604 1c001b0c 02010113 addi x2, x2, 32 x2=108ff360 x2:108ff340 + 20620500 20605 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108ff3e8 x24:108ff3e8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20664500 20649 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20665500 20650 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20668500 20653 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20669500 20654 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20670500 20655 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20672500 20657 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20673500 20658 1c001778 fddff06f jal x0, -36 + 20675500 20660 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20676500 20661 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 20677500 20662 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20678500 20663 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 20679500 20664 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 20680500 20665 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 20681500 20666 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 20682500 20667 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 20683500 20668 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20684500 20669 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104120 + 20688500 20673 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20689500 20674 1c001bca 16a0006f jal x0, 362 + 20691500 20676 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20692500 20677 1c001d36 e69ff06f jal x0, -408 + 20695500 20680 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20709500 20694 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20710500 20695 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20713500 20698 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20714500 20699 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20715500 20700 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20717500 20702 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20718500 20703 1c001778 fddff06f jal x0, -36 + 20720500 20705 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20721500 20706 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 20722500 20707 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20723500 20708 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 20724500 20709 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 20725500 20710 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 20726500 20711 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 20727500 20712 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 20728500 20713 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20729500 20714 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104120 + 20733500 20718 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20734500 20719 1c001bca 16a0006f jal x0, 362 + 20736500 20721 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20737500 20722 1c001d36 e69ff06f jal x0, -408 + 20740500 20725 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20757500 20742 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20758500 20743 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20761500 20746 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20764500 20749 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108ff360 PA:108ff364 + 20765500 20750 1c001bd0 00012423 sw x0, 8(x2) x2:108ff360 PA:108ff368 + 20766500 20751 1c001bd2 00010623 sb x0, 12(x2) x2:108ff360 PA:108ff36c + 20767500 20752 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20768500 20753 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20769500 20754 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20770500 20755 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108ff360 PA:108ff364 + 20771500 20756 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20772500 20757 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20773500 20758 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20774500 20759 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20775500 20760 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20776500 20761 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20777500 20762 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20778500 20763 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20795500 20780 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20796500 20781 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20799500 20784 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20800500 20785 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20801500 20786 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20804500 20789 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20807500 20792 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20810500 20795 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20813500 20798 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20814500 20799 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20815500 20800 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20816500 20801 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20819500 20804 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20820500 20805 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20823500 20808 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20824500 20809 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20827500 20812 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20829500 20814 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20832500 20817 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20833500 20818 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20836500 20821 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20837500 20822 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20838500 20823 1c001f42 e09ff06f jal x0, -504 + 20840500 20825 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20841500 20826 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108ff360 PA:108ff370 + 20842500 20827 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20845500 20830 1c001e34 00440c13 addi x24, x8, 4 x24=108ff3ec x8:108ff3e8 + 20846500 20831 1c001e38 00042503 lw x10, 0(x8) x10=00000004 x8:108ff3e8 PA:108ff3e8 + 20847500 20832 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20850500 20835 1c001e54 00055863 bge x10, x0, 16 x10:00000004 + 20853500 20838 1c001e64 00410593 addi x11, x2, 4 x11=108ff364 x2:108ff360 + 20854500 20839 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20856500 20841 1c0019fe 0105a683 lw x13, 16(x11) x13=108ff378 x11:108ff364 PA:108ff374 + 20857500 20842 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff364 PA:108ff370 + 20858500 20843 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20859500 20844 1c001a04 02f55633 divu x12, x10, x15 x12=00000004 x10:00000004 x15:00000001 + 20893500 20878 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000004 x14:0000000a + 20894500 20879 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20895500 20880 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20896500 20881 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20899500 20884 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff364 PA:108ff370 + 20900500 20885 1c001a20 02f55833 divu x16, x10, x15 x16=00000004 x10:00000004 x15:00000001 + 20934500 20919 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000004 x15:00000001 + 20968500 20953 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20999500 20984 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21000500 20985 1c001a2e 01004663 blt x0, x16, 12 x16:00000004 + 21003500 20988 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21005500 20990 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000004 + 21008500 20993 1c001a56 01070733 add x14, x14, x16 x14=00000034 x14:00000030 x16:00000004 + 21009500 20994 1c001a58 00e68023 sb x14, 0(x13) x14:00000034 x13:108ff378 PA:108ff378 + 21011500 20996 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21012500 20997 1c001a5e 00168693 addi x13, x13, 1 x13=108ff379 x13:108ff378 + 21013500 20998 1c001a60 fb1ff06f jal x0, -80 + 21015500 21000 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21016500 21001 1c001a12 00068023 sb x0, 0(x13) x13:108ff379 PA:108ff379 + 21017500 21002 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21019500 21004 1c001e68 f17ff06f jal x0, -234 + 21021500 21006 1c001d7e 00410613 addi x12, x2, 4 x12=108ff364 x2:108ff360 + 21022500 21007 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21023500 21008 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21024500 21009 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21026500 21011 1c001a62 fe010113 addi x2, x2, -32 x2=108ff340 x2:108ff360 + 21027500 21012 1c001a64 00812c23 sw x8, 24(x2) x8:108ff3e8 x2:108ff340 PA:108ff358 + 21028500 21013 1c001a66 01062783 lw x15, 16(x12) x15=108ff378 x12:108ff364 PA:108ff374 + 21029500 21014 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108ff364 PA:108ff368 + 21030500 21015 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108ff340 PA:108ff354 + 21031500 21016 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108ff340 PA:108ff350 + 21032500 21017 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108ff340 PA:108ff34c + 21033500 21018 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108ff340 PA:108ff35c + 21034500 21019 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108ff340 PA:108ff348 + 21035500 21020 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21036500 21021 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21037500 21022 1c001a78 00c004b3 add x9, x0, x12 x9=108ff364 x12:108ff364 + 21038500 21023 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000034 x15=108ff379 x15:108ff378 PA:108ff378 + 21040500 21025 1c001a7e 00070363 beq x14, x0, 6 x14:00000034 + 21041500 21026 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21042500 21027 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108ff364 PA:108ff36c + 21044500 21029 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21047500 21032 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 21049500 21034 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21050500 21035 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21053500 21038 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21054500 21039 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21055500 21040 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21058500 21043 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21059500 21044 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21060500 21045 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21061500 21046 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21062500 21047 1c001b36 f71ff06f jal x0, -144 + 21064500 21049 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108ff364 PA:108ff36c + 21066500 21051 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21069500 21054 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 21071500 21056 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21072500 21057 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21075500 21060 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 21076500 21061 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21077500 21062 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21078500 21063 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21079500 21064 1c001ae8 0104aa03 lw x20, 16(x9) x20=108ff378 x9:108ff364 PA:108ff374 + 21081500 21066 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000034 x20=108ff379 x20:108ff378 PA:108ff378 + 21083500 21068 1c001af0 06059763 bne x11, x0, 110 x11:00000034 + 21086500 21071 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21087500 21072 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21089500 21074 1c001776 00b00533 add x10, x0, x11 x10=00000034 x11:00000034 + 21090500 21075 1c001778 fddff06f jal x0, -36 + 21092500 21077 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21093500 21078 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 21094500 21079 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21095500 21080 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 21096500 21081 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 21097500 21082 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 21098500 21083 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 21099500 21084 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 21100500 21085 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21101500 21086 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000034 x14:1a104000 PA:1a104120 + 21105500 21090 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21106500 21091 1c001b62 f8bff06f jal x0, -118 + 21108500 21093 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108ff37a x20:108ff379 PA:108ff379 + 21110500 21095 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21111500 21096 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff364 PA:108ff364 + 21113500 21098 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21114500 21099 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21117500 21102 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108ff340 PA:108ff35c + 21118500 21103 1c001b02 01812403 lw x8, 24(x2) x8=108ff3e8 x2:108ff340 PA:108ff358 + 21119500 21104 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108ff340 PA:108ff354 + 21120500 21105 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108ff340 PA:108ff350 + 21121500 21106 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108ff340 PA:108ff34c + 21122500 21107 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108ff340 PA:108ff348 + 21123500 21108 1c001b0c 02010113 addi x2, x2, 32 x2=108ff360 x2:108ff340 + 21124500 21109 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21126500 21111 1c001d86 01800433 add x8, x0, x24 x8=108ff3ec x24:108ff3ec + 21127500 21112 1c001d88 fadff06f jal x0, -84 + 21129500 21114 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21130500 21115 1c001d36 e69ff06f jal x0, -408 + 21133500 21118 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21158500 21143 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21159500 21144 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21162500 21147 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21163500 21148 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21164500 21149 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21166500 21151 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21167500 21152 1c001778 fddff06f jal x0, -36 + 21169500 21154 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21170500 21155 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 21171500 21156 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21172500 21157 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 21173500 21158 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 21174500 21159 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 21175500 21160 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 21176500 21161 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 21177500 21162 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21178500 21163 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104120 + 21182500 21167 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21183500 21168 1c001bca 16a0006f jal x0, 362 + 21185500 21170 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21186500 21171 1c001d36 e69ff06f jal x0, -408 + 21189500 21174 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21209500 21194 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21210500 21195 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21213500 21198 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21214500 21199 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21215500 21200 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21217500 21202 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21218500 21203 1c001778 fddff06f jal x0, -36 + 21220500 21205 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21221500 21206 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 21222500 21207 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21223500 21208 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 21224500 21209 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 21225500 21210 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 21226500 21211 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 21227500 21212 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 21228500 21213 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21229500 21214 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104120 + 21233500 21218 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21234500 21219 1c001bca 16a0006f jal x0, 362 + 21236500 21221 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21237500 21222 1c001d36 e69ff06f jal x0, -408 + 21240500 21225 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21254500 21239 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21255500 21240 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21258500 21243 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21259500 21244 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21260500 21245 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21262500 21247 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21263500 21248 1c001778 fddff06f jal x0, -36 + 21265500 21250 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21266500 21251 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000044 + 21267500 21252 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21268500 21253 1c00175e 00379713 slli x14, x15, 0x3 x14=00000220 x15:00000044 + 21269500 21254 1c001762 00279793 slli x15, x15, 0x2 x15=00000110 x15:00000044 + 21270500 21255 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000220 + 21271500 21256 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000110 x13:00001f80 + 21272500 21257 1c00176a 00e787b3 add x15, x15, x14 x15=00000120 x15:00000100 x14:00000020 + 21273500 21258 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21274500 21259 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104120 + 21278500 21263 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21279500 21264 1c001bca 16a0006f jal x0, 362 + 21281500 21266 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21282500 21267 1c001d36 e69ff06f jal x0, -408 + 21285500 21270 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21303500 21288 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21304500 21289 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21305500 21290 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108ff360 PA:108ff3bc + 21306500 21291 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:108ff360 PA:108ff3b8 + 21307500 21292 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:108ff360 PA:108ff3b4 + 21308500 21293 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:108ff360 PA:108ff3b0 + 21309500 21294 1c001bb0 04c12983 lw x19, 76(x2) x19=00000004 x2:108ff360 PA:108ff3ac + 21310500 21295 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:108ff360 PA:108ff3a8 + 21311500 21296 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:108ff360 PA:108ff3a4 + 21312500 21297 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:108ff360 PA:108ff3a0 + 21313500 21298 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:108ff360 PA:108ff39c + 21317500 21302 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:108ff360 PA:108ff398 + 21318500 21303 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:108ff360 PA:108ff394 + 21319500 21304 1c001bbe 06010113 addi x2, x2, 96 x2=108ff3c0 x2:108ff360 + 21320500 21305 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21322500 21307 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:108ff3c0 PA:108ff3dc + 21323500 21308 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21324500 21309 1c001838 04010113 addi x2, x2, 64 x2=108ff400 x2:108ff3c0 + 21325500 21310 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21327500 21312 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_5.log b/sw/scripts/tracevis/example/traces/trace_core_02_5.log new file mode 100644 index 0000000..4509040 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_5.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000045 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000005 x10:00000045 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000045 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000005 + 14871500 14856 1c0000a6 05a0206f jal x0, 8282 + 14889500 14874 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14890500 14875 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14891500 14876 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14892500 14877 1c00210c 0e059163 bne x11, x0, 226 x11:00000005 + 14944500 14929 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 14945500 14930 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000045 + 14946500 14931 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000005 x19:00000045 + 14947500 14932 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 14964500 14949 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 14965500 14950 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 14966500 14951 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 14967500 14952 1c00220a 0060006f jal x0, 6 + 14986500 14971 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18321500 18306 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18338500 18323 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18339500 18324 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18361500 18346 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18362500 18347 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18364500 18349 1c00222c 08096283 p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080 + 18388500 18373 1c002230 02a98533 mul x10, x19, x10 x10=00001400 x19:00000005 x10:00000400 + 18389500 18374 1c002234 00550133 add x2, x10, x5 x2=108ff800 x10:00001400 x5:108fe400 + 18390500 18375 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18392500 18377 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18427500 18412 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18435500 18420 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18436500 18421 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18437500 18422 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18438500 18423 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18459500 18444 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000045 + 18476500 18461 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18477500 18462 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000002 x12:00000045 + 18478500 18463 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002 + 18479500 18464 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000005 x12:00000045 + 18480500 18465 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18481500 18466 1c0009d4 63d0006f jal x0, 3644 + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108ff7c0 x2:108ff800 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108ff7c0 PA:108ff7e4 + 18506500 18491 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18507500 18492 1c001818 02c12423 sw x12, 40(x2) x12:00000005 x2:108ff7c0 PA:108ff7e8 + 18508500 18493 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108ff7c0 PA:108ff7ec + 18509500 18494 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18510500 18495 1c00181e 02410693 addi x13, x2, 36 x13=108ff7e4 x2:108ff7c0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:108ff7c0 PA:108ff7dc + 18530500 18515 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:108ff7c0 PA:108ff7f0 + 18531500 18516 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:108ff7c0 PA:108ff7f4 + 18532500 18517 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108ff7c0 PA:108ff7f8 + 18533500 18518 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108ff7c0 PA:108ff7fc + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108ff7e4 x2:108ff7c0 PA:108ff7cc + 18550500 18535 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108ff760 x2:108ff7c0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108ff778 x2:108ff760 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:108ff760 PA:108ff7b8 + 18574500 18559 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:108ff760 PA:108ff7b0 + 18575500 18560 1c001b78 05312623 sw x19, 76(x2) x19:00000005 x2:108ff760 PA:108ff7ac + 18576500 18561 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:108ff760 PA:108ff7a8 + 18577500 18562 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:108ff760 PA:108ff7a4 + 18578500 18563 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:108ff760 PA:108ff7a0 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:108ff760 PA:108ff79c + 18598500 18583 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108ff760 PA:108ff7bc + 18599500 18584 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:108ff760 PA:108ff7b4 + 18600500 18585 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:108ff760 PA:108ff798 + 18601500 18586 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:108ff760 PA:108ff794 + 18602500 18587 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18603500 18588 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18604500 18589 1c001b8e 00d00433 add x8, x0, x13 x8=108ff7e4 x13:108ff7e4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108ff778 x2:108ff760 PA:108ff774 + 18621500 18606 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18622500 18607 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18623500 18608 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18624500 18609 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18661500 18646 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18662500 18647 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18678500 18663 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18679500 18664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18680500 18665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104128 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18797500 18782 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18798500 18783 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18801500 18786 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18802500 18787 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18803500 18788 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18805500 18790 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18806500 18791 1c001778 fddff06f jal x0, -36 + 18808500 18793 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18809500 18794 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 18810500 18795 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18811500 18796 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 18812500 18797 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 18813500 18798 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 18814500 18799 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 18815500 18800 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 18816500 18801 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18817500 18802 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104128 + 18821500 18806 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18822500 18807 1c001bca 16a0006f jal x0, 362 + 18824500 18809 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18825500 18810 1c001d36 e69ff06f jal x0, -408 + 18828500 18813 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18842500 18827 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18843500 18828 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18846500 18831 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18847500 18832 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18848500 18833 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18850500 18835 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18851500 18836 1c001778 fddff06f jal x0, -36 + 18853500 18838 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18854500 18839 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 18855500 18840 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18856500 18841 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 18857500 18842 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 18858500 18843 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 18859500 18844 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 18860500 18845 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 18861500 18846 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18862500 18847 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104128 + 18866500 18851 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18867500 18852 1c001bca 16a0006f jal x0, 362 + 18869500 18854 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18870500 18855 1c001d36 e69ff06f jal x0, -408 + 18873500 18858 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18893500 18878 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18894500 18879 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18897500 18882 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18898500 18883 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18899500 18884 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18901500 18886 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18902500 18887 1c001778 fddff06f jal x0, -36 + 18904500 18889 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18905500 18890 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 18906500 18891 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18907500 18892 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 18908500 18893 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 18909500 18894 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 18910500 18895 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 18911500 18896 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 18912500 18897 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18913500 18898 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104128 + 18917500 18902 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18918500 18903 1c001bca 16a0006f jal x0, 362 + 18920500 18905 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18921500 18906 1c001d36 e69ff06f jal x0, -408 + 18924500 18909 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18939500 18924 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18940500 18925 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18943500 18928 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18944500 18929 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18945500 18930 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18947500 18932 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18948500 18933 1c001778 fddff06f jal x0, -36 + 18950500 18935 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18951500 18936 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 18952500 18937 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18953500 18938 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 18954500 18939 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 18955500 18940 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 18956500 18941 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 18957500 18942 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 18958500 18943 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18959500 18944 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104128 + 18963500 18948 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18964500 18949 1c001bca 16a0006f jal x0, 362 + 18966500 18951 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18967500 18952 1c001d36 e69ff06f jal x0, -408 + 18970500 18955 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18987500 18972 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18988500 18973 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18991500 18976 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18992500 18977 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18993500 18978 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18995500 18980 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18996500 18981 1c001778 fddff06f jal x0, -36 + 18998500 18983 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18999500 18984 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19000500 18985 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19001500 18986 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19002500 18987 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19003500 18988 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19004500 18989 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19005500 18990 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19006500 18991 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19007500 18992 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104128 + 19011500 18996 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19012500 18997 1c001bca 16a0006f jal x0, 362 + 19014500 18999 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19015500 19000 1c001d36 e69ff06f jal x0, -408 + 19018500 19003 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19035500 19020 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19036500 19021 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19039500 19024 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19040500 19025 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19041500 19026 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19043500 19028 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19044500 19029 1c001778 fddff06f jal x0, -36 + 19046500 19031 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19047500 19032 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19048500 19033 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19049500 19034 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19050500 19035 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19051500 19036 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19052500 19037 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19053500 19038 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19054500 19039 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19055500 19040 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104128 + 19059500 19044 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19060500 19045 1c001bca 16a0006f jal x0, 362 + 19062500 19047 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19063500 19048 1c001d36 e69ff06f jal x0, -408 + 19066500 19051 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19081500 19066 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19082500 19067 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19085500 19070 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19086500 19071 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19087500 19072 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19089500 19074 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19090500 19075 1c001778 fddff06f jal x0, -36 + 19092500 19077 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19093500 19078 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19094500 19079 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19095500 19080 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19096500 19081 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19097500 19082 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19098500 19083 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19099500 19084 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19100500 19085 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19101500 19086 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104128 + 19105500 19090 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19106500 19091 1c001bca 16a0006f jal x0, 362 + 19108500 19093 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19109500 19094 1c001d36 e69ff06f jal x0, -408 + 19112500 19097 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19129500 19114 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19130500 19115 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19133500 19118 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19134500 19119 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19135500 19120 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19137500 19122 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19138500 19123 1c001778 fddff06f jal x0, -36 + 19140500 19125 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19141500 19126 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19142500 19127 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19143500 19128 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19144500 19129 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19145500 19130 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19146500 19131 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19147500 19132 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19148500 19133 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19149500 19134 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104128 + 19153500 19138 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19154500 19139 1c001bca 16a0006f jal x0, 362 + 19156500 19141 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19157500 19142 1c001d36 e69ff06f jal x0, -408 + 19160500 19145 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19181500 19166 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19182500 19167 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19185500 19170 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19186500 19171 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19187500 19172 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19189500 19174 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19190500 19175 1c001778 fddff06f jal x0, -36 + 19192500 19177 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19193500 19178 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19194500 19179 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19195500 19180 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19196500 19181 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19197500 19182 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19198500 19183 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19199500 19184 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19200500 19185 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19201500 19186 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104128 + 19205500 19190 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19206500 19191 1c001bca 16a0006f jal x0, 362 + 19208500 19193 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19209500 19194 1c001d36 e69ff06f jal x0, -408 + 19212500 19197 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19231500 19216 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19232500 19217 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19235500 19220 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19236500 19221 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19237500 19222 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19239500 19224 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19240500 19225 1c001778 fddff06f jal x0, -36 + 19242500 19227 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19243500 19228 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19244500 19229 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19245500 19230 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19246500 19231 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19247500 19232 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19248500 19233 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19249500 19234 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19250500 19235 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19251500 19236 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104128 + 19255500 19240 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19256500 19241 1c001bca 16a0006f jal x0, 362 + 19258500 19243 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19259500 19244 1c001d36 e69ff06f jal x0, -408 + 19262500 19247 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19282500 19267 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19283500 19268 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19286500 19271 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19287500 19272 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19288500 19273 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19290500 19275 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19291500 19276 1c001778 fddff06f jal x0, -36 + 19293500 19278 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19294500 19279 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19295500 19280 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19296500 19281 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19297500 19282 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19298500 19283 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19299500 19284 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19300500 19285 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19301500 19286 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19302500 19287 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104128 + 19306500 19291 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19307500 19292 1c001bca 16a0006f jal x0, 362 + 19309500 19294 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19310500 19295 1c001d36 e69ff06f jal x0, -408 + 19313500 19298 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19330500 19315 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19331500 19316 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19334500 19319 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19335500 19320 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19336500 19321 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19338500 19323 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19339500 19324 1c001778 fddff06f jal x0, -36 + 19341500 19326 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19342500 19327 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19343500 19328 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19344500 19329 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19345500 19330 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19346500 19331 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19347500 19332 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19348500 19333 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19349500 19334 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19350500 19335 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104128 + 19354500 19339 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19355500 19340 1c001bca 16a0006f jal x0, 362 + 19357500 19342 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19358500 19343 1c001d36 e69ff06f jal x0, -408 + 19361500 19346 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19380500 19365 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19381500 19366 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19384500 19369 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19385500 19370 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19386500 19371 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19388500 19373 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19389500 19374 1c001778 fddff06f jal x0, -36 + 19391500 19376 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19392500 19377 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19393500 19378 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19394500 19379 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19395500 19380 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19396500 19381 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19397500 19382 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19398500 19383 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19399500 19384 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19400500 19385 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104128 + 19404500 19389 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19405500 19390 1c001bca 16a0006f jal x0, 362 + 19407500 19392 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19408500 19393 1c001d36 e69ff06f jal x0, -408 + 19411500 19396 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19430500 19415 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19431500 19416 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19434500 19419 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19435500 19420 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19436500 19421 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19438500 19423 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19439500 19424 1c001778 fddff06f jal x0, -36 + 19441500 19426 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19442500 19427 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 19443500 19428 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19444500 19429 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 19445500 19430 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 19446500 19431 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 19447500 19432 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 19448500 19433 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 19449500 19434 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19450500 19435 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104128 + 19454500 19439 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19455500 19440 1c001bca 16a0006f jal x0, 362 + 19457500 19442 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19458500 19443 1c001d36 e69ff06f jal x0, -408 + 19461500 19446 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19480500 19465 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19481500 19466 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19484500 19469 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19487500 19472 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108ff760 PA:108ff764 + 19488500 19473 1c001bd0 00012423 sw x0, 8(x2) x2:108ff760 PA:108ff768 + 19492500 19477 1c001bd2 00010623 sb x0, 12(x2) x2:108ff760 PA:108ff76c + 19493500 19478 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19494500 19479 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19513500 19498 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19514500 19499 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108ff760 PA:108ff764 + 19521500 19506 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19522500 19507 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19523500 19508 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19524500 19509 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19525500 19510 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19563500 19548 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19564500 19549 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19586500 19571 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19587500 19572 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19588500 19573 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108ff760 PA:108ff770 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108ff7e8 x8:108ff7e4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108ff7e4 PA:108ff7e4 + 19950500 19935 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108ff764 x2:108ff760 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108ff778 x11:108ff764 PA:108ff774 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff764 PA:108ff770 + 20046500 20031 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20047500 20032 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20081500 20066 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20082500 20067 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20083500 20068 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20084500 20069 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20087500 20072 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff764 PA:108ff770 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108ff778 PA:108ff778 + 20250500 20235 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20251500 20236 1c001a5e 00168693 addi x13, x13, 1 x13=108ff779 x13:108ff778 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108ff779 PA:108ff779 + 20270500 20255 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20271500 20256 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108ff764 x2:108ff760 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108ff740 x2:108ff760 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108ff7e4 x2:108ff740 PA:108ff758 + 20322500 20307 1c001a66 01062783 lw x15, 16(x12) x15=108ff778 x12:108ff764 PA:108ff774 + 20323500 20308 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108ff764 PA:108ff768 + 20324500 20309 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108ff740 PA:108ff754 + 20325500 20310 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108ff740 PA:108ff750 + 20326500 20311 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108ff740 PA:108ff74c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108ff740 PA:108ff75c + 20343500 20328 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108ff740 PA:108ff748 + 20344500 20329 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20345500 20330 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20346500 20331 1c001a78 00c004b3 add x9, x0, x12 x9=108ff764 x12:108ff764 + 20347500 20332 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108ff779 x15:108ff778 PA:108ff778 + 20349500 20334 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108ff764 PA:108ff76c + 20365500 20350 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20368500 20353 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108ff764 PA:108ff76c + 20453500 20438 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 20473500 20458 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20474500 20459 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108ff778 x9:108ff764 PA:108ff774 + 20515500 20500 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108ff779 x20:108ff778 PA:108ff778 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104128 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108ff77a x20:108ff779 PA:108ff779 + 20590500 20575 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20591500 20576 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 20593500 20578 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20594500 20579 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108ff740 PA:108ff75c + 20615500 20600 1c001b02 01812403 lw x8, 24(x2) x8=108ff7e4 x2:108ff740 PA:108ff758 + 20616500 20601 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108ff740 PA:108ff754 + 20617500 20602 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108ff740 PA:108ff750 + 20618500 20603 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108ff740 PA:108ff74c + 20619500 20604 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108ff740 PA:108ff748 + 20620500 20605 1c001b0c 02010113 addi x2, x2, 32 x2=108ff760 x2:108ff740 + 20621500 20606 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108ff7e8 x24:108ff7e8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20668500 20653 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20669500 20654 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20672500 20657 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20673500 20658 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20674500 20659 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20676500 20661 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20677500 20662 1c001778 fddff06f jal x0, -36 + 20679500 20664 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20680500 20665 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 20681500 20666 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20682500 20667 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 20683500 20668 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 20684500 20669 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 20685500 20670 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 20686500 20671 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 20687500 20672 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20688500 20673 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104128 + 20692500 20677 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20693500 20678 1c001bca 16a0006f jal x0, 362 + 20695500 20680 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20696500 20681 1c001d36 e69ff06f jal x0, -408 + 20699500 20684 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20713500 20698 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20714500 20699 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20717500 20702 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20718500 20703 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20719500 20704 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20721500 20706 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20722500 20707 1c001778 fddff06f jal x0, -36 + 20724500 20709 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20725500 20710 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 20726500 20711 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20727500 20712 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 20728500 20713 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 20729500 20714 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 20730500 20715 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 20731500 20716 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 20732500 20717 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20733500 20718 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104128 + 20737500 20722 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20738500 20723 1c001bca 16a0006f jal x0, 362 + 20740500 20725 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20741500 20726 1c001d36 e69ff06f jal x0, -408 + 20744500 20729 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20762500 20747 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20763500 20748 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20766500 20751 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20769500 20754 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108ff760 PA:108ff764 + 20770500 20755 1c001bd0 00012423 sw x0, 8(x2) x2:108ff760 PA:108ff768 + 20771500 20756 1c001bd2 00010623 sb x0, 12(x2) x2:108ff760 PA:108ff76c + 20772500 20757 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20773500 20758 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20774500 20759 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20775500 20760 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108ff760 PA:108ff764 + 20776500 20761 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20777500 20762 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20778500 20763 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20779500 20764 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20780500 20765 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20781500 20766 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20782500 20767 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20783500 20768 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20799500 20784 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20800500 20785 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20803500 20788 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20804500 20789 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20805500 20790 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20808500 20793 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20811500 20796 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20814500 20799 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20817500 20802 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20818500 20803 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20819500 20804 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20820500 20805 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20823500 20808 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20824500 20809 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20827500 20812 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20828500 20813 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20831500 20816 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20833500 20818 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20836500 20821 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20837500 20822 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20840500 20825 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20841500 20826 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20842500 20827 1c001f42 e09ff06f jal x0, -504 + 20844500 20829 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20845500 20830 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108ff760 PA:108ff770 + 20846500 20831 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20849500 20834 1c001e34 00440c13 addi x24, x8, 4 x24=108ff7ec x8:108ff7e8 + 20850500 20835 1c001e38 00042503 lw x10, 0(x8) x10=00000005 x8:108ff7e8 PA:108ff7e8 + 20851500 20836 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20854500 20839 1c001e54 00055863 bge x10, x0, 16 x10:00000005 + 20857500 20842 1c001e64 00410593 addi x11, x2, 4 x11=108ff764 x2:108ff760 + 20858500 20843 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20860500 20845 1c0019fe 0105a683 lw x13, 16(x11) x13=108ff778 x11:108ff764 PA:108ff774 + 20861500 20846 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff764 PA:108ff770 + 20862500 20847 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20863500 20848 1c001a04 02f55633 divu x12, x10, x15 x12=00000005 x10:00000005 x15:00000001 + 20897500 20882 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000005 x14:0000000a + 20898500 20883 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20899500 20884 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20900500 20885 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20903500 20888 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ff764 PA:108ff770 + 20904500 20889 1c001a20 02f55833 divu x16, x10, x15 x16=00000005 x10:00000005 x15:00000001 + 20938500 20923 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000005 x15:00000001 + 20972500 20957 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21003500 20988 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21004500 20989 1c001a2e 01004663 blt x0, x16, 12 x16:00000005 + 21007500 20992 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21009500 20994 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000005 + 21012500 20997 1c001a56 01070733 add x14, x14, x16 x14=00000035 x14:00000030 x16:00000005 + 21013500 20998 1c001a58 00e68023 sb x14, 0(x13) x14:00000035 x13:108ff778 PA:108ff778 + 21014500 20999 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21015500 21000 1c001a5e 00168693 addi x13, x13, 1 x13=108ff779 x13:108ff778 + 21016500 21001 1c001a60 fb1ff06f jal x0, -80 + 21018500 21003 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21019500 21004 1c001a12 00068023 sb x0, 0(x13) x13:108ff779 PA:108ff779 + 21020500 21005 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21022500 21007 1c001e68 f17ff06f jal x0, -234 + 21024500 21009 1c001d7e 00410613 addi x12, x2, 4 x12=108ff764 x2:108ff760 + 21025500 21010 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21026500 21011 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21027500 21012 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21029500 21014 1c001a62 fe010113 addi x2, x2, -32 x2=108ff740 x2:108ff760 + 21030500 21015 1c001a64 00812c23 sw x8, 24(x2) x8:108ff7e8 x2:108ff740 PA:108ff758 + 21031500 21016 1c001a66 01062783 lw x15, 16(x12) x15=108ff778 x12:108ff764 PA:108ff774 + 21032500 21017 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108ff764 PA:108ff768 + 21033500 21018 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108ff740 PA:108ff754 + 21034500 21019 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108ff740 PA:108ff750 + 21035500 21020 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108ff740 PA:108ff74c + 21036500 21021 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108ff740 PA:108ff75c + 21037500 21022 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108ff740 PA:108ff748 + 21038500 21023 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21039500 21024 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21040500 21025 1c001a78 00c004b3 add x9, x0, x12 x9=108ff764 x12:108ff764 + 21041500 21026 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000035 x15=108ff779 x15:108ff778 PA:108ff778 + 21043500 21028 1c001a7e 00070363 beq x14, x0, 6 x14:00000035 + 21044500 21029 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21045500 21030 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108ff764 PA:108ff76c + 21047500 21032 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21050500 21035 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 21052500 21037 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21053500 21038 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21056500 21041 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21057500 21042 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21058500 21043 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21061500 21046 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21062500 21047 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21063500 21048 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21064500 21049 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21065500 21050 1c001b36 f71ff06f jal x0, -144 + 21067500 21052 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108ff764 PA:108ff76c + 21069500 21054 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21072500 21057 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 21074500 21059 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21075500 21060 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21078500 21063 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 21079500 21064 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21080500 21065 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21081500 21066 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21082500 21067 1c001ae8 0104aa03 lw x20, 16(x9) x20=108ff778 x9:108ff764 PA:108ff774 + 21084500 21069 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000035 x20=108ff779 x20:108ff778 PA:108ff778 + 21086500 21071 1c001af0 06059763 bne x11, x0, 110 x11:00000035 + 21089500 21074 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21090500 21075 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21092500 21077 1c001776 00b00533 add x10, x0, x11 x10=00000035 x11:00000035 + 21093500 21078 1c001778 fddff06f jal x0, -36 + 21095500 21080 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21096500 21081 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 21097500 21082 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21098500 21083 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 21099500 21084 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 21100500 21085 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 21101500 21086 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 21102500 21087 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 21103500 21088 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21104500 21089 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000035 x14:1a104000 PA:1a104128 + 21108500 21093 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21109500 21094 1c001b62 f8bff06f jal x0, -118 + 21111500 21096 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108ff77a x20:108ff779 PA:108ff779 + 21113500 21098 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21114500 21099 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ff764 PA:108ff764 + 21116500 21101 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21117500 21102 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21120500 21105 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108ff740 PA:108ff75c + 21121500 21106 1c001b02 01812403 lw x8, 24(x2) x8=108ff7e8 x2:108ff740 PA:108ff758 + 21122500 21107 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108ff740 PA:108ff754 + 21123500 21108 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108ff740 PA:108ff750 + 21124500 21109 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108ff740 PA:108ff74c + 21125500 21110 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108ff740 PA:108ff748 + 21126500 21111 1c001b0c 02010113 addi x2, x2, 32 x2=108ff760 x2:108ff740 + 21127500 21112 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21129500 21114 1c001d86 01800433 add x8, x0, x24 x8=108ff7ec x24:108ff7ec + 21130500 21115 1c001d88 fadff06f jal x0, -84 + 21132500 21117 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21133500 21118 1c001d36 e69ff06f jal x0, -408 + 21136500 21121 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21159500 21144 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21160500 21145 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21163500 21148 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21164500 21149 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21165500 21150 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21167500 21152 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21168500 21153 1c001778 fddff06f jal x0, -36 + 21170500 21155 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21171500 21156 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 21172500 21157 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21173500 21158 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 21174500 21159 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 21175500 21160 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 21176500 21161 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 21177500 21162 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 21178500 21163 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21179500 21164 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104128 + 21183500 21168 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21184500 21169 1c001bca 16a0006f jal x0, 362 + 21186500 21171 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21187500 21172 1c001d36 e69ff06f jal x0, -408 + 21190500 21175 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21211500 21196 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21212500 21197 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21215500 21200 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21216500 21201 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21217500 21202 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21219500 21204 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21220500 21205 1c001778 fddff06f jal x0, -36 + 21222500 21207 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21223500 21208 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 21224500 21209 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21225500 21210 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 21226500 21211 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 21227500 21212 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 21228500 21213 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 21229500 21214 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 21230500 21215 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21231500 21216 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104128 + 21235500 21220 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21236500 21221 1c001bca 16a0006f jal x0, 362 + 21238500 21223 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21239500 21224 1c001d36 e69ff06f jal x0, -408 + 21242500 21227 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21256500 21241 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21257500 21242 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21260500 21245 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21261500 21246 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21262500 21247 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21264500 21249 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21265500 21250 1c001778 fddff06f jal x0, -36 + 21267500 21252 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21268500 21253 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000045 + 21269500 21254 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21270500 21255 1c00175e 00379713 slli x14, x15, 0x3 x14=00000228 x15:00000045 + 21271500 21256 1c001762 00279793 slli x15, x15, 0x2 x15=00000114 x15:00000045 + 21272500 21257 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000228 + 21273500 21258 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000114 x13:00001f80 + 21274500 21259 1c00176a 00e787b3 add x15, x15, x14 x15=00000128 x15:00000100 x14:00000028 + 21275500 21260 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21276500 21261 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104128 + 21280500 21265 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21281500 21266 1c001bca 16a0006f jal x0, 362 + 21283500 21268 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21284500 21269 1c001d36 e69ff06f jal x0, -408 + 21287500 21272 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21304500 21289 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21305500 21290 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21306500 21291 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108ff760 PA:108ff7bc + 21307500 21292 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:108ff760 PA:108ff7b8 + 21308500 21293 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:108ff760 PA:108ff7b4 + 21309500 21294 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:108ff760 PA:108ff7b0 + 21310500 21295 1c001bb0 04c12983 lw x19, 76(x2) x19=00000005 x2:108ff760 PA:108ff7ac + 21312500 21297 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:108ff760 PA:108ff7a8 + 21313500 21298 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:108ff760 PA:108ff7a4 + 21314500 21299 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:108ff760 PA:108ff7a0 + 21315500 21300 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:108ff760 PA:108ff79c + 21318500 21303 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:108ff760 PA:108ff798 + 21319500 21304 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:108ff760 PA:108ff794 + 21320500 21305 1c001bbe 06010113 addi x2, x2, 96 x2=108ff7c0 x2:108ff760 + 21321500 21306 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21323500 21308 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:108ff7c0 PA:108ff7dc + 21326500 21311 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21327500 21312 1c001838 04010113 addi x2, x2, 64 x2=108ff800 x2:108ff7c0 + 21328500 21313 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21330500 21315 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_6.log b/sw/scripts/tracevis/example/traces/trace_core_02_6.log new file mode 100644 index 0000000..7754095 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_6.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000046 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000006 x10:00000046 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000046 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000006 + 14871500 14856 1c0000a6 05a0206f jal x0, 8282 + 14889500 14874 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14890500 14875 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14891500 14876 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14892500 14877 1c00210c 0e059163 bne x11, x0, 226 x11:00000006 + 14944500 14929 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 14945500 14930 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000046 + 14946500 14931 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000006 x19:00000046 + 14947500 14932 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 14964500 14949 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 14965500 14950 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 14966500 14951 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 14967500 14952 1c00220a 0060006f jal x0, 6 + 14986500 14971 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18321500 18306 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18338500 18323 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18339500 18324 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18361500 18346 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18362500 18347 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18364500 18349 1c00222c 08096283 p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080 + 18388500 18373 1c002230 02a98533 mul x10, x19, x10 x10=00001800 x19:00000006 x10:00000400 + 18389500 18374 1c002234 00550133 add x2, x10, x5 x2=108ffc00 x10:00001800 x5:108fe400 + 18390500 18375 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18392500 18377 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18427500 18412 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18435500 18420 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18436500 18421 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18437500 18422 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18438500 18423 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18459500 18444 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000046 + 18476500 18461 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18477500 18462 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000002 x12:00000046 + 18478500 18463 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002 + 18479500 18464 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000006 x12:00000046 + 18480500 18465 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18481500 18466 1c0009d4 63d0006f jal x0, 3644 + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108ffbc0 x2:108ffc00 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108ffbc0 PA:108ffbe4 + 18509500 18494 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18510500 18495 1c001818 02c12423 sw x12, 40(x2) x12:00000006 x2:108ffbc0 PA:108ffbe8 + 18511500 18496 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108ffbc0 PA:108ffbec + 18512500 18497 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18513500 18498 1c00181e 02410693 addi x13, x2, 36 x13=108ffbe4 x2:108ffbc0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:108ffbc0 PA:108ffbdc + 18535500 18520 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:108ffbc0 PA:108ffbf0 + 18536500 18521 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:108ffbc0 PA:108ffbf4 + 18537500 18522 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108ffbc0 PA:108ffbf8 + 18538500 18523 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108ffbc0 PA:108ffbfc + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108ffbe4 x2:108ffbc0 PA:108ffbcc + 18556500 18541 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108ffb60 x2:108ffbc0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108ffb78 x2:108ffb60 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:108ffb60 PA:108ffbb8 + 18575500 18560 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:108ffb60 PA:108ffbb0 + 18576500 18561 1c001b78 05312623 sw x19, 76(x2) x19:00000006 x2:108ffb60 PA:108ffbac + 18577500 18562 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:108ffb60 PA:108ffba8 + 18578500 18563 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:108ffb60 PA:108ffba4 + 18579500 18564 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:108ffb60 PA:108ffba0 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:108ffb60 PA:108ffb9c + 18593500 18578 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108ffb60 PA:108ffbbc + 18594500 18579 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:108ffb60 PA:108ffbb4 + 18595500 18580 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:108ffb60 PA:108ffb98 + 18596500 18581 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:108ffb60 PA:108ffb94 + 18597500 18582 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18598500 18583 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18599500 18584 1c001b8e 00d00433 add x8, x0, x13 x8=108ffbe4 x13:108ffbe4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108ffb78 x2:108ffb60 PA:108ffb74 + 18622500 18607 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18623500 18608 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18624500 18609 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18625500 18610 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18665500 18650 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18666500 18651 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18678500 18663 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18679500 18664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18680500 18665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104130 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18799500 18784 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18800500 18785 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18803500 18788 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18804500 18789 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18805500 18790 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18807500 18792 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18808500 18793 1c001778 fddff06f jal x0, -36 + 18810500 18795 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18811500 18796 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 18812500 18797 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18813500 18798 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 18814500 18799 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 18815500 18800 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 18816500 18801 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 18817500 18802 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 18818500 18803 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18819500 18804 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104130 + 18823500 18808 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18824500 18809 1c001bca 16a0006f jal x0, 362 + 18826500 18811 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18827500 18812 1c001d36 e69ff06f jal x0, -408 + 18830500 18815 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18844500 18829 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18845500 18830 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18848500 18833 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18849500 18834 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18850500 18835 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18852500 18837 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18853500 18838 1c001778 fddff06f jal x0, -36 + 18855500 18840 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18856500 18841 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 18857500 18842 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18858500 18843 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 18859500 18844 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 18860500 18845 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 18861500 18846 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 18862500 18847 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 18863500 18848 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18864500 18849 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104130 + 18868500 18853 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18869500 18854 1c001bca 16a0006f jal x0, 362 + 18871500 18856 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18872500 18857 1c001d36 e69ff06f jal x0, -408 + 18875500 18860 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18894500 18879 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18895500 18880 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18898500 18883 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18899500 18884 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18900500 18885 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18902500 18887 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18903500 18888 1c001778 fddff06f jal x0, -36 + 18905500 18890 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18906500 18891 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 18907500 18892 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18908500 18893 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 18909500 18894 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 18910500 18895 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 18911500 18896 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 18912500 18897 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 18913500 18898 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18914500 18899 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104130 + 18918500 18903 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18919500 18904 1c001bca 16a0006f jal x0, 362 + 18921500 18906 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18922500 18907 1c001d36 e69ff06f jal x0, -408 + 18925500 18910 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18941500 18926 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18942500 18927 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18945500 18930 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18946500 18931 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18947500 18932 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18949500 18934 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18950500 18935 1c001778 fddff06f jal x0, -36 + 18952500 18937 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18953500 18938 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 18954500 18939 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18955500 18940 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 18956500 18941 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 18957500 18942 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 18958500 18943 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 18959500 18944 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 18960500 18945 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18961500 18946 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104130 + 18965500 18950 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18966500 18951 1c001bca 16a0006f jal x0, 362 + 18968500 18953 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18969500 18954 1c001d36 e69ff06f jal x0, -408 + 18972500 18957 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18989500 18974 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18990500 18975 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18993500 18978 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18994500 18979 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18995500 18980 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18997500 18982 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 18998500 18983 1c001778 fddff06f jal x0, -36 + 19000500 18985 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19001500 18986 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19002500 18987 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19003500 18988 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19004500 18989 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19005500 18990 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19006500 18991 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19007500 18992 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19008500 18993 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19009500 18994 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104130 + 19013500 18998 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19014500 18999 1c001bca 16a0006f jal x0, 362 + 19016500 19001 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19017500 19002 1c001d36 e69ff06f jal x0, -408 + 19020500 19005 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19036500 19021 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19037500 19022 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19040500 19025 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19041500 19026 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19042500 19027 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19044500 19029 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19045500 19030 1c001778 fddff06f jal x0, -36 + 19047500 19032 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19048500 19033 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19049500 19034 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19050500 19035 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19051500 19036 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19052500 19037 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19053500 19038 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19054500 19039 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19055500 19040 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19056500 19041 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104130 + 19060500 19045 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19061500 19046 1c001bca 16a0006f jal x0, 362 + 19063500 19048 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19064500 19049 1c001d36 e69ff06f jal x0, -408 + 19067500 19052 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19083500 19068 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19084500 19069 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19087500 19072 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19088500 19073 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19089500 19074 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19091500 19076 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19092500 19077 1c001778 fddff06f jal x0, -36 + 19094500 19079 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19095500 19080 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19096500 19081 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19097500 19082 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19098500 19083 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19099500 19084 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19100500 19085 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19101500 19086 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19102500 19087 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19103500 19088 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104130 + 19107500 19092 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19108500 19093 1c001bca 16a0006f jal x0, 362 + 19110500 19095 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19111500 19096 1c001d36 e69ff06f jal x0, -408 + 19114500 19099 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19130500 19115 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19131500 19116 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19134500 19119 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19135500 19120 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19136500 19121 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19138500 19123 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19139500 19124 1c001778 fddff06f jal x0, -36 + 19141500 19126 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19142500 19127 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19143500 19128 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19144500 19129 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19145500 19130 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19146500 19131 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19147500 19132 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19148500 19133 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19149500 19134 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19150500 19135 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104130 + 19154500 19139 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19155500 19140 1c001bca 16a0006f jal x0, 362 + 19157500 19142 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19158500 19143 1c001d36 e69ff06f jal x0, -408 + 19161500 19146 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19191500 19176 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19192500 19177 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19195500 19180 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19196500 19181 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19197500 19182 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19199500 19184 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19200500 19185 1c001778 fddff06f jal x0, -36 + 19202500 19187 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19203500 19188 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19204500 19189 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19205500 19190 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19206500 19191 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19207500 19192 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19208500 19193 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19209500 19194 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19210500 19195 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19211500 19196 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104130 + 19215500 19200 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19216500 19201 1c001bca 16a0006f jal x0, 362 + 19218500 19203 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19219500 19204 1c001d36 e69ff06f jal x0, -408 + 19222500 19207 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19241500 19226 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19242500 19227 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19245500 19230 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19246500 19231 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19247500 19232 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19249500 19234 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19250500 19235 1c001778 fddff06f jal x0, -36 + 19252500 19237 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19253500 19238 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19254500 19239 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19255500 19240 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19256500 19241 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19257500 19242 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19258500 19243 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19259500 19244 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19260500 19245 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19261500 19246 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104130 + 19265500 19250 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19266500 19251 1c001bca 16a0006f jal x0, 362 + 19268500 19253 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19269500 19254 1c001d36 e69ff06f jal x0, -408 + 19272500 19257 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19288500 19273 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19289500 19274 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19292500 19277 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19293500 19278 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19294500 19279 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19296500 19281 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19297500 19282 1c001778 fddff06f jal x0, -36 + 19299500 19284 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19300500 19285 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19301500 19286 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19302500 19287 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19303500 19288 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19304500 19289 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19305500 19290 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19306500 19291 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19307500 19292 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19308500 19293 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104130 + 19312500 19297 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19313500 19298 1c001bca 16a0006f jal x0, 362 + 19315500 19300 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19316500 19301 1c001d36 e69ff06f jal x0, -408 + 19319500 19304 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19336500 19321 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19337500 19322 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19340500 19325 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19341500 19326 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19342500 19327 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19344500 19329 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19345500 19330 1c001778 fddff06f jal x0, -36 + 19347500 19332 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19348500 19333 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19349500 19334 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19350500 19335 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19351500 19336 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19352500 19337 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19353500 19338 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19354500 19339 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19355500 19340 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19356500 19341 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104130 + 19360500 19345 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19361500 19346 1c001bca 16a0006f jal x0, 362 + 19363500 19348 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19364500 19349 1c001d36 e69ff06f jal x0, -408 + 19367500 19352 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19387500 19372 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19388500 19373 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19391500 19376 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19392500 19377 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19393500 19378 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19395500 19380 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19396500 19381 1c001778 fddff06f jal x0, -36 + 19398500 19383 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19399500 19384 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19400500 19385 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19401500 19386 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19402500 19387 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19403500 19388 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19404500 19389 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19405500 19390 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19406500 19391 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19407500 19392 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104130 + 19411500 19396 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19412500 19397 1c001bca 16a0006f jal x0, 362 + 19414500 19399 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19415500 19400 1c001d36 e69ff06f jal x0, -408 + 19418500 19403 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19436500 19421 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19437500 19422 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19440500 19425 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19441500 19426 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19442500 19427 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19444500 19429 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19445500 19430 1c001778 fddff06f jal x0, -36 + 19447500 19432 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19448500 19433 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 19449500 19434 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19450500 19435 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 19451500 19436 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 19452500 19437 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 19453500 19438 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 19454500 19439 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 19455500 19440 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19456500 19441 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104130 + 19460500 19445 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19461500 19446 1c001bca 16a0006f jal x0, 362 + 19463500 19448 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19464500 19449 1c001d36 e69ff06f jal x0, -408 + 19467500 19452 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19487500 19472 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19488500 19473 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19491500 19476 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19494500 19479 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108ffb60 PA:108ffb64 + 19495500 19480 1c001bd0 00012423 sw x0, 8(x2) x2:108ffb60 PA:108ffb68 + 19496500 19481 1c001bd2 00010623 sb x0, 12(x2) x2:108ffb60 PA:108ffb6c + 19497500 19482 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19498500 19483 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19513500 19498 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19514500 19499 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108ffb60 PA:108ffb64 + 19519500 19504 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19520500 19505 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19521500 19506 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19522500 19507 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19523500 19508 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19569500 19554 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19570500 19555 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19586500 19571 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19587500 19572 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19588500 19573 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108ffb60 PA:108ffb70 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108ffbe8 x8:108ffbe4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108ffbe4 PA:108ffbe4 + 19951500 19936 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108ffb64 x2:108ffb60 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108ffb78 x11:108ffb64 PA:108ffb74 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ffb64 PA:108ffb70 + 20047500 20032 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20048500 20033 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20082500 20067 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20083500 20068 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20084500 20069 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20085500 20070 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20088500 20073 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ffb64 PA:108ffb70 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108ffb78 PA:108ffb78 + 20251500 20236 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20252500 20237 1c001a5e 00168693 addi x13, x13, 1 x13=108ffb79 x13:108ffb78 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108ffb79 PA:108ffb79 + 20271500 20256 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20272500 20257 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108ffb64 x2:108ffb60 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108ffb40 x2:108ffb60 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108ffbe4 x2:108ffb40 PA:108ffb58 + 20323500 20308 1c001a66 01062783 lw x15, 16(x12) x15=108ffb78 x12:108ffb64 PA:108ffb74 + 20324500 20309 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108ffb64 PA:108ffb68 + 20325500 20310 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108ffb40 PA:108ffb54 + 20326500 20311 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108ffb40 PA:108ffb50 + 20327500 20312 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108ffb40 PA:108ffb4c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108ffb40 PA:108ffb5c + 20344500 20329 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108ffb40 PA:108ffb48 + 20345500 20330 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20346500 20331 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20347500 20332 1c001a78 00c004b3 add x9, x0, x12 x9=108ffb64 x12:108ffb64 + 20348500 20333 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108ffb79 x15:108ffb78 PA:108ffb78 + 20350500 20335 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108ffb64 PA:108ffb6c + 20366500 20351 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20369500 20354 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108ffb64 PA:108ffb6c + 20456500 20441 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 20474500 20459 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20475500 20460 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108ffb78 x9:108ffb64 PA:108ffb74 + 20516500 20501 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108ffb79 x20:108ffb78 PA:108ffb78 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104130 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108ffb7a x20:108ffb79 PA:108ffb79 + 20593500 20578 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20594500 20579 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 20596500 20581 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20597500 20582 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108ffb40 PA:108ffb5c + 20616500 20601 1c001b02 01812403 lw x8, 24(x2) x8=108ffbe4 x2:108ffb40 PA:108ffb58 + 20617500 20602 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108ffb40 PA:108ffb54 + 20618500 20603 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108ffb40 PA:108ffb50 + 20619500 20604 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108ffb40 PA:108ffb4c + 20620500 20605 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108ffb40 PA:108ffb48 + 20621500 20606 1c001b0c 02010113 addi x2, x2, 32 x2=108ffb60 x2:108ffb40 + 20622500 20607 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108ffbe8 x24:108ffbe8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20674500 20659 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20675500 20660 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20678500 20663 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20679500 20664 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20680500 20665 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20682500 20667 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20683500 20668 1c001778 fddff06f jal x0, -36 + 20685500 20670 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20686500 20671 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 20687500 20672 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20688500 20673 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 20689500 20674 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 20690500 20675 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 20691500 20676 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 20692500 20677 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 20693500 20678 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20694500 20679 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104130 + 20698500 20683 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20699500 20684 1c001bca 16a0006f jal x0, 362 + 20701500 20686 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20702500 20687 1c001d36 e69ff06f jal x0, -408 + 20705500 20690 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20721500 20706 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20722500 20707 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20725500 20710 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20726500 20711 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20727500 20712 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20729500 20714 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20730500 20715 1c001778 fddff06f jal x0, -36 + 20732500 20717 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20733500 20718 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 20734500 20719 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20735500 20720 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 20736500 20721 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 20737500 20722 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 20738500 20723 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 20739500 20724 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 20740500 20725 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20741500 20726 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104130 + 20745500 20730 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20746500 20731 1c001bca 16a0006f jal x0, 362 + 20748500 20733 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20749500 20734 1c001d36 e69ff06f jal x0, -408 + 20752500 20737 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20766500 20751 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20767500 20752 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20770500 20755 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20773500 20758 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108ffb60 PA:108ffb64 + 20774500 20759 1c001bd0 00012423 sw x0, 8(x2) x2:108ffb60 PA:108ffb68 + 20775500 20760 1c001bd2 00010623 sb x0, 12(x2) x2:108ffb60 PA:108ffb6c + 20776500 20761 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20777500 20762 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20778500 20763 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20779500 20764 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108ffb60 PA:108ffb64 + 20780500 20765 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20781500 20766 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20782500 20767 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20783500 20768 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20784500 20769 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20785500 20770 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20786500 20771 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20787500 20772 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20801500 20786 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20802500 20787 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20805500 20790 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20806500 20791 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20807500 20792 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20810500 20795 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20813500 20798 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20816500 20801 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20819500 20804 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20820500 20805 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20821500 20806 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20822500 20807 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20825500 20810 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20826500 20811 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20829500 20814 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20830500 20815 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20833500 20818 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20835500 20820 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20838500 20823 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20839500 20824 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20842500 20827 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20843500 20828 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20844500 20829 1c001f42 e09ff06f jal x0, -504 + 20846500 20831 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20847500 20832 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108ffb60 PA:108ffb70 + 20848500 20833 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20851500 20836 1c001e34 00440c13 addi x24, x8, 4 x24=108ffbec x8:108ffbe8 + 20852500 20837 1c001e38 00042503 lw x10, 0(x8) x10=00000006 x8:108ffbe8 PA:108ffbe8 + 20853500 20838 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20856500 20841 1c001e54 00055863 bge x10, x0, 16 x10:00000006 + 20859500 20844 1c001e64 00410593 addi x11, x2, 4 x11=108ffb64 x2:108ffb60 + 20860500 20845 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20862500 20847 1c0019fe 0105a683 lw x13, 16(x11) x13=108ffb78 x11:108ffb64 PA:108ffb74 + 20863500 20848 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ffb64 PA:108ffb70 + 20864500 20849 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20865500 20850 1c001a04 02f55633 divu x12, x10, x15 x12=00000006 x10:00000006 x15:00000001 + 20899500 20884 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000006 x14:0000000a + 20900500 20885 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20901500 20886 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20902500 20887 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20905500 20890 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108ffb64 PA:108ffb70 + 20906500 20891 1c001a20 02f55833 divu x16, x10, x15 x16=00000006 x10:00000006 x15:00000001 + 20940500 20925 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000006 x15:00000001 + 20974500 20959 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21005500 20990 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21006500 20991 1c001a2e 01004663 blt x0, x16, 12 x16:00000006 + 21009500 20994 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21011500 20996 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000006 + 21014500 20999 1c001a56 01070733 add x14, x14, x16 x14=00000036 x14:00000030 x16:00000006 + 21015500 21000 1c001a58 00e68023 sb x14, 0(x13) x14:00000036 x13:108ffb78 PA:108ffb78 + 21016500 21001 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21017500 21002 1c001a5e 00168693 addi x13, x13, 1 x13=108ffb79 x13:108ffb78 + 21018500 21003 1c001a60 fb1ff06f jal x0, -80 + 21020500 21005 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21021500 21006 1c001a12 00068023 sb x0, 0(x13) x13:108ffb79 PA:108ffb79 + 21022500 21007 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21024500 21009 1c001e68 f17ff06f jal x0, -234 + 21026500 21011 1c001d7e 00410613 addi x12, x2, 4 x12=108ffb64 x2:108ffb60 + 21027500 21012 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21028500 21013 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21029500 21014 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21031500 21016 1c001a62 fe010113 addi x2, x2, -32 x2=108ffb40 x2:108ffb60 + 21032500 21017 1c001a64 00812c23 sw x8, 24(x2) x8:108ffbe8 x2:108ffb40 PA:108ffb58 + 21033500 21018 1c001a66 01062783 lw x15, 16(x12) x15=108ffb78 x12:108ffb64 PA:108ffb74 + 21034500 21019 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108ffb64 PA:108ffb68 + 21035500 21020 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108ffb40 PA:108ffb54 + 21036500 21021 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108ffb40 PA:108ffb50 + 21037500 21022 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108ffb40 PA:108ffb4c + 21038500 21023 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108ffb40 PA:108ffb5c + 21039500 21024 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108ffb40 PA:108ffb48 + 21040500 21025 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21041500 21026 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21042500 21027 1c001a78 00c004b3 add x9, x0, x12 x9=108ffb64 x12:108ffb64 + 21043500 21028 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000036 x15=108ffb79 x15:108ffb78 PA:108ffb78 + 21045500 21030 1c001a7e 00070363 beq x14, x0, 6 x14:00000036 + 21046500 21031 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21047500 21032 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108ffb64 PA:108ffb6c + 21049500 21034 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21052500 21037 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 21054500 21039 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21055500 21040 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21058500 21043 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21059500 21044 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21060500 21045 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21063500 21048 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21064500 21049 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21065500 21050 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21066500 21051 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21067500 21052 1c001b36 f71ff06f jal x0, -144 + 21069500 21054 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108ffb64 PA:108ffb6c + 21071500 21056 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21074500 21059 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 21076500 21061 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21077500 21062 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21080500 21065 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 21081500 21066 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21082500 21067 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21083500 21068 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21084500 21069 1c001ae8 0104aa03 lw x20, 16(x9) x20=108ffb78 x9:108ffb64 PA:108ffb74 + 21086500 21071 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000036 x20=108ffb79 x20:108ffb78 PA:108ffb78 + 21088500 21073 1c001af0 06059763 bne x11, x0, 110 x11:00000036 + 21091500 21076 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21092500 21077 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21094500 21079 1c001776 00b00533 add x10, x0, x11 x10=00000036 x11:00000036 + 21095500 21080 1c001778 fddff06f jal x0, -36 + 21097500 21082 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21098500 21083 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 21099500 21084 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21100500 21085 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 21101500 21086 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 21102500 21087 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 21103500 21088 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 21104500 21089 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 21105500 21090 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21106500 21091 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000036 x14:1a104000 PA:1a104130 + 21110500 21095 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21111500 21096 1c001b62 f8bff06f jal x0, -118 + 21113500 21098 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108ffb7a x20:108ffb79 PA:108ffb79 + 21115500 21100 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21116500 21101 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108ffb64 PA:108ffb64 + 21118500 21103 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21119500 21104 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21122500 21107 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108ffb40 PA:108ffb5c + 21123500 21108 1c001b02 01812403 lw x8, 24(x2) x8=108ffbe8 x2:108ffb40 PA:108ffb58 + 21124500 21109 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108ffb40 PA:108ffb54 + 21125500 21110 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108ffb40 PA:108ffb50 + 21126500 21111 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108ffb40 PA:108ffb4c + 21127500 21112 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108ffb40 PA:108ffb48 + 21128500 21113 1c001b0c 02010113 addi x2, x2, 32 x2=108ffb60 x2:108ffb40 + 21129500 21114 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21131500 21116 1c001d86 01800433 add x8, x0, x24 x8=108ffbec x24:108ffbec + 21132500 21117 1c001d88 fadff06f jal x0, -84 + 21134500 21119 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21135500 21120 1c001d36 e69ff06f jal x0, -408 + 21138500 21123 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21161500 21146 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21162500 21147 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21165500 21150 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21166500 21151 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21167500 21152 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21169500 21154 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21170500 21155 1c001778 fddff06f jal x0, -36 + 21172500 21157 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21173500 21158 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 21174500 21159 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21175500 21160 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 21176500 21161 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 21177500 21162 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 21178500 21163 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 21179500 21164 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 21180500 21165 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21181500 21166 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104130 + 21185500 21170 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21186500 21171 1c001bca 16a0006f jal x0, 362 + 21188500 21173 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21189500 21174 1c001d36 e69ff06f jal x0, -408 + 21192500 21177 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21213500 21198 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21214500 21199 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21217500 21202 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21218500 21203 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21219500 21204 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21221500 21206 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21222500 21207 1c001778 fddff06f jal x0, -36 + 21224500 21209 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21225500 21210 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 21226500 21211 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21227500 21212 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 21228500 21213 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 21229500 21214 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 21230500 21215 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 21231500 21216 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 21232500 21217 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21233500 21218 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104130 + 21237500 21222 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21238500 21223 1c001bca 16a0006f jal x0, 362 + 21240500 21225 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21241500 21226 1c001d36 e69ff06f jal x0, -408 + 21244500 21229 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21258500 21243 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21259500 21244 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21262500 21247 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21263500 21248 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21264500 21249 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21266500 21251 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21267500 21252 1c001778 fddff06f jal x0, -36 + 21269500 21254 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21270500 21255 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000046 + 21271500 21256 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21272500 21257 1c00175e 00379713 slli x14, x15, 0x3 x14=00000230 x15:00000046 + 21273500 21258 1c001762 00279793 slli x15, x15, 0x2 x15=00000118 x15:00000046 + 21274500 21259 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000230 + 21275500 21260 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:00000118 x13:00001f80 + 21276500 21261 1c00176a 00e787b3 add x15, x15, x14 x15=00000130 x15:00000100 x14:00000030 + 21277500 21262 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21278500 21263 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104130 + 21282500 21267 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21283500 21268 1c001bca 16a0006f jal x0, 362 + 21285500 21270 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21286500 21271 1c001d36 e69ff06f jal x0, -408 + 21289500 21274 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21306500 21291 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21307500 21292 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21308500 21293 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108ffb60 PA:108ffbbc + 21309500 21294 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:108ffb60 PA:108ffbb8 + 21310500 21295 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:108ffb60 PA:108ffbb4 + 21311500 21296 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:108ffb60 PA:108ffbb0 + 21312500 21297 1c001bb0 04c12983 lw x19, 76(x2) x19=00000006 x2:108ffb60 PA:108ffbac + 21313500 21298 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:108ffb60 PA:108ffba8 + 21314500 21299 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:108ffb60 PA:108ffba4 + 21315500 21300 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:108ffb60 PA:108ffba0 + 21316500 21301 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:108ffb60 PA:108ffb9c + 21319500 21304 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:108ffb60 PA:108ffb98 + 21320500 21305 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:108ffb60 PA:108ffb94 + 21321500 21306 1c001bbe 06010113 addi x2, x2, 96 x2=108ffbc0 x2:108ffb60 + 21322500 21307 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21324500 21309 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:108ffbc0 PA:108ffbdc + 21325500 21310 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21326500 21311 1c001838 04010113 addi x2, x2, 64 x2=108ffc00 x2:108ffbc0 + 21327500 21312 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21329500 21314 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_02_7.log b/sw/scripts/tracevis/example/traces/trace_core_02_7.log new file mode 100644 index 0000000..efa757e --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_02_7.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 14833500 14818 1c000080 0180006f jal x0, 24 + 14851500 14836 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000047 + 14852500 14837 1c00009c 01f57593 andi x11, x10, 31 x11=00000007 x10:00000047 + 14869500 14854 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000002 x10:00000047 + 14870500 14855 1c0000a2 00058463 beq x11, x0, 8 x11:00000007 + 14871500 14856 1c0000a6 05a0206f jal x0, 8282 + 14889500 14874 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 14890500 14875 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 14891500 14876 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 14892500 14877 1c00210c 0e059163 bne x11, x0, 226 x11:00000007 + 14944500 14929 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 14945500 14930 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000047 + 14946500 14931 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000007 x19:00000047 + 14947500 14932 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 14964500 14949 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 14965500 14950 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 14966500 14951 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 14967500 14952 1c00220a 0060006f jal x0, 6 + 14986500 14971 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18321500 18306 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18338500 18323 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18339500 18324 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18361500 18346 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18362500 18347 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18364500 18349 1c00222c 08096283 p.elw x5, 128(x18) x5=108fe400 x18:1b204000 PA:1b204080 + 18388500 18373 1c002230 02a98533 mul x10, x19, x10 x10=00001c00 x19:00000007 x10:00000400 + 18389500 18374 1c002234 00550133 add x2, x10, x5 x2=10900000 x10:00001c00 x5:108fe400 + 18390500 18375 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18392500 18377 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18427500 18412 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18435500 18420 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18436500 18421 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18437500 18422 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18438500 18423 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18459500 18444 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000047 + 18476500 18461 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18477500 18462 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000002 x12:00000047 + 18478500 18463 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000002 x11:00000002 + 18479500 18464 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000007 x12:00000047 + 18480500 18465 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18481500 18466 1c0009d4 63d0006f jal x0, 3644 + 18502500 18487 1c001810 fc010113 addi x2, x2, -64 x2=108fffc0 x2:10900000 + 18503500 18488 1c001812 02b12223 sw x11, 36(x2) x11:00000002 x2:108fffc0 PA:108fffe4 + 18510500 18495 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 18511500 18496 1c001818 02c12423 sw x12, 40(x2) x12:00000007 x2:108fffc0 PA:108fffe8 + 18512500 18497 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:108fffc0 PA:108fffec + 18513500 18498 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 18514500 18499 1c00181e 02410693 addi x13, x2, 36 x13=108fffe4 x2:108fffc0 + 18526500 18511 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 18527500 18512 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 18528500 18513 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:108fffc0 PA:108fffdc + 18534500 18519 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:108fffc0 PA:108ffff0 + 18535500 18520 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:108fffc0 PA:108ffff4 + 18536500 18521 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:108fffc0 PA:108ffff8 + 18537500 18522 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:108fffc0 PA:108ffffc + 18549500 18534 1c001830 00d12623 sw x13, 12(x2) x13:108fffe4 x2:108fffc0 PA:108fffcc + 18554500 18539 1c001832 33e000ef jal x1, 830 x1=1c001834 + 18568500 18553 1c001b70 fa010113 addi x2, x2, -96 x2=108fff60 x2:108fffc0 + 18569500 18554 1c001b72 01810793 addi x15, x2, 24 x15=108fff78 x2:108fff60 + 18570500 18555 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:108fff60 PA:108fffb8 + 18576500 18561 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:108fff60 PA:108fffb0 + 18577500 18562 1c001b78 05312623 sw x19, 76(x2) x19:00000007 x2:108fff60 PA:108fffac + 18578500 18563 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:108fff60 PA:108fffa8 + 18579500 18564 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:108fff60 PA:108fffa4 + 18580500 18565 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:108fff60 PA:108fffa0 + 18592500 18577 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:108fff60 PA:108fff9c + 18594500 18579 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:108fff60 PA:108fffbc + 18595500 18580 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:108fff60 PA:108fffb4 + 18596500 18581 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:108fff60 PA:108fff98 + 18597500 18582 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:108fff60 PA:108fff94 + 18598500 18583 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 18599500 18584 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 18600500 18585 1c001b8e 00d00433 add x8, x0, x13 x8=108fffe4 x13:108fffe4 + 18616500 18601 1c001b90 00f12a23 sw x15, 20(x2) x15:108fff78 x2:108fff60 PA:108fff74 + 18623500 18608 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 18624500 18609 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 18625500 18610 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 18626500 18611 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 18638500 18623 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 18671500 18656 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 18672500 18657 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 18679500 18664 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 18680500 18665 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18681500 18666 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18698500 18683 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 18699500 18684 1c001778 fddff06f jal x0, -36 + 18718500 18703 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18719500 18704 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 18720500 18705 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18738500 18723 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 18739500 18724 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 18740500 18725 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 18741500 18726 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 18742500 18727 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 18743500 18728 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18744500 18729 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104138 + 18748500 18733 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18749500 18734 1c001bca 16a0006f jal x0, 362 + 18768500 18753 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 18769500 18754 1c001d36 e69ff06f jal x0, -408 + 18772500 18757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 18801500 18786 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 18802500 18787 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 18805500 18790 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 18806500 18791 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18807500 18792 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18809500 18794 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 18810500 18795 1c001778 fddff06f jal x0, -36 + 18812500 18797 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18813500 18798 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 18814500 18799 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18815500 18800 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 18816500 18801 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 18817500 18802 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 18818500 18803 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 18819500 18804 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 18820500 18805 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18821500 18806 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104138 + 18825500 18810 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18826500 18811 1c001bca 16a0006f jal x0, 362 + 18828500 18813 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 18829500 18814 1c001d36 e69ff06f jal x0, -408 + 18832500 18817 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 18846500 18831 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 18847500 18832 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 18850500 18835 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 18851500 18836 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18852500 18837 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18854500 18839 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 18855500 18840 1c001778 fddff06f jal x0, -36 + 18857500 18842 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18858500 18843 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 18859500 18844 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18860500 18845 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 18861500 18846 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 18862500 18847 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 18863500 18848 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 18864500 18849 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 18865500 18850 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18866500 18851 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104138 + 18870500 18855 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18871500 18856 1c001bca 16a0006f jal x0, 362 + 18873500 18858 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 18874500 18859 1c001d36 e69ff06f jal x0, -408 + 18877500 18862 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 18896500 18881 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 18897500 18882 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 18900500 18885 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 18901500 18886 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18902500 18887 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18904500 18889 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 18905500 18890 1c001778 fddff06f jal x0, -36 + 18907500 18892 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18908500 18893 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 18909500 18894 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18910500 18895 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 18911500 18896 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 18912500 18897 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 18913500 18898 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 18914500 18899 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 18915500 18900 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18916500 18901 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104138 + 18920500 18905 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18921500 18906 1c001bca 16a0006f jal x0, 362 + 18923500 18908 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 18924500 18909 1c001d36 e69ff06f jal x0, -408 + 18927500 18912 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 18943500 18928 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 18944500 18929 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 18947500 18932 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 18948500 18933 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18949500 18934 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 18951500 18936 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 18952500 18937 1c001778 fddff06f jal x0, -36 + 18954500 18939 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 18955500 18940 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 18956500 18941 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 18957500 18942 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 18958500 18943 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 18959500 18944 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 18960500 18945 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 18961500 18946 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 18962500 18947 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 18963500 18948 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104138 + 18967500 18952 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 18968500 18953 1c001bca 16a0006f jal x0, 362 + 18970500 18955 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 18971500 18956 1c001d36 e69ff06f jal x0, -408 + 18974500 18959 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 18993500 18978 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 18994500 18979 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 18997500 18982 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 18998500 18983 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 18999500 18984 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19001500 18986 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19002500 18987 1c001778 fddff06f jal x0, -36 + 19004500 18989 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19005500 18990 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19006500 18991 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19007500 18992 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19008500 18993 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19009500 18994 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19010500 18995 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19011500 18996 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19012500 18997 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19013500 18998 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104138 + 19017500 19002 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19018500 19003 1c001bca 16a0006f jal x0, 362 + 19020500 19005 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19021500 19006 1c001d36 e69ff06f jal x0, -408 + 19024500 19009 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19042500 19027 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19043500 19028 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19046500 19031 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19047500 19032 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19048500 19033 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19050500 19035 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19051500 19036 1c001778 fddff06f jal x0, -36 + 19053500 19038 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19054500 19039 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19055500 19040 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19056500 19041 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19057500 19042 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19058500 19043 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19059500 19044 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19060500 19045 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19061500 19046 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19062500 19047 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104138 + 19066500 19051 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19067500 19052 1c001bca 16a0006f jal x0, 362 + 19069500 19054 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19070500 19055 1c001d36 e69ff06f jal x0, -408 + 19073500 19058 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19088500 19073 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19089500 19074 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19092500 19077 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19093500 19078 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19094500 19079 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19096500 19081 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19097500 19082 1c001778 fddff06f jal x0, -36 + 19099500 19084 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19100500 19085 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19101500 19086 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19102500 19087 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19103500 19088 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19104500 19089 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19105500 19090 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19106500 19091 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19107500 19092 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19108500 19093 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104138 + 19112500 19097 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19113500 19098 1c001bca 16a0006f jal x0, 362 + 19115500 19100 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19116500 19101 1c001d36 e69ff06f jal x0, -408 + 19119500 19104 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19133500 19118 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19134500 19119 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19137500 19122 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19138500 19123 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19139500 19124 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19141500 19126 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19142500 19127 1c001778 fddff06f jal x0, -36 + 19144500 19129 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19145500 19130 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19146500 19131 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19147500 19132 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19148500 19133 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19149500 19134 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19150500 19135 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19151500 19136 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19152500 19137 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19153500 19138 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104138 + 19157500 19142 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19158500 19143 1c001bca 16a0006f jal x0, 362 + 19160500 19145 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19161500 19146 1c001d36 e69ff06f jal x0, -408 + 19164500 19149 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19199500 19184 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19200500 19185 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19203500 19188 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19204500 19189 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19205500 19190 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19207500 19192 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19208500 19193 1c001778 fddff06f jal x0, -36 + 19210500 19195 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19211500 19196 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19212500 19197 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19213500 19198 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19214500 19199 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19215500 19200 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19216500 19201 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19217500 19202 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19218500 19203 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19219500 19204 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104138 + 19223500 19208 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19224500 19209 1c001bca 16a0006f jal x0, 362 + 19226500 19211 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19227500 19212 1c001d36 e69ff06f jal x0, -408 + 19230500 19215 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19249500 19234 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19250500 19235 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19253500 19238 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19254500 19239 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19255500 19240 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19257500 19242 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19258500 19243 1c001778 fddff06f jal x0, -36 + 19260500 19245 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19261500 19246 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19262500 19247 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19263500 19248 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19264500 19249 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19265500 19250 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19266500 19251 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19267500 19252 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19268500 19253 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19269500 19254 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104138 + 19273500 19258 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19274500 19259 1c001bca 16a0006f jal x0, 362 + 19276500 19261 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19277500 19262 1c001d36 e69ff06f jal x0, -408 + 19280500 19265 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19296500 19281 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19297500 19282 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19300500 19285 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19301500 19286 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19302500 19287 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19304500 19289 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19305500 19290 1c001778 fddff06f jal x0, -36 + 19307500 19292 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19308500 19293 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19309500 19294 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19310500 19295 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19311500 19296 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19312500 19297 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19313500 19298 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19314500 19299 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19315500 19300 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19316500 19301 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104138 + 19320500 19305 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19321500 19306 1c001bca 16a0006f jal x0, 362 + 19323500 19308 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19324500 19309 1c001d36 e69ff06f jal x0, -408 + 19327500 19312 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19347500 19332 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19348500 19333 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19351500 19336 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19352500 19337 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19353500 19338 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19355500 19340 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19356500 19341 1c001778 fddff06f jal x0, -36 + 19358500 19343 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19359500 19344 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19360500 19345 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19361500 19346 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19362500 19347 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19363500 19348 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19364500 19349 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19365500 19350 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19366500 19351 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19367500 19352 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104138 + 19371500 19356 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19372500 19357 1c001bca 16a0006f jal x0, 362 + 19374500 19359 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19375500 19360 1c001d36 e69ff06f jal x0, -408 + 19378500 19363 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19396500 19381 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19397500 19382 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19400500 19385 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19401500 19386 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19402500 19387 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19404500 19389 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19405500 19390 1c001778 fddff06f jal x0, -36 + 19407500 19392 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19408500 19393 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19409500 19394 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19410500 19395 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19411500 19396 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19412500 19397 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19413500 19398 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19414500 19399 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19415500 19400 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19416500 19401 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104138 + 19420500 19405 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19421500 19406 1c001bca 16a0006f jal x0, 362 + 19423500 19408 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19424500 19409 1c001d36 e69ff06f jal x0, -408 + 19427500 19412 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19446500 19431 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19447500 19432 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 19450500 19435 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 19451500 19436 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19452500 19437 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19454500 19439 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 19455500 19440 1c001778 fddff06f jal x0, -36 + 19457500 19442 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19458500 19443 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 19459500 19444 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19460500 19445 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 19461500 19446 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 19462500 19447 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 19463500 19448 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 19464500 19449 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 19465500 19450 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19466500 19451 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104138 + 19470500 19455 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19471500 19456 1c001bca 16a0006f jal x0, 362 + 19473500 19458 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 19474500 19459 1c001d36 e69ff06f jal x0, -408 + 19477500 19462 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 19496500 19481 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 19497500 19482 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 19500500 19485 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 19503500 19488 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:108fff60 PA:108fff64 + 19504500 19489 1c001bd0 00012423 sw x0, 8(x2) x2:108fff60 PA:108fff68 + 19505500 19490 1c001bd2 00010623 sb x0, 12(x2) x2:108fff60 PA:108fff6c + 19506500 19491 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 19507500 19492 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 19513500 19498 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 19514500 19499 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fff60 PA:108fff64 + 19515500 19500 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 19516500 19501 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 19517500 19502 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 19518500 19503 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 19519500 19504 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 19536500 19521 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 19537500 19522 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 19538500 19523 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 19572500 19557 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 19573500 19558 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 19586500 19571 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 19587500 19572 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 19588500 19573 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 19611500 19596 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 19630500 19615 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 19633500 19618 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 19656500 19641 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 19674500 19659 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 19675500 19660 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 19676500 19661 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 19696500 19681 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 19714500 19699 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 19733500 19718 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 19734500 19719 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 19774500 19759 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 19793500 19778 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 19816500 19801 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 19817500 19802 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 19856500 19841 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 19880500 19865 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 19881500 19866 1c001f42 e09ff06f jal x0, -504 + 19901500 19886 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 19902500 19887 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fff60 PA:108fff70 + 19921500 19906 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 19943500 19928 1c001e34 00440c13 addi x24, x8, 4 x24=108fffe8 x8:108fffe4 + 19944500 19929 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:108fffe4 PA:108fffe4 + 19948500 19933 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 19984500 19969 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 20003500 19988 1c001e64 00410593 addi x11, x2, 4 x11=108fff64 x2:108fff60 + 20004500 19989 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20024500 20009 1c0019fe 0105a683 lw x13, 16(x11) x13=108fff78 x11:108fff64 PA:108fff74 + 20041500 20026 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fff64 PA:108fff70 + 20048500 20033 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20049500 20034 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 20083500 20068 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 20084500 20069 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20085500 20070 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20086500 20071 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20089500 20074 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fff64 PA:108fff70 + 20100500 20085 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 20134500 20119 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 20168500 20153 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20199500 20184 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20200500 20185 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 20203500 20188 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20222500 20207 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 20244500 20229 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 20245500 20230 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:108fff78 PA:108fff78 + 20252500 20237 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20253500 20238 1c001a5e 00168693 addi x13, x13, 1 x13=108fff79 x13:108fff78 + 20263500 20248 1c001a60 fb1ff06f jal x0, -80 + 20265500 20250 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20266500 20251 1c001a12 00068023 sb x0, 0(x13) x13:108fff79 PA:108fff79 + 20272500 20257 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20273500 20258 1c001e68 f17ff06f jal x0, -234 + 20292500 20277 1c001d7e 00410613 addi x12, x2, 4 x12=108fff64 x2:108fff60 + 20310500 20295 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20311500 20296 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20312500 20297 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20314500 20299 1c001a62 fe010113 addi x2, x2, -32 x2=108fff40 x2:108fff60 + 20315500 20300 1c001a64 00812c23 sw x8, 24(x2) x8:108fffe4 x2:108fff40 PA:108fff58 + 20316500 20301 1c001a66 01062783 lw x15, 16(x12) x15=108fff78 x12:108fff64 PA:108fff74 + 20317500 20302 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fff64 PA:108fff68 + 20318500 20303 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:108fff40 PA:108fff54 + 20319500 20304 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fff40 PA:108fff50 + 20320500 20305 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fff40 PA:108fff4c + 20337500 20322 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fff40 PA:108fff5c + 20341500 20326 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fff40 PA:108fff48 + 20342500 20327 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20343500 20328 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20344500 20329 1c001a78 00c004b3 add x9, x0, x12 x9=108fff64 x12:108fff64 + 20345500 20330 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=108fff79 x15:108fff78 PA:108fff78 + 20347500 20332 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 20360500 20345 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20361500 20346 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fff64 PA:108fff6c + 20367500 20352 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20370500 20355 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 20384500 20369 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20385500 20370 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20404500 20389 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20405500 20390 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20406500 20391 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20426500 20411 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20427500 20412 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20444500 20429 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20445500 20430 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20446500 20431 1c001b36 f71ff06f jal x0, -144 + 20448500 20433 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fff64 PA:108fff6c + 20455500 20440 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20468500 20453 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 20475500 20460 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 20476500 20461 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 20490500 20475 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 20507500 20492 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 20508500 20493 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 20509500 20494 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 20510500 20495 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fff78 x9:108fff64 PA:108fff74 + 20517500 20502 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=108fff79 x20:108fff78 PA:108fff78 + 20528500 20513 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 20547500 20532 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20564500 20549 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 20566500 20551 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 20567500 20552 1c001778 fddff06f jal x0, -36 + 20569500 20554 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20570500 20555 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 20571500 20556 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20572500 20557 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 20573500 20558 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 20574500 20559 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 20575500 20560 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 20576500 20561 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 20577500 20562 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20578500 20563 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104138 + 20582500 20567 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 20583500 20568 1c001b62 f8bff06f jal x0, -118 + 20585500 20570 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fff7a x20:108fff79 PA:108fff79 + 20592500 20577 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 20593500 20578 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 20595500 20580 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20596500 20581 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 20610500 20595 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fff40 PA:108fff5c + 20617500 20602 1c001b02 01812403 lw x8, 24(x2) x8=108fffe4 x2:108fff40 PA:108fff58 + 20618500 20603 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:108fff40 PA:108fff54 + 20619500 20604 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fff40 PA:108fff50 + 20620500 20605 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fff40 PA:108fff4c + 20621500 20606 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fff40 PA:108fff48 + 20622500 20607 1c001b0c 02010113 addi x2, x2, 32 x2=108fff60 x2:108fff40 + 20623500 20608 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 20636500 20621 1c001d86 01800433 add x8, x0, x24 x8=108fffe8 x24:108fffe8 + 20637500 20622 1c001d88 fadff06f jal x0, -84 + 20639500 20624 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 20640500 20625 1c001d36 e69ff06f jal x0, -408 + 20643500 20628 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 20678500 20663 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 20679500 20664 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 20682500 20667 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 20683500 20668 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20684500 20669 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20686500 20671 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 20687500 20672 1c001778 fddff06f jal x0, -36 + 20689500 20674 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20690500 20675 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 20691500 20676 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20692500 20677 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 20693500 20678 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 20694500 20679 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 20695500 20680 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 20696500 20681 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 20697500 20682 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20698500 20683 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104138 + 20702500 20687 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20703500 20688 1c001bca 16a0006f jal x0, 362 + 20705500 20690 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 20706500 20691 1c001d36 e69ff06f jal x0, -408 + 20709500 20694 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 20725500 20710 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 20726500 20711 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 20729500 20714 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 20730500 20715 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20731500 20716 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20733500 20718 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 20734500 20719 1c001778 fddff06f jal x0, -36 + 20736500 20721 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20737500 20722 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 20738500 20723 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20739500 20724 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 20740500 20725 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 20741500 20726 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 20742500 20727 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 20743500 20728 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 20744500 20729 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20745500 20730 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104138 + 20749500 20734 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20750500 20735 1c001bca 16a0006f jal x0, 362 + 20752500 20737 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 20753500 20738 1c001d36 e69ff06f jal x0, -408 + 20756500 20741 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 20770500 20755 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 20771500 20756 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20774500 20759 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20777500 20762 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:108fff60 PA:108fff64 + 20778500 20763 1c001bd0 00012423 sw x0, 8(x2) x2:108fff60 PA:108fff68 + 20779500 20764 1c001bd2 00010623 sb x0, 12(x2) x2:108fff60 PA:108fff6c + 20780500 20765 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 20781500 20766 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20782500 20767 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20783500 20768 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:108fff60 PA:108fff64 + 20784500 20769 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20785500 20770 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20786500 20771 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20787500 20772 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20788500 20773 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20789500 20774 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20790500 20775 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20791500 20776 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 20806500 20791 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 20807500 20792 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20810500 20795 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20811500 20796 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20812500 20797 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20815500 20800 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20818500 20803 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20821500 20806 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20824500 20809 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20825500 20810 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20826500 20811 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20827500 20812 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20830500 20815 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20831500 20816 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20834500 20819 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20835500 20820 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20838500 20823 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20840500 20825 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20843500 20828 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20844500 20829 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20847500 20832 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 20848500 20833 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20849500 20834 1c001f42 e09ff06f jal x0, -504 + 20851500 20836 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20852500 20837 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:108fff60 PA:108fff70 + 20853500 20838 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20856500 20841 1c001e34 00440c13 addi x24, x8, 4 x24=108fffec x8:108fffe8 + 20857500 20842 1c001e38 00042503 lw x10, 0(x8) x10=00000007 x8:108fffe8 PA:108fffe8 + 20858500 20843 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20861500 20846 1c001e54 00055863 bge x10, x0, 16 x10:00000007 + 20864500 20849 1c001e64 00410593 addi x11, x2, 4 x11=108fff64 x2:108fff60 + 20865500 20850 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20867500 20852 1c0019fe 0105a683 lw x13, 16(x11) x13=108fff78 x11:108fff64 PA:108fff74 + 20868500 20853 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fff64 PA:108fff70 + 20869500 20854 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20870500 20855 1c001a04 02f55633 divu x12, x10, x15 x12=00000007 x10:00000007 x15:00000001 + 20904500 20889 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000007 x14:0000000a + 20905500 20890 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20906500 20891 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20907500 20892 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20910500 20895 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:108fff64 PA:108fff70 + 20911500 20896 1c001a20 02f55833 divu x16, x10, x15 x16=00000007 x10:00000007 x15:00000001 + 20945500 20930 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000007 x15:00000001 + 20979500 20964 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21010500 20995 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21011500 20996 1c001a2e 01004663 blt x0, x16, 12 x16:00000007 + 21014500 20999 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21016500 21001 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000007 + 21019500 21004 1c001a56 01070733 add x14, x14, x16 x14=00000037 x14:00000030 x16:00000007 + 21020500 21005 1c001a58 00e68023 sb x14, 0(x13) x14:00000037 x13:108fff78 PA:108fff78 + 21021500 21006 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21022500 21007 1c001a5e 00168693 addi x13, x13, 1 x13=108fff79 x13:108fff78 + 21023500 21008 1c001a60 fb1ff06f jal x0, -80 + 21025500 21010 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21026500 21011 1c001a12 00068023 sb x0, 0(x13) x13:108fff79 PA:108fff79 + 21027500 21012 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21029500 21014 1c001e68 f17ff06f jal x0, -234 + 21031500 21016 1c001d7e 00410613 addi x12, x2, 4 x12=108fff64 x2:108fff60 + 21032500 21017 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21033500 21018 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21034500 21019 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21036500 21021 1c001a62 fe010113 addi x2, x2, -32 x2=108fff40 x2:108fff60 + 21037500 21022 1c001a64 00812c23 sw x8, 24(x2) x8:108fffe8 x2:108fff40 PA:108fff58 + 21038500 21023 1c001a66 01062783 lw x15, 16(x12) x15=108fff78 x12:108fff64 PA:108fff74 + 21039500 21024 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:108fff64 PA:108fff68 + 21040500 21025 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:108fff40 PA:108fff54 + 21041500 21026 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:108fff40 PA:108fff50 + 21042500 21027 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:108fff40 PA:108fff4c + 21043500 21028 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:108fff40 PA:108fff5c + 21044500 21029 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:108fff40 PA:108fff48 + 21046500 21031 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21047500 21032 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21048500 21033 1c001a78 00c004b3 add x9, x0, x12 x9=108fff64 x12:108fff64 + 21049500 21034 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000037 x15=108fff79 x15:108fff78 PA:108fff78 + 21051500 21036 1c001a7e 00070363 beq x14, x0, 6 x14:00000037 + 21052500 21037 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21053500 21038 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:108fff64 PA:108fff6c + 21055500 21040 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21058500 21043 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 21060500 21045 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21061500 21046 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21064500 21049 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21065500 21050 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21066500 21051 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21069500 21054 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21070500 21055 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21071500 21056 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21072500 21057 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21073500 21058 1c001b36 f71ff06f jal x0, -144 + 21075500 21060 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:108fff64 PA:108fff6c + 21077500 21062 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21080500 21065 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 21083500 21068 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21084500 21069 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21087500 21072 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 21088500 21073 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21089500 21074 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21090500 21075 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21091500 21076 1c001ae8 0104aa03 lw x20, 16(x9) x20=108fff78 x9:108fff64 PA:108fff74 + 21093500 21078 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000037 x20=108fff79 x20:108fff78 PA:108fff78 + 21095500 21080 1c001af0 06059763 bne x11, x0, 110 x11:00000037 + 21098500 21083 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21099500 21084 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21101500 21086 1c001776 00b00533 add x10, x0, x11 x10=00000037 x11:00000037 + 21102500 21087 1c001778 fddff06f jal x0, -36 + 21104500 21089 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21105500 21090 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 21106500 21091 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21107500 21092 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 21108500 21093 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 21109500 21094 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 21110500 21095 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 21111500 21096 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 21112500 21097 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21113500 21098 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000037 x14:1a104000 PA:1a104138 + 21117500 21102 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21118500 21103 1c001b62 f8bff06f jal x0, -118 + 21120500 21105 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=108fff7a x20:108fff79 PA:108fff79 + 21122500 21107 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21123500 21108 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:108fff64 PA:108fff64 + 21125500 21110 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21126500 21111 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21129500 21114 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:108fff40 PA:108fff5c + 21130500 21115 1c001b02 01812403 lw x8, 24(x2) x8=108fffe8 x2:108fff40 PA:108fff58 + 21131500 21116 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:108fff40 PA:108fff54 + 21132500 21117 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:108fff40 PA:108fff50 + 21133500 21118 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:108fff40 PA:108fff4c + 21134500 21119 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:108fff40 PA:108fff48 + 21135500 21120 1c001b0c 02010113 addi x2, x2, 32 x2=108fff60 x2:108fff40 + 21136500 21121 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21138500 21123 1c001d86 01800433 add x8, x0, x24 x8=108fffec x24:108fffec + 21139500 21124 1c001d88 fadff06f jal x0, -84 + 21141500 21126 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21142500 21127 1c001d36 e69ff06f jal x0, -408 + 21145500 21130 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21162500 21147 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21163500 21148 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21166500 21151 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21167500 21152 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21168500 21153 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21170500 21155 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21171500 21156 1c001778 fddff06f jal x0, -36 + 21173500 21158 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21174500 21159 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 21175500 21160 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21176500 21161 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 21177500 21162 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 21178500 21163 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 21179500 21164 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 21180500 21165 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 21181500 21166 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21182500 21167 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104138 + 21186500 21171 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21187500 21172 1c001bca 16a0006f jal x0, 362 + 21189500 21174 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21190500 21175 1c001d36 e69ff06f jal x0, -408 + 21193500 21178 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21219500 21204 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21220500 21205 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21223500 21208 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21224500 21209 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21225500 21210 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21227500 21212 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21228500 21213 1c001778 fddff06f jal x0, -36 + 21230500 21215 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21231500 21216 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 21232500 21217 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21233500 21218 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 21234500 21219 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 21235500 21220 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 21236500 21221 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 21237500 21222 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 21238500 21223 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21239500 21224 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104138 + 21243500 21228 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21244500 21229 1c001bca 16a0006f jal x0, 362 + 21246500 21231 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21247500 21232 1c001d36 e69ff06f jal x0, -408 + 21250500 21235 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21264500 21249 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21265500 21250 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21268500 21253 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21269500 21254 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21270500 21255 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21272500 21257 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21273500 21258 1c001778 fddff06f jal x0, -36 + 21275500 21260 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21276500 21261 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000047 + 21277500 21262 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21278500 21263 1c00175e 00379713 slli x14, x15, 0x3 x14=00000238 x15:00000047 + 21279500 21264 1c001762 00279793 slli x15, x15, 0x2 x15=0000011c x15:00000047 + 21280500 21265 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000238 + 21281500 21266 1c001768 00d7f7b3 and x15, x15, x13 x15=00000100 x15:0000011c x13:00001f80 + 21282500 21267 1c00176a 00e787b3 add x15, x15, x14 x15=00000138 x15:00000100 x14:00000038 + 21283500 21268 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21284500 21269 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104138 + 21288500 21273 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21289500 21274 1c001bca 16a0006f jal x0, 362 + 21291500 21276 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21292500 21277 1c001d36 e69ff06f jal x0, -408 + 21295500 21280 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21312500 21297 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21313500 21298 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21314500 21299 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:108fff60 PA:108fffbc + 21315500 21300 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:108fff60 PA:108fffb8 + 21316500 21301 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:108fff60 PA:108fffb4 + 21317500 21302 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:108fff60 PA:108fffb0 + 21318500 21303 1c001bb0 04c12983 lw x19, 76(x2) x19=00000007 x2:108fff60 PA:108fffac + 21319500 21304 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:108fff60 PA:108fffa8 + 21320500 21305 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:108fff60 PA:108fffa4 + 21321500 21306 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:108fff60 PA:108fffa0 + 21322500 21307 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:108fff60 PA:108fff9c + 21324500 21309 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:108fff60 PA:108fff98 + 21325500 21310 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:108fff60 PA:108fff94 + 21326500 21311 1c001bbe 06010113 addi x2, x2, 96 x2=108fffc0 x2:108fff60 + 21327500 21312 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21329500 21314 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:108fffc0 PA:108fffdc + 21330500 21315 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21331500 21316 1c001838 04010113 addi x2, x2, 64 x2=10900000 x2:108fffc0 + 21332500 21317 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21334500 21319 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_0.log b/sw/scripts/tracevis/example/traces/trace_core_03_0.log new file mode 100644 index 0000000..568444f --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_0.log @@ -0,0 +1,921 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000060 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000000 x10:00000060 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000060 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000000 + 17054500 17039 1c0000aa 00050463 beq x10, x0, 8 x10:00000003 + 17073500 17058 1c0000ae 0520206f jal x0, 8274 + 17075500 17060 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17076500 17061 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17077500 17062 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17078500 17063 1c00210c 0e059163 bne x11, x0, 226 x11:00000000 + 17090500 17075 1c002110 feffe417 auipc x8, 0xfeffe000 x8=1b000110 + 17091500 17076 1c002114 ef840413 addi x8, x8, -264 x8=1b000008 x8:1b000110 + 17092500 17077 1c002118 04040493 addi x9, x8, 64 x9=1b000048 x8:1b000008 + 17093500 17078 1c00211c 00800933 add x18, x0, x8 x18=1b000008 x8:1b000008 + 17110500 17095 1c00211e 1b2049b7 lui x19, 0x1b204000 x19=1b204000 + 17111500 17096 1c002122 00200a13 addi x20, x0, 2 x20=00000002 + 17112500 17097 1c002124 00000a97 auipc x21, 0x0 x21=1c002124 + 17113500 17098 1c002128 036a8a93 addi x21, x21, 54 x21=1c00215a x21:1c002124 + 17114500 17099 1c00212c 00000b97 auipc x23, 0x0 x23=1c00212c + 17131500 17116 1c002130 57cb8b93 addi x23, x23, 1404 x23=1c0026a8 x23:1c00212c + 17132500 17117 1c002134 000bab83 lw x23, 0(x23) x23=1c2fff50 x23:1c0026a8 PA:1c0026a8 + 17146500 17131 1c002138 01800393 addi x7, x0, 24 x7=00000018 + 17147500 17132 1c00213a 02a383b3 mul x7, x7, x10 x7=00000048 x7:00000018 x10:00000003 + 17148500 17133 1c00213e 007b8bb3 add x23, x23, x7 x23=1c2fff98 x23:1c2fff50 x7:00000048 + 17165500 17150 1c002140 008b8b93 addi x23, x23, 8 x23=1c2fffa0 x23:1c2fff98 + 17166500 17151 1c002142 10201cb7 lui x25, 0x10201000 x25=10201000 + 17167500 17152 1c002146 e04c8c93 addi x25, x25, -508 x25=10200e04 x25:10201000 + 17168500 17153 1c00214a 00100c13 addi x24, x0, 1 x24=00000001 + 17169500 17154 1c00214c 00000d17 auipc x26, 0x0 x26=1c00214c + 17186500 17171 1c002150 0e0d0d13 addi x26, x26, 224 x26=1c00222c x26:1c00214c + 17187500 17172 1c002154 001d6d13 ori x26, x26, 1 x26=1c00222d x26:1c00222c + 17188500 17173 1c002158 0160006f jal x0, 22 + 17223500 17208 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000008 PA:1b000008 + 17225500 17210 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 17244500 17229 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 + 17245500 17230 1c0021d6 03c9e003 p.elw x0, 60(x19) x19:1b204000 PA:1b20403c + 18702500 18687 1c0021da 0149a223 sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004 + 18703500 18688 1c0021de f91ff06f jal x0, -112 + 18706500 18691 1c00216e 00042e03 lw x28, 0(x8) x28=00000008 x8:1b000008 PA:1b000008 + 18708500 18693 1c002172 060e0063 beq x28, x0, 96 x28:00000008 + 18709500 18694 1c002176 00842503 lw x10, 8(x8) x10=00000000 x8:1b000008 PA:1b000010 + 18710500 18695 1c002178 00442283 lw x5, 4(x8) x5=1c0009d8 x8:1b000008 PA:1b00000c + 18711500 18696 1c00217c 00c42103 lw x2, 12(x8) x2=10cfe400 x8:1b000008 PA:1b000014 + 18732500 18717 1c002180 01042303 lw x6, 16(x8) x6=00000400 x8:1b000008 PA:1b000018 + 18733500 18718 1c002184 01442383 lw x7, 20(x8) x7=00000400 x8:1b000008 PA:1b00001c + 18734500 18719 1c002188 01842b03 lw x22, 24(x8) x22=100fc720 x8:1b000008 PA:1b000020 + 18735500 18720 1c00218c 01c42e83 lw x29, 28(x8) x29=1000013c x8:1b000008 PA:1b000024 + 18753500 18738 1c002190 00042023 sw x0, 0(x8) x8:1b000008 PA:1b000008 + 18754500 18739 1c002194 feffef17 auipc x30, 0xfeffe000 x30=1b000194 + 18755500 18740 1c002198 eb4f0f13 addi x30, x30, -332 x30=1b000048 x30:1b000194 + 18756500 18741 1c00219c 01df2023 sw x29, 0(x30) x29:1000013c x30:1b000048 PA:1b000048 + 18776500 18761 1c0021a0 015000b3 add x1, x0, x21 x1=1c00215a x21:1c00215a + 18777500 18762 1c0021a2 00100e93 addi x29, x0, 1 x29=00000001 + 18778500 18763 1c0021a4 01ce9e33 sll x28, x29, x28 x28=00000100 x29:00000001 x28:00000008 + 18779500 18764 1c0021a8 fffe0e13 addi x28, x28, -1 x28=000000ff x28:00000100 + 18780500 18765 1c0021aa 21c9a023 sw x28, 512(x19) x28:000000ff x19:1b204000 PA:1b204200 + 18806500 18791 1c0021ae 21c9a623 sw x28, 524(x19) x28:000000ff x19:1b204000 PA:1b20420c + 18807500 18792 1c0021b2 09c9a223 sw x28, 132(x19) x28:000000ff x19:1b204000 PA:1b204084 + 18808500 18793 1c0021b6 001e2863 p.beqimm x28, 16 x28:000000ff + 18809500 18794 1c0021ba 09a9a023 sw x26, 128(x19) x26:1c00222d x19:1b204000 PA:1b204080 + 18828500 18813 1c0021be 0879a023 sw x7, 128(x19) x7:00000400 x19:1b204000 PA:1b204080 + 18829500 18814 1c0021c2 0829a023 sw x2, 128(x19) x2:10cfe400 x19:1b204000 PA:1b204080 + 18830500 18815 1c0021c6 02040413 addi x8, x8, 32 x8=1b000028 x8:1b000008 + 18831500 18816 1c0021ca 00941363 bne x8, x9, 6 x8:1b000028 x9:1b000048 + 18834500 18819 1c0021d0 00028067 jalr x0, x5, 0 x5:1c0009d8 + 18852500 18837 1c0009d8 ff010113 addi x2, x2, -16 x2=10cfe3f0 x2:10cfe400 + 18853500 18838 1c0009da 0ff00713 addi x14, x0, 255 x14=000000ff + 18873500 18858 1c0009de 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 18874500 18859 1c0009e2 00112623 sw x1, 12(x2) x1:1c00215a x2:10cfe3f0 PA:10cfe3fc + 18875500 18860 1c0009e4 00812423 sw x8, 8(x2) x8:1b000028 x2:10cfe3f0 PA:10cfe3f8 + 18876500 18861 1c0009e6 00912223 sw x9, 4(x2) x9:1b000048 x2:10cfe3f0 PA:10cfe3f4 + 18877500 18862 1c0009e8 08e7a223 sw x14, 132(x15) x14:000000ff x15:1b204000 PA:1b204084 + 18878500 18863 1c0009ec 20078493 addi x9, x15, 512 x9=1b204200 x15:1b204000 + 18901500 18886 1c0009f0 00e4a023 sw x14, 0(x9) x14:000000ff x9:1b204200 PA:1b204200 + 18902500 18887 1c0009f2 20c78793 addi x15, x15, 524 x15=1b20420c x15:1b204000 + 18903500 18888 1c0009f6 00e7a023 sw x14, 0(x15) x14:000000ff x15:1b20420c PA:1b20420c + 18904500 18889 1c0009f8 1c0017b7 lui x15, 0x1c001000 x15=1c001000 + 18905500 18890 1c0009fc 9bc78793 addi x15, x15, -1604 x15=1c0009bc x15:1c001000 + 18927500 18912 1c000a00 1b204737 lui x14, 0x1b204000 x14=1b204000 + 18928500 18913 1c000a04 08f72023 sw x15, 128(x14) x15:1c0009bc x14:1b204000 PA:1b204080 + 18929500 18914 1c000a08 1b2047b7 lui x15, 0x1b204000 x15=1b204000 + 18930500 18915 1c000a0c 08a7a023 sw x10, 128(x15) x10:00000000 x15:1b204000 PA:1b204080 + 18950500 18935 1c000a10 f1402673 csrrs x12, x0, 0xf14 x12=00000060 + 18951500 18936 1c000a14 40565413 srai x8, x12, 0x405 x8=00000003 x12:00000060 + 18952500 18937 1c000a18 f2643433 p.bclr x8, x8, 25, 6 x8=00000003 x8:00000003 + 18953500 18938 1c000a1c 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18970500 18955 1c000a20 f4563633 p.bclr x12, x12, 26, 5 x12=00000000 x12:00000060 + 18971500 18956 1c000a24 008005b3 add x11, x0, x8 x11=00000003 x8:00000003 + 18972500 18957 1c000a26 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18973500 18958 1c000a2a 5e7000ef jal x1, 3558 x1=1c000a2e + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cfe3b0 x2:10cfe3f0 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cfe3b0 PA:10cfe3d4 + 19022500 19007 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19023500 19008 1c001818 02c12423 sw x12, 40(x2) x12:00000000 x2:10cfe3b0 PA:10cfe3d8 + 19024500 19009 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cfe3b0 PA:10cfe3dc + 19025500 19010 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19026500 19011 1c00181e 02410693 addi x13, x2, 36 x13=10cfe3d4 x2:10cfe3b0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c000a2e x2:10cfe3b0 PA:10cfe3cc + 19048500 19033 1c001828 02e12823 sw x14, 48(x2) x14:1b204000 x2:10cfe3b0 PA:10cfe3e0 + 19049500 19034 1c00182a 02f12a23 sw x15, 52(x2) x15:1b204000 x2:10cfe3b0 PA:10cfe3e4 + 19050500 19035 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cfe3b0 PA:10cfe3e8 + 19051500 19036 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cfe3b0 PA:10cfe3ec + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cfe3d4 x2:10cfe3b0 PA:10cfe3bc + 19073500 19058 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cfe350 x2:10cfe3b0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cfe368 x2:10cfe350 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000003 x2:10cfe350 PA:10cfe3a8 + 19095500 19080 1c001b76 05212823 sw x18, 80(x2) x18:1b000008 x2:10cfe350 PA:10cfe3a0 + 19096500 19081 1c001b78 05312623 sw x19, 76(x2) x19:1b204000 x2:10cfe350 PA:10cfe39c + 19097500 19082 1c001b7a 05412423 sw x20, 72(x2) x20:00000002 x2:10cfe350 PA:10cfe398 + 19098500 19083 1c001b7c 05512223 sw x21, 68(x2) x21:1c00215a x2:10cfe350 PA:10cfe394 + 19099500 19084 1c001b7e 05612023 sw x22, 64(x2) x22:100fc720 x2:10cfe350 PA:10cfe390 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:1c2fffa0 x2:10cfe350 PA:10cfe38c + 19116500 19101 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cfe350 PA:10cfe3ac + 19117500 19102 1c001b84 04912a23 sw x9, 84(x2) x9:1b204200 x2:10cfe350 PA:10cfe3a4 + 19118500 19103 1c001b86 03812c23 sw x24, 56(x2) x24:00000001 x2:10cfe350 PA:10cfe388 + 19119500 19104 1c001b88 03912a23 sw x25, 52(x2) x25:10200e04 x2:10cfe350 PA:10cfe384 + 19120500 19105 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19121500 19106 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19122500 19107 1c001b8e 00d00433 add x8, x0, x13 x8=10cfe3d4 x13:10cfe3d4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cfe368 x2:10cfe350 PA:10cfe364 + 19139500 19124 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19140500 19125 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19141500 19126 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19142500 19127 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19213500 19198 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19214500 19199 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19226500 19211 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19227500 19212 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19228500 19213 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104180 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19376500 19361 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19377500 19362 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19380500 19365 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19381500 19366 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19382500 19367 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19384500 19369 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19385500 19370 1c001778 fddff06f jal x0, -36 + 19387500 19372 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19388500 19373 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19389500 19374 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19390500 19375 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19391500 19376 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19392500 19377 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19393500 19378 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19394500 19379 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19395500 19380 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19396500 19381 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104180 + 19400500 19385 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19401500 19386 1c001bca 16a0006f jal x0, 362 + 19403500 19388 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19404500 19389 1c001d36 e69ff06f jal x0, -408 + 19407500 19392 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19428500 19413 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19429500 19414 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19432500 19417 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19433500 19418 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19434500 19419 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19436500 19421 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19437500 19422 1c001778 fddff06f jal x0, -36 + 19439500 19424 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19440500 19425 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19441500 19426 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19442500 19427 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19443500 19428 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19444500 19429 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19445500 19430 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19446500 19431 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19447500 19432 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19448500 19433 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104180 + 19452500 19437 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19453500 19438 1c001bca 16a0006f jal x0, 362 + 19455500 19440 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19456500 19441 1c001d36 e69ff06f jal x0, -408 + 19459500 19444 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19488500 19473 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19489500 19474 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19492500 19477 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19493500 19478 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19494500 19479 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19496500 19481 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19497500 19482 1c001778 fddff06f jal x0, -36 + 19499500 19484 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19500500 19485 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19501500 19486 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19502500 19487 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19503500 19488 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19504500 19489 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19505500 19490 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19506500 19491 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19507500 19492 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19508500 19493 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104180 + 19512500 19497 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19513500 19498 1c001bca 16a0006f jal x0, 362 + 19515500 19500 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19516500 19501 1c001d36 e69ff06f jal x0, -408 + 19519500 19504 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19535500 19520 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19536500 19521 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19539500 19524 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19540500 19525 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19541500 19526 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19543500 19528 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19544500 19529 1c001778 fddff06f jal x0, -36 + 19546500 19531 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19547500 19532 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19548500 19533 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19549500 19534 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19550500 19535 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19551500 19536 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19552500 19537 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19553500 19538 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19554500 19539 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19555500 19540 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104180 + 19559500 19544 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19560500 19545 1c001bca 16a0006f jal x0, 362 + 19562500 19547 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19563500 19548 1c001d36 e69ff06f jal x0, -408 + 19566500 19551 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19605500 19590 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19606500 19591 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19609500 19594 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19610500 19595 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19611500 19596 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19613500 19598 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19614500 19599 1c001778 fddff06f jal x0, -36 + 19616500 19601 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19617500 19602 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19618500 19603 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19619500 19604 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19620500 19605 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19621500 19606 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19622500 19607 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19623500 19608 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19624500 19609 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19625500 19610 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104180 + 19629500 19614 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19630500 19615 1c001bca 16a0006f jal x0, 362 + 19632500 19617 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19633500 19618 1c001d36 e69ff06f jal x0, -408 + 19636500 19621 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19654500 19639 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19655500 19640 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19658500 19643 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19659500 19644 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19660500 19645 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19662500 19647 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19663500 19648 1c001778 fddff06f jal x0, -36 + 19665500 19650 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19666500 19651 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19667500 19652 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19668500 19653 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19669500 19654 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19670500 19655 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19671500 19656 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19672500 19657 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19673500 19658 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19674500 19659 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104180 + 19678500 19663 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19679500 19664 1c001bca 16a0006f jal x0, 362 + 19681500 19666 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19682500 19667 1c001d36 e69ff06f jal x0, -408 + 19685500 19670 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19700500 19685 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19701500 19686 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19704500 19689 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19705500 19690 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19706500 19691 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19708500 19693 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19709500 19694 1c001778 fddff06f jal x0, -36 + 19711500 19696 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19712500 19697 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19713500 19698 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19714500 19699 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19715500 19700 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19716500 19701 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19717500 19702 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19718500 19703 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19719500 19704 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19720500 19705 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104180 + 19724500 19709 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19725500 19710 1c001bca 16a0006f jal x0, 362 + 19727500 19712 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19728500 19713 1c001d36 e69ff06f jal x0, -408 + 19731500 19716 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19745500 19730 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19746500 19731 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19749500 19734 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19750500 19735 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19751500 19736 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19753500 19738 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19754500 19739 1c001778 fddff06f jal x0, -36 + 19756500 19741 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19757500 19742 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19758500 19743 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19759500 19744 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19760500 19745 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19761500 19746 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19762500 19747 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19763500 19748 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19764500 19749 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19765500 19750 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104180 + 19769500 19754 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19770500 19755 1c001bca 16a0006f jal x0, 362 + 19772500 19757 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19773500 19758 1c001d36 e69ff06f jal x0, -408 + 19776500 19761 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19792500 19777 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19793500 19778 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19796500 19781 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19797500 19782 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19798500 19783 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19800500 19785 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19801500 19786 1c001778 fddff06f jal x0, -36 + 19803500 19788 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19804500 19789 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19805500 19790 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19806500 19791 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19807500 19792 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19808500 19793 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19809500 19794 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19810500 19795 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19811500 19796 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19812500 19797 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104180 + 19816500 19801 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19817500 19802 1c001bca 16a0006f jal x0, 362 + 19819500 19804 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19820500 19805 1c001d36 e69ff06f jal x0, -408 + 19823500 19808 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19838500 19823 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19839500 19824 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19842500 19827 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19843500 19828 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19844500 19829 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19846500 19831 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19847500 19832 1c001778 fddff06f jal x0, -36 + 19849500 19834 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19850500 19835 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19851500 19836 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19852500 19837 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19853500 19838 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19854500 19839 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19855500 19840 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19856500 19841 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19857500 19842 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19858500 19843 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104180 + 19862500 19847 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19863500 19848 1c001bca 16a0006f jal x0, 362 + 19865500 19850 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19866500 19851 1c001d36 e69ff06f jal x0, -408 + 19869500 19854 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19885500 19870 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19886500 19871 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19889500 19874 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19890500 19875 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19891500 19876 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19893500 19878 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19894500 19879 1c001778 fddff06f jal x0, -36 + 19896500 19881 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19897500 19882 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19898500 19883 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19899500 19884 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19900500 19885 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19901500 19886 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19902500 19887 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19903500 19888 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19904500 19889 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19905500 19890 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104180 + 19909500 19894 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19910500 19895 1c001bca 16a0006f jal x0, 362 + 19912500 19897 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19913500 19898 1c001d36 e69ff06f jal x0, -408 + 19916500 19901 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19930500 19915 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19931500 19916 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19934500 19919 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19935500 19920 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19936500 19921 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19938500 19923 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19939500 19924 1c001778 fddff06f jal x0, -36 + 19941500 19926 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19942500 19927 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19943500 19928 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19944500 19929 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19945500 19930 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19946500 19931 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19947500 19932 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19948500 19933 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19949500 19934 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19950500 19935 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104180 + 19954500 19939 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19955500 19940 1c001bca 16a0006f jal x0, 362 + 19957500 19942 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19958500 19943 1c001d36 e69ff06f jal x0, -408 + 19961500 19946 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19975500 19960 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19976500 19961 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19979500 19964 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19980500 19965 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19981500 19966 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19983500 19968 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19984500 19969 1c001778 fddff06f jal x0, -36 + 19986500 19971 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19987500 19972 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 19988500 19973 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19989500 19974 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 19990500 19975 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 19991500 19976 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 19992500 19977 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 19993500 19978 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 19994500 19979 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19995500 19980 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104180 + 19999500 19984 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20000500 19985 1c001bca 16a0006f jal x0, 362 + 20002500 19987 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 20003500 19988 1c001d36 e69ff06f jal x0, -408 + 20006500 19991 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 20023500 20008 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 20024500 20009 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20027500 20012 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20028500 20013 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20029500 20014 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20031500 20016 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20032500 20017 1c001778 fddff06f jal x0, -36 + 20034500 20019 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20035500 20020 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 20036500 20021 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20037500 20022 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 20038500 20023 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 20039500 20024 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 20040500 20025 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 20041500 20026 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 20042500 20027 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20043500 20028 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104180 + 20047500 20032 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20048500 20033 1c001bca 16a0006f jal x0, 362 + 20050500 20035 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20051500 20036 1c001d36 e69ff06f jal x0, -408 + 20054500 20039 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20072500 20057 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20073500 20058 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20076500 20061 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20079500 20064 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cfe350 PA:10cfe354 + 20080500 20065 1c001bd0 00012423 sw x0, 8(x2) x2:10cfe350 PA:10cfe358 + 20081500 20066 1c001bd2 00010623 sb x0, 12(x2) x2:10cfe350 PA:10cfe35c + 20082500 20067 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20083500 20068 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20091500 20076 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20092500 20077 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfe350 PA:10cfe354 + 20093500 20078 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20094500 20079 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20095500 20080 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20096500 20081 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20097500 20082 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20113500 20098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20114500 20099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20115500 20100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20145500 20130 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20146500 20131 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20156500 20141 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20157500 20142 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20158500 20143 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfe350 PA:10cfe360 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cfe3d8 x8:10cfe3d4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cfe3d4 PA:10cfe3d4 + 20485500 20470 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cfe354 x2:10cfe350 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfe368 x11:10cfe354 PA:10cfe364 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe354 PA:10cfe360 + 20575500 20560 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20576500 20561 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20610500 20595 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20611500 20596 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20612500 20597 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20613500 20598 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20616500 20601 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe354 PA:10cfe360 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cfe368 PA:10cfe368 + 20782500 20767 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20783500 20768 1c001a5e 00168693 addi x13, x13, 1 x13=10cfe369 x13:10cfe368 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cfe369 PA:10cfe369 + 20804500 20789 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20806500 20791 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cfe354 x2:10cfe350 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cfe330 x2:10cfe350 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cfe3d4 x2:10cfe330 PA:10cfe348 + 20848500 20833 1c001a66 01062783 lw x15, 16(x12) x15=10cfe368 x12:10cfe354 PA:10cfe364 + 20849500 20834 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfe354 PA:10cfe358 + 20850500 20835 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cfe330 PA:10cfe344 + 20851500 20836 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfe330 PA:10cfe340 + 20852500 20837 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfe330 PA:10cfe33c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfe330 PA:10cfe34c + 20869500 20854 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfe330 PA:10cfe338 + 20870500 20855 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20871500 20856 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20872500 20857 1c001a78 00c004b3 add x9, x0, x12 x9=10cfe354 x12:10cfe354 + 20873500 20858 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cfe369 x15:10cfe368 PA:10cfe368 + 20875500 20860 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfe354 PA:10cfe35c + 20895500 20880 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20898500 20883 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfe354 PA:10cfe35c + 20981500 20966 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 21001500 20986 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21002500 20987 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfe368 x9:10cfe354 PA:10cfe364 + 21043500 21028 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cfe369 x20:10cfe368 PA:10cfe368 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104180 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfe36a x20:10cfe369 PA:10cfe369 + 21124500 21109 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21125500 21110 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 21127500 21112 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21128500 21113 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfe330 PA:10cfe34c + 21156500 21141 1c001b02 01812403 lw x8, 24(x2) x8=10cfe3d4 x2:10cfe330 PA:10cfe348 + 21157500 21142 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cfe330 PA:10cfe344 + 21158500 21143 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfe330 PA:10cfe340 + 21159500 21144 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfe330 PA:10cfe33c + 21160500 21145 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfe330 PA:10cfe338 + 21161500 21146 1c001b0c 02010113 addi x2, x2, 32 x2=10cfe350 x2:10cfe330 + 21162500 21147 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cfe3d8 x24:10cfe3d8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21224500 21209 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21225500 21210 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21228500 21213 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21229500 21214 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21230500 21215 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21232500 21217 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21233500 21218 1c001778 fddff06f jal x0, -36 + 21235500 21220 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21236500 21221 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 21237500 21222 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21238500 21223 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 21239500 21224 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 21240500 21225 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 21241500 21226 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 21242500 21227 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 21243500 21228 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21244500 21229 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104180 + 21248500 21233 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21249500 21234 1c001bca 16a0006f jal x0, 362 + 21251500 21236 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21252500 21237 1c001d36 e69ff06f jal x0, -408 + 21255500 21240 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21270500 21255 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21271500 21256 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21274500 21259 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21275500 21260 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21276500 21261 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21278500 21263 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21279500 21264 1c001778 fddff06f jal x0, -36 + 21281500 21266 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21282500 21267 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 21283500 21268 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21284500 21269 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 21285500 21270 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 21286500 21271 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 21287500 21272 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 21288500 21273 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 21289500 21274 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21290500 21275 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104180 + 21294500 21279 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21295500 21280 1c001bca 16a0006f jal x0, 362 + 21297500 21282 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21298500 21283 1c001d36 e69ff06f jal x0, -408 + 21301500 21286 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21317500 21302 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21318500 21303 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21321500 21306 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21324500 21309 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cfe350 PA:10cfe354 + 21325500 21310 1c001bd0 00012423 sw x0, 8(x2) x2:10cfe350 PA:10cfe358 + 21326500 21311 1c001bd2 00010623 sb x0, 12(x2) x2:10cfe350 PA:10cfe35c + 21327500 21312 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21328500 21313 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21329500 21314 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21330500 21315 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfe350 PA:10cfe354 + 21331500 21316 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21332500 21317 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21333500 21318 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21334500 21319 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21335500 21320 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21336500 21321 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21337500 21322 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21338500 21323 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21353500 21338 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21354500 21339 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21357500 21342 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21358500 21343 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21359500 21344 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21362500 21347 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21365500 21350 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21368500 21353 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21371500 21356 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21372500 21357 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21373500 21358 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21374500 21359 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21377500 21362 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21378500 21363 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21381500 21366 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21382500 21367 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21385500 21370 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21387500 21372 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21390500 21375 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21391500 21376 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21394500 21379 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21395500 21380 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21396500 21381 1c001f42 e09ff06f jal x0, -504 + 21398500 21383 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21399500 21384 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfe350 PA:10cfe360 + 21400500 21385 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21403500 21388 1c001e34 00440c13 addi x24, x8, 4 x24=10cfe3dc x8:10cfe3d8 + 21404500 21389 1c001e38 00042503 lw x10, 0(x8) x10=00000000 x8:10cfe3d8 PA:10cfe3d8 + 21405500 21390 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21408500 21393 1c001e54 00055863 bge x10, x0, 16 x10:00000000 + 21411500 21396 1c001e64 00410593 addi x11, x2, 4 x11=10cfe354 x2:10cfe350 + 21412500 21397 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21414500 21399 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfe368 x11:10cfe354 PA:10cfe364 + 21415500 21400 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe354 PA:10cfe360 + 21416500 21401 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21417500 21402 1c001a04 02f55633 divu x12, x10, x15 x12=00000000 x10:00000000 x15:00000001 + 21451500 21436 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000000 x14:0000000a + 21452500 21437 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21453500 21438 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21454500 21439 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21457500 21442 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe354 PA:10cfe360 + 21458500 21443 1c001a20 02f55833 divu x16, x10, x15 x16=00000000 x10:00000000 x15:00000001 + 21492500 21477 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000000 x15:00000001 + 21526500 21511 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21557500 21542 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21558500 21543 1c001a2e 01004663 blt x0, x16, 12 x16:00000000 + 21559500 21544 1c001a32 fc079fe3 bne x15, x0, -34 x15:00000000 + 21560500 21545 1c001a34 03000713 addi x14, x0, 48 x14=00000030 + 21561500 21546 1c001a38 01e0006f jal x0, 30 + 21563500 21548 1c001a56 01070733 add x14, x14, x16 x14=00000030 x14:00000030 x16:00000000 + 21564500 21549 1c001a58 00e68023 sb x14, 0(x13) x14:00000030 x13:10cfe368 PA:10cfe368 + 21566500 21551 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21567500 21552 1c001a5e 00168693 addi x13, x13, 1 x13=10cfe369 x13:10cfe368 + 21568500 21553 1c001a60 fb1ff06f jal x0, -80 + 21570500 21555 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21571500 21556 1c001a12 00068023 sb x0, 0(x13) x13:10cfe369 PA:10cfe369 + 21572500 21557 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21574500 21559 1c001e68 f17ff06f jal x0, -234 + 21576500 21561 1c001d7e 00410613 addi x12, x2, 4 x12=10cfe354 x2:10cfe350 + 21577500 21562 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21578500 21563 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21579500 21564 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21581500 21566 1c001a62 fe010113 addi x2, x2, -32 x2=10cfe330 x2:10cfe350 + 21582500 21567 1c001a64 00812c23 sw x8, 24(x2) x8:10cfe3d8 x2:10cfe330 PA:10cfe348 + 21583500 21568 1c001a66 01062783 lw x15, 16(x12) x15=10cfe368 x12:10cfe354 PA:10cfe364 + 21584500 21569 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfe354 PA:10cfe358 + 21585500 21570 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cfe330 PA:10cfe344 + 21586500 21571 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfe330 PA:10cfe340 + 21587500 21572 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfe330 PA:10cfe33c + 21588500 21573 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfe330 PA:10cfe34c + 21589500 21574 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfe330 PA:10cfe338 + 21590500 21575 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21591500 21576 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21592500 21577 1c001a78 00c004b3 add x9, x0, x12 x9=10cfe354 x12:10cfe354 + 21593500 21578 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000030 x15=10cfe369 x15:10cfe368 PA:10cfe368 + 21595500 21580 1c001a7e 00070363 beq x14, x0, 6 x14:00000030 + 21596500 21581 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21597500 21582 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfe354 PA:10cfe35c + 21599500 21584 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21602500 21587 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 21604500 21589 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21605500 21590 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21608500 21593 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21609500 21594 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21610500 21595 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21613500 21598 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21614500 21599 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21615500 21600 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21616500 21601 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21617500 21602 1c001b36 f71ff06f jal x0, -144 + 21619500 21604 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfe354 PA:10cfe35c + 21621500 21606 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21624500 21609 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 21626500 21611 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21627500 21612 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21630500 21615 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 21631500 21616 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21632500 21617 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21633500 21618 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21634500 21619 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfe368 x9:10cfe354 PA:10cfe364 + 21636500 21621 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000030 x20=10cfe369 x20:10cfe368 PA:10cfe368 + 21638500 21623 1c001af0 06059763 bne x11, x0, 110 x11:00000030 + 21641500 21626 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21642500 21627 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21644500 21629 1c001776 00b00533 add x10, x0, x11 x10=00000030 x11:00000030 + 21645500 21630 1c001778 fddff06f jal x0, -36 + 21647500 21632 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21648500 21633 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 21649500 21634 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21650500 21635 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 21651500 21636 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 21652500 21637 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 21653500 21638 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 21654500 21639 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 21655500 21640 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21656500 21641 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000030 x14:1a104000 PA:1a104180 + 21660500 21645 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21661500 21646 1c001b62 f8bff06f jal x0, -118 + 21663500 21648 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfe36a x20:10cfe369 PA:10cfe369 + 21665500 21650 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21666500 21651 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe354 PA:10cfe354 + 21668500 21653 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21669500 21654 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21672500 21657 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfe330 PA:10cfe34c + 21673500 21658 1c001b02 01812403 lw x8, 24(x2) x8=10cfe3d8 x2:10cfe330 PA:10cfe348 + 21674500 21659 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cfe330 PA:10cfe344 + 21675500 21660 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfe330 PA:10cfe340 + 21676500 21661 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfe330 PA:10cfe33c + 21677500 21662 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfe330 PA:10cfe338 + 21678500 21663 1c001b0c 02010113 addi x2, x2, 32 x2=10cfe350 x2:10cfe330 + 21679500 21664 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21681500 21666 1c001d86 01800433 add x8, x0, x24 x8=10cfe3dc x24:10cfe3dc + 21682500 21667 1c001d88 fadff06f jal x0, -84 + 21684500 21669 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21685500 21670 1c001d36 e69ff06f jal x0, -408 + 21688500 21673 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21702500 21687 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21703500 21688 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21706500 21691 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21707500 21692 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21708500 21693 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21710500 21695 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21711500 21696 1c001778 fddff06f jal x0, -36 + 21713500 21698 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21714500 21699 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 21715500 21700 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21716500 21701 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 21717500 21702 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 21718500 21703 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 21719500 21704 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 21720500 21705 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 21721500 21706 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21722500 21707 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104180 + 21726500 21711 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21727500 21712 1c001bca 16a0006f jal x0, 362 + 21729500 21714 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21730500 21715 1c001d36 e69ff06f jal x0, -408 + 21733500 21718 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21747500 21732 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21748500 21733 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21751500 21736 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21752500 21737 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21753500 21738 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21755500 21740 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21756500 21741 1c001778 fddff06f jal x0, -36 + 21758500 21743 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21759500 21744 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 21760500 21745 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21761500 21746 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 21762500 21747 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 21763500 21748 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 21764500 21749 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 21765500 21750 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 21766500 21751 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21767500 21752 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104180 + 21771500 21756 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21772500 21757 1c001bca 16a0006f jal x0, 362 + 21774500 21759 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21775500 21760 1c001d36 e69ff06f jal x0, -408 + 21778500 21763 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21792500 21777 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21793500 21778 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21796500 21781 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21797500 21782 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21798500 21783 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21800500 21785 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21801500 21786 1c001778 fddff06f jal x0, -36 + 21803500 21788 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21804500 21789 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000060 + 21805500 21790 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21806500 21791 1c00175e 00379713 slli x14, x15, 0x3 x14=00000300 x15:00000060 + 21807500 21792 1c001762 00279793 slli x15, x15, 0x2 x15=00000180 x15:00000060 + 21808500 21793 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000000 x14:00000300 + 21809500 21794 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000180 x13:00001f80 + 21810500 21795 1c00176a 00e787b3 add x15, x15, x14 x15=00000180 x15:00000180 x14:00000000 + 21811500 21796 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21812500 21797 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104180 + 21816500 21801 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21817500 21802 1c001bca 16a0006f jal x0, 362 + 21819500 21804 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21820500 21805 1c001d36 e69ff06f jal x0, -408 + 21823500 21808 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21840500 21825 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21841500 21826 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21842500 21827 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cfe350 PA:10cfe3ac + 21846500 21831 1c001baa 05812403 lw x8, 88(x2) x8=00000003 x2:10cfe350 PA:10cfe3a8 + 21847500 21832 1c001bac 05412483 lw x9, 84(x2) x9=1b204200 x2:10cfe350 PA:10cfe3a4 + 21848500 21833 1c001bae 05012903 lw x18, 80(x2) x18=1b000008 x2:10cfe350 PA:10cfe3a0 + 21849500 21834 1c001bb0 04c12983 lw x19, 76(x2) x19=1b204000 x2:10cfe350 PA:10cfe39c + 21850500 21835 1c001bb2 04812a03 lw x20, 72(x2) x20=00000002 x2:10cfe350 PA:10cfe398 + 21851500 21836 1c001bb4 04412a83 lw x21, 68(x2) x21=1c00215a x2:10cfe350 PA:10cfe394 + 21852500 21837 1c001bb6 04012b03 lw x22, 64(x2) x22=100fc720 x2:10cfe350 PA:10cfe390 + 21853500 21838 1c001bb8 03c12b83 lw x23, 60(x2) x23=1c2fffa0 x2:10cfe350 PA:10cfe38c + 21854500 21839 1c001bba 03812c03 lw x24, 56(x2) x24=00000001 x2:10cfe350 PA:10cfe388 + 21855500 21840 1c001bbc 03412c83 lw x25, 52(x2) x25=10200e04 x2:10cfe350 PA:10cfe384 + 21856500 21841 1c001bbe 06010113 addi x2, x2, 96 x2=10cfe3b0 x2:10cfe350 + 21857500 21842 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21859500 21844 1c001834 01c12083 lw x1, 28(x2) x1=1c000a2e x2:10cfe3b0 PA:10cfe3cc + 21860500 21845 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21861500 21846 1c001838 04010113 addi x2, x2, 64 x2=10cfe3f0 x2:10cfe3b0 + 21862500 21847 1c00183a 00008067 jalr x0, x1, 0 x1:1c000a2e + 21865500 21850 1c000a2e 01c4e783 p.elw x15, 28(x9) x15=00000000 x9:1b204200 PA:1b20421c + 21877500 21862 1c000a32 1c0027b7 lui x15, 0x1c002000 x15=1c002000 + 21878500 21863 1c000a36 00241413 slli x8, x8, 0x2 x8=0000000c x8:00000003 + 21879500 21864 1c000a38 68478793 addi x15, x15, 1668 x15=1c002684 x15:1c002000 + 21880500 21865 1c000a3c 00100713 addi x14, x0, 1 x14=00000001 + 21897500 21882 1c000a3e 00e7e423 p.sw x14, x0(x15) x14:00000001 x15:1c002684 PA:1c002690 + 21915500 21900 1c000a42 00c12083 lw x1, 12(x2) x1=1c00215a x2:10cfe3f0 PA:10cfe3fc + 21916500 21901 1c000a44 00812403 lw x8, 8(x2) x8=1b000028 x2:10cfe3f0 PA:10cfe3f8 + 21917500 21902 1c000a46 00412483 lw x9, 4(x2) x9=1b000048 x2:10cfe3f0 PA:10cfe3f4 + 21918500 21903 1c000a48 01010113 addi x2, x2, 16 x2=10cfe400 x2:10cfe3f0 + 21919500 21904 1c000a4a 00008067 jalr x0, x1, 0 x1:1c00215a + 21921500 21906 1c00215a 000b0a63 beq x22, x0, 20 x22:100fc720 + 21923500 21908 1c00215e 000ba283 lw x5, 0(x23) x5=00000000 x23:1c2fffa0 PA:1c2fffa0 + 21938500 21923 1c002162 06029f63 bne x5, x0, 126 x5:00000000 + 21939500 21924 1c002166 016ba023 sw x22, 0(x23) x22:100fc720 x23:1c2fffa0 PA:1c2fffa0 + 21957500 21942 1c00216a 018ca023 sw x24, 0(x25) x24:00000001 x25:10200e04 PA:10200e04 + 21961500 21946 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028 + 21963500 21948 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 21966500 21951 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 + 21967500 21952 1c0021d6 03c9e003 p.elw x0, 60(x19) x19:1b204000 PA:1b20403c + 21972500 21957 1c0021da 0149a223 sw x20, 4(x19) x20:00000002 x19:1b204000 PA:1b204004 + 21973500 21958 1c0021de f91ff06f jal x0, -112 + 21976500 21961 1c00216e 00042e03 lw x28, 0(x8) x28=00000000 x8:1b000028 PA:1b000028 + 21978500 21963 1c002172 060e0063 beq x28, x0, 96 x28:00000000 + 21981500 21966 1c0021d2 0149a423 sw x20, 8(x19) x20:00000002 x19:1b204000 PA:1b204008 diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_1.log b/sw/scripts/tracevis/example/traces/trace_core_03_1.log new file mode 100644 index 0000000..2630855 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_1.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000061 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000001 x10:00000061 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000061 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000001 + 17052500 17037 1c0000a6 05a0206f jal x0, 8282 + 17070500 17055 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17071500 17056 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17072500 17057 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17073500 17058 1c00210c 0e059163 bne x11, x0, 226 x11:00000001 + 17125500 17110 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 17126500 17111 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000061 + 17127500 17112 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000001 x19:00000061 + 17128500 17113 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 17147500 17132 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 17148500 17133 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 17149500 17134 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 17150500 17135 1c00220a 0060006f jal x0, 6 + 17169500 17154 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18817500 18802 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18836500 18821 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18837500 18822 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18862500 18847 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18863500 18848 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18865500 18850 1c00222c 08096283 p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080 + 18895500 18880 1c002230 02a98533 mul x10, x19, x10 x10=00000400 x19:00000001 x10:00000400 + 18896500 18881 1c002234 00550133 add x2, x10, x5 x2=10cfe800 x10:00000400 x5:10cfe400 + 18897500 18882 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18899500 18884 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18936500 18921 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18944500 18929 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18945500 18930 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18946500 18931 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18947500 18932 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18965500 18950 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000061 + 18986500 18971 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18987500 18972 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000003 x12:00000061 + 18988500 18973 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003 + 18989500 18974 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000001 x12:00000061 + 18990500 18975 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18991500 18976 1c0009d4 63d0006f jal x0, 3644 + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cfe7c0 x2:10cfe800 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cfe7c0 PA:10cfe7e4 + 19025500 19010 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19026500 19011 1c001818 02c12423 sw x12, 40(x2) x12:00000001 x2:10cfe7c0 PA:10cfe7e8 + 19027500 19012 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cfe7c0 PA:10cfe7ec + 19028500 19013 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19029500 19014 1c00181e 02410693 addi x13, x2, 36 x13=10cfe7e4 x2:10cfe7c0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:10cfe7c0 PA:10cfe7dc + 19050500 19035 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:10cfe7c0 PA:10cfe7f0 + 19051500 19036 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:10cfe7c0 PA:10cfe7f4 + 19052500 19037 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cfe7c0 PA:10cfe7f8 + 19053500 19038 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cfe7c0 PA:10cfe7fc + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cfe7e4 x2:10cfe7c0 PA:10cfe7cc + 19074500 19059 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cfe760 x2:10cfe7c0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cfe778 x2:10cfe760 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:10cfe760 PA:10cfe7b8 + 19101500 19086 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:10cfe760 PA:10cfe7b0 + 19102500 19087 1c001b78 05312623 sw x19, 76(x2) x19:00000001 x2:10cfe760 PA:10cfe7ac + 19103500 19088 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:10cfe760 PA:10cfe7a8 + 19104500 19089 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:10cfe760 PA:10cfe7a4 + 19105500 19090 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:10cfe760 PA:10cfe7a0 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:10cfe760 PA:10cfe79c + 19118500 19103 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cfe760 PA:10cfe7bc + 19119500 19104 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:10cfe760 PA:10cfe7b4 + 19120500 19105 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:10cfe760 PA:10cfe798 + 19121500 19106 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:10cfe760 PA:10cfe794 + 19122500 19107 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19123500 19108 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19124500 19109 1c001b8e 00d00433 add x8, x0, x13 x8=10cfe7e4 x13:10cfe7e4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cfe778 x2:10cfe760 PA:10cfe774 + 19139500 19124 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19140500 19125 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19141500 19126 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19142500 19127 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19183500 19168 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19184500 19169 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19226500 19211 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19227500 19212 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19228500 19213 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104188 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19350500 19335 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19351500 19336 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19354500 19339 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19355500 19340 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19356500 19341 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19358500 19343 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19359500 19344 1c001778 fddff06f jal x0, -36 + 19361500 19346 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19362500 19347 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19363500 19348 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19364500 19349 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19365500 19350 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19366500 19351 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19367500 19352 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19368500 19353 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19369500 19354 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19370500 19355 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104188 + 19374500 19359 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19375500 19360 1c001bca 16a0006f jal x0, 362 + 19377500 19362 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19378500 19363 1c001d36 e69ff06f jal x0, -408 + 19381500 19366 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19404500 19389 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19405500 19390 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19408500 19393 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19409500 19394 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19410500 19395 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19412500 19397 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19413500 19398 1c001778 fddff06f jal x0, -36 + 19415500 19400 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19416500 19401 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19417500 19402 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19418500 19403 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19419500 19404 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19420500 19405 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19421500 19406 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19422500 19407 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19423500 19408 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19424500 19409 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104188 + 19428500 19413 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19429500 19414 1c001bca 16a0006f jal x0, 362 + 19431500 19416 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19432500 19417 1c001d36 e69ff06f jal x0, -408 + 19435500 19420 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19457500 19442 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19458500 19443 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19461500 19446 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19462500 19447 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19463500 19448 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19465500 19450 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19466500 19451 1c001778 fddff06f jal x0, -36 + 19468500 19453 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19469500 19454 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19470500 19455 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19471500 19456 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19472500 19457 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19473500 19458 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19474500 19459 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19475500 19460 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19476500 19461 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19477500 19462 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104188 + 19481500 19466 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19482500 19467 1c001bca 16a0006f jal x0, 362 + 19484500 19469 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19485500 19470 1c001d36 e69ff06f jal x0, -408 + 19488500 19473 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19508500 19493 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19509500 19494 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19512500 19497 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19513500 19498 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19514500 19499 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19516500 19501 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19517500 19502 1c001778 fddff06f jal x0, -36 + 19519500 19504 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19520500 19505 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19521500 19506 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19522500 19507 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19523500 19508 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19524500 19509 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19525500 19510 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19526500 19511 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19527500 19512 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19528500 19513 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104188 + 19532500 19517 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19533500 19518 1c001bca 16a0006f jal x0, 362 + 19535500 19520 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19536500 19521 1c001d36 e69ff06f jal x0, -408 + 19539500 19524 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19565500 19550 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19566500 19551 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19569500 19554 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19570500 19555 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19571500 19556 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19573500 19558 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19574500 19559 1c001778 fddff06f jal x0, -36 + 19576500 19561 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19577500 19562 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19578500 19563 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19579500 19564 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19580500 19565 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19581500 19566 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19582500 19567 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19583500 19568 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19584500 19569 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19585500 19570 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104188 + 19589500 19574 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19590500 19575 1c001bca 16a0006f jal x0, 362 + 19592500 19577 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19593500 19578 1c001d36 e69ff06f jal x0, -408 + 19596500 19581 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19614500 19599 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19615500 19600 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19618500 19603 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19619500 19604 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19620500 19605 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19622500 19607 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19623500 19608 1c001778 fddff06f jal x0, -36 + 19625500 19610 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19626500 19611 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19627500 19612 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19628500 19613 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19629500 19614 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19630500 19615 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19631500 19616 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19632500 19617 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19633500 19618 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19634500 19619 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104188 + 19638500 19623 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19639500 19624 1c001bca 16a0006f jal x0, 362 + 19641500 19626 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19642500 19627 1c001d36 e69ff06f jal x0, -408 + 19645500 19630 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19661500 19646 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19662500 19647 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19665500 19650 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19666500 19651 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19667500 19652 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19669500 19654 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19670500 19655 1c001778 fddff06f jal x0, -36 + 19672500 19657 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19673500 19658 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19674500 19659 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19675500 19660 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19676500 19661 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19677500 19662 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19678500 19663 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19679500 19664 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19680500 19665 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19681500 19666 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104188 + 19685500 19670 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19686500 19671 1c001bca 16a0006f jal x0, 362 + 19688500 19673 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19689500 19674 1c001d36 e69ff06f jal x0, -408 + 19692500 19677 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19708500 19693 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19709500 19694 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19712500 19697 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19713500 19698 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19714500 19699 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19716500 19701 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19717500 19702 1c001778 fddff06f jal x0, -36 + 19719500 19704 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19720500 19705 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19721500 19706 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19722500 19707 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19723500 19708 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19724500 19709 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19725500 19710 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19726500 19711 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19727500 19712 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19728500 19713 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104188 + 19732500 19717 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19733500 19718 1c001bca 16a0006f jal x0, 362 + 19735500 19720 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19736500 19721 1c001d36 e69ff06f jal x0, -408 + 19739500 19724 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19756500 19741 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19757500 19742 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19760500 19745 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19761500 19746 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19762500 19747 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19764500 19749 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19765500 19750 1c001778 fddff06f jal x0, -36 + 19767500 19752 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19768500 19753 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19769500 19754 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19770500 19755 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19771500 19756 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19772500 19757 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19773500 19758 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19774500 19759 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19775500 19760 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19776500 19761 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104188 + 19780500 19765 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19781500 19766 1c001bca 16a0006f jal x0, 362 + 19783500 19768 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19784500 19769 1c001d36 e69ff06f jal x0, -408 + 19787500 19772 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19805500 19790 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19806500 19791 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19809500 19794 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19810500 19795 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19811500 19796 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19813500 19798 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19814500 19799 1c001778 fddff06f jal x0, -36 + 19816500 19801 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19817500 19802 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19818500 19803 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19819500 19804 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19820500 19805 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19821500 19806 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19822500 19807 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19823500 19808 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19824500 19809 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19825500 19810 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104188 + 19829500 19814 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19830500 19815 1c001bca 16a0006f jal x0, 362 + 19832500 19817 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19833500 19818 1c001d36 e69ff06f jal x0, -408 + 19836500 19821 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19851500 19836 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19852500 19837 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19855500 19840 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19856500 19841 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19857500 19842 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19859500 19844 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19860500 19845 1c001778 fddff06f jal x0, -36 + 19862500 19847 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19863500 19848 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19864500 19849 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19865500 19850 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19866500 19851 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19867500 19852 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19868500 19853 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19869500 19854 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19870500 19855 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19871500 19856 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104188 + 19875500 19860 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19876500 19861 1c001bca 16a0006f jal x0, 362 + 19878500 19863 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19879500 19864 1c001d36 e69ff06f jal x0, -408 + 19882500 19867 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19897500 19882 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19898500 19883 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19901500 19886 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19902500 19887 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19903500 19888 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19905500 19890 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19906500 19891 1c001778 fddff06f jal x0, -36 + 19908500 19893 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19909500 19894 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19910500 19895 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19911500 19896 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19912500 19897 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19913500 19898 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19914500 19899 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19915500 19900 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19916500 19901 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19917500 19902 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104188 + 19921500 19906 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19922500 19907 1c001bca 16a0006f jal x0, 362 + 19924500 19909 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19925500 19910 1c001d36 e69ff06f jal x0, -408 + 19928500 19913 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19952500 19937 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19953500 19938 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19956500 19941 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19957500 19942 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19958500 19943 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19960500 19945 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19961500 19946 1c001778 fddff06f jal x0, -36 + 19963500 19948 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19964500 19949 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 19965500 19950 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19966500 19951 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 19967500 19952 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 19968500 19953 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 19969500 19954 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 19970500 19955 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 19971500 19956 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19972500 19957 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104188 + 19976500 19961 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19977500 19962 1c001bca 16a0006f jal x0, 362 + 19979500 19964 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19980500 19965 1c001d36 e69ff06f jal x0, -408 + 19983500 19968 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 19998500 19983 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 19999500 19984 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20002500 19987 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20003500 19988 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20004500 19989 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20006500 19991 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20007500 19992 1c001778 fddff06f jal x0, -36 + 20009500 19994 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20010500 19995 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 20011500 19996 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20012500 19997 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 20013500 19998 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 20014500 19999 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 20015500 20000 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 20016500 20001 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 20017500 20002 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20018500 20003 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104188 + 20022500 20007 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20023500 20008 1c001bca 16a0006f jal x0, 362 + 20025500 20010 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20026500 20011 1c001d36 e69ff06f jal x0, -408 + 20029500 20014 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20043500 20028 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20044500 20029 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20047500 20032 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20050500 20035 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cfe760 PA:10cfe764 + 20069500 20054 1c001bd0 00012423 sw x0, 8(x2) x2:10cfe760 PA:10cfe768 + 20071500 20056 1c001bd2 00010623 sb x0, 12(x2) x2:10cfe760 PA:10cfe76c + 20072500 20057 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20073500 20058 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20091500 20076 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20092500 20077 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfe760 PA:10cfe764 + 20094500 20079 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20095500 20080 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20096500 20081 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20097500 20082 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20098500 20083 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20113500 20098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20114500 20099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20115500 20100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20130500 20115 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20135500 20120 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20156500 20141 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20157500 20142 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20158500 20143 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfe760 PA:10cfe770 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cfe7e8 x8:10cfe7e4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cfe7e4 PA:10cfe7e4 + 20485500 20470 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cfe764 x2:10cfe760 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfe778 x11:10cfe764 PA:10cfe774 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe764 PA:10cfe770 + 20575500 20560 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20576500 20561 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20610500 20595 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20611500 20596 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20612500 20597 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20613500 20598 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20616500 20601 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe764 PA:10cfe770 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cfe778 PA:10cfe778 + 20782500 20767 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20783500 20768 1c001a5e 00168693 addi x13, x13, 1 x13=10cfe779 x13:10cfe778 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cfe779 PA:10cfe779 + 20810500 20795 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20811500 20796 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cfe764 x2:10cfe760 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cfe740 x2:10cfe760 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cfe7e4 x2:10cfe740 PA:10cfe758 + 20849500 20834 1c001a66 01062783 lw x15, 16(x12) x15=10cfe778 x12:10cfe764 PA:10cfe774 + 20850500 20835 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfe764 PA:10cfe768 + 20851500 20836 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cfe740 PA:10cfe754 + 20852500 20837 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfe740 PA:10cfe750 + 20853500 20838 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfe740 PA:10cfe74c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfe740 PA:10cfe75c + 20869500 20854 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfe740 PA:10cfe748 + 20870500 20855 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20871500 20856 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20872500 20857 1c001a78 00c004b3 add x9, x0, x12 x9=10cfe764 x12:10cfe764 + 20873500 20858 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cfe779 x15:10cfe778 PA:10cfe778 + 20875500 20860 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfe764 PA:10cfe76c + 20900500 20885 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20903500 20888 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfe764 PA:10cfe76c + 20985500 20970 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 21007500 20992 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21008500 20993 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfe778 x9:10cfe764 PA:10cfe774 + 21049500 21034 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cfe779 x20:10cfe778 PA:10cfe778 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104188 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfe77a x20:10cfe779 PA:10cfe779 + 21128500 21113 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21129500 21114 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 21131500 21116 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21132500 21117 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfe740 PA:10cfe75c + 21156500 21141 1c001b02 01812403 lw x8, 24(x2) x8=10cfe7e4 x2:10cfe740 PA:10cfe758 + 21157500 21142 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cfe740 PA:10cfe754 + 21158500 21143 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfe740 PA:10cfe750 + 21159500 21144 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfe740 PA:10cfe74c + 21160500 21145 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfe740 PA:10cfe748 + 21161500 21146 1c001b0c 02010113 addi x2, x2, 32 x2=10cfe760 x2:10cfe740 + 21162500 21147 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cfe7e8 x24:10cfe7e8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21201500 21186 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21202500 21187 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21205500 21190 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21206500 21191 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21207500 21192 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21209500 21194 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21210500 21195 1c001778 fddff06f jal x0, -36 + 21212500 21197 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21213500 21198 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 21214500 21199 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21215500 21200 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 21216500 21201 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 21217500 21202 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 21218500 21203 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 21219500 21204 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 21220500 21205 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21221500 21206 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104188 + 21225500 21210 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21226500 21211 1c001bca 16a0006f jal x0, 362 + 21228500 21213 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21229500 21214 1c001d36 e69ff06f jal x0, -408 + 21232500 21217 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21246500 21231 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21247500 21232 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21250500 21235 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21251500 21236 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21252500 21237 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21254500 21239 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21255500 21240 1c001778 fddff06f jal x0, -36 + 21257500 21242 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21258500 21243 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 21259500 21244 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21260500 21245 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 21261500 21246 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 21262500 21247 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 21263500 21248 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 21264500 21249 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 21265500 21250 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21266500 21251 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104188 + 21270500 21255 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21271500 21256 1c001bca 16a0006f jal x0, 362 + 21273500 21258 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21274500 21259 1c001d36 e69ff06f jal x0, -408 + 21277500 21262 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21291500 21276 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21292500 21277 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21295500 21280 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21298500 21283 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cfe760 PA:10cfe764 + 21299500 21284 1c001bd0 00012423 sw x0, 8(x2) x2:10cfe760 PA:10cfe768 + 21300500 21285 1c001bd2 00010623 sb x0, 12(x2) x2:10cfe760 PA:10cfe76c + 21301500 21286 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21302500 21287 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21303500 21288 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21304500 21289 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfe760 PA:10cfe764 + 21305500 21290 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21306500 21291 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21307500 21292 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21308500 21293 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21309500 21294 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21310500 21295 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21311500 21296 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21312500 21297 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21326500 21311 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21327500 21312 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21330500 21315 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21331500 21316 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21332500 21317 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21335500 21320 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21338500 21323 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21341500 21326 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21344500 21329 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21345500 21330 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21346500 21331 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21347500 21332 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21350500 21335 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21351500 21336 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21354500 21339 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21355500 21340 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21358500 21343 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21360500 21345 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21363500 21348 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21364500 21349 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21367500 21352 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21368500 21353 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21369500 21354 1c001f42 e09ff06f jal x0, -504 + 21371500 21356 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21372500 21357 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfe760 PA:10cfe770 + 21373500 21358 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21376500 21361 1c001e34 00440c13 addi x24, x8, 4 x24=10cfe7ec x8:10cfe7e8 + 21377500 21362 1c001e38 00042503 lw x10, 0(x8) x10=00000001 x8:10cfe7e8 PA:10cfe7e8 + 21378500 21363 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21381500 21366 1c001e54 00055863 bge x10, x0, 16 x10:00000001 + 21384500 21369 1c001e64 00410593 addi x11, x2, 4 x11=10cfe764 x2:10cfe760 + 21385500 21370 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21387500 21372 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfe778 x11:10cfe764 PA:10cfe774 + 21388500 21373 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe764 PA:10cfe770 + 21389500 21374 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21390500 21375 1c001a04 02f55633 divu x12, x10, x15 x12=00000001 x10:00000001 x15:00000001 + 21424500 21409 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000001 x14:0000000a + 21425500 21410 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21426500 21411 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21427500 21412 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21430500 21415 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfe764 PA:10cfe770 + 21431500 21416 1c001a20 02f55833 divu x16, x10, x15 x16=00000001 x10:00000001 x15:00000001 + 21465500 21450 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000001 x15:00000001 + 21499500 21484 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21530500 21515 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21531500 21516 1c001a2e 01004663 blt x0, x16, 12 x16:00000001 + 21534500 21519 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21536500 21521 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000001 + 21539500 21524 1c001a56 01070733 add x14, x14, x16 x14=00000031 x14:00000030 x16:00000001 + 21540500 21525 1c001a58 00e68023 sb x14, 0(x13) x14:00000031 x13:10cfe778 PA:10cfe778 + 21541500 21526 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21542500 21527 1c001a5e 00168693 addi x13, x13, 1 x13=10cfe779 x13:10cfe778 + 21543500 21528 1c001a60 fb1ff06f jal x0, -80 + 21545500 21530 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21546500 21531 1c001a12 00068023 sb x0, 0(x13) x13:10cfe779 PA:10cfe779 + 21547500 21532 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21549500 21534 1c001e68 f17ff06f jal x0, -234 + 21551500 21536 1c001d7e 00410613 addi x12, x2, 4 x12=10cfe764 x2:10cfe760 + 21552500 21537 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21553500 21538 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21554500 21539 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21556500 21541 1c001a62 fe010113 addi x2, x2, -32 x2=10cfe740 x2:10cfe760 + 21557500 21542 1c001a64 00812c23 sw x8, 24(x2) x8:10cfe7e8 x2:10cfe740 PA:10cfe758 + 21558500 21543 1c001a66 01062783 lw x15, 16(x12) x15=10cfe778 x12:10cfe764 PA:10cfe774 + 21559500 21544 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfe764 PA:10cfe768 + 21560500 21545 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cfe740 PA:10cfe754 + 21561500 21546 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfe740 PA:10cfe750 + 21562500 21547 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfe740 PA:10cfe74c + 21563500 21548 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfe740 PA:10cfe75c + 21564500 21549 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfe740 PA:10cfe748 + 21565500 21550 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21566500 21551 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21567500 21552 1c001a78 00c004b3 add x9, x0, x12 x9=10cfe764 x12:10cfe764 + 21568500 21553 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000031 x15=10cfe779 x15:10cfe778 PA:10cfe778 + 21570500 21555 1c001a7e 00070363 beq x14, x0, 6 x14:00000031 + 21571500 21556 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21572500 21557 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfe764 PA:10cfe76c + 21574500 21559 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21577500 21562 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 21579500 21564 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21580500 21565 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21583500 21568 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21584500 21569 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21585500 21570 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21588500 21573 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21589500 21574 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21590500 21575 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21591500 21576 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21592500 21577 1c001b36 f71ff06f jal x0, -144 + 21594500 21579 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfe764 PA:10cfe76c + 21596500 21581 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21599500 21584 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 21601500 21586 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21602500 21587 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21605500 21590 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 21608500 21593 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21609500 21594 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21610500 21595 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21611500 21596 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfe778 x9:10cfe764 PA:10cfe774 + 21613500 21598 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000031 x20=10cfe779 x20:10cfe778 PA:10cfe778 + 21615500 21600 1c001af0 06059763 bne x11, x0, 110 x11:00000031 + 21618500 21603 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21619500 21604 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21621500 21606 1c001776 00b00533 add x10, x0, x11 x10=00000031 x11:00000031 + 21622500 21607 1c001778 fddff06f jal x0, -36 + 21624500 21609 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21625500 21610 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 21626500 21611 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21627500 21612 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 21628500 21613 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 21629500 21614 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 21630500 21615 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 21631500 21616 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 21632500 21617 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21633500 21618 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000031 x14:1a104000 PA:1a104188 + 21637500 21622 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21638500 21623 1c001b62 f8bff06f jal x0, -118 + 21640500 21625 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfe77a x20:10cfe779 PA:10cfe779 + 21642500 21627 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21643500 21628 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfe764 PA:10cfe764 + 21645500 21630 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21646500 21631 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21649500 21634 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfe740 PA:10cfe75c + 21650500 21635 1c001b02 01812403 lw x8, 24(x2) x8=10cfe7e8 x2:10cfe740 PA:10cfe758 + 21651500 21636 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cfe740 PA:10cfe754 + 21652500 21637 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfe740 PA:10cfe750 + 21653500 21638 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfe740 PA:10cfe74c + 21654500 21639 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfe740 PA:10cfe748 + 21655500 21640 1c001b0c 02010113 addi x2, x2, 32 x2=10cfe760 x2:10cfe740 + 21656500 21641 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21658500 21643 1c001d86 01800433 add x8, x0, x24 x8=10cfe7ec x24:10cfe7ec + 21659500 21644 1c001d88 fadff06f jal x0, -84 + 21661500 21646 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21662500 21647 1c001d36 e69ff06f jal x0, -408 + 21665500 21650 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21681500 21666 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21682500 21667 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21685500 21670 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21686500 21671 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21687500 21672 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21689500 21674 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21690500 21675 1c001778 fddff06f jal x0, -36 + 21692500 21677 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21693500 21678 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 21694500 21679 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21695500 21680 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 21696500 21681 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 21697500 21682 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 21698500 21683 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 21699500 21684 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 21700500 21685 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21701500 21686 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104188 + 21705500 21690 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21706500 21691 1c001bca 16a0006f jal x0, 362 + 21708500 21693 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21709500 21694 1c001d36 e69ff06f jal x0, -408 + 21712500 21697 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21726500 21711 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21727500 21712 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21730500 21715 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21731500 21716 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21732500 21717 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21734500 21719 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21735500 21720 1c001778 fddff06f jal x0, -36 + 21737500 21722 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21738500 21723 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 21739500 21724 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21740500 21725 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 21741500 21726 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 21742500 21727 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 21743500 21728 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 21744500 21729 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 21745500 21730 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21746500 21731 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104188 + 21750500 21735 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21751500 21736 1c001bca 16a0006f jal x0, 362 + 21753500 21738 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21754500 21739 1c001d36 e69ff06f jal x0, -408 + 21757500 21742 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21771500 21756 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21772500 21757 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21775500 21760 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21776500 21761 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21777500 21762 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21779500 21764 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21780500 21765 1c001778 fddff06f jal x0, -36 + 21782500 21767 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21783500 21768 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000061 + 21784500 21769 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21785500 21770 1c00175e 00379713 slli x14, x15, 0x3 x14=00000308 x15:00000061 + 21786500 21771 1c001762 00279793 slli x15, x15, 0x2 x15=00000184 x15:00000061 + 21787500 21772 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000008 x14:00000308 + 21788500 21773 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000184 x13:00001f80 + 21789500 21774 1c00176a 00e787b3 add x15, x15, x14 x15=00000188 x15:00000180 x14:00000008 + 21790500 21775 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21791500 21776 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104188 + 21795500 21780 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21796500 21781 1c001bca 16a0006f jal x0, 362 + 21798500 21783 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21799500 21784 1c001d36 e69ff06f jal x0, -408 + 21802500 21787 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21818500 21803 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21819500 21804 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21820500 21805 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cfe760 PA:10cfe7bc + 21821500 21806 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:10cfe760 PA:10cfe7b8 + 21822500 21807 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:10cfe760 PA:10cfe7b4 + 21823500 21808 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:10cfe760 PA:10cfe7b0 + 21841500 21826 1c001bb0 04c12983 lw x19, 76(x2) x19=00000001 x2:10cfe760 PA:10cfe7ac + 21847500 21832 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:10cfe760 PA:10cfe7a8 + 21848500 21833 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:10cfe760 PA:10cfe7a4 + 21849500 21834 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:10cfe760 PA:10cfe7a0 + 21850500 21835 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:10cfe760 PA:10cfe79c + 21851500 21836 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:10cfe760 PA:10cfe798 + 21852500 21837 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:10cfe760 PA:10cfe794 + 21853500 21838 1c001bbe 06010113 addi x2, x2, 96 x2=10cfe7c0 x2:10cfe760 + 21854500 21839 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21856500 21841 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:10cfe7c0 PA:10cfe7dc + 21857500 21842 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21858500 21843 1c001838 04010113 addi x2, x2, 64 x2=10cfe800 x2:10cfe7c0 + 21859500 21844 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21861500 21846 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_2.log b/sw/scripts/tracevis/example/traces/trace_core_03_2.log new file mode 100644 index 0000000..b809f4c --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_2.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000062 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000002 x10:00000062 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000062 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000002 + 17052500 17037 1c0000a6 05a0206f jal x0, 8282 + 17070500 17055 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17071500 17056 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17072500 17057 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17073500 17058 1c00210c 0e059163 bne x11, x0, 226 x11:00000002 + 17125500 17110 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 17126500 17111 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000062 + 17127500 17112 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000002 x19:00000062 + 17128500 17113 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 17147500 17132 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 17148500 17133 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 17149500 17134 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 17150500 17135 1c00220a 0060006f jal x0, 6 + 17169500 17154 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18817500 18802 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18836500 18821 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18837500 18822 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18862500 18847 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18863500 18848 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18865500 18850 1c00222c 08096283 p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080 + 18895500 18880 1c002230 02a98533 mul x10, x19, x10 x10=00000800 x19:00000002 x10:00000400 + 18896500 18881 1c002234 00550133 add x2, x10, x5 x2=10cfec00 x10:00000800 x5:10cfe400 + 18897500 18882 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18899500 18884 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18936500 18921 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18944500 18929 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18945500 18930 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18946500 18931 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18947500 18932 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18965500 18950 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000062 + 18986500 18971 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18987500 18972 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000003 x12:00000062 + 18988500 18973 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003 + 18989500 18974 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000002 x12:00000062 + 18990500 18975 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18991500 18976 1c0009d4 63d0006f jal x0, 3644 + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cfebc0 x2:10cfec00 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cfebc0 PA:10cfebe4 + 19026500 19011 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19027500 19012 1c001818 02c12423 sw x12, 40(x2) x12:00000002 x2:10cfebc0 PA:10cfebe8 + 19028500 19013 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cfebc0 PA:10cfebec + 19029500 19014 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19030500 19015 1c00181e 02410693 addi x13, x2, 36 x13=10cfebe4 x2:10cfebc0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:10cfebc0 PA:10cfebdc + 19052500 19037 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:10cfebc0 PA:10cfebf0 + 19053500 19038 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:10cfebc0 PA:10cfebf4 + 19054500 19039 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cfebc0 PA:10cfebf8 + 19055500 19040 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cfebc0 PA:10cfebfc + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cfebe4 x2:10cfebc0 PA:10cfebcc + 19076500 19061 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cfeb60 x2:10cfebc0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cfeb78 x2:10cfeb60 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:10cfeb60 PA:10cfebb8 + 19095500 19080 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:10cfeb60 PA:10cfebb0 + 19096500 19081 1c001b78 05312623 sw x19, 76(x2) x19:00000002 x2:10cfeb60 PA:10cfebac + 19097500 19082 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:10cfeb60 PA:10cfeba8 + 19098500 19083 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:10cfeb60 PA:10cfeba4 + 19099500 19084 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:10cfeb60 PA:10cfeba0 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:10cfeb60 PA:10cfeb9c + 19120500 19105 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cfeb60 PA:10cfebbc + 19121500 19106 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:10cfeb60 PA:10cfebb4 + 19122500 19107 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:10cfeb60 PA:10cfeb98 + 19123500 19108 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:10cfeb60 PA:10cfeb94 + 19124500 19109 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19125500 19110 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19126500 19111 1c001b8e 00d00433 add x8, x0, x13 x8=10cfebe4 x13:10cfebe4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cfeb78 x2:10cfeb60 PA:10cfeb74 + 19140500 19125 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19141500 19126 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19142500 19127 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19143500 19128 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19194500 19179 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19195500 19180 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19226500 19211 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19227500 19212 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19228500 19213 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104190 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19354500 19339 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19355500 19340 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19358500 19343 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19359500 19344 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19360500 19345 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19362500 19347 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19363500 19348 1c001778 fddff06f jal x0, -36 + 19365500 19350 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19366500 19351 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19367500 19352 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19368500 19353 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19369500 19354 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19370500 19355 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19371500 19356 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19372500 19357 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19373500 19358 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19374500 19359 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104190 + 19378500 19363 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19379500 19364 1c001bca 16a0006f jal x0, 362 + 19381500 19366 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19382500 19367 1c001d36 e69ff06f jal x0, -408 + 19385500 19370 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19407500 19392 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19408500 19393 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19411500 19396 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19412500 19397 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19413500 19398 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19415500 19400 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19416500 19401 1c001778 fddff06f jal x0, -36 + 19418500 19403 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19419500 19404 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19420500 19405 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19421500 19406 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19422500 19407 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19423500 19408 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19424500 19409 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19425500 19410 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19426500 19411 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19427500 19412 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104190 + 19431500 19416 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19432500 19417 1c001bca 16a0006f jal x0, 362 + 19434500 19419 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19435500 19420 1c001d36 e69ff06f jal x0, -408 + 19438500 19423 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19458500 19443 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19459500 19444 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19462500 19447 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19463500 19448 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19464500 19449 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19466500 19451 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19467500 19452 1c001778 fddff06f jal x0, -36 + 19469500 19454 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19470500 19455 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19471500 19456 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19472500 19457 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19473500 19458 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19474500 19459 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19475500 19460 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19476500 19461 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19477500 19462 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19478500 19463 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104190 + 19482500 19467 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19483500 19468 1c001bca 16a0006f jal x0, 362 + 19485500 19470 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19486500 19471 1c001d36 e69ff06f jal x0, -408 + 19489500 19474 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19514500 19499 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19515500 19500 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19518500 19503 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19519500 19504 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19520500 19505 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19522500 19507 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19523500 19508 1c001778 fddff06f jal x0, -36 + 19525500 19510 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19526500 19511 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19527500 19512 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19528500 19513 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19529500 19514 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19530500 19515 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19531500 19516 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19532500 19517 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19533500 19518 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19534500 19519 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104190 + 19538500 19523 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19539500 19524 1c001bca 16a0006f jal x0, 362 + 19541500 19526 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19542500 19527 1c001d36 e69ff06f jal x0, -408 + 19545500 19530 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19575500 19560 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19576500 19561 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19579500 19564 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19580500 19565 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19581500 19566 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19583500 19568 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19584500 19569 1c001778 fddff06f jal x0, -36 + 19586500 19571 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19587500 19572 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19588500 19573 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19589500 19574 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19590500 19575 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19591500 19576 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19592500 19577 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19593500 19578 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19594500 19579 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19595500 19580 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104190 + 19599500 19584 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19600500 19585 1c001bca 16a0006f jal x0, 362 + 19602500 19587 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19603500 19588 1c001d36 e69ff06f jal x0, -408 + 19606500 19591 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19620500 19605 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19621500 19606 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19624500 19609 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19625500 19610 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19626500 19611 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19628500 19613 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19629500 19614 1c001778 fddff06f jal x0, -36 + 19631500 19616 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19632500 19617 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19633500 19618 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19634500 19619 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19635500 19620 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19636500 19621 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19637500 19622 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19638500 19623 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19639500 19624 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19640500 19625 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104190 + 19644500 19629 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19645500 19630 1c001bca 16a0006f jal x0, 362 + 19647500 19632 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19648500 19633 1c001d36 e69ff06f jal x0, -408 + 19651500 19636 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19665500 19650 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19666500 19651 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19669500 19654 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19670500 19655 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19671500 19656 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19673500 19658 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19674500 19659 1c001778 fddff06f jal x0, -36 + 19676500 19661 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19677500 19662 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19678500 19663 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19679500 19664 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19680500 19665 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19681500 19666 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19682500 19667 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19683500 19668 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19684500 19669 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19685500 19670 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104190 + 19689500 19674 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19690500 19675 1c001bca 16a0006f jal x0, 362 + 19692500 19677 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19693500 19678 1c001d36 e69ff06f jal x0, -408 + 19696500 19681 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19714500 19699 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19715500 19700 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19718500 19703 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19719500 19704 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19720500 19705 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19722500 19707 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19723500 19708 1c001778 fddff06f jal x0, -36 + 19725500 19710 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19726500 19711 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19727500 19712 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19728500 19713 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19729500 19714 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19730500 19715 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19731500 19716 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19732500 19717 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19733500 19718 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19734500 19719 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104190 + 19738500 19723 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19739500 19724 1c001bca 16a0006f jal x0, 362 + 19741500 19726 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19742500 19727 1c001d36 e69ff06f jal x0, -408 + 19745500 19730 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19759500 19744 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19760500 19745 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19763500 19748 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19764500 19749 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19765500 19750 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19767500 19752 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19768500 19753 1c001778 fddff06f jal x0, -36 + 19770500 19755 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19771500 19756 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19772500 19757 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19773500 19758 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19774500 19759 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19775500 19760 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19776500 19761 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19777500 19762 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19778500 19763 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19779500 19764 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104190 + 19783500 19768 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19784500 19769 1c001bca 16a0006f jal x0, 362 + 19786500 19771 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19787500 19772 1c001d36 e69ff06f jal x0, -408 + 19790500 19775 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19807500 19792 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19808500 19793 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19811500 19796 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19812500 19797 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19813500 19798 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19815500 19800 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19816500 19801 1c001778 fddff06f jal x0, -36 + 19818500 19803 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19819500 19804 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19820500 19805 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19821500 19806 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19822500 19807 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19823500 19808 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19824500 19809 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19825500 19810 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19826500 19811 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19827500 19812 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104190 + 19831500 19816 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19832500 19817 1c001bca 16a0006f jal x0, 362 + 19834500 19819 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19835500 19820 1c001d36 e69ff06f jal x0, -408 + 19838500 19823 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19855500 19840 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19856500 19841 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19859500 19844 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19860500 19845 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19861500 19846 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19863500 19848 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19864500 19849 1c001778 fddff06f jal x0, -36 + 19866500 19851 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19867500 19852 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19868500 19853 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19869500 19854 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19870500 19855 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19871500 19856 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19872500 19857 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19873500 19858 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19874500 19859 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19875500 19860 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104190 + 19879500 19864 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19880500 19865 1c001bca 16a0006f jal x0, 362 + 19882500 19867 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19883500 19868 1c001d36 e69ff06f jal x0, -408 + 19886500 19871 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19900500 19885 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19901500 19886 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19904500 19889 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19905500 19890 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19906500 19891 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19908500 19893 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19909500 19894 1c001778 fddff06f jal x0, -36 + 19911500 19896 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19912500 19897 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19913500 19898 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19914500 19899 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19915500 19900 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19916500 19901 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19917500 19902 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19918500 19903 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19919500 19904 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19920500 19905 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104190 + 19924500 19909 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19925500 19910 1c001bca 16a0006f jal x0, 362 + 19927500 19912 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19928500 19913 1c001d36 e69ff06f jal x0, -408 + 19931500 19916 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19962500 19947 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19963500 19948 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19966500 19951 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19967500 19952 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19968500 19953 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19970500 19955 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19971500 19956 1c001778 fddff06f jal x0, -36 + 19973500 19958 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19974500 19959 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 19975500 19960 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19976500 19961 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 19977500 19962 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 19978500 19963 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 19979500 19964 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 19980500 19965 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 19981500 19966 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19982500 19967 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104190 + 19986500 19971 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19987500 19972 1c001bca 16a0006f jal x0, 362 + 19989500 19974 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19990500 19975 1c001d36 e69ff06f jal x0, -408 + 19993500 19978 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 20008500 19993 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 20009500 19994 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20012500 19997 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20013500 19998 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20014500 19999 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20016500 20001 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20017500 20002 1c001778 fddff06f jal x0, -36 + 20019500 20004 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20020500 20005 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 20021500 20006 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20022500 20007 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 20023500 20008 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 20024500 20009 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 20025500 20010 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 20026500 20011 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 20027500 20012 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20028500 20013 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104190 + 20032500 20017 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20033500 20018 1c001bca 16a0006f jal x0, 362 + 20035500 20020 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20036500 20021 1c001d36 e69ff06f jal x0, -408 + 20039500 20024 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20053500 20038 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20054500 20039 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20057500 20042 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20060500 20045 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cfeb60 PA:10cfeb64 + 20069500 20054 1c001bd0 00012423 sw x0, 8(x2) x2:10cfeb60 PA:10cfeb68 + 20070500 20055 1c001bd2 00010623 sb x0, 12(x2) x2:10cfeb60 PA:10cfeb6c + 20071500 20056 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20072500 20057 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20091500 20076 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20092500 20077 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfeb60 PA:10cfeb64 + 20096500 20081 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20097500 20082 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20098500 20083 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20099500 20084 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20100500 20085 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20113500 20098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20114500 20099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20115500 20100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20134500 20119 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20135500 20120 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20156500 20141 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20157500 20142 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20158500 20143 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfeb60 PA:10cfeb70 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cfebe8 x8:10cfebe4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cfebe4 PA:10cfebe4 + 20487500 20472 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cfeb64 x2:10cfeb60 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfeb78 x11:10cfeb64 PA:10cfeb74 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfeb64 PA:10cfeb70 + 20576500 20561 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20577500 20562 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20611500 20596 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20612500 20597 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20613500 20598 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20614500 20599 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20617500 20602 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfeb64 PA:10cfeb70 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cfeb78 PA:10cfeb78 + 20783500 20768 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20784500 20769 1c001a5e 00168693 addi x13, x13, 1 x13=10cfeb79 x13:10cfeb78 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cfeb79 PA:10cfeb79 + 20804500 20789 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20806500 20791 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cfeb64 x2:10cfeb60 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cfeb40 x2:10cfeb60 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cfebe4 x2:10cfeb40 PA:10cfeb58 + 20851500 20836 1c001a66 01062783 lw x15, 16(x12) x15=10cfeb78 x12:10cfeb64 PA:10cfeb74 + 20852500 20837 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfeb64 PA:10cfeb68 + 20853500 20838 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cfeb40 PA:10cfeb54 + 20854500 20839 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfeb40 PA:10cfeb50 + 20855500 20840 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfeb40 PA:10cfeb4c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfeb40 PA:10cfeb5c + 20871500 20856 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfeb40 PA:10cfeb48 + 20872500 20857 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20873500 20858 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20874500 20859 1c001a78 00c004b3 add x9, x0, x12 x9=10cfeb64 x12:10cfeb64 + 20875500 20860 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cfeb79 x15:10cfeb78 PA:10cfeb78 + 20877500 20862 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfeb64 PA:10cfeb6c + 20901500 20886 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20904500 20889 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfeb64 PA:10cfeb6c + 20981500 20966 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 21001500 20986 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21002500 20987 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfeb78 x9:10cfeb64 PA:10cfeb74 + 21043500 21028 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cfeb79 x20:10cfeb78 PA:10cfeb78 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104190 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfeb7a x20:10cfeb79 PA:10cfeb79 + 21124500 21109 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21125500 21110 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 21127500 21112 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21128500 21113 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfeb40 PA:10cfeb5c + 21157500 21142 1c001b02 01812403 lw x8, 24(x2) x8=10cfebe4 x2:10cfeb40 PA:10cfeb58 + 21158500 21143 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cfeb40 PA:10cfeb54 + 21159500 21144 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfeb40 PA:10cfeb50 + 21160500 21145 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfeb40 PA:10cfeb4c + 21161500 21146 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfeb40 PA:10cfeb48 + 21162500 21147 1c001b0c 02010113 addi x2, x2, 32 x2=10cfeb60 x2:10cfeb40 + 21163500 21148 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cfebe8 x24:10cfebe8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21203500 21188 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21204500 21189 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21207500 21192 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21208500 21193 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21209500 21194 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21211500 21196 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21212500 21197 1c001778 fddff06f jal x0, -36 + 21214500 21199 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21215500 21200 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 21216500 21201 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21217500 21202 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 21218500 21203 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 21219500 21204 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 21220500 21205 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 21221500 21206 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 21222500 21207 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21223500 21208 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104190 + 21227500 21212 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21228500 21213 1c001bca 16a0006f jal x0, 362 + 21230500 21215 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21231500 21216 1c001d36 e69ff06f jal x0, -408 + 21234500 21219 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21248500 21233 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21249500 21234 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21252500 21237 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21253500 21238 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21254500 21239 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21256500 21241 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21257500 21242 1c001778 fddff06f jal x0, -36 + 21259500 21244 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21260500 21245 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 21261500 21246 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21262500 21247 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 21263500 21248 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 21264500 21249 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 21265500 21250 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 21266500 21251 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 21267500 21252 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21268500 21253 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104190 + 21272500 21257 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21273500 21258 1c001bca 16a0006f jal x0, 362 + 21275500 21260 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21276500 21261 1c001d36 e69ff06f jal x0, -408 + 21279500 21264 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21293500 21278 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21294500 21279 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21297500 21282 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21300500 21285 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cfeb60 PA:10cfeb64 + 21301500 21286 1c001bd0 00012423 sw x0, 8(x2) x2:10cfeb60 PA:10cfeb68 + 21302500 21287 1c001bd2 00010623 sb x0, 12(x2) x2:10cfeb60 PA:10cfeb6c + 21303500 21288 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21304500 21289 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21305500 21290 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21306500 21291 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfeb60 PA:10cfeb64 + 21307500 21292 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21308500 21293 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21309500 21294 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21310500 21295 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21311500 21296 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21312500 21297 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21313500 21298 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21314500 21299 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21329500 21314 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21330500 21315 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21333500 21318 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21334500 21319 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21335500 21320 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21338500 21323 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21341500 21326 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21344500 21329 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21347500 21332 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21348500 21333 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21349500 21334 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21350500 21335 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21353500 21338 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21354500 21339 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21357500 21342 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21358500 21343 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21361500 21346 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21363500 21348 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21366500 21351 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21367500 21352 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21370500 21355 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21371500 21356 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21372500 21357 1c001f42 e09ff06f jal x0, -504 + 21374500 21359 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21375500 21360 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfeb60 PA:10cfeb70 + 21376500 21361 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21379500 21364 1c001e34 00440c13 addi x24, x8, 4 x24=10cfebec x8:10cfebe8 + 21380500 21365 1c001e38 00042503 lw x10, 0(x8) x10=00000002 x8:10cfebe8 PA:10cfebe8 + 21381500 21366 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21384500 21369 1c001e54 00055863 bge x10, x0, 16 x10:00000002 + 21387500 21372 1c001e64 00410593 addi x11, x2, 4 x11=10cfeb64 x2:10cfeb60 + 21388500 21373 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21390500 21375 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfeb78 x11:10cfeb64 PA:10cfeb74 + 21391500 21376 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfeb64 PA:10cfeb70 + 21392500 21377 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21393500 21378 1c001a04 02f55633 divu x12, x10, x15 x12=00000002 x10:00000002 x15:00000001 + 21427500 21412 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000002 x14:0000000a + 21428500 21413 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21429500 21414 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21430500 21415 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21433500 21418 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfeb64 PA:10cfeb70 + 21434500 21419 1c001a20 02f55833 divu x16, x10, x15 x16=00000002 x10:00000002 x15:00000001 + 21468500 21453 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000002 x15:00000001 + 21502500 21487 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21533500 21518 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21534500 21519 1c001a2e 01004663 blt x0, x16, 12 x16:00000002 + 21537500 21522 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21539500 21524 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000002 + 21542500 21527 1c001a56 01070733 add x14, x14, x16 x14=00000032 x14:00000030 x16:00000002 + 21543500 21528 1c001a58 00e68023 sb x14, 0(x13) x14:00000032 x13:10cfeb78 PA:10cfeb78 + 21544500 21529 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21545500 21530 1c001a5e 00168693 addi x13, x13, 1 x13=10cfeb79 x13:10cfeb78 + 21546500 21531 1c001a60 fb1ff06f jal x0, -80 + 21548500 21533 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21549500 21534 1c001a12 00068023 sb x0, 0(x13) x13:10cfeb79 PA:10cfeb79 + 21550500 21535 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21552500 21537 1c001e68 f17ff06f jal x0, -234 + 21554500 21539 1c001d7e 00410613 addi x12, x2, 4 x12=10cfeb64 x2:10cfeb60 + 21555500 21540 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21556500 21541 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21557500 21542 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21559500 21544 1c001a62 fe010113 addi x2, x2, -32 x2=10cfeb40 x2:10cfeb60 + 21560500 21545 1c001a64 00812c23 sw x8, 24(x2) x8:10cfebe8 x2:10cfeb40 PA:10cfeb58 + 21561500 21546 1c001a66 01062783 lw x15, 16(x12) x15=10cfeb78 x12:10cfeb64 PA:10cfeb74 + 21562500 21547 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfeb64 PA:10cfeb68 + 21563500 21548 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cfeb40 PA:10cfeb54 + 21564500 21549 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfeb40 PA:10cfeb50 + 21565500 21550 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfeb40 PA:10cfeb4c + 21566500 21551 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfeb40 PA:10cfeb5c + 21567500 21552 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfeb40 PA:10cfeb48 + 21568500 21553 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21569500 21554 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21570500 21555 1c001a78 00c004b3 add x9, x0, x12 x9=10cfeb64 x12:10cfeb64 + 21571500 21556 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000032 x15=10cfeb79 x15:10cfeb78 PA:10cfeb78 + 21573500 21558 1c001a7e 00070363 beq x14, x0, 6 x14:00000032 + 21574500 21559 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21575500 21560 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfeb64 PA:10cfeb6c + 21577500 21562 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21580500 21565 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 21582500 21567 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21583500 21568 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21586500 21571 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21587500 21572 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21588500 21573 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21591500 21576 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21592500 21577 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21593500 21578 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21594500 21579 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21595500 21580 1c001b36 f71ff06f jal x0, -144 + 21597500 21582 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfeb64 PA:10cfeb6c + 21599500 21584 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21602500 21587 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 21604500 21589 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21605500 21590 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21608500 21593 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 21609500 21594 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21610500 21595 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21611500 21596 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21612500 21597 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfeb78 x9:10cfeb64 PA:10cfeb74 + 21614500 21599 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000032 x20=10cfeb79 x20:10cfeb78 PA:10cfeb78 + 21616500 21601 1c001af0 06059763 bne x11, x0, 110 x11:00000032 + 21619500 21604 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21620500 21605 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21622500 21607 1c001776 00b00533 add x10, x0, x11 x10=00000032 x11:00000032 + 21623500 21608 1c001778 fddff06f jal x0, -36 + 21625500 21610 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21626500 21611 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 21627500 21612 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21628500 21613 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 21629500 21614 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 21630500 21615 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 21631500 21616 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 21632500 21617 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 21633500 21618 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21634500 21619 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000032 x14:1a104000 PA:1a104190 + 21638500 21623 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21639500 21624 1c001b62 f8bff06f jal x0, -118 + 21641500 21626 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfeb7a x20:10cfeb79 PA:10cfeb79 + 21643500 21628 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21644500 21629 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfeb64 PA:10cfeb64 + 21646500 21631 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21647500 21632 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21650500 21635 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfeb40 PA:10cfeb5c + 21651500 21636 1c001b02 01812403 lw x8, 24(x2) x8=10cfebe8 x2:10cfeb40 PA:10cfeb58 + 21652500 21637 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cfeb40 PA:10cfeb54 + 21653500 21638 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfeb40 PA:10cfeb50 + 21654500 21639 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfeb40 PA:10cfeb4c + 21655500 21640 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfeb40 PA:10cfeb48 + 21656500 21641 1c001b0c 02010113 addi x2, x2, 32 x2=10cfeb60 x2:10cfeb40 + 21657500 21642 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21659500 21644 1c001d86 01800433 add x8, x0, x24 x8=10cfebec x24:10cfebec + 21660500 21645 1c001d88 fadff06f jal x0, -84 + 21662500 21647 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21663500 21648 1c001d36 e69ff06f jal x0, -408 + 21666500 21651 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21684500 21669 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21685500 21670 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21688500 21673 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21689500 21674 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21690500 21675 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21692500 21677 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21693500 21678 1c001778 fddff06f jal x0, -36 + 21695500 21680 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21696500 21681 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 21697500 21682 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21698500 21683 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 21699500 21684 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 21700500 21685 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 21701500 21686 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 21702500 21687 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 21703500 21688 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21704500 21689 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104190 + 21708500 21693 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21709500 21694 1c001bca 16a0006f jal x0, 362 + 21711500 21696 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21712500 21697 1c001d36 e69ff06f jal x0, -408 + 21715500 21700 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21730500 21715 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21731500 21716 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21734500 21719 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21735500 21720 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21736500 21721 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21738500 21723 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21739500 21724 1c001778 fddff06f jal x0, -36 + 21741500 21726 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21742500 21727 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 21743500 21728 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21744500 21729 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 21745500 21730 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 21746500 21731 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 21747500 21732 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 21748500 21733 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 21749500 21734 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21750500 21735 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104190 + 21754500 21739 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21755500 21740 1c001bca 16a0006f jal x0, 362 + 21757500 21742 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21758500 21743 1c001d36 e69ff06f jal x0, -408 + 21761500 21746 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21779500 21764 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21780500 21765 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21783500 21768 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21784500 21769 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21785500 21770 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21787500 21772 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21788500 21773 1c001778 fddff06f jal x0, -36 + 21790500 21775 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21791500 21776 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000062 + 21792500 21777 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21793500 21778 1c00175e 00379713 slli x14, x15, 0x3 x14=00000310 x15:00000062 + 21794500 21779 1c001762 00279793 slli x15, x15, 0x2 x15=00000188 x15:00000062 + 21795500 21780 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000010 x14:00000310 + 21796500 21781 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000188 x13:00001f80 + 21797500 21782 1c00176a 00e787b3 add x15, x15, x14 x15=00000190 x15:00000180 x14:00000010 + 21798500 21783 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21799500 21784 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104190 + 21803500 21788 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21804500 21789 1c001bca 16a0006f jal x0, 362 + 21806500 21791 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21807500 21792 1c001d36 e69ff06f jal x0, -408 + 21810500 21795 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21824500 21809 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21825500 21810 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21826500 21811 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cfeb60 PA:10cfebbc + 21827500 21812 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:10cfeb60 PA:10cfebb8 + 21828500 21813 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:10cfeb60 PA:10cfebb4 + 21829500 21814 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:10cfeb60 PA:10cfebb0 + 21841500 21826 1c001bb0 04c12983 lw x19, 76(x2) x19=00000002 x2:10cfeb60 PA:10cfebac + 21842500 21827 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:10cfeb60 PA:10cfeba8 + 21843500 21828 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:10cfeb60 PA:10cfeba4 + 21844500 21829 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:10cfeb60 PA:10cfeba0 + 21845500 21830 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:10cfeb60 PA:10cfeb9c + 21846500 21831 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:10cfeb60 PA:10cfeb98 + 21847500 21832 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:10cfeb60 PA:10cfeb94 + 21848500 21833 1c001bbe 06010113 addi x2, x2, 96 x2=10cfebc0 x2:10cfeb60 + 21849500 21834 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21851500 21836 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:10cfebc0 PA:10cfebdc + 21852500 21837 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21853500 21838 1c001838 04010113 addi x2, x2, 64 x2=10cfec00 x2:10cfebc0 + 21854500 21839 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21856500 21841 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_3.log b/sw/scripts/tracevis/example/traces/trace_core_03_3.log new file mode 100644 index 0000000..0e25e53 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_3.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000063 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000003 x10:00000063 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000063 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000003 + 17052500 17037 1c0000a6 05a0206f jal x0, 8282 + 17070500 17055 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17071500 17056 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17072500 17057 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17073500 17058 1c00210c 0e059163 bne x11, x0, 226 x11:00000003 + 17125500 17110 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 17126500 17111 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000063 + 17127500 17112 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000003 x19:00000063 + 17128500 17113 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 17147500 17132 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 17148500 17133 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 17149500 17134 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 17150500 17135 1c00220a 0060006f jal x0, 6 + 17169500 17154 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18817500 18802 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18836500 18821 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18837500 18822 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18862500 18847 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18863500 18848 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18865500 18850 1c00222c 08096283 p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080 + 18895500 18880 1c002230 02a98533 mul x10, x19, x10 x10=00000c00 x19:00000003 x10:00000400 + 18896500 18881 1c002234 00550133 add x2, x10, x5 x2=10cff000 x10:00000c00 x5:10cfe400 + 18897500 18882 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18899500 18884 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18936500 18921 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18944500 18929 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18945500 18930 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18946500 18931 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18947500 18932 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18965500 18950 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000063 + 18986500 18971 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18987500 18972 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000003 x12:00000063 + 18988500 18973 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003 + 18989500 18974 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000003 x12:00000063 + 18990500 18975 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18991500 18976 1c0009d4 63d0006f jal x0, 3644 + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cfefc0 x2:10cff000 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cfefc0 PA:10cfefe4 + 19022500 19007 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19023500 19008 1c001818 02c12423 sw x12, 40(x2) x12:00000003 x2:10cfefc0 PA:10cfefe8 + 19024500 19009 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cfefc0 PA:10cfefec + 19025500 19010 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19026500 19011 1c00181e 02410693 addi x13, x2, 36 x13=10cfefe4 x2:10cfefc0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:10cfefc0 PA:10cfefdc + 19051500 19036 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:10cfefc0 PA:10cfeff0 + 19052500 19037 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:10cfefc0 PA:10cfeff4 + 19053500 19038 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cfefc0 PA:10cfeff8 + 19054500 19039 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cfefc0 PA:10cfeffc + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cfefe4 x2:10cfefc0 PA:10cfefcc + 19075500 19060 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cfef60 x2:10cfefc0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cfef78 x2:10cfef60 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:10cfef60 PA:10cfefb8 + 19096500 19081 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:10cfef60 PA:10cfefb0 + 19097500 19082 1c001b78 05312623 sw x19, 76(x2) x19:00000003 x2:10cfef60 PA:10cfefac + 19098500 19083 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:10cfef60 PA:10cfefa8 + 19099500 19084 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:10cfef60 PA:10cfefa4 + 19100500 19085 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:10cfef60 PA:10cfefa0 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:10cfef60 PA:10cfef9c + 19119500 19104 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cfef60 PA:10cfefbc + 19120500 19105 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:10cfef60 PA:10cfefb4 + 19121500 19106 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:10cfef60 PA:10cfef98 + 19122500 19107 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:10cfef60 PA:10cfef94 + 19123500 19108 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19124500 19109 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19125500 19110 1c001b8e 00d00433 add x8, x0, x13 x8=10cfefe4 x13:10cfefe4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cfef78 x2:10cfef60 PA:10cfef74 + 19141500 19126 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19142500 19127 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19143500 19128 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19144500 19129 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19203500 19188 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19204500 19189 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19226500 19211 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19227500 19212 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19228500 19213 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a104198 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19356500 19341 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19357500 19342 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19360500 19345 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19361500 19346 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19362500 19347 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19364500 19349 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19365500 19350 1c001778 fddff06f jal x0, -36 + 19367500 19352 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19368500 19353 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19369500 19354 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19370500 19355 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19371500 19356 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19372500 19357 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19373500 19358 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19374500 19359 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19375500 19360 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19376500 19361 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104198 + 19380500 19365 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19381500 19366 1c001bca 16a0006f jal x0, 362 + 19383500 19368 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19384500 19369 1c001d36 e69ff06f jal x0, -408 + 19387500 19372 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19408500 19393 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19409500 19394 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19412500 19397 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19413500 19398 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19414500 19399 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19416500 19401 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19417500 19402 1c001778 fddff06f jal x0, -36 + 19419500 19404 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19420500 19405 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19421500 19406 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19422500 19407 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19423500 19408 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19424500 19409 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19425500 19410 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19426500 19411 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19427500 19412 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19428500 19413 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a104198 + 19432500 19417 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19433500 19418 1c001bca 16a0006f jal x0, 362 + 19435500 19420 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19436500 19421 1c001d36 e69ff06f jal x0, -408 + 19439500 19424 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19464500 19449 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19465500 19450 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19468500 19453 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19469500 19454 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19470500 19455 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19472500 19457 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19473500 19458 1c001778 fddff06f jal x0, -36 + 19475500 19460 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19476500 19461 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19477500 19462 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19478500 19463 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19479500 19464 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19480500 19465 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19481500 19466 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19482500 19467 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19483500 19468 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19484500 19469 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104198 + 19488500 19473 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19489500 19474 1c001bca 16a0006f jal x0, 362 + 19491500 19476 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19492500 19477 1c001d36 e69ff06f jal x0, -408 + 19495500 19480 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19517500 19502 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19518500 19503 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19521500 19506 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19522500 19507 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19523500 19508 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19525500 19510 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19526500 19511 1c001778 fddff06f jal x0, -36 + 19528500 19513 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19529500 19514 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19530500 19515 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19531500 19516 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19532500 19517 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19533500 19518 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19534500 19519 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19535500 19520 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19536500 19521 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19537500 19522 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104198 + 19541500 19526 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19542500 19527 1c001bca 16a0006f jal x0, 362 + 19544500 19529 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19545500 19530 1c001d36 e69ff06f jal x0, -408 + 19548500 19533 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19585500 19570 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19586500 19571 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19589500 19574 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19590500 19575 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19591500 19576 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19593500 19578 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19594500 19579 1c001778 fddff06f jal x0, -36 + 19596500 19581 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19597500 19582 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19598500 19583 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19599500 19584 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19600500 19585 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19601500 19586 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19602500 19587 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19603500 19588 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19604500 19589 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19605500 19590 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a104198 + 19609500 19594 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19610500 19595 1c001bca 16a0006f jal x0, 362 + 19612500 19597 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19613500 19598 1c001d36 e69ff06f jal x0, -408 + 19616500 19601 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19630500 19615 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19631500 19616 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19634500 19619 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19635500 19620 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19636500 19621 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19638500 19623 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19639500 19624 1c001778 fddff06f jal x0, -36 + 19641500 19626 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19642500 19627 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19643500 19628 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19644500 19629 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19645500 19630 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19646500 19631 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19647500 19632 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19648500 19633 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19649500 19634 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19650500 19635 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a104198 + 19654500 19639 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19655500 19640 1c001bca 16a0006f jal x0, 362 + 19657500 19642 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19658500 19643 1c001d36 e69ff06f jal x0, -408 + 19661500 19646 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19675500 19660 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19676500 19661 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19679500 19664 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19680500 19665 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19681500 19666 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19683500 19668 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19684500 19669 1c001778 fddff06f jal x0, -36 + 19686500 19671 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19687500 19672 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19688500 19673 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19689500 19674 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19690500 19675 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19691500 19676 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19692500 19677 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19693500 19678 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19694500 19679 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19695500 19680 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a104198 + 19699500 19684 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19700500 19685 1c001bca 16a0006f jal x0, 362 + 19702500 19687 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19703500 19688 1c001d36 e69ff06f jal x0, -408 + 19706500 19691 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19720500 19705 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19721500 19706 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19724500 19709 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19725500 19710 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19726500 19711 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19728500 19713 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19729500 19714 1c001778 fddff06f jal x0, -36 + 19731500 19716 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19732500 19717 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19733500 19718 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19734500 19719 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19735500 19720 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19736500 19721 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19737500 19722 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19738500 19723 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19739500 19724 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19740500 19725 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104198 + 19744500 19729 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19745500 19730 1c001bca 16a0006f jal x0, 362 + 19747500 19732 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19748500 19733 1c001d36 e69ff06f jal x0, -408 + 19751500 19736 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19765500 19750 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19766500 19751 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19769500 19754 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19770500 19755 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19771500 19756 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19773500 19758 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19774500 19759 1c001778 fddff06f jal x0, -36 + 19776500 19761 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19777500 19762 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19778500 19763 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19779500 19764 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19780500 19765 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19781500 19766 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19782500 19767 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19783500 19768 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19784500 19769 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19785500 19770 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a104198 + 19789500 19774 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19790500 19775 1c001bca 16a0006f jal x0, 362 + 19792500 19777 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19793500 19778 1c001d36 e69ff06f jal x0, -408 + 19796500 19781 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19816500 19801 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19817500 19802 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19820500 19805 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19821500 19806 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19822500 19807 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19824500 19809 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19825500 19810 1c001778 fddff06f jal x0, -36 + 19827500 19812 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19828500 19813 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19829500 19814 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19830500 19815 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19831500 19816 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19832500 19817 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19833500 19818 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19834500 19819 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19835500 19820 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19836500 19821 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a104198 + 19840500 19825 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19841500 19826 1c001bca 16a0006f jal x0, 362 + 19843500 19828 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19844500 19829 1c001d36 e69ff06f jal x0, -408 + 19847500 19832 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19863500 19848 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19864500 19849 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19867500 19852 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19868500 19853 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19869500 19854 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19871500 19856 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19872500 19857 1c001778 fddff06f jal x0, -36 + 19874500 19859 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19875500 19860 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19876500 19861 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19877500 19862 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19878500 19863 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19879500 19864 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19880500 19865 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19881500 19866 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19882500 19867 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19883500 19868 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a104198 + 19887500 19872 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19888500 19873 1c001bca 16a0006f jal x0, 362 + 19890500 19875 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19891500 19876 1c001d36 e69ff06f jal x0, -408 + 19894500 19879 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19908500 19893 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19909500 19894 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19912500 19897 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19913500 19898 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19914500 19899 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19916500 19901 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19917500 19902 1c001778 fddff06f jal x0, -36 + 19919500 19904 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19920500 19905 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19921500 19906 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19922500 19907 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19923500 19908 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19924500 19909 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19925500 19910 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19926500 19911 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19927500 19912 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19928500 19913 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a104198 + 19932500 19917 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19933500 19918 1c001bca 16a0006f jal x0, 362 + 19935500 19920 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19936500 19921 1c001d36 e69ff06f jal x0, -408 + 19939500 19924 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19966500 19951 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19967500 19952 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19970500 19955 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19971500 19956 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19972500 19957 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19974500 19959 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19975500 19960 1c001778 fddff06f jal x0, -36 + 19977500 19962 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19978500 19963 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 19979500 19964 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19980500 19965 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 19981500 19966 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 19982500 19967 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 19983500 19968 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 19984500 19969 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 19985500 19970 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19986500 19971 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104198 + 19990500 19975 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19991500 19976 1c001bca 16a0006f jal x0, 362 + 19993500 19978 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19994500 19979 1c001d36 e69ff06f jal x0, -408 + 19997500 19982 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 20011500 19996 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 20012500 19997 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20015500 20000 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20016500 20001 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20017500 20002 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20019500 20004 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20020500 20005 1c001778 fddff06f jal x0, -36 + 20022500 20007 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20023500 20008 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 20024500 20009 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20025500 20010 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 20026500 20011 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 20027500 20012 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 20028500 20013 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 20029500 20014 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 20030500 20015 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20031500 20016 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a104198 + 20035500 20020 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20036500 20021 1c001bca 16a0006f jal x0, 362 + 20038500 20023 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20039500 20024 1c001d36 e69ff06f jal x0, -408 + 20042500 20027 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20059500 20044 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20060500 20045 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20063500 20048 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20066500 20051 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cfef60 PA:10cfef64 + 20071500 20056 1c001bd0 00012423 sw x0, 8(x2) x2:10cfef60 PA:10cfef68 + 20073500 20058 1c001bd2 00010623 sb x0, 12(x2) x2:10cfef60 PA:10cfef6c + 20074500 20059 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20075500 20060 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20091500 20076 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20092500 20077 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfef60 PA:10cfef64 + 20095500 20080 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20096500 20081 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20097500 20082 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20098500 20083 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20099500 20084 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20113500 20098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20114500 20099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20115500 20100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20136500 20121 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20137500 20122 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20156500 20141 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20157500 20142 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20158500 20143 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfef60 PA:10cfef70 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cfefe8 x8:10cfefe4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cfefe4 PA:10cfefe4 + 20486500 20471 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cfef64 x2:10cfef60 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfef78 x11:10cfef64 PA:10cfef74 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfef64 PA:10cfef70 + 20577500 20562 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20578500 20563 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20612500 20597 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20613500 20598 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20614500 20599 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20615500 20600 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20618500 20603 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfef64 PA:10cfef70 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cfef78 PA:10cfef78 + 20784500 20769 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20785500 20770 1c001a5e 00168693 addi x13, x13, 1 x13=10cfef79 x13:10cfef78 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cfef79 PA:10cfef79 + 20805500 20790 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20806500 20791 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cfef64 x2:10cfef60 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cfef40 x2:10cfef60 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cfefe4 x2:10cfef40 PA:10cfef58 + 20852500 20837 1c001a66 01062783 lw x15, 16(x12) x15=10cfef78 x12:10cfef64 PA:10cfef74 + 20853500 20838 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfef64 PA:10cfef68 + 20854500 20839 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cfef40 PA:10cfef54 + 20855500 20840 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfef40 PA:10cfef50 + 20856500 20841 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfef40 PA:10cfef4c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfef40 PA:10cfef5c + 20870500 20855 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfef40 PA:10cfef48 + 20871500 20856 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20872500 20857 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20873500 20858 1c001a78 00c004b3 add x9, x0, x12 x9=10cfef64 x12:10cfef64 + 20874500 20859 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cfef79 x15:10cfef78 PA:10cfef78 + 20876500 20861 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfef64 PA:10cfef6c + 20895500 20880 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20898500 20883 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfef64 PA:10cfef6c + 20982500 20967 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 21002500 20987 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21003500 20988 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfef78 x9:10cfef64 PA:10cfef74 + 21044500 21029 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cfef79 x20:10cfef78 PA:10cfef78 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104198 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfef7a x20:10cfef79 PA:10cfef79 + 21125500 21110 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21126500 21111 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 21128500 21113 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21129500 21114 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfef40 PA:10cfef5c + 21158500 21143 1c001b02 01812403 lw x8, 24(x2) x8=10cfefe4 x2:10cfef40 PA:10cfef58 + 21159500 21144 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cfef40 PA:10cfef54 + 21160500 21145 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfef40 PA:10cfef50 + 21161500 21146 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfef40 PA:10cfef4c + 21162500 21147 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfef40 PA:10cfef48 + 21163500 21148 1c001b0c 02010113 addi x2, x2, 32 x2=10cfef60 x2:10cfef40 + 21164500 21149 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cfefe8 x24:10cfefe8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21205500 21190 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21206500 21191 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21209500 21194 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21210500 21195 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21211500 21196 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21213500 21198 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21214500 21199 1c001778 fddff06f jal x0, -36 + 21216500 21201 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21217500 21202 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 21218500 21203 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21219500 21204 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 21220500 21205 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 21221500 21206 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 21222500 21207 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 21223500 21208 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 21224500 21209 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21225500 21210 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a104198 + 21229500 21214 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21230500 21215 1c001bca 16a0006f jal x0, 362 + 21232500 21217 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21233500 21218 1c001d36 e69ff06f jal x0, -408 + 21236500 21221 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21250500 21235 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21251500 21236 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21254500 21239 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21255500 21240 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21256500 21241 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21258500 21243 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21259500 21244 1c001778 fddff06f jal x0, -36 + 21261500 21246 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21262500 21247 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 21263500 21248 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21264500 21249 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 21265500 21250 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 21266500 21251 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 21267500 21252 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 21268500 21253 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 21269500 21254 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21270500 21255 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a104198 + 21274500 21259 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21275500 21260 1c001bca 16a0006f jal x0, 362 + 21277500 21262 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21278500 21263 1c001d36 e69ff06f jal x0, -408 + 21281500 21266 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21296500 21281 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21297500 21282 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21300500 21285 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21303500 21288 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cfef60 PA:10cfef64 + 21304500 21289 1c001bd0 00012423 sw x0, 8(x2) x2:10cfef60 PA:10cfef68 + 21305500 21290 1c001bd2 00010623 sb x0, 12(x2) x2:10cfef60 PA:10cfef6c + 21306500 21291 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21307500 21292 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21308500 21293 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21309500 21294 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfef60 PA:10cfef64 + 21310500 21295 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21311500 21296 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21312500 21297 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21313500 21298 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21314500 21299 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21315500 21300 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21316500 21301 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21317500 21302 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21331500 21316 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21332500 21317 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21335500 21320 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21336500 21321 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21337500 21322 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21340500 21325 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21343500 21328 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21346500 21331 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21349500 21334 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21350500 21335 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21351500 21336 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21352500 21337 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21355500 21340 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21356500 21341 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21359500 21344 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21360500 21345 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21363500 21348 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21365500 21350 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21368500 21353 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21369500 21354 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21372500 21357 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21373500 21358 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21374500 21359 1c001f42 e09ff06f jal x0, -504 + 21376500 21361 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21377500 21362 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfef60 PA:10cfef70 + 21378500 21363 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21381500 21366 1c001e34 00440c13 addi x24, x8, 4 x24=10cfefec x8:10cfefe8 + 21382500 21367 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cfefe8 PA:10cfefe8 + 21383500 21368 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21386500 21371 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 21389500 21374 1c001e64 00410593 addi x11, x2, 4 x11=10cfef64 x2:10cfef60 + 21390500 21375 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21392500 21377 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfef78 x11:10cfef64 PA:10cfef74 + 21393500 21378 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfef64 PA:10cfef70 + 21394500 21379 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21395500 21380 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 21429500 21414 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 21430500 21415 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21431500 21416 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21432500 21417 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21435500 21420 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfef64 PA:10cfef70 + 21436500 21421 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 21470500 21455 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 21504500 21489 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21535500 21520 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21536500 21521 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 21539500 21524 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21541500 21526 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 21544500 21529 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 21545500 21530 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cfef78 PA:10cfef78 + 21546500 21531 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21547500 21532 1c001a5e 00168693 addi x13, x13, 1 x13=10cfef79 x13:10cfef78 + 21548500 21533 1c001a60 fb1ff06f jal x0, -80 + 21550500 21535 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21551500 21536 1c001a12 00068023 sb x0, 0(x13) x13:10cfef79 PA:10cfef79 + 21552500 21537 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21554500 21539 1c001e68 f17ff06f jal x0, -234 + 21556500 21541 1c001d7e 00410613 addi x12, x2, 4 x12=10cfef64 x2:10cfef60 + 21557500 21542 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21558500 21543 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21559500 21544 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21561500 21546 1c001a62 fe010113 addi x2, x2, -32 x2=10cfef40 x2:10cfef60 + 21562500 21547 1c001a64 00812c23 sw x8, 24(x2) x8:10cfefe8 x2:10cfef40 PA:10cfef58 + 21563500 21548 1c001a66 01062783 lw x15, 16(x12) x15=10cfef78 x12:10cfef64 PA:10cfef74 + 21564500 21549 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfef64 PA:10cfef68 + 21565500 21550 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cfef40 PA:10cfef54 + 21566500 21551 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfef40 PA:10cfef50 + 21567500 21552 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfef40 PA:10cfef4c + 21568500 21553 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfef40 PA:10cfef5c + 21569500 21554 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfef40 PA:10cfef48 + 21570500 21555 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21571500 21556 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21572500 21557 1c001a78 00c004b3 add x9, x0, x12 x9=10cfef64 x12:10cfef64 + 21573500 21558 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cfef79 x15:10cfef78 PA:10cfef78 + 21576500 21561 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 21577500 21562 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21578500 21563 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfef64 PA:10cfef6c + 21580500 21565 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21583500 21568 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 21586500 21571 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21587500 21572 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21590500 21575 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21591500 21576 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21592500 21577 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21595500 21580 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21596500 21581 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21597500 21582 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21598500 21583 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21599500 21584 1c001b36 f71ff06f jal x0, -144 + 21601500 21586 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfef64 PA:10cfef6c + 21603500 21588 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21606500 21591 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 21608500 21593 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21609500 21594 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21612500 21597 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 21613500 21598 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21614500 21599 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21615500 21600 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21616500 21601 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfef78 x9:10cfef64 PA:10cfef74 + 21618500 21603 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cfef79 x20:10cfef78 PA:10cfef78 + 21620500 21605 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21623500 21608 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21624500 21609 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21626500 21611 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21627500 21612 1c001778 fddff06f jal x0, -36 + 21629500 21614 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21630500 21615 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 21631500 21616 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21632500 21617 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 21633500 21618 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 21634500 21619 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 21635500 21620 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 21636500 21621 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 21637500 21622 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21638500 21623 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a104198 + 21642500 21627 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21643500 21628 1c001b62 f8bff06f jal x0, -118 + 21645500 21630 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfef7a x20:10cfef79 PA:10cfef79 + 21647500 21632 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21648500 21633 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfef64 PA:10cfef64 + 21650500 21635 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21651500 21636 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21654500 21639 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfef40 PA:10cfef5c + 21655500 21640 1c001b02 01812403 lw x8, 24(x2) x8=10cfefe8 x2:10cfef40 PA:10cfef58 + 21656500 21641 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cfef40 PA:10cfef54 + 21657500 21642 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfef40 PA:10cfef50 + 21658500 21643 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfef40 PA:10cfef4c + 21659500 21644 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfef40 PA:10cfef48 + 21660500 21645 1c001b0c 02010113 addi x2, x2, 32 x2=10cfef60 x2:10cfef40 + 21661500 21646 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21663500 21648 1c001d86 01800433 add x8, x0, x24 x8=10cfefec x24:10cfefec + 21664500 21649 1c001d88 fadff06f jal x0, -84 + 21666500 21651 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21667500 21652 1c001d36 e69ff06f jal x0, -408 + 21670500 21655 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21685500 21670 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21686500 21671 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21689500 21674 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21690500 21675 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21691500 21676 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21693500 21678 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21694500 21679 1c001778 fddff06f jal x0, -36 + 21696500 21681 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21697500 21682 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 21698500 21683 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21699500 21684 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 21700500 21685 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 21701500 21686 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 21702500 21687 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 21703500 21688 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 21704500 21689 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21705500 21690 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a104198 + 21709500 21694 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21710500 21695 1c001bca 16a0006f jal x0, 362 + 21712500 21697 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21713500 21698 1c001d36 e69ff06f jal x0, -408 + 21716500 21701 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21732500 21717 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21733500 21718 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21736500 21721 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21737500 21722 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21738500 21723 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21740500 21725 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21741500 21726 1c001778 fddff06f jal x0, -36 + 21743500 21728 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21744500 21729 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 21745500 21730 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21746500 21731 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 21747500 21732 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 21748500 21733 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 21749500 21734 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 21750500 21735 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 21751500 21736 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21752500 21737 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a104198 + 21756500 21741 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21757500 21742 1c001bca 16a0006f jal x0, 362 + 21759500 21744 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21760500 21745 1c001d36 e69ff06f jal x0, -408 + 21763500 21748 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21781500 21766 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21782500 21767 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21785500 21770 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21786500 21771 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21787500 21772 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21789500 21774 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21790500 21775 1c001778 fddff06f jal x0, -36 + 21792500 21777 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21793500 21778 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000063 + 21794500 21779 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21795500 21780 1c00175e 00379713 slli x14, x15, 0x3 x14=00000318 x15:00000063 + 21796500 21781 1c001762 00279793 slli x15, x15, 0x2 x15=0000018c x15:00000063 + 21797500 21782 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000018 x14:00000318 + 21798500 21783 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000018c x13:00001f80 + 21799500 21784 1c00176a 00e787b3 add x15, x15, x14 x15=00000198 x15:00000180 x14:00000018 + 21800500 21785 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21801500 21786 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a104198 + 21805500 21790 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21806500 21791 1c001bca 16a0006f jal x0, 362 + 21808500 21793 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21809500 21794 1c001d36 e69ff06f jal x0, -408 + 21812500 21797 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21827500 21812 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21828500 21813 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21829500 21814 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cfef60 PA:10cfefbc + 21830500 21815 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:10cfef60 PA:10cfefb8 + 21831500 21816 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:10cfef60 PA:10cfefb4 + 21832500 21817 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:10cfef60 PA:10cfefb0 + 21841500 21826 1c001bb0 04c12983 lw x19, 76(x2) x19=00000003 x2:10cfef60 PA:10cfefac + 21843500 21828 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:10cfef60 PA:10cfefa8 + 21844500 21829 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:10cfef60 PA:10cfefa4 + 21845500 21830 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:10cfef60 PA:10cfefa0 + 21846500 21831 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:10cfef60 PA:10cfef9c + 21847500 21832 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:10cfef60 PA:10cfef98 + 21848500 21833 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:10cfef60 PA:10cfef94 + 21849500 21834 1c001bbe 06010113 addi x2, x2, 96 x2=10cfefc0 x2:10cfef60 + 21850500 21835 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21852500 21837 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:10cfefc0 PA:10cfefdc + 21855500 21840 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21856500 21841 1c001838 04010113 addi x2, x2, 64 x2=10cff000 x2:10cfefc0 + 21857500 21842 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21859500 21844 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_4.log b/sw/scripts/tracevis/example/traces/trace_core_03_4.log new file mode 100644 index 0000000..5c9abd2 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_4.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000064 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000004 x10:00000064 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000064 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000004 + 17052500 17037 1c0000a6 05a0206f jal x0, 8282 + 17070500 17055 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17071500 17056 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17072500 17057 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17073500 17058 1c00210c 0e059163 bne x11, x0, 226 x11:00000004 + 17125500 17110 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 17126500 17111 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000064 + 17127500 17112 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000004 x19:00000064 + 17128500 17113 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 17147500 17132 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 17148500 17133 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 17149500 17134 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 17150500 17135 1c00220a 0060006f jal x0, 6 + 17169500 17154 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18817500 18802 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18836500 18821 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18837500 18822 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18862500 18847 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18863500 18848 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18865500 18850 1c00222c 08096283 p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080 + 18895500 18880 1c002230 02a98533 mul x10, x19, x10 x10=00001000 x19:00000004 x10:00000400 + 18896500 18881 1c002234 00550133 add x2, x10, x5 x2=10cff400 x10:00001000 x5:10cfe400 + 18897500 18882 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18899500 18884 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18936500 18921 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18944500 18929 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18945500 18930 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18946500 18931 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18947500 18932 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18965500 18950 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000064 + 18986500 18971 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18987500 18972 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000003 x12:00000064 + 18988500 18973 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003 + 18989500 18974 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000004 x12:00000064 + 18990500 18975 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18991500 18976 1c0009d4 63d0006f jal x0, 3644 + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cff3c0 x2:10cff400 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cff3c0 PA:10cff3e4 + 19023500 19008 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19024500 19009 1c001818 02c12423 sw x12, 40(x2) x12:00000004 x2:10cff3c0 PA:10cff3e8 + 19025500 19010 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cff3c0 PA:10cff3ec + 19026500 19011 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19027500 19012 1c00181e 02410693 addi x13, x2, 36 x13=10cff3e4 x2:10cff3c0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:10cff3c0 PA:10cff3dc + 19048500 19033 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:10cff3c0 PA:10cff3f0 + 19049500 19034 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:10cff3c0 PA:10cff3f4 + 19050500 19035 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cff3c0 PA:10cff3f8 + 19051500 19036 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cff3c0 PA:10cff3fc + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cff3e4 x2:10cff3c0 PA:10cff3cc + 19078500 19063 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cff360 x2:10cff3c0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cff378 x2:10cff360 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:10cff360 PA:10cff3b8 + 19097500 19082 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:10cff360 PA:10cff3b0 + 19098500 19083 1c001b78 05312623 sw x19, 76(x2) x19:00000004 x2:10cff360 PA:10cff3ac + 19099500 19084 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:10cff360 PA:10cff3a8 + 19100500 19085 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:10cff360 PA:10cff3a4 + 19101500 19086 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:10cff360 PA:10cff3a0 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:10cff360 PA:10cff39c + 19122500 19107 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cff360 PA:10cff3bc + 19123500 19108 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:10cff360 PA:10cff3b4 + 19124500 19109 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:10cff360 PA:10cff398 + 19125500 19110 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:10cff360 PA:10cff394 + 19126500 19111 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19127500 19112 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19128500 19113 1c001b8e 00d00433 add x8, x0, x13 x8=10cff3e4 x13:10cff3e4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cff378 x2:10cff360 PA:10cff374 + 19142500 19127 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19143500 19128 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19144500 19129 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19145500 19130 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19233500 19218 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19234500 19219 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19237500 19222 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19238500 19223 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19239500 19224 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1041a0 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19358500 19343 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19359500 19344 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19362500 19347 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19363500 19348 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19364500 19349 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19366500 19351 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19367500 19352 1c001778 fddff06f jal x0, -36 + 19369500 19354 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19370500 19355 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19371500 19356 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19372500 19357 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19373500 19358 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19374500 19359 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19375500 19360 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19376500 19361 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19377500 19362 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19378500 19363 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041a0 + 19382500 19367 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19383500 19368 1c001bca 16a0006f jal x0, 362 + 19385500 19370 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19386500 19371 1c001d36 e69ff06f jal x0, -408 + 19389500 19374 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19415500 19400 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19416500 19401 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19419500 19404 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19420500 19405 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19421500 19406 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19423500 19408 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19424500 19409 1c001778 fddff06f jal x0, -36 + 19426500 19411 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19427500 19412 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19428500 19413 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19429500 19414 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19430500 19415 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19431500 19416 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19432500 19417 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19433500 19418 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19434500 19419 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19435500 19420 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1041a0 + 19439500 19424 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19440500 19425 1c001bca 16a0006f jal x0, 362 + 19442500 19427 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19443500 19428 1c001d36 e69ff06f jal x0, -408 + 19446500 19431 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19468500 19453 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19469500 19454 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19472500 19457 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19473500 19458 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19474500 19459 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19476500 19461 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19477500 19462 1c001778 fddff06f jal x0, -36 + 19479500 19464 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19480500 19465 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19481500 19466 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19482500 19467 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19483500 19468 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19484500 19469 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19485500 19470 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19486500 19471 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19487500 19472 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19488500 19473 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041a0 + 19492500 19477 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19493500 19478 1c001bca 16a0006f jal x0, 362 + 19495500 19480 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19496500 19481 1c001d36 e69ff06f jal x0, -408 + 19499500 19484 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19518500 19503 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19519500 19504 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19522500 19507 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19523500 19508 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19524500 19509 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19526500 19511 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19527500 19512 1c001778 fddff06f jal x0, -36 + 19529500 19514 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19530500 19515 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19531500 19516 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19532500 19517 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19533500 19518 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19534500 19519 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19535500 19520 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19536500 19521 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19537500 19522 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19538500 19523 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a0 + 19542500 19527 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19543500 19528 1c001bca 16a0006f jal x0, 362 + 19545500 19530 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19546500 19531 1c001d36 e69ff06f jal x0, -408 + 19549500 19534 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19596500 19581 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19597500 19582 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19600500 19585 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19601500 19586 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19602500 19587 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19604500 19589 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19605500 19590 1c001778 fddff06f jal x0, -36 + 19607500 19592 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19608500 19593 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19609500 19594 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19610500 19595 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19611500 19596 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19612500 19597 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19613500 19598 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19614500 19599 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19615500 19600 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19616500 19601 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1041a0 + 19620500 19605 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19621500 19606 1c001bca 16a0006f jal x0, 362 + 19623500 19608 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19624500 19609 1c001d36 e69ff06f jal x0, -408 + 19627500 19612 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19642500 19627 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19643500 19628 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19646500 19631 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19647500 19632 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19648500 19633 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19650500 19635 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19651500 19636 1c001778 fddff06f jal x0, -36 + 19653500 19638 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19654500 19639 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19655500 19640 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19656500 19641 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19657500 19642 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19658500 19643 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19659500 19644 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19660500 19645 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19661500 19646 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19662500 19647 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1041a0 + 19666500 19651 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19667500 19652 1c001bca 16a0006f jal x0, 362 + 19669500 19654 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19670500 19655 1c001d36 e69ff06f jal x0, -408 + 19673500 19658 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19687500 19672 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19688500 19673 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19691500 19676 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19692500 19677 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19693500 19678 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19695500 19680 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19696500 19681 1c001778 fddff06f jal x0, -36 + 19698500 19683 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19699500 19684 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19700500 19685 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19701500 19686 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19702500 19687 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19703500 19688 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19704500 19689 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19705500 19690 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19706500 19691 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19707500 19692 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1041a0 + 19711500 19696 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19712500 19697 1c001bca 16a0006f jal x0, 362 + 19714500 19699 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19715500 19700 1c001d36 e69ff06f jal x0, -408 + 19718500 19703 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19732500 19717 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19733500 19718 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19736500 19721 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19737500 19722 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19738500 19723 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19740500 19725 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19741500 19726 1c001778 fddff06f jal x0, -36 + 19743500 19728 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19744500 19729 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19745500 19730 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19746500 19731 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19747500 19732 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19748500 19733 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19749500 19734 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19750500 19735 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19751500 19736 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19752500 19737 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a0 + 19756500 19741 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19757500 19742 1c001bca 16a0006f jal x0, 362 + 19759500 19744 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19760500 19745 1c001d36 e69ff06f jal x0, -408 + 19763500 19748 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19777500 19762 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19778500 19763 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19781500 19766 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19782500 19767 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19783500 19768 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19785500 19770 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19786500 19771 1c001778 fddff06f jal x0, -36 + 19788500 19773 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19789500 19774 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19790500 19775 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19791500 19776 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19792500 19777 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19793500 19778 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19794500 19779 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19795500 19780 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19796500 19781 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19797500 19782 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1041a0 + 19801500 19786 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19802500 19787 1c001bca 16a0006f jal x0, 362 + 19804500 19789 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19805500 19790 1c001d36 e69ff06f jal x0, -408 + 19808500 19793 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19822500 19807 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19823500 19808 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19826500 19811 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19827500 19812 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19828500 19813 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19830500 19815 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19831500 19816 1c001778 fddff06f jal x0, -36 + 19833500 19818 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19834500 19819 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19835500 19820 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19836500 19821 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19837500 19822 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19838500 19823 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19839500 19824 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19840500 19825 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19841500 19826 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19842500 19827 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1041a0 + 19846500 19831 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19847500 19832 1c001bca 16a0006f jal x0, 362 + 19849500 19834 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19850500 19835 1c001d36 e69ff06f jal x0, -408 + 19853500 19838 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19871500 19856 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19872500 19857 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19875500 19860 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19876500 19861 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19877500 19862 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19879500 19864 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19880500 19865 1c001778 fddff06f jal x0, -36 + 19882500 19867 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19883500 19868 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19884500 19869 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19885500 19870 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19886500 19871 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19887500 19872 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19888500 19873 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19889500 19874 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19890500 19875 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19891500 19876 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1041a0 + 19895500 19880 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19896500 19881 1c001bca 16a0006f jal x0, 362 + 19898500 19883 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19899500 19884 1c001d36 e69ff06f jal x0, -408 + 19902500 19887 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19919500 19904 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19920500 19905 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19923500 19908 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19924500 19909 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19925500 19910 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19927500 19912 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19928500 19913 1c001778 fddff06f jal x0, -36 + 19930500 19915 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19931500 19916 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19932500 19917 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19933500 19918 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19934500 19919 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19935500 19920 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19936500 19921 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19937500 19922 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19938500 19923 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19939500 19924 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041a0 + 19943500 19928 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19944500 19929 1c001bca 16a0006f jal x0, 362 + 19946500 19931 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19947500 19932 1c001d36 e69ff06f jal x0, -408 + 19950500 19935 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19969500 19954 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19970500 19955 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19973500 19958 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19974500 19959 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19975500 19960 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19977500 19962 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19978500 19963 1c001778 fddff06f jal x0, -36 + 19980500 19965 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19981500 19966 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 19982500 19967 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19983500 19968 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 19984500 19969 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 19985500 19970 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 19986500 19971 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 19987500 19972 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 19988500 19973 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19989500 19974 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a0 + 19993500 19978 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19994500 19979 1c001bca 16a0006f jal x0, 362 + 19996500 19981 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 19997500 19982 1c001d36 e69ff06f jal x0, -408 + 20000500 19985 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 20017500 20002 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 20018500 20003 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20021500 20006 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20022500 20007 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20023500 20008 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20025500 20010 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20026500 20011 1c001778 fddff06f jal x0, -36 + 20028500 20013 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20029500 20014 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 20030500 20015 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20031500 20016 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 20032500 20017 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 20033500 20018 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 20034500 20019 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 20035500 20020 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 20036500 20021 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20037500 20022 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1041a0 + 20041500 20026 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20042500 20027 1c001bca 16a0006f jal x0, 362 + 20044500 20029 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20045500 20030 1c001d36 e69ff06f jal x0, -408 + 20048500 20033 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20063500 20048 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20064500 20049 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20067500 20052 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20070500 20055 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cff360 PA:10cff364 + 20071500 20056 1c001bd0 00012423 sw x0, 8(x2) x2:10cff360 PA:10cff368 + 20072500 20057 1c001bd2 00010623 sb x0, 12(x2) x2:10cff360 PA:10cff36c + 20073500 20058 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20074500 20059 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20091500 20076 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20092500 20077 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cff360 PA:10cff364 + 20098500 20083 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20099500 20084 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20100500 20085 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20101500 20086 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20102500 20087 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20113500 20098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20114500 20099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20115500 20100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20138500 20123 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20139500 20124 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20156500 20141 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20157500 20142 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20158500 20143 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cff360 PA:10cff370 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cff3e8 x8:10cff3e4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cff3e4 PA:10cff3e4 + 20489500 20474 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cff364 x2:10cff360 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cff378 x11:10cff364 PA:10cff374 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff364 PA:10cff370 + 20578500 20563 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20579500 20564 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20613500 20598 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20614500 20599 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20615500 20600 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20616500 20601 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20619500 20604 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff364 PA:10cff370 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cff378 PA:10cff378 + 20785500 20770 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20786500 20771 1c001a5e 00168693 addi x13, x13, 1 x13=10cff379 x13:10cff378 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cff379 PA:10cff379 + 20806500 20791 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20807500 20792 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cff364 x2:10cff360 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cff340 x2:10cff360 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cff3e4 x2:10cff340 PA:10cff358 + 20853500 20838 1c001a66 01062783 lw x15, 16(x12) x15=10cff378 x12:10cff364 PA:10cff374 + 20854500 20839 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cff364 PA:10cff368 + 20855500 20840 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cff340 PA:10cff354 + 20856500 20841 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cff340 PA:10cff350 + 20857500 20842 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cff340 PA:10cff34c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cff340 PA:10cff35c + 20873500 20858 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cff340 PA:10cff348 + 20874500 20859 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20875500 20860 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20876500 20861 1c001a78 00c004b3 add x9, x0, x12 x9=10cff364 x12:10cff364 + 20877500 20862 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cff379 x15:10cff378 PA:10cff378 + 20879500 20864 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cff364 PA:10cff36c + 20896500 20881 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20899500 20884 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cff364 PA:10cff36c + 20983500 20968 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 21003500 20988 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21004500 20989 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cff378 x9:10cff364 PA:10cff374 + 21045500 21030 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cff379 x20:10cff378 PA:10cff378 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a1041a0 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cff37a x20:10cff379 PA:10cff379 + 21126500 21111 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21127500 21112 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 21129500 21114 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21130500 21115 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cff340 PA:10cff35c + 21159500 21144 1c001b02 01812403 lw x8, 24(x2) x8=10cff3e4 x2:10cff340 PA:10cff358 + 21160500 21145 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cff340 PA:10cff354 + 21161500 21146 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cff340 PA:10cff350 + 21162500 21147 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cff340 PA:10cff34c + 21163500 21148 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cff340 PA:10cff348 + 21164500 21149 1c001b0c 02010113 addi x2, x2, 32 x2=10cff360 x2:10cff340 + 21165500 21150 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cff3e8 x24:10cff3e8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21207500 21192 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21208500 21193 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21211500 21196 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21212500 21197 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21213500 21198 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21215500 21200 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21216500 21201 1c001778 fddff06f jal x0, -36 + 21218500 21203 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21219500 21204 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 21220500 21205 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21221500 21206 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 21222500 21207 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 21223500 21208 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 21224500 21209 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 21225500 21210 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 21226500 21211 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21227500 21212 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041a0 + 21231500 21216 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21232500 21217 1c001bca 16a0006f jal x0, 362 + 21234500 21219 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21235500 21220 1c001d36 e69ff06f jal x0, -408 + 21238500 21223 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21252500 21237 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21253500 21238 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21256500 21241 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21257500 21242 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21258500 21243 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21260500 21245 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21261500 21246 1c001778 fddff06f jal x0, -36 + 21263500 21248 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21264500 21249 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 21265500 21250 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21266500 21251 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 21267500 21252 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 21268500 21253 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 21269500 21254 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 21270500 21255 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 21271500 21256 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21272500 21257 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a0 + 21276500 21261 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21277500 21262 1c001bca 16a0006f jal x0, 362 + 21279500 21264 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21280500 21265 1c001d36 e69ff06f jal x0, -408 + 21283500 21268 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21300500 21285 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21301500 21286 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21304500 21289 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21307500 21292 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cff360 PA:10cff364 + 21308500 21293 1c001bd0 00012423 sw x0, 8(x2) x2:10cff360 PA:10cff368 + 21309500 21294 1c001bd2 00010623 sb x0, 12(x2) x2:10cff360 PA:10cff36c + 21310500 21295 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21311500 21296 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21312500 21297 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21313500 21298 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cff360 PA:10cff364 + 21314500 21299 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21315500 21300 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21316500 21301 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21317500 21302 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21318500 21303 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21319500 21304 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21320500 21305 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21321500 21306 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21335500 21320 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21336500 21321 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21339500 21324 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21340500 21325 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21341500 21326 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21344500 21329 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21347500 21332 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21350500 21335 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21353500 21338 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21354500 21339 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21355500 21340 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21356500 21341 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21359500 21344 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21360500 21345 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21363500 21348 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21364500 21349 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21367500 21352 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21369500 21354 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21372500 21357 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21373500 21358 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21376500 21361 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21377500 21362 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21378500 21363 1c001f42 e09ff06f jal x0, -504 + 21380500 21365 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21381500 21366 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cff360 PA:10cff370 + 21382500 21367 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21385500 21370 1c001e34 00440c13 addi x24, x8, 4 x24=10cff3ec x8:10cff3e8 + 21386500 21371 1c001e38 00042503 lw x10, 0(x8) x10=00000004 x8:10cff3e8 PA:10cff3e8 + 21387500 21372 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21390500 21375 1c001e54 00055863 bge x10, x0, 16 x10:00000004 + 21393500 21378 1c001e64 00410593 addi x11, x2, 4 x11=10cff364 x2:10cff360 + 21394500 21379 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21396500 21381 1c0019fe 0105a683 lw x13, 16(x11) x13=10cff378 x11:10cff364 PA:10cff374 + 21397500 21382 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff364 PA:10cff370 + 21398500 21383 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21399500 21384 1c001a04 02f55633 divu x12, x10, x15 x12=00000004 x10:00000004 x15:00000001 + 21433500 21418 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000004 x14:0000000a + 21434500 21419 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21435500 21420 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21436500 21421 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21439500 21424 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff364 PA:10cff370 + 21440500 21425 1c001a20 02f55833 divu x16, x10, x15 x16=00000004 x10:00000004 x15:00000001 + 21474500 21459 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000004 x15:00000001 + 21508500 21493 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21539500 21524 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21540500 21525 1c001a2e 01004663 blt x0, x16, 12 x16:00000004 + 21543500 21528 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21545500 21530 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000004 + 21548500 21533 1c001a56 01070733 add x14, x14, x16 x14=00000034 x14:00000030 x16:00000004 + 21549500 21534 1c001a58 00e68023 sb x14, 0(x13) x14:00000034 x13:10cff378 PA:10cff378 + 21551500 21536 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21552500 21537 1c001a5e 00168693 addi x13, x13, 1 x13=10cff379 x13:10cff378 + 21553500 21538 1c001a60 fb1ff06f jal x0, -80 + 21555500 21540 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21556500 21541 1c001a12 00068023 sb x0, 0(x13) x13:10cff379 PA:10cff379 + 21557500 21542 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21559500 21544 1c001e68 f17ff06f jal x0, -234 + 21561500 21546 1c001d7e 00410613 addi x12, x2, 4 x12=10cff364 x2:10cff360 + 21562500 21547 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21563500 21548 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21564500 21549 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21566500 21551 1c001a62 fe010113 addi x2, x2, -32 x2=10cff340 x2:10cff360 + 21567500 21552 1c001a64 00812c23 sw x8, 24(x2) x8:10cff3e8 x2:10cff340 PA:10cff358 + 21568500 21553 1c001a66 01062783 lw x15, 16(x12) x15=10cff378 x12:10cff364 PA:10cff374 + 21569500 21554 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cff364 PA:10cff368 + 21570500 21555 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cff340 PA:10cff354 + 21571500 21556 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cff340 PA:10cff350 + 21572500 21557 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cff340 PA:10cff34c + 21573500 21558 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cff340 PA:10cff35c + 21574500 21559 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cff340 PA:10cff348 + 21575500 21560 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21576500 21561 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21577500 21562 1c001a78 00c004b3 add x9, x0, x12 x9=10cff364 x12:10cff364 + 21578500 21563 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000034 x15=10cff379 x15:10cff378 PA:10cff378 + 21580500 21565 1c001a7e 00070363 beq x14, x0, 6 x14:00000034 + 21581500 21566 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21582500 21567 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cff364 PA:10cff36c + 21584500 21569 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21587500 21572 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 21589500 21574 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21590500 21575 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21593500 21578 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21594500 21579 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21595500 21580 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21598500 21583 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21599500 21584 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21600500 21585 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21601500 21586 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21602500 21587 1c001b36 f71ff06f jal x0, -144 + 21604500 21589 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cff364 PA:10cff36c + 21606500 21591 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21609500 21594 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 21611500 21596 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21612500 21597 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21615500 21600 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 21616500 21601 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21617500 21602 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21618500 21603 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21619500 21604 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cff378 x9:10cff364 PA:10cff374 + 21621500 21606 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000034 x20=10cff379 x20:10cff378 PA:10cff378 + 21623500 21608 1c001af0 06059763 bne x11, x0, 110 x11:00000034 + 21626500 21611 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21627500 21612 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21629500 21614 1c001776 00b00533 add x10, x0, x11 x10=00000034 x11:00000034 + 21630500 21615 1c001778 fddff06f jal x0, -36 + 21632500 21617 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21633500 21618 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 21634500 21619 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21635500 21620 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 21636500 21621 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 21637500 21622 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 21638500 21623 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 21639500 21624 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 21640500 21625 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21641500 21626 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000034 x14:1a104000 PA:1a1041a0 + 21645500 21630 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21646500 21631 1c001b62 f8bff06f jal x0, -118 + 21648500 21633 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cff37a x20:10cff379 PA:10cff379 + 21650500 21635 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21651500 21636 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff364 PA:10cff364 + 21653500 21638 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21654500 21639 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21657500 21642 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cff340 PA:10cff35c + 21658500 21643 1c001b02 01812403 lw x8, 24(x2) x8=10cff3e8 x2:10cff340 PA:10cff358 + 21659500 21644 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cff340 PA:10cff354 + 21660500 21645 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cff340 PA:10cff350 + 21661500 21646 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cff340 PA:10cff34c + 21662500 21647 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cff340 PA:10cff348 + 21663500 21648 1c001b0c 02010113 addi x2, x2, 32 x2=10cff360 x2:10cff340 + 21664500 21649 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21666500 21651 1c001d86 01800433 add x8, x0, x24 x8=10cff3ec x24:10cff3ec + 21667500 21652 1c001d88 fadff06f jal x0, -84 + 21669500 21654 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21670500 21655 1c001d36 e69ff06f jal x0, -408 + 21673500 21658 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21687500 21672 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21688500 21673 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21691500 21676 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21692500 21677 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21693500 21678 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21695500 21680 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21696500 21681 1c001778 fddff06f jal x0, -36 + 21698500 21683 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21699500 21684 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 21700500 21685 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21701500 21686 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 21702500 21687 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 21703500 21688 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 21704500 21689 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 21705500 21690 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 21706500 21691 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21707500 21692 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1041a0 + 21711500 21696 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21712500 21697 1c001bca 16a0006f jal x0, 362 + 21714500 21699 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21715500 21700 1c001d36 e69ff06f jal x0, -408 + 21718500 21703 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21734500 21719 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21735500 21720 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21738500 21723 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21739500 21724 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21740500 21725 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21742500 21727 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21743500 21728 1c001778 fddff06f jal x0, -36 + 21745500 21730 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21746500 21731 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 21747500 21732 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21748500 21733 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 21749500 21734 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 21750500 21735 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 21751500 21736 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 21752500 21737 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 21753500 21738 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21754500 21739 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1041a0 + 21758500 21743 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21759500 21744 1c001bca 16a0006f jal x0, 362 + 21761500 21746 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21762500 21747 1c001d36 e69ff06f jal x0, -408 + 21765500 21750 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21782500 21767 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21783500 21768 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21786500 21771 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21787500 21772 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21788500 21773 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21790500 21775 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21791500 21776 1c001778 fddff06f jal x0, -36 + 21793500 21778 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21794500 21779 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000064 + 21795500 21780 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21796500 21781 1c00175e 00379713 slli x14, x15, 0x3 x14=00000320 x15:00000064 + 21797500 21782 1c001762 00279793 slli x15, x15, 0x2 x15=00000190 x15:00000064 + 21798500 21783 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000020 x14:00000320 + 21799500 21784 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000190 x13:00001f80 + 21800500 21785 1c00176a 00e787b3 add x15, x15, x14 x15=000001a0 x15:00000180 x14:00000020 + 21801500 21786 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21802500 21787 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1041a0 + 21806500 21791 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21807500 21792 1c001bca 16a0006f jal x0, 362 + 21809500 21794 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21810500 21795 1c001d36 e69ff06f jal x0, -408 + 21813500 21798 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21831500 21816 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21832500 21817 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21833500 21818 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cff360 PA:10cff3bc + 21834500 21819 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:10cff360 PA:10cff3b8 + 21835500 21820 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:10cff360 PA:10cff3b4 + 21836500 21821 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:10cff360 PA:10cff3b0 + 21841500 21826 1c001bb0 04c12983 lw x19, 76(x2) x19=00000004 x2:10cff360 PA:10cff3ac + 21844500 21829 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:10cff360 PA:10cff3a8 + 21845500 21830 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:10cff360 PA:10cff3a4 + 21846500 21831 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:10cff360 PA:10cff3a0 + 21847500 21832 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:10cff360 PA:10cff39c + 21848500 21833 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:10cff360 PA:10cff398 + 21849500 21834 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:10cff360 PA:10cff394 + 21850500 21835 1c001bbe 06010113 addi x2, x2, 96 x2=10cff3c0 x2:10cff360 + 21851500 21836 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21853500 21838 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:10cff3c0 PA:10cff3dc + 21854500 21839 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21855500 21840 1c001838 04010113 addi x2, x2, 64 x2=10cff400 x2:10cff3c0 + 21856500 21841 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21858500 21843 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_5.log b/sw/scripts/tracevis/example/traces/trace_core_03_5.log new file mode 100644 index 0000000..a522774 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_5.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000065 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000005 x10:00000065 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000065 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000005 + 17052500 17037 1c0000a6 05a0206f jal x0, 8282 + 17070500 17055 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17071500 17056 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17072500 17057 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17073500 17058 1c00210c 0e059163 bne x11, x0, 226 x11:00000005 + 17125500 17110 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 17126500 17111 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000065 + 17127500 17112 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000005 x19:00000065 + 17128500 17113 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 17147500 17132 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 17148500 17133 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 17149500 17134 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 17150500 17135 1c00220a 0060006f jal x0, 6 + 17169500 17154 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18817500 18802 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18836500 18821 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18837500 18822 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18862500 18847 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18863500 18848 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18865500 18850 1c00222c 08096283 p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080 + 18895500 18880 1c002230 02a98533 mul x10, x19, x10 x10=00001400 x19:00000005 x10:00000400 + 18896500 18881 1c002234 00550133 add x2, x10, x5 x2=10cff800 x10:00001400 x5:10cfe400 + 18897500 18882 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18899500 18884 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18936500 18921 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18944500 18929 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18945500 18930 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18946500 18931 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18947500 18932 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18965500 18950 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000065 + 18986500 18971 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18987500 18972 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000003 x12:00000065 + 18988500 18973 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003 + 18989500 18974 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000005 x12:00000065 + 18990500 18975 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18991500 18976 1c0009d4 63d0006f jal x0, 3644 + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cff7c0 x2:10cff800 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cff7c0 PA:10cff7e4 + 19024500 19009 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19025500 19010 1c001818 02c12423 sw x12, 40(x2) x12:00000005 x2:10cff7c0 PA:10cff7e8 + 19026500 19011 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cff7c0 PA:10cff7ec + 19027500 19012 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19028500 19013 1c00181e 02410693 addi x13, x2, 36 x13=10cff7e4 x2:10cff7c0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:10cff7c0 PA:10cff7dc + 19049500 19034 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:10cff7c0 PA:10cff7f0 + 19050500 19035 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:10cff7c0 PA:10cff7f4 + 19051500 19036 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cff7c0 PA:10cff7f8 + 19052500 19037 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cff7c0 PA:10cff7fc + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cff7e4 x2:10cff7c0 PA:10cff7cc + 19073500 19058 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cff760 x2:10cff7c0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cff778 x2:10cff760 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:10cff760 PA:10cff7b8 + 19098500 19083 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:10cff760 PA:10cff7b0 + 19099500 19084 1c001b78 05312623 sw x19, 76(x2) x19:00000005 x2:10cff760 PA:10cff7ac + 19100500 19085 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:10cff760 PA:10cff7a8 + 19101500 19086 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:10cff760 PA:10cff7a4 + 19102500 19087 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:10cff760 PA:10cff7a0 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:10cff760 PA:10cff79c + 19121500 19106 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cff760 PA:10cff7bc + 19122500 19107 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:10cff760 PA:10cff7b4 + 19123500 19108 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:10cff760 PA:10cff798 + 19124500 19109 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:10cff760 PA:10cff794 + 19125500 19110 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19126500 19111 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19127500 19112 1c001b8e 00d00433 add x8, x0, x13 x8=10cff7e4 x13:10cff7e4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cff778 x2:10cff760 PA:10cff774 + 19143500 19128 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19144500 19129 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19145500 19130 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19146500 19131 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19205500 19190 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19206500 19191 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19226500 19211 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19227500 19212 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19228500 19213 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1041a8 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19368500 19353 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19369500 19354 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19372500 19357 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19373500 19358 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19374500 19359 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19376500 19361 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19377500 19362 1c001778 fddff06f jal x0, -36 + 19379500 19364 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19380500 19365 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19381500 19366 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19382500 19367 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19383500 19368 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19384500 19369 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19385500 19370 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19386500 19371 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19387500 19372 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19388500 19373 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041a8 + 19392500 19377 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19393500 19378 1c001bca 16a0006f jal x0, 362 + 19395500 19380 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19396500 19381 1c001d36 e69ff06f jal x0, -408 + 19399500 19384 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19418500 19403 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19419500 19404 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19422500 19407 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19423500 19408 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19424500 19409 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19426500 19411 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19427500 19412 1c001778 fddff06f jal x0, -36 + 19429500 19414 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19430500 19415 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19431500 19416 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19432500 19417 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19433500 19418 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19434500 19419 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19435500 19420 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19436500 19421 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19437500 19422 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19438500 19423 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1041a8 + 19442500 19427 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19443500 19428 1c001bca 16a0006f jal x0, 362 + 19445500 19430 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19446500 19431 1c001d36 e69ff06f jal x0, -408 + 19449500 19434 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19478500 19463 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19479500 19464 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19482500 19467 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19483500 19468 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19484500 19469 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19486500 19471 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19487500 19472 1c001778 fddff06f jal x0, -36 + 19489500 19474 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19490500 19475 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19491500 19476 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19492500 19477 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19493500 19478 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19494500 19479 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19495500 19480 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19496500 19481 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19497500 19482 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19498500 19483 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041a8 + 19502500 19487 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19503500 19488 1c001bca 16a0006f jal x0, 362 + 19505500 19490 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19506500 19491 1c001d36 e69ff06f jal x0, -408 + 19509500 19494 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19525500 19510 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19526500 19511 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19529500 19514 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19530500 19515 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19531500 19516 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19533500 19518 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19534500 19519 1c001778 fddff06f jal x0, -36 + 19536500 19521 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19537500 19522 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19538500 19523 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19539500 19524 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19540500 19525 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19541500 19526 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19542500 19527 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19543500 19528 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19544500 19529 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19545500 19530 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a8 + 19549500 19534 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19550500 19535 1c001bca 16a0006f jal x0, 362 + 19552500 19537 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19553500 19538 1c001d36 e69ff06f jal x0, -408 + 19556500 19541 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19601500 19586 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19602500 19587 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19605500 19590 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19606500 19591 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19607500 19592 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19609500 19594 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19610500 19595 1c001778 fddff06f jal x0, -36 + 19612500 19597 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19613500 19598 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19614500 19599 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19615500 19600 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19616500 19601 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19617500 19602 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19618500 19603 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19619500 19604 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19620500 19605 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19621500 19606 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1041a8 + 19625500 19610 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19626500 19611 1c001bca 16a0006f jal x0, 362 + 19628500 19613 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19629500 19614 1c001d36 e69ff06f jal x0, -408 + 19632500 19617 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19650500 19635 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19651500 19636 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19654500 19639 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19655500 19640 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19656500 19641 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19658500 19643 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19659500 19644 1c001778 fddff06f jal x0, -36 + 19661500 19646 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19662500 19647 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19663500 19648 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19664500 19649 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19665500 19650 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19666500 19651 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19667500 19652 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19668500 19653 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19669500 19654 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19670500 19655 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1041a8 + 19674500 19659 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19675500 19660 1c001bca 16a0006f jal x0, 362 + 19677500 19662 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19678500 19663 1c001d36 e69ff06f jal x0, -408 + 19681500 19666 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19696500 19681 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19697500 19682 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19700500 19685 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19701500 19686 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19702500 19687 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19704500 19689 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19705500 19690 1c001778 fddff06f jal x0, -36 + 19707500 19692 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19708500 19693 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19709500 19694 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19710500 19695 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19711500 19696 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19712500 19697 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19713500 19698 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19714500 19699 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19715500 19700 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19716500 19701 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1041a8 + 19720500 19705 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19721500 19706 1c001bca 16a0006f jal x0, 362 + 19723500 19708 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19724500 19709 1c001d36 e69ff06f jal x0, -408 + 19727500 19712 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19741500 19726 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19742500 19727 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19745500 19730 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19746500 19731 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19747500 19732 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19749500 19734 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19750500 19735 1c001778 fddff06f jal x0, -36 + 19752500 19737 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19753500 19738 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19754500 19739 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19755500 19740 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19756500 19741 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19757500 19742 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19758500 19743 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19759500 19744 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19760500 19745 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19761500 19746 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a8 + 19765500 19750 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19766500 19751 1c001bca 16a0006f jal x0, 362 + 19768500 19753 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19769500 19754 1c001d36 e69ff06f jal x0, -408 + 19772500 19757 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19786500 19771 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19787500 19772 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19790500 19775 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19791500 19776 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19792500 19777 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19794500 19779 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19795500 19780 1c001778 fddff06f jal x0, -36 + 19797500 19782 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19798500 19783 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19799500 19784 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19800500 19785 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19801500 19786 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19802500 19787 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19803500 19788 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19804500 19789 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19805500 19790 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19806500 19791 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1041a8 + 19810500 19795 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19811500 19796 1c001bca 16a0006f jal x0, 362 + 19813500 19798 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19814500 19799 1c001d36 e69ff06f jal x0, -408 + 19817500 19802 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19835500 19820 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19836500 19821 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19839500 19824 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19840500 19825 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19841500 19826 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19843500 19828 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19844500 19829 1c001778 fddff06f jal x0, -36 + 19846500 19831 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19847500 19832 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19848500 19833 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19849500 19834 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19850500 19835 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19851500 19836 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19852500 19837 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19853500 19838 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19854500 19839 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19855500 19840 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1041a8 + 19859500 19844 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19860500 19845 1c001bca 16a0006f jal x0, 362 + 19862500 19847 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19863500 19848 1c001d36 e69ff06f jal x0, -408 + 19866500 19851 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19880500 19865 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19881500 19866 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19884500 19869 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19885500 19870 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19886500 19871 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19888500 19873 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19889500 19874 1c001778 fddff06f jal x0, -36 + 19891500 19876 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19892500 19877 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19893500 19878 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19894500 19879 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19895500 19880 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19896500 19881 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19897500 19882 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19898500 19883 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19899500 19884 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19900500 19885 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1041a8 + 19904500 19889 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19905500 19890 1c001bca 16a0006f jal x0, 362 + 19907500 19892 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19908500 19893 1c001d36 e69ff06f jal x0, -408 + 19911500 19896 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19926500 19911 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19927500 19912 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19930500 19915 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19931500 19916 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19932500 19917 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19934500 19919 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19935500 19920 1c001778 fddff06f jal x0, -36 + 19937500 19922 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19938500 19923 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19939500 19924 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19940500 19925 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19941500 19926 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19942500 19927 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19943500 19928 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19944500 19929 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19945500 19930 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19946500 19931 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041a8 + 19950500 19935 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19951500 19936 1c001bca 16a0006f jal x0, 362 + 19953500 19938 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19954500 19939 1c001d36 e69ff06f jal x0, -408 + 19957500 19942 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19972500 19957 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19973500 19958 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19976500 19961 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19977500 19962 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19978500 19963 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19980500 19965 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19981500 19966 1c001778 fddff06f jal x0, -36 + 19983500 19968 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19984500 19969 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 19985500 19970 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19986500 19971 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 19987500 19972 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 19988500 19973 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 19989500 19974 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 19990500 19975 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 19991500 19976 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19992500 19977 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a8 + 19996500 19981 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19997500 19982 1c001bca 16a0006f jal x0, 362 + 19999500 19984 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 20000500 19985 1c001d36 e69ff06f jal x0, -408 + 20003500 19988 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 20019500 20004 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 20020500 20005 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20023500 20008 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20024500 20009 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20025500 20010 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20027500 20012 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20028500 20013 1c001778 fddff06f jal x0, -36 + 20030500 20015 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20031500 20016 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 20032500 20017 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20033500 20018 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 20034500 20019 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 20035500 20020 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 20036500 20021 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 20037500 20022 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 20038500 20023 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20039500 20024 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1041a8 + 20043500 20028 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20044500 20029 1c001bca 16a0006f jal x0, 362 + 20046500 20031 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20047500 20032 1c001d36 e69ff06f jal x0, -408 + 20050500 20035 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20065500 20050 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20066500 20051 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20069500 20054 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20072500 20057 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cff760 PA:10cff764 + 20073500 20058 1c001bd0 00012423 sw x0, 8(x2) x2:10cff760 PA:10cff768 + 20074500 20059 1c001bd2 00010623 sb x0, 12(x2) x2:10cff760 PA:10cff76c + 20075500 20060 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20076500 20061 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20091500 20076 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20092500 20077 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cff760 PA:10cff764 + 20097500 20082 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20098500 20083 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20099500 20084 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20100500 20085 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20101500 20086 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20113500 20098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20114500 20099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20115500 20100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20140500 20125 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20141500 20126 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20156500 20141 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20157500 20142 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20158500 20143 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cff760 PA:10cff770 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cff7e8 x8:10cff7e4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cff7e4 PA:10cff7e4 + 20490500 20475 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cff764 x2:10cff760 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cff778 x11:10cff764 PA:10cff774 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff764 PA:10cff770 + 20579500 20564 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20580500 20565 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20614500 20599 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20615500 20600 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20616500 20601 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20617500 20602 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20620500 20605 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff764 PA:10cff770 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cff778 PA:10cff778 + 20786500 20771 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20787500 20772 1c001a5e 00168693 addi x13, x13, 1 x13=10cff779 x13:10cff778 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cff779 PA:10cff779 + 20807500 20792 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20808500 20793 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cff764 x2:10cff760 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cff740 x2:10cff760 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cff7e4 x2:10cff740 PA:10cff758 + 20854500 20839 1c001a66 01062783 lw x15, 16(x12) x15=10cff778 x12:10cff764 PA:10cff774 + 20855500 20840 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cff764 PA:10cff768 + 20856500 20841 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cff740 PA:10cff754 + 20857500 20842 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cff740 PA:10cff750 + 20858500 20843 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cff740 PA:10cff74c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cff740 PA:10cff75c + 20874500 20859 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cff740 PA:10cff748 + 20875500 20860 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20876500 20861 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20877500 20862 1c001a78 00c004b3 add x9, x0, x12 x9=10cff764 x12:10cff764 + 20878500 20863 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cff779 x15:10cff778 PA:10cff778 + 20880500 20865 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cff764 PA:10cff76c + 20897500 20882 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20900500 20885 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cff764 PA:10cff76c + 20984500 20969 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 21004500 20989 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21005500 20990 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cff778 x9:10cff764 PA:10cff774 + 21046500 21031 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cff779 x20:10cff778 PA:10cff778 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a1041a8 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cff77a x20:10cff779 PA:10cff779 + 21127500 21112 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21128500 21113 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 21130500 21115 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21131500 21116 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cff740 PA:10cff75c + 21160500 21145 1c001b02 01812403 lw x8, 24(x2) x8=10cff7e4 x2:10cff740 PA:10cff758 + 21161500 21146 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cff740 PA:10cff754 + 21162500 21147 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cff740 PA:10cff750 + 21163500 21148 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cff740 PA:10cff74c + 21164500 21149 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cff740 PA:10cff748 + 21165500 21150 1c001b0c 02010113 addi x2, x2, 32 x2=10cff760 x2:10cff740 + 21166500 21151 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cff7e8 x24:10cff7e8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21217500 21202 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21218500 21203 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21221500 21206 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21222500 21207 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21223500 21208 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21225500 21210 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21226500 21211 1c001778 fddff06f jal x0, -36 + 21228500 21213 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21229500 21214 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 21230500 21215 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21231500 21216 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 21232500 21217 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 21233500 21218 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 21234500 21219 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 21235500 21220 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 21236500 21221 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21237500 21222 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041a8 + 21241500 21226 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21242500 21227 1c001bca 16a0006f jal x0, 362 + 21244500 21229 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21245500 21230 1c001d36 e69ff06f jal x0, -408 + 21248500 21233 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21263500 21248 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21264500 21249 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21267500 21252 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21268500 21253 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21269500 21254 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21271500 21256 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21272500 21257 1c001778 fddff06f jal x0, -36 + 21274500 21259 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21275500 21260 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 21276500 21261 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21277500 21262 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 21278500 21263 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 21279500 21264 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 21280500 21265 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 21281500 21266 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 21282500 21267 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21283500 21268 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041a8 + 21287500 21272 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21288500 21273 1c001bca 16a0006f jal x0, 362 + 21290500 21275 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21291500 21276 1c001d36 e69ff06f jal x0, -408 + 21294500 21279 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21310500 21295 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21311500 21296 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21314500 21299 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21317500 21302 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cff760 PA:10cff764 + 21318500 21303 1c001bd0 00012423 sw x0, 8(x2) x2:10cff760 PA:10cff768 + 21319500 21304 1c001bd2 00010623 sb x0, 12(x2) x2:10cff760 PA:10cff76c + 21320500 21305 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21321500 21306 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21322500 21307 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21323500 21308 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cff760 PA:10cff764 + 21325500 21310 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21326500 21311 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21327500 21312 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21328500 21313 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21329500 21314 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21330500 21315 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21331500 21316 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21332500 21317 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21346500 21331 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21347500 21332 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21350500 21335 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21351500 21336 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21352500 21337 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21355500 21340 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21358500 21343 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21361500 21346 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21364500 21349 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21365500 21350 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21366500 21351 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21367500 21352 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21370500 21355 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21371500 21356 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21374500 21359 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21375500 21360 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21378500 21363 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21380500 21365 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21383500 21368 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21384500 21369 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21387500 21372 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21388500 21373 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21389500 21374 1c001f42 e09ff06f jal x0, -504 + 21391500 21376 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21392500 21377 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cff760 PA:10cff770 + 21393500 21378 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21396500 21381 1c001e34 00440c13 addi x24, x8, 4 x24=10cff7ec x8:10cff7e8 + 21397500 21382 1c001e38 00042503 lw x10, 0(x8) x10=00000005 x8:10cff7e8 PA:10cff7e8 + 21398500 21383 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21401500 21386 1c001e54 00055863 bge x10, x0, 16 x10:00000005 + 21404500 21389 1c001e64 00410593 addi x11, x2, 4 x11=10cff764 x2:10cff760 + 21405500 21390 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21407500 21392 1c0019fe 0105a683 lw x13, 16(x11) x13=10cff778 x11:10cff764 PA:10cff774 + 21408500 21393 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff764 PA:10cff770 + 21409500 21394 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21410500 21395 1c001a04 02f55633 divu x12, x10, x15 x12=00000005 x10:00000005 x15:00000001 + 21444500 21429 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000005 x14:0000000a + 21445500 21430 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21446500 21431 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21447500 21432 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21450500 21435 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cff764 PA:10cff770 + 21451500 21436 1c001a20 02f55833 divu x16, x10, x15 x16=00000005 x10:00000005 x15:00000001 + 21485500 21470 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000005 x15:00000001 + 21519500 21504 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21550500 21535 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21551500 21536 1c001a2e 01004663 blt x0, x16, 12 x16:00000005 + 21554500 21539 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21556500 21541 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000005 + 21559500 21544 1c001a56 01070733 add x14, x14, x16 x14=00000035 x14:00000030 x16:00000005 + 21560500 21545 1c001a58 00e68023 sb x14, 0(x13) x14:00000035 x13:10cff778 PA:10cff778 + 21561500 21546 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21562500 21547 1c001a5e 00168693 addi x13, x13, 1 x13=10cff779 x13:10cff778 + 21563500 21548 1c001a60 fb1ff06f jal x0, -80 + 21565500 21550 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21566500 21551 1c001a12 00068023 sb x0, 0(x13) x13:10cff779 PA:10cff779 + 21567500 21552 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21569500 21554 1c001e68 f17ff06f jal x0, -234 + 21571500 21556 1c001d7e 00410613 addi x12, x2, 4 x12=10cff764 x2:10cff760 + 21572500 21557 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21573500 21558 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21574500 21559 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21576500 21561 1c001a62 fe010113 addi x2, x2, -32 x2=10cff740 x2:10cff760 + 21577500 21562 1c001a64 00812c23 sw x8, 24(x2) x8:10cff7e8 x2:10cff740 PA:10cff758 + 21578500 21563 1c001a66 01062783 lw x15, 16(x12) x15=10cff778 x12:10cff764 PA:10cff774 + 21579500 21564 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cff764 PA:10cff768 + 21580500 21565 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cff740 PA:10cff754 + 21581500 21566 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cff740 PA:10cff750 + 21582500 21567 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cff740 PA:10cff74c + 21583500 21568 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cff740 PA:10cff75c + 21584500 21569 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cff740 PA:10cff748 + 21585500 21570 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21586500 21571 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21587500 21572 1c001a78 00c004b3 add x9, x0, x12 x9=10cff764 x12:10cff764 + 21588500 21573 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000035 x15=10cff779 x15:10cff778 PA:10cff778 + 21590500 21575 1c001a7e 00070363 beq x14, x0, 6 x14:00000035 + 21591500 21576 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21592500 21577 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cff764 PA:10cff76c + 21594500 21579 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21597500 21582 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 21599500 21584 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21600500 21585 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21603500 21588 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21604500 21589 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21605500 21590 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21608500 21593 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21609500 21594 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21610500 21595 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21611500 21596 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21612500 21597 1c001b36 f71ff06f jal x0, -144 + 21614500 21599 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cff764 PA:10cff76c + 21616500 21601 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21619500 21604 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 21621500 21606 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21622500 21607 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21625500 21610 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 21626500 21611 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21627500 21612 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21628500 21613 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21629500 21614 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cff778 x9:10cff764 PA:10cff774 + 21631500 21616 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000035 x20=10cff779 x20:10cff778 PA:10cff778 + 21633500 21618 1c001af0 06059763 bne x11, x0, 110 x11:00000035 + 21636500 21621 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21637500 21622 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21639500 21624 1c001776 00b00533 add x10, x0, x11 x10=00000035 x11:00000035 + 21640500 21625 1c001778 fddff06f jal x0, -36 + 21642500 21627 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21643500 21628 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 21644500 21629 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21645500 21630 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 21646500 21631 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 21647500 21632 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 21648500 21633 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 21649500 21634 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 21650500 21635 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21651500 21636 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000035 x14:1a104000 PA:1a1041a8 + 21655500 21640 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21656500 21641 1c001b62 f8bff06f jal x0, -118 + 21658500 21643 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cff77a x20:10cff779 PA:10cff779 + 21660500 21645 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21661500 21646 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cff764 PA:10cff764 + 21663500 21648 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21664500 21649 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21667500 21652 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cff740 PA:10cff75c + 21668500 21653 1c001b02 01812403 lw x8, 24(x2) x8=10cff7e8 x2:10cff740 PA:10cff758 + 21669500 21654 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cff740 PA:10cff754 + 21670500 21655 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cff740 PA:10cff750 + 21671500 21656 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cff740 PA:10cff74c + 21672500 21657 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cff740 PA:10cff748 + 21673500 21658 1c001b0c 02010113 addi x2, x2, 32 x2=10cff760 x2:10cff740 + 21674500 21659 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21676500 21661 1c001d86 01800433 add x8, x0, x24 x8=10cff7ec x24:10cff7ec + 21677500 21662 1c001d88 fadff06f jal x0, -84 + 21679500 21664 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21680500 21665 1c001d36 e69ff06f jal x0, -408 + 21683500 21668 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21697500 21682 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21698500 21683 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21701500 21686 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21702500 21687 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21703500 21688 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21705500 21690 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21706500 21691 1c001778 fddff06f jal x0, -36 + 21708500 21693 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21709500 21694 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 21710500 21695 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21711500 21696 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 21712500 21697 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 21713500 21698 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 21714500 21699 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 21715500 21700 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 21716500 21701 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21717500 21702 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1041a8 + 21721500 21706 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21722500 21707 1c001bca 16a0006f jal x0, 362 + 21724500 21709 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21725500 21710 1c001d36 e69ff06f jal x0, -408 + 21728500 21713 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21742500 21727 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21743500 21728 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21746500 21731 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21747500 21732 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21748500 21733 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21750500 21735 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21751500 21736 1c001778 fddff06f jal x0, -36 + 21753500 21738 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21754500 21739 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 21755500 21740 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21756500 21741 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 21757500 21742 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 21758500 21743 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 21759500 21744 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 21760500 21745 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 21761500 21746 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21762500 21747 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1041a8 + 21766500 21751 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21767500 21752 1c001bca 16a0006f jal x0, 362 + 21769500 21754 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21770500 21755 1c001d36 e69ff06f jal x0, -408 + 21773500 21758 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21787500 21772 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21788500 21773 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21791500 21776 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21792500 21777 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21793500 21778 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21795500 21780 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21796500 21781 1c001778 fddff06f jal x0, -36 + 21798500 21783 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21799500 21784 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000065 + 21800500 21785 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21801500 21786 1c00175e 00379713 slli x14, x15, 0x3 x14=00000328 x15:00000065 + 21802500 21787 1c001762 00279793 slli x15, x15, 0x2 x15=00000194 x15:00000065 + 21803500 21788 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000028 x14:00000328 + 21804500 21789 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000194 x13:00001f80 + 21805500 21790 1c00176a 00e787b3 add x15, x15, x14 x15=000001a8 x15:00000180 x14:00000028 + 21806500 21791 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21807500 21792 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1041a8 + 21811500 21796 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21812500 21797 1c001bca 16a0006f jal x0, 362 + 21814500 21799 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21815500 21800 1c001d36 e69ff06f jal x0, -408 + 21818500 21803 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21832500 21817 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21833500 21818 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21834500 21819 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cff760 PA:10cff7bc + 21835500 21820 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:10cff760 PA:10cff7b8 + 21836500 21821 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:10cff760 PA:10cff7b4 + 21837500 21822 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:10cff760 PA:10cff7b0 + 21841500 21826 1c001bb0 04c12983 lw x19, 76(x2) x19=00000005 x2:10cff760 PA:10cff7ac + 21845500 21830 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:10cff760 PA:10cff7a8 + 21846500 21831 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:10cff760 PA:10cff7a4 + 21847500 21832 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:10cff760 PA:10cff7a0 + 21848500 21833 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:10cff760 PA:10cff79c + 21849500 21834 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:10cff760 PA:10cff798 + 21850500 21835 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:10cff760 PA:10cff794 + 21851500 21836 1c001bbe 06010113 addi x2, x2, 96 x2=10cff7c0 x2:10cff760 + 21852500 21837 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21854500 21839 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:10cff7c0 PA:10cff7dc + 21856500 21841 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21857500 21842 1c001838 04010113 addi x2, x2, 64 x2=10cff800 x2:10cff7c0 + 21858500 21843 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21860500 21845 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_6.log b/sw/scripts/tracevis/example/traces/trace_core_03_6.log new file mode 100644 index 0000000..d62db0c --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_6.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000066 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000006 x10:00000066 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000066 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000006 + 17052500 17037 1c0000a6 05a0206f jal x0, 8282 + 17070500 17055 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17071500 17056 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17072500 17057 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17073500 17058 1c00210c 0e059163 bne x11, x0, 226 x11:00000006 + 17125500 17110 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 17126500 17111 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000066 + 17127500 17112 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000006 x19:00000066 + 17128500 17113 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 17147500 17132 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 17148500 17133 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 17149500 17134 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 17150500 17135 1c00220a 0060006f jal x0, 6 + 17169500 17154 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18817500 18802 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18836500 18821 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18837500 18822 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18862500 18847 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18863500 18848 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18865500 18850 1c00222c 08096283 p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080 + 18895500 18880 1c002230 02a98533 mul x10, x19, x10 x10=00001800 x19:00000006 x10:00000400 + 18896500 18881 1c002234 00550133 add x2, x10, x5 x2=10cffc00 x10:00001800 x5:10cfe400 + 18897500 18882 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18899500 18884 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18936500 18921 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18944500 18929 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18945500 18930 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18946500 18931 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18947500 18932 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18965500 18950 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000066 + 18986500 18971 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18987500 18972 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000003 x12:00000066 + 18988500 18973 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003 + 18989500 18974 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000006 x12:00000066 + 18990500 18975 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18991500 18976 1c0009d4 63d0006f jal x0, 3644 + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cffbc0 x2:10cffc00 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cffbc0 PA:10cffbe4 + 19027500 19012 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19028500 19013 1c001818 02c12423 sw x12, 40(x2) x12:00000006 x2:10cffbc0 PA:10cffbe8 + 19029500 19014 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cffbc0 PA:10cffbec + 19030500 19015 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19031500 19016 1c00181e 02410693 addi x13, x2, 36 x13=10cffbe4 x2:10cffbc0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:10cffbc0 PA:10cffbdc + 19054500 19039 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:10cffbc0 PA:10cffbf0 + 19055500 19040 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:10cffbc0 PA:10cffbf4 + 19056500 19041 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cffbc0 PA:10cffbf8 + 19057500 19042 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cffbc0 PA:10cffbfc + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cffbe4 x2:10cffbc0 PA:10cffbcc + 19079500 19064 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cffb60 x2:10cffbc0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cffb78 x2:10cffb60 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:10cffb60 PA:10cffbb8 + 19099500 19084 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:10cffb60 PA:10cffbb0 + 19100500 19085 1c001b78 05312623 sw x19, 76(x2) x19:00000006 x2:10cffb60 PA:10cffbac + 19101500 19086 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:10cffb60 PA:10cffba8 + 19102500 19087 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:10cffb60 PA:10cffba4 + 19103500 19088 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:10cffb60 PA:10cffba0 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:10cffb60 PA:10cffb9c + 19116500 19101 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cffb60 PA:10cffbbc + 19117500 19102 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:10cffb60 PA:10cffbb4 + 19118500 19103 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:10cffb60 PA:10cffb98 + 19119500 19104 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:10cffb60 PA:10cffb94 + 19120500 19105 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19121500 19106 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19122500 19107 1c001b8e 00d00433 add x8, x0, x13 x8=10cffbe4 x13:10cffbe4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cffb78 x2:10cffb60 PA:10cffb74 + 19144500 19129 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19145500 19130 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19146500 19131 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19147500 19132 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19207500 19192 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19208500 19193 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19226500 19211 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19227500 19212 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19228500 19213 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1041b0 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19378500 19363 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19379500 19364 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19382500 19367 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19383500 19368 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19384500 19369 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19386500 19371 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19387500 19372 1c001778 fddff06f jal x0, -36 + 19389500 19374 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19390500 19375 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19391500 19376 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19392500 19377 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19393500 19378 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19394500 19379 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19395500 19380 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19396500 19381 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19397500 19382 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19398500 19383 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041b0 + 19402500 19387 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19403500 19388 1c001bca 16a0006f jal x0, 362 + 19405500 19390 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19406500 19391 1c001d36 e69ff06f jal x0, -408 + 19409500 19394 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19438500 19423 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19439500 19424 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19442500 19427 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19443500 19428 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19444500 19429 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19446500 19431 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19447500 19432 1c001778 fddff06f jal x0, -36 + 19449500 19434 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19450500 19435 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19451500 19436 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19452500 19437 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19453500 19438 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19454500 19439 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19455500 19440 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19456500 19441 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19457500 19442 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19458500 19443 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1041b0 + 19462500 19447 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19463500 19448 1c001bca 16a0006f jal x0, 362 + 19465500 19450 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19466500 19451 1c001d36 e69ff06f jal x0, -408 + 19469500 19454 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19498500 19483 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19499500 19484 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19502500 19487 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19503500 19488 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19504500 19489 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19506500 19491 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19507500 19492 1c001778 fddff06f jal x0, -36 + 19509500 19494 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19510500 19495 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19511500 19496 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19512500 19497 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19513500 19498 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19514500 19499 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19515500 19500 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19516500 19501 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19517500 19502 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19518500 19503 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041b0 + 19522500 19507 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19523500 19508 1c001bca 16a0006f jal x0, 362 + 19525500 19510 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19526500 19511 1c001d36 e69ff06f jal x0, -408 + 19529500 19514 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19543500 19528 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19544500 19529 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19547500 19532 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19548500 19533 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19549500 19534 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19551500 19536 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19552500 19537 1c001778 fddff06f jal x0, -36 + 19554500 19539 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19555500 19540 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19556500 19541 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19557500 19542 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19558500 19543 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19559500 19544 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19560500 19545 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19561500 19546 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19562500 19547 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19563500 19548 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b0 + 19567500 19552 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19568500 19553 1c001bca 16a0006f jal x0, 362 + 19570500 19555 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19571500 19556 1c001d36 e69ff06f jal x0, -408 + 19574500 19559 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19609500 19594 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19610500 19595 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19613500 19598 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19614500 19599 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19615500 19600 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19617500 19602 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19618500 19603 1c001778 fddff06f jal x0, -36 + 19620500 19605 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19621500 19606 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19622500 19607 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19623500 19608 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19624500 19609 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19625500 19610 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19626500 19611 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19627500 19612 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19628500 19613 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19629500 19614 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1041b0 + 19633500 19618 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19634500 19619 1c001bca 16a0006f jal x0, 362 + 19636500 19621 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19637500 19622 1c001d36 e69ff06f jal x0, -408 + 19640500 19625 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19656500 19641 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19657500 19642 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19660500 19645 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19661500 19646 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19662500 19647 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19664500 19649 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19665500 19650 1c001778 fddff06f jal x0, -36 + 19667500 19652 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19668500 19653 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19669500 19654 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19670500 19655 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19671500 19656 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19672500 19657 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19673500 19658 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19674500 19659 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19675500 19660 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19676500 19661 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1041b0 + 19680500 19665 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19681500 19666 1c001bca 16a0006f jal x0, 362 + 19683500 19668 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19684500 19669 1c001d36 e69ff06f jal x0, -408 + 19687500 19672 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19702500 19687 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19703500 19688 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19706500 19691 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19707500 19692 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19708500 19693 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19710500 19695 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19711500 19696 1c001778 fddff06f jal x0, -36 + 19713500 19698 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19714500 19699 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19715500 19700 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19716500 19701 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19717500 19702 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19718500 19703 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19719500 19704 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19720500 19705 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19721500 19706 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19722500 19707 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1041b0 + 19726500 19711 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19727500 19712 1c001bca 16a0006f jal x0, 362 + 19729500 19714 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19730500 19715 1c001d36 e69ff06f jal x0, -408 + 19733500 19718 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19747500 19732 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19748500 19733 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19751500 19736 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19752500 19737 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19753500 19738 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19755500 19740 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19756500 19741 1c001778 fddff06f jal x0, -36 + 19758500 19743 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19759500 19744 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19760500 19745 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19761500 19746 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19762500 19747 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19763500 19748 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19764500 19749 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19765500 19750 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19766500 19751 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19767500 19752 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b0 + 19771500 19756 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19772500 19757 1c001bca 16a0006f jal x0, 362 + 19774500 19759 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19775500 19760 1c001d36 e69ff06f jal x0, -408 + 19778500 19763 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19793500 19778 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19794500 19779 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19797500 19782 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19798500 19783 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19799500 19784 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19801500 19786 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19802500 19787 1c001778 fddff06f jal x0, -36 + 19804500 19789 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19805500 19790 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19806500 19791 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19807500 19792 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19808500 19793 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19809500 19794 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19810500 19795 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19811500 19796 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19812500 19797 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19813500 19798 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1041b0 + 19817500 19802 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19818500 19803 1c001bca 16a0006f jal x0, 362 + 19820500 19805 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19821500 19806 1c001d36 e69ff06f jal x0, -408 + 19824500 19809 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19840500 19825 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19841500 19826 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19844500 19829 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19845500 19830 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19846500 19831 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19848500 19833 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19849500 19834 1c001778 fddff06f jal x0, -36 + 19851500 19836 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19852500 19837 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19853500 19838 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19854500 19839 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19855500 19840 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19856500 19841 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19857500 19842 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19858500 19843 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19859500 19844 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19860500 19845 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1041b0 + 19864500 19849 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19865500 19850 1c001bca 16a0006f jal x0, 362 + 19867500 19852 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19868500 19853 1c001d36 e69ff06f jal x0, -408 + 19871500 19856 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19887500 19872 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19888500 19873 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19891500 19876 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19892500 19877 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19893500 19878 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19895500 19880 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19896500 19881 1c001778 fddff06f jal x0, -36 + 19898500 19883 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19899500 19884 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19900500 19885 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19901500 19886 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19902500 19887 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19903500 19888 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19904500 19889 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19905500 19890 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19906500 19891 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19907500 19892 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1041b0 + 19911500 19896 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19912500 19897 1c001bca 16a0006f jal x0, 362 + 19914500 19899 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19915500 19900 1c001d36 e69ff06f jal x0, -408 + 19918500 19903 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19932500 19917 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19933500 19918 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19936500 19921 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19937500 19922 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19938500 19923 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19940500 19925 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19941500 19926 1c001778 fddff06f jal x0, -36 + 19943500 19928 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19944500 19929 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19945500 19930 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19946500 19931 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19947500 19932 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19948500 19933 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19949500 19934 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19950500 19935 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19951500 19936 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19952500 19937 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041b0 + 19956500 19941 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19957500 19942 1c001bca 16a0006f jal x0, 362 + 19959500 19944 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19960500 19945 1c001d36 e69ff06f jal x0, -408 + 19963500 19948 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19977500 19962 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19978500 19963 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19981500 19966 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19982500 19967 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19983500 19968 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19985500 19970 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19986500 19971 1c001778 fddff06f jal x0, -36 + 19988500 19973 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19989500 19974 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 19990500 19975 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19991500 19976 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 19992500 19977 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 19993500 19978 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 19994500 19979 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 19995500 19980 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 19996500 19981 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19997500 19982 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b0 + 20001500 19986 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20002500 19987 1c001bca 16a0006f jal x0, 362 + 20004500 19989 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 20005500 19990 1c001d36 e69ff06f jal x0, -408 + 20008500 19993 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 20024500 20009 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 20025500 20010 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20028500 20013 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20029500 20014 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20030500 20015 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20032500 20017 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20033500 20018 1c001778 fddff06f jal x0, -36 + 20035500 20020 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20036500 20021 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 20037500 20022 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20038500 20023 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 20039500 20024 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 20040500 20025 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 20041500 20026 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 20042500 20027 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 20043500 20028 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20044500 20029 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1041b0 + 20048500 20033 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20049500 20034 1c001bca 16a0006f jal x0, 362 + 20051500 20036 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20052500 20037 1c001d36 e69ff06f jal x0, -408 + 20055500 20040 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20073500 20058 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20074500 20059 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20077500 20062 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20080500 20065 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cffb60 PA:10cffb64 + 20081500 20066 1c001bd0 00012423 sw x0, 8(x2) x2:10cffb60 PA:10cffb68 + 20082500 20067 1c001bd2 00010623 sb x0, 12(x2) x2:10cffb60 PA:10cffb6c + 20083500 20068 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20084500 20069 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20091500 20076 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20092500 20077 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cffb60 PA:10cffb64 + 20093500 20078 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20094500 20079 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20095500 20080 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20096500 20081 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20097500 20082 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20113500 20098 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20114500 20099 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20115500 20100 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20142500 20127 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20143500 20128 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20156500 20141 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20157500 20142 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20158500 20143 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cffb60 PA:10cffb70 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cffbe8 x8:10cffbe4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cffbe4 PA:10cffbe4 + 20491500 20476 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cffb64 x2:10cffb60 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cffb78 x11:10cffb64 PA:10cffb74 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cffb64 PA:10cffb70 + 20580500 20565 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20581500 20566 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20615500 20600 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20616500 20601 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20617500 20602 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20618500 20603 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20621500 20606 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cffb64 PA:10cffb70 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cffb78 PA:10cffb78 + 20787500 20772 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20788500 20773 1c001a5e 00168693 addi x13, x13, 1 x13=10cffb79 x13:10cffb78 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cffb79 PA:10cffb79 + 20808500 20793 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20809500 20794 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cffb64 x2:10cffb60 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cffb40 x2:10cffb60 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cffbe4 x2:10cffb40 PA:10cffb58 + 20855500 20840 1c001a66 01062783 lw x15, 16(x12) x15=10cffb78 x12:10cffb64 PA:10cffb74 + 20856500 20841 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cffb64 PA:10cffb68 + 20857500 20842 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cffb40 PA:10cffb54 + 20858500 20843 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cffb40 PA:10cffb50 + 20859500 20844 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cffb40 PA:10cffb4c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cffb40 PA:10cffb5c + 20875500 20860 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cffb40 PA:10cffb48 + 20876500 20861 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20877500 20862 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20878500 20863 1c001a78 00c004b3 add x9, x0, x12 x9=10cffb64 x12:10cffb64 + 20879500 20864 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cffb79 x15:10cffb78 PA:10cffb78 + 20881500 20866 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cffb64 PA:10cffb6c + 20898500 20883 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20901500 20886 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cffb64 PA:10cffb6c + 20987500 20972 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 21005500 20990 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21006500 20991 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cffb78 x9:10cffb64 PA:10cffb74 + 21047500 21032 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cffb79 x20:10cffb78 PA:10cffb78 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a1041b0 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cffb7a x20:10cffb79 PA:10cffb79 + 21130500 21115 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21131500 21116 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 21133500 21118 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21134500 21119 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cffb40 PA:10cffb5c + 21161500 21146 1c001b02 01812403 lw x8, 24(x2) x8=10cffbe4 x2:10cffb40 PA:10cffb58 + 21162500 21147 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cffb40 PA:10cffb54 + 21163500 21148 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cffb40 PA:10cffb50 + 21164500 21149 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cffb40 PA:10cffb4c + 21165500 21150 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cffb40 PA:10cffb48 + 21166500 21151 1c001b0c 02010113 addi x2, x2, 32 x2=10cffb60 x2:10cffb40 + 21167500 21152 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cffbe8 x24:10cffbe8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21221500 21206 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21222500 21207 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21225500 21210 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21226500 21211 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21227500 21212 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21229500 21214 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21230500 21215 1c001778 fddff06f jal x0, -36 + 21232500 21217 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21233500 21218 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 21234500 21219 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21235500 21220 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 21236500 21221 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 21237500 21222 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 21238500 21223 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 21239500 21224 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 21240500 21225 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21241500 21226 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041b0 + 21245500 21230 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21246500 21231 1c001bca 16a0006f jal x0, 362 + 21248500 21233 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21249500 21234 1c001d36 e69ff06f jal x0, -408 + 21252500 21237 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21266500 21251 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21267500 21252 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21270500 21255 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21271500 21256 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21272500 21257 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21274500 21259 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21275500 21260 1c001778 fddff06f jal x0, -36 + 21277500 21262 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21278500 21263 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 21279500 21264 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21280500 21265 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 21281500 21266 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 21282500 21267 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 21283500 21268 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 21284500 21269 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 21285500 21270 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21286500 21271 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b0 + 21290500 21275 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21291500 21276 1c001bca 16a0006f jal x0, 362 + 21293500 21278 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21294500 21279 1c001d36 e69ff06f jal x0, -408 + 21297500 21282 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21314500 21299 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21315500 21300 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21318500 21303 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21321500 21306 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cffb60 PA:10cffb64 + 21322500 21307 1c001bd0 00012423 sw x0, 8(x2) x2:10cffb60 PA:10cffb68 + 21323500 21308 1c001bd2 00010623 sb x0, 12(x2) x2:10cffb60 PA:10cffb6c + 21324500 21309 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21325500 21310 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21326500 21311 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21327500 21312 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cffb60 PA:10cffb64 + 21328500 21313 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21329500 21314 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21330500 21315 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21331500 21316 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21332500 21317 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21333500 21318 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21334500 21319 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21335500 21320 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21349500 21334 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21350500 21335 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21353500 21338 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21354500 21339 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21355500 21340 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21358500 21343 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21361500 21346 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21364500 21349 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21367500 21352 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21368500 21353 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21369500 21354 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21370500 21355 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21373500 21358 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21374500 21359 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21377500 21362 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21378500 21363 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21381500 21366 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21383500 21368 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21386500 21371 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21387500 21372 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21390500 21375 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21391500 21376 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21392500 21377 1c001f42 e09ff06f jal x0, -504 + 21394500 21379 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21395500 21380 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cffb60 PA:10cffb70 + 21396500 21381 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21399500 21384 1c001e34 00440c13 addi x24, x8, 4 x24=10cffbec x8:10cffbe8 + 21400500 21385 1c001e38 00042503 lw x10, 0(x8) x10=00000006 x8:10cffbe8 PA:10cffbe8 + 21401500 21386 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21404500 21389 1c001e54 00055863 bge x10, x0, 16 x10:00000006 + 21407500 21392 1c001e64 00410593 addi x11, x2, 4 x11=10cffb64 x2:10cffb60 + 21408500 21393 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21410500 21395 1c0019fe 0105a683 lw x13, 16(x11) x13=10cffb78 x11:10cffb64 PA:10cffb74 + 21411500 21396 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cffb64 PA:10cffb70 + 21412500 21397 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21413500 21398 1c001a04 02f55633 divu x12, x10, x15 x12=00000006 x10:00000006 x15:00000001 + 21447500 21432 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000006 x14:0000000a + 21448500 21433 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21449500 21434 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21450500 21435 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21453500 21438 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cffb64 PA:10cffb70 + 21454500 21439 1c001a20 02f55833 divu x16, x10, x15 x16=00000006 x10:00000006 x15:00000001 + 21488500 21473 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000006 x15:00000001 + 21522500 21507 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21553500 21538 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21554500 21539 1c001a2e 01004663 blt x0, x16, 12 x16:00000006 + 21557500 21542 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21559500 21544 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000006 + 21562500 21547 1c001a56 01070733 add x14, x14, x16 x14=00000036 x14:00000030 x16:00000006 + 21563500 21548 1c001a58 00e68023 sb x14, 0(x13) x14:00000036 x13:10cffb78 PA:10cffb78 + 21564500 21549 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21565500 21550 1c001a5e 00168693 addi x13, x13, 1 x13=10cffb79 x13:10cffb78 + 21566500 21551 1c001a60 fb1ff06f jal x0, -80 + 21568500 21553 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21569500 21554 1c001a12 00068023 sb x0, 0(x13) x13:10cffb79 PA:10cffb79 + 21570500 21555 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21572500 21557 1c001e68 f17ff06f jal x0, -234 + 21574500 21559 1c001d7e 00410613 addi x12, x2, 4 x12=10cffb64 x2:10cffb60 + 21575500 21560 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21576500 21561 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21577500 21562 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21579500 21564 1c001a62 fe010113 addi x2, x2, -32 x2=10cffb40 x2:10cffb60 + 21580500 21565 1c001a64 00812c23 sw x8, 24(x2) x8:10cffbe8 x2:10cffb40 PA:10cffb58 + 21581500 21566 1c001a66 01062783 lw x15, 16(x12) x15=10cffb78 x12:10cffb64 PA:10cffb74 + 21582500 21567 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cffb64 PA:10cffb68 + 21583500 21568 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cffb40 PA:10cffb54 + 21584500 21569 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cffb40 PA:10cffb50 + 21585500 21570 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cffb40 PA:10cffb4c + 21586500 21571 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cffb40 PA:10cffb5c + 21587500 21572 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cffb40 PA:10cffb48 + 21588500 21573 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21589500 21574 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21590500 21575 1c001a78 00c004b3 add x9, x0, x12 x9=10cffb64 x12:10cffb64 + 21591500 21576 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000036 x15=10cffb79 x15:10cffb78 PA:10cffb78 + 21593500 21578 1c001a7e 00070363 beq x14, x0, 6 x14:00000036 + 21594500 21579 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21595500 21580 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cffb64 PA:10cffb6c + 21597500 21582 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21600500 21585 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 21602500 21587 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21603500 21588 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21606500 21591 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21607500 21592 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21608500 21593 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21611500 21596 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21612500 21597 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21613500 21598 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21614500 21599 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21615500 21600 1c001b36 f71ff06f jal x0, -144 + 21617500 21602 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cffb64 PA:10cffb6c + 21619500 21604 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21622500 21607 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 21624500 21609 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21625500 21610 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21628500 21613 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 21629500 21614 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21630500 21615 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21631500 21616 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21632500 21617 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cffb78 x9:10cffb64 PA:10cffb74 + 21634500 21619 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000036 x20=10cffb79 x20:10cffb78 PA:10cffb78 + 21636500 21621 1c001af0 06059763 bne x11, x0, 110 x11:00000036 + 21639500 21624 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21640500 21625 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21642500 21627 1c001776 00b00533 add x10, x0, x11 x10=00000036 x11:00000036 + 21643500 21628 1c001778 fddff06f jal x0, -36 + 21645500 21630 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21646500 21631 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 21647500 21632 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21648500 21633 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 21649500 21634 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 21650500 21635 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 21651500 21636 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 21652500 21637 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 21653500 21638 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21654500 21639 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000036 x14:1a104000 PA:1a1041b0 + 21658500 21643 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21659500 21644 1c001b62 f8bff06f jal x0, -118 + 21661500 21646 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cffb7a x20:10cffb79 PA:10cffb79 + 21663500 21648 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21664500 21649 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cffb64 PA:10cffb64 + 21666500 21651 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21667500 21652 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21670500 21655 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cffb40 PA:10cffb5c + 21671500 21656 1c001b02 01812403 lw x8, 24(x2) x8=10cffbe8 x2:10cffb40 PA:10cffb58 + 21672500 21657 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cffb40 PA:10cffb54 + 21673500 21658 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cffb40 PA:10cffb50 + 21674500 21659 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cffb40 PA:10cffb4c + 21675500 21660 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cffb40 PA:10cffb48 + 21676500 21661 1c001b0c 02010113 addi x2, x2, 32 x2=10cffb60 x2:10cffb40 + 21677500 21662 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21679500 21664 1c001d86 01800433 add x8, x0, x24 x8=10cffbec x24:10cffbec + 21680500 21665 1c001d88 fadff06f jal x0, -84 + 21682500 21667 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21683500 21668 1c001d36 e69ff06f jal x0, -408 + 21686500 21671 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21700500 21685 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21701500 21686 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21704500 21689 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21705500 21690 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21706500 21691 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21708500 21693 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21709500 21694 1c001778 fddff06f jal x0, -36 + 21711500 21696 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21712500 21697 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 21713500 21698 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21714500 21699 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 21715500 21700 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 21716500 21701 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 21717500 21702 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 21718500 21703 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 21719500 21704 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21720500 21705 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1041b0 + 21724500 21709 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21725500 21710 1c001bca 16a0006f jal x0, 362 + 21727500 21712 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21728500 21713 1c001d36 e69ff06f jal x0, -408 + 21731500 21716 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21745500 21730 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21746500 21731 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21749500 21734 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21750500 21735 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21751500 21736 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21753500 21738 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21754500 21739 1c001778 fddff06f jal x0, -36 + 21756500 21741 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21757500 21742 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 21758500 21743 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21759500 21744 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 21760500 21745 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 21761500 21746 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 21762500 21747 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 21763500 21748 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 21764500 21749 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21765500 21750 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1041b0 + 21769500 21754 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21770500 21755 1c001bca 16a0006f jal x0, 362 + 21772500 21757 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21773500 21758 1c001d36 e69ff06f jal x0, -408 + 21776500 21761 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21790500 21775 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21791500 21776 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21794500 21779 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21795500 21780 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21796500 21781 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21798500 21783 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21799500 21784 1c001778 fddff06f jal x0, -36 + 21801500 21786 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21802500 21787 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000066 + 21803500 21788 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21804500 21789 1c00175e 00379713 slli x14, x15, 0x3 x14=00000330 x15:00000066 + 21805500 21790 1c001762 00279793 slli x15, x15, 0x2 x15=00000198 x15:00000066 + 21806500 21791 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000030 x14:00000330 + 21807500 21792 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:00000198 x13:00001f80 + 21808500 21793 1c00176a 00e787b3 add x15, x15, x14 x15=000001b0 x15:00000180 x14:00000030 + 21809500 21794 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21810500 21795 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1041b0 + 21814500 21799 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21815500 21800 1c001bca 16a0006f jal x0, 362 + 21817500 21802 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21818500 21803 1c001d36 e69ff06f jal x0, -408 + 21821500 21806 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21836500 21821 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21837500 21822 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21838500 21823 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cffb60 PA:10cffbbc + 21839500 21824 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:10cffb60 PA:10cffbb8 + 21840500 21825 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:10cffb60 PA:10cffbb4 + 21841500 21826 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:10cffb60 PA:10cffbb0 + 21842500 21827 1c001bb0 04c12983 lw x19, 76(x2) x19=00000006 x2:10cffb60 PA:10cffbac + 21848500 21833 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:10cffb60 PA:10cffba8 + 21849500 21834 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:10cffb60 PA:10cffba4 + 21850500 21835 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:10cffb60 PA:10cffba0 + 21851500 21836 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:10cffb60 PA:10cffb9c + 21853500 21838 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:10cffb60 PA:10cffb98 + 21854500 21839 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:10cffb60 PA:10cffb94 + 21855500 21840 1c001bbe 06010113 addi x2, x2, 96 x2=10cffbc0 x2:10cffb60 + 21856500 21841 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21858500 21843 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:10cffbc0 PA:10cffbdc + 21859500 21844 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21860500 21845 1c001838 04010113 addi x2, x2, 64 x2=10cffc00 x2:10cffbc0 + 21861500 21846 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21863500 21848 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/example/traces/trace_core_03_7.log b/sw/scripts/tracevis/example/traces/trace_core_03_7.log new file mode 100644 index 0000000..edcf2a1 --- /dev/null +++ b/sw/scripts/tracevis/example/traces/trace_core_03_7.log @@ -0,0 +1,846 @@ + Time Cycles PC Instr Mnemonic + 17014500 16999 1c000080 0180006f jal x0, 24 + 17032500 17017 1c000098 f1402573 csrrs x10, x0, 0xf14 x10=00000067 + 17033500 17018 1c00009c 01f57593 andi x11, x10, 31 x11=00000007 x10:00000067 + 17050500 17035 1c0000a0 00555513 srli x10, x10, 0x5 x10=00000003 x10:00000067 + 17051500 17036 1c0000a2 00058463 beq x11, x0, 8 x11:00000007 + 17052500 17037 1c0000a6 05a0206f jal x0, 8282 + 17070500 17055 1c002100 000702b7 lui x5, 0x70000 x5=00070000 + 17071500 17056 1c002104 1b204337 lui x6, 0x1b204000 x6=1b204000 + 17072500 17057 1c002108 00532023 sw x5, 0(x6) x5:00070000 x6:1b204000 PA:1b204000 + 17073500 17058 1c00210c 0e059163 bne x11, x0, 226 x11:00000007 + 17125500 17110 1c0021ee 1b204937 lui x18, 0x1b204000 x18=1b204000 + 17126500 17111 1c0021f2 f14029f3 csrrs x19, x0, 0xf14 x19=00000067 + 17127500 17112 1c0021f6 01f9f993 andi x19, x19, 31 x19=00000007 x19:00000067 + 17128500 17113 1c0021fa 00000a17 auipc x20, 0x0 x20=1c0021fa + 17147500 17132 1c0021fe 012a0a13 addi x20, x20, 18 x20=1c00220c x20:1c0021fa + 17148500 17133 1c002202 00000a97 auipc x21, 0x0 x21=1c002202 + 17149500 17134 1c002206 00ea8a93 addi x21, x21, 14 x21=1c002210 x21:1c002202 + 17150500 17135 1c00220a 0060006f jal x0, 6 + 17169500 17154 1c002210 08096283 p.elw x5, 128(x18) x5=1c00222d x18:1b204000 PA:1b204080 + 18817500 18802 1c002214 08096503 p.elw x10, 128(x18) x10=00000400 x18:1b204000 PA:1b204080 + 18836500 18821 1c002218 0012f313 andi x6, x5, 1 x6=00000001 x5:1c00222d + 18837500 18822 1c00221c 00031563 bne x6, x0, 10 x6:00000001 + 18862500 18847 1c002226 000a80b3 add x1, x21, x0 x1=1c002210 x21:1c002210 + 18863500 18848 1c00222a 00028067 jalr x0, x5, 0 x5:1c00222d + 18865500 18850 1c00222c 08096283 p.elw x5, 128(x18) x5=10cfe400 x18:1b204000 PA:1b204080 + 18895500 18880 1c002230 02a98533 mul x10, x19, x10 x10=00001c00 x19:00000007 x10:00000400 + 18896500 18881 1c002234 00550133 add x2, x10, x5 x2=10d00000 x10:00001c00 x5:10cfe400 + 18897500 18882 1c002238 00008067 jalr x0, x1, 0 x1:1c002210 + 18899500 18884 1c002210 08096283 p.elw x5, 128(x18) x5=1c0009bc x18:1b204000 PA:1b204080 + 18936500 18921 1c002214 08096503 p.elw x10, 128(x18) x10=00000000 x18:1b204000 PA:1b204080 + 18944500 18929 1c002218 0012f313 andi x6, x5, 1 x6=00000000 x5:1c0009bc + 18945500 18930 1c00221c 00031563 bne x6, x0, 10 x6:00000000 + 18946500 18931 1c002220 000a00b3 add x1, x20, x0 x1=1c00220c x20:1c00220c + 18947500 18932 1c002224 00028067 jalr x0, x5, 0 x5:1c0009bc + 18965500 18950 1c0009bc f1402673 csrrs x12, x0, 0xf14 x12=00000067 + 18986500 18971 1c0009c0 1c002537 lui x10, 0x1c002000 x10=1c002000 + 18987500 18972 1c0009c4 40565593 srai x11, x12, 0x405 x11=00000003 x12:00000067 + 18988500 18973 1c0009c8 f265b5b3 p.bclr x11, x11, 25, 6 x11=00000003 x11:00000003 + 18989500 18974 1c0009cc f4563633 p.bclr x12, x12, 26, 5 x12=00000007 x12:00000067 + 18990500 18975 1c0009d0 33c50513 addi x10, x10, 828 x10=1c00233c x10:1c002000 + 18991500 18976 1c0009d4 63d0006f jal x0, 3644 + 19020500 19005 1c001810 fc010113 addi x2, x2, -64 x2=10cfffc0 x2:10d00000 + 19021500 19006 1c001812 02b12223 sw x11, 36(x2) x11:00000003 x2:10cfffc0 PA:10cfffe4 + 19028500 19013 1c001814 1c0015b7 lui x11, 0x1c001000 x11=1c001000 + 19029500 19014 1c001818 02c12423 sw x12, 40(x2) x12:00000007 x2:10cfffc0 PA:10cfffe8 + 19030500 19015 1c00181a 02d12623 sw x13, 44(x2) x13:00000000 x2:10cfffc0 PA:10cfffec + 19031500 19016 1c00181c 00a00633 add x12, x0, x10 x12=1c00233c x10:1c00233c + 19032500 19017 1c00181e 02410693 addi x13, x2, 36 x13=10cfffe4 x2:10cfffc0 + 19045500 19030 1c001820 00000513 addi x10, x0, 0 x10=00000000 + 19046500 19031 1c001822 77658593 addi x11, x11, 1910 x11=1c001776 x11:1c001000 + 19047500 19032 1c001826 00112e23 sw x1, 28(x2) x1:1c00220c x2:10cfffc0 PA:10cfffdc + 19053500 19038 1c001828 02e12823 sw x14, 48(x2) x14:00000000 x2:10cfffc0 PA:10cffff0 + 19054500 19039 1c00182a 02f12a23 sw x15, 52(x2) x15:00000000 x2:10cfffc0 PA:10cffff4 + 19055500 19040 1c00182c 03012c23 sw x16, 56(x2) x16:00000000 x2:10cfffc0 PA:10cffff8 + 19056500 19041 1c00182e 03112e23 sw x17, 60(x2) x17:00000000 x2:10cfffc0 PA:10cffffc + 19072500 19057 1c001830 00d12623 sw x13, 12(x2) x13:10cfffe4 x2:10cfffc0 PA:10cfffcc + 19077500 19062 1c001832 33e000ef jal x1, 830 x1=1c001834 + 19092500 19077 1c001b70 fa010113 addi x2, x2, -96 x2=10cfff60 x2:10cfffc0 + 19093500 19078 1c001b72 01810793 addi x15, x2, 24 x15=10cfff78 x2:10cfff60 + 19094500 19079 1c001b74 04812c23 sw x8, 88(x2) x8:00000000 x2:10cfff60 PA:10cfffb8 + 19100500 19085 1c001b76 05212823 sw x18, 80(x2) x18:1b204000 x2:10cfff60 PA:10cfffb0 + 19101500 19086 1c001b78 05312623 sw x19, 76(x2) x19:00000007 x2:10cfff60 PA:10cfffac + 19102500 19087 1c001b7a 05412423 sw x20, 72(x2) x20:1c00220c x2:10cfff60 PA:10cfffa8 + 19103500 19088 1c001b7c 05512223 sw x21, 68(x2) x21:1c002210 x2:10cfff60 PA:10cfffa4 + 19104500 19089 1c001b7e 05612023 sw x22, 64(x2) x22:00000000 x2:10cfff60 PA:10cfffa0 + 19115500 19100 1c001b80 03712e23 sw x23, 60(x2) x23:00000000 x2:10cfff60 PA:10cfff9c + 19117500 19102 1c001b82 04112e23 sw x1, 92(x2) x1:1c001834 x2:10cfff60 PA:10cfffbc + 19118500 19103 1c001b84 04912a23 sw x9, 84(x2) x9:00000000 x2:10cfff60 PA:10cfffb4 + 19119500 19104 1c001b86 03812c23 sw x24, 56(x2) x24:00000000 x2:10cfff60 PA:10cfff98 + 19120500 19105 1c001b88 03912a23 sw x25, 52(x2) x25:00000000 x2:10cfff60 PA:10cfff94 + 19121500 19106 1c001b8a 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 19122500 19107 1c001b8c 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 19123500 19108 1c001b8e 00d00433 add x8, x0, x13 x8=10cfffe4 x13:10cfffe4 + 19138500 19123 1c001b90 00f12a23 sw x15, 20(x2) x15:10cfff78 x2:10cfff60 PA:10cfff74 + 19145500 19130 1c001b92 02500a13 addi x20, x0, 37 x20=00000025 + 19146500 19131 1c001b96 02d00b93 addi x23, x0, 45 x23=0000002d + 19147500 19132 1c001b9a 00100a93 addi x21, x0, 1 x21=00000001 + 19148500 19133 1c001b9c 00500b13 addi x22, x0, 5 x22=00000005 + 19159500 19144 1c001b9e 00064583 lbu x11, 0(x12) x11=00000048 x12:1c00233c PA:1c00233c + 19209500 19194 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233d x12:1c00233c + 19210500 19195 1c001ba6 00059e63 bne x11, x0, 28 x11:00000048 + 19226500 19211 1c001bc2 01458563 beq x11, x20, 10 x11:00000048 x20:00000025 + 19227500 19212 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19228500 19213 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19255500 19240 1c001776 00b00533 add x10, x0, x11 x10=00000048 x11:00000048 + 19256500 19241 1c001778 fddff06f jal x0, -36 + 19279500 19264 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19280500 19265 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19281500 19266 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19301500 19286 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19302500 19287 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19303500 19288 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19304500 19289 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19305500 19290 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19306500 19291 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19307500 19292 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000048 x14:1a104000 PA:1a1041b8 + 19311500 19296 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19312500 19297 1c001bca 16a0006f jal x0, 362 + 19331500 19316 1c001d34 00900633 add x12, x0, x9 x12=1c00233d x9:1c00233d + 19332500 19317 1c001d36 e69ff06f jal x0, -408 + 19335500 19320 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c00233d PA:1c00233d + 19389500 19374 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233e x12:1c00233d + 19390500 19375 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19393500 19378 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19394500 19379 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19395500 19380 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19397500 19382 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19398500 19383 1c001778 fddff06f jal x0, -36 + 19400500 19385 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19401500 19386 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19402500 19387 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19403500 19388 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19404500 19389 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19405500 19390 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19406500 19391 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19407500 19392 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19408500 19393 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19409500 19394 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041b8 + 19413500 19398 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19414500 19399 1c001bca 16a0006f jal x0, 362 + 19416500 19401 1c001d34 00900633 add x12, x0, x9 x12=1c00233e x9:1c00233e + 19417500 19402 1c001d36 e69ff06f jal x0, -408 + 19420500 19405 1c001b9e 00064583 lbu x11, 0(x12) x11=00000079 x12:1c00233e PA:1c00233e + 19444500 19429 1c001ba2 00160493 addi x9, x12, 1 x9=1c00233f x12:1c00233e + 19445500 19430 1c001ba6 00059e63 bne x11, x0, 28 x11:00000079 + 19448500 19433 1c001bc2 01458563 beq x11, x20, 10 x11:00000079 x20:00000025 + 19449500 19434 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19450500 19435 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19452500 19437 1c001776 00b00533 add x10, x0, x11 x10=00000079 x11:00000079 + 19453500 19438 1c001778 fddff06f jal x0, -36 + 19455500 19440 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19456500 19441 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19457500 19442 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19458500 19443 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19459500 19444 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19460500 19445 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19461500 19446 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19462500 19447 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19463500 19448 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19464500 19449 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000079 x14:1a104000 PA:1a1041b8 + 19468500 19453 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19469500 19454 1c001bca 16a0006f jal x0, 362 + 19471500 19456 1c001d34 00900633 add x12, x0, x9 x12=1c00233f x9:1c00233f + 19472500 19457 1c001d36 e69ff06f jal x0, -408 + 19475500 19460 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00233f PA:1c00233f + 19507500 19492 1c001ba2 00160493 addi x9, x12, 1 x9=1c002340 x12:1c00233f + 19508500 19493 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 19511500 19496 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 19512500 19497 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19513500 19498 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19515500 19500 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 19516500 19501 1c001778 fddff06f jal x0, -36 + 19518500 19503 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19519500 19504 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19520500 19505 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19521500 19506 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19522500 19507 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19523500 19508 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19524500 19509 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19525500 19510 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19526500 19511 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19527500 19512 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041b8 + 19531500 19516 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19532500 19517 1c001bca 16a0006f jal x0, 362 + 19534500 19519 1c001d34 00900633 add x12, x0, x9 x12=1c002340 x9:1c002340 + 19535500 19520 1c001d36 e69ff06f jal x0, -408 + 19538500 19523 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002340 PA:1c002340 + 19557500 19542 1c001ba2 00160493 addi x9, x12, 1 x9=1c002341 x12:1c002340 + 19558500 19543 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19561500 19546 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19562500 19547 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19563500 19548 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19565500 19550 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19566500 19551 1c001778 fddff06f jal x0, -36 + 19568500 19553 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19569500 19554 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19570500 19555 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19571500 19556 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19572500 19557 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19573500 19558 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19574500 19559 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19575500 19560 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19576500 19561 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19577500 19562 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b8 + 19581500 19566 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19582500 19567 1c001bca 16a0006f jal x0, 362 + 19584500 19569 1c001d34 00900633 add x12, x0, x9 x12=1c002341 x9:1c002341 + 19585500 19570 1c001d36 e69ff06f jal x0, -408 + 19588500 19573 1c001b9e 00064583 lbu x11, 0(x12) x11=00000049 x12:1c002341 PA:1c002341 + 19611500 19596 1c001ba2 00160493 addi x9, x12, 1 x9=1c002342 x12:1c002341 + 19612500 19597 1c001ba6 00059e63 bne x11, x0, 28 x11:00000049 + 19615500 19600 1c001bc2 01458563 beq x11, x20, 10 x11:00000049 x20:00000025 + 19616500 19601 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19617500 19602 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19619500 19604 1c001776 00b00533 add x10, x0, x11 x10=00000049 x11:00000049 + 19620500 19605 1c001778 fddff06f jal x0, -36 + 19622500 19607 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19623500 19608 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19624500 19609 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19625500 19610 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19626500 19611 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19627500 19612 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19628500 19613 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19629500 19614 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19630500 19615 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19631500 19616 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000049 x14:1a104000 PA:1a1041b8 + 19635500 19620 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19636500 19621 1c001bca 16a0006f jal x0, 362 + 19638500 19623 1c001d34 00900633 add x12, x0, x9 x12=1c002342 x9:1c002342 + 19639500 19624 1c001d36 e69ff06f jal x0, -408 + 19642500 19627 1c001b9e 00064583 lbu x11, 0(x12) x11=00000027 x12:1c002342 PA:1c002342 + 19657500 19642 1c001ba2 00160493 addi x9, x12, 1 x9=1c002343 x12:1c002342 + 19658500 19643 1c001ba6 00059e63 bne x11, x0, 28 x11:00000027 + 19661500 19646 1c001bc2 01458563 beq x11, x20, 10 x11:00000027 x20:00000025 + 19662500 19647 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19663500 19648 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19665500 19650 1c001776 00b00533 add x10, x0, x11 x10=00000027 x11:00000027 + 19666500 19651 1c001778 fddff06f jal x0, -36 + 19668500 19653 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19669500 19654 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19670500 19655 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19671500 19656 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19672500 19657 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19673500 19658 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19674500 19659 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19675500 19660 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19676500 19661 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19677500 19662 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000027 x14:1a104000 PA:1a1041b8 + 19681500 19666 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19682500 19667 1c001bca 16a0006f jal x0, 362 + 19684500 19669 1c001d34 00900633 add x12, x0, x9 x12=1c002343 x9:1c002343 + 19685500 19670 1c001d36 e69ff06f jal x0, -408 + 19688500 19673 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006d x12:1c002343 PA:1c002343 + 19704500 19689 1c001ba2 00160493 addi x9, x12, 1 x9=1c002344 x12:1c002343 + 19705500 19690 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006d + 19708500 19693 1c001bc2 01458563 beq x11, x20, 10 x11:0000006d x20:00000025 + 19709500 19694 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19710500 19695 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19712500 19697 1c001776 00b00533 add x10, x0, x11 x10=0000006d x11:0000006d + 19713500 19698 1c001778 fddff06f jal x0, -36 + 19715500 19700 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19716500 19701 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19717500 19702 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19718500 19703 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19719500 19704 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19720500 19705 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19721500 19706 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19722500 19707 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19723500 19708 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19724500 19709 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006d x14:1a104000 PA:1a1041b8 + 19728500 19713 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19729500 19714 1c001bca 16a0006f jal x0, 362 + 19731500 19716 1c001d34 00900633 add x12, x0, x9 x12=1c002344 x9:1c002344 + 19732500 19717 1c001d36 e69ff06f jal x0, -408 + 19735500 19720 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002344 PA:1c002344 + 19750500 19735 1c001ba2 00160493 addi x9, x12, 1 x9=1c002345 x12:1c002344 + 19751500 19736 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19754500 19739 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19755500 19740 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19756500 19741 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19758500 19743 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19759500 19744 1c001778 fddff06f jal x0, -36 + 19761500 19746 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19762500 19747 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19763500 19748 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19764500 19749 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19765500 19750 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19766500 19751 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19767500 19752 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19768500 19753 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19769500 19754 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19770500 19755 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b8 + 19774500 19759 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19775500 19760 1c001bca 16a0006f jal x0, 362 + 19777500 19762 1c001d34 00900633 add x12, x0, x9 x12=1c002345 x9:1c002345 + 19778500 19763 1c001d36 e69ff06f jal x0, -408 + 19781500 19766 1c001b9e 00064583 lbu x11, 0(x12) x11=00000063 x12:1c002345 PA:1c002345 + 19795500 19780 1c001ba2 00160493 addi x9, x12, 1 x9=1c002346 x12:1c002345 + 19796500 19781 1c001ba6 00059e63 bne x11, x0, 28 x11:00000063 + 19799500 19784 1c001bc2 01458563 beq x11, x20, 10 x11:00000063 x20:00000025 + 19800500 19785 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19801500 19786 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19803500 19788 1c001776 00b00533 add x10, x0, x11 x10=00000063 x11:00000063 + 19804500 19789 1c001778 fddff06f jal x0, -36 + 19806500 19791 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19807500 19792 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19808500 19793 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19809500 19794 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19810500 19795 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19811500 19796 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19812500 19797 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19813500 19798 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19814500 19799 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19815500 19800 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000063 x14:1a104000 PA:1a1041b8 + 19819500 19804 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19820500 19805 1c001bca 16a0006f jal x0, 362 + 19822500 19807 1c001d34 00900633 add x12, x0, x9 x12=1c002346 x9:1c002346 + 19823500 19808 1c001d36 e69ff06f jal x0, -408 + 19826500 19811 1c001b9e 00064583 lbu x11, 0(x12) x11=0000006f x12:1c002346 PA:1c002346 + 19841500 19826 1c001ba2 00160493 addi x9, x12, 1 x9=1c002347 x12:1c002346 + 19842500 19827 1c001ba6 00059e63 bne x11, x0, 28 x11:0000006f + 19845500 19830 1c001bc2 01458563 beq x11, x20, 10 x11:0000006f x20:00000025 + 19846500 19831 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19847500 19832 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19849500 19834 1c001776 00b00533 add x10, x0, x11 x10=0000006f x11:0000006f + 19850500 19835 1c001778 fddff06f jal x0, -36 + 19852500 19837 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19853500 19838 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19854500 19839 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19855500 19840 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19856500 19841 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19857500 19842 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19858500 19843 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19859500 19844 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19860500 19845 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19861500 19846 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000006f x14:1a104000 PA:1a1041b8 + 19865500 19850 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19866500 19851 1c001bca 16a0006f jal x0, 362 + 19868500 19853 1c001d34 00900633 add x12, x0, x9 x12=1c002347 x9:1c002347 + 19869500 19854 1c001d36 e69ff06f jal x0, -408 + 19872500 19857 1c001b9e 00064583 lbu x11, 0(x12) x11=00000072 x12:1c002347 PA:1c002347 + 19890500 19875 1c001ba2 00160493 addi x9, x12, 1 x9=1c002348 x12:1c002347 + 19891500 19876 1c001ba6 00059e63 bne x11, x0, 28 x11:00000072 + 19894500 19879 1c001bc2 01458563 beq x11, x20, 10 x11:00000072 x20:00000025 + 19895500 19880 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19896500 19881 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19898500 19883 1c001776 00b00533 add x10, x0, x11 x10=00000072 x11:00000072 + 19899500 19884 1c001778 fddff06f jal x0, -36 + 19901500 19886 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19902500 19887 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19903500 19888 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19904500 19889 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19905500 19890 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19906500 19891 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19907500 19892 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19908500 19893 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19909500 19894 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19910500 19895 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000072 x14:1a104000 PA:1a1041b8 + 19914500 19899 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19915500 19900 1c001bca 16a0006f jal x0, 362 + 19917500 19902 1c001d34 00900633 add x12, x0, x9 x12=1c002348 x9:1c002348 + 19918500 19903 1c001d36 e69ff06f jal x0, -408 + 19921500 19906 1c001b9e 00064583 lbu x11, 0(x12) x11=00000065 x12:1c002348 PA:1c002348 + 19942500 19927 1c001ba2 00160493 addi x9, x12, 1 x9=1c002349 x12:1c002348 + 19943500 19928 1c001ba6 00059e63 bne x11, x0, 28 x11:00000065 + 19946500 19931 1c001bc2 01458563 beq x11, x20, 10 x11:00000065 x20:00000025 + 19947500 19932 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19948500 19933 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19950500 19935 1c001776 00b00533 add x10, x0, x11 x10=00000065 x11:00000065 + 19951500 19936 1c001778 fddff06f jal x0, -36 + 19953500 19938 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 19954500 19939 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 19955500 19940 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 19956500 19941 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 19957500 19942 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 19958500 19943 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 19959500 19944 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 19960500 19945 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 19961500 19946 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 19962500 19947 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000065 x14:1a104000 PA:1a1041b8 + 19966500 19951 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 19967500 19952 1c001bca 16a0006f jal x0, 362 + 19969500 19954 1c001d34 00900633 add x12, x0, x9 x12=1c002349 x9:1c002349 + 19970500 19955 1c001d36 e69ff06f jal x0, -408 + 19973500 19958 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c002349 PA:1c002349 + 19988500 19973 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234a x12:1c002349 + 19989500 19974 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 19992500 19977 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 19993500 19978 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 19994500 19979 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 19996500 19981 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 19997500 19982 1c001778 fddff06f jal x0, -36 + 19999500 19984 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20000500 19985 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 20001500 19986 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20002500 19987 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 20003500 19988 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 20004500 19989 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 20005500 19990 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 20006500 19991 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 20007500 19992 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20008500 19993 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b8 + 20012500 19997 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20013500 19998 1c001bca 16a0006f jal x0, 362 + 20015500 20000 1c001d34 00900633 add x12, x0, x9 x12=1c00234a x9:1c00234a + 20016500 20001 1c001d36 e69ff06f jal x0, -408 + 20019500 20004 1c001b9e 00064583 lbu x11, 0(x12) x11=00000028 x12:1c00234a PA:1c00234a + 20033500 20018 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234b x12:1c00234a + 20034500 20019 1c001ba6 00059e63 bne x11, x0, 28 x11:00000028 + 20037500 20022 1c001bc2 01458563 beq x11, x20, 10 x11:00000028 x20:00000025 + 20038500 20023 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20039500 20024 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 20041500 20026 1c001776 00b00533 add x10, x0, x11 x10=00000028 x11:00000028 + 20042500 20027 1c001778 fddff06f jal x0, -36 + 20044500 20029 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 20045500 20030 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 20046500 20031 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 20047500 20032 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 20048500 20033 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 20049500 20034 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 20050500 20035 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 20051500 20036 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 20052500 20037 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 20053500 20038 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000028 x14:1a104000 PA:1a1041b8 + 20057500 20042 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 20058500 20043 1c001bca 16a0006f jal x0, 362 + 20060500 20045 1c001d34 00900633 add x12, x0, x9 x12=1c00234b x9:1c00234b + 20061500 20046 1c001d36 e69ff06f jal x0, -408 + 20064500 20049 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234b PA:1c00234b + 20078500 20063 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234c x12:1c00234b + 20079500 20064 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 20082500 20067 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 20085500 20070 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xx x2:10cfff60 PA:10cfff64 + 20086500 20071 1c001bd0 00012423 sw x0, 8(x2) x2:10cfff60 PA:10cfff68 + 20087500 20072 1c001bd2 00010623 sb x0, 12(x2) x2:10cfff60 PA:10cfff6c + 20088500 20073 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xx + 20089500 20074 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 20107500 20092 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 20108500 20093 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfff60 PA:10cfff64 + 20109500 20094 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 20110500 20095 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 20111500 20096 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 20112500 20097 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 20113500 20098 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 20114500 20099 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 20115500 20100 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 20116500 20101 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c00234c PA:1c00234c + 20150500 20135 1c001bfc 00148c13 addi x24, x9, 1 x24=1c00234d x9:1c00234c + 20151500 20136 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 20158500 20143 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 20159500 20144 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 20160500 20145 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 20180500 20165 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 20199500 20184 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 20202500 20187 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 20220500 20205 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 20239500 20224 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 20240500 20225 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 20241500 20226 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 20260500 20245 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 20278500 20263 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 20297500 20282 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 20298500 20283 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 20336500 20321 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 20354500 20339 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 20373500 20358 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 20374500 20359 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 20408500 20393 1c001f3e 018004b3 add x9, x0, x24 x9=1c00234d x24:1c00234d + 20427500 20412 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 20428500 20413 1c001f42 e09ff06f jal x0, -504 + 20446500 20431 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 20447500 20432 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfff60 PA:10cfff70 + 20464500 20449 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 20483500 20468 1c001e34 00440c13 addi x24, x8, 4 x24=10cfffe8 x8:10cfffe4 + 20484500 20469 1c001e38 00042503 lw x10, 0(x8) x10=00000003 x8:10cfffe4 PA:10cfffe4 + 20488500 20473 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 20519500 20504 1c001e54 00055863 bge x10, x0, 16 x10:00000003 + 20538500 20523 1c001e64 00410593 addi x11, x2, 4 x11=10cfff64 x2:10cfff60 + 20539500 20524 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 20557500 20542 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfff78 x11:10cfff64 PA:10cfff74 + 20574500 20559 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfff64 PA:10cfff70 + 20581500 20566 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 20582500 20567 1c001a04 02f55633 divu x12, x10, x15 x12=00000003 x10:00000003 x15:00000001 + 20616500 20601 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000003 x14:0000000a + 20617500 20602 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 20618500 20603 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 20619500 20604 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 20622500 20607 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfff64 PA:10cfff70 + 20634500 20619 1c001a20 02f55833 divu x16, x10, x15 x16=00000003 x10:00000003 x15:00000001 + 20668500 20653 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000003 x15:00000001 + 20702500 20687 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 20733500 20718 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 20734500 20719 1c001a2e 01004663 blt x0, x16, 12 x16:00000003 + 20737500 20722 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 20758500 20743 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000003 + 20780500 20765 1c001a56 01070733 add x14, x14, x16 x14=00000033 x14:00000030 x16:00000003 + 20781500 20766 1c001a58 00e68023 sb x14, 0(x13) x14:00000033 x13:10cfff78 PA:10cfff78 + 20788500 20773 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 20789500 20774 1c001a5e 00168693 addi x13, x13, 1 x13=10cfff79 x13:10cfff78 + 20800500 20785 1c001a60 fb1ff06f jal x0, -80 + 20802500 20787 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 20803500 20788 1c001a12 00068023 sb x0, 0(x13) x13:10cfff79 PA:10cfff79 + 20809500 20794 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 20810500 20795 1c001e68 f17ff06f jal x0, -234 + 20825500 20810 1c001d7e 00410613 addi x12, x2, 4 x12=10cfff64 x2:10cfff60 + 20842500 20827 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 20843500 20828 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 20844500 20829 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 20846500 20831 1c001a62 fe010113 addi x2, x2, -32 x2=10cfff40 x2:10cfff60 + 20847500 20832 1c001a64 00812c23 sw x8, 24(x2) x8:10cfffe4 x2:10cfff40 PA:10cfff58 + 20848500 20833 1c001a66 01062783 lw x15, 16(x12) x15=10cfff78 x12:10cfff64 PA:10cfff74 + 20849500 20834 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfff64 PA:10cfff68 + 20850500 20835 1c001a6a 00912a23 sw x9, 20(x2) x9:1c00234d x2:10cfff40 PA:10cfff54 + 20851500 20836 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfff40 PA:10cfff50 + 20852500 20837 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfff40 PA:10cfff4c + 20868500 20853 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfff40 PA:10cfff5c + 20872500 20857 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfff40 PA:10cfff48 + 20873500 20858 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 20874500 20859 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 20875500 20860 1c001a78 00c004b3 add x9, x0, x12 x9=10cfff64 x12:10cfff64 + 20876500 20861 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000033 x15=10cfff79 x15:10cfff78 PA:10cfff78 + 20878500 20863 1c001a7e 00070363 beq x14, x0, 6 x14:00000033 + 20892500 20877 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 20893500 20878 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfff64 PA:10cfff6c + 20899500 20884 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 20902500 20887 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 20915500 20900 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 20916500 20901 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 20935500 20920 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 20936500 20921 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 20937500 20922 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 20957500 20942 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 20958500 20943 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 20975500 20960 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 20976500 20961 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 20977500 20962 1c001b36 f71ff06f jal x0, -144 + 20979500 20964 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfff64 PA:10cfff6c + 20986500 20971 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 20999500 20984 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 21006500 20991 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21007500 20992 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21021500 21006 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 21038500 21023 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21039500 21024 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21040500 21025 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21041500 21026 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfff78 x9:10cfff64 PA:10cfff74 + 21048500 21033 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000033 x20=10cfff79 x20:10cfff78 PA:10cfff78 + 21062500 21047 1c001af0 06059763 bne x11, x0, 110 x11:00000033 + 21081500 21066 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21101500 21086 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21103500 21088 1c001776 00b00533 add x10, x0, x11 x10=00000033 x11:00000033 + 21104500 21089 1c001778 fddff06f jal x0, -36 + 21106500 21091 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21107500 21092 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 21108500 21093 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21109500 21094 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 21110500 21095 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 21111500 21096 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 21112500 21097 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 21113500 21098 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 21114500 21099 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21115500 21100 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000033 x14:1a104000 PA:1a1041b8 + 21119500 21104 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21120500 21105 1c001b62 f8bff06f jal x0, -118 + 21122500 21107 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfff7a x20:10cfff79 PA:10cfff79 + 21129500 21114 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21130500 21115 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 21132500 21117 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21133500 21118 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21155500 21140 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfff40 PA:10cfff5c + 21162500 21147 1c001b02 01812403 lw x8, 24(x2) x8=10cfffe4 x2:10cfff40 PA:10cfff58 + 21163500 21148 1c001b04 01412483 lw x9, 20(x2) x9=1c00234d x2:10cfff40 PA:10cfff54 + 21164500 21149 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfff40 PA:10cfff50 + 21165500 21150 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfff40 PA:10cfff4c + 21166500 21151 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfff40 PA:10cfff48 + 21167500 21152 1c001b0c 02010113 addi x2, x2, 32 x2=10cfff60 x2:10cfff40 + 21168500 21153 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21179500 21164 1c001d86 01800433 add x8, x0, x24 x8=10cfffe8 x24:10cfffe8 + 21180500 21165 1c001d88 fadff06f jal x0, -84 + 21182500 21167 1c001d34 00900633 add x12, x0, x9 x12=1c00234d x9:1c00234d + 21183500 21168 1c001d36 e69ff06f jal x0, -408 + 21186500 21171 1c001b9e 00064583 lbu x11, 0(x12) x11=0000002c x12:1c00234d PA:1c00234d + 21223500 21208 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234e x12:1c00234d + 21224500 21209 1c001ba6 00059e63 bne x11, x0, 28 x11:0000002c + 21227500 21212 1c001bc2 01458563 beq x11, x20, 10 x11:0000002c x20:00000025 + 21228500 21213 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21229500 21214 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21231500 21216 1c001776 00b00533 add x10, x0, x11 x10=0000002c x11:0000002c + 21232500 21217 1c001778 fddff06f jal x0, -36 + 21234500 21219 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21235500 21220 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 21236500 21221 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21237500 21222 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 21238500 21223 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 21239500 21224 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 21240500 21225 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 21241500 21226 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 21242500 21227 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21243500 21228 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000002c x14:1a104000 PA:1a1041b8 + 21247500 21232 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21248500 21233 1c001bca 16a0006f jal x0, 362 + 21250500 21235 1c001d34 00900633 add x12, x0, x9 x12=1c00234e x9:1c00234e + 21251500 21236 1c001d36 e69ff06f jal x0, -408 + 21254500 21239 1c001b9e 00064583 lbu x11, 0(x12) x11=00000020 x12:1c00234e PA:1c00234e + 21269500 21254 1c001ba2 00160493 addi x9, x12, 1 x9=1c00234f x12:1c00234e + 21270500 21255 1c001ba6 00059e63 bne x11, x0, 28 x11:00000020 + 21273500 21258 1c001bc2 01458563 beq x11, x20, 10 x11:00000020 x20:00000025 + 21274500 21259 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21275500 21260 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21277500 21262 1c001776 00b00533 add x10, x0, x11 x10=00000020 x11:00000020 + 21278500 21263 1c001778 fddff06f jal x0, -36 + 21280500 21265 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21281500 21266 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 21282500 21267 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21283500 21268 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 21284500 21269 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 21285500 21270 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 21286500 21271 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 21287500 21272 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 21288500 21273 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21289500 21274 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000020 x14:1a104000 PA:1a1041b8 + 21293500 21278 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21294500 21279 1c001bca 16a0006f jal x0, 362 + 21296500 21281 1c001d34 00900633 add x12, x0, x9 x12=1c00234f x9:1c00234f + 21297500 21282 1c001d36 e69ff06f jal x0, -408 + 21300500 21285 1c001b9e 00064583 lbu x11, 0(x12) x11=00000025 x12:1c00234f PA:1c00234f + 21316500 21301 1c001ba2 00160493 addi x9, x12, 1 x9=1c002350 x12:1c00234f + 21317500 21302 1c001ba6 00059e63 bne x11, x0, 28 x11:00000025 + 21320500 21305 1c001bc2 01458563 beq x11, x20, 10 x11:00000025 x20:00000025 + 21323500 21308 1c001bcc 00414783 lbu x15, 4(x2) x15=000000xX x2:10cfff60 PA:10cfff64 + 21324500 21309 1c001bd0 00012423 sw x0, 8(x2) x2:10cfff60 PA:10cfff68 + 21325500 21310 1c001bd2 00010623 sb x0, 12(x2) x2:10cfff60 PA:10cfff6c + 21326500 21311 1c001bd6 c00027b3 p.insert x15, x0, 0, 0 x15=000000xX x15:000000xX + 21327500 21312 1c001bda c01027b3 p.insert x15, x0, 0, 1 x15=000000xX x15:000000xX + 21328500 21313 1c001bde c03027b3 p.insert x15, x0, 0, 3 x15=000000xX x15:000000xX + 21329500 21314 1c001be2 00f10223 sb x15, 4(x2) x15:000000xX x2:10cfff60 PA:10cfff64 + 21330500 21315 1c001be6 00000713 addi x14, x0, 0 x14=00000000 + 21331500 21316 1c001be8 00000613 addi x12, x0, 0 x12=00000000 + 21332500 21317 1c001bea 00000693 addi x13, x0, 0 x13=00000000 + 21333500 21318 1c001bec 00000513 addi x10, x0, 0 x10=00000000 + 21334500 21319 1c001bee 00000593 addi x11, x0, 0 x11=00000000 + 21335500 21320 1c001bf0 03000813 addi x16, x0, 48 x16=00000030 + 21336500 21321 1c001bf4 02300893 addi x17, x0, 35 x17=00000023 + 21337500 21322 1c001bf8 0004c783 lbu x15, 0(x9) x15=00000069 x9:1c002350 PA:1c002350 + 21352500 21337 1c001bfc 00148c13 addi x24, x9, 1 x24=1c002351 x9:1c002350 + 21353500 21338 1c001c00 04079163 bne x15, x0, 66 x15:00000069 + 21356500 21341 1c001c42 01778c63 beq x15, x23, 24 x15:00000069 x23:0000002d + 21357500 21342 1c001c46 01078663 beq x15, x16, 12 x15:00000069 x16:00000030 + 21358500 21343 1c001c4a fb179ce3 bne x15, x17, -72 x15:00000069 x17:00000023 + 21361500 21346 1c001c02 00050763 beq x10, x0, 14 x10:00000000 + 21364500 21349 1c001c10 00060763 beq x12, x0, 14 x12:00000000 + 21367500 21352 1c001c1e 00070763 beq x14, x0, 14 x14:00000000 + 21370500 21355 1c001c2c fd078713 addi x14, x15, -48 x14=00000039 x15:00000069 + 21371500 21356 1c001c30 0ff77713 andi x14, x14, 255 x14=00000039 x14:00000039 + 21372500 21357 1c001c34 00900693 addi x13, x0, 9 x13=00000009 + 21373500 21358 1c001c36 04e6eb63 bltu x13, x14, 86 x13:00000009 x14:00000039 + 21376500 21361 1c001c8c 02e00713 addi x14, x0, 46 x14=0000002e + 21377500 21362 1c001c90 02e79163 bne x15, x14, 34 x15:00000069 x14:0000002e + 21380500 21365 1c001cb2 07a00713 addi x14, x0, 122 x14=0000007a + 21381500 21366 1c001cb6 04e79263 bne x15, x14, 68 x15:00000069 x14:0000007a + 21384500 21369 1c001cfa 06c00713 addi x14, x0, 108 x14=0000006c + 21386500 21371 1c001cfe 20e79463 bne x15, x14, 520 x15:00000069 x14:0000006c + 21389500 21374 1c001f06 06900713 addi x14, x0, 105 x14=00000069 + 21390500 21375 1c001f0a 02e78a63 beq x15, x14, 52 x15:00000069 x14:00000069 + 21393500 21378 1c001f3e 018004b3 add x9, x0, x24 x9=1c002351 x24:1c002351 + 21394500 21379 1c001f40 00000793 addi x15, x0, 0 x15=00000000 + 21395500 21380 1c001f42 e09ff06f jal x0, -504 + 21397500 21382 1c001d4a 00a00713 addi x14, x0, 10 x14=0000000a + 21398500 21383 1c001d4c 00e12823 sw x14, 16(x2) x14:0000000a x2:10cfff60 PA:10cfff70 + 21399500 21384 1c001d4e 0e27b363 p.bneimm x15, 230 x15:00000000 + 21402500 21387 1c001e34 00440c13 addi x24, x8, 4 x24=10cfffec x8:10cfffe8 + 21403500 21388 1c001e38 00042503 lw x10, 0(x8) x10=00000007 x8:10cfffe8 PA:10cfffe8 + 21404500 21389 1c001e3a 0017bd63 p.bneimm x15, 26 x15:00000000 + 21407500 21392 1c001e54 00055863 bge x10, x0, 16 x10:00000007 + 21410500 21395 1c001e64 00410593 addi x11, x2, 4 x11=10cfff64 x2:10cfff60 + 21411500 21396 1c001e66 b99ff0ef jal x1, -1128 x1=1c001e68 + 21413500 21398 1c0019fe 0105a683 lw x13, 16(x11) x13=10cfff78 x11:10cfff64 PA:10cfff74 + 21414500 21399 1c001a00 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfff64 PA:10cfff70 + 21415500 21400 1c001a02 00100793 addi x15, x0, 1 x15=00000001 + 21416500 21401 1c001a04 02f55633 divu x12, x10, x15 x12=00000007 x10:00000007 x15:00000001 + 21450500 21435 1c001a08 00e67863 bgeu x12, x14, 16 x12:00000007 x14:0000000a + 21451500 21436 1c001a0c 00000613 addi x12, x0, 0 x12=00000000 + 21452500 21437 1c001a0e 00900313 addi x6, x0, 9 x6=00000009 + 21453500 21438 1c001a10 00079763 bne x15, x0, 14 x15:00000001 + 21456500 21441 1c001a1e 00c5a703 lw x14, 12(x11) x14=0000000a x11:10cfff64 PA:10cfff70 + 21457500 21442 1c001a20 02f55833 divu x16, x10, x15 x16=00000007 x10:00000007 x15:00000001 + 21491500 21476 1c001a24 02f57533 remu x10, x10, x15 x10=00000000 x10:00000007 x15:00000001 + 21525500 21510 1c001a28 02e7d7b3 divu x15, x15, x14 x15=00000000 x15:00000001 x14:0000000a + 21556500 21541 1c001a2c 00061763 bne x12, x0, 14 x12:00000000 + 21557500 21542 1c001a2e 01004663 blt x0, x16, 12 x16:00000007 + 21560500 21545 1c001a3a 03000713 addi x14, x0, 48 x14=00000030 + 21562500 21547 1c001a3e 01035c63 bge x6, x16, 24 x6:00000009 x16:00000007 + 21565500 21550 1c001a56 01070733 add x14, x14, x16 x14=00000037 x14:00000030 x16:00000007 + 21566500 21551 1c001a58 00e68023 sb x14, 0(x13) x14:00000037 x13:10cfff78 PA:10cfff78 + 21568500 21553 1c001a5c 00160613 addi x12, x12, 1 x12=00000001 x12:00000000 + 21569500 21554 1c001a5e 00168693 addi x13, x13, 1 x13=10cfff79 x13:10cfff78 + 21570500 21555 1c001a60 fb1ff06f jal x0, -80 + 21572500 21557 1c001a10 00079763 bne x15, x0, 14 x15:00000000 + 21573500 21558 1c001a12 00068023 sb x0, 0(x13) x13:10cfff79 PA:10cfff79 + 21574500 21559 1c001a16 00008067 jalr x0, x1, 0 x1:1c001e68 + 21576500 21561 1c001e68 f17ff06f jal x0, -234 + 21578500 21563 1c001d7e 00410613 addi x12, x2, 4 x12=10cfff64 x2:10cfff60 + 21579500 21564 1c001d80 013005b3 add x11, x0, x19 x11=1c001776 x19:1c001776 + 21580500 21565 1c001d82 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21581500 21566 1c001d84 cdfff0ef jal x1, -802 x1=1c001d86 + 21583500 21568 1c001a62 fe010113 addi x2, x2, -32 x2=10cfff40 x2:10cfff60 + 21584500 21569 1c001a64 00812c23 sw x8, 24(x2) x8:10cfffe8 x2:10cfff40 PA:10cfff58 + 21586500 21571 1c001a66 01062783 lw x15, 16(x12) x15=10cfff78 x12:10cfff64 PA:10cfff74 + 21587500 21572 1c001a68 00462403 lw x8, 4(x12) x8=00000000 x12:10cfff64 PA:10cfff68 + 21588500 21573 1c001a6a 00912a23 sw x9, 20(x2) x9:1c002351 x2:10cfff40 PA:10cfff54 + 21589500 21574 1c001a6c 01212823 sw x18, 16(x2) x18:00000000 x2:10cfff40 PA:10cfff50 + 21590500 21575 1c001a6e 01312623 sw x19, 12(x2) x19:1c001776 x2:10cfff40 PA:10cfff4c + 21591500 21576 1c001a70 00112e23 sw x1, 28(x2) x1:1c001d86 x2:10cfff40 PA:10cfff5c + 21592500 21577 1c001a72 01412423 sw x20, 8(x2) x20:00000025 x2:10cfff40 PA:10cfff48 + 21593500 21578 1c001a74 00a00933 add x18, x0, x10 x18=00000000 x10:00000000 + 21594500 21579 1c001a76 00b009b3 add x19, x0, x11 x19=1c001776 x11:1c001776 + 21595500 21580 1c001a78 00c004b3 add x9, x0, x12 x9=10cfff64 x12:10cfff64 + 21596500 21581 1c001a7a 0017c70b p.lbu x14, 1(x15!) x14=00000037 x15=10cfff79 x15:10cfff78 PA:10cfff78 + 21598500 21583 1c001a7e 00070363 beq x14, x0, 6 x14:00000037 + 21599500 21584 1c001a80 08804863 blt x0, x8, 144 x8:00000000 + 21600500 21585 1c001a84 0084c783 lbu x15, 8(x9) x15=00000000 x9:10cfff64 PA:10cfff6c + 21602500 21587 1c001a88 00078263 beq x15, x0, 4 x15:00000000 + 21605500 21590 1c001a8c 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 21607500 21592 1c001a90 0027f713 andi x14, x15, 2 x14=00000000 x15:000000xX + 21608500 21593 1c001a94 00070663 beq x14, x0, 12 x14:00000000 + 21611500 21596 1c001aa0 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21612500 21597 1c001aa2 00800a33 add x20, x0, x8 x20=00000000 x8:00000000 + 21613500 21598 1c001aa4 08078163 beq x15, x0, 130 x15:00000000 + 21616500 21601 1c001b26 ff404be3 blt x0, x20, -10 x20:00000000 + 21617500 21602 1c001b2a fff40793 addi x15, x8, -1 x15=ffffffff x8:00000000 + 21618500 21603 1c001b2e 04046433 p.max x8, x8, x0 x8=00000000 x8:00000000 + 21619500 21604 1c001b32 40878433 sub x8, x15, x8 x8=ffffffff x15:ffffffff x8:00000000 + 21620500 21605 1c001b36 f71ff06f jal x0, -144 + 21622500 21607 1c001aa6 0084c583 lbu x11, 8(x9) x11=00000000 x9:10cfff64 PA:10cfff6c + 21624500 21609 1c001aaa 00058363 beq x11, x0, 6 x11:00000000 + 21627500 21612 1c001ab0 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 21629500 21614 1c001ab4 0027f793 andi x15, x15, 2 x15=00000000 x15:000000xX + 21630500 21615 1c001ab6 02078363 beq x15, x0, 38 x15:00000000 + 21633500 21618 1c001adc 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 21634500 21619 1c001ae0 00800a33 add x20, x0, x8 x20=ffffffff x8:ffffffff + 21635500 21620 1c001ae2 fc17b7b3 p.bclr x15, x15, 30, 1 x15=00000000 x15:000000xX + 21636500 21621 1c001ae6 06079363 bne x15, x0, 102 x15:00000000 + 21637500 21622 1c001ae8 0104aa03 lw x20, 16(x9) x20=10cfff78 x9:10cfff64 PA:10cfff74 + 21639500 21624 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000037 x20=10cfff79 x20:10cfff78 PA:10cfff78 + 21641500 21626 1c001af0 06059763 bne x11, x0, 110 x11:00000037 + 21644500 21629 1c001b5e 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21645500 21630 1c001b60 000980e7 jalr x1, x19, 0 x1=1c001b62 x19:1c001776 + 21647500 21632 1c001776 00b00533 add x10, x0, x11 x10=00000037 x11:00000037 + 21648500 21633 1c001778 fddff06f jal x0, -36 + 21650500 21635 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21651500 21636 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 21652500 21637 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21653500 21638 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 21654500 21639 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 21655500 21640 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 21656500 21641 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 21657500 21642 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 21658500 21643 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21659500 21644 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000037 x14:1a104000 PA:1a1041b8 + 21663500 21648 1c001774 00008067 jalr x0, x1, 0 x1:1c001b62 + 21664500 21649 1c001b62 f8bff06f jal x0, -118 + 21666500 21651 1c001aec 001a458b p.lbu x11, 1(x20!) x11=00000000 x20=10cfff7a x20:10cfff79 PA:10cfff79 + 21668500 21653 1c001af0 06059763 bne x11, x0, 110 x11:00000000 + 21669500 21654 1c001af2 0004c783 lbu x15, 0(x9) x15=000000xX x9:10cfff64 PA:10cfff64 + 21671500 21656 1c001af6 0097f793 andi x15, x15, 9 x15=00000000 x15:000000xX + 21672500 21657 1c001af8 0087b463 p.bneimm x15, 8 x15:00000000 + 21675500 21660 1c001b00 01c12083 lw x1, 28(x2) x1=1c001d86 x2:10cfff40 PA:10cfff5c + 21676500 21661 1c001b02 01812403 lw x8, 24(x2) x8=10cfffe8 x2:10cfff40 PA:10cfff58 + 21677500 21662 1c001b04 01412483 lw x9, 20(x2) x9=1c002351 x2:10cfff40 PA:10cfff54 + 21678500 21663 1c001b06 01012903 lw x18, 16(x2) x18=00000000 x2:10cfff40 PA:10cfff50 + 21679500 21664 1c001b08 00c12983 lw x19, 12(x2) x19=1c001776 x2:10cfff40 PA:10cfff4c + 21680500 21665 1c001b0a 00812a03 lw x20, 8(x2) x20=00000025 x2:10cfff40 PA:10cfff48 + 21681500 21666 1c001b0c 02010113 addi x2, x2, 32 x2=10cfff60 x2:10cfff40 + 21682500 21667 1c001b0e 00008067 jalr x0, x1, 0 x1:1c001d86 + 21684500 21669 1c001d86 01800433 add x8, x0, x24 x8=10cfffec x24:10cfffec + 21685500 21670 1c001d88 fadff06f jal x0, -84 + 21687500 21672 1c001d34 00900633 add x12, x0, x9 x12=1c002351 x9:1c002351 + 21688500 21673 1c001d36 e69ff06f jal x0, -408 + 21691500 21676 1c001b9e 00064583 lbu x11, 0(x12) x11=00000029 x12:1c002351 PA:1c002351 + 21705500 21690 1c001ba2 00160493 addi x9, x12, 1 x9=1c002352 x12:1c002351 + 21706500 21691 1c001ba6 00059e63 bne x11, x0, 28 x11:00000029 + 21709500 21694 1c001bc2 01458563 beq x11, x20, 10 x11:00000029 x20:00000025 + 21710500 21695 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21711500 21696 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21713500 21698 1c001776 00b00533 add x10, x0, x11 x10=00000029 x11:00000029 + 21714500 21699 1c001778 fddff06f jal x0, -36 + 21716500 21701 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21717500 21702 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 21718500 21703 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21719500 21704 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 21720500 21705 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 21721500 21706 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 21722500 21707 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 21723500 21708 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 21724500 21709 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21725500 21710 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000029 x14:1a104000 PA:1a1041b8 + 21729500 21714 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21730500 21715 1c001bca 16a0006f jal x0, 362 + 21732500 21717 1c001d34 00900633 add x12, x0, x9 x12=1c002352 x9:1c002352 + 21733500 21718 1c001d36 e69ff06f jal x0, -408 + 21736500 21721 1c001b9e 00064583 lbu x11, 0(x12) x11=00000021 x12:1c002352 PA:1c002352 + 21750500 21735 1c001ba2 00160493 addi x9, x12, 1 x9=1c002353 x12:1c002352 + 21751500 21736 1c001ba6 00059e63 bne x11, x0, 28 x11:00000021 + 21754500 21739 1c001bc2 01458563 beq x11, x20, 10 x11:00000021 x20:00000025 + 21755500 21740 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21756500 21741 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21758500 21743 1c001776 00b00533 add x10, x0, x11 x10=00000021 x11:00000021 + 21759500 21744 1c001778 fddff06f jal x0, -36 + 21761500 21746 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21762500 21747 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 21763500 21748 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21764500 21749 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 21765500 21750 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 21766500 21751 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 21767500 21752 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 21768500 21753 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 21769500 21754 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21770500 21755 1c001770 00a767a3 p.sw x10, x0(x14) x10:00000021 x14:1a104000 PA:1a1041b8 + 21774500 21759 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21775500 21760 1c001bca 16a0006f jal x0, 362 + 21777500 21762 1c001d34 00900633 add x12, x0, x9 x12=1c002353 x9:1c002353 + 21778500 21763 1c001d36 e69ff06f jal x0, -408 + 21781500 21766 1c001b9e 00064583 lbu x11, 0(x12) x11=0000000a x12:1c002353 PA:1c002353 + 21796500 21781 1c001ba2 00160493 addi x9, x12, 1 x9=1c002354 x12:1c002353 + 21797500 21782 1c001ba6 00059e63 bne x11, x0, 28 x11:0000000a + 21800500 21785 1c001bc2 01458563 beq x11, x20, 10 x11:0000000a x20:00000025 + 21801500 21786 1c001bc6 01200533 add x10, x0, x18 x10=00000000 x18:00000000 + 21802500 21787 1c001bc8 000980e7 jalr x1, x19, 0 x1=1c001bca x19:1c001776 + 21804500 21789 1c001776 00b00533 add x10, x0, x11 x10=0000000a x11:0000000a + 21805500 21790 1c001778 fddff06f jal x0, -36 + 21807500 21792 1c001754 000026b7 lui x13, 0x2000 x13=00002000 + 21808500 21793 1c001756 f14027f3 csrrs x15, x0, 0xf14 x15=00000067 + 21809500 21794 1c00175a f8068693 addi x13, x13, -128 x13=00001f80 x13:00002000 + 21810500 21795 1c00175e 00379713 slli x14, x15, 0x3 x14=00000338 x15:00000067 + 21811500 21796 1c001762 00279793 slli x15, x15, 0x2 x15=0000019c x15:00000067 + 21812500 21797 1c001764 ee873733 p.bclr x14, x14, 23, 8 x14=00000038 x14:00000338 + 21813500 21798 1c001768 00d7f7b3 and x15, x15, x13 x15=00000180 x15:0000019c x13:00001f80 + 21814500 21799 1c00176a 00e787b3 add x15, x15, x14 x15=000001b8 x15:00000180 x14:00000038 + 21815500 21800 1c00176c 1a104737 lui x14, 0x1a104000 x14=1a104000 + 21816500 21801 1c001770 00a767a3 p.sw x10, x0(x14) x10:0000000a x14:1a104000 PA:1a1041b8 + 21820500 21805 1c001774 00008067 jalr x0, x1, 0 x1:1c001bca + 21821500 21806 1c001bca 16a0006f jal x0, 362 + 21823500 21808 1c001d34 00900633 add x12, x0, x9 x12=1c002354 x9:1c002354 + 21824500 21809 1c001d36 e69ff06f jal x0, -408 + 21827500 21812 1c001b9e 00064583 lbu x11, 0(x12) x11=00000000 x12:1c002354 PA:1c002354 + 21843500 21828 1c001ba2 00160493 addi x9, x12, 1 x9=1c002355 x12:1c002354 + 21844500 21829 1c001ba6 00059e63 bne x11, x0, 28 x11:00000000 + 21845500 21830 1c001ba8 05c12083 lw x1, 92(x2) x1=1c001834 x2:10cfff60 PA:10cfffbc + 21846500 21831 1c001baa 05812403 lw x8, 88(x2) x8=00000000 x2:10cfff60 PA:10cfffb8 + 21847500 21832 1c001bac 05412483 lw x9, 84(x2) x9=00000000 x2:10cfff60 PA:10cfffb4 + 21848500 21833 1c001bae 05012903 lw x18, 80(x2) x18=1b204000 x2:10cfff60 PA:10cfffb0 + 21849500 21834 1c001bb0 04c12983 lw x19, 76(x2) x19=00000007 x2:10cfff60 PA:10cfffac + 21850500 21835 1c001bb2 04812a03 lw x20, 72(x2) x20=1c00220c x2:10cfff60 PA:10cfffa8 + 21851500 21836 1c001bb4 04412a83 lw x21, 68(x2) x21=1c002210 x2:10cfff60 PA:10cfffa4 + 21852500 21837 1c001bb6 04012b03 lw x22, 64(x2) x22=00000000 x2:10cfff60 PA:10cfffa0 + 21853500 21838 1c001bb8 03c12b83 lw x23, 60(x2) x23=00000000 x2:10cfff60 PA:10cfff9c + 21858500 21843 1c001bba 03812c03 lw x24, 56(x2) x24=00000000 x2:10cfff60 PA:10cfff98 + 21859500 21844 1c001bbc 03412c83 lw x25, 52(x2) x25=00000000 x2:10cfff60 PA:10cfff94 + 21860500 21845 1c001bbe 06010113 addi x2, x2, 96 x2=10cfffc0 x2:10cfff60 + 21861500 21846 1c001bc0 00008067 jalr x0, x1, 0 x1:1c001834 + 21863500 21848 1c001834 01c12083 lw x1, 28(x2) x1=1c00220c x2:10cfffc0 PA:10cfffdc + 21864500 21849 1c001836 00000513 addi x10, x0, 0 x10=00000000 + 21865500 21850 1c001838 04010113 addi x2, x2, 64 x2=10d00000 x2:10cfffc0 + 21866500 21851 1c00183a 00008067 jalr x0, x1, 0 x1:1c00220c + 21868500 21853 1c00220c 21c96283 p.elw x5, 540(x18) x5=00000000 x18:1b204000 PA:1b20421c diff --git a/sw/scripts/tracevis/parse.pl b/sw/scripts/tracevis/parse.pl new file mode 100644 index 0000000..1bf47c2 --- /dev/null +++ b/sw/scripts/tracevis/parse.pl @@ -0,0 +1,204 @@ +sub flush_buffer { + my $key = $_[0]; + my $buffer = $_[1]; + my $pcs = $_[2]; + my $binfile = $_[3]; + my $last_time = $_[4]; + my $inline = $_[5]; + my $use_pc_as_label = $_[6]; + my $format = $_[7]; + my $gvsoc = $_[8]; + + my $linenum = $buffer =~ tr/\n//; + + if ($linenum < 2) { return; } + + #print $buffer; + my $funcnames = `addr2line -e $binfile -f -a -i $pcs`; + + $funcnames = "$funcnames\n0x0"; # to let it process the last address in the below loop + + #print "$funcnames"; + + #remove first line + $funcnames =~ s/^[^\n]*\n//s; + + my @a2l_first_last_lines = {}; + $a2l_first_last_lines[0] = ""; + $a2l_first_last_lines[1] = ""; + + my @a2i_first_last_lines = {}; + $a2i_first_last_lines[0] = ""; + $a2i_first_last_lines[1] = ""; + + + my $a2l_line_index = 1; + if (!$inline) { $a2l_line_index = 0;} + + for (split /\n/, $funcnames) { + my $a2l_line = $_; + #print "$_\n"; + if ($a2l_line =~ /^(0x[0-9a-f]+)(.*)/ and $buffer =~ /.*\n.*\n.*/) { + #print "ADDR: $1 $2\n"; + + my $regex= qr/^\s+([0-9]+)\s+([0-9]+)\s+([0-9a-f]+)\s+[0-9a-f]+\s+([^ ]+)(.*)?\n/; + if($gvsoc == 1) { + #salvo: I might have broke it. I removed the "rest" group and merged it with "args", but I don't have a gvsoc trace to try out. :( + $regex = qr/^\s*([0-9]+):\s+([0-9]+):\s+\[\e\[[0-9;]*m[^ ]*\s*\e\[[0-9;]*m\]\s+[^ ]+\s+M\s+([0-9a-f]+)\s+([^ ]+)(.*)?\n/; + } + + my ($time, $cycles, $pc, $instr, $args) = $buffer =~ $regex; + + #remove current line from the buffer + $buffer =~ s/^[^\n]*\n//s; + + my ($next_time, $next_cycles) = $buffer =~ /^\s+([0-9]+)\s+([0-9]+).*/; + + #print "$time - $cycles - $pc - $instr - $args\n"; + my $funcname = $a2l_first_last_lines[$a2l_line_index]; + my $coords = $a2i_first_last_lines[$a2l_line_index]; + my $duration_cycles = ($next_cycles - $cycles); + my $duration_time = ($next_time - $time); + + my $duration = $duration_time; + my $start_time = $time; + + #my $start_time = $cycles; + #my $duration = $duration_cycles; + + my $label = $instr; + if ($use_pc_as_label) { $label = "$pc - $instr"; } + + + if ($format eq "json") { + print "{\"name\": \"$label\", \"cat\": \"$instr\", \"ph\": \"X\", \"ts\": $start_time, \"dur\": $duration, \"pid\": \"$key\", \"tid\": \"$funcname\", \"args\":{\"pc\": \"$pc\", \"instr\": \"$instr $args\", \"time\": \"$cycles\", \"Origin\": \"$coords\"}},\n"; + } else { + $coords =~ s/^(.*\/)+([^ ]*).*/$2/s; + $instr =~ s/ +/ /; + $args =~ s/ +/ /; + $key =~ s/.*core_([0-9]+)_([0-9]+).*/$1 $2/s; + print "$start_time $cycles $duration $key $funcname $pc $coords $instr \"$instr $args\"\n" + } + + $a2l_first_last_lines[0] = ""; + $a2l_first_last_lines[1] = ""; + $a2i_first_last_lines[0] = ""; + $a2i_first_last_lines[1] = ""; + $last_time = $start_time; + + } elsif ($a2l_line =~ /^[^\/].*/) { + if ($a2l_first_last_lines[0] eq "") { $a2l_first_last_lines[0] = $a2l_line; } + $a2l_first_last_lines[1] = $a2l_line; + } else { + if ($a2i_first_last_lines[0] eq "") { $a2i_first_last_lines[0] = $a2l_line; } + $a2i_first_last_lines[1] = $a2l_line; + } + + } + #print "\n\nend flush\n\n"; + return $last_time; +} + +sub convert_file { + my $file = $_[0]; + my $binfile = $_[1]; + my $inline = $_[2]; + my $use_pc_as_label = $_[3]; + my $format = $_[4]; + my $gvsoc = $_[5]; + + open my $info, $file or die "Could not open $file: $!"; + my $last_time = 0; + my $buffer = ""; + my $pcs=""; + my $count = 0; + + while(my $line = <$info>) { + + my $regex = qr/^\s+([0-9]+)\s+([0-9]+)\s+([0-9a-f]+)\s+[0-9a-f]+\s+([^ ]+)\s+(.+?(?= )).*/; + if($gvsoc == 1) { + $regex = qr/^\s*([0-9]+):\s+([0-9]+):\s+\[\e\[[0-9;]*m[^ ]*\s*\e\[[0-9;]*m\]\s+[^ ]+\s+M\s+([0-9a-f]+)\s+([^ ]+)\s+(.+?(?= ))(.*)/; + } + if ($line =~ $regex) { + $buffer = "$buffer$line"; + $pcs = "$pcs $3"; + $count++; + + if ($count==1000){ + #print "flushing buffer\n"; + #print "$buffer"; + $last_time = flush_buffer($file, $buffer, $pcs, $binfile, $last_time, $inline, $use_pc_as_label, $format, $gvsoc); +# print $last_time; + #print "completed\n"; + $buffer="$line"; + $pcs="$3"; + $count=0; + } + } + } + + #in case we didn't reach the flushing threshold + #print "flushing buffer (last) Buffer:\n$buffer\n"; + $last_time = flush_buffer($file, $buffer, $pcs, $binfile, $last_time, $inline, $use_pc_as_label, $format, $gvsoc); + #print "completed\n"; + close $info; + return $last_time; +} + +if ($#ARGV < 1) { + print "Usage: $0 [-i] [-t] .. \n"; + exit; +} + +my $arg_index = 0; + +my $inline = 0; +my $format = "json"; +my $use_pc_as_label = 0; +my $gvsoc = 0; + +if ($ARGV[$arg_index] eq "-i") { + $inline = 1; + #$arg_index++; + shift; +} + +if ($ARGV[$arg_index] eq "-p") { + $use_pc_as_label=1; + #$arg_index++; + shift; +} + +if ($ARGV[$arg_index] eq "-t") { + $format="txt"; + #$arg_index++; + shift; +} + +if ($ARGV[$arg_index] eq "-g") { + $gvsoc=1; + #$arg_index++; + shift; +} + +my $binfile=shift; #$ARGV[$arg_index++]; + +#print "$arg_index $inline $binfile\n"; + + +if ($format eq "json") { + print "{\"traceEvents\": [\n"; +} + +my $last_time=0; +foreach my $file (@ARGV) { + $last_time = convert_file($file, $binfile, $inline, $use_pc_as_label, $format, $gvsoc); +} + + +#print "{\"name\": \"end\", \"cat\": \"end\", \"ph\": \"X\", \"ts\": $last_time, \"dur\": 0, \"pid\": \"$file\", \"tid\": \"end\", \"args\":{}}\n"; + +if ($format eq "json") { + print "{}]}\n"; +} +