I am one of the lead developers of Project Unnamed, an FPGA synthesis and P&R toolchain in early stages of development. I am also working on Project Combine, which aims to reverse engineer and document a wide range of FPGAs (and be a backend of sorts for Project Unnamed).

My current areas of focus are:

• getting Project Unnamed synthesis capabilities up to par
  • memory inference code
  • improving optimization passes
  • adding more targets
• bootstrapping Project Unnamed place & route
  • packer implementation for supported targets
  • hooking into Project Combine database
  • timing engine
  • initial placer and router implementation
  • bitstream generation using Project Combine
• Project Combine work
  • development of new bitstream correlation algorithm for reverse engineering
    • add SiliconBlue iCE65 and iCE40 targets as a test run
    • use the new algorithm to reverse UltraScale and UltraScale+ bitstreams
  • timing database extraction for current ISE-based Xilinx targets
  • writing documentation for and in-hardware testing of current Xilinx targets

The funds will be used to keep the catgirl fed, housed, and supplied with devboards. I also accept in-kind donations in the form of FPGA devboards.