can iverilog simulate designs with PLLs

[pm100]

I have an ice40 project. I recently added a PLL primitive. I cannot make it sim (no clock out from the pll). The icecube IP generator added a comment

input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */

I did that (1 to 0 , hold for a few clock cycles, then 1). Doesnt seem to make any difference

[caryr]

Are you sure the comment is correct? You could try it with the polarity flipped or dig into the PLL code and make sure it is correct. There is no reason Icarus cannot model a PLL

[pm100]

I have no idea if the comment is correct. I am just reporting what the IP generator tools generated. I flipped it every which way I could think of

here what it generated

module Shell_pll (
    REFERENCECLK,
    PLLOUTCORE,
    PLLOUTGLOBAL,
    RESET
);

  input REFERENCECLK;
  input RESET;    /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
  output PLLOUTCORE;
  output PLLOUTGLOBAL;

  SB_PLL40_CORE Shell_pll_inst (
      .REFERENCECLK(REFERENCECLK),
      .PLLOUTCORE(PLLOUTCORE),
      .PLLOUTGLOBAL(PLLOUTGLOBAL),
      .EXTFEEDBACK(),
      .DYNAMICDELAY(),
      .RESETB(RESET),
      .BYPASS(1'b0),
      .LATCHINPUTVALUE(),
      .LOCK(),
      .SDI(),
      .SDO(),
      .SCLK()
  );

  //\\ Fin=100, Fout=25;
  defparam Shell_pll_inst.DIVR = 4'b0000;
defparam Shell_pll_inst.DIVF = 7'b0000111;
defparam Shell_pll_inst.DIVQ = 3'b101;
defparam Shell_pll_inst.FILTER_RANGE = 3'b101;
defparam Shell_pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam Shell_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam Shell_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam Shell_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam Shell_pll_inst.FDA_RELATIVE = 4'b0000;
defparam Shell_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam Shell_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam Shell_pll_inst.ENABLE_ICEGATE = 1'b0;

what I ended up doing was ifdefing the pll code on ICARUS, and just using the simulated clock directly