Problems with missing custom files used for CFS in Vivado IP block

[Sam-Vervaeck]

I have taken an accelerator design and hooked it up into the CFS module. Since it is a (system)verilog design I did a component-style instantiation of the top module ComputeCoreWrapper.v. I have added all the files in the Aloha-HE_Common folder to the neorv32 library in Vivado as well.

When running the simple TB file and running the Vivado simulator, this ComputeCoreWrapper instance shows up perfectly in the Vivado Scope window under neorv32_cfs_inst_true > neorv32_cfs_inst > ComputeCoreWrapper_inst.
However, when creating a block design with the Vivado NEORV32 IP, I get this warning:

WARNING: 'computecorewrapper' remains a black box since it has no binding entity

And when looking through the Scope window under neorv32_cfs_inst_true > neorv32_cfs_inst > there is a "missing IP" icon for the ComputeCoreWrapper.

I wonder if this has to do something with the file_list_soc.f used by the packaging tcl script? Do I have to change those files for it to include the Aloha-HE_Common folder during packaging?
Another thing I noticed when googling this warning online is that a lot of people were mentioning correct capitalisation of names. In my VHDL file I have the exact same module names (double checked and copy+pasted) but in the warning it does say 'computecorewrapper' with lower case letters. I don't know where I can find the internal naming list of Vivado though.

[stnolting]

I have taken an accelerator design and hooked it up into the CFS module. Since it is a (system)verilog design I did a component-style instantiation of the top module ComputeCoreWrapper.v.

👍

Did you add those files via the GUI?

I have added all the files in the Aloha-HE_Common folder to the neorv32 library in Vivado as well.

This is not necessary and not even possible, as Verilog does not have the concept of "libraries". Just make sure that your customized neorv32_cpu_cp_cfu.vhd is still part of the neorv32 library.

I wonder if this has to do something with the file_list_soc.f used by the packaging tcl script? Do I have to change those files for it to include the Aloha-HE_Common folder during packaging?

Right, you need to add your additional files to the IP packager as well:

# additional user sources (VHDL, Verilog, System-Verilog)
set SRC_USER {
 ./path/to/some/file.v
 ./path/to/another/file.v
}
add_files $SRC_USER

Another thing I noticed when googling this warning online is that a lot of people were mentioning correct capitalisation of names. In my VHDL file I have the exact same module names (double checked and copy+pasted) but in the warning it does say 'computecorewrapper' with lower case letters.

Verilog is case sensitive, but VHDL is not. As you are instantiating Verilog inside VHDL, capitalization should be irrelevant at that point I think. 🤔

[Sam-Vervaeck]

@stnolting I think I got it working, my ComputeCoreWrapper now shows up in my Vivado IP block:

However, I don't think I have fixed it in the correct fashion, I had to edit the neorv32_vivado_ip.vhd file on top of changing the neorv_vivado_ip.tcl script. I set this to true in the vhd file:

IO_CFS_EN : boolean := true;

This made it that my Aloha-HE files were packaged within the IP block finally. This is not the correct way to fix it though right?

This is how my tcl script ended up looking like:

# -- ================================================================================ --
# -- NEORV32 - Vivado IP Packaging + Customization GUI Setup                          --
# -- -------------------------------------------------------------------------------- --
# -- This scripts packages the entire processor as Vivado IP module including a fancy --
# -- customization GUI. See the NEORV32 Datasheet & User Guide for more information.  --
# -- -------------------------------------------------------------------------------- --
# -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
# -- Copyright (c) NEORV32 contributors.                                              --
# -- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  --
# -- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
# -- SPDX-License-Identifier: BSD-3-Clause                                            --
# -- ================================================================================ --


# **************************************************************
# Global configuration
# **************************************************************
set neorv32_home ../..
set AlohaHE_Common_home ../../../thesis_Aloha-HE/Aloha-HE_Common
set AlohaHE_IP_home ../../../thesis_Aloha-HE/Aloha-HE_Kintex/Aloha-HE_Kintex.srcs/sources_1/ip
set rtl_top neorv32_vivado_ip.vhd
set logo docs/figures/neorv32_logo_riscv_small.png
set outputdir neorv32_vivado_ip_work
set cur_dir [file normalize .]


# **************************************************************
# Create empty (!) output/working directory
# **************************************************************
file mkdir $outputdir
set files [glob -nocomplain "$outputdir/*"]
if {[llength $files] != 0} {
    puts "DELETING ALL FILES in $outputdir"
    file delete -force {*}[glob -directory $outputdir *];
}


# **************************************************************
# Create Vivado project
# **************************************************************
create_project "neorv32-ip" $outputdir
set_property target_language VHDL [current_project]
set_property board_part digilentinc.com:genesys2:part0:1.1 [current_project]


# **************************************************************
# Import HDL source files
# **************************************************************

# read and process NEORV32 file list
set file_list_file [read [open "$neorv32_home/rtl/file_list_soc.f" r]]
set file_list [string map [list "NEORV32_RTL_PATH_PLACEHOLDER" "$neorv32_home/rtl"] $file_list_file]
puts "NEORV32 source files:"
puts $file_list

# additional user sources (VHDL, Verilog, System-Verilog)
set SRC_USER {}
proc get_files_recursive {dir pattern} {
    global SRC_USER

    # Get a list of all files and directories in the current directory
    foreach file_or_dir [glob -nocomplain -directory $dir *] {
        set full_path "$file_or_dir"
        # puts "Searching current path:"
        # puts $full_path

        # If it's a directory, recursively search it
        if {[file isdirectory $full_path]} {
            get_files_recursive $full_path $pattern
        } elseif {[file isfile $full_path] && [string match $pattern $full_path]} {
            # If it's a file and matches the pattern, add it to the list
            lappend SRC_USER $full_path
        }
    }
}
get_files_recursive $AlohaHE_Common_home *.v
get_files_recursive $AlohaHE_Common_home *.sv
get_files_recursive $AlohaHE_Common_home *.vh
get_files_recursive $AlohaHE_Common_home *.coe
get_files_recursive $AlohaHE_IP_home *.xci
# Print the new files for verification, one per line
puts "Aloha-HE source files:"
foreach file $SRC_USER {
    puts $file
}

add_files $SRC_USER
add_files $file_list
set_property library neorv32 [get_files $SRC_USER]
set_property library neorv32 [get_files $file_list]

# IP top module
add_file $neorv32_home/rtl/system_integration/$rtl_top
set_property library neorv32 [get_files [glob $neorv32_home/rtl/system_integration/$rtl_top]]

set_property top neorv32_vivado_ip [current_fileset]

update_compile_order -fileset sources_1
[...]

[stnolting]

First of all, how the hell did you figure out all this tcl packaging stuff, it is very impressive! There does not seem to be a lot of clear guides online. Did you do it once by hand and then copy the tcl console commands Vivado printed?

Copy&paste from Vivado's journal file plus a lot of stuff I found in some threads on Reddit... 😅

And it automatically sets the ComputeCoreWrapper as top.
I have tried overwriting it by turning these on: [...]

Right, the definition of the IP's top is still missing in the TCL file. I'll add that ASAP.

The CFS file is also greyed out and still mentions a missing ComputeCoreWrapper file:

Did your enable that in the customization GUI?

the current project setup seems to not specify anything and a random project part is selected?

I think it is impossible to create a new project without specifying a specific part. However, individual IP modules do not have this restriction.

Seems like I can fix this by setting only

👍

So $rtl_top must be changed to neorv32_vivado_ip (! without the .vhd).

Right. I'll fix that.

I think I got it working, my ComputeCoreWrapper now shows up in my Vivado IP block:

Great!! 🎉

This made it that my Aloha-HE files were packaged within the IP block finally. This is not the correct way to fix it though right?

Hmm, no... Vivado should be able to identify the hierarchy and file dependencies even if the according module is not enabled (I mean, it works for all the remaining NEORV32 components, right?!). 🤔

[Sam-Vervaeck]

Did your enable that in the customization GUI?

Yeah I did, my NEO IP block has had the CFS enabled all this time.

Hmm, no... Vivado should be able to identify the hierarchy and file dependencies even if the according module is not enabled (I mean, it works for all the remaining NEORV32 components, right?!). 🤔

Yeah I would also expect that to be the case but maybe it has something to do with it being a Verilog instantiation inside VHDL files? All the other NEO components are VHDL.

[stnolting]

Yeah I would also expect that to be the case but maybe it has something to do with it being a Verilog instantiation inside VHDL files? All the other NEO components are VHDL.

I am using a similar setup but for the CFU: instantiate a rather complex design (Verilog!) as custom instructions. But I do not have any such issues (yet). Which version Vivado are you using?

[Sam-Vervaeck]

Same as yours I thought: 2019.1