004-clarifications-mem.txt

Part 4: Clarifications for Memory Location Descriptions

This is part 4 in a series of proposals related to support for debugging on
heterogeneous architectures. This proposal lays more groundwork for subsequent
proposals by introducing the concept of addressable memory storage that is
associated with each address space supported by a target architecture, which
heretofore had only been alluded to in the spec (See Section 1.3.2).


BACKGROUND
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The changes proposed below introduce the concept of distinct memory storage for
each address space supported by a target architecture, and a default address
space for the target architecture. Subsequent proposals will make use of this,
allowing memory location descriptions to specify address spaces other than the
default one.


PROPOSED CHANGES
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In Section 2.6.1.1.2 (now 2.6.2), add the following after the first
paragraph:

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    Each of the target architecture specific address spaces has a
    corresponding memory location storage that denotes the linear
    addressable memory of that address space. The size of each memory
    location storage corresponds to the range of the addresses in the
    corresponding address space.

    [non-normative] It is target architecture defined how address space
    location storage maps to target architecture physical memory. For
    example, they may be independent memory, or more than one location
    storage may alias the same physical memory possibly at different
    offsets and with different interleaving. The mapping may also be
    dictated by the source language address classes.

    A memory location description specifies a memory location storage.
    The bit offset corresponds to a bit position within a byte of the
    memory. Bits accessed using a memory location description, access
    the corresponding target architecture memory starting at the bit
    position within the byte specified by the bit offset.

    A memory location description that has a bit offset that is a
    multiple of 8 (the byte size) is defined to be a byte address memory
    location description. It has a memory byte address A that is equal
    to the bit offset divided by 8.

    A memory location description that does not have a bit offset that
    is a multiple of 8 (the byte size) is defined to be a bit field
    memory location description. It has a bit position B equal to the
    bit offset modulo 8, and a memory byte address A equal to the bit
    offset minus B that is then divided by 8.

    The address space AS of a memory location description is defined to
    be the address space that corresponds to the memory location storage
    associated with the memory location description.

    A location description that is comprised of one byte address memory
    location description SL is defined to be a memory byte address
    location description. It has a byte address equal to A and an
    address space equal to AS of the corresponding SL.
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