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clktree_ccopt.rpt
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###############################################################
# Generated by: Cadence Innovus 16.13-s045_1
# OS: Linux x86_64(Host ID toke.fransg.eit.lth.se)
# Generated on: Wed Feb 21 14:36:31 2024
# Design: jollof_top
# Command: report_ccopt_clock_trees -filename ./clktree_ccopt.rpt
###############################################################
Clock DAG stats:
================
--------------------------------------------------------------
Cell type Count Area Capacitance
--------------------------------------------------------------
Buffers 8 71.240 0.043
Inverters 0 0.000 0.000
Integrated Clock Gates 0 0.000 0.000
Non-Integrated Clock Gates 0 0.000 0.000
Clock Logic 1 3775.000 0.000
All 9 3846.240 0.043
--------------------------------------------------------------
Clock DAG wire lengths:
=======================
--------------------
Type Wire Length
--------------------
Top 0.000
Trunk 420.636
Leaf 2490.545
Total 2911.181
--------------------
Clock DAG capacitances:
=======================
--------------------------------
Type Gate Wire Total
--------------------------------
Top 0.000 0.000 0.000
Trunk 1.395 0.056 1.451
Leaf 0.498 0.426 0.925
Total 1.894 0.482 2.376
--------------------------------
Clock DAG sink capacitances:
============================
--------------------------------------------------------
Count Total Average Std. Dev. Min Max
--------------------------------------------------------
464 0.498 0.001 0.001 0.001 0.025
--------------------------------------------------------
Clock DAG net violations:
=========================
None
Clock DAG primary half-corner transition distribution:
======================================================
-----------------------------------------------------------------------------------------------------
Net Type Target Count Average Std. Dev. Min Max Distribution
-----------------------------------------------------------------------------------------------------
Trunk 0.200 5 0.027 0.034 0.000 0.085 {4 <= 0.040ns, 1 <= 0.120ns}
Leaf 0.200 5 0.104 0.012 0.091 0.122 {4 <= 0.120ns, 1 <= 0.160ns}
-----------------------------------------------------------------------------------------------------
Clock DAG library cell distribution:
====================================
-------------------------------------------------
Name Type Inst Inst Area
Count (um^2)
-------------------------------------------------
HS65_LL_CNBFX82 buffer 4 47.840
HS65_LL_CNBFX62 buffer 1 9.360
HS65_LL_CNBFX45 buffer 1 7.800
HS65_LL_CNBFX14 buffer 2 6.240
CPAD_S_74x50u_IN logic 1 3775.000
-------------------------------------------------
Please note that the following tables reflect only the defined clock trees, so the flop counts might not include all flops in your design.
Clock Tree Summary:
===================
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Clock Tree # Posedge # Negedge # RAM # Enable # Non enable # Other # Clock # Bufs # Invs # Other # Implicit Max Max Max Max Standard Wire Gate Clock Tree Root
Name Flops Flops Clock Latch Latch Sinks Gates Clock ignore/ Non-leaf Leaf Length Source-sink cell area cap cap
Pins Sinks Sinks Cells stop pins Fanout Fanout (um) Resistance (um^2) (pF) (pF)
(Ohms)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
clk 463 0 0 0 1 0 0 8 0 1 0 5 100 263.08 3809.52 3846.240 0.482 1.894 clk
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1 clock trees contain a total of 1 nets marked dont_touch, which will not have been buffered, and may have Design Rule Violations as a consequence.
1 clock trees contain a total of 1 nets marked ideal_network, which will not have been buffered, and may have Design Rule Violations as a consequence.
Summary across all clock trees :
================================
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# Posedge # Negedge # RAM # Enable # Non enable # Other # Clock # Bufs # Invs # Other # Implicit Max Average Max Average Max Max Standard Wire Gate
Flops Flops Clock Latch Latch Sinks Gates Clock ignore/ Non-leaf Non-leaf Leaf Leaf Length Source-sink cell area cap cap
Pins Sinks Sinks Cells stop pins Fanout Fanout Fanout Fanout (um) Resistance (um^2) (pF) (pF)
(Ohms)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
463 0 0 0 1 0 0 8 0 1 0 5 1.8 100 92.8 263.080 380.952 3846.240 0.482 1.894
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Physical metrics across all clock trees
=======================================
-----------------------------------------------------------------------
Metric Minimum Average Maximum Std.dev
-----------------------------------------------------------------------
Source-sink routed net length (um) 0.001 89.334 263.080 75.505
Source-sink manhattan distance (um) 0.000 80.026 264.940 74.739
Source-sink resistance (Ohm) 0.001 139.438 380.952 109.360
-----------------------------------------------------------------------
Count of violations across all clock trees:
===========================================
---------------------------------------------------------------------------------------
Clock Tree # Max capacitance # Max resistance # Max length # Max fanout # Slew
Name violations violations violations violations violations
---------------------------------------------------------------------------------------
clk 2 0 0 0 0
---------------------------------------------------------------------------------------
Total 2 0 0 0 0
---------------------------------------------------------------------------------------
Note the above table per clock tree is based on CCOpt clock tree view. The violations are counted across half corners.
Found a total of 2 clock tree pins with max capacitance violations.
Found a total of 2 max capacitance violations.
Total violation amount 1.229pF.
Max capacitance violation summary across all clock trees - Top 2 violations:
============================================================================
Target and measured capacitances (in pF):
--------------------------------------------------------------------------------------------
Half corner Violation Capacitance Capacitance Target Pin
amount target achieved source
--------------------------------------------------------------------------------------------
SS:setup.late 1.229 0.140 1.369 library_or_sdc_constraint clkpad/COREIO
SS:setup.late 0.000 0.000 0.000 clock_root_forced clk
--------------------------------------------------------------------------------------------
Target sources:
target_max_capacitance_property - the target was set in the target_max_capacitance property
library_or_sdc_constraint - the non-frequency-dependent target was set in a library file or by an SDC constraint
frequency_dependent_library_or_sdc_constraint - the frequency-dependent target was set in a library file or by an SDC constraint
computed_from_slew_target - the target was calculated based on the slew target at a clock root
clock_root_forced - the target was forced to be zero at a clock root
Found a total of 0 clock tree nets with max resistance violations.
Found a total of 0 clock tree nets with max length violations.
Found a total of 0 clock tree nets with max fanout violations.
Found a total of 0 clock tree pins with a slew violation.
Report for clock tree: clk
==========================
Clock Tree Gating Structure (Logical):
# Full cycle clock gates : 0
Minimum clock gating depth : 0
Maximum clock gating depth : 0
Clock gate area (um^2) : 0.000
Clock Tree Buffering Structure (Logical):
# Buffers : 8
# Inverters : 0
Total : 8
Minimum depth : 5
Maximum depth : 5
Buffering area (um^2) : 71.240
Clock Tree Level Structure (Logical):
---------------------------------------------------------------------------
Level # Full # Posedge # Negedge # RAM # Enable # Non enable # Other
Cycle Flops Flops Clock Latch Latch Sinks
Pins Sinks Sinks
---------------------------------------------------------------------------
root 0 463 0 0 0 1 0
---------------------------------------------------------------------------
Total 0 463 0 0 0 1 0
---------------------------------------------------------------------------
Target and measured clock slews (in ns):
-------------------------------------------------------------------------------------------------------------------------------
Timing Corner Worst Rising Worst Falling Worst Rising Worst Falling Leaf Slew Leaf Slew Trunk Slew Trunk Slew
Leaf Slew Leaf Slew Trunk Slew Trunk Slew Target Type Target Target Type Target
-------------------------------------------------------------------------------------------------------------------------------
FF:hold.early 0.034 0.036 0.025 0.024 ignored - ignored -
FF:hold.late 0.037 0.036 0.027 0.027 ignored - ignored -
SS:setup.early 0.110 0.106 0.076 0.069 ignored - ignored -
SS:setup.late 0.122 0.106 0.085 0.077 auto extracted 0.200 auto extracted 0.200
-------------------------------------------------------------------------------------------------------------------------------
* - indicates that target was not met.
auto extracted - target was extracted from SDC.
auto computed - target was computed when balancing trees.