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skewgrp_ccopt.rpt
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###############################################################
# Generated by: Cadence Innovus 16.13-s045_1
# OS: Linux x86_64(Host ID toke.fransg.eit.lth.se)
# Generated on: Wed Feb 21 14:36:57 2024
# Design: jollof_top
# Command: report_ccopt_skew_groups -filename ./skewgrp_ccopt.rpt
###############################################################
Skew Group Structure:
=====================
--------------------------------------------------------------------
Skew Group Sources Constrained Sinks Ignore Sinks
--------------------------------------------------------------------
clk/Clock_Constraint 1 464 0
--------------------------------------------------------------------
Skew Group Summary:
===================
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Corner Skew Group ID Target Min ID Max ID Avg ID Std.Dev. ID Skew Target Type Skew Target Skew Skew window occupancy
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SS:setup.early clk/Clock_Constraint - 0.343 0.362 0.354 0.005 ignored - 0.019 -
SS:setup.late clk/Clock_Constraint none 0.860 0.882 0.872 0.006 auto computed 0.121 0.022 100% {0.860, 0.872, 0.882}
FF:hold.early clk/Clock_Constraint - 0.101 0.107 0.104 0.001 ignored - 0.006 -
FF:hold.late clk/Clock_Constraint - 0.605 0.612 0.609 0.002 ignored - 0.007 -
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
* - indicates that target was not met.
Skew Group Min/Max path pins:
=============================
------------------------------------------------------------------------------
Timing Corner Skew Group Min ID PathID Max ID PathID
------------------------------------------------------------------------------
SS:setup.early clk/Clock_Constraint 0.343 1 0.362 2
- min Controller_inst/in3_reg_reg[0]/CP
- max Controller_inst/in3_reg_reg[43]/CP
SS:setup.late clk/Clock_Constraint 0.860 3 0.882 4
- min Controller_inst/coef1_reg_reg[3]/CP
- max Controller_inst/in3_reg_reg[43]/CP
FF:hold.early clk/Clock_Constraint 0.101 5 0.107 6
- min Controller_inst/in3_reg_reg[1]/CP
- max Controller_inst/in3_reg_reg[43]/CP
FF:hold.late clk/Clock_Constraint 0.605 7 0.612 8
- min Controller_inst/coef2_reg_reg[3]/CP
- max Controller_inst/in3_reg_reg[47]/CP
------------------------------------------------------------------------------
Timing for timing corner SS:setup.early, min clock_path:
========================================================
PathID : 1
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/in3_reg_reg[0]/CP
Delay : 0.343
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.000 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.000 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.002 0.003 1.369 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.000 0.002 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.050 0.052 0.020 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.052 0.020 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.065 0.117 0.026 0.005 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.117 0.026 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.083 0.200 0.071 0.075 (159.855,286.775) 1.440 5
Controller_inst/CTS_ccl_BUF_clk_G0_L5_2/A
- HS65_LL_CNBFX82 rise 0.017 0.216 0.076 - (341.200,227.020) 241.100 -
Controller_inst/CTS_ccl_BUF_clk_G0_L5_2/Z
- HS65_LL_CNBFX82 rise 0.126 0.342 0.085 0.176 (339.900,226.630) 1.690 100
Controller_inst/in3_reg_reg[0]/CP
- HS65_LL_DFPQX9 rise 0.001 0.343 0.085 - (336.350,227.190) 4.110 -
--------------------------------------------------------------------------------------------------------
Timing for timing corner SS:setup.early, max clock_path:
========================================================
PathID : 2
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/in3_reg_reg[19]/CP
Delay : 0.362
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.000 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.000 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.002 0.003 1.369 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.000 0.002 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.050 0.052 0.020 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.052 0.020 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.065 0.117 0.026 0.005 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.117 0.026 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.083 0.200 0.071 0.075 (159.855,286.775) 1.440 5
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/A
- HS65_LL_CNBFX62 rise 0.016 0.216 0.076 - (324.410,229.050) 222.280 -
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/Z
- HS65_LL_CNBFX62 rise 0.140 0.356 0.110 0.180 (325.505,229.570) 1.615 100
Controller_inst/in3_reg_reg[19]/CP
- HS65_LL_DFPQX9 rise 0.005 0.362 0.110 - (294.350,223.810) 36.915 -
--------------------------------------------------------------------------------------------------------
Timing for timing corner SS:setup.late, min clock_path:
=======================================================
PathID : 3
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/coef1_reg_reg[3]/CP
Delay : 0.860
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.500 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.500 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.502 0.003 1.369 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.000 0.502 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.051 0.553 0.021 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.553 0.021 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.067 0.620 0.028 0.005 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.620 0.028 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.086 0.706 0.079 0.075 (159.855,286.775) 1.440 5
CTS_ccl_BUF_clk_G0_L5_1/A
- HS65_LL_CNBFX82 rise 0.019 0.725 0.085 - (309.800,187.580) 249.140 -
CTS_ccl_BUF_clk_G0_L5_1/Z
- HS65_LL_CNBFX82 rise 0.130 0.855 0.090 0.166 (311.100,187.970) 1.690 64
Controller_inst/coef1_reg_reg[3]/CP
- HS65_LL_DFPQX9 rise 0.005 0.860 0.091 - (317.350,211.590) 29.870 -
--------------------------------------------------------------------------------------------------------
Timing for timing corner SS:setup.late, max clock_path:
=======================================================
PathID : 4
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/in3_reg_reg[22]/CP
Delay : 0.882
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.500 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.500 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.502 0.003 1.369 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.000 0.502 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.051 0.553 0.021 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.553 0.021 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.067 0.620 0.028 0.005 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.620 0.028 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.086 0.706 0.079 0.075 (159.855,286.775) 1.440 5
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/A
- HS65_LL_CNBFX62 rise 0.019 0.725 0.085 - (324.410,229.050) 222.280 -
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/Z
- HS65_LL_CNBFX62 rise 0.151 0.876 0.121 0.180 (325.505,229.570) 1.615 100
Controller_inst/in3_reg_reg[22]/CP
- HS65_LL_DFPQX9 rise 0.006 0.882 0.122 - (292.750,216.790) 45.535 -
--------------------------------------------------------------------------------------------------------
Timing for timing corner FF:hold.early, min clock_path:
=======================================================
PathID : 5
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/in3_reg_reg[1]/CP
Delay : 0.101
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.000 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.000 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.002 0.003 1.366 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.000 0.002 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.016 0.018 0.007 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.018 0.007 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.018 0.037 0.008 0.004 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.037 0.008 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.023 0.060 0.022 0.061 (159.855,286.775) 1.440 5
Controller_inst/CTS_ccl_BUF_clk_G0_L5_2/A
- HS65_LL_CNBFX82 rise 0.007 0.067 0.025 - (341.200,227.020) 241.100 -
Controller_inst/CTS_ccl_BUF_clk_G0_L5_2/Z
- HS65_LL_CNBFX82 rise 0.034 0.101 0.027 0.145 (339.900,226.630) 1.690 100
Controller_inst/in3_reg_reg[1]/CP
- HS65_LL_DFPQX9 rise 0.000 0.101 0.027 - (338.450,223.810) 4.270 -
--------------------------------------------------------------------------------------------------------
Timing for timing corner FF:hold.early, max clock_path:
=======================================================
PathID : 6
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/in3_reg_reg[22]/CP
Delay : 0.107
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.000 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.000 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.002 0.003 1.366 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.000 0.002 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.016 0.018 0.007 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.018 0.007 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.018 0.037 0.008 0.004 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.037 0.008 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.023 0.060 0.022 0.061 (159.855,286.775) 1.440 5
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/A
- HS65_LL_CNBFX62 rise 0.006 0.066 0.025 - (324.410,229.050) 222.280 -
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/Z
- HS65_LL_CNBFX62 rise 0.039 0.105 0.034 0.148 (325.505,229.570) 1.615 100
Controller_inst/in3_reg_reg[22]/CP
- HS65_LL_DFPQX9 rise 0.002 0.107 0.034 - (292.750,216.790) 45.535 -
--------------------------------------------------------------------------------------------------------
Timing for timing corner FF:hold.late, min clock_path:
======================================================
PathID : 7
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/coef2_reg_reg[3]/CP
Delay : 0.605
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.500 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.500 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.502 0.003 1.366 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.001 0.503 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.016 0.519 0.007 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.519 0.007 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.019 0.538 0.009 0.004 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.538 0.009 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.023 0.561 0.024 0.061 (159.855,286.775) 1.440 5
CTS_ccl_BUF_clk_G0_L5_1/A
- HS65_LL_CNBFX82 rise 0.008 0.569 0.027 - (309.800,187.580) 249.140 -
CTS_ccl_BUF_clk_G0_L5_1/Z
- HS65_LL_CNBFX82 rise 0.035 0.604 0.028 0.138 (311.100,187.970) 1.690 64
Controller_inst/coef2_reg_reg[3]/CP
- HS65_LL_DFPQX9 rise 0.002 0.605 0.028 - (314.750,208.210) 23.890 -
--------------------------------------------------------------------------------------------------------
Timing for timing corner FF:hold.late, max clock_path:
======================================================
PathID : 8
Path type : skew group clk/Clock_Constraint (path 1 of 1)
Start : clk
End : Controller_inst/in3_reg_reg[11]/CP
Delay : 0.612
--------------------------------------------------------------------------------------------------------
Name Lib cell Event Incr Arrival Slew Cap Location Distance Fanout Status
(ns) (ns) (ns) (pF) (um)
-- Clockpath trace -------------------------------------------------------------------------------------
clk
- - rise - 0.500 0.000 0.000 (3.605,289.195) - 1
clkpad/PADIO
- CPAD_S_74x50u_IN rise 0.000 0.500 0.003 - (3.605,289.195) 0.000 -
clkpad/COREIO
- CPAD_S_74x50u_IN rise 0.002 0.502 0.003 1.366 (69.770,310.255) 87.225 1
CTS_cpc_drv_BUF_clk_G0_L2_1/A
- HS65_LL_CNBFX14 rise 0.001 0.503 0.003 - (155.045,286.335) 109.195 -
CTS_cpc_drv_BUF_clk_G0_L2_1/Z
- HS65_LL_CNBFX14 rise 0.016 0.519 0.007 0.002 (155.535,286.810) 0.965 1
CTS_cmf_BUF_clk_G0_L3_1/A
- HS65_LL_CNBFX14 rise 0.000 0.519 0.007 - (156.645,286.335) 1.585 -
CTS_cmf_BUF_clk_G0_L3_1/Z
- HS65_LL_CNBFX14 rise 0.019 0.538 0.009 0.004 (157.135,286.810) 0.965 1
CTS_ccl_BUF_clk_G0_L4_1/A
- HS65_LL_CNBFX45 rise 0.000 0.538 0.009 - (158.820,286.370) 2.125 -
CTS_ccl_BUF_clk_G0_L4_1/Z
- HS65_LL_CNBFX45 rise 0.023 0.561 0.024 0.061 (159.855,286.775) 1.440 5
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/A
- HS65_LL_CNBFX62 rise 0.007 0.569 0.027 - (324.410,229.050) 222.280 -
Controller_inst/CTS_ccl_BUF_clk_G0_L5_4/Z
- HS65_LL_CNBFX62 rise 0.041 0.610 0.037 0.148 (325.505,229.570) 1.615 100
Controller_inst/in3_reg_reg[11]/CP
- HS65_LL_DFPQX9 rise 0.002 0.612 0.037 - (294.350,221.990) 38.735 -
--------------------------------------------------------------------------------------------------------