diff --git a/hw/application_fpga/core/tk1/rtl/tk1.v b/hw/application_fpga/core/tk1/rtl/tk1.v
index cbd6e3d0..8d163dbe 100644
--- a/hw/application_fpga/core/tk1/rtl/tk1.v
+++ b/hw/application_fpga/core/tk1/rtl/tk1.v
@@ -330,6 +330,10 @@ module tk1(
 	    tmp_force_trap = 1'h1;
 	  end
 
+	  if (~cpu_addr[31] & cpu_addr[30] & |cpu_addr[29 : 17]) begin
+	    tmp_force_trap = 1'h1;
+	  end
+
 	  if (cpu_mon_en_reg) begin
 	    if ((cpu_addr >= cpu_mon_first_reg) &&
 		(cpu_addr <= cpu_mon_last_reg)) begin
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index 6755e8b1..00a229cd 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -434,17 +434,10 @@ module application_fpga(
             end
 
             RAM_PREFIX: begin
-	      if (|cpu_addr[29 : 17]) begin
-		muxed_rdata_new = 32'hdeadbeef;
-		muxed_ready_new = 1'h1;
-		ram_cs          = 1'h0;
-		ram_we          = 4'h0;
-	      end else begin
-		ram_cs          = 1'h1;
-		ram_we          = cpu_wstrb;
-		muxed_rdata_new = ram_read_data ^ ram_scramble ^ {2{cpu_addr[15 : 0]}};
-		muxed_ready_new = ram_ready;
-              end
+	      ram_cs          = 1'h1;
+	      ram_we          = cpu_wstrb;
+	      muxed_rdata_new = ram_read_data ^ ram_scramble ^ {2{cpu_addr[15 : 0]}};
+	      muxed_ready_new = ram_ready;
 	    end
 
             RESERVED_PREFIX: begin