Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Investigate increased througput of the TRNG #255

Open
dehanj opened this issue Aug 21, 2024 · 0 comments
Open

Investigate increased througput of the TRNG #255

dehanj opened this issue Aug 21, 2024 · 0 comments
Labels
enhancement New feature or request fpga Related to the FPGA design

Comments

@dehanj
Copy link
Member

dehanj commented Aug 21, 2024

The current TRNG has a defined sample cycle to sample every 1000th clock tick, currently giving 21 kHz (or 18 kHz in the latest release). It might be possible to increase the throughput, by sampling more often, without lowering the quality.

It needs however to be investigated, dumping out large amounts of data and running it through relevant tools (such as PRACTRAND and ENT) to see if there is a difference.

in rosc.v

  localparam SAMPLE_CYCLES = 16'h1000;
@dehanj dehanj added enhancement New feature or request fpga Related to the FPGA design labels Aug 21, 2024
@mchack-work mchack-work changed the title Investigate increased throughout of the TRNG Investigate increased througput of the TRNG Aug 26, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request fpga Related to the FPGA design
Projects
None yet
Development

No branches or pull requests

1 participant