Skip to content

Latest commit

 

History

History
73 lines (54 loc) · 2.72 KB

README.md

File metadata and controls

73 lines (54 loc) · 2.72 KB
Raw

SystemVerilog Analysis Library

This directory contains libraries for analyzing SystemVerilog code. Analysis is often done on the token stream and syntax tree from the lexer and parser, as read-only operations.

Linter user documentation can be found here.

Partial File or Single Construct Parsing

For cases where one wishes to parse only subset of the grammar, e.g. module-body-items, we provide wrappers around the full-parser. This approach maximizes reuse of the full language parser without having to generate or slice out separate grammars, and guarantees consistent concrete syntax tree node enumerations.

Alternative Parsing Modes

Source files that are known to be indented for inclusion in another syntactic context may trigger an alternative parsing mode with comment directives. These directives are understood by tools including the style-linter and formatter.

The following example would normally fail to compile because wire declarations can only occur inside modules:

// This file is `included inside a module definition body.
// verilog_syntax: parse-as-module-body
wire x;
initial begin
  x = 0;
end

However, the verilog_syntax directive tells the parser (in this case) that the contents of this file are to be treated as if they are inside a module declaration. Scanning for this directive stops as soon as any non-preprocessing-control token is encountered (after `ifndef or comments is ok, but not after any keyword like module, for instance).

Available parser modes include:

  • parse-as-statements: Text contains only statements (e.g. inside function, always, ...)
  • parse-as-expression: Text occurs inside an expression.
  • parse-as-module-body: Text occurs inside a module definition.
  • parse-as-class-body: Text occurs inside a class definition.
  • parse-as-package-body: Text occurs inside a package definition.
  • parse-as-library-map: Verilog library map sub-language (LRM: Ch. 33).

Lint Rules

Individual lint rules live under checkers. The global lint rule registry manager the entire collection of lint rules. The lint analysis driver traverses the structural representation of the code-under-analysis as configured.

The default-enabled set of lint rules is maintained here.

Linter tool user documentation can be found here.

Equivalence Checking

Lexical equivalence checking verifies that two Verilog source files are equivalent under various conditions.

Diff tool user documentation can be found here.