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sfr62p.h
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/****************************************************************************
* *
* file name : definition of M16C/62P's SFR *
* *
* Copyright : MITSUBISHI ELECTRIC CORPORATION *
* *
* Version : 1.00 ( 2002- 4- ) Initial *
*****************************************************************************/
/*
note:
This data is a freeware that SFR for M16C/62P groups is described.
Mitsubishi Electric Corporation assumes no responsibility for any damage
that occurred by this data.
*/
/********************************************************
* declare SFR addresses *
********************************************************/
#ifndef SFR62P_H
#define SFR62P_H
#pragma ADDRESS pm0_addr 0004H /* Processor mode register 0 */
#pragma ADDRESS pm1_addr 0005H /* Processor mode register 1 */
#pragma ADDRESS cm0_addr 0006H /* System clock control register 0 */
#pragma ADDRESS cm1_addr 0007H /* System clock control register 1 */
#pragma ADDRESS csr_addr 0008H /* Chip select control register */
#pragma ADDRESS aier_addr 0009H /* Address match interrupt enable register */
#pragma ADDRESS prcr_addr 000aH /* Protect register */
#pragma ADDRESS dbr_addr 000bH /* Data bank register */
#pragma ADDRESS cm2_addr 000cH /* Oscillation stop detection register */
#pragma ADDRESS cm3_addr 000dH /* Ring mode register */
#pragma ADDRESS wdts_addr 000eH /* Watchdog timer start register */
#pragma ADDRESS wdc_addr 000fH /* Watchdog timer control register */
#pragma ADDRESS rmad0_addr 0010H /* Address match interrupt register 0 */
#pragma ADDRESS rmad1_addr 0014H /* Address match interrupt register 1 */
#pragma ADDRESS cse_addr 001bH /* Chip select expansion control register */
#pragma ADDRESS plc0_addr 001cH /* PLC control register 0 */
#pragma ADDRESS pm2_addr 001eH /* Processor mode register 2 */
#pragma ADDRESS sar0_addr 0020H /* DMA0 source pointer */
#pragma ADDRESS dar0_addr 0024H /* DMA0 destination pointer */
#pragma ADDRESS tcr0_addr 0028H /* DMA0 transfer counter */
#pragma ADDRESS dm0con_addr 002cH /* DMA0 control register */
#pragma ADDRESS sar1_addr 0030H /* DMA1 source pointer */
#pragma ADDRESS dar1_addr 0034H /* DMA1 destination pointer */
#pragma ADDRESS tcr1_addr 0038H /* DMA1 transfer counter */
#pragma ADDRESS dm1con_addr 003cH /* DMA1 control register */
#pragma ADDRESS int3ic_addr 0044H /* INT3~ interrupt control register */
#pragma ADDRESS tb5ic_addr 0045H /* Timer B5 interrupt control register */
#pragma ADDRESS tb4ic_addr 0046H /* Timer B4 interrupt control register */
#pragma ADDRESS tb3ic_addr 0047H /* Timer B3 interrupt control register */
#pragma ADDRESS s4ic_addr 0048H /* SI/O4 interrupt control register */
#pragma ADDRESS s3ic_addr 0049H /* SI/O3 interrupt control register */
#pragma ADDRESS int5ic_addr 0048H /* INT5~ interrupt control register */
#pragma ADDRESS int4ic_addr 0049H /* INT4~ interrupt control register */
#pragma ADDRESS bcnic_addr 004aH /* Bus collision detection interrupt control register */
#pragma ADDRESS dm0ic_addr 004bH /* DMA0 interrupt control register */
#pragma ADDRESS dm1ic_addr 004cH /* DMA1 interrupt control register */
#pragma ADDRESS kupic_addr 004dH /* Key input interrupt control register */
#pragma ADDRESS adic_addr 004eH /* A-D conversion interrupt control register */
#pragma ADDRESS s2tic_addr 004fH /* UART2 transmit interrupt control register */
#pragma ADDRESS s2ric_addr 0050H /* UART2 receive interrupt control register */
#pragma ADDRESS s0tic_addr 0051H /* UART0 transmit interrupt control register */
#pragma ADDRESS s0ric_addr 0052H /* UART0 receive interrupt control register */
#pragma ADDRESS s1tic_addr 0053H /* UART1 transmit interrupt control register */
#pragma ADDRESS s1ric_addr 0054H /* UART1 receive interrupt control register */
#pragma ADDRESS ta0ic_addr 0055H /* Timer A0 interrupt control register */
#pragma ADDRESS ta1ic_addr 0056H /* Timer A1 interrupt control register */
#pragma ADDRESS ta2ic_addr 0057H /* Timer A2 interrupt control register */
#pragma ADDRESS ta3ic_addr 0058H /* Timer A3 interrupt control register */
#pragma ADDRESS ta4ic_addr 0059H /* Timer A4 interrupt control register */
#pragma ADDRESS tb0ic_addr 005aH /* Timer B0 interrupt control register */
#pragma ADDRESS tb1ic_addr 005bH /* Timer B1 interrupt control register */
#pragma ADDRESS tb2ic_addr 005cH /* Timer B2 interrupt control register */
#pragma ADDRESS int0ic_addr 005dH /* INT0~ interrupt control register */
#pragma ADDRESS int1ic_addr 005eH /* INT1~ interrupt control register */
#pragma ADDRESS int2ic_addr 005fH /* INT2~ interrupt control register */
#pragma ADDRESS fmr1_addr 01b5H /* Flash memory control register 1 */
#pragma ADDRESS fmr0_addr 01b7H /* Flash memory control register 0 */
#pragma ADDRESS rmad2_addr 01b8H /* Address match interrupt register 2 */
#pragma ADDRESS aier2_addr 01bbH /* Address match interrupt enable register 2 */
#pragma ADDRESS rmad3_addr 01bcH /* Address match interrupt register 3 */
#pragma ADDRESS pclkr_addr 025eH /* Peripheral clock select register */
#pragma ADDRESS tbsr_addr 0340H /* Timer B3,4,5 count start flag */
#pragma ADDRESS ta11_addr 0342H /* Timer A1-1 register */
#pragma ADDRESS ta21_addr 0344H /* Timer A2-1 register */
#pragma ADDRESS ta41_addr 0346H /* Timer A4-1 register */
#pragma ADDRESS invc0_addr 0348H /* Three-phase PWM control regester 0 */
#pragma ADDRESS invc1_addr 0349H /* Three-phase PWM control register 1 */
#pragma ADDRESS idb0_addr 034aH /* Three-phase output buffer register 0 */
#pragma ADDRESS idb1_addr 034bH /* Three-phase output buffer register 1 */
#pragma ADDRESS dtt_addr 034cH /* Dead time timer */
#pragma ADDRESS ictb2_addr 034dH /* Timer B2 interrupt occurrences frequency set counter */
#pragma ADDRESS tb3_addr 0350H /* Timer B3 register */
#pragma ADDRESS tb4_addr 0352H /* Timer B4 register */
#pragma ADDRESS tb5_addr 0354H /* Timer B5 register */
#pragma ADDRESS tb3mr_addr 035bH /* Timer B3 mode register */
#pragma ADDRESS tb4mr_addr 035cH /* Timer B4 mode register */
#pragma ADDRESS tb5mr_addr 035dH /* Timer B5 mode register */
#pragma ADDRESS ifsr2a_addr 035eH /* Interrupt request cause select register 2 */
#pragma ADDRESS ifsr_addr 035fH /* Interrupt request cause select register */
#pragma ADDRESS s3trr_addr 0360H /* SI/O3 transmit/receive register */
#pragma ADDRESS s3c_addr 0362H /* SI/O3 control register */
#pragma ADDRESS s3brg_addr 0363H /* SI/O3 bit rate generator */
#pragma ADDRESS s4trr_addr 0364H /* SI/O4 transmit/receive register */
#pragma ADDRESS s4c_addr 0366H /* SI/O4 control register */
#pragma ADDRESS s4brg_addr 0367H /* SI/O4 bit rate generator */
#pragma ADDRESS u0smr4_addr 036cH /* UART0 special mode register 4 */
#pragma ADDRESS u0smr3_addr 036dH /* UART0 special mode register 3 */
#pragma ADDRESS u0smr2_addr 036eH /* UART0 special mode register 2 */
#pragma ADDRESS u0smr_addr 036fH /* UART0 special mode register */
#pragma ADDRESS u1smr4_addr 0370H /* UART1 special mode register 4 */
#pragma ADDRESS u1smr3_addr 0371H /* UART1 special mode register 3 */
#pragma ADDRESS u1smr2_addr 0372H /* UART1 special mode register 2 */
#pragma ADDRESS u1smr_addr 0373H /* UART1 special mode register */
#pragma ADDRESS u2smr4_addr 0374H /* UART2 special mode register 4 */
#pragma ADDRESS u2smr3_addr 0375H /* UART2 special mode register 3 */
#pragma ADDRESS u2smr2_addr 0376H /* UART2 special mode register 2 */
#pragma ADDRESS u2smr_addr 0377H /* UART2 special mode register */
#pragma ADDRESS u2mr_addr 0378H /* UART2 transmit/receive mode register */
#pragma ADDRESS u2brg_addr 0379H /* UART2 bit rate generator */
#pragma ADDRESS u2tb_addr 037aH /* UART2 transmit buffer register */
#pragma ADDRESS u2c0_addr 037cH /* UART2 transmit/receive control register 0 */
#pragma ADDRESS u2c1_addr 037dH /* UART2 transmit/receive control register 1 */
#pragma ADDRESS u2rb_addr 037eH /* UART2 receive buffer register */
#pragma ADDRESS tabsr_addr 0380H /* Count start flag */
#pragma ADDRESS cpsrf_addr 0381H /* Clock prescaler reset flag */
#pragma ADDRESS onsf_addr 0382H /* One-shot start flag */
#pragma ADDRESS trgsr_addr 0383H /* Trigger select register */
#pragma ADDRESS udf_addr 0384H /* Up/down flag */
#pragma ADDRESS ta0_addr 0386H /* Timer A0 register */
#pragma ADDRESS ta1_addr 0388H /* Timer A1 register */
#pragma ADDRESS ta2_addr 038aH /* Timer A2 register */
#pragma ADDRESS ta3_addr 038cH /* Timer A3 register */
#pragma ADDRESS ta4_addr 038eH /* Timer A4 register */
#pragma ADDRESS tb0_addr 0390H /* Timer B0 register */
#pragma ADDRESS tb1_addr 0392H /* Timer B1 register */
#pragma ADDRESS tb2_addr 0394H /* Timer B2 register */
#pragma ADDRESS ta0mr_addr 0396H /* Timer A0 mode register */
#pragma ADDRESS ta1mr_addr 0397H /* Timer A1 mode register */
#pragma ADDRESS ta2mr_addr 0398H /* Timer A2 mode register */
#pragma ADDRESS ta3mr_addr 0399H /* Timer A3 mode register */
#pragma ADDRESS ta4mr_addr 039aH /* Timer A4 mode register */
#pragma ADDRESS tb0mr_addr 039bH /* Timer B0 mode register */
#pragma ADDRESS tb1mr_addr 039cH /* Timer B1 mode register */
#pragma ADDRESS tb2mr_addr 039dH /* Timer B2 mode register */
#pragma ADDRESS tb2sc_addr 039eH /* Timer B2 special mode register */
#pragma ADDRESS u0mr_addr 03a0H /* UART0 transmit/receive mode register */
#pragma ADDRESS u0brg_addr 03a1H /* UART0 bit rate generator */
#pragma ADDRESS u0tb_addr 03a2H /* UART0 transmit buffer register */
#pragma ADDRESS u0c0_addr 03a4H /* UART0 transmit/receive control register 0 */
#pragma ADDRESS u0c1_addr 03a5H /* UART0 transmit/receive control register 1 */
#pragma ADDRESS u0rb_addr 03a6H /* UART0 receive buffer register */
#pragma ADDRESS u1mr_addr 03a8H /* UART1 transmit/receive mode register */
#pragma ADDRESS u1brg_addr 03a9H /* UART1 bit rate generator */
#pragma ADDRESS u1tb_addr 03aaH /* UART1 transmit buffer register */
#pragma ADDRESS u1c0_addr 03acH /* UART1 transmit/receive control register 0 */
#pragma ADDRESS u1c1_addr 03adH /* UART1 transmit/receive control register 1 */
#pragma ADDRESS u1rb_addr 03aeH /* UART1 receive buffer register */
#pragma ADDRESS ucon_addr 03b0H /* UART transmit/receive control register 2 */
#pragma ADDRESS fidr_addr 03b4H /* Flash identification register */
#pragma ADDRESS dm0sl_addr 03b8H /* DMA0 cause select register */
#pragma ADDRESS dm1sl_addr 03baH /* DMA1 cause select register */
#pragma ADDRESS crcd_addr 03bcH /* CRC data register */
#pragma ADDRESS crcin_addr 03beH /* CRC input register */
#pragma ADDRESS ad0_addr 03c0H /* A-D register 0 */
#pragma ADDRESS ad1_addr 03c2H /* A-D register 1 */
#pragma ADDRESS ad2_addr 03c4H /* A-D register 2 */
#pragma ADDRESS ad3_addr 03c6H /* A-D register 3 */
#pragma ADDRESS ad4_addr 03c8H /* A-D register 4 */
#pragma ADDRESS ad5_addr 03caH /* A-D register 5 */
#pragma ADDRESS ad6_addr 03ccH /* A-D register 6 */
#pragma ADDRESS ad7_addr 03ceH /* A-D register 7 */
#pragma ADDRESS adcon2_addr 03d4H /* A-D control register 2 */
#pragma ADDRESS adcon0_addr 03d6H /* A-D control register 0 */
#pragma ADDRESS adcon1_addr 03d7H /* A-D control register 1 */
#pragma ADDRESS da0_addr 03d8H /* D-A register 0 */
#pragma ADDRESS da1_addr 03daH /* D-A register 1 */
#pragma ADDRESS dacon_addr 03dcH /* D-A control register */
#pragma ADDRESS pc14_addr 03deH /* Port P14 control register */
#pragma ADDRESS pur3_addr 03dfH /* Pull-up control register 3 */
#pragma ADDRESS p0_addr 03e0H /* Port P0 register */
#pragma ADDRESS p1_addr 03e1H /* Port P1 register */
#pragma ADDRESS pd0_addr 03e2H /* Port P0 direction register */
#pragma ADDRESS pd1_addr 03e3H /* Port P1 direction register */
#pragma ADDRESS p2_addr 03e4H /* Port P2 register */
#pragma ADDRESS p3_addr 03e5H /* Port P3 register */
#pragma ADDRESS pd2_addr 03e6H /* Port P2 direction register */
#pragma ADDRESS pd3_addr 03e7H /* Port P3 direction register */
#pragma ADDRESS p4_addr 03e8H /* Port P4 register */
#pragma ADDRESS p5_addr 03e9H /* Port P5 register */
#pragma ADDRESS pd4_addr 03eaH /* Port P4 direction register */
#pragma ADDRESS pd5_addr 03ebH /* Port P5 direction register */
#pragma ADDRESS p6_addr 03ecH /* Port P6 register */
#pragma ADDRESS p7_addr 03edH /* Port P7 register */
#pragma ADDRESS pd6_addr 03eeH /* Port P6 direction register */
#pragma ADDRESS pd7_addr 03efH /* Port P7 direction register */
#pragma ADDRESS p8_addr 03f0H /* Port P8 register */
#pragma ADDRESS p9_addr 03f1H /* Port P9 register */
#pragma ADDRESS pd8_addr 03f2H /* Port P8 direction register */
#pragma ADDRESS pd9_addr 03f3H /* Port P9 direction register */
#pragma ADDRESS p10_addr 03f4H /* Port P10 register */
#pragma ADDRESS p11_addr 03f5H /* Port P11 register */
#pragma ADDRESS pd10_addr 03f6H /* Port P10 direction register */
#pragma ADDRESS pd11_addr 03f7H /* Port P11 direction register */
#pragma ADDRESS p12_addr 03f8H /* Port P12 register */
#pragma ADDRESS p13_addr 03f9H /* Port P13 register */
#pragma ADDRESS pd12_addr 03faH /* Port P12 direction register */
#pragma ADDRESS pd13_addr 03fbH /* Port P13 direction register */
#pragma ADDRESS pur0_addr 03fcH /* Pull-up control register 0 */
#pragma ADDRESS pur1_addr 03fdH /* Pull-up control register 1 */
#pragma ADDRESS pur2_addr 03feH /* Pull-up control register 2 */
#pragma ADDRESS pcr_addr 03ffH /* Port control register */
/********************************************************
* declare SFR char *
********************************************************/
unsigned char da0_addr; /* D-A register 0 */
#define da0 da0_addr
unsigned char da1_addr; /* D-A register 1 */
#define da1 da1_addr
/*--------------------------------------------------------
Up/down flag ; Use "MOV" instruction when writing to this register.
--------------------------------------------------------*/
unsigned char udf_addr;
#define udf udf_addr
/********************************************************
* declare SFR short *
********************************************************/
/*--------------------------------------------------------
Timer registers : Read and write data in 16-bit units.
--------------------------------------------------------*/
unsigned short ta11_addr; /* Timer A1-1 register */
#define ta11 ta11_addr
unsigned short ta21_addr; /* Timer A2-1 register */
#define ta21 ta21_addr
unsigned short ta41_addr; /* Timer A4-1 register */
#define ta41 ta41_addr
unsigned short tb3_addr; /* Timer B3 register */
#define tb3 tb3_addr
unsigned short tb4_addr; /* Timer B4 register */
#define tb4 tb4_addr
unsigned short tb5_addr; /* Timer B5 register */
#define tb5 tb5_addr
unsigned short ta0_addr; /* Timer A0 register */
#define ta0 ta0_addr
unsigned short ta1_addr; /* Timer A1 register */
#define ta1 ta1_addr
unsigned short ta2_addr; /* Timer A2 register */
#define ta2 ta2_addr
unsigned short ta3_addr; /* Timer A3 register */
#define ta3 ta3_addr
unsigned short ta4_addr; /* Timer A4 register */
#define ta4 ta4_addr
unsigned short tb0_addr; /* Timer B0 register */
#define tb0 tb0_addr
unsigned short tb1_addr; /* Timer B1 register */
#define tb1 tb1_addr
unsigned short tb2_addr; /* Timer B2 register */
#define tb2 tb2_addr
/********************************************************
* declare SFR bit *
********************************************************/
struct bit_def {
char b0:1;
char b1:1;
char b2:1;
char b3:1;
char b4:1;
char b5:1;
char b6:1;
char b7:1;
};
union byte_def{
struct bit_def bit;
char byte;
};
/*------------------------------------------------------
Processor mode register 0
------------------------------------------------------*/
union byte_def pm0_addr;
#define pm0 pm0_addr.byte
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
#define pm02 pm0_addr.bit.b2 /* R/W mode select bit */
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */
#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */
#define pm06 pm0_addr.bit.b6 /* Port P4_0 to P4_3 function select bit */
#define pm07 pm0_addr.bit.b7 /* BCLK output disable bit */
/*------------------------------------------------------
Processor mode register 1
------------------------------------------------------*/
union byte_def pm1_addr;
#define pm1 pm1_addr.byte
#define pm10 pm1_addr.bit.b0 /* CS2 area switching bit */
#define pm11 pm1_addr.bit.b1 /* Port P3_4 to P3_7 function select bit */
#define pm12 pm1_addr.bit.b2 /* Watch dog timer function select bit */
#define pm13 pm1_addr.bit.b3 /* Intermal reserved area expansion bit */
#define pm14 pm1_addr.bit.b4 /* Memory area expansion bit */
#define pm15 pm1_addr.bit.b5 /* Memory area expansion bit */
#define pm17 pm1_addr.bit.b7 /* Wait bit */
/*------------------------------------------------------
System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define cm0 cm0_addr.byte
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
#define cm06 cm0_addr.bit.b6 /* Main clock division select bit 0 */
#define cm07 cm0_addr.bit.b7 /* System clock select bit */
/*------------------------------------------------------
System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define cm1 cm1_addr.byte
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
#define cm11 cm1_addr.bit.b1 /* System clock select bit */
#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
#define cm16 cm1_addr.bit.b6 /* Main clock division select bit 1 */
#define cm17 cm1_addr.bit.b7 /* Main clock division select bit 1 */
/*------------------------------------------------------
Chip select control register
------------------------------------------------------*/
union byte_def csr_addr;
#define csr csr_addr.byte
#define cs0 csr_addr.bit.b0 /* CS0~ output enable bit */
#define cs1 csr_addr.bit.b1 /* CS1~ output enable bit */
#define cs2 csr_addr.bit.b2 /* CS2~ output enable bit */
#define cs3 csr_addr.bit.b3 /* CS3~ output enable bit */
#define cs0w csr_addr.bit.b4 /* CS0~ wait bit */
#define cs1w csr_addr.bit.b5 /* CS1~ wait bit */
#define cs2w csr_addr.bit.b6 /* CS2~ wait bit */
#define cs3w csr_addr.bit.b7 /* CS3~ wait bit */
/*------------------------------------------------------
Address match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enable writting to system clock control registers 0 and 1 */
#define prc1 prcr_addr.bit.b1 /* Enable writting to processor mode registers 0 and 1 */
#define prc2 prcr_addr.bit.b2 /* Enable writting to port P9 direction register and SI/Oi control register(i=3,4) */
/*------------------------------------------------------
Data bank register
------------------------------------------------------*/
union byte_def dbr_addr;
#define dbr dbr_addr.byte
#define ofs dbr_addr.bit.b2 /* Offset bit */
#define bsr0 dbr_addr.bit.b3 /* Bank select bit 0 */
#define bsr1 dbr_addr.bit.b4 /* Bank select bit 1 */
#define bsr2 dbr_addr.bit.b5 /* Bank select bit 2 */
/*------------------------------------------------------
Oscillation stop detection register
------------------------------------------------------*/
union byte_def cm2_addr;
#define cm2 cm2_addr.byte
#define cm20 cm2_addr.bit.b0 /* Oscillation stop detection bit */
#define cm21 cm2_addr.bit.b1 /* Main clock switch bit */
#define cm22 cm2_addr.bit.b2 /* Oscillation stop detection status */
#define cm23 cm2_addr.bit.b3 /* Clock monitor bit */
#define cm27 cm2_addr.bit.b7 /* Operation select bit(when an oscillation stop is detected) */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Chip select expansion control register
------------------------------------------------------*/
union byte_def cse_addr;
#define cse cse_addr.byte
#define cse00w cse_addr.bit.b0 /* CS0~ wait expansion bit */
#define cse01w cse_addr.bit.b1 /* CS0~ wait expansion bit */
#define cse10w cse_addr.bit.b2 /* CS1~ wait expansion bit */
#define cse11w cse_addr.bit.b3 /* CS1~ wait expansion bit */
#define cse20w cse_addr.bit.b4 /* CS2~ wait expansion bit */
#define cse21w cse_addr.bit.b5 /* CS2~ wait expansion bit */
#define cse30w cse_addr.bit.b6 /* CS3~ wait expansion bit */
#define cse31w cse_addr.bit.b7 /* CS3~ wait expansion bit */
/*------------------------------------------------------
PLL control register 0
------------------------------------------------------*/
union byte_def plc0_addr;
#define plc0 plc0_addr.byte
#define plc00 plc0_addr.bit.b0 /* Programmable counter select bit */
#define plc01 plc0_addr.bit.b1 /* Programmable counter select bit */
#define plc02 plc0_addr.bit.b2 /* Programmable counter select bit */
#define plc06 plc0_addr.bit.b6 /* External low-pass filter connecting bit */
#define plc07 plc0_addr.bit.b7 /* Operation enable bit */
/*------------------------------------------------------
Processor mode register 2
------------------------------------------------------*/
union byte_def pm2_addr;
#define pm2 pm2_addr.byte
#define pm20 pm2_addr.bit.b0 /* Specifying wait when accessing SFR at PLL operation */
/*------------------------------------------------------
DMA0 control register
------------------------------------------------------*/
union byte_def dm0con_addr;
#define dm0con dm0con_addr.byte
#define dmbit_dm0con dm0con_addr.bit.b0 /* Transfer unit bit select bit */
#define dmasl_dm0con dm0con_addr.bit.b1 /* Repeat transfer mode select bit */
#define dmas_dm0con dm0con_addr.bit.b2 /* DMA request bit */
#define dmae_dm0con dm0con_addr.bit.b3 /* DMA enable bit */
#define dsd_dm0con dm0con_addr.bit.b4 /* Source address direction select bit */
#define dad_dm0con dm0con_addr.bit.b5 /* Destination address direction select bit */
/*------------------------------------------------------
DMA1 control register
------------------------------------------------------*/
union byte_def dm1con_addr;
#define dm1con dm1con_addr.byte
#define dmbit_dm1con dm1con_addr.bit.b0 /* Transfer unit bit select bit */
#define dmasl_dm1con dm1con_addr.bit.b1 /* Repeat transfer mode select bit */
#define dmas_dm1con dm1con_addr.bit.b2 /* DMA request bit */
#define dmae_dm1con dm1con_addr.bit.b3 /* DMA enable bit */
#define dsd_dm1con dm1con_addr.bit.b4 /* Source address direction select bit */
#define dad_dm1con dm1con_addr.bit.b5 /* Destination address direction select bit */
/*------------------------------------------------------
INT3 interrupt control register
------------------------------------------------------*/
union byte_def int3ic_addr;
#define int3ic int3ic_addr.byte
#define ilvl0_int3ic int3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int3ic int3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int3ic int3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int3ic int3ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int3ic int3ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
Timer B5 interrupt control register
------------------------------------------------------*/
union byte_def tb5ic_addr;
#define tb5ic tb5ic_addr.byte
#define ilvl0_tb5ic tb5ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb5ic tb5ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb5ic tb5ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb5ic tb5ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B4 interrupt control register
------------------------------------------------------*/
union byte_def tb4ic_addr;
#define tb4ic tb4ic_addr.byte
#define ilvl0_tb4ic tb4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb4ic tb4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb4ic tb4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb4ic tb4ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B3 interrupt control register
------------------------------------------------------*/
union byte_def tb3ic_addr;
#define tb3ic tb3ic_addr.byte
#define ilvl0_tb3ic tb3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb3ic tb3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb3ic tb3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb3ic tb3ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
SI/O4 interrupt control register
------------------------------------------------------*/
union byte_def s4ic_addr;
#define s4ic s4ic_addr.byte
#define ilvl0_s4ic s4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s4ic s4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s4ic s4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s4ic s4ic_addr.bit.b3 /* Interrupt request bit */
#define pol_s4ic s4ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
SI/O3 interrupt control register
------------------------------------------------------*/
union byte_def s3ic_addr;
#define s3ic s3ic_addr.byte
#define ilvl0_s3ic s3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s3ic s3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s3ic s3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s3ic s3ic_addr.bit.b3 /* Interrupt request bit */
#define pol_s3ic s3ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT5 interrupt control register
------------------------------------------------------*/
union byte_def int5ic_addr;
#define int5ic int5ic_addr.byte
#define ilvl0_int5ic int5ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int5ic int5ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int5ic int5ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int5ic int5ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int5ic int5ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT4 interrupt control register
------------------------------------------------------*/
union byte_def int4ic_addr;
#define int4ic int4ic_addr.byte
#define ilvl0_int4ic int4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int4ic int4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int4ic int4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int4ic int4ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int4ic int4ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
Bus collision detection interrupt control register
------------------------------------------------------*/
union byte_def bcnic_addr;
#define bcnic bcnic_addr.byte
#define ilvl0_bcnic bcnic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_bcnic bcnic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_bcnic bcnic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_bcnic bcnic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
DMA0 interrupt control register
------------------------------------------------------*/
union byte_def dm0ic_addr;
#define dm0ic dm0ic_addr.byte
#define ilvl0_dm0ic dm0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_dm0ic dm0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_dm0ic dm0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_dm0ic dm0ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
DMA1 interrupt control register
------------------------------------------------------*/
union byte_def dm1ic_addr;
#define dm1ic dm1ic_addr.byte
#define ilvl0_dm1ic dm1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_dm1ic dm1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_dm1ic dm1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_dm1ic dm1ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Key input interrupt control register
------------------------------------------------------*/
union byte_def kupic_addr;
#define kupic kupic_addr.byte
#define ilvl0_kupic kupic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_kupic kupic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_kupic kupic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_kupic kupic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
A-D conversion interrupt control register
------------------------------------------------------*/
union byte_def adic_addr;
#define adic adic_addr.byte
#define ilvl0_adic adic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_adic adic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_adic adic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_adic adic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART2 transmit interrupt control register
------------------------------------------------------*/
union byte_def s2tic_addr;
#define s2tic s2tic_addr.byte
#define ilvl0_s2tic s2tic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s2tic s2tic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s2tic s2tic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s2tic s2tic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART2 receive interrupt control register
------------------------------------------------------*/
union byte_def s2ric_addr;
#define s2ric s2ric_addr.byte
#define ilvl0_s2ric s2ric_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s2ric s2ric_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s2ric s2ric_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s2ric s2ric_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART0 transmit interrupt control register
------------------------------------------------------*/
union byte_def s0tic_addr;
#define s0tic s0tic_addr.byte
#define ilvl0_s0tic s0tic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s0tic s0tic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s0tic s0tic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s0tic s0tic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART0 receive interrupt control register
------------------------------------------------------*/
union byte_def s0ric_addr;
#define s0ric s0ric_addr.byte
#define ilvl0_s0ric s0ric_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s0ric s0ric_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s0ric s0ric_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s0ric s0ric_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART1 transmit interrupt control register
------------------------------------------------------*/
union byte_def s1tic_addr;
#define s1tic s1tic_addr.byte
#define ilvl0_s1tic s1tic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s1tic s1tic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s1tic s1tic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s1tic s1tic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART1 receive interrupt control register
------------------------------------------------------*/
union byte_def s1ric_addr;
#define s1ric s1ric_addr.byte
#define ilvl0_s1ric s1ric_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s1ric s1ric_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s1ric s1ric_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s1ric s1ric_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A0 receive interrupt control register
------------------------------------------------------*/
union byte_def ta0ic_addr;
#define ta0ic ta0ic_addr.byte
#define ilvl0_ta0ic ta0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta0ic ta0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta0ic ta0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta0ic ta0ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A1 receive interrupt control register
------------------------------------------------------*/
union byte_def ta1ic_addr;
#define ta1ic ta1ic_addr.byte
#define ilvl0_ta1ic ta1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta1ic ta1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta1ic ta1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta1ic ta1ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A2 receive interrupt control register
------------------------------------------------------*/
union byte_def ta2ic_addr;
#define ta2ic ta2ic_addr.byte
#define ilvl0_ta2ic ta2ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta2ic ta2ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta2ic ta2ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta2ic ta2ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A3 receive interrupt control register
------------------------------------------------------*/
union byte_def ta3ic_addr;
#define ta3ic ta3ic_addr.byte
#define ilvl0_ta3ic ta3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta3ic ta3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta3ic ta3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta3ic ta3ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer A4 receive interrupt control register
------------------------------------------------------*/
union byte_def ta4ic_addr;
#define ta4ic ta4ic_addr.byte
#define ilvl0_ta4ic ta4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_ta4ic ta4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_ta4ic ta4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_ta4ic ta4ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B0 receive interrupt control register
------------------------------------------------------*/
union byte_def tb0ic_addr;
#define tb0ic tb0ic_addr.byte
#define ilvl0_tb0ic tb0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb0ic tb0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb0ic tb0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb0ic tb0ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B1 receive interrupt control register
------------------------------------------------------*/
union byte_def tb1ic_addr;
#define tb1ic tb1ic_addr.byte
#define ilvl0_tb1ic tb1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb1ic tb1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb1ic tb1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb1ic tb1ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B2 receive interrupt control register
------------------------------------------------------*/
union byte_def tb2ic_addr;
#define tb2ic tb2ic_addr.byte
#define ilvl0_tb2ic tb2ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb2ic tb2ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb2ic tb2ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb2ic tb2ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
INT0 receive interrupt control register
------------------------------------------------------*/
union byte_def int0ic_addr;
#define int0ic int0ic_addr.byte
#define ilvl0_int0ic int0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int0ic int0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int0ic int0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int0ic int0ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int0ic int0ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT1 receive interrupt control register
------------------------------------------------------*/
union byte_def int1ic_addr;
#define int1ic int1ic_addr.byte
#define ilvl0_int1ic int1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int1ic int1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int1ic int1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int1ic int1ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int1ic int1ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT2 receive interrupt control register
------------------------------------------------------*/