From 5ec8bb892bb53e87ad3d2ebe4eb06a1d58162d4e Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Mon, 21 Oct 2024 13:54:53 +0200 Subject: [PATCH] Make `cmp` and `cmp+branch` instruction docs more consistent (#1242) * improve consistency of docs of `cmp` instructions * improve cmp instrs docs and make them more consistent --- crates/ir/src/for_each_op.rs | 436 ++++++++++------------------------- 1 file changed, 116 insertions(+), 320 deletions(-) diff --git a/crates/ir/src/for_each_op.rs b/crates/ir/src/for_each_op.rs index 514443a4a7..346e2109be 100644 --- a/crates/ir/src/for_each_op.rs +++ b/crates/ir/src/for_each_op.rs @@ -269,7 +269,7 @@ macro_rules! for_each_op { /// [`ComparatorAndOffset`]: crate::ComparatorAndOffset params: Reg, }, - /// A fused [`Instruction::I32And`] and Wasm branch instruction. + /// A fused `i32.and` and branch instruction. #[snake_name(branch_i32_and)] BranchI32And { /// The left-hand side operand to the branch conditional. @@ -279,11 +279,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32And`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32And`] with 16-bit encoded constant `rhs`. + /// A fused `i32.and` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_and_imm16)] BranchI32AndImm16 { /// The left-hand side operand to the conditional operator. @@ -293,7 +289,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32Or`] and Wasm branch instruction. + /// A fused `i32.or` and branch instruction. #[snake_name(branch_i32_or)] BranchI32Or { /// The left-hand side operand to the branch conditional. @@ -303,11 +299,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32Or`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32Or`] with 16-bit encoded constant `rhs`. + /// A fused `i32.or` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_or_imm16)] BranchI32OrImm16 { /// The left-hand side operand to the conditional operator. @@ -317,7 +309,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32Xor`] and Wasm branch instruction. + /// A fused `i32.xor` and branch instruction. #[snake_name(branch_i32_xor)] BranchI32Xor { /// The left-hand side operand to the branch conditional. @@ -327,11 +319,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32Xor`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32Xor`] with 16-bit encoded constant `rhs`. + /// A fused `i32.xor` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_xor_imm16)] BranchI32XorImm16 { /// The left-hand side operand to the conditional operator. @@ -342,7 +330,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused not-[`Instruction::I32And`] and Wasm branch instruction. + /// A fused `i32.eqz(i32.and)` and branch instruction. #[snake_name(branch_i32_and_eqz)] BranchI32AndEqz { /// The left-hand side operand to the branch conditional. @@ -352,11 +340,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused not-[`Instruction::I32And`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32AndEqz`] with 16-bit encoded constant `rhs`. + /// A fused `i32.eqz(i32.and)` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_and_eqz_imm16)] BranchI32AndEqzImm16 { /// The left-hand side operand to the conditional operator. @@ -366,7 +350,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused not-[`Instruction::I32Or`] and Wasm branch instruction. + /// A fused `i32.eqz(i32.or)` and branch instruction. #[snake_name(branch_i32_or_eqz)] BranchI32OrEqz { /// The left-hand side operand to the branch conditional. @@ -376,11 +360,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused not-[`Instruction::I32Or`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32OrEqz`] with 16-bit encoded constant `rhs`. + /// A fused `i32.eqz(i32.or)` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_or_eqz_imm16)] BranchI32OrEqzImm16 { /// The left-hand side operand to the conditional operator. @@ -390,7 +370,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused not-[`Instruction::I32Xor`] and Wasm branch instruction. + /// A fused `i32.eqz(i32.xor)` and branch instruction. #[snake_name(branch_i32_xor_eqz)] BranchI32XorEqz { /// The left-hand side operand to the branch conditional. @@ -400,11 +380,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused not-[`Instruction::I32Xor`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32XorEqz`] with 16-bit encoded constant `rhs`. + /// A fused `i32.eqz(i32.xor)` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_xor_eqz_imm16)] BranchI32XorEqzImm16 { /// The left-hand side operand to the conditional operator. @@ -415,7 +391,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::I32Eq`] and Wasm branch instruction. + /// A fused `i32.eq` and branch instruction. #[snake_name(branch_i32_eq)] BranchI32Eq { /// The left-hand side operand to the branch conditional. @@ -425,11 +401,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32Eq`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32Eq`] with 16-bit encoded constant `rhs`. + /// A fused `i32.eq` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_eq_imm16)] BranchI32EqImm16 { /// The left-hand side operand to the conditional operator. @@ -439,7 +411,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32Ne`] and Wasm branch instruction. + /// A fused `i32.ne` and branch instruction. #[snake_name(branch_i32_ne)] BranchI32Ne { /// The left-hand side operand to the branch conditional. @@ -449,11 +421,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32Ne`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32Ne`] with 16-bit encoded constant `rhs`. + /// A fused `i32.ne` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_ne_imm16)] BranchI32NeImm16 { /// The left-hand side operand to the conditional operator. @@ -464,7 +432,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::I32LtS`] and Wasm branch instruction. + /// A fused `i32.lt_s` and branch instruction. #[snake_name(branch_i32_lt_s)] BranchI32LtS { /// The left-hand side operand to the branch conditional. @@ -474,11 +442,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32LtS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32LtS`] with 16-bit encoded constant `rhs`. + /// A fused `i32.lt_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_lt_s_imm16_rhs)] BranchI32LtSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -488,7 +452,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32LtU`] and Wasm branch instruction. + /// A fused `i32.lt_u` and branch instruction. #[snake_name(branch_i32_lt_u)] BranchI32LtU { /// The left-hand side operand to the branch conditional. @@ -498,11 +462,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32LtU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32LtU`] with 16-bit encoded constant `rhs`. + /// A fused `i32.lt_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_lt_u_imm16_rhs)] BranchI32LtUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -512,7 +472,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32LeS`] and Wasm branch instruction. + /// A fused `i32.le_s` and branch instruction. #[snake_name(branch_i32_le_s)] BranchI32LeS { /// The left-hand side operand to the branch conditional. @@ -522,11 +482,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32LeS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32LeS`] with 16-bit encoded constant `rhs`. + /// A fused `i32.le_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_le_s_imm16_rhs)] BranchI32LeSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -536,7 +492,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32LeU`] and Wasm branch instruction. + /// A fused `i32.le_u` and branch instruction. #[snake_name(branch_i32_le_u)] BranchI32LeU { /// The left-hand side operand to the branch conditional. @@ -546,11 +502,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32LeU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32LeU`] with 16-bit encoded constant `rhs`. + /// A fused `i32.le_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_le_u_imm16_rhs)] BranchI32LeUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -560,7 +512,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GtS`] and Wasm branch instruction. + /// A fused `i32.gt_s` and branch instruction. #[snake_name(branch_i32_gt_s)] BranchI32GtS { /// The left-hand side operand to the branch conditional. @@ -570,11 +522,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GtS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32GtS`] with 16-bit encoded constant `rhs`. + /// A fused `i32.gt_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_gt_s_imm16_rhs)] BranchI32GtSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -584,7 +532,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GtU`] and Wasm branch instruction. + /// A fused `i32.gt_u` and branch instruction. #[snake_name(branch_i32_gt_u)] BranchI32GtU { /// The left-hand side operand to the branch conditional. @@ -594,11 +542,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GtU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32GtU`] with 16-bit encoded constant `rhs`. + /// A fused `i32.gt_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_gt_u_imm16_rhs)] BranchI32GtUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -608,7 +552,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GeS`] and Wasm branch instruction. + /// A fused `i32.ge_s` and branch instruction. #[snake_name(branch_i32_ge_s)] BranchI32GeS { /// The left-hand side operand to the branch conditional. @@ -618,11 +562,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GeS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32GeS`] with 16-bit encoded constant `rhs`. + /// A fused `i32.ge_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_ge_s_imm16_rhs)] BranchI32GeSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -632,7 +572,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GeU`] and Wasm branch instruction. + /// A fused `i32.ge_u` and branch instruction. #[snake_name(branch_i32_ge_u)] BranchI32GeU { /// The left-hand side operand to the branch conditional. @@ -642,11 +582,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I32GeU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI32GeU`] with 16-bit encoded constant `rhs`. + /// A fused `i32.ge_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i32_ge_u_imm16_rhs)] BranchI32GeUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -657,7 +593,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::I64Eq`] and Wasm branch instruction. + /// A fused `i64.eq` and branch instruction. #[snake_name(branch_i64_eq)] BranchI64Eq { /// The left-hand side operand to the branch conditional. @@ -667,11 +603,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64Eq`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64Eq`] with 16-bit encoded constant `rhs`. + /// A fused `i64.eq` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_eq_imm16)] BranchI64EqImm16 { /// The left-hand side operand to the conditional operator. @@ -681,7 +613,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64Ne`] and Wasm branch instruction. + /// A fused `i64.ne` and branch instruction. #[snake_name(branch_i64_ne)] BranchI64Ne { /// The left-hand side operand to the branch conditional. @@ -691,11 +623,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64Ne`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64Ne`] with 16-bit encoded constant `rhs`. + /// A fused `i64.ne` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_ne_imm16)] BranchI64NeImm16 { /// The left-hand side operand to the conditional operator. @@ -706,7 +634,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::I64LtS`] and Wasm branch instruction. + /// A fused `i64.lt_s` and branch instruction. #[snake_name(branch_i64_lt_s)] BranchI64LtS { /// The left-hand side operand to the branch conditional. @@ -716,11 +644,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64LtS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64LtS`] with 16-bit encoded constant `rhs`. + /// A fused `i64.lt_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_lt_s_imm16_rhs)] BranchI64LtSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -730,7 +654,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64LtU`] and Wasm branch instruction. + /// A fused `i64.lt_u` and branch instruction. #[snake_name(branch_i64_lt_u)] BranchI64LtU { /// The left-hand side operand to the branch conditional. @@ -740,11 +664,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64LtU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64LtU`] with 16-bit encoded constant `rhs`. + /// A fused `i64.lt_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_lt_u_imm16_rhs)] BranchI64LtUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -754,7 +674,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64LeS`] and Wasm branch instruction. + /// A fused `i64.le_s` and branch instruction. #[snake_name(branch_i64_le_s)] BranchI64LeS { /// The left-hand side operand to the branch conditional. @@ -764,11 +684,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64LeS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64LeS`] with 16-bit encoded constant `rhs`. + /// A fused `i64.le_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_le_s_imm16_rhs)] BranchI64LeSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -778,7 +694,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64LeU`] and Wasm branch instruction. + /// A fused `i64.le_u` and branch instruction. #[snake_name(branch_i64_le_u)] BranchI64LeU { /// The left-hand side operand to the branch conditional. @@ -788,11 +704,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64LeU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64LeU`] with 16-bit encoded constant `rhs`. + /// A fused `i64.le_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_le_u_imm16_rhs)] BranchI64LeUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -802,7 +714,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GtS`] and Wasm branch instruction. + /// A fused `i64.gt_s` and branch instruction. #[snake_name(branch_i64_gt_s)] BranchI64GtS { /// The left-hand side operand to the branch conditional. @@ -812,11 +724,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GtS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64GtS`] with 16-bit encoded constant `rhs`. + /// A fused `i64.gt_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_gt_s_imm16_rhs)] BranchI64GtSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -826,7 +734,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GtU`] and Wasm branch instruction. + /// A fused `i64.gt_u` and branch instruction. #[snake_name(branch_i64_gt_u)] BranchI64GtU { /// The left-hand side operand to the branch conditional. @@ -836,11 +744,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GtU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64GtU`] with 16-bit encoded constant `rhs`. + /// A fused `i64.gt_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_gt_u_imm16_rhs)] BranchI64GtUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -850,7 +754,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GeS`] and Wasm branch instruction. + /// A fused `i64.ge_s` and branch instruction. #[snake_name(branch_i64_ge_s)] BranchI64GeS { /// The left-hand side operand to the branch conditional. @@ -860,11 +764,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GeS`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64GeS`] with 16-bit encoded constant `rhs`. + /// A fused `i64.ge_s` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_ge_s_imm16_rhs)] BranchI64GeSImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -874,7 +774,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GeU`] and Wasm branch instruction. + /// A fused `i64.ge_u` and branch instruction. #[snake_name(branch_i64_ge_u)] BranchI64GeU { /// The left-hand side operand to the branch conditional. @@ -884,11 +784,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::I64GeU`] and Wasm branch instruction. - /// - /// # Note - /// - /// Variant of [`Instruction::BranchI64GeU`] with 16-bit encoded constant `rhs`. + /// A fused `i64.ge_u` and branch instruction with 16-bit immediate `rhs` value. #[snake_name(branch_i64_ge_u_imm16_rhs)] BranchI64GeUImm16Rhs { /// The left-hand side operand to the conditional operator. @@ -899,7 +795,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::F32Eq`] and Wasm branch instruction. + /// A fused `f32.eq` and branch instruction. #[snake_name(branch_f32_eq)] BranchF32Eq { /// The left-hand side operand to the branch conditional. @@ -909,7 +805,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F32Ne`] and Wasm branch instruction. + /// A fused `f32.ne` and branch instruction. #[snake_name(branch_f32_ne)] BranchF32Ne { /// The left-hand side operand to the branch conditional. @@ -920,7 +816,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::F32Lt`] and Wasm branch instruction. + /// A fused `f32.lt` and branch instruction. #[snake_name(branch_f32_lt)] BranchF32Lt { /// The left-hand side operand to the branch conditional. @@ -930,7 +826,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F32Le`] and Wasm branch instruction. + /// A fused `f32.le` and branch instruction. #[snake_name(branch_f32_le)] BranchF32Le { /// The left-hand side operand to the branch conditional. @@ -940,7 +836,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F32Gt`] and Wasm branch instruction. + /// A fused `f32.gt` and branch instruction. #[snake_name(branch_f32_gt)] BranchF32Gt { /// The left-hand side operand to the branch conditional. @@ -950,7 +846,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F32Ge`] and Wasm branch instruction. + /// A fused `f32.ge` and branch instruction. #[snake_name(branch_f32_ge)] BranchF32Ge { /// The left-hand side operand to the branch conditional. @@ -961,7 +857,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::F64Eq`] and Wasm branch instruction. + /// A fused `f64.eq` and branch instruction. #[snake_name(branch_f64_eq)] BranchF64Eq { /// The left-hand side operand to the branch conditional. @@ -971,7 +867,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F64Ne`] and Wasm branch instruction. + /// A fused `f64.ne` and branch instruction. #[snake_name(branch_f64_ne)] BranchF64Ne { /// The left-hand side operand to the branch conditional. @@ -982,7 +878,7 @@ macro_rules! for_each_op { offset: BranchOffset16, }, - /// A fused [`Instruction::F64Lt`] and Wasm branch instruction. + /// A fused `f64.lt` and branch instruction. #[snake_name(branch_f64_lt)] BranchF64Lt { /// The left-hand side operand to the branch conditional. @@ -992,7 +888,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F64Le`] and Wasm branch instruction. + /// A fused `f64.le` and branch instruction. #[snake_name(branch_f64_le)] BranchF64Le { /// The left-hand side operand to the branch conditional. @@ -1002,7 +898,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F64Gt`] and Wasm branch instruction. + /// A fused `f64.gt` and branch instruction. #[snake_name(branch_f64_gt)] BranchF64Gt { /// The left-hand side operand to the branch conditional. @@ -1012,7 +908,7 @@ macro_rules! for_each_op { /// The 16-bit encoded branch offset. offset: BranchOffset16, }, - /// A fused [`Instruction::F64Ge`] and Wasm branch instruction. + /// A fused `f64.ge` and branch instruction. #[snake_name(branch_f64_ge)] BranchF64Ge { /// The left-hand side operand to the branch conditional. @@ -3048,7 +2944,7 @@ macro_rules! for_each_op { address: u32, }, - /// `i32` equality comparison instruction: `r0 = r1 == r2` + /// Wasm `i32.eq` equivalent Wasmi instruction. #[snake_name(i32_eq)] I32Eq{ @result: Reg, @@ -3057,12 +2953,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` equality comparison instruction with immediate: `r0 = r1 == c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32Eq`] - /// for 16-bit right-hand side constant values. + /// Wasm `i32.eq` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_eq_imm16)] I32EqImm16{ @result: Reg, @@ -3072,7 +2963,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i32` inequality comparison instruction: `r0 = r1 != r2` + /// Wasm `i32.ne` equivalent Wasmi instruction. #[snake_name(i32_ne)] I32Ne{ @result: Reg, @@ -3081,12 +2972,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` inequality comparison instruction with immediate: `r0 = r1 != c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32Ne`] - /// for 16-bit right-hand side constant values. + /// Wasm `i32.ne` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_ne_imm16)] I32NeImm16{ @result: Reg, @@ -3096,7 +2982,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i32` signed less-than comparison instruction: `r0 = r1 < r2` + /// Wasm `i32.lt_s` equivalent Wasmi instruction. #[snake_name(i32_lt_s)] I32LtS{ @result: Reg, @@ -3105,12 +2991,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` signed less-than comparison instruction with immediate: `r0 = r1 < c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32LtS`] - /// for small right-hand side constant values. + /// Wasm `i32.lt_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_lt_s_imm16_rhs)] I32LtSImm16Rhs{ @result: Reg, @@ -3119,7 +3000,7 @@ macro_rules! for_each_op { /// The 16-bit immediate value. rhs: Const16, }, - /// `i32` unsigned less-than comparison instruction: `r0 = r1 < r2` + /// Wasm `i32.lt_u` equivalent Wasmi instruction. #[snake_name(i32_lt_u)] I32LtU{ @result: Reg, @@ -3128,12 +3009,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` unsigned less-than comparison instruction with immediate: `r0 = r1 < c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32LtU`] - /// for small right-hand side constant values. + /// Wasm `i32.lt_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_lt_u_imm16_rhs)] I32LtUImm16Rhs{ @result: Reg, @@ -3143,7 +3019,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i32` signed greater-than comparison instruction: `r0 = r1 > r2` + /// Wasm `i32.gt_s` equivalent Wasmi instruction. #[snake_name(i32_gt_s)] I32GtS{ @result: Reg, @@ -3152,12 +3028,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` signed greater-than comparison instruction with immediate: `r0 = r1 > c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32GtS`] - /// for small right-hand side constant values. + /// Wasm `i32.gt_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_gt_s_imm16_rhs)] I32GtSImm16Rhs{ @result: Reg, @@ -3166,7 +3037,7 @@ macro_rules! for_each_op { /// The 16-bit immediate value. rhs: Const16, }, - /// `i32` unsigned greater-than comparison instruction: `r0 = r1 > r2` + /// Wasm `i32.gt_u` equivalent Wasmi instruction. #[snake_name(i32_gt_u)] I32GtU{ @result: Reg, @@ -3175,12 +3046,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` unsigned greater-than comparison instruction with immediate: `r0 = r1 > c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32GtU`] - /// for small right-hand side constant values. + /// Wasm `i32.gt_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_gt_u_imm16_rhs)] I32GtUImm16Rhs{ @result: Reg, @@ -3190,7 +3056,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i32` signed less-than or equals comparison instruction: `r0 = r1 <= r2` + /// Wasm `i32.le_s` equivalent Wasmi instruction. #[snake_name(i32_le_s)] I32LeS{ @result: Reg, @@ -3199,12 +3065,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` signed less-than or equals comparison instruction with immediate: `r0 = r1 <= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32LeS`] - /// for small right-hand side constant values. + /// Wasm `i32.le_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_le_s_imm16_rhs)] I32LeSImm16Rhs{ @result: Reg, @@ -3213,7 +3074,7 @@ macro_rules! for_each_op { /// The 16-bit immediate value. rhs: Const16, }, - /// `i32` unsigned less-than or equals comparison instruction: `r0 = r1 <= r2` + /// Wasm `i32.le_u` equivalent Wasmi instruction. #[snake_name(i32_le_u)] I32LeU{ @result: Reg, @@ -3222,12 +3083,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` unsigned less-than or equals comparison instruction with immediate: `r0 = r1 <= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32LeU`] - /// for small right-hand side constant values. + /// Wasm `i32.le_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_le_u_imm16_rhs)] I32LeUImm16Rhs{ @result: Reg, @@ -3237,7 +3093,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i32` signed greater-than or equals comparison instruction: `r0 = r1 >= r2` + /// Wasm `i32.ge_s` equivalent Wasmi instruction. #[snake_name(i32_ge_s)] I32GeS{ @result: Reg, @@ -3246,12 +3102,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` signed greater-than or equals comparison instruction with immediate: `r0 = r1 >= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32GeS`] - /// for small right-hand side constant values. + /// Wasm `i32.ge_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_ge_s_imm16_rhs)] I32GeSImm16Rhs{ @result: Reg, @@ -3260,7 +3111,7 @@ macro_rules! for_each_op { /// The 16-bit immediate value. rhs: Const16, }, - /// `i32` unsigned greater-than or equals comparison instruction: `r0 = r1 >= r2` + /// Wasm `i32.ge_u` equivalent Wasmi instruction. #[snake_name(i32_ge_u)] I32GeU{ @result: Reg, @@ -3269,12 +3120,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i32` unsigned greater-than or equals comparison instruction with immediate: `r0 = r1 >= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I32GeU`] - /// for small right-hand side constant values. + /// Wasm `i32.ge_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i32_ge_u_imm16_rhs)] I32GeUImm16Rhs{ @result: Reg, @@ -3284,7 +3130,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` equality comparison instruction: `r0 = r1 == r2` + /// Wasm `i64.eq` equivalent Wasmi instruction. #[snake_name(i64_eq)] I64Eq{ @result: Reg, @@ -3293,12 +3139,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` equality comparison instruction with immediate: `r0 = r1 == c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64Eq`] - /// for 16-bit right-hand side constant values. + /// Wasm `i64.eq` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_eq_imm16)] I64EqImm16{ @result: Reg, @@ -3308,7 +3149,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` inequality comparison instruction: `r0 = r1 != r2` + /// Wasm `i64.ne` equivalent Wasmi instruction. #[snake_name(i64_ne)] I64Ne{ @result: Reg, @@ -3317,12 +3158,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` inequality comparison instruction with immediate: `r0 = r1 != c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64Ne`] - /// for 16-bit right-hand side constant values. + /// Wasm `i64.ne` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_ne_imm16)] I64NeImm16{ @result: Reg, @@ -3332,7 +3168,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` signed less-than comparison instruction: `r0 = r1 < r2` + /// Wasm `i64.lt_s` equivalent Wasmi instruction. #[snake_name(i64_lt_s)] I64LtS{ @result: Reg, @@ -3341,12 +3177,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` signed less-than comparison instruction with immediate: `r0 = r1 < c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64LtS`] - /// for small right-hand side constant values. + /// Wasm `i64.lt_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_lt_s_imm16_rhs)] I64LtSImm16Rhs{ @result: Reg, @@ -3356,7 +3187,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` unsigned less-than comparison instruction: `r0 = r1 < r2` + /// Wasm `i64.lt_s` equivalent Wasmi instruction. #[snake_name(i64_lt_u)] I64LtU{ @result: Reg, @@ -3365,12 +3196,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` unsigned less-than comparison instruction with immediate: `r0 = r1 < c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64LtU`] - /// for small right-hand side constant values. + /// Wasm `i64.lt_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_lt_u_imm16_rhs)] I64LtUImm16Rhs{ @result: Reg, @@ -3380,7 +3206,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` signed greater-than comparison instruction: `r0 = r1 > r2` + /// Wasm `i64.gt_s` equivalent Wasmi instruction. #[snake_name(i64_gt_s)] I64GtS{ @result: Reg, @@ -3389,12 +3215,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` signed greater-than comparison instruction with immediate: `r0 = r1 > c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64GtS`] - /// for small right-hand side constant values. + /// Wasm `i64.gt_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_gt_s_imm16_rhs)] I64GtSImm16Rhs{ @result: Reg, @@ -3404,7 +3225,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` unsigned greater-than comparison instruction: `r0 = r1 > r2` + /// Wasm `i64.gt_u` equivalent Wasmi instruction. #[snake_name(i64_gt_u)] I64GtU{ @result: Reg, @@ -3413,12 +3234,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` unsigned greater-than comparison instruction with immediate: `r0 = r1 > c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64GtU`] - /// for small right-hand side constant values. + /// Wasm `i64.gt_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_gt_u_imm16_rhs)] I64GtUImm16Rhs{ @result: Reg, @@ -3428,7 +3244,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` signed less-than or equals comparison instruction: `r0 = r1 <= r2` + /// Wasm `i64.le_s` equivalent Wasmi instruction. #[snake_name(i64_le_s)] I64LeS{ @result: Reg, @@ -3437,12 +3253,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` signed less-than or equals comparison instruction with immediate: `r0 = r1 <= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64LeS`] - /// for small right-hand side constant values. + /// Wasm `i64.le_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_le_s_imm16_rhs)] I64LeSImm16Rhs{ @result: Reg, @@ -3452,7 +3263,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` unsigned less-than or equals comparison instruction: `r0 = r1 <= r2` + /// Wasm `i64.le_u` equivalent Wasmi instruction. #[snake_name(i64_le_u)] I64LeU{ @result: Reg, @@ -3461,12 +3272,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` unsigned less-than or equals comparison instruction with immediate: `r0 = r1 <= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64LeU`] - /// for small right-hand side constant values. + /// Wasm `i64.le_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_le_u_imm16_rhs)] I64LeUImm16Rhs{ @result: Reg, @@ -3476,7 +3282,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` signed greater-than or equals comparison instruction: `r0 = r1 >= r2` + /// Wasm `i64.ge_s` equivalent Wasmi instruction. #[snake_name(i64_ge_s)] I64GeS{ @result: Reg, @@ -3485,12 +3291,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` signed greater-than or equals comparison instruction with immediate: `r0 = r1 >= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64GeS`] - /// for small right-hand side constant values. + /// Wasm `i64.ge_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_ge_s_imm16_rhs)] I64GeSImm16Rhs{ @result: Reg, @@ -3500,7 +3301,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `i64` unsigned greater-than or equals comparison instruction: `r0 = r1 >= r2` + /// Wasm `i64.ge_u` equivalent Wasmi instruction. #[snake_name(i64_ge_u)] I64GeU{ @result: Reg, @@ -3509,12 +3310,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `i64` unsigned greater-than or equals comparison instruction with immediate: `r0 = r1 >= c0` - /// - /// # Note - /// - /// This is an optimization of [`Instruction::I64GeU`] - /// for small right-hand side constant values. + /// Wasm `i64.ge_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. #[snake_name(i64_ge_u_imm16_rhs)] I64GeUImm16Rhs{ @result: Reg, @@ -3524,7 +3320,7 @@ macro_rules! for_each_op { rhs: Const16, }, - /// `f32` equality comparison instruction: `r0 = r1 == r2` + /// Wasm `f32.eq` equivalent Wasmi instruction. #[snake_name(f32_eq)] F32Eq{ @result: Reg, @@ -3533,7 +3329,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f32` inequality comparison instruction: `r0 = r1 != r2` + /// Wasm `f32.ne` equivalent Wasmi instruction. #[snake_name(f32_ne)] F32Ne{ @result: Reg, @@ -3542,7 +3338,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f32` less-than comparison instruction: `r0 = r1 < r2` + /// Wasm `f32.lt` equivalent Wasmi instruction. #[snake_name(f32_lt)] F32Lt{ @result: Reg, @@ -3551,7 +3347,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f32` less-than or equals comparison instruction: `r0 = r1 <= r2` + /// Wasm `f32.le` equivalent Wasmi instruction. #[snake_name(f32_le)] F32Le{ @result: Reg, @@ -3560,7 +3356,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f32` greater-than comparison instruction: `r0 = r1 > r2` + /// Wasm `f32.gt` equivalent Wasmi instruction. #[snake_name(f32_gt)] F32Gt{ @result: Reg, @@ -3569,7 +3365,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f32` greater-than or equals comparison instruction: `r0 = r1 >= r2` + /// Wasm `f32.ge` equivalent Wasmi instruction. #[snake_name(f32_ge)] F32Ge{ @result: Reg, @@ -3579,7 +3375,7 @@ macro_rules! for_each_op { rhs: Reg, }, - /// `f64` equality comparison instruction: `r0 = r1 == r2` + /// Wasm `f64.eq` equivalent Wasmi instruction. #[snake_name(f64_eq)] F64Eq{ @result: Reg, @@ -3588,7 +3384,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f64` inequality comparison instruction: `r0 = r1 != r2` + /// Wasm `f64.ne` equivalent Wasmi instruction. #[snake_name(f64_ne)] F64Ne{ @result: Reg, @@ -3597,7 +3393,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f64` less-than comparison instruction: `r0 = r1 < r2` + /// Wasm `f64.lt` equivalent Wasmi instruction. #[snake_name(f64_lt)] F64Lt{ @result: Reg, @@ -3606,7 +3402,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f64` less-than or equals comparison instruction: `r0 = r1 <= r2` + /// Wasm `f64.le` equivalent Wasmi instruction. #[snake_name(f64_le)] F64Le{ @result: Reg, @@ -3615,7 +3411,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f64` greater-than comparison instruction: `r0 = r1 > r2` + /// Wasm `f64.gt` equivalent Wasmi instruction. #[snake_name(f64_gt)] F64Gt{ @result: Reg, @@ -3624,7 +3420,7 @@ macro_rules! for_each_op { /// The register holding the right-hand side value. rhs: Reg, }, - /// `f64` greater-than or equals comparison instruction: `r0 = r1 >= r2` + /// Wasm `f64.ge` equivalent Wasmi instruction. #[snake_name(f64_ge)] F64Ge{ @result: Reg,