diff --git a/examples/5-dining-philosophers_GN/5-dining-philosophers.petrinet.GN.workcraft.g b/examples/5-dining-philosophers_GN/5-dining-philosophers.petrinet.GN.workcraft.g new file mode 100644 index 0000000..c8c5771 --- /dev/null +++ b/examples/5-dining-philosophers_GN/5-dining-philosophers.petrinet.GN.workcraft.g @@ -0,0 +1,26 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.0 +.model dining_philosophers_5 +.internal t0 t1 t2 t3 t4 t5 t6 t7 t9 t8 +.graph +t0 p0 p2 +t1 p1 +t2 p2 p4 +t3 p3 +t4 p4 p6 +t5 p5 +t6 p6 p8 +t7 p7 +t9 p9 +t8 p0 p8 +p2 t1 t3 +p1 t0 +p0 t1 t9 +p4 t3 t5 +p3 t2 +p5 t4 +p6 t5 t7 +p8 t7 t9 +p7 t6 +p9 t8 +.marking {p1 p4 p7} +.end diff --git a/examples/5-dining-philosophers_GN/AsyncMSFSMs/fsm_afsm.afsm b/examples/5-dining-philosophers_GN/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..a3ed7df --- /dev/null +++ b/examples/5-dining-philosophers_GN/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,15 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p7*: t6_ p8 +p4*: t5_ p5 +p1*: t0_ p2 +p9: t8_ p0 +p6: t7_ p7 +p3: t2_ p4 +p0: t1_ p1 +p8: t9_ p9 +p5: t4_ p6 +p2: t3_ p3 +### End of FSM #01 Declaration ### + diff --git a/examples/5-dining-philosophers_GN/AsyncMSFSMs/msfsms_afsm.v b/examples/5-dining-philosophers_GN/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..f5fdd4b --- /dev/null +++ b/examples/5-dining-philosophers_GN/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,49 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + t9, + t6, + t3, + t0, + t8, + t5, + t2, + t7, + t4, + t1); + + input reset; + input t9; + input t6; + input t3; + input t0; + input t8; + input t5; + input t2; + input t7; + input t4; + input t1; + + wire p7_FSM1out, p4_FSM1out, p1_FSM1out, p9_FSM1out, p6_FSM1out, p3_FSM1out, p0_FSM1out, p8_FSM1out, p5_FSM1out, p2_FSM1out; // State Synchronisation output signals of FSM1 // + + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t9_(t9), + .t6_(t6), + .t3_(t3), + .t0_(t0), + .t8_(t8), + .t5_(t5), + .t2_(t2), + .t7_(t7), + .t4_(t4), + .t1_(t1) + ); + +endmodule // msfsms_mealy // diff --git a/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..07b5592 --- /dev/null +++ b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,210 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + t9_, + t6_, + t3_, + t0_, + t8_, + t5_, + t2_, + t7_, + t4_, + t1_ +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t9_; + input t6_; + input t3_; + input t0_; + input t8_; + input t5_; + input t2_; + input t7_; + input t4_; + input t1_; + // Transition Barrier Inputs for input Signals // + // === EMPTY! === // + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + // === EMPTY! === // + + + + parameter p7_1HOT_ENCODING = 10'd1; // 10'b0000000001 // + parameter p7_1HOT_CASEX_ENCODING = 10'bxxxxxxxxx1; // 10'b0000000001 // + parameter p4_1HOT_ENCODING = 10'd2; // 10'b0000000010 // + parameter p4_1HOT_CASEX_ENCODING = 10'bxxxxxxxx1x; // 10'b0000000010 // + parameter p1_1HOT_ENCODING = 10'd4; // 10'b0000000100 // + parameter p1_1HOT_CASEX_ENCODING = 10'bxxxxxxx1xx; // 10'b0000000100 // + parameter p9_1HOT_ENCODING = 10'd8; // 10'b0000001000 // + parameter p9_1HOT_CASEX_ENCODING = 10'bxxxxxx1xxx; // 10'b0000001000 // + parameter p6_1HOT_ENCODING = 10'd16; // 10'b0000010000 // + parameter p6_1HOT_CASEX_ENCODING = 10'bxxxxx1xxxx; // 10'b0000010000 // + parameter p3_1HOT_ENCODING = 10'd32; // 10'b0000100000 // + parameter p3_1HOT_CASEX_ENCODING = 10'bxxxx1xxxxx; // 10'b0000100000 // + parameter p0_1HOT_ENCODING = 10'd64; // 10'b0001000000 // + parameter p0_1HOT_CASEX_ENCODING = 10'bxxx1xxxxxx; // 10'b0001000000 // + parameter p8_1HOT_ENCODING = 10'd128; // 10'b0010000000 // + parameter p8_1HOT_CASEX_ENCODING = 10'bxx1xxxxxxx; // 10'b0010000000 // + parameter p5_1HOT_ENCODING = 10'd256; // 10'b0100000000 // + parameter p5_1HOT_CASEX_ENCODING = 10'bx1xxxxxxxx; // 10'b0100000000 // + parameter p2_1HOT_ENCODING = 10'd512; // 10'b1000000000 // + parameter p2_1HOT_CASEX_ENCODING = 10'b1xxxxxxxxx; // 10'b1000000000 // + + reg [9 : 0] state; + reg [9 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p7_1HOT_ENCODING; + // state <= p4_1HOT_ENCODING; + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b1; + state[2] <= 1'b1; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + + always @(state or t9_ or t6_ or t3_ or t0_ or t8_ or t5_ or t2_ or t7_ or t4_ or t1_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 10'bxxxxxxxxx1: // p7_1HOT_ENCODING: // + begin + if (t6_) + begin + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[7] = 1'b1; + end + end + + 10'bxxxxxxxx1x: // p4_1HOT_ENCODING: // + begin + if (t5_) + begin + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[8] = 1'b1; + end + end + + 10'bxxxxxxx1xx: // p1_1HOT_ENCODING: // + begin + if (t0_) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[9] = 1'b1; + end + end + + 10'bxxxxxx1xxx: // p9_1HOT_ENCODING: // + begin + if (t8_) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[6] = 1'b1; + end + end + + 10'bxxxxx1xxxx: // p6_1HOT_ENCODING: // + begin + if (t7_) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[0] = 1'b1; + end + end + + 10'bxxxx1xxxxx: // p3_1HOT_ENCODING: // + begin + if (t2_) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[1] = 1'b1; + end + end + + 10'bxxx1xxxxxx: // p0_1HOT_ENCODING: // + begin + if (t1_) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[2] = 1'b1; + end + end + + 10'bxx1xxxxxxx: // p8_1HOT_ENCODING: // + begin + if (t9_) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[3] = 1'b1; + end + end + + 10'bx1xxxxxxxx: // p5_1HOT_ENCODING: // + begin + if (t4_) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[4] = 1'b1; + end + end + + 10'b1xxxxxxxxx: // p2_1HOT_ENCODING: // + begin + if (t3_) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[5] = 1'b1; + end + end + + default: + begin + next_state = 10'dx; + end + endcase + end +endmodule + diff --git a/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..77e52f6 --- /dev/null +++ b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,170 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + t9_, + t6_, + t3_, + t0_, + t8_, + t5_, + t2_, + t7_, + t4_, + t1_ +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t9_; + input t6_; + input t3_; + input t0_; + input t8_; + input t5_; + input t2_; + input t7_; + input t4_; + input t1_; + // Transition Barrier Inputs for input Signals // + // === EMPTY! === // + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + // === EMPTY! === // + + + + parameter p7_1HOT_ENCODING = 10'd1; // 10'b0000000001 // + parameter p4_1HOT_ENCODING = 10'd2; // 10'b0000000010 // + parameter p1_1HOT_ENCODING = 10'd4; // 10'b0000000100 // + parameter p9_1HOT_ENCODING = 10'd8; // 10'b0000001000 // + parameter p6_1HOT_ENCODING = 10'd16; // 10'b0000010000 // + parameter p3_1HOT_ENCODING = 10'd32; // 10'b0000100000 // + parameter p0_1HOT_ENCODING = 10'd64; // 10'b0001000000 // + parameter p8_1HOT_ENCODING = 10'd128; // 10'b0010000000 // + parameter p5_1HOT_ENCODING = 10'd256; // 10'b0100000000 // + parameter p2_1HOT_ENCODING = 10'd512; // 10'b1000000000 // + + reg [9 : 0] state; + reg [9 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p7_1HOT_ENCODING; + state <= p4_1HOT_ENCODING; + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + + always @(state or t9_ or t6_ or t3_ or t0_ or t8_ or t5_ or t2_ or t7_ or t4_ or t1_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p7_1HOT_ENCODING: // 10'b0000000001: // + begin + if (t6_) + begin + next_state = p8_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 10'b0000000010: // + begin + if (t5_) + begin + next_state = p5_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 10'b0000000100: // + begin + if (t0_) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 10'b0000001000: // + begin + if (t8_) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 10'b0000010000: // + begin + if (t7_) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 10'b0000100000: // + begin + if (t2_) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 10'b0001000000: // + begin + if (t1_) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 10'b0010000000: // + begin + if (t9_) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 10'b0100000000: // + begin + if (t4_) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 10'b1000000000: // + begin + if (t3_) + begin + next_state = p3_1HOT_ENCODING; + end + end + + default: + begin + next_state = 10'dx; + end + endcase + end +endmodule + diff --git a/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..af25c72 --- /dev/null +++ b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,48 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + t9, + t6, + t3, + t0, + t8, + t5, + t2, + t7, + t4, + t1); + + input clk; + input reset; + input t9; + input t6; + input t3; + input t0; + input t8; + input t5; + input t2; + input t7; + input t4; + input t1; + + wire p7_FSM1out, p4_FSM1out, p1_FSM1out, p9_FSM1out, p6_FSM1out, p3_FSM1out, p0_FSM1out, p8_FSM1out, p5_FSM1out, p2_FSM1out; // State Synchronisation output signals of FSM1 // + + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .t9_(t9), + .t6_(t6), + .t3_(t3), + .t0_(t0), + .t8_(t8), + .t5_(t5), + .t2_(t2), + .t7_(t7), + .t4_(t4), + .t1_(t1) + ); + +endmodule // msfsms_mealy // diff --git a/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..2d4a086 --- /dev/null +++ b/examples/5-dining-philosophers_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,48 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + t9, + t6, + t3, + t0, + t8, + t5, + t2, + t7, + t4, + t1); + + input clk; + input reset; + input t9; + input t6; + input t3; + input t0; + input t8; + input t5; + input t2; + input t7; + input t4; + input t1; + + wire p7_FSM1out, p4_FSM1out, p1_FSM1out, p9_FSM1out, p6_FSM1out, p3_FSM1out, p0_FSM1out, p8_FSM1out, p5_FSM1out, p2_FSM1out; // State Synchronisation output signals of FSM1 // + + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .t9_(t9), + .t6_(t6), + .t3_(t3), + .t0_(t0), + .t8_(t8), + .t5_(t5), + .t2_(t2), + .t7_(t7), + .t4_(t4), + .t1_(t1) + ); + +endmodule // msfsms_mealy // diff --git a/examples/5-dining-philosophers_GN/msfsms_tool_bm.log b/examples/5-dining-philosophers_GN/msfsms_tool_bm.log new file mode 100644 index 0000000..f4e6a02 --- /dev/null +++ b/examples/5-dining-philosophers_GN/msfsms_tool_bm.log @@ -0,0 +1,218 @@ +--------------------------------------------------------------------------- +Benchmark: 5-dining-philosophers_GN/5-dining-philosophers.petrinet.GN.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/5-dining-philosophers_GN/5-dining-philosophers.petrinet.GN.workcraft.g +INFO: Total Nodes : 20 +INFO: Total Transitions : 10 +INFO: Total Places : 10 +INFO: Total Edges : 30 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = p7, Type = Place (is Marked) + Predecessors: t7[16][0] + Successors: t6[3][0] +PT-Net [1][0]: Label = p4, Type = Place (is Marked) + Predecessors: t2[11][0], t4[17][0] + Successors: t3[4][0], t5[10][0] +PT-Net [2][0]: Label = p1, Type = Place (is Marked) + Predecessors: t1[18][0] + Successors: t0[5][0] +PT-Net [2][1]: Label = t9, Type = Transition (is Input) + Predecessors: p0[9][0], p8[13][0] + Successors: p9[6][0] +PT-Net [3][0]: Label = t6, Type = Transition (is Input) + Predecessors: p7[0][0] + Successors: p6[7][0], p8[13][0] +PT-Net [4][0]: Label = t3, Type = Transition (is Input) + Predecessors: p2[15][0], p4[1][0] + Successors: p3[8][0] +PT-Net [5][0]: Label = t0, Type = Transition (is Input) + Predecessors: p1[2][0] + Successors: p0[9][0], p2[15][0] +PT-Net [6][0]: Label = p9, Type = Place (is Empty) + Predecessors: t9[2][1] + Successors: t8[9][1] +PT-Net [7][0]: Label = p6, Type = Place (is Empty) + Predecessors: t4[17][0], t6[3][0] + Successors: t5[10][0], t7[16][0] +PT-Net [8][0]: Label = p3, Type = Place (is Empty) + Predecessors: t3[4][0] + Successors: t2[11][0] +PT-Net [9][0]: Label = p0, Type = Place (is Empty) + Predecessors: t0[5][0], t8[9][1] + Successors: t1[18][0], t9[2][1] +PT-Net [9][1]: Label = t8, Type = Transition (is Input) + Predecessors: p9[6][0] + Successors: p0[9][0], p8[13][0] +PT-Net [10][0]: Label = t5, Type = Transition (is Input) + Predecessors: p4[1][0], p6[7][0] + Successors: p5[14][0] +PT-Net [11][0]: Label = t2, Type = Transition (is Input) + Predecessors: p3[8][0] + Successors: p2[15][0], p4[1][0] +PT-Net [13][0]: Label = p8, Type = Place (is Empty) + Predecessors: t6[3][0], t8[9][1] + Successors: t7[16][0], t9[2][1] +PT-Net [14][0]: Label = p5, Type = Place (is Empty) + Predecessors: t5[10][0] + Successors: t4[17][0] +PT-Net [15][0]: Label = p2, Type = Place (is Empty) + Predecessors: t0[5][0], t2[11][0] + Successors: t1[18][0], t3[4][0] +PT-Net [16][0]: Label = t7, Type = Transition (is Input) + Predecessors: p6[7][0], p8[13][0] + Successors: p7[0][0] +PT-Net [17][0]: Label = t4, Type = Transition (is Input) + Predecessors: p5[14][0] + Successors: p4[1][0], p6[7][0] +PT-Net [18][0]: Label = t1, Type = Transition (is Input) + Predecessors: p2[15][0], p0[9][0] + Successors: p1[2][0] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #1 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 20, H-collapsed = 'false' *** +SC S-net (1,1): p7[0][0] +SC S-net (1,2): p4[1][0] +SC S-net (1,3): p1[2][0] +SC S-net (1,4): t9[2][1] + Predecessor Place: p8(1,15)[13,0] + Successor Place: p9(1,8)[6,0] +SC S-net (1,5): t6[3][0] + Predecessor Place: p7(1,1)[0,0] + Successor Place: p8(1,15)[13,0] +SC S-net (1,6): t3[4][0] + Predecessor Place: p2(1,17)[15,0] + Successor Place: p3(1,10)[8,0] +SC S-net (1,7): t0[5][0] + Predecessor Place: p1(1,3)[2,0] + Successor Place: p2(1,17)[15,0] +SC S-net (1,8): p9[6][0] +SC S-net (1,9): p6[7][0] +SC S-net (1,10): p3[8][0] +SC S-net (1,11): p0[9][0] +SC S-net (1,12): t8[9][1] + Predecessor Place: p9(1,8)[6,0] + Successor Place: p0(1,11)[9,0] +SC S-net (1,13): t5[10][0] + Predecessor Place: p4(1,2)[1,0] + Successor Place: p5(1,16)[14,0] +SC S-net (1,14): t2[11][0] + Predecessor Place: p3(1,10)[8,0] + Successor Place: p4(1,2)[1,0] +SC S-net (1,15): p8[13][0] +SC S-net (1,16): p5[14][0] +SC S-net (1,17): p2[15][0] +SC S-net (1,18): t7[16][0] + Predecessor Place: p6(1,9)[7,0] + Successor Place: p7(1,1)[0,0] +SC S-net (1,19): t4[17][0] + Predecessor Place: p5(1,16)[14,0] + Successor Place: p6(1,9)[7,0] +SC S-net (1,20): t1[18][0] + Predecessor Place: p0(1,11)[9,0] + Successor Place: p1(1,3)[2,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #1 total). +INFO: P "p4"[1, 0] should NOT be a successor of T "t4"[17, 0] in S-Net #1. +INFO: P "p4"[1, 0] should NOT be a predecessor of T "t3"[4, 0] in S-Net #1. +INFO: P "p6"[7, 0] should NOT be a successor of T "t6"[3, 0] in S-Net #1. +INFO: P "p6"[7, 0] should NOT be a predecessor of T "t5"[10, 0] in S-Net #1. +INFO: P "p0"[9, 0] should NOT be a successor of T "t0"[5, 0] in S-Net #1. +INFO: P "p0"[9, 0] should NOT be a predecessor of T "t9"[2, 1] in S-Net #1. +INFO: P "p8"[13, 0] should NOT be a successor of T "t8"[9, 1] in S-Net #1. +INFO: P "p8"[13, 0] should NOT be a predecessor of T "t7"[16, 0] in S-Net #1. +INFO: P "p2"[15, 0] should NOT be a successor of T "t2"[11, 0] in S-Net #1. +INFO: P "p2"[15, 0] should NOT be a predecessor of T "t1"[18, 0] in S-Net #1. +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 20, H-Collapsed = 'false' *** +FSM (1,1): Label = p7, Type = State (is Initially Active) + Successor(s): t6/(0,5) + Predecessor(s): t7/(0,18) +FSM (1,2): Label = p4, Type = State (is Initially Active) + Successor(s): t5/(0,13) + Predecessor(s): t2/(0,14) +FSM (1,3): Label = p1, Type = State (is Initially Active) + Successor(s): t0/(0,7) + Predecessor(s): t1/(0,20) +FSM (1,4): Label = t9/, Type = Trans. Function (is Input) + Successor(s): p9(0,8) + Predecessor(s): p8(0,15) +FSM (1,5): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p8(0,15) + Predecessor(s): p7(0,1) +FSM (1,6): Label = t3/, Type = Trans. Function (is Input) + Successor(s): p3(0,10) + Predecessor(s): p2(0,17) +FSM (1,7): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p2(0,17) + Predecessor(s): p1(0,3) +FSM (1,8): Label = p9, Type = State (is Initially Inactive) + Successor(s): t8/(0,12) + Predecessor(s): t9/(0,4) +FSM (1,9): Label = p6, Type = State (is Initially Inactive) + Successor(s): t7/(0,18) + Predecessor(s): t4/(0,19) +FSM (1,10): Label = p3, Type = State (is Initially Inactive) + Successor(s): t2/(0,14) + Predecessor(s): t3/(0,6) +FSM (1,11): Label = p0, Type = State (is Initially Inactive) + Successor(s): t1/(0,20) + Predecessor(s): t8/(0,12) +FSM (1,12): Label = t8/, Type = Trans. Function (is Input) + Successor(s): p0(0,11) + Predecessor(s): p9(0,8) +FSM (1,13): Label = t5/, Type = Trans. Function (is Input) + Successor(s): p5(0,16) + Predecessor(s): p4(0,2) +FSM (1,14): Label = t2/, Type = Trans. Function (is Input) + Successor(s): p4(0,2) + Predecessor(s): p3(0,10) +FSM (1,15): Label = p8, Type = State (is Initially Inactive) + Successor(s): t9/(0,4) + Predecessor(s): t6/(0,5) +FSM (1,16): Label = p5, Type = State (is Initially Inactive) + Successor(s): t4/(0,19) + Predecessor(s): t5/(0,13) +FSM (1,17): Label = p2, Type = State (is Initially Inactive) + Successor(s): t3/(0,6) + Predecessor(s): t0/(0,7) +FSM (1,18): Label = t7/, Type = Trans. Function (is Input) + Successor(s): p7(0,1) + Predecessor(s): p6(0,9) +FSM (1,19): Label = t4/, Type = Trans. Function (is Input) + Successor(s): p6(0,9) + Predecessor(s): p5(0,16) +FSM (1,20): Label = t1/, Type = Trans. Function (is Input) + Successor(s): p1(0,3) + Predecessor(s): p0(0,11) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +WARNING: Multiple initial active states for FSM(1), continuing... +WARNING: Multiple Active states for FSMs: |#1| +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +WARNING: Multiple initial active states for FSM(1), continuing... +WARNING: Multiple Active states for FSMs: |#1| +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +WARNING: Multiple initial active states for FSM(1), continuing... +WARNING: Multiple Active states for FSMs: |#1| +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/Basic-EFC-v01-PTnet/Basic-EFC-v01-PTnet.png b/examples/Basic-EFC-v01-PTnet/Basic-EFC-v01-PTnet.png deleted file mode 100644 index 2f466c9..0000000 Binary files a/examples/Basic-EFC-v01-PTnet/Basic-EFC-v01-PTnet.png and /dev/null differ diff --git a/examples/Basic-EFC-v01-PTnet/Basic-EFC-v01-PTnet.work b/examples/Basic-EFC-v01-PTnet/Basic-EFC-v01-PTnet.work deleted file mode 100644 index 00cb52d..0000000 Binary files a/examples/Basic-EFC-v01-PTnet/Basic-EFC-v01-PTnet.work and /dev/null differ diff --git a/examples/Basic-EFC-v01-PTnet/script.tcl b/examples/Basic-EFC-v01-PTnet/script.tcl deleted file mode 100644 index 5249ad8..0000000 --- a/examples/Basic-EFC-v01-PTnet/script.tcl +++ /dev/null @@ -1,6 +0,0 @@ -read_graph -format work Basic-EFC-v01-PTnet.work -get_scover -fsm_collapsing -sync_fsm -write_fsms_to_petrify_format -format sg -multiplefiles 1 -quit diff --git a/examples/Basic-FC-v02-PTnet/Basic-FC-v02-PTnet.png b/examples/Basic-FC-v02-PTnet/Basic-FC-v02-PTnet.png deleted file mode 100644 index 8bb8880..0000000 Binary files a/examples/Basic-FC-v02-PTnet/Basic-FC-v02-PTnet.png and /dev/null differ diff --git a/examples/Basic-FC-v02-PTnet/Basic-FC-v02-PTnet.work b/examples/Basic-FC-v02-PTnet/Basic-FC-v02-PTnet.work deleted file mode 100644 index d104c73..0000000 Binary files a/examples/Basic-FC-v02-PTnet/Basic-FC-v02-PTnet.work and /dev/null differ diff --git a/examples/Basic-FC-v02-PTnet/script.tcl b/examples/Basic-FC-v02-PTnet/script.tcl deleted file mode 100644 index cb062e3..0000000 --- a/examples/Basic-FC-v02-PTnet/script.tcl +++ /dev/null @@ -1,6 +0,0 @@ -read_graph -format work Basic-FC-v02-PTnet.work -get_scover -fsm_collapsing -sync_fsm -write_fsms_to_petrify_format -format sg -multiplefiles 1 -quit diff --git a/examples/Basic-FC-v03-PTnet/script.tcl b/examples/Basic-FC-v03-PTnet/script.tcl deleted file mode 100644 index 9ab5b76..0000000 --- a/examples/Basic-FC-v03-PTnet/script.tcl +++ /dev/null @@ -1,6 +0,0 @@ -read_graph -format g Basic-FC-v03-PTnet.g -get_scover -fsm_collapsing -sync_fsm -write_fsms_to_petrify_format -format sg -multiplefiles 1 -quit diff --git a/examples/and-gate_GN/AsyncMSFSMs/fsm_afsm.afsm b/examples/and-gate_GN/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..ad4832e --- /dev/null +++ b/examples/and-gate_GN/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,28 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p3: t7_ t7__p3_FSM2_TB p6 +p3: t8_ t8__p5_FSM2_TB p7 +p2: t6_ t6__p2_FSM2_TB p6 +p7: e_out_M e_out_M_p7_FSM2_TB p1 +p1*: b_P_ p4 +p6: e_out_P e_out_P_p6_FSM2_TB p0 +p0*: a_M_ a_M__p0_FSM2_TB p3 +p0*: a_P_ a_P__p0_FSM2_TB p2 +p4: t5_ t5__p2_FSM2_TB p6 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p3: t7_ t7__p3_FSM1_TB p6 +p2: t5_ t5__p4_FSM1_TB p6 +p2: t6_ t6__p2_FSM1_TB p6 +p7: e_out_M e_out_M_p7_FSM1_TB p0 +p1*: b_M_ p5 +p6: e_out_P e_out_P_p6_FSM1_TB p1 +p0*: a_M_ a_M__p0_FSM1_TB p3 +p0*: a_P_ a_P__p0_FSM1_TB p2 +p5: t8_ t8__p3_FSM1_TB p7 +### End of FSM #02 Declaration ### + diff --git a/examples/and-gate_GN/AsyncMSFSMs/msfsms_afsm.v b/examples/and-gate_GN/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..ff1994a --- /dev/null +++ b/examples/and-gate_GN/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,73 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + a_P, + b_M, + t8, + out_M, + t7, + t6, + a_M, + b_P, + t5, + out_P); + + input reset; + input a_P; + input b_M; + input t8; + output out_M; + input t7; + input t6; + input a_M; + input b_P; + input t5; + output out_P; + + wire e_out_M_FSM1out, e_out_P_FSM1out; // Regular output signals of FSM1 // + wire p3_FSM1out, p2_FSM1out, p7_FSM1out, p1_FSM1out, p6_FSM1out, p0_FSM1out, p4_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_out_M_FSM2out, e_out_P_FSM2out; // Regular output signals of FSM2 // + wire p3_FSM2out, p2_FSM2out, p7_FSM2out, p1_FSM2out, p6_FSM2out, p0_FSM2out, p5_FSM2out; // State Synchronisation output signals of FSM2 // + + assign out_M = e_out_M_FSM1out & e_out_M_FSM2out; + assign out_P = e_out_P_FSM1out & e_out_P_FSM2out; + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .a_P_(a_P), .a_P__p0_FSM2_TB(p0_FSM2out), + .t8_(t8), .t8__p5_FSM2_TB(p5_FSM2out), + .t7_(t7), .t7__p3_FSM2_TB(p3_FSM2out), + .t6_(t6), .t6__p2_FSM2_TB(p2_FSM2out), + .a_M_(a_M), .a_M__p0_FSM2_TB(p0_FSM2out), + .b_P_(b_P), + .t5_(t5), .t5__p2_FSM2_TB(p2_FSM2out), + .e_out_M(p7_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), + .e_out_P(p6_FSM1out), .e_out_P_p6_FSM2_TB(p6_FSM2out), + .e/out_M(e/out_M_FSM1out), + .e/out_P(e/out_P_FSM1out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .a_P_(a_P), .a_P__p0_FSM1_TB(p0_FSM1out), + .b_M_(b_M), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), + .t6_(t6), .t6__p2_FSM1_TB(p2_FSM1out), + .a_M_(a_M), .a_M__p0_FSM1_TB(p0_FSM1out), + .t5_(t5), .t5__p4_FSM1_TB(p4_FSM1out), + .e_out_M(p7_FSM2out), .e_out_M_p7_FSM1_TB(p7_FSM1out), + .e_out_P(p6_FSM2out), .e_out_P_p6_FSM1_TB(p6_FSM1out), + .e/out_M(e/out_M_FSM2out), + .e/out_P(e/out_P_FSM2out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/and-gate_GN/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/and-gate_GN/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..6891904 --- /dev/null +++ b/examples/and-gate_GN/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,456 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + a_P_, a_P__p0_FSM2_TB, + t8_, t8__p5_FSM2_TB, + t7_, t7__p3_FSM2_TB, + t6_, t6__p2_FSM2_TB, + a_M_, a_M__p0_FSM2_TB, + b_P_, + t5_, t5__p2_FSM2_TB, + e_out_M, e_out_M_p7_FSM2_TB, + e_out_P, e_out_P_p6_FSM2_TB, + p3, + p2, + p7, + p6, + p0, + p4 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input a_P_; + input t8_; + input t7_; + input t6_; + input a_M_; + input b_P_; + input t5_; + // Transition Barrier Inputs for input Signals // + input a_P__p0_FSM2_TB; + input t8__p5_FSM2_TB; + input t7__p3_FSM2_TB; + input t6__p2_FSM2_TB; + input a_M__p0_FSM2_TB; + input t5__p2_FSM2_TB; + + // Regular output Signals // + output e_out_M; + output e_out_P; + // Transition Barrier outputs for output Signals // + input e_out_M_p7_FSM2_TB; + input e_out_P_p6_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p3; + output p2; + output p7; + output p6; + output p0; + output p4; + + reg e_out_M; + reg e_out_P; + wire p3; + wire p2; + wire p7; + wire p6; + wire p0; + wire p4; + + wire a_P__TB_sync; + wire t8__TB_sync; + wire t7__TB_sync; + wire t6__TB_sync; + wire a_M__TB_sync; + wire t5__TB_sync; + wire e_out_M_TB_sync; + wire e_out_P_TB_sync; + assign a_P__TB_sync = a_P_ & a_P__p0_FSM2_TB; + assign t8__TB_sync = t8_ & t8__p5_FSM2_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM2_TB; + assign t6__TB_sync = t6_ & t6__p2_FSM2_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM2_TB; + assign t5__TB_sync = t5_ & t5__p2_FSM2_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM2_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM2_TB; + + parameter p3_1HOT_ENCODING = 7'd1; // 7'b0000001 // + parameter p3_1HOT_CASEX_ENCODING = 7'bxxxxxx1; // 7'b0000001 // + parameter p2_1HOT_ENCODING = 7'd2; // 7'b0000010 // + parameter p2_1HOT_CASEX_ENCODING = 7'bxxxxx1x; // 7'b0000010 // + parameter p7_1HOT_ENCODING = 7'd4; // 7'b0000100 // + parameter p7_1HOT_CASEX_ENCODING = 7'bxxxx1xx; // 7'b0000100 // + parameter p1_1HOT_ENCODING = 7'd8; // 7'b0001000 // + parameter p1_1HOT_CASEX_ENCODING = 7'bxxx1xxx; // 7'b0001000 // + parameter p6_1HOT_ENCODING = 7'd16; // 7'b0010000 // + parameter p6_1HOT_CASEX_ENCODING = 7'bxx1xxxx; // 7'b0010000 // + parameter p0_1HOT_ENCODING = 7'd32; // 7'b0100000 // + parameter p0_1HOT_CASEX_ENCODING = 7'bx1xxxxx; // 7'b0100000 // + parameter p4_1HOT_ENCODING = 7'd64; // 7'b1000000 // + parameter p4_1HOT_CASEX_ENCODING = 7'b1xxxxxx; // 7'b1000000 // + + reg [6 : 0] state; + reg [6 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + // state <= p0_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + state[4] <= 1'b0; + state[5] <= 1'b1; + state[6] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or a_P__TB_sync or t8__TB_sync or t7__TB_sync or t6__TB_sync or a_M__TB_sync or b_P_ or t5__TB_sync or e_out_M_TB_sync or e_out_P_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_M = 1'b0; + e_out_P = 1'b0; + + casex (state) + 7'bxxxxxx1: // p3_1HOT_ENCODING: // + begin + if (t7__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[4] = 1'b1; + end + else if (t8__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[2] = 1'b1; + end + end + + 7'bxxxxx1x: // p2_1HOT_ENCODING: // + begin + if (t6__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[4] = 1'b1; + end + end + + 7'bxxxx1xx: // p7_1HOT_ENCODING: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[3] = 1'b1; + end + end + + 7'bxxx1xxx: // p1_1HOT_ENCODING: // + begin + if (b_P_) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[6] = 1'b1; + end + end + + 7'bxx1xxxx: // p6_1HOT_ENCODING: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[5] = 1'b1; + end + end + + 7'bx1xxxxx: // p0_1HOT_ENCODING: // + begin + if (a_M__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[0] = 1'b1; + end + else if (a_P__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[1] = 1'b1; + end + end + + 7'b1xxxxxx: // p4_1HOT_ENCODING: // + begin + if (t5__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[4] = 1'b1; + end + end + + default: + begin + next_state = 7'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + a_P_, a_P__p0_FSM1_TB, + b_M_, + t8_, t8__p3_FSM1_TB, + t7_, t7__p3_FSM1_TB, + t6_, t6__p2_FSM1_TB, + a_M_, a_M__p0_FSM1_TB, + t5_, t5__p4_FSM1_TB, + e_out_M, e_out_M_p7_FSM1_TB, + e_out_P, e_out_P_p6_FSM1_TB, + p3, + p2, + p7, + p6, + p0, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input a_P_; + input b_M_; + input t8_; + input t7_; + input t6_; + input a_M_; + input t5_; + // Transition Barrier Inputs for input Signals // + input a_P__p0_FSM1_TB; + input t8__p3_FSM1_TB; + input t7__p3_FSM1_TB; + input t6__p2_FSM1_TB; + input a_M__p0_FSM1_TB; + input t5__p4_FSM1_TB; + + // Regular output Signals // + output e_out_M; + output e_out_P; + // Transition Barrier outputs for output Signals // + input e_out_M_p7_FSM1_TB; + input e_out_P_p6_FSM1_TB; + + // FSMs' Synchronisation output Signals // + output p3; + output p2; + output p7; + output p6; + output p0; + output p5; + + reg e_out_M; + reg e_out_P; + wire p3; + wire p2; + wire p7; + wire p6; + wire p0; + wire p5; + + wire a_P__TB_sync; + wire t8__TB_sync; + wire t7__TB_sync; + wire t6__TB_sync; + wire a_M__TB_sync; + wire t5__TB_sync; + wire e_out_M_TB_sync; + wire e_out_P_TB_sync; + assign a_P__TB_sync = a_P_ & a_P__p0_FSM1_TB; + assign t8__TB_sync = t8_ & t8__p3_FSM1_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM1_TB; + assign t6__TB_sync = t6_ & t6__p2_FSM1_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM1_TB; + assign t5__TB_sync = t5_ & t5__p4_FSM1_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM1_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM1_TB; + + parameter p3_1HOT_ENCODING = 7'd1; // 7'b0000001 // + parameter p3_1HOT_CASEX_ENCODING = 7'bxxxxxx1; // 7'b0000001 // + parameter p2_1HOT_ENCODING = 7'd2; // 7'b0000010 // + parameter p2_1HOT_CASEX_ENCODING = 7'bxxxxx1x; // 7'b0000010 // + parameter p7_1HOT_ENCODING = 7'd4; // 7'b0000100 // + parameter p7_1HOT_CASEX_ENCODING = 7'bxxxx1xx; // 7'b0000100 // + parameter p1_1HOT_ENCODING = 7'd8; // 7'b0001000 // + parameter p1_1HOT_CASEX_ENCODING = 7'bxxx1xxx; // 7'b0001000 // + parameter p6_1HOT_ENCODING = 7'd16; // 7'b0010000 // + parameter p6_1HOT_CASEX_ENCODING = 7'bxx1xxxx; // 7'b0010000 // + parameter p0_1HOT_ENCODING = 7'd32; // 7'b0100000 // + parameter p0_1HOT_CASEX_ENCODING = 7'bx1xxxxx; // 7'b0100000 // + parameter p5_1HOT_ENCODING = 7'd64; // 7'b1000000 // + parameter p5_1HOT_CASEX_ENCODING = 7'b1xxxxxx; // 7'b1000000 // + + reg [6 : 0] state; + reg [6 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + // state <= p0_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + state[4] <= 1'b0; + state[5] <= 1'b1; + state[6] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or a_P__TB_sync or b_M_ or t8__TB_sync or t7__TB_sync or t6__TB_sync or a_M__TB_sync or t5__TB_sync or e_out_M_TB_sync or e_out_P_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_M = 1'b0; + e_out_P = 1'b0; + + casex (state) + 7'bxxxxxx1: // p3_1HOT_ENCODING: // + begin + if (t7__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[4] = 1'b1; + end + end + + 7'bxxxxx1x: // p2_1HOT_ENCODING: // + begin + if (t5__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[4] = 1'b1; + end + else if (t6__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[4] = 1'b1; + end + end + + 7'bxxxx1xx: // p7_1HOT_ENCODING: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[5] = 1'b1; + end + end + + 7'bxxx1xxx: // p1_1HOT_ENCODING: // + begin + if (b_M_) + begin + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[6] = 1'b1; + end + end + + 7'bxx1xxxx: // p6_1HOT_ENCODING: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 7'bx1xxxxx: // p0_1HOT_ENCODING: // + begin + if (a_M__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[0] = 1'b1; + end + else if (a_P__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[1] = 1'b1; + end + end + + 7'b1xxxxxx: // p5_1HOT_ENCODING: // + begin + if (t8__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 7'dx; + end + endcase + end +endmodule + diff --git a/examples/and-gate_GN/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/and-gate_GN/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..3301a7a --- /dev/null +++ b/examples/and-gate_GN/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,392 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + a_P_, a_P__p0_FSM2_TB, + t8_, t8__p5_FSM2_TB, + t7_, t7__p3_FSM2_TB, + t6_, t6__p2_FSM2_TB, + a_M_, a_M__p0_FSM2_TB, + b_P_, + t5_, t5__p2_FSM2_TB, + e_out_M, e_out_M_p7_FSM2_TB, + e_out_P, e_out_P_p6_FSM2_TB, + p3, + p2, + p7, + p6, + p0, + p4 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input a_P_; + input t8_; + input t7_; + input t6_; + input a_M_; + input b_P_; + input t5_; + // Transition Barrier Inputs for input Signals // + input a_P__p0_FSM2_TB; + input t8__p5_FSM2_TB; + input t7__p3_FSM2_TB; + input t6__p2_FSM2_TB; + input a_M__p0_FSM2_TB; + input t5__p2_FSM2_TB; + + // Regular output Signals // + output e_out_M; + output e_out_P; + // Transition Barrier outputs for output Signals // + input e_out_M_p7_FSM2_TB; + input e_out_P_p6_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p3; + output p2; + output p7; + output p6; + output p0; + output p4; + + reg e_out_M; + reg e_out_P; + wire p3; + wire p2; + wire p7; + wire p6; + wire p0; + wire p4; + + wire a_P__TB_sync; + wire t8__TB_sync; + wire t7__TB_sync; + wire t6__TB_sync; + wire a_M__TB_sync; + wire t5__TB_sync; + wire e_out_M_TB_sync; + wire e_out_P_TB_sync; + assign a_P__TB_sync = a_P_ & a_P__p0_FSM2_TB; + assign t8__TB_sync = t8_ & t8__p5_FSM2_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM2_TB; + assign t6__TB_sync = t6_ & t6__p2_FSM2_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM2_TB; + assign t5__TB_sync = t5_ & t5__p2_FSM2_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM2_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM2_TB; + + parameter p3_1HOT_ENCODING = 7'd1; // 7'b0000001 // + parameter p2_1HOT_ENCODING = 7'd2; // 7'b0000010 // + parameter p7_1HOT_ENCODING = 7'd4; // 7'b0000100 // + parameter p1_1HOT_ENCODING = 7'd8; // 7'b0001000 // + parameter p6_1HOT_ENCODING = 7'd16; // 7'b0010000 // + parameter p0_1HOT_ENCODING = 7'd32; // 7'b0100000 // + parameter p4_1HOT_ENCODING = 7'd64; // 7'b1000000 // + + reg [6 : 0] state; + reg [6 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + state <= p0_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or a_P__TB_sync or t8__TB_sync or t7__TB_sync or t6__TB_sync or a_M__TB_sync or b_P_ or t5__TB_sync or e_out_M_TB_sync or e_out_P_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_M = 1'b0; + e_out_P = 1'b0; + + case (state) + p3_1HOT_ENCODING: // 7'b0000001: // + begin + if (t7__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + else if (t8__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 7'b0000010: // + begin + if (t6__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 7'b0000100: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + next_state = p1_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 7'b0001000: // + begin + if (b_P_) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 7'b0010000: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + next_state = p0_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 7'b0100000: // + begin + if (a_M__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + else if (a_P__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 7'b1000000: // + begin + if (t5__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + default: + begin + next_state = 7'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + a_P_, a_P__p0_FSM1_TB, + b_M_, + t8_, t8__p3_FSM1_TB, + t7_, t7__p3_FSM1_TB, + t6_, t6__p2_FSM1_TB, + a_M_, a_M__p0_FSM1_TB, + t5_, t5__p4_FSM1_TB, + e_out_M, e_out_M_p7_FSM1_TB, + e_out_P, e_out_P_p6_FSM1_TB, + p3, + p2, + p7, + p6, + p0, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input a_P_; + input b_M_; + input t8_; + input t7_; + input t6_; + input a_M_; + input t5_; + // Transition Barrier Inputs for input Signals // + input a_P__p0_FSM1_TB; + input t8__p3_FSM1_TB; + input t7__p3_FSM1_TB; + input t6__p2_FSM1_TB; + input a_M__p0_FSM1_TB; + input t5__p4_FSM1_TB; + + // Regular output Signals // + output e_out_M; + output e_out_P; + // Transition Barrier outputs for output Signals // + input e_out_M_p7_FSM1_TB; + input e_out_P_p6_FSM1_TB; + + // FSMs' Synchronisation output Signals // + output p3; + output p2; + output p7; + output p6; + output p0; + output p5; + + reg e_out_M; + reg e_out_P; + wire p3; + wire p2; + wire p7; + wire p6; + wire p0; + wire p5; + + wire a_P__TB_sync; + wire t8__TB_sync; + wire t7__TB_sync; + wire t6__TB_sync; + wire a_M__TB_sync; + wire t5__TB_sync; + wire e_out_M_TB_sync; + wire e_out_P_TB_sync; + assign a_P__TB_sync = a_P_ & a_P__p0_FSM1_TB; + assign t8__TB_sync = t8_ & t8__p3_FSM1_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM1_TB; + assign t6__TB_sync = t6_ & t6__p2_FSM1_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM1_TB; + assign t5__TB_sync = t5_ & t5__p4_FSM1_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM1_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM1_TB; + + parameter p3_1HOT_ENCODING = 7'd1; // 7'b0000001 // + parameter p2_1HOT_ENCODING = 7'd2; // 7'b0000010 // + parameter p7_1HOT_ENCODING = 7'd4; // 7'b0000100 // + parameter p1_1HOT_ENCODING = 7'd8; // 7'b0001000 // + parameter p6_1HOT_ENCODING = 7'd16; // 7'b0010000 // + parameter p0_1HOT_ENCODING = 7'd32; // 7'b0100000 // + parameter p5_1HOT_ENCODING = 7'd64; // 7'b1000000 // + + reg [6 : 0] state; + reg [6 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + state <= p0_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or a_P__TB_sync or b_M_ or t8__TB_sync or t7__TB_sync or t6__TB_sync or a_M__TB_sync or t5__TB_sync or e_out_M_TB_sync or e_out_P_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_M = 1'b0; + e_out_P = 1'b0; + + case (state) + p3_1HOT_ENCODING: // 7'b0000001: // + begin + if (t7__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 7'b0000010: // + begin + if (t5__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + else if (t6__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 7'b0000100: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + next_state = p0_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 7'b0001000: // + begin + if (b_M_) + begin + next_state = p5_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 7'b0010000: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + next_state = p1_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 7'b0100000: // + begin + if (a_M__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + else if (a_P__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 7'b1000000: // + begin + if (t8__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 7'dx; + end + endcase + end +endmodule + diff --git a/examples/and-gate_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/and-gate_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..3b14455 --- /dev/null +++ b/examples/and-gate_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,79 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + a_P, + b_M, + t8, + out_M, + t7, + t6, + a_M, + b_P, + t5, + out_P); + + input clk; + input reset; + input a_P; + input b_M; + input t8; + output out_M; + input t7; + input t6; + input a_M; + input b_P; + input t5; + output out_P; + + wire e_out_M_FSM1out, e_out_P_FSM1out; // Regular output signals of FSM1 // + wire p3_FSM1out, p2_FSM1out, p7_FSM1out, p1_FSM1out, p6_FSM1out, p0_FSM1out, p4_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_out_M_FSM2out, e_out_P_FSM2out; // Regular output signals of FSM2 // + wire p3_FSM2out, p2_FSM2out, p7_FSM2out, p1_FSM2out, p6_FSM2out, p0_FSM2out, p5_FSM2out; // State Synchronisation output signals of FSM2 // + + assign out_M = e_out_M_FSM1out & e_out_M_FSM2out; + assign out_P = e_out_P_FSM1out & e_out_P_FSM2out; + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .a_P_(a_P), .a_P__p0_FSM2_TB(p0_FSM2out), + .t8_(t8), .t8__p5_FSM2_TB(p5_FSM2out), + .t7_(t7), .t7__p3_FSM2_TB(p3_FSM2out), + .t6_(t6), .t6__p2_FSM2_TB(p2_FSM2out), + .a_M_(a_M), .a_M__p0_FSM2_TB(p0_FSM2out), + .b_P_(b_P), + .t5_(t5), .t5__p2_FSM2_TB(p2_FSM2out), + .e_out_M(e_out_M_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), + .e_out_P(e_out_P_FSM1out), .e_out_P_p6_FSM2_TB(p6_FSM2out), + .p3(p3_FSM1out), + .p2(p2_FSM1out), + .p7(p7_FSM1out), + .p6(p6_FSM1out), + .p0(p0_FSM1out), + .p4(p4_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .a_P_(a_P), .a_P__p0_FSM1_TB(p0_FSM1out), + .b_M_(b_M), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), + .t6_(t6), .t6__p2_FSM1_TB(p2_FSM1out), + .a_M_(a_M), .a_M__p0_FSM1_TB(p0_FSM1out), + .t5_(t5), .t5__p4_FSM1_TB(p4_FSM1out), + .e_out_M(e_out_M_FSM2out), .e_out_M_p7_FSM1_TB(p7_FSM1out), + .e_out_P(e_out_P_FSM2out), .e_out_P_p6_FSM1_TB(p6_FSM1out), + .p3(p3_FSM2out), + .p2(p2_FSM2out), + .p7(p7_FSM2out), + .p6(p6_FSM2out), + .p0(p0_FSM2out), + .p5(p5_FSM2out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/and-gate_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/and-gate_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..0ade96c --- /dev/null +++ b/examples/and-gate_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,79 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + a_P, + b_M, + t8, + out_M, + t7, + t6, + a_M, + b_P, + t5, + out_P); + + input clk; + input reset; + input a_P; + input b_M; + input t8; + output out_M; + input t7; + input t6; + input a_M; + input b_P; + input t5; + output out_P; + + wire e_out_M_FSM1out, e_out_P_FSM1out; // Regular output signals of FSM1 // + wire p3_FSM1out, p2_FSM1out, p7_FSM1out, p1_FSM1out, p6_FSM1out, p0_FSM1out, p4_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_out_M_FSM2out, e_out_P_FSM2out; // Regular output signals of FSM2 // + wire p3_FSM2out, p2_FSM2out, p7_FSM2out, p1_FSM2out, p6_FSM2out, p0_FSM2out, p5_FSM2out; // State Synchronisation output signals of FSM2 // + + assign out_M = e_out_M_FSM1out & e_out_M_FSM2out; + assign out_P = e_out_P_FSM1out & e_out_P_FSM2out; + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .a_P_(a_P), .a_P__p0_FSM2_TB(p0_FSM2out), + .t8_(t8), .t8__p5_FSM2_TB(p5_FSM2out), + .t7_(t7), .t7__p3_FSM2_TB(p3_FSM2out), + .t6_(t6), .t6__p2_FSM2_TB(p2_FSM2out), + .a_M_(a_M), .a_M__p0_FSM2_TB(p0_FSM2out), + .b_P_(b_P), + .t5_(t5), .t5__p2_FSM2_TB(p2_FSM2out), + .e_out_M(e_out_M_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), + .e_out_P(e_out_P_FSM1out), .e_out_P_p6_FSM2_TB(p6_FSM2out), + .p3(p3_FSM1out), + .p2(p2_FSM1out), + .p7(p7_FSM1out), + .p6(p6_FSM1out), + .p0(p0_FSM1out), + .p4(p4_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .a_P_(a_P), .a_P__p0_FSM1_TB(p0_FSM1out), + .b_M_(b_M), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), + .t6_(t6), .t6__p2_FSM1_TB(p2_FSM1out), + .a_M_(a_M), .a_M__p0_FSM1_TB(p0_FSM1out), + .t5_(t5), .t5__p4_FSM1_TB(p4_FSM1out), + .e_out_M(e_out_M_FSM2out), .e_out_M_p7_FSM1_TB(p7_FSM1out), + .e_out_P(e_out_P_FSM2out), .e_out_P_p6_FSM1_TB(p6_FSM1out), + .p3(p3_FSM2out), + .p2(p2_FSM2out), + .p7(p7_FSM2out), + .p6(p6_FSM2out), + .p0(p0_FSM2out), + .p5(p5_FSM2out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/and-gate_GN/and-gate.petrinet.GN.workcraft.g b/examples/and-gate_GN/and-gate.petrinet.GN.workcraft.g new file mode 100644 index 0000000..2efbedd --- /dev/null +++ b/examples/and-gate_GN/and-gate.petrinet.GN.workcraft.g @@ -0,0 +1,26 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.3 +.model andGATE +.inputs a_P a_M b_P b_M +.outputs out_P out_M +.internal t5 t6 t7 t8 +.graph +a_P p2 +a_M p3 +b_P p4 +b_M p5 +t5 p6 +t6 p6 +t7 p6 +t8 p7 +out_P p0 p1 +out_M p0 p1 +p0 a_M a_P +p1 b_M b_P +p2 t5 t6 +p3 t7 t8 +p4 t5 t7 +p5 t6 t8 +p6 out_P +p7 out_M +.marking {p0 p1} +.end diff --git a/examples/and-gate_GN/msfsms_tool_bm.log b/examples/and-gate_GN/msfsms_tool_bm.log new file mode 100644 index 0000000..d9248a7 --- /dev/null +++ b/examples/and-gate_GN/msfsms_tool_bm.log @@ -0,0 +1,283 @@ +--------------------------------------------------------------------------- +Benchmark: and-gate_GN/and-gate.petrinet.GN.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/and-gate_GN/and-gate.petrinet.GN.workcraft.g +INFO: Total Nodes : 18 +INFO: Total Transitions : 10 +INFO: Total Places : 8 +INFO: Total Edges : 26 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = p3, Type = Place (is Empty) + Predecessors: a_M[12][0] + Successors: t7[6][0], t8[3][3] +PT-Net [3][0]: Label = a_P, Type = Transition (is Input) + Predecessors: p0[9][2] + Successors: p2[3][1] +PT-Net [3][1]: Label = p2, Type = Place (is Empty) + Predecessors: a_P[3][0] + Successors: t5[12][3], t6[9][1] +PT-Net [3][2]: Label = b_M, Type = Transition (is Input) + Predecessors: p1[6][2] + Successors: p5[12][2] +PT-Net [3][3]: Label = t8, Type = Transition (is Input) + Predecessors: p3[0][0], p5[12][2] + Successors: p7[6][1] +PT-Net [3][4]: Label = out_M, Type = Transition (is Output) + Predecessors: p7[6][1] + Successors: p0[9][2], p1[6][2] +PT-Net [6][0]: Label = t7, Type = Transition (is Input) + Predecessors: p3[0][0], p4[15][0] + Successors: p6[9][0] +PT-Net [6][1]: Label = p7, Type = Place (is Empty) + Predecessors: t8[3][3] + Successors: out_M[3][4] +PT-Net [6][2]: Label = p1, Type = Place (is Marked) + Predecessors: out_P[12][4], out_M[3][4] + Successors: b_M[3][2], b_P[12][1] +PT-Net [9][0]: Label = p6, Type = Place (is Empty) + Predecessors: t5[12][3], t6[9][1], t7[6][0] + Successors: out_P[12][4] +PT-Net [9][1]: Label = t6, Type = Transition (is Input) + Predecessors: p2[3][1], p5[12][2] + Successors: p6[9][0] +PT-Net [9][2]: Label = p0, Type = Place (is Marked) + Predecessors: out_P[12][4], out_M[3][4] + Successors: a_M[12][0], a_P[3][0] +PT-Net [12][0]: Label = a_M, Type = Transition (is Input) + Predecessors: p0[9][2] + Successors: p3[0][0] +PT-Net [12][1]: Label = b_P, Type = Transition (is Input) + Predecessors: p1[6][2] + Successors: p4[15][0] +PT-Net [12][2]: Label = p5, Type = Place (is Empty) + Predecessors: b_M[3][2] + Successors: t6[9][1], t8[3][3] +PT-Net [12][3]: Label = t5, Type = Transition (is Input) + Predecessors: p2[3][1], p4[15][0] + Successors: p6[9][0] +PT-Net [12][4]: Label = out_P, Type = Transition (is Output) + Predecessors: p6[9][0] + Successors: p0[9][2], p1[6][2] +PT-Net [15][0]: Label = p4, Type = Place (is Empty) + Predecessors: b_P[12][1] + Successors: t5[12][3], t7[6][0] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #2 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 16, H-collapsed = 'false' *** +SC S-net (1,1): p3[0][0] +SC S-net (1,2): a_P[3][0] + Predecessor Place: p0(1,11)[9,2] + Successor Place: p2(1,3)[3,1] +SC S-net (1,3): p2[3][1] +SC S-net (1,4): t8[3][3] + Predecessor Place: p3(1,1)[0,0] + Successor Place: p7(1,7)[6,1] +SC S-net (1,5): out_M[3][4] + Predecessor Place: p7(1,7)[6,1] + Successor Place: p1(1,8)[6,2] +SC S-net (1,6): t7[6][0] + Predecessor Place: p3(1,1)[0,0] + Successor Place: p6(1,9)[9,0] +SC S-net (1,7): p7[6][1] +SC S-net (1,8): p1[6][2] +SC S-net (1,9): p6[9][0] +SC S-net (1,10): t6[9][1] + Predecessor Place: p2(1,3)[3,1] + Successor Place: p6(1,9)[9,0] +SC S-net (1,11): p0[9][2] +SC S-net (1,12): a_M[12][0] + Predecessor Place: p0(1,11)[9,2] + Successor Place: p3(1,1)[0,0] +SC S-net (1,13): b_P[12][1] + Predecessor Place: p1(1,8)[6,2] + Successor Place: p4(1,16)[15,0] +SC S-net (1,14): t5[12][3] + Predecessor Place: p4(1,16)[15,0] + Successor Place: p6(1,9)[9,0] +SC S-net (1,15): out_P[12][4] + Predecessor Place: p6(1,9)[9,0] + Successor Place: p0(1,11)[9,2] +SC S-net (1,16): p4[15][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 16, H-collapsed = 'false' *** +SC S-net (2,1): p3[0][0] +SC S-net (2,2): a_P[3][0] + Predecessor Place: p0(2,12)[9,2] + Successor Place: p2(2,3)[3,1] +SC S-net (2,3): p2[3][1] +SC S-net (2,4): b_M[3][2] + Predecessor Place: p1(2,9)[6,2] + Successor Place: p5(2,14)[12,2] +SC S-net (2,5): t8[3][3] + Predecessor Place: p5(2,14)[12,2] + Successor Place: p7(2,8)[6,1] +SC S-net (2,6): out_M[3][4] + Predecessor Place: p7(2,8)[6,1] + Successor Place: p0(2,12)[9,2] +SC S-net (2,7): t7[6][0] + Predecessor Place: p3(2,1)[0,0] + Successor Place: p6(2,10)[9,0] +SC S-net (2,8): p7[6][1] +SC S-net (2,9): p1[6][2] +SC S-net (2,10): p6[9][0] +SC S-net (2,11): t6[9][1] + Predecessor Place: p2(2,3)[3,1] + Successor Place: p6(2,10)[9,0] +SC S-net (2,12): p0[9][2] +SC S-net (2,13): a_M[12][0] + Predecessor Place: p0(2,12)[9,2] + Successor Place: p3(2,1)[0,0] +SC S-net (2,14): p5[12][2] +SC S-net (2,15): t5[12][3] + Predecessor Place: p2(2,3)[3,1] + Successor Place: p6(2,10)[9,0] +SC S-net (2,16): out_P[12][4] + Predecessor Place: p6(2,10)[9,0] + Successor Place: p1(2,9)[6,2] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #2 total). +INFO: P "p2"[3, 1] should NOT be a predecessor of T "t5"[12, 3] in S-Net #1. +INFO: P "p1"[6, 2] should NOT be a successor of T "out_P"[12, 4] in S-Net #1. +INFO: P "p0"[9, 2] should NOT be a successor of T "out_M"[3, 4] in S-Net #1. +INFO: P "p4"[15, 0] should NOT be a predecessor of T "t7"[6, 0] in S-Net #1. +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #2 total). +INFO: P "p3"[0, 0] should NOT be a predecessor of T "t8"[3, 3] in S-Net #2. +INFO: P "p1"[6, 2] should NOT be a successor of T "out_M"[3, 4] in S-Net #2. +INFO: P "p0"[9, 2] should NOT be a successor of T "out_P"[12, 4] in S-Net #2. +INFO: P "p5"[12, 2] should NOT be a predecessor of T "t6"[9, 1] in S-Net #2. +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 16, H-Collapsed = 'false' *** +FSM (1,1): Label = p3, Type = State (is Initially Inactive) + Successor(s): t7/(0,6) t8/(0,4) + Predecessor(s): a_M/(0,12) +FSM (1,2): Label = a_P/, Type = Trans. Function (is Input) + Successor(s): p2(0,3) + Predecessor(s): p0(0,11) +FSM (1,3): Label = p2, Type = State (is Initially Inactive) + Successor(s): t6/(0,10) + Predecessor(s): a_P/(0,2) +FSM (1,4): Label = t8/, Type = Trans. Function (is Input) + Successor(s): p7(0,7) + Predecessor(s): p3(0,1) +FSM (1,5): Label = e/out_M, Type = Trans. Function (is Output) + Successor(s): p1(0,8) + Predecessor(s): p7(0,7) +FSM (1,6): Label = t7/, Type = Trans. Function (is Input) + Successor(s): p6(0,9) + Predecessor(s): p3(0,1) +FSM (1,7): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/out_M(0,5) + Predecessor(s): t8/(0,4) +FSM (1,8): Label = p1, Type = State (is Initially Active) + Successor(s): b_P/(0,13) + Predecessor(s): e/out_M(0,5) +FSM (1,9): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/out_P(0,15) + Predecessor(s): t5/(0,14) t6/(0,10) t7/(0,6) +FSM (1,10): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p6(0,9) + Predecessor(s): p2(0,3) +FSM (1,11): Label = p0, Type = State (is Initially Active) + Successor(s): a_M/(0,12) a_P/(0,2) + Predecessor(s): e/out_P(0,15) +FSM (1,12): Label = a_M/, Type = Trans. Function (is Input) + Successor(s): p3(0,1) + Predecessor(s): p0(0,11) +FSM (1,13): Label = b_P/, Type = Trans. Function (is Input) + Successor(s): p4(0,16) + Predecessor(s): p1(0,8) +FSM (1,14): Label = t5/, Type = Trans. Function (is Input) + Successor(s): p6(0,9) + Predecessor(s): p4(0,16) +FSM (1,15): Label = e/out_P, Type = Trans. Function (is Output) + Successor(s): p0(0,11) + Predecessor(s): p6(0,9) +FSM (1,16): Label = p4, Type = State (is Initially Inactive) + Successor(s): t5/(0,14) + Predecessor(s): b_P/(0,13) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 16, H-Collapsed = 'false' *** +FSM (2,1): Label = p3, Type = State (is Initially Inactive) + Successor(s): t7/(1,7) + Predecessor(s): a_M/(1,13) +FSM (2,2): Label = a_P/, Type = Trans. Function (is Input) + Successor(s): p2(1,3) + Predecessor(s): p0(1,12) +FSM (2,3): Label = p2, Type = State (is Initially Inactive) + Successor(s): t5/(1,15) t6/(1,11) + Predecessor(s): a_P/(1,2) +FSM (2,4): Label = b_M/, Type = Trans. Function (is Input) + Successor(s): p5(1,14) + Predecessor(s): p1(1,9) +FSM (2,5): Label = t8/, Type = Trans. Function (is Input) + Successor(s): p7(1,8) + Predecessor(s): p5(1,14) +FSM (2,6): Label = e/out_M, Type = Trans. Function (is Output) + Successor(s): p0(1,12) + Predecessor(s): p7(1,8) +FSM (2,7): Label = t7/, Type = Trans. Function (is Input) + Successor(s): p6(1,10) + Predecessor(s): p3(1,1) +FSM (2,8): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/out_M(1,6) + Predecessor(s): t8/(1,5) +FSM (2,9): Label = p1, Type = State (is Initially Active) + Successor(s): b_M/(1,4) + Predecessor(s): e/out_P(1,16) +FSM (2,10): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/out_P(1,16) + Predecessor(s): t5/(1,15) t6/(1,11) t7/(1,7) +FSM (2,11): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p6(1,10) + Predecessor(s): p2(1,3) +FSM (2,12): Label = p0, Type = State (is Initially Active) + Successor(s): a_M/(1,13) a_P/(1,2) + Predecessor(s): e/out_M(1,6) +FSM (2,13): Label = a_M/, Type = Trans. Function (is Input) + Successor(s): p3(1,1) + Predecessor(s): p0(1,12) +FSM (2,14): Label = p5, Type = State (is Initially Inactive) + Successor(s): t8/(1,5) + Predecessor(s): b_M/(1,4) +FSM (2,15): Label = t5/, Type = Trans. Function (is Input) + Successor(s): p6(1,10) + Predecessor(s): p2(1,3) +FSM (2,16): Label = e/out_P, Type = Trans. Function (is Output) + Successor(s): p1(1,9) + Predecessor(s): p6(1,10) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +WARNING: Multiple initial active states for FSM(1), continuing... +WARNING: Multiple initial active states for FSM(2), continuing... +WARNING: Multiple Active states for FSMs: |#1|#2| +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +WARNING: Multiple initial active states for FSM(1), continuing... +WARNING: Multiple initial active states for FSM(2), continuing... +WARNING: Multiple Active states for FSMs: |#1|#2| +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +WARNING: Multiple initial active states for FSM(1), continuing... +WARNING: Multiple initial active states for FSM(2), continuing... +WARNING: Multiple Active states for FSMs: |#1|#2| +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/converta_MG/AsyncMSFSMs/fsm_afsm.afsm b/examples/converta_MG/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..01c55b2 --- /dev/null +++ b/examples/converta_MG/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,49 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p7: e_x_PLUS e_x_PLUS_p7_FSM2_TB e_x_PLUS_p7_FSM3_TB p14 +p10: e_Ao_MINUS e_Ao_MINUS_p10_FSM2_TB p3 +p9: Ai_PLUSa_ Ai_PLUSa__p9_FSM2_TB Ai_PLUSa__p9_FSM3_TB p12 +p12: e_x_MINUS e_x_MINUS_p12_FSM2_TB e_x_MINUS_p12_FSM3_TB p15 +p0: e_Ro_PLUS e_Ro_PLUS_p0_FSM2_TB e_Ro_PLUS_p13_FSM3_TB p4 +p1: e_Ro_PLUSa e_Ro_PLUSa_p8_FSM2_TB e_Ro_PLUSa_p1_FSM3_TB p9 +p14: e_Ro_MINUS e_Ro_MINUS_p14_FSM2_TB e_Ro_MINUS_p14_FSM3_TB p5 +p2: Ri_MINUS_ Ri_MINUS__p2_FSM3_TB p1 +p15: e_Ro_MINUSa e_Ro_MINUSa_p15_FSM2_TB e_Ro_MINUSa_p15_FSM3_TB p10 +p3*: Ri_PLUS_ Ri_PLUS__p3_FSM2_TB p0 +p4: Ai_PLUS_ Ai_PLUS__p4_FSM2_TB Ai_PLUS__p4_FSM3_TB p7 +p5: e_Ao_PLUS e_Ao_PLUS_p5_FSM3_TB p2 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p7: e_x_PLUS e_x_PLUS_p7_FSM1_TB e_x_PLUS_p7_FSM3_TB p14 +p10: e_Ao_MINUS e_Ao_MINUS_p10_FSM1_TB p3 +p8: e_Ro_PLUSa e_Ro_PLUSa_p1_FSM1_TB e_Ro_PLUSa_p1_FSM3_TB p9 +p9: Ai_PLUSa_ Ai_PLUSa__p9_FSM1_TB Ai_PLUSa__p9_FSM3_TB p12 +p12: e_x_MINUS e_x_MINUS_p12_FSM1_TB e_x_MINUS_p12_FSM3_TB p15 +p0: e_Ro_PLUS e_Ro_PLUS_p0_FSM1_TB e_Ro_PLUS_p13_FSM3_TB p4 +p14: e_Ro_MINUS e_Ro_MINUS_p14_FSM1_TB e_Ro_MINUS_p14_FSM3_TB p6 +p15: e_Ro_MINUSa e_Ro_MINUSa_p15_FSM1_TB e_Ro_MINUSa_p15_FSM3_TB p10 +p3*: Ri_PLUS_ Ri_PLUS__p3_FSM1_TB p0 +p4: Ai_PLUS_ Ai_PLUS__p4_FSM1_TB Ai_PLUS__p4_FSM3_TB p7 +p6: Ai_MINUS_ p8 +### End of FSM #02 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#03 Declaration ### +p7: e_x_PLUS e_x_PLUS_p7_FSM1_TB e_x_PLUS_p7_FSM2_TB p14 +p11: Ai_MINUSa_ p13 +p9: Ai_PLUSa_ Ai_PLUSa__p9_FSM1_TB Ai_PLUSa__p9_FSM2_TB p12 +p12: e_x_MINUS e_x_MINUS_p12_FSM1_TB e_x_MINUS_p12_FSM2_TB p15 +p13*: e_Ro_PLUS e_Ro_PLUS_p0_FSM1_TB e_Ro_PLUS_p0_FSM2_TB p4 +p1: e_Ro_PLUSa e_Ro_PLUSa_p1_FSM1_TB e_Ro_PLUSa_p8_FSM2_TB p9 +p14: e_Ro_MINUS e_Ro_MINUS_p14_FSM1_TB e_Ro_MINUS_p14_FSM2_TB p5 +p2: Ri_MINUS_ Ri_MINUS__p2_FSM1_TB p1 +p15: e_Ro_MINUSa e_Ro_MINUSa_p15_FSM1_TB e_Ro_MINUSa_p15_FSM2_TB p11 +p4: Ai_PLUS_ Ai_PLUS__p4_FSM1_TB Ai_PLUS__p4_FSM2_TB p7 +p5: e_Ao_PLUS e_Ao_PLUS_p5_FSM1_TB p2 +### End of FSM #03 Declaration ### + diff --git a/examples/converta_MG/AsyncMSFSMs/msfsms_afsm.v b/examples/converta_MG/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..bd5bfe1 --- /dev/null +++ b/examples/converta_MG/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,130 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + x_MINUS, + Ro_PLUSa, + Ao_PLUS, + Ri_MINUS, + Ai_PLUS, + Ai_MINUS, + Ro_PLUS, + x_PLUS, + Ri_PLUS, + Ro_MINUS, + Ao_MINUS, + Ro_MINUSa, + Ai_PLUSa, + Ai_MINUSa); + + input reset; + output x_MINUS; + output Ro_PLUSa; + output Ao_PLUS; + input Ri_MINUS; + input Ai_PLUS; + input Ai_MINUS; + output Ro_PLUS; + output x_PLUS; + input Ri_PLUS; + output Ro_MINUS; + output Ao_MINUS; + output Ro_MINUSa; + input Ai_PLUSa; + input Ai_MINUSa; + + wire e_x_MINUS_FSM1out, e_Ro_PLUSa_FSM1out, e_Ao_PLUS_FSM1out, e_Ro_PLUS_FSM1out, e_x_PLUS_FSM1out, e_Ro_MINUS_FSM1out, e_Ao_MINUS_FSM1out, e_Ro_MINUSa_FSM1out; // Regular output signals of FSM1 // + wire p7_FSM1out, p10_FSM1out, p9_FSM1out, p12_FSM1out, p0_FSM1out, p1_FSM1out, p14_FSM1out, p2_FSM1out, p15_FSM1out, p3_FSM1out, p4_FSM1out, p5_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_x_MINUS_FSM2out, e_Ro_PLUSa_FSM2out, e_Ro_PLUS_FSM2out, e_x_PLUS_FSM2out, e_Ro_MINUS_FSM2out, e_Ao_MINUS_FSM2out, e_Ro_MINUSa_FSM2out; // Regular output signals of FSM2 // + wire p7_FSM2out, p10_FSM2out, p8_FSM2out, p9_FSM2out, p12_FSM2out, p0_FSM2out, p14_FSM2out, p15_FSM2out, p3_FSM2out, p4_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_x_MINUS_FSM3out, e_Ro_PLUSa_FSM3out, e_Ao_PLUS_FSM3out, e_Ro_PLUS_FSM3out, e_x_PLUS_FSM3out, e_Ro_MINUS_FSM3out, e_Ro_MINUSa_FSM3out; // Regular output signals of FSM3 // + wire p7_FSM3out, p11_FSM3out, p9_FSM3out, p12_FSM3out, p13_FSM3out, p1_FSM3out, p14_FSM3out, p2_FSM3out, p15_FSM3out, p4_FSM3out, p5_FSM3out; // State Synchronisation output signals of FSM3 // + + assign x_MINUS = e_x_MINUS_FSM1out & e_x_MINUS_FSM2out & e_x_MINUS_FSM3out; + assign Ro_PLUSa = e_Ro_PLUSa_FSM1out & e_Ro_PLUSa_FSM2out & e_Ro_PLUSa_FSM3out; + assign Ao_PLUS = e_Ao_PLUS_FSM1out & e_Ao_PLUS_FSM3out; + assign Ro_PLUS = e_Ro_PLUS_FSM1out & e_Ro_PLUS_FSM2out & e_Ro_PLUS_FSM3out; + assign x_PLUS = e_x_PLUS_FSM1out & e_x_PLUS_FSM2out & e_x_PLUS_FSM3out; + assign Ro_MINUS = e_Ro_MINUS_FSM1out & e_Ro_MINUS_FSM2out & e_Ro_MINUS_FSM3out; + assign Ao_MINUS = e_Ao_MINUS_FSM1out & e_Ao_MINUS_FSM2out; + assign Ro_MINUSa = e_Ro_MINUSa_FSM1out & e_Ro_MINUSa_FSM2out & e_Ro_MINUSa_FSM3out; + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p2_FSM3_TB(p2_FSM3out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM2_TB(p4_FSM2out), .Ai_PLUS__p4_FSM3_TB(p4_FSM3out), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p3_FSM2_TB(p3_FSM2out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM2_TB(p9_FSM2out), .Ai_PLUSa__p9_FSM3_TB(p9_FSM3out), + .e_x_MINUS(p12_FSM1out), .e_x_MINUS_p12_FSM2_TB(p12_FSM2out), .e_x_MINUS_p12_FSM3_TB(p12_FSM3out), + .e_Ro_PLUSa(p1_FSM1out), .e_Ro_PLUSa_p8_FSM2_TB(p8_FSM2out), .e_Ro_PLUSa_p1_FSM3_TB(p1_FSM3out), + .e_Ao_PLUS(p5_FSM1out), .e_Ao_PLUS_p5_FSM3_TB(p5_FSM3out), + .e_Ro_PLUS(p0_FSM1out), .e_Ro_PLUS_p0_FSM2_TB(p0_FSM2out), .e_Ro_PLUS_p13_FSM3_TB(p13_FSM3out), + .e_x_PLUS(p7_FSM1out), .e_x_PLUS_p7_FSM2_TB(p7_FSM2out), .e_x_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(p14_FSM1out), .e_Ro_MINUS_p14_FSM2_TB(p14_FSM2out), .e_Ro_MINUS_p14_FSM3_TB(p14_FSM3out), + .e_Ao_MINUS(p10_FSM1out), .e_Ao_MINUS_p10_FSM2_TB(p10_FSM2out), + .e_Ro_MINUSa(p15_FSM1out), .e_Ro_MINUSa_p15_FSM2_TB(p15_FSM2out), .e_Ro_MINUSa_p15_FSM3_TB(p15_FSM3out), + .e/x_MINUS(e/x_MINUS_FSM1out), + .e/Ro_PLUSa(e/Ro_PLUSa_FSM1out), + .e/Ao_PLUS(e/Ao_PLUS_FSM1out), + .e/Ro_PLUS(e/Ro_PLUS_FSM1out), + .e/x_PLUS(e/x_PLUS_FSM1out), + .e/Ro_MINUS(e/Ro_MINUS_FSM1out), + .e/Ao_MINUS(e/Ao_MINUS_FSM1out), + .e/Ro_MINUSa(e/Ro_MINUSa_FSM1out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM1_TB(p4_FSM1out), .Ai_PLUS__p4_FSM3_TB(p4_FSM3out), + .Ai_MINUS_(Ai_MINUS), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p3_FSM1_TB(p3_FSM1out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM1_TB(p9_FSM1out), .Ai_PLUSa__p9_FSM3_TB(p9_FSM3out), + .e_x_MINUS(p12_FSM2out), .e_x_MINUS_p12_FSM1_TB(p12_FSM1out), .e_x_MINUS_p12_FSM3_TB(p12_FSM3out), + .e_Ro_PLUSa(p8_FSM2out), .e_Ro_PLUSa_p1_FSM1_TB(p1_FSM1out), .e_Ro_PLUSa_p1_FSM3_TB(p1_FSM3out), + .e_Ro_PLUS(p0_FSM2out), .e_Ro_PLUS_p0_FSM1_TB(p0_FSM1out), .e_Ro_PLUS_p13_FSM3_TB(p13_FSM3out), + .e_x_PLUS(p7_FSM2out), .e_x_PLUS_p7_FSM1_TB(p7_FSM1out), .e_x_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(p14_FSM2out), .e_Ro_MINUS_p14_FSM1_TB(p14_FSM1out), .e_Ro_MINUS_p14_FSM3_TB(p14_FSM3out), + .e_Ao_MINUS(p10_FSM2out), .e_Ao_MINUS_p10_FSM1_TB(p10_FSM1out), + .e_Ro_MINUSa(p15_FSM2out), .e_Ro_MINUSa_p15_FSM1_TB(p15_FSM1out), .e_Ro_MINUSa_p15_FSM3_TB(p15_FSM3out), + .e/x_MINUS(e/x_MINUS_FSM2out), + .e/Ro_PLUSa(e/Ro_PLUSa_FSM2out), + .e/Ro_PLUS(e/Ro_PLUS_FSM2out), + .e/x_PLUS(e/x_PLUS_FSM2out), + .e/Ro_MINUS(e/Ro_MINUS_FSM2out), + .e/Ao_MINUS(e/Ao_MINUS_FSM2out), + .e/Ro_MINUSa(e/Ro_MINUSa_FSM2out) + ); + + + fsm_afsm_03 fsm_afsm_03_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p2_FSM1_TB(p2_FSM1out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM1_TB(p4_FSM1out), .Ai_PLUS__p4_FSM2_TB(p4_FSM2out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM1_TB(p9_FSM1out), .Ai_PLUSa__p9_FSM2_TB(p9_FSM2out), + .Ai_MINUSa_(Ai_MINUSa), + .e_x_MINUS(p12_FSM3out), .e_x_MINUS_p12_FSM1_TB(p12_FSM1out), .e_x_MINUS_p12_FSM2_TB(p12_FSM2out), + .e_Ro_PLUSa(p1_FSM3out), .e_Ro_PLUSa_p1_FSM1_TB(p1_FSM1out), .e_Ro_PLUSa_p8_FSM2_TB(p8_FSM2out), + .e_Ao_PLUS(p5_FSM3out), .e_Ao_PLUS_p5_FSM1_TB(p5_FSM1out), + .e_Ro_PLUS(p13_FSM3out), .e_Ro_PLUS_p0_FSM1_TB(p0_FSM1out), .e_Ro_PLUS_p0_FSM2_TB(p0_FSM2out), + .e_x_PLUS(p7_FSM3out), .e_x_PLUS_p7_FSM1_TB(p7_FSM1out), .e_x_PLUS_p7_FSM2_TB(p7_FSM2out), + .e_Ro_MINUS(p14_FSM3out), .e_Ro_MINUS_p14_FSM1_TB(p14_FSM1out), .e_Ro_MINUS_p14_FSM2_TB(p14_FSM2out), + .e_Ro_MINUSa(p15_FSM3out), .e_Ro_MINUSa_p15_FSM1_TB(p15_FSM1out), .e_Ro_MINUSa_p15_FSM2_TB(p15_FSM2out), + .e/x_MINUS(e/x_MINUS_FSM3out), + .e/Ro_PLUSa(e/Ro_PLUSa_FSM3out), + .e/Ao_PLUS(e/Ao_PLUS_FSM3out), + .e/Ro_PLUS(e/Ro_PLUS_FSM3out), + .e/x_PLUS(e/x_PLUS_FSM3out), + .e/Ro_MINUS(e/Ro_MINUS_FSM3out), + .e/Ro_MINUSa(e/Ro_MINUSa_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/converta_MG/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/converta_MG/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..4e9dce3 --- /dev/null +++ b/examples/converta_MG/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,955 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + Ri_MINUS_, Ri_MINUS__p2_FSM3_TB, + Ai_PLUS_, Ai_PLUS__p4_FSM2_TB, Ai_PLUS__p4_FSM3_TB, + Ri_PLUS_, Ri_PLUS__p3_FSM2_TB, + Ai_PLUSa_, Ai_PLUSa__p9_FSM2_TB, Ai_PLUSa__p9_FSM3_TB, + e_x_MINUS, e_x_MINUS_p12_FSM2_TB, e_x_MINUS_p12_FSM3_TB, + e_Ro_PLUSa, e_Ro_PLUSa_p8_FSM2_TB, e_Ro_PLUSa_p1_FSM3_TB, + e_Ao_PLUS, e_Ao_PLUS_p5_FSM3_TB, + e_Ro_PLUS, e_Ro_PLUS_p0_FSM2_TB, e_Ro_PLUS_p13_FSM3_TB, + e_x_PLUS, e_x_PLUS_p7_FSM2_TB, e_x_PLUS_p7_FSM3_TB, + e_Ro_MINUS, e_Ro_MINUS_p14_FSM2_TB, e_Ro_MINUS_p14_FSM3_TB, + e_Ao_MINUS, e_Ao_MINUS_p10_FSM2_TB, + e_Ro_MINUSa, e_Ro_MINUSa_p15_FSM2_TB, e_Ro_MINUSa_p15_FSM3_TB, + p7, + p10, + p9, + p12, + p0, + p1, + p14, + p2, + p15, + p3, + p4, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_MINUS_; + input Ai_PLUS_; + input Ri_PLUS_; + input Ai_PLUSa_; + // Transition Barrier Inputs for input Signals // + input Ri_MINUS__p2_FSM3_TB; + input Ai_PLUS__p4_FSM2_TB, Ai_PLUS__p4_FSM3_TB; + input Ri_PLUS__p3_FSM2_TB; + input Ai_PLUSa__p9_FSM2_TB, Ai_PLUSa__p9_FSM3_TB; + + // Regular output Signals // + output e_x_MINUS; + output e_Ro_PLUSa; + output e_Ao_PLUS; + output e_Ro_PLUS; + output e_x_PLUS; + output e_Ro_MINUS; + output e_Ao_MINUS; + output e_Ro_MINUSa; + // Transition Barrier outputs for output Signals // + input e_x_MINUS_p12_FSM2_TB, e_x_MINUS_p12_FSM3_TB; + input e_Ro_PLUSa_p8_FSM2_TB, e_Ro_PLUSa_p1_FSM3_TB; + input e_Ao_PLUS_p5_FSM3_TB; + input e_Ro_PLUS_p0_FSM2_TB, e_Ro_PLUS_p13_FSM3_TB; + input e_x_PLUS_p7_FSM2_TB, e_x_PLUS_p7_FSM3_TB; + input e_Ro_MINUS_p14_FSM2_TB, e_Ro_MINUS_p14_FSM3_TB; + input e_Ao_MINUS_p10_FSM2_TB; + input e_Ro_MINUSa_p15_FSM2_TB, e_Ro_MINUSa_p15_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p10; + output p9; + output p12; + output p0; + output p1; + output p14; + output p2; + output p15; + output p3; + output p4; + output p5; + + reg e_x_MINUS; + reg e_Ro_PLUSa; + reg e_Ao_PLUS; + reg e_Ro_PLUS; + reg e_x_PLUS; + reg e_Ro_MINUS; + reg e_Ao_MINUS; + reg e_Ro_MINUSa; + wire p7; + wire p10; + wire p9; + wire p12; + wire p0; + wire p1; + wire p14; + wire p2; + wire p15; + wire p3; + wire p4; + wire p5; + + wire Ri_MINUS__TB_sync; + wire Ai_PLUS__TB_sync; + wire Ri_PLUS__TB_sync; + wire Ai_PLUSa__TB_sync; + wire e_x_MINUS_TB_sync; + wire e_Ro_PLUSa_TB_sync; + wire e_Ao_PLUS_TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_x_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + wire e_Ro_MINUSa_TB_sync; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p2_FSM3_TB; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p4_FSM2_TB & Ai_PLUS__p4_FSM3_TB; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p3_FSM2_TB; + assign Ai_PLUSa__TB_sync = Ai_PLUSa_ & Ai_PLUSa__p9_FSM2_TB & Ai_PLUSa__p9_FSM3_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p12_FSM2_TB & e_x_MINUS_p12_FSM3_TB; + assign e_Ro_PLUSa_TB_sync = e_Ro_PLUSa_p8_FSM2_TB & e_Ro_PLUSa_p1_FSM3_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p5_FSM3_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p0_FSM2_TB & e_Ro_PLUS_p13_FSM3_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p7_FSM2_TB & e_x_PLUS_p7_FSM3_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p14_FSM2_TB & e_Ro_MINUS_p14_FSM3_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p10_FSM2_TB; + assign e_Ro_MINUSa_TB_sync = e_Ro_MINUSa_p15_FSM2_TB & e_Ro_MINUSa_p15_FSM3_TB; + + parameter p7_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p10_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p10_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p9_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p9_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p12_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p12_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p0_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p0_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p1_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p1_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p14_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p14_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p2_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p2_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p15_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p15_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p3_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p3_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p4_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p4_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p5_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p5_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p3_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b1; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p10 = (state == p10_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_MINUS__TB_sync or Ai_PLUS__TB_sync or Ri_PLUS__TB_sync or Ai_PLUSa__TB_sync or e_x_MINUS_TB_sync or e_Ro_PLUSa_TB_sync or e_Ao_PLUS_TB_sync or e_Ro_PLUS_TB_sync or e_x_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_MINUS_TB_sync or e_Ro_MINUSa_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_MINUS = 1'b0; + e_Ro_PLUSa = 1'b0; + e_Ao_PLUS = 1'b0; + e_Ro_PLUS = 1'b0; + e_x_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_MINUS = 1'b0; + e_Ro_MINUSa = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p7_1HOT_ENCODING: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + // next_state = p14_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p10_1HOT_ENCODING: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[9] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p9_1HOT_ENCODING: // + begin + if (Ai_PLUSa__TB_sync) + begin + // next_state = p12_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p12_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[8] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p0_1HOT_ENCODING: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[10] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p1_1HOT_ENCODING: // + begin + if (e_Ro_PLUSa_TB_sync) + begin + e_Ro_PLUSa = 1'b1; + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxxx1xxxxxx: // p14_1HOT_ENCODING: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[11] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p2_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p15_1HOT_ENCODING: // + begin + if (e_Ro_MINUSa_TB_sync) + begin + e_Ro_MINUSa = 1'b1; + // next_state = p10_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p3_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[4] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p4_1HOT_ENCODING: // + begin + if (Ai_PLUS__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p5_1HOT_ENCODING: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[7] = 1'b1; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + Ai_PLUS_, Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM3_TB, + Ai_MINUS_, + Ri_PLUS_, Ri_PLUS__p3_FSM1_TB, + Ai_PLUSa_, Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM3_TB, + e_x_MINUS, e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM3_TB, + e_Ro_PLUSa, e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p1_FSM3_TB, + e_Ro_PLUS, e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p13_FSM3_TB, + e_x_PLUS, e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM3_TB, + e_Ro_MINUS, e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM3_TB, + e_Ao_MINUS, e_Ao_MINUS_p10_FSM1_TB, + e_Ro_MINUSa, e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM3_TB, + p7, + p10, + p8, + p9, + p12, + p0, + p14, + p15, + p3, + p4 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ai_PLUS_; + input Ai_MINUS_; + input Ri_PLUS_; + input Ai_PLUSa_; + // Transition Barrier Inputs for input Signals // + input Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM3_TB; + input Ri_PLUS__p3_FSM1_TB; + input Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM3_TB; + + // Regular output Signals // + output e_x_MINUS; + output e_Ro_PLUSa; + output e_Ro_PLUS; + output e_x_PLUS; + output e_Ro_MINUS; + output e_Ao_MINUS; + output e_Ro_MINUSa; + // Transition Barrier outputs for output Signals // + input e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM3_TB; + input e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p1_FSM3_TB; + input e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p13_FSM3_TB; + input e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM3_TB; + input e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM3_TB; + input e_Ao_MINUS_p10_FSM1_TB; + input e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p10; + output p8; + output p9; + output p12; + output p0; + output p14; + output p15; + output p3; + output p4; + + reg e_x_MINUS; + reg e_Ro_PLUSa; + reg e_Ro_PLUS; + reg e_x_PLUS; + reg e_Ro_MINUS; + reg e_Ao_MINUS; + reg e_Ro_MINUSa; + wire p7; + wire p10; + wire p8; + wire p9; + wire p12; + wire p0; + wire p14; + wire p15; + wire p3; + wire p4; + + wire Ai_PLUS__TB_sync; + wire Ri_PLUS__TB_sync; + wire Ai_PLUSa__TB_sync; + wire e_x_MINUS_TB_sync; + wire e_Ro_PLUSa_TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_x_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + wire e_Ro_MINUSa_TB_sync; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p4_FSM1_TB & Ai_PLUS__p4_FSM3_TB; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p3_FSM1_TB; + assign Ai_PLUSa__TB_sync = Ai_PLUSa_ & Ai_PLUSa__p9_FSM1_TB & Ai_PLUSa__p9_FSM3_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p12_FSM1_TB & e_x_MINUS_p12_FSM3_TB; + assign e_Ro_PLUSa_TB_sync = e_Ro_PLUSa_p1_FSM1_TB & e_Ro_PLUSa_p1_FSM3_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p0_FSM1_TB & e_Ro_PLUS_p13_FSM3_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p7_FSM1_TB & e_x_PLUS_p7_FSM3_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p14_FSM1_TB & e_Ro_MINUS_p14_FSM3_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p10_FSM1_TB; + assign e_Ro_MINUSa_TB_sync = e_Ro_MINUSa_p15_FSM1_TB & e_Ro_MINUSa_p15_FSM3_TB; + + parameter p7_1HOT_ENCODING = 11'd1; // 11'b00000000001 // + parameter p7_1HOT_CASEX_ENCODING = 11'bxxxxxxxxxx1; // 11'b00000000001 // + parameter p10_1HOT_ENCODING = 11'd2; // 11'b00000000010 // + parameter p10_1HOT_CASEX_ENCODING = 11'bxxxxxxxxx1x; // 11'b00000000010 // + parameter p8_1HOT_ENCODING = 11'd4; // 11'b00000000100 // + parameter p8_1HOT_CASEX_ENCODING = 11'bxxxxxxxx1xx; // 11'b00000000100 // + parameter p9_1HOT_ENCODING = 11'd8; // 11'b00000001000 // + parameter p9_1HOT_CASEX_ENCODING = 11'bxxxxxxx1xxx; // 11'b00000001000 // + parameter p12_1HOT_ENCODING = 11'd16; // 11'b00000010000 // + parameter p12_1HOT_CASEX_ENCODING = 11'bxxxxxx1xxxx; // 11'b00000010000 // + parameter p0_1HOT_ENCODING = 11'd32; // 11'b00000100000 // + parameter p0_1HOT_CASEX_ENCODING = 11'bxxxxx1xxxxx; // 11'b00000100000 // + parameter p14_1HOT_ENCODING = 11'd64; // 11'b00001000000 // + parameter p14_1HOT_CASEX_ENCODING = 11'bxxxx1xxxxxx; // 11'b00001000000 // + parameter p15_1HOT_ENCODING = 11'd128; // 11'b00010000000 // + parameter p15_1HOT_CASEX_ENCODING = 11'bxxx1xxxxxxx; // 11'b00010000000 // + parameter p3_1HOT_ENCODING = 11'd256; // 11'b00100000000 // + parameter p3_1HOT_CASEX_ENCODING = 11'bxx1xxxxxxxx; // 11'b00100000000 // + parameter p4_1HOT_ENCODING = 11'd512; // 11'b01000000000 // + parameter p4_1HOT_CASEX_ENCODING = 11'bx1xxxxxxxxx; // 11'b01000000000 // + parameter p6_1HOT_ENCODING = 11'd1024; // 11'b10000000000 // + parameter p6_1HOT_CASEX_ENCODING = 11'b1xxxxxxxxxx; // 11'b10000000000 // + + reg [10 : 0] state; + reg [10 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p3_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b1; + state[9] <= 1'b0; + state[10] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p10 = (state == p10_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ai_PLUS__TB_sync or Ai_MINUS_ or Ri_PLUS__TB_sync or Ai_PLUSa__TB_sync or e_x_MINUS_TB_sync or e_Ro_PLUSa_TB_sync or e_Ro_PLUS_TB_sync or e_x_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_MINUS_TB_sync or e_Ro_MINUSa_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_MINUS = 1'b0; + e_Ro_PLUSa = 1'b0; + e_Ro_PLUS = 1'b0; + e_x_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_MINUS = 1'b0; + e_Ro_MINUSa = 1'b0; + + casex (state) + 11'bxxxxxxxxxx1: // p7_1HOT_ENCODING: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + // next_state = p14_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[6] = 1'b1; + end + end + + 11'bxxxxxxxxx1x: // p10_1HOT_ENCODING: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[8] = 1'b1; + end + end + + 11'bxxxxxxxx1xx: // p8_1HOT_ENCODING: // + begin + if (e_Ro_PLUSa_TB_sync) + begin + e_Ro_PLUSa = 1'b1; + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[3] = 1'b1; + end + end + + 11'bxxxxxxx1xxx: // p9_1HOT_ENCODING: // + begin + if (Ai_PLUSa__TB_sync) + begin + // next_state = p12_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[4] = 1'b1; + end + end + + 11'bxxxxxx1xxxx: // p12_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[7] = 1'b1; + end + end + + 11'bxxxxx1xxxxx: // p0_1HOT_ENCODING: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[9] = 1'b1; + end + end + + 11'bxxxx1xxxxxx: // p14_1HOT_ENCODING: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[10] = 1'b1; + end + end + + 11'bxxx1xxxxxxx: // p15_1HOT_ENCODING: // + begin + if (e_Ro_MINUSa_TB_sync) + begin + e_Ro_MINUSa = 1'b1; + // next_state = p10_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[1] = 1'b1; + end + end + + 11'bxx1xxxxxxxx: // p3_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[5] = 1'b1; + end + end + + 11'bx1xxxxxxxxx: // p4_1HOT_ENCODING: // + begin + if (Ai_PLUS__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[0] = 1'b1; + end + end + + 11'b1xxxxxxxxxx: // p6_1HOT_ENCODING: // + begin + if (Ai_MINUS_) + begin + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 11'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_03 ( + clk, + reset, + Ri_MINUS_, Ri_MINUS__p2_FSM1_TB, + Ai_PLUS_, Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM2_TB, + Ai_PLUSa_, Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM2_TB, + Ai_MINUSa_, + e_x_MINUS, e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM2_TB, + e_Ro_PLUSa, e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p8_FSM2_TB, + e_Ao_PLUS, e_Ao_PLUS_p5_FSM1_TB, + e_Ro_PLUS, e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p0_FSM2_TB, + e_x_PLUS, e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM2_TB, + e_Ro_MINUS, e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM2_TB, + e_Ro_MINUSa, e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM2_TB, + p7, + p9, + p12, + p13, + p1, + p14, + p2, + p15, + p4, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_MINUS_; + input Ai_PLUS_; + input Ai_PLUSa_; + input Ai_MINUSa_; + // Transition Barrier Inputs for input Signals // + input Ri_MINUS__p2_FSM1_TB; + input Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM2_TB; + input Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM2_TB; + + // Regular output Signals // + output e_x_MINUS; + output e_Ro_PLUSa; + output e_Ao_PLUS; + output e_Ro_PLUS; + output e_x_PLUS; + output e_Ro_MINUS; + output e_Ro_MINUSa; + // Transition Barrier outputs for output Signals // + input e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM2_TB; + input e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p8_FSM2_TB; + input e_Ao_PLUS_p5_FSM1_TB; + input e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p0_FSM2_TB; + input e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM2_TB; + input e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM2_TB; + input e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p9; + output p12; + output p13; + output p1; + output p14; + output p2; + output p15; + output p4; + output p5; + + reg e_x_MINUS; + reg e_Ro_PLUSa; + reg e_Ao_PLUS; + reg e_Ro_PLUS; + reg e_x_PLUS; + reg e_Ro_MINUS; + reg e_Ro_MINUSa; + wire p7; + wire p9; + wire p12; + wire p13; + wire p1; + wire p14; + wire p2; + wire p15; + wire p4; + wire p5; + + wire Ri_MINUS__TB_sync; + wire Ai_PLUS__TB_sync; + wire Ai_PLUSa__TB_sync; + wire e_x_MINUS_TB_sync; + wire e_Ro_PLUSa_TB_sync; + wire e_Ao_PLUS_TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_x_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ro_MINUSa_TB_sync; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p2_FSM1_TB; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p4_FSM1_TB & Ai_PLUS__p4_FSM2_TB; + assign Ai_PLUSa__TB_sync = Ai_PLUSa_ & Ai_PLUSa__p9_FSM1_TB & Ai_PLUSa__p9_FSM2_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p12_FSM1_TB & e_x_MINUS_p12_FSM2_TB; + assign e_Ro_PLUSa_TB_sync = e_Ro_PLUSa_p1_FSM1_TB & e_Ro_PLUSa_p8_FSM2_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p5_FSM1_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p0_FSM1_TB & e_Ro_PLUS_p0_FSM2_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p7_FSM1_TB & e_x_PLUS_p7_FSM2_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p14_FSM1_TB & e_Ro_MINUS_p14_FSM2_TB; + assign e_Ro_MINUSa_TB_sync = e_Ro_MINUSa_p15_FSM1_TB & e_Ro_MINUSa_p15_FSM2_TB; + + parameter p7_1HOT_ENCODING = 11'd1; // 11'b00000000001 // + parameter p7_1HOT_CASEX_ENCODING = 11'bxxxxxxxxxx1; // 11'b00000000001 // + parameter p11_1HOT_ENCODING = 11'd2; // 11'b00000000010 // + parameter p11_1HOT_CASEX_ENCODING = 11'bxxxxxxxxx1x; // 11'b00000000010 // + parameter p9_1HOT_ENCODING = 11'd4; // 11'b00000000100 // + parameter p9_1HOT_CASEX_ENCODING = 11'bxxxxxxxx1xx; // 11'b00000000100 // + parameter p12_1HOT_ENCODING = 11'd8; // 11'b00000001000 // + parameter p12_1HOT_CASEX_ENCODING = 11'bxxxxxxx1xxx; // 11'b00000001000 // + parameter p13_1HOT_ENCODING = 11'd16; // 11'b00000010000 // + parameter p13_1HOT_CASEX_ENCODING = 11'bxxxxxx1xxxx; // 11'b00000010000 // + parameter p1_1HOT_ENCODING = 11'd32; // 11'b00000100000 // + parameter p1_1HOT_CASEX_ENCODING = 11'bxxxxx1xxxxx; // 11'b00000100000 // + parameter p14_1HOT_ENCODING = 11'd64; // 11'b00001000000 // + parameter p14_1HOT_CASEX_ENCODING = 11'bxxxx1xxxxxx; // 11'b00001000000 // + parameter p2_1HOT_ENCODING = 11'd128; // 11'b00010000000 // + parameter p2_1HOT_CASEX_ENCODING = 11'bxxx1xxxxxxx; // 11'b00010000000 // + parameter p15_1HOT_ENCODING = 11'd256; // 11'b00100000000 // + parameter p15_1HOT_CASEX_ENCODING = 11'bxx1xxxxxxxx; // 11'b00100000000 // + parameter p4_1HOT_ENCODING = 11'd512; // 11'b01000000000 // + parameter p4_1HOT_CASEX_ENCODING = 11'bx1xxxxxxxxx; // 11'b01000000000 // + parameter p5_1HOT_ENCODING = 11'd1024; // 11'b10000000000 // + parameter p5_1HOT_CASEX_ENCODING = 11'b1xxxxxxxxxx; // 11'b10000000000 // + + reg [10 : 0] state; + reg [10 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p13_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b1; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_MINUS__TB_sync or Ai_PLUS__TB_sync or Ai_PLUSa__TB_sync or Ai_MINUSa_ or e_x_MINUS_TB_sync or e_Ro_PLUSa_TB_sync or e_Ao_PLUS_TB_sync or e_Ro_PLUS_TB_sync or e_x_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ro_MINUSa_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_MINUS = 1'b0; + e_Ro_PLUSa = 1'b0; + e_Ao_PLUS = 1'b0; + e_Ro_PLUS = 1'b0; + e_x_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ro_MINUSa = 1'b0; + + casex (state) + 11'bxxxxxxxxxx1: // p7_1HOT_ENCODING: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + // next_state = p14_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[6] = 1'b1; + end + end + + 11'bxxxxxxxxx1x: // p11_1HOT_ENCODING: // + begin + if (Ai_MINUSa_) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[4] = 1'b1; + end + end + + 11'bxxxxxxxx1xx: // p9_1HOT_ENCODING: // + begin + if (Ai_PLUSa__TB_sync) + begin + // next_state = p12_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[3] = 1'b1; + end + end + + 11'bxxxxxxx1xxx: // p12_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[8] = 1'b1; + end + end + + 11'bxxxxxx1xxxx: // p13_1HOT_ENCODING: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[9] = 1'b1; + end + end + + 11'bxxxxx1xxxxx: // p1_1HOT_ENCODING: // + begin + if (e_Ro_PLUSa_TB_sync) + begin + e_Ro_PLUSa = 1'b1; + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[2] = 1'b1; + end + end + + 11'bxxxx1xxxxxx: // p14_1HOT_ENCODING: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[10] = 1'b1; + end + end + + 11'bxxx1xxxxxxx: // p2_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[5] = 1'b1; + end + end + + 11'bxx1xxxxxxxx: // p15_1HOT_ENCODING: // + begin + if (e_Ro_MINUSa_TB_sync) + begin + e_Ro_MINUSa = 1'b1; + // next_state = p11_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[1] = 1'b1; + end + end + + 11'bx1xxxxxxxxx: // p4_1HOT_ENCODING: // + begin + if (Ai_PLUS__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[0] = 1'b1; + end + end + + 11'b1xxxxxxxxxx: // p5_1HOT_ENCODING: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[7] = 1'b1; + end + end + + default: + begin + next_state = 11'dx; + end + endcase + end +endmodule + diff --git a/examples/converta_MG/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/converta_MG/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..c564e27 --- /dev/null +++ b/examples/converta_MG/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,819 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + Ri_MINUS_, Ri_MINUS__p2_FSM3_TB, + Ai_PLUS_, Ai_PLUS__p4_FSM2_TB, Ai_PLUS__p4_FSM3_TB, + Ri_PLUS_, Ri_PLUS__p3_FSM2_TB, + Ai_PLUSa_, Ai_PLUSa__p9_FSM2_TB, Ai_PLUSa__p9_FSM3_TB, + e_x_MINUS, e_x_MINUS_p12_FSM2_TB, e_x_MINUS_p12_FSM3_TB, + e_Ro_PLUSa, e_Ro_PLUSa_p8_FSM2_TB, e_Ro_PLUSa_p1_FSM3_TB, + e_Ao_PLUS, e_Ao_PLUS_p5_FSM3_TB, + e_Ro_PLUS, e_Ro_PLUS_p0_FSM2_TB, e_Ro_PLUS_p13_FSM3_TB, + e_x_PLUS, e_x_PLUS_p7_FSM2_TB, e_x_PLUS_p7_FSM3_TB, + e_Ro_MINUS, e_Ro_MINUS_p14_FSM2_TB, e_Ro_MINUS_p14_FSM3_TB, + e_Ao_MINUS, e_Ao_MINUS_p10_FSM2_TB, + e_Ro_MINUSa, e_Ro_MINUSa_p15_FSM2_TB, e_Ro_MINUSa_p15_FSM3_TB, + p7, + p10, + p9, + p12, + p0, + p1, + p14, + p2, + p15, + p3, + p4, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_MINUS_; + input Ai_PLUS_; + input Ri_PLUS_; + input Ai_PLUSa_; + // Transition Barrier Inputs for input Signals // + input Ri_MINUS__p2_FSM3_TB; + input Ai_PLUS__p4_FSM2_TB, Ai_PLUS__p4_FSM3_TB; + input Ri_PLUS__p3_FSM2_TB; + input Ai_PLUSa__p9_FSM2_TB, Ai_PLUSa__p9_FSM3_TB; + + // Regular output Signals // + output e_x_MINUS; + output e_Ro_PLUSa; + output e_Ao_PLUS; + output e_Ro_PLUS; + output e_x_PLUS; + output e_Ro_MINUS; + output e_Ao_MINUS; + output e_Ro_MINUSa; + // Transition Barrier outputs for output Signals // + input e_x_MINUS_p12_FSM2_TB, e_x_MINUS_p12_FSM3_TB; + input e_Ro_PLUSa_p8_FSM2_TB, e_Ro_PLUSa_p1_FSM3_TB; + input e_Ao_PLUS_p5_FSM3_TB; + input e_Ro_PLUS_p0_FSM2_TB, e_Ro_PLUS_p13_FSM3_TB; + input e_x_PLUS_p7_FSM2_TB, e_x_PLUS_p7_FSM3_TB; + input e_Ro_MINUS_p14_FSM2_TB, e_Ro_MINUS_p14_FSM3_TB; + input e_Ao_MINUS_p10_FSM2_TB; + input e_Ro_MINUSa_p15_FSM2_TB, e_Ro_MINUSa_p15_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p10; + output p9; + output p12; + output p0; + output p1; + output p14; + output p2; + output p15; + output p3; + output p4; + output p5; + + reg e_x_MINUS; + reg e_Ro_PLUSa; + reg e_Ao_PLUS; + reg e_Ro_PLUS; + reg e_x_PLUS; + reg e_Ro_MINUS; + reg e_Ao_MINUS; + reg e_Ro_MINUSa; + wire p7; + wire p10; + wire p9; + wire p12; + wire p0; + wire p1; + wire p14; + wire p2; + wire p15; + wire p3; + wire p4; + wire p5; + + wire Ri_MINUS__TB_sync; + wire Ai_PLUS__TB_sync; + wire Ri_PLUS__TB_sync; + wire Ai_PLUSa__TB_sync; + wire e_x_MINUS_TB_sync; + wire e_Ro_PLUSa_TB_sync; + wire e_Ao_PLUS_TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_x_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + wire e_Ro_MINUSa_TB_sync; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p2_FSM3_TB; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p4_FSM2_TB & Ai_PLUS__p4_FSM3_TB; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p3_FSM2_TB; + assign Ai_PLUSa__TB_sync = Ai_PLUSa_ & Ai_PLUSa__p9_FSM2_TB & Ai_PLUSa__p9_FSM3_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p12_FSM2_TB & e_x_MINUS_p12_FSM3_TB; + assign e_Ro_PLUSa_TB_sync = e_Ro_PLUSa_p8_FSM2_TB & e_Ro_PLUSa_p1_FSM3_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p5_FSM3_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p0_FSM2_TB & e_Ro_PLUS_p13_FSM3_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p7_FSM2_TB & e_x_PLUS_p7_FSM3_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p14_FSM2_TB & e_Ro_MINUS_p14_FSM3_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p10_FSM2_TB; + assign e_Ro_MINUSa_TB_sync = e_Ro_MINUSa_p15_FSM2_TB & e_Ro_MINUSa_p15_FSM3_TB; + + parameter p7_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p10_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p9_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p12_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p0_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p1_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p14_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p2_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p15_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p3_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p4_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p5_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p3_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p10 = (state == p10_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_MINUS__TB_sync or Ai_PLUS__TB_sync or Ri_PLUS__TB_sync or Ai_PLUSa__TB_sync or e_x_MINUS_TB_sync or e_Ro_PLUSa_TB_sync or e_Ao_PLUS_TB_sync or e_Ro_PLUS_TB_sync or e_x_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_MINUS_TB_sync or e_Ro_MINUSa_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_MINUS = 1'b0; + e_Ro_PLUSa = 1'b0; + e_Ao_PLUS = 1'b0; + e_Ro_PLUS = 1'b0; + e_x_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_MINUS = 1'b0; + e_Ro_MINUSa = 1'b0; + + case (state) + p7_1HOT_ENCODING: // 12'b000000000001: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + next_state = p14_1HOT_ENCODING; + end + end + + p10_1HOT_ENCODING: // 12'b000000000010: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + next_state = p3_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 12'b000000000100: // + begin + if (Ai_PLUSa__TB_sync) + begin + next_state = p12_1HOT_ENCODING; + end + end + + p12_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 12'b000000010000: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 12'b000000100000: // + begin + if (e_Ro_PLUSa_TB_sync) + begin + e_Ro_PLUSa = 1'b1; + next_state = p9_1HOT_ENCODING; + end + end + + p14_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 12'b000010000000: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 12'b000100000000: // + begin + if (e_Ro_MINUSa_TB_sync) + begin + e_Ro_MINUSa = 1'b1; + next_state = p10_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 12'b001000000000: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 12'b010000000000: // + begin + if (Ai_PLUS__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 12'b100000000000: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + next_state = p2_1HOT_ENCODING; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + Ai_PLUS_, Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM3_TB, + Ai_MINUS_, + Ri_PLUS_, Ri_PLUS__p3_FSM1_TB, + Ai_PLUSa_, Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM3_TB, + e_x_MINUS, e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM3_TB, + e_Ro_PLUSa, e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p1_FSM3_TB, + e_Ro_PLUS, e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p13_FSM3_TB, + e_x_PLUS, e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM3_TB, + e_Ro_MINUS, e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM3_TB, + e_Ao_MINUS, e_Ao_MINUS_p10_FSM1_TB, + e_Ro_MINUSa, e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM3_TB, + p7, + p10, + p8, + p9, + p12, + p0, + p14, + p15, + p3, + p4 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ai_PLUS_; + input Ai_MINUS_; + input Ri_PLUS_; + input Ai_PLUSa_; + // Transition Barrier Inputs for input Signals // + input Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM3_TB; + input Ri_PLUS__p3_FSM1_TB; + input Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM3_TB; + + // Regular output Signals // + output e_x_MINUS; + output e_Ro_PLUSa; + output e_Ro_PLUS; + output e_x_PLUS; + output e_Ro_MINUS; + output e_Ao_MINUS; + output e_Ro_MINUSa; + // Transition Barrier outputs for output Signals // + input e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM3_TB; + input e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p1_FSM3_TB; + input e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p13_FSM3_TB; + input e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM3_TB; + input e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM3_TB; + input e_Ao_MINUS_p10_FSM1_TB; + input e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p10; + output p8; + output p9; + output p12; + output p0; + output p14; + output p15; + output p3; + output p4; + + reg e_x_MINUS; + reg e_Ro_PLUSa; + reg e_Ro_PLUS; + reg e_x_PLUS; + reg e_Ro_MINUS; + reg e_Ao_MINUS; + reg e_Ro_MINUSa; + wire p7; + wire p10; + wire p8; + wire p9; + wire p12; + wire p0; + wire p14; + wire p15; + wire p3; + wire p4; + + wire Ai_PLUS__TB_sync; + wire Ri_PLUS__TB_sync; + wire Ai_PLUSa__TB_sync; + wire e_x_MINUS_TB_sync; + wire e_Ro_PLUSa_TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_x_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + wire e_Ro_MINUSa_TB_sync; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p4_FSM1_TB & Ai_PLUS__p4_FSM3_TB; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p3_FSM1_TB; + assign Ai_PLUSa__TB_sync = Ai_PLUSa_ & Ai_PLUSa__p9_FSM1_TB & Ai_PLUSa__p9_FSM3_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p12_FSM1_TB & e_x_MINUS_p12_FSM3_TB; + assign e_Ro_PLUSa_TB_sync = e_Ro_PLUSa_p1_FSM1_TB & e_Ro_PLUSa_p1_FSM3_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p0_FSM1_TB & e_Ro_PLUS_p13_FSM3_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p7_FSM1_TB & e_x_PLUS_p7_FSM3_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p14_FSM1_TB & e_Ro_MINUS_p14_FSM3_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p10_FSM1_TB; + assign e_Ro_MINUSa_TB_sync = e_Ro_MINUSa_p15_FSM1_TB & e_Ro_MINUSa_p15_FSM3_TB; + + parameter p7_1HOT_ENCODING = 11'd1; // 11'b00000000001 // + parameter p10_1HOT_ENCODING = 11'd2; // 11'b00000000010 // + parameter p8_1HOT_ENCODING = 11'd4; // 11'b00000000100 // + parameter p9_1HOT_ENCODING = 11'd8; // 11'b00000001000 // + parameter p12_1HOT_ENCODING = 11'd16; // 11'b00000010000 // + parameter p0_1HOT_ENCODING = 11'd32; // 11'b00000100000 // + parameter p14_1HOT_ENCODING = 11'd64; // 11'b00001000000 // + parameter p15_1HOT_ENCODING = 11'd128; // 11'b00010000000 // + parameter p3_1HOT_ENCODING = 11'd256; // 11'b00100000000 // + parameter p4_1HOT_ENCODING = 11'd512; // 11'b01000000000 // + parameter p6_1HOT_ENCODING = 11'd1024; // 11'b10000000000 // + + reg [10 : 0] state; + reg [10 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p3_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p10 = (state == p10_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ai_PLUS__TB_sync or Ai_MINUS_ or Ri_PLUS__TB_sync or Ai_PLUSa__TB_sync or e_x_MINUS_TB_sync or e_Ro_PLUSa_TB_sync or e_Ro_PLUS_TB_sync or e_x_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_MINUS_TB_sync or e_Ro_MINUSa_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_MINUS = 1'b0; + e_Ro_PLUSa = 1'b0; + e_Ro_PLUS = 1'b0; + e_x_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_MINUS = 1'b0; + e_Ro_MINUSa = 1'b0; + + case (state) + p7_1HOT_ENCODING: // 11'b00000000001: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + next_state = p14_1HOT_ENCODING; + end + end + + p10_1HOT_ENCODING: // 11'b00000000010: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + next_state = p3_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 11'b00000000100: // + begin + if (e_Ro_PLUSa_TB_sync) + begin + e_Ro_PLUSa = 1'b1; + next_state = p9_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 11'b00000001000: // + begin + if (Ai_PLUSa__TB_sync) + begin + next_state = p12_1HOT_ENCODING; + end + end + + p12_1HOT_ENCODING: // 11'b00000010000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 11'b00000100000: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p14_1HOT_ENCODING: // 11'b00001000000: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + next_state = p6_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 11'b00010000000: // + begin + if (e_Ro_MINUSa_TB_sync) + begin + e_Ro_MINUSa = 1'b1; + next_state = p10_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 11'b00100000000: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 11'b01000000000: // + begin + if (Ai_PLUS__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 11'b10000000000: // + begin + if (Ai_MINUS_) + begin + next_state = p8_1HOT_ENCODING; + end + end + + default: + begin + next_state = 11'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_03 ( + clk, + reset, + Ri_MINUS_, Ri_MINUS__p2_FSM1_TB, + Ai_PLUS_, Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM2_TB, + Ai_PLUSa_, Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM2_TB, + Ai_MINUSa_, + e_x_MINUS, e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM2_TB, + e_Ro_PLUSa, e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p8_FSM2_TB, + e_Ao_PLUS, e_Ao_PLUS_p5_FSM1_TB, + e_Ro_PLUS, e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p0_FSM2_TB, + e_x_PLUS, e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM2_TB, + e_Ro_MINUS, e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM2_TB, + e_Ro_MINUSa, e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM2_TB, + p7, + p9, + p12, + p13, + p1, + p14, + p2, + p15, + p4, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_MINUS_; + input Ai_PLUS_; + input Ai_PLUSa_; + input Ai_MINUSa_; + // Transition Barrier Inputs for input Signals // + input Ri_MINUS__p2_FSM1_TB; + input Ai_PLUS__p4_FSM1_TB, Ai_PLUS__p4_FSM2_TB; + input Ai_PLUSa__p9_FSM1_TB, Ai_PLUSa__p9_FSM2_TB; + + // Regular output Signals // + output e_x_MINUS; + output e_Ro_PLUSa; + output e_Ao_PLUS; + output e_Ro_PLUS; + output e_x_PLUS; + output e_Ro_MINUS; + output e_Ro_MINUSa; + // Transition Barrier outputs for output Signals // + input e_x_MINUS_p12_FSM1_TB, e_x_MINUS_p12_FSM2_TB; + input e_Ro_PLUSa_p1_FSM1_TB, e_Ro_PLUSa_p8_FSM2_TB; + input e_Ao_PLUS_p5_FSM1_TB; + input e_Ro_PLUS_p0_FSM1_TB, e_Ro_PLUS_p0_FSM2_TB; + input e_x_PLUS_p7_FSM1_TB, e_x_PLUS_p7_FSM2_TB; + input e_Ro_MINUS_p14_FSM1_TB, e_Ro_MINUS_p14_FSM2_TB; + input e_Ro_MINUSa_p15_FSM1_TB, e_Ro_MINUSa_p15_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p9; + output p12; + output p13; + output p1; + output p14; + output p2; + output p15; + output p4; + output p5; + + reg e_x_MINUS; + reg e_Ro_PLUSa; + reg e_Ao_PLUS; + reg e_Ro_PLUS; + reg e_x_PLUS; + reg e_Ro_MINUS; + reg e_Ro_MINUSa; + wire p7; + wire p9; + wire p12; + wire p13; + wire p1; + wire p14; + wire p2; + wire p15; + wire p4; + wire p5; + + wire Ri_MINUS__TB_sync; + wire Ai_PLUS__TB_sync; + wire Ai_PLUSa__TB_sync; + wire e_x_MINUS_TB_sync; + wire e_Ro_PLUSa_TB_sync; + wire e_Ao_PLUS_TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_x_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ro_MINUSa_TB_sync; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p2_FSM1_TB; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p4_FSM1_TB & Ai_PLUS__p4_FSM2_TB; + assign Ai_PLUSa__TB_sync = Ai_PLUSa_ & Ai_PLUSa__p9_FSM1_TB & Ai_PLUSa__p9_FSM2_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p12_FSM1_TB & e_x_MINUS_p12_FSM2_TB; + assign e_Ro_PLUSa_TB_sync = e_Ro_PLUSa_p1_FSM1_TB & e_Ro_PLUSa_p8_FSM2_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p5_FSM1_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p0_FSM1_TB & e_Ro_PLUS_p0_FSM2_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p7_FSM1_TB & e_x_PLUS_p7_FSM2_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p14_FSM1_TB & e_Ro_MINUS_p14_FSM2_TB; + assign e_Ro_MINUSa_TB_sync = e_Ro_MINUSa_p15_FSM1_TB & e_Ro_MINUSa_p15_FSM2_TB; + + parameter p7_1HOT_ENCODING = 11'd1; // 11'b00000000001 // + parameter p11_1HOT_ENCODING = 11'd2; // 11'b00000000010 // + parameter p9_1HOT_ENCODING = 11'd4; // 11'b00000000100 // + parameter p12_1HOT_ENCODING = 11'd8; // 11'b00000001000 // + parameter p13_1HOT_ENCODING = 11'd16; // 11'b00000010000 // + parameter p1_1HOT_ENCODING = 11'd32; // 11'b00000100000 // + parameter p14_1HOT_ENCODING = 11'd64; // 11'b00001000000 // + parameter p2_1HOT_ENCODING = 11'd128; // 11'b00010000000 // + parameter p15_1HOT_ENCODING = 11'd256; // 11'b00100000000 // + parameter p4_1HOT_ENCODING = 11'd512; // 11'b01000000000 // + parameter p5_1HOT_ENCODING = 11'd1024; // 11'b10000000000 // + + reg [10 : 0] state; + reg [10 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p13_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_MINUS__TB_sync or Ai_PLUS__TB_sync or Ai_PLUSa__TB_sync or Ai_MINUSa_ or e_x_MINUS_TB_sync or e_Ro_PLUSa_TB_sync or e_Ao_PLUS_TB_sync or e_Ro_PLUS_TB_sync or e_x_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ro_MINUSa_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_MINUS = 1'b0; + e_Ro_PLUSa = 1'b0; + e_Ao_PLUS = 1'b0; + e_Ro_PLUS = 1'b0; + e_x_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ro_MINUSa = 1'b0; + + case (state) + p7_1HOT_ENCODING: // 11'b00000000001: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + next_state = p14_1HOT_ENCODING; + end + end + + p11_1HOT_ENCODING: // 11'b00000000010: // + begin + if (Ai_MINUSa_) + begin + next_state = p13_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 11'b00000000100: // + begin + if (Ai_PLUSa__TB_sync) + begin + next_state = p12_1HOT_ENCODING; + end + end + + p12_1HOT_ENCODING: // 11'b00000001000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 11'b00000010000: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 11'b00000100000: // + begin + if (e_Ro_PLUSa_TB_sync) + begin + e_Ro_PLUSa = 1'b1; + next_state = p9_1HOT_ENCODING; + end + end + + p14_1HOT_ENCODING: // 11'b00001000000: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 11'b00010000000: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 11'b00100000000: // + begin + if (e_Ro_MINUSa_TB_sync) + begin + e_Ro_MINUSa = 1'b1; + next_state = p11_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 11'b01000000000: // + begin + if (Ai_PLUS__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 11'b10000000000: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + next_state = p2_1HOT_ENCODING; + end + end + + default: + begin + next_state = 11'dx; + end + endcase + end +endmodule + diff --git a/examples/converta_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/converta_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..f2d9099 --- /dev/null +++ b/examples/converta_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,137 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + x_MINUS, + Ro_PLUSa, + Ao_PLUS, + Ri_MINUS, + Ai_PLUS, + Ai_MINUS, + Ro_PLUS, + x_PLUS, + Ri_PLUS, + Ro_MINUS, + Ao_MINUS, + Ro_MINUSa, + Ai_PLUSa, + Ai_MINUSa); + + input clk; + input reset; + output x_MINUS; + output Ro_PLUSa; + output Ao_PLUS; + input Ri_MINUS; + input Ai_PLUS; + input Ai_MINUS; + output Ro_PLUS; + output x_PLUS; + input Ri_PLUS; + output Ro_MINUS; + output Ao_MINUS; + output Ro_MINUSa; + input Ai_PLUSa; + input Ai_MINUSa; + + wire e_x_MINUS_FSM1out, e_Ro_PLUSa_FSM1out, e_Ao_PLUS_FSM1out, e_Ro_PLUS_FSM1out, e_x_PLUS_FSM1out, e_Ro_MINUS_FSM1out, e_Ao_MINUS_FSM1out, e_Ro_MINUSa_FSM1out; // Regular output signals of FSM1 // + wire p7_FSM1out, p10_FSM1out, p9_FSM1out, p12_FSM1out, p0_FSM1out, p1_FSM1out, p14_FSM1out, p2_FSM1out, p15_FSM1out, p3_FSM1out, p4_FSM1out, p5_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_x_MINUS_FSM2out, e_Ro_PLUSa_FSM2out, e_Ro_PLUS_FSM2out, e_x_PLUS_FSM2out, e_Ro_MINUS_FSM2out, e_Ao_MINUS_FSM2out, e_Ro_MINUSa_FSM2out; // Regular output signals of FSM2 // + wire p7_FSM2out, p10_FSM2out, p8_FSM2out, p9_FSM2out, p12_FSM2out, p0_FSM2out, p14_FSM2out, p15_FSM2out, p3_FSM2out, p4_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_x_MINUS_FSM3out, e_Ro_PLUSa_FSM3out, e_Ao_PLUS_FSM3out, e_Ro_PLUS_FSM3out, e_x_PLUS_FSM3out, e_Ro_MINUS_FSM3out, e_Ro_MINUSa_FSM3out; // Regular output signals of FSM3 // + wire p7_FSM3out, p11_FSM3out, p9_FSM3out, p12_FSM3out, p13_FSM3out, p1_FSM3out, p14_FSM3out, p2_FSM3out, p15_FSM3out, p4_FSM3out, p5_FSM3out; // State Synchronisation output signals of FSM3 // + + assign x_MINUS = e_x_MINUS_FSM1out & e_x_MINUS_FSM2out & e_x_MINUS_FSM3out; + assign Ro_PLUSa = e_Ro_PLUSa_FSM1out & e_Ro_PLUSa_FSM2out & e_Ro_PLUSa_FSM3out; + assign Ao_PLUS = e_Ao_PLUS_FSM1out & e_Ao_PLUS_FSM3out; + assign Ro_PLUS = e_Ro_PLUS_FSM1out & e_Ro_PLUS_FSM2out & e_Ro_PLUS_FSM3out; + assign x_PLUS = e_x_PLUS_FSM1out & e_x_PLUS_FSM2out & e_x_PLUS_FSM3out; + assign Ro_MINUS = e_Ro_MINUS_FSM1out & e_Ro_MINUS_FSM2out & e_Ro_MINUS_FSM3out; + assign Ao_MINUS = e_Ao_MINUS_FSM1out & e_Ao_MINUS_FSM2out; + assign Ro_MINUSa = e_Ro_MINUSa_FSM1out & e_Ro_MINUSa_FSM2out & e_Ro_MINUSa_FSM3out; + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p2_FSM3_TB(p2_FSM3out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM2_TB(p4_FSM2out), .Ai_PLUS__p4_FSM3_TB(p4_FSM3out), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p3_FSM2_TB(p3_FSM2out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM2_TB(p9_FSM2out), .Ai_PLUSa__p9_FSM3_TB(p9_FSM3out), + .e_x_MINUS(e_x_MINUS_FSM1out), .e_x_MINUS_p12_FSM2_TB(p12_FSM2out), .e_x_MINUS_p12_FSM3_TB(p12_FSM3out), + .e_Ro_PLUSa(e_Ro_PLUSa_FSM1out), .e_Ro_PLUSa_p8_FSM2_TB(p8_FSM2out), .e_Ro_PLUSa_p1_FSM3_TB(p1_FSM3out), + .e_Ao_PLUS(e_Ao_PLUS_FSM1out), .e_Ao_PLUS_p5_FSM3_TB(p5_FSM3out), + .e_Ro_PLUS(e_Ro_PLUS_FSM1out), .e_Ro_PLUS_p0_FSM2_TB(p0_FSM2out), .e_Ro_PLUS_p13_FSM3_TB(p13_FSM3out), + .e_x_PLUS(e_x_PLUS_FSM1out), .e_x_PLUS_p7_FSM2_TB(p7_FSM2out), .e_x_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(e_Ro_MINUS_FSM1out), .e_Ro_MINUS_p14_FSM2_TB(p14_FSM2out), .e_Ro_MINUS_p14_FSM3_TB(p14_FSM3out), + .e_Ao_MINUS(e_Ao_MINUS_FSM1out), .e_Ao_MINUS_p10_FSM2_TB(p10_FSM2out), + .e_Ro_MINUSa(e_Ro_MINUSa_FSM1out), .e_Ro_MINUSa_p15_FSM2_TB(p15_FSM2out), .e_Ro_MINUSa_p15_FSM3_TB(p15_FSM3out), + .p7(p7_FSM1out), + .p10(p10_FSM1out), + .p9(p9_FSM1out), + .p12(p12_FSM1out), + .p0(p0_FSM1out), + .p1(p1_FSM1out), + .p14(p14_FSM1out), + .p2(p2_FSM1out), + .p15(p15_FSM1out), + .p3(p3_FSM1out), + .p4(p4_FSM1out), + .p5(p5_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM1_TB(p4_FSM1out), .Ai_PLUS__p4_FSM3_TB(p4_FSM3out), + .Ai_MINUS_(Ai_MINUS), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p3_FSM1_TB(p3_FSM1out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM1_TB(p9_FSM1out), .Ai_PLUSa__p9_FSM3_TB(p9_FSM3out), + .e_x_MINUS(e_x_MINUS_FSM2out), .e_x_MINUS_p12_FSM1_TB(p12_FSM1out), .e_x_MINUS_p12_FSM3_TB(p12_FSM3out), + .e_Ro_PLUSa(e_Ro_PLUSa_FSM2out), .e_Ro_PLUSa_p1_FSM1_TB(p1_FSM1out), .e_Ro_PLUSa_p1_FSM3_TB(p1_FSM3out), + .e_Ro_PLUS(e_Ro_PLUS_FSM2out), .e_Ro_PLUS_p0_FSM1_TB(p0_FSM1out), .e_Ro_PLUS_p13_FSM3_TB(p13_FSM3out), + .e_x_PLUS(e_x_PLUS_FSM2out), .e_x_PLUS_p7_FSM1_TB(p7_FSM1out), .e_x_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(e_Ro_MINUS_FSM2out), .e_Ro_MINUS_p14_FSM1_TB(p14_FSM1out), .e_Ro_MINUS_p14_FSM3_TB(p14_FSM3out), + .e_Ao_MINUS(e_Ao_MINUS_FSM2out), .e_Ao_MINUS_p10_FSM1_TB(p10_FSM1out), + .e_Ro_MINUSa(e_Ro_MINUSa_FSM2out), .e_Ro_MINUSa_p15_FSM1_TB(p15_FSM1out), .e_Ro_MINUSa_p15_FSM3_TB(p15_FSM3out), + .p7(p7_FSM2out), + .p10(p10_FSM2out), + .p8(p8_FSM2out), + .p9(p9_FSM2out), + .p12(p12_FSM2out), + .p0(p0_FSM2out), + .p14(p14_FSM2out), + .p15(p15_FSM2out), + .p3(p3_FSM2out), + .p4(p4_FSM2out) + ); + + + fsm_mealy_behav_03 fsm_mealy_behav_03_inst ( + .clk(clk), + .reset(reset), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p2_FSM1_TB(p2_FSM1out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM1_TB(p4_FSM1out), .Ai_PLUS__p4_FSM2_TB(p4_FSM2out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM1_TB(p9_FSM1out), .Ai_PLUSa__p9_FSM2_TB(p9_FSM2out), + .Ai_MINUSa_(Ai_MINUSa), + .e_x_MINUS(e_x_MINUS_FSM3out), .e_x_MINUS_p12_FSM1_TB(p12_FSM1out), .e_x_MINUS_p12_FSM2_TB(p12_FSM2out), + .e_Ro_PLUSa(e_Ro_PLUSa_FSM3out), .e_Ro_PLUSa_p1_FSM1_TB(p1_FSM1out), .e_Ro_PLUSa_p8_FSM2_TB(p8_FSM2out), + .e_Ao_PLUS(e_Ao_PLUS_FSM3out), .e_Ao_PLUS_p5_FSM1_TB(p5_FSM1out), + .e_Ro_PLUS(e_Ro_PLUS_FSM3out), .e_Ro_PLUS_p0_FSM1_TB(p0_FSM1out), .e_Ro_PLUS_p0_FSM2_TB(p0_FSM2out), + .e_x_PLUS(e_x_PLUS_FSM3out), .e_x_PLUS_p7_FSM1_TB(p7_FSM1out), .e_x_PLUS_p7_FSM2_TB(p7_FSM2out), + .e_Ro_MINUS(e_Ro_MINUS_FSM3out), .e_Ro_MINUS_p14_FSM1_TB(p14_FSM1out), .e_Ro_MINUS_p14_FSM2_TB(p14_FSM2out), + .e_Ro_MINUSa(e_Ro_MINUSa_FSM3out), .e_Ro_MINUSa_p15_FSM1_TB(p15_FSM1out), .e_Ro_MINUSa_p15_FSM2_TB(p15_FSM2out), + .p7(p7_FSM3out), + .p9(p9_FSM3out), + .p12(p12_FSM3out), + .p13(p13_FSM3out), + .p1(p1_FSM3out), + .p14(p14_FSM3out), + .p2(p2_FSM3out), + .p15(p15_FSM3out), + .p4(p4_FSM3out), + .p5(p5_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/converta_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/converta_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..e30b1c6 --- /dev/null +++ b/examples/converta_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,137 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + x_MINUS, + Ro_PLUSa, + Ao_PLUS, + Ri_MINUS, + Ai_PLUS, + Ai_MINUS, + Ro_PLUS, + x_PLUS, + Ri_PLUS, + Ro_MINUS, + Ao_MINUS, + Ro_MINUSa, + Ai_PLUSa, + Ai_MINUSa); + + input clk; + input reset; + output x_MINUS; + output Ro_PLUSa; + output Ao_PLUS; + input Ri_MINUS; + input Ai_PLUS; + input Ai_MINUS; + output Ro_PLUS; + output x_PLUS; + input Ri_PLUS; + output Ro_MINUS; + output Ao_MINUS; + output Ro_MINUSa; + input Ai_PLUSa; + input Ai_MINUSa; + + wire e_x_MINUS_FSM1out, e_Ro_PLUSa_FSM1out, e_Ao_PLUS_FSM1out, e_Ro_PLUS_FSM1out, e_x_PLUS_FSM1out, e_Ro_MINUS_FSM1out, e_Ao_MINUS_FSM1out, e_Ro_MINUSa_FSM1out; // Regular output signals of FSM1 // + wire p7_FSM1out, p10_FSM1out, p9_FSM1out, p12_FSM1out, p0_FSM1out, p1_FSM1out, p14_FSM1out, p2_FSM1out, p15_FSM1out, p3_FSM1out, p4_FSM1out, p5_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_x_MINUS_FSM2out, e_Ro_PLUSa_FSM2out, e_Ro_PLUS_FSM2out, e_x_PLUS_FSM2out, e_Ro_MINUS_FSM2out, e_Ao_MINUS_FSM2out, e_Ro_MINUSa_FSM2out; // Regular output signals of FSM2 // + wire p7_FSM2out, p10_FSM2out, p8_FSM2out, p9_FSM2out, p12_FSM2out, p0_FSM2out, p14_FSM2out, p15_FSM2out, p3_FSM2out, p4_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_x_MINUS_FSM3out, e_Ro_PLUSa_FSM3out, e_Ao_PLUS_FSM3out, e_Ro_PLUS_FSM3out, e_x_PLUS_FSM3out, e_Ro_MINUS_FSM3out, e_Ro_MINUSa_FSM3out; // Regular output signals of FSM3 // + wire p7_FSM3out, p11_FSM3out, p9_FSM3out, p12_FSM3out, p13_FSM3out, p1_FSM3out, p14_FSM3out, p2_FSM3out, p15_FSM3out, p4_FSM3out, p5_FSM3out; // State Synchronisation output signals of FSM3 // + + assign x_MINUS = e_x_MINUS_FSM1out & e_x_MINUS_FSM2out & e_x_MINUS_FSM3out; + assign Ro_PLUSa = e_Ro_PLUSa_FSM1out & e_Ro_PLUSa_FSM2out & e_Ro_PLUSa_FSM3out; + assign Ao_PLUS = e_Ao_PLUS_FSM1out & e_Ao_PLUS_FSM3out; + assign Ro_PLUS = e_Ro_PLUS_FSM1out & e_Ro_PLUS_FSM2out & e_Ro_PLUS_FSM3out; + assign x_PLUS = e_x_PLUS_FSM1out & e_x_PLUS_FSM2out & e_x_PLUS_FSM3out; + assign Ro_MINUS = e_Ro_MINUS_FSM1out & e_Ro_MINUS_FSM2out & e_Ro_MINUS_FSM3out; + assign Ao_MINUS = e_Ao_MINUS_FSM1out & e_Ao_MINUS_FSM2out; + assign Ro_MINUSa = e_Ro_MINUSa_FSM1out & e_Ro_MINUSa_FSM2out & e_Ro_MINUSa_FSM3out; + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p2_FSM3_TB(p2_FSM3out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM2_TB(p4_FSM2out), .Ai_PLUS__p4_FSM3_TB(p4_FSM3out), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p3_FSM2_TB(p3_FSM2out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM2_TB(p9_FSM2out), .Ai_PLUSa__p9_FSM3_TB(p9_FSM3out), + .e_x_MINUS(e_x_MINUS_FSM1out), .e_x_MINUS_p12_FSM2_TB(p12_FSM2out), .e_x_MINUS_p12_FSM3_TB(p12_FSM3out), + .e_Ro_PLUSa(e_Ro_PLUSa_FSM1out), .e_Ro_PLUSa_p8_FSM2_TB(p8_FSM2out), .e_Ro_PLUSa_p1_FSM3_TB(p1_FSM3out), + .e_Ao_PLUS(e_Ao_PLUS_FSM1out), .e_Ao_PLUS_p5_FSM3_TB(p5_FSM3out), + .e_Ro_PLUS(e_Ro_PLUS_FSM1out), .e_Ro_PLUS_p0_FSM2_TB(p0_FSM2out), .e_Ro_PLUS_p13_FSM3_TB(p13_FSM3out), + .e_x_PLUS(e_x_PLUS_FSM1out), .e_x_PLUS_p7_FSM2_TB(p7_FSM2out), .e_x_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(e_Ro_MINUS_FSM1out), .e_Ro_MINUS_p14_FSM2_TB(p14_FSM2out), .e_Ro_MINUS_p14_FSM3_TB(p14_FSM3out), + .e_Ao_MINUS(e_Ao_MINUS_FSM1out), .e_Ao_MINUS_p10_FSM2_TB(p10_FSM2out), + .e_Ro_MINUSa(e_Ro_MINUSa_FSM1out), .e_Ro_MINUSa_p15_FSM2_TB(p15_FSM2out), .e_Ro_MINUSa_p15_FSM3_TB(p15_FSM3out), + .p7(p7_FSM1out), + .p10(p10_FSM1out), + .p9(p9_FSM1out), + .p12(p12_FSM1out), + .p0(p0_FSM1out), + .p1(p1_FSM1out), + .p14(p14_FSM1out), + .p2(p2_FSM1out), + .p15(p15_FSM1out), + .p3(p3_FSM1out), + .p4(p4_FSM1out), + .p5(p5_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM1_TB(p4_FSM1out), .Ai_PLUS__p4_FSM3_TB(p4_FSM3out), + .Ai_MINUS_(Ai_MINUS), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p3_FSM1_TB(p3_FSM1out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM1_TB(p9_FSM1out), .Ai_PLUSa__p9_FSM3_TB(p9_FSM3out), + .e_x_MINUS(e_x_MINUS_FSM2out), .e_x_MINUS_p12_FSM1_TB(p12_FSM1out), .e_x_MINUS_p12_FSM3_TB(p12_FSM3out), + .e_Ro_PLUSa(e_Ro_PLUSa_FSM2out), .e_Ro_PLUSa_p1_FSM1_TB(p1_FSM1out), .e_Ro_PLUSa_p1_FSM3_TB(p1_FSM3out), + .e_Ro_PLUS(e_Ro_PLUS_FSM2out), .e_Ro_PLUS_p0_FSM1_TB(p0_FSM1out), .e_Ro_PLUS_p13_FSM3_TB(p13_FSM3out), + .e_x_PLUS(e_x_PLUS_FSM2out), .e_x_PLUS_p7_FSM1_TB(p7_FSM1out), .e_x_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(e_Ro_MINUS_FSM2out), .e_Ro_MINUS_p14_FSM1_TB(p14_FSM1out), .e_Ro_MINUS_p14_FSM3_TB(p14_FSM3out), + .e_Ao_MINUS(e_Ao_MINUS_FSM2out), .e_Ao_MINUS_p10_FSM1_TB(p10_FSM1out), + .e_Ro_MINUSa(e_Ro_MINUSa_FSM2out), .e_Ro_MINUSa_p15_FSM1_TB(p15_FSM1out), .e_Ro_MINUSa_p15_FSM3_TB(p15_FSM3out), + .p7(p7_FSM2out), + .p10(p10_FSM2out), + .p8(p8_FSM2out), + .p9(p9_FSM2out), + .p12(p12_FSM2out), + .p0(p0_FSM2out), + .p14(p14_FSM2out), + .p15(p15_FSM2out), + .p3(p3_FSM2out), + .p4(p4_FSM2out) + ); + + + fsm_mealy_synth_03 fsm_mealy_synth_03_inst ( + .clk(clk), + .reset(reset), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p2_FSM1_TB(p2_FSM1out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p4_FSM1_TB(p4_FSM1out), .Ai_PLUS__p4_FSM2_TB(p4_FSM2out), + .Ai_PLUSa_(Ai_PLUSa), .Ai_PLUSa__p9_FSM1_TB(p9_FSM1out), .Ai_PLUSa__p9_FSM2_TB(p9_FSM2out), + .Ai_MINUSa_(Ai_MINUSa), + .e_x_MINUS(e_x_MINUS_FSM3out), .e_x_MINUS_p12_FSM1_TB(p12_FSM1out), .e_x_MINUS_p12_FSM2_TB(p12_FSM2out), + .e_Ro_PLUSa(e_Ro_PLUSa_FSM3out), .e_Ro_PLUSa_p1_FSM1_TB(p1_FSM1out), .e_Ro_PLUSa_p8_FSM2_TB(p8_FSM2out), + .e_Ao_PLUS(e_Ao_PLUS_FSM3out), .e_Ao_PLUS_p5_FSM1_TB(p5_FSM1out), + .e_Ro_PLUS(e_Ro_PLUS_FSM3out), .e_Ro_PLUS_p0_FSM1_TB(p0_FSM1out), .e_Ro_PLUS_p0_FSM2_TB(p0_FSM2out), + .e_x_PLUS(e_x_PLUS_FSM3out), .e_x_PLUS_p7_FSM1_TB(p7_FSM1out), .e_x_PLUS_p7_FSM2_TB(p7_FSM2out), + .e_Ro_MINUS(e_Ro_MINUS_FSM3out), .e_Ro_MINUS_p14_FSM1_TB(p14_FSM1out), .e_Ro_MINUS_p14_FSM2_TB(p14_FSM2out), + .e_Ro_MINUSa(e_Ro_MINUSa_FSM3out), .e_Ro_MINUSa_p15_FSM1_TB(p15_FSM1out), .e_Ro_MINUSa_p15_FSM2_TB(p15_FSM2out), + .p7(p7_FSM3out), + .p9(p9_FSM3out), + .p12(p12_FSM3out), + .p13(p13_FSM3out), + .p1(p1_FSM3out), + .p14(p14_FSM3out), + .p2(p2_FSM3out), + .p15(p15_FSM3out), + .p4(p4_FSM3out), + .p5(p5_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/converta_MG/converta.petrinet.MG.workcraft.g b/examples/converta_MG/converta.petrinet.MG.workcraft.g new file mode 100644 index 0000000..b299fd1 --- /dev/null +++ b/examples/converta_MG/converta.petrinet.MG.workcraft.g @@ -0,0 +1,37 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.5 +.model converta +.inputs Ri_MINUS Ri_PLUS Ai_PLUS Ai_MINUSa Ai_MINUS Ai_PLUSa +.outputs Ao_MINUS Ao_PLUS Ro_MINUS Ro_MINUSa Ro_PLUS Ro_PLUSa x_MINUS x_PLUS +.graph +Ri_PLUS p0 +Ro_PLUS p4 +Ri_MINUS p1 +Ro_PLUSa p9 +Ao_PLUS p2 +Ao_MINUS p3 +Ai_PLUS p7 +Ro_MINUS p5 p6 +Ai_MINUS p8 +x_PLUS p14 +Ai_PLUSa p12 +Ro_MINUSa p10 p11 +Ai_MINUSa p13 +x_MINUS p15 +p0 Ro_PLUS +p1 Ro_PLUSa +p2 Ri_MINUS +p3 Ri_PLUS +p4 Ai_PLUS +p5 Ao_PLUS +p6 Ai_MINUS +p7 x_PLUS +p8 Ro_PLUSa +p9 Ai_PLUSa +p10 Ao_MINUS +p11 Ai_MINUSa +p12 x_MINUS +p13 Ro_PLUS +p14 Ro_MINUS +p15 Ro_MINUSa +.marking {p13 p3} +.end diff --git a/examples/converta_MG/msfsms_tool_bm.log b/examples/converta_MG/msfsms_tool_bm.log new file mode 100644 index 0000000..1d79a6b --- /dev/null +++ b/examples/converta_MG/msfsms_tool_bm.log @@ -0,0 +1,484 @@ +--------------------------------------------------------------------------- +Benchmark: converta_MG/converta.petrinet.MG.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/converta_MG/converta.petrinet.MG.workcraft.g +INFO: Total Nodes : 30 +INFO: Total Transitions : 14 +INFO: Total Places : 16 +INFO: Total Edges : 32 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = p7, Type = Place (is Empty) + Predecessors: Ai_PLUS[12][1] + Successors: x_PLUS[18][1] +PT-Net [0][1]: Label = p10, Type = Place (is Empty) + Predecessors: Ro_MINUSa[24][2] + Successors: Ao_MINUS[24][0] +PT-Net [0][2]: Label = x_MINUS, Type = Transition (is Output) + Predecessors: p12[6][3] + Successors: p15[15][2] +PT-Net [3][0]: Label = p8, Type = Place (is Empty) + Predecessors: Ai_MINUS[12][2] + Successors: Ro_PLUSa[6][0] +PT-Net [3][1]: Label = p11, Type = Place (is Empty) + Predecessors: Ro_MINUSa[24][2] + Successors: Ai_MINUSa[27][2] +PT-Net [6][0]: Label = Ro_PLUSa, Type = Transition (is Output) + Predecessors: p1[12][0], p8[3][0] + Successors: p9[6][1] +PT-Net [6][1]: Label = p9, Type = Place (is Empty) + Predecessors: Ro_PLUSa[6][0] + Successors: Ai_PLUSa[27][1] +PT-Net [6][2]: Label = Ao_PLUS, Type = Transition (is Output) + Predecessors: p5[24][1] + Successors: p2[15][1] +PT-Net [6][3]: Label = p12, Type = Place (is Empty) + Predecessors: Ai_PLUSa[27][1] + Successors: x_MINUS[0][2] +PT-Net [9][0]: Label = p0, Type = Place (is Empty) + Predecessors: Ri_PLUS[21][0] + Successors: Ro_PLUS[15][0] +PT-Net [9][1]: Label = Ri_MINUS, Type = Transition (is Input) + Predecessors: p2[15][1] + Successors: p1[12][0] +PT-Net [9][2]: Label = p13, Type = Place (is Marked) + Predecessors: Ai_MINUSa[27][2] + Successors: Ro_PLUS[15][0] +PT-Net [12][0]: Label = p1, Type = Place (is Empty) + Predecessors: Ri_MINUS[9][1] + Successors: Ro_PLUSa[6][0] +PT-Net [12][1]: Label = Ai_PLUS, Type = Transition (is Input) + Predecessors: p4[21][1] + Successors: p7[0][0] +PT-Net [12][2]: Label = Ai_MINUS, Type = Transition (is Input) + Predecessors: p6[27][0] + Successors: p8[3][0] +PT-Net [12][3]: Label = p14, Type = Place (is Empty) + Predecessors: x_PLUS[18][1] + Successors: Ro_MINUS[21][2] +PT-Net [15][0]: Label = Ro_PLUS, Type = Transition (is Output) + Predecessors: p0[9][0], p13[9][2] + Successors: p4[21][1] +PT-Net [15][1]: Label = p2, Type = Place (is Empty) + Predecessors: Ao_PLUS[6][2] + Successors: Ri_MINUS[9][1] +PT-Net [15][2]: Label = p15, Type = Place (is Empty) + Predecessors: x_MINUS[0][2] + Successors: Ro_MINUSa[24][2] +PT-Net [18][0]: Label = p3, Type = Place (is Marked) + Predecessors: Ao_MINUS[24][0] + Successors: Ri_PLUS[21][0] +PT-Net [18][1]: Label = x_PLUS, Type = Transition (is Output) + Predecessors: p7[0][0] + Successors: p14[12][3] +PT-Net [21][0]: Label = Ri_PLUS, Type = Transition (is Input) + Predecessors: p3[18][0] + Successors: p0[9][0] +PT-Net [21][1]: Label = p4, Type = Place (is Empty) + Predecessors: Ro_PLUS[15][0] + Successors: Ai_PLUS[12][1] +PT-Net [21][2]: Label = Ro_MINUS, Type = Transition (is Output) + Predecessors: p14[12][3] + Successors: p5[24][1], p6[27][0] +PT-Net [24][0]: Label = Ao_MINUS, Type = Transition (is Output) + Predecessors: p10[0][1] + Successors: p3[18][0] +PT-Net [24][1]: Label = p5, Type = Place (is Empty) + Predecessors: Ro_MINUS[21][2] + Successors: Ao_PLUS[6][2] +PT-Net [24][2]: Label = Ro_MINUSa, Type = Transition (is Output) + Predecessors: p15[15][2] + Successors: p10[0][1], p11[3][1] +PT-Net [27][0]: Label = p6, Type = Place (is Empty) + Predecessors: Ro_MINUS[21][2] + Successors: Ai_MINUS[12][2] +PT-Net [27][1]: Label = Ai_PLUSa, Type = Transition (is Input) + Predecessors: p9[6][1] + Successors: p12[6][3] +PT-Net [27][2]: Label = Ai_MINUSa, Type = Transition (is Input) + Predecessors: p11[3][1] + Successors: p13[9][2] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #3 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 24, H-collapsed = 'false' *** +SC S-net (1,1): p7[0][0] +SC S-net (1,2): p10[0][1] +SC S-net (1,3): x_MINUS[0][2] + Predecessor Place: p12(1,7)[6,3] + Successor Place: p15(1,15)[15,2] +SC S-net (1,4): Ro_PLUSa[6][0] + Predecessor Place: p1(1,10)[12,0] + Successor Place: p9(1,5)[6,1] +SC S-net (1,5): p9[6][1] +SC S-net (1,6): Ao_PLUS[6][2] + Predecessor Place: p5(1,22)[24,1] + Successor Place: p2(1,14)[15,1] +SC S-net (1,7): p12[6][3] +SC S-net (1,8): p0[9][0] +SC S-net (1,9): Ri_MINUS[9][1] + Predecessor Place: p2(1,14)[15,1] + Successor Place: p1(1,10)[12,0] +SC S-net (1,10): p1[12][0] +SC S-net (1,11): Ai_PLUS[12][1] + Predecessor Place: p4(1,19)[21,1] + Successor Place: p7(1,1)[0,0] +SC S-net (1,12): p14[12][3] +SC S-net (1,13): Ro_PLUS[15][0] + Predecessor Place: p0(1,8)[9,0] + Successor Place: p4(1,19)[21,1] +SC S-net (1,14): p2[15][1] +SC S-net (1,15): p15[15][2] +SC S-net (1,16): p3[18][0] +SC S-net (1,17): x_PLUS[18][1] + Predecessor Place: p7(1,1)[0,0] + Successor Place: p14(1,12)[12,3] +SC S-net (1,18): Ri_PLUS[21][0] + Predecessor Place: p3(1,16)[18,0] + Successor Place: p0(1,8)[9,0] +SC S-net (1,19): p4[21][1] +SC S-net (1,20): Ro_MINUS[21][2] + Predecessor Place: p14(1,12)[12,3] + Successor Place: p5(1,22)[24,1] +SC S-net (1,21): Ao_MINUS[24][0] + Predecessor Place: p10(1,2)[0,1] + Successor Place: p3(1,16)[18,0] +SC S-net (1,22): p5[24][1] +SC S-net (1,23): Ro_MINUSa[24][2] + Predecessor Place: p15(1,15)[15,2] + Successor Place: p10(1,2)[0,1] +SC S-net (1,24): Ai_PLUSa[27][1] + Predecessor Place: p9(1,5)[6,1] + Successor Place: p12(1,7)[6,3] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 22, H-collapsed = 'false' *** +SC S-net (2,1): p7[0][0] +SC S-net (2,2): p10[0][1] +SC S-net (2,3): x_MINUS[0][2] + Predecessor Place: p12(2,7)[6,3] + Successor Place: p15(2,13)[15,2] +SC S-net (2,4): p8[3][0] +SC S-net (2,5): Ro_PLUSa[6][0] + Predecessor Place: p8(2,4)[3,0] + Successor Place: p9(2,6)[6,1] +SC S-net (2,6): p9[6][1] +SC S-net (2,7): p12[6][3] +SC S-net (2,8): p0[9][0] +SC S-net (2,9): Ai_PLUS[12][1] + Predecessor Place: p4(2,17)[21,1] + Successor Place: p7(2,1)[0,0] +SC S-net (2,10): Ai_MINUS[12][2] + Predecessor Place: p6(2,21)[27,0] + Successor Place: p8(2,4)[3,0] +SC S-net (2,11): p14[12][3] +SC S-net (2,12): Ro_PLUS[15][0] + Predecessor Place: p0(2,8)[9,0] + Successor Place: p4(2,17)[21,1] +SC S-net (2,13): p15[15][2] +SC S-net (2,14): p3[18][0] +SC S-net (2,15): x_PLUS[18][1] + Predecessor Place: p7(2,1)[0,0] + Successor Place: p14(2,11)[12,3] +SC S-net (2,16): Ri_PLUS[21][0] + Predecessor Place: p3(2,14)[18,0] + Successor Place: p0(2,8)[9,0] +SC S-net (2,17): p4[21][1] +SC S-net (2,18): Ro_MINUS[21][2] + Predecessor Place: p14(2,11)[12,3] + Successor Place: p6(2,21)[27,0] +SC S-net (2,19): Ao_MINUS[24][0] + Predecessor Place: p10(2,2)[0,1] + Successor Place: p3(2,14)[18,0] +SC S-net (2,20): Ro_MINUSa[24][2] + Predecessor Place: p15(2,13)[15,2] + Successor Place: p10(2,2)[0,1] +SC S-net (2,21): p6[27][0] +SC S-net (2,22): Ai_PLUSa[27][1] + Predecessor Place: p9(2,6)[6,1] + Successor Place: p12(2,7)[6,3] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #3, Total Nodes = 22, H-collapsed = 'false' *** +SC S-net (3,1): p7[0][0] +SC S-net (3,2): x_MINUS[0][2] + Predecessor Place: p12(3,7)[6,3] + Successor Place: p15(3,15)[15,2] +SC S-net (3,3): p11[3][1] +SC S-net (3,4): Ro_PLUSa[6][0] + Predecessor Place: p1(3,10)[12,0] + Successor Place: p9(3,5)[6,1] +SC S-net (3,5): p9[6][1] +SC S-net (3,6): Ao_PLUS[6][2] + Predecessor Place: p5(3,19)[24,1] + Successor Place: p2(3,14)[15,1] +SC S-net (3,7): p12[6][3] +SC S-net (3,8): Ri_MINUS[9][1] + Predecessor Place: p2(3,14)[15,1] + Successor Place: p1(3,10)[12,0] +SC S-net (3,9): p13[9][2] +SC S-net (3,10): p1[12][0] +SC S-net (3,11): Ai_PLUS[12][1] + Predecessor Place: p4(3,17)[21,1] + Successor Place: p7(3,1)[0,0] +SC S-net (3,12): p14[12][3] +SC S-net (3,13): Ro_PLUS[15][0] + Predecessor Place: p13(3,9)[9,2] + Successor Place: p4(3,17)[21,1] +SC S-net (3,14): p2[15][1] +SC S-net (3,15): p15[15][2] +SC S-net (3,16): x_PLUS[18][1] + Predecessor Place: p7(3,1)[0,0] + Successor Place: p14(3,12)[12,3] +SC S-net (3,17): p4[21][1] +SC S-net (3,18): Ro_MINUS[21][2] + Predecessor Place: p14(3,12)[12,3] + Successor Place: p5(3,19)[24,1] +SC S-net (3,19): p5[24][1] +SC S-net (3,20): Ro_MINUSa[24][2] + Predecessor Place: p15(3,15)[15,2] + Successor Place: p11(3,3)[3,1] +SC S-net (3,21): Ai_PLUSa[27][1] + Predecessor Place: p9(3,5)[6,1] + Successor Place: p12(3,7)[6,3] +SC S-net (3,22): Ai_MINUSa[27][2] + Predecessor Place: p11(3,3)[3,1] + Successor Place: p13(3,9)[9,2] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #3 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 24, H-Collapsed = 'false' *** +FSM (1,1): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_PLUS(0,17) + Predecessor(s): Ai_PLUS/(0,11) +FSM (1,2): Label = p10, Type = State (is Initially Inactive) + Successor(s): e/Ao_MINUS(0,21) + Predecessor(s): e/Ro_MINUSa(0,23) +FSM (1,3): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p15(0,15) + Predecessor(s): p12(0,7) +FSM (1,4): Label = e/Ro_PLUSa, Type = Trans. Function (is Output) + Successor(s): p9(0,5) + Predecessor(s): p1(0,10) +FSM (1,5): Label = p9, Type = State (is Initially Inactive) + Successor(s): Ai_PLUSa/(0,24) + Predecessor(s): e/Ro_PLUSa(0,4) +FSM (1,6): Label = e/Ao_PLUS, Type = Trans. Function (is Output) + Successor(s): p2(0,14) + Predecessor(s): p5(0,22) +FSM (1,7): Label = p12, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(0,3) + Predecessor(s): Ai_PLUSa/(0,24) +FSM (1,8): Label = p0, Type = State (is Initially Inactive) + Successor(s): e/Ro_PLUS(0,13) + Predecessor(s): Ri_PLUS/(0,18) +FSM (1,9): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p1(0,10) + Predecessor(s): p2(0,14) +FSM (1,10): Label = p1, Type = State (is Initially Inactive) + Successor(s): e/Ro_PLUSa(0,4) + Predecessor(s): Ri_MINUS/(0,9) +FSM (1,11): Label = Ai_PLUS/, Type = Trans. Function (is Input) + Successor(s): p7(0,1) + Predecessor(s): p4(0,19) +FSM (1,12): Label = p14, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUS(0,20) + Predecessor(s): e/x_PLUS(0,17) +FSM (1,13): Label = e/Ro_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(0,19) + Predecessor(s): p0(0,8) +FSM (1,14): Label = p2, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(0,9) + Predecessor(s): e/Ao_PLUS(0,6) +FSM (1,15): Label = p15, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUSa(0,23) + Predecessor(s): e/x_MINUS(0,3) +FSM (1,16): Label = p3, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(0,18) + Predecessor(s): e/Ao_MINUS(0,21) +FSM (1,17): Label = e/x_PLUS, Type = Trans. Function (is Output) + Successor(s): p14(0,12) + Predecessor(s): p7(0,1) +FSM (1,18): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(0,8) + Predecessor(s): p3(0,16) +FSM (1,19): Label = p4, Type = State (is Initially Inactive) + Successor(s): Ai_PLUS/(0,11) + Predecessor(s): e/Ro_PLUS(0,13) +FSM (1,20): Label = e/Ro_MINUS, Type = Trans. Function (is Output) + Successor(s): p5(0,22) + Predecessor(s): p14(0,12) +FSM (1,21): Label = e/Ao_MINUS, Type = Trans. Function (is Output) + Successor(s): p3(0,16) + Predecessor(s): p10(0,2) +FSM (1,22): Label = p5, Type = State (is Initially Inactive) + Successor(s): e/Ao_PLUS(0,6) + Predecessor(s): e/Ro_MINUS(0,20) +FSM (1,23): Label = e/Ro_MINUSa, Type = Trans. Function (is Output) + Successor(s): p10(0,2) + Predecessor(s): p15(0,15) +FSM (1,24): Label = Ai_PLUSa/, Type = Trans. Function (is Input) + Successor(s): p12(0,7) + Predecessor(s): p9(0,5) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 22, H-Collapsed = 'false' *** +FSM (2,1): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_PLUS(1,15) + Predecessor(s): Ai_PLUS/(1,9) +FSM (2,2): Label = p10, Type = State (is Initially Inactive) + Successor(s): e/Ao_MINUS(1,19) + Predecessor(s): e/Ro_MINUSa(1,20) +FSM (2,3): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p15(1,13) + Predecessor(s): p12(1,7) +FSM (2,4): Label = p8, Type = State (is Initially Inactive) + Successor(s): e/Ro_PLUSa(1,5) + Predecessor(s): Ai_MINUS/(1,10) +FSM (2,5): Label = e/Ro_PLUSa, Type = Trans. Function (is Output) + Successor(s): p9(1,6) + Predecessor(s): p8(1,4) +FSM (2,6): Label = p9, Type = State (is Initially Inactive) + Successor(s): Ai_PLUSa/(1,22) + Predecessor(s): e/Ro_PLUSa(1,5) +FSM (2,7): Label = p12, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(1,3) + Predecessor(s): Ai_PLUSa/(1,22) +FSM (2,8): Label = p0, Type = State (is Initially Inactive) + Successor(s): e/Ro_PLUS(1,12) + Predecessor(s): Ri_PLUS/(1,16) +FSM (2,9): Label = Ai_PLUS/, Type = Trans. Function (is Input) + Successor(s): p7(1,1) + Predecessor(s): p4(1,17) +FSM (2,10): Label = Ai_MINUS/, Type = Trans. Function (is Input) + Successor(s): p8(1,4) + Predecessor(s): p6(1,21) +FSM (2,11): Label = p14, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUS(1,18) + Predecessor(s): e/x_PLUS(1,15) +FSM (2,12): Label = e/Ro_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(1,17) + Predecessor(s): p0(1,8) +FSM (2,13): Label = p15, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUSa(1,20) + Predecessor(s): e/x_MINUS(1,3) +FSM (2,14): Label = p3, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(1,16) + Predecessor(s): e/Ao_MINUS(1,19) +FSM (2,15): Label = e/x_PLUS, Type = Trans. Function (is Output) + Successor(s): p14(1,11) + Predecessor(s): p7(1,1) +FSM (2,16): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(1,8) + Predecessor(s): p3(1,14) +FSM (2,17): Label = p4, Type = State (is Initially Inactive) + Successor(s): Ai_PLUS/(1,9) + Predecessor(s): e/Ro_PLUS(1,12) +FSM (2,18): Label = e/Ro_MINUS, Type = Trans. Function (is Output) + Successor(s): p6(1,21) + Predecessor(s): p14(1,11) +FSM (2,19): Label = e/Ao_MINUS, Type = Trans. Function (is Output) + Successor(s): p3(1,14) + Predecessor(s): p10(1,2) +FSM (2,20): Label = e/Ro_MINUSa, Type = Trans. Function (is Output) + Successor(s): p10(1,2) + Predecessor(s): p15(1,13) +FSM (2,21): Label = p6, Type = State (is Initially Inactive) + Successor(s): Ai_MINUS/(1,10) + Predecessor(s): e/Ro_MINUS(1,18) +FSM (2,22): Label = Ai_PLUSa/, Type = Trans. Function (is Input) + Successor(s): p12(1,7) + Predecessor(s): p9(1,6) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 3, Total list Entries = 22, H-Collapsed = 'false' *** +FSM (3,1): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_PLUS(2,16) + Predecessor(s): Ai_PLUS/(2,11) +FSM (3,2): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p15(2,15) + Predecessor(s): p12(2,7) +FSM (3,3): Label = p11, Type = State (is Initially Inactive) + Successor(s): Ai_MINUSa/(2,22) + Predecessor(s): e/Ro_MINUSa(2,20) +FSM (3,4): Label = e/Ro_PLUSa, Type = Trans. Function (is Output) + Successor(s): p9(2,5) + Predecessor(s): p1(2,10) +FSM (3,5): Label = p9, Type = State (is Initially Inactive) + Successor(s): Ai_PLUSa/(2,21) + Predecessor(s): e/Ro_PLUSa(2,4) +FSM (3,6): Label = e/Ao_PLUS, Type = Trans. Function (is Output) + Successor(s): p2(2,14) + Predecessor(s): p5(2,19) +FSM (3,7): Label = p12, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(2,2) + Predecessor(s): Ai_PLUSa/(2,21) +FSM (3,8): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p1(2,10) + Predecessor(s): p2(2,14) +FSM (3,9): Label = p13, Type = State (is Initially Active) + Successor(s): e/Ro_PLUS(2,13) + Predecessor(s): Ai_MINUSa/(2,22) +FSM (3,10): Label = p1, Type = State (is Initially Inactive) + Successor(s): e/Ro_PLUSa(2,4) + Predecessor(s): Ri_MINUS/(2,8) +FSM (3,11): Label = Ai_PLUS/, Type = Trans. Function (is Input) + Successor(s): p7(2,1) + Predecessor(s): p4(2,17) +FSM (3,12): Label = p14, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUS(2,18) + Predecessor(s): e/x_PLUS(2,16) +FSM (3,13): Label = e/Ro_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(2,17) + Predecessor(s): p13(2,9) +FSM (3,14): Label = p2, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(2,8) + Predecessor(s): e/Ao_PLUS(2,6) +FSM (3,15): Label = p15, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUSa(2,20) + Predecessor(s): e/x_MINUS(2,2) +FSM (3,16): Label = e/x_PLUS, Type = Trans. Function (is Output) + Successor(s): p14(2,12) + Predecessor(s): p7(2,1) +FSM (3,17): Label = p4, Type = State (is Initially Inactive) + Successor(s): Ai_PLUS/(2,11) + Predecessor(s): e/Ro_PLUS(2,13) +FSM (3,18): Label = e/Ro_MINUS, Type = Trans. Function (is Output) + Successor(s): p5(2,19) + Predecessor(s): p14(2,12) +FSM (3,19): Label = p5, Type = State (is Initially Inactive) + Successor(s): e/Ao_PLUS(2,6) + Predecessor(s): e/Ro_MINUS(2,18) +FSM (3,20): Label = e/Ro_MINUSa, Type = Trans. Function (is Output) + Successor(s): p11(2,3) + Predecessor(s): p15(2,15) +FSM (3,21): Label = Ai_PLUSa/, Type = Trans. Function (is Input) + Successor(s): p12(2,7) + Predecessor(s): p9(2,5) +FSM (3,22): Label = Ai_MINUSa/, Type = Trans. Function (is Input) + Successor(s): p13(2,9) + Predecessor(s): p11(2,3) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/half_MG/AsyncMSFSMs/fsm_afsm.afsm b/examples/half_MG/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..d2a5a2d --- /dev/null +++ b/examples/half_MG/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,38 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p9: e_Ao_MINUS e_Ao_MINUS_p1_FSM3_TB p2 +p4: e_Ro_MINUS e_Ro_MINUS_p4_FSM2_TB e_Ro_MINUS_p10_FSM4_TB p9 +p7*: e_Ro_PLUS e_Ro_PLUS_p6_FSM2_TB e_Ro_PLUS_p7_FSM3_TB e_Ro_PLUS_p6_FSM4_TB p3 +p3: Ai_PLUS_ Ai_PLUS__p3_FSM2_TB p4 +p2: Ri_PLUS_ Ri_PLUS__p2_FSM3_TB p7 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p5: Ai_MINUS_ Ai_MINUS__p5_FSM4_TB p6 +p4: e_Ro_MINUS e_Ro_MINUS_p4_FSM1_TB e_Ro_MINUS_p10_FSM4_TB p5 +p3: Ai_PLUS_ Ai_PLUS__p3_FSM1_TB p4 +p6*: e_Ro_PLUS e_Ro_PLUS_p7_FSM1_TB e_Ro_PLUS_p7_FSM3_TB e_Ro_PLUS_p6_FSM4_TB p3 +### End of FSM #02 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#03 Declaration ### +p1: e_Ao_MINUS e_Ao_MINUS_p9_FSM1_TB p2 +p8: e_Ao_PLUS e_Ao_PLUS_p8_FSM4_TB p0 +p0: Ri_MINUS_ p1 +p7*: e_Ro_PLUS e_Ro_PLUS_p7_FSM1_TB e_Ro_PLUS_p6_FSM2_TB e_Ro_PLUS_p6_FSM4_TB p8 +p2: Ri_PLUS_ Ri_PLUS__p2_FSM1_TB p7 +### End of FSM #03 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#04 Declaration ### +p5: Ai_MINUS_ Ai_MINUS__p5_FSM2_TB p6 +p8: e_Ao_PLUS e_Ao_PLUS_p8_FSM3_TB p10 +p10: e_Ro_MINUS e_Ro_MINUS_p4_FSM1_TB e_Ro_MINUS_p4_FSM2_TB p5 +p6*: e_Ro_PLUS e_Ro_PLUS_p7_FSM1_TB e_Ro_PLUS_p6_FSM2_TB e_Ro_PLUS_p7_FSM3_TB p8 +### End of FSM #04 Declaration ### + diff --git a/examples/half_MG/AsyncMSFSMs/msfsms_afsm.v b/examples/half_MG/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..c21e9b5 --- /dev/null +++ b/examples/half_MG/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,96 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + Ri_PLUS, + Ro_PLUS, + Ro_MINUS, + Ri_MINUS, + Ai_PLUS, + Ao_PLUS, + Ao_MINUS, + Ai_MINUS); + + input reset; + input Ri_PLUS; + output Ro_PLUS; + output Ro_MINUS; + input Ri_MINUS; + input Ai_PLUS; + output Ao_PLUS; + output Ao_MINUS; + input Ai_MINUS; + + wire e_Ro_PLUS_FSM1out, e_Ro_MINUS_FSM1out, e_Ao_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p9_FSM1out, p4_FSM1out, p7_FSM1out, p3_FSM1out, p2_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_Ro_PLUS_FSM2out, e_Ro_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p5_FSM2out, p4_FSM2out, p3_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_Ro_PLUS_FSM3out, e_Ao_PLUS_FSM3out, e_Ao_MINUS_FSM3out; // Regular output signals of FSM3 // + wire p1_FSM3out, p8_FSM3out, p0_FSM3out, p7_FSM3out, p2_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_Ro_PLUS_FSM4out, e_Ro_MINUS_FSM4out, e_Ao_PLUS_FSM4out; // Regular output signals of FSM4 // + wire p5_FSM4out, p8_FSM4out, p10_FSM4out, p6_FSM4out; // State Synchronisation output signals of FSM4 // + + assign Ro_PLUS = e_Ro_PLUS_FSM1out & e_Ro_PLUS_FSM2out & e_Ro_PLUS_FSM3out & e_Ro_PLUS_FSM4out; + assign Ro_MINUS = e_Ro_MINUS_FSM1out & e_Ro_MINUS_FSM2out & e_Ro_MINUS_FSM4out; + assign Ao_PLUS = e_Ao_PLUS_FSM3out & e_Ao_PLUS_FSM4out; + assign Ao_MINUS = e_Ao_MINUS_FSM1out & e_Ao_MINUS_FSM3out; + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p2_FSM3_TB(p2_FSM3out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p3_FSM2_TB(p3_FSM2out), + .e_Ro_PLUS(p7_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ro_MINUS(p4_FSM1out), .e_Ro_MINUS_p4_FSM2_TB(p4_FSM2out), .e_Ro_MINUS_p10_FSM4_TB(p10_FSM4out), + .e_Ao_MINUS(p9_FSM1out), .e_Ao_MINUS_p1_FSM3_TB(p1_FSM3out), + .e/Ro_PLUS(e/Ro_PLUS_FSM1out), + .e/Ro_MINUS(e/Ro_MINUS_FSM1out), + .e/Ao_MINUS(e/Ao_MINUS_FSM1out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p3_FSM1_TB(p3_FSM1out), + .Ai_MINUS_(Ai_MINUS), .Ai_MINUS__p5_FSM4_TB(p5_FSM4out), + .e_Ro_PLUS(p6_FSM2out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ro_MINUS(p4_FSM2out), .e_Ro_MINUS_p4_FSM1_TB(p4_FSM1out), .e_Ro_MINUS_p10_FSM4_TB(p10_FSM4out), + .e/Ro_PLUS(e/Ro_PLUS_FSM2out), + .e/Ro_MINUS(e/Ro_MINUS_FSM2out) + ); + + + fsm_afsm_03 fsm_afsm_03_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p2_FSM1_TB(p2_FSM1out), + .Ri_MINUS_(Ri_MINUS), + .e_Ro_PLUS(p7_FSM3out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ao_PLUS(p8_FSM3out), .e_Ao_PLUS_p8_FSM4_TB(p8_FSM4out), + .e_Ao_MINUS(p1_FSM3out), .e_Ao_MINUS_p9_FSM1_TB(p9_FSM1out), + .e/Ro_PLUS(e/Ro_PLUS_FSM3out), + .e/Ao_PLUS(e/Ao_PLUS_FSM3out), + .e/Ao_MINUS(e/Ao_MINUS_FSM3out) + ); + + + fsm_afsm_04 fsm_afsm_04_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ai_MINUS_(Ai_MINUS), .Ai_MINUS__p5_FSM2_TB(p5_FSM2out), + .e_Ro_PLUS(p6_FSM4out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(p10_FSM4out), .e_Ro_MINUS_p4_FSM1_TB(p4_FSM1out), .e_Ro_MINUS_p4_FSM2_TB(p4_FSM2out), + .e_Ao_PLUS(p8_FSM4out), .e_Ao_PLUS_p8_FSM3_TB(p8_FSM3out), + .e/Ro_PLUS(e/Ro_PLUS_FSM4out), + .e/Ro_MINUS(e/Ro_MINUS_FSM4out), + .e/Ao_PLUS(e/Ao_PLUS_FSM4out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/half_MG/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/half_MG/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..3deba2d --- /dev/null +++ b/examples/half_MG/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,628 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p2_FSM3_TB, + Ai_PLUS_, Ai_PLUS__p3_FSM2_TB, + e_Ro_PLUS, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB, + e_Ro_MINUS, e_Ro_MINUS_p4_FSM2_TB, e_Ro_MINUS_p10_FSM4_TB, + e_Ao_MINUS, e_Ao_MINUS_p1_FSM3_TB, + p9, + p4, + p7, + p3, + p2 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ai_PLUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p2_FSM3_TB; + input Ai_PLUS__p3_FSM2_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ro_MINUS; + output e_Ao_MINUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB; + input e_Ro_MINUS_p4_FSM2_TB, e_Ro_MINUS_p10_FSM4_TB; + input e_Ao_MINUS_p1_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p9; + output p4; + output p7; + output p3; + output p2; + + reg e_Ro_PLUS; + reg e_Ro_MINUS; + reg e_Ao_MINUS; + wire p9; + wire p4; + wire p7; + wire p3; + wire p2; + + wire Ri_PLUS__TB_sync; + wire Ai_PLUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p2_FSM3_TB; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p3_FSM2_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p6_FSM2_TB & e_Ro_PLUS_p7_FSM3_TB & e_Ro_PLUS_p6_FSM4_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p4_FSM2_TB & e_Ro_MINUS_p10_FSM4_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p1_FSM3_TB; + + parameter p9_1HOT_ENCODING = 5'd1; // 5'b00001 // + parameter p9_1HOT_CASEX_ENCODING = 5'bxxxx1; // 5'b00001 // + parameter p4_1HOT_ENCODING = 5'd2; // 5'b00010 // + parameter p4_1HOT_CASEX_ENCODING = 5'bxxx1x; // 5'b00010 // + parameter p7_1HOT_ENCODING = 5'd4; // 5'b00100 // + parameter p7_1HOT_CASEX_ENCODING = 5'bxx1xx; // 5'b00100 // + parameter p3_1HOT_ENCODING = 5'd8; // 5'b01000 // + parameter p3_1HOT_CASEX_ENCODING = 5'bx1xxx; // 5'b01000 // + parameter p2_1HOT_ENCODING = 5'd16; // 5'b10000 // + parameter p2_1HOT_CASEX_ENCODING = 5'b1xxxx; // 5'b10000 // + + reg [4 : 0] state; + reg [4 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p7_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + state[3] <= 1'b0; + state[4] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ai_PLUS__TB_sync or e_Ro_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_MINUS = 1'b0; + + casex (state) + 5'bxxxx1: // p9_1HOT_ENCODING: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[4] = 1'b1; + end + end + + 5'bxxx1x: // p4_1HOT_ENCODING: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 5'bxx1xx: // p7_1HOT_ENCODING: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[3] = 1'b1; + end + end + + 5'bx1xxx: // p3_1HOT_ENCODING: // + begin + if (Ai_PLUS__TB_sync) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + 5'b1xxxx: // p2_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 5'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + Ai_PLUS_, Ai_PLUS__p3_FSM1_TB, + Ai_MINUS_, Ai_MINUS__p5_FSM4_TB, + e_Ro_PLUS, e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB, + e_Ro_MINUS, e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p10_FSM4_TB, + p5, + p4, + p3, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ai_PLUS_; + input Ai_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ai_PLUS__p3_FSM1_TB; + input Ai_MINUS__p5_FSM4_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ro_MINUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB; + input e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p10_FSM4_TB; + + // FSMs' Synchronisation output Signals // + output p5; + output p4; + output p3; + output p6; + + reg e_Ro_PLUS; + reg e_Ro_MINUS; + wire p5; + wire p4; + wire p3; + wire p6; + + wire Ai_PLUS__TB_sync; + wire Ai_MINUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p3_FSM1_TB; + assign Ai_MINUS__TB_sync = Ai_MINUS_ & Ai_MINUS__p5_FSM4_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p7_FSM1_TB & e_Ro_PLUS_p7_FSM3_TB & e_Ro_PLUS_p6_FSM4_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p4_FSM1_TB & e_Ro_MINUS_p10_FSM4_TB; + + parameter p5_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p5_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p4_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p4_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p3_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p3_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p6_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p6_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p6_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ai_PLUS__TB_sync or Ai_MINUS__TB_sync or e_Ro_PLUS_TB_sync or e_Ro_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + + casex (state) + 4'bxxx1: // p5_1HOT_ENCODING: // + begin + if (Ai_MINUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bxx1x: // p4_1HOT_ENCODING: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'bx1xx: // p3_1HOT_ENCODING: // + begin + if (Ai_PLUS__TB_sync) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + 4'b1xxx: // p6_1HOT_ENCODING: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_03 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p2_FSM1_TB, + Ri_MINUS_, + e_Ro_PLUS, e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p6_FSM4_TB, + e_Ao_PLUS, e_Ao_PLUS_p8_FSM4_TB, + e_Ao_MINUS, e_Ao_MINUS_p9_FSM1_TB, + p1, + p8, + p7, + p2 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p2_FSM1_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ao_PLUS; + output e_Ao_MINUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p6_FSM4_TB; + input e_Ao_PLUS_p8_FSM4_TB; + input e_Ao_MINUS_p9_FSM1_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p8; + output p7; + output p2; + + reg e_Ro_PLUS; + reg e_Ao_PLUS; + reg e_Ao_MINUS; + wire p1; + wire p8; + wire p7; + wire p2; + + wire Ri_PLUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ao_PLUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p2_FSM1_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p7_FSM1_TB & e_Ro_PLUS_p6_FSM2_TB & e_Ro_PLUS_p6_FSM4_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p8_FSM4_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p9_FSM1_TB; + + parameter p1_1HOT_ENCODING = 5'd1; // 5'b00001 // + parameter p1_1HOT_CASEX_ENCODING = 5'bxxxx1; // 5'b00001 // + parameter p8_1HOT_ENCODING = 5'd2; // 5'b00010 // + parameter p8_1HOT_CASEX_ENCODING = 5'bxxx1x; // 5'b00010 // + parameter p0_1HOT_ENCODING = 5'd4; // 5'b00100 // + parameter p0_1HOT_CASEX_ENCODING = 5'bxx1xx; // 5'b00100 // + parameter p7_1HOT_ENCODING = 5'd8; // 5'b01000 // + parameter p7_1HOT_CASEX_ENCODING = 5'bx1xxx; // 5'b01000 // + parameter p2_1HOT_ENCODING = 5'd16; // 5'b10000 // + parameter p2_1HOT_CASEX_ENCODING = 5'b1xxxx; // 5'b10000 // + + reg [4 : 0] state; + reg [4 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p7_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + state[4] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS_ or e_Ro_PLUS_TB_sync or e_Ao_PLUS_TB_sync or e_Ao_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ao_PLUS = 1'b0; + e_Ao_MINUS = 1'b0; + + casex (state) + 5'bxxxx1: // p1_1HOT_ENCODING: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[4] = 1'b1; + end + end + + 5'bxxx1x: // p8_1HOT_ENCODING: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + end + + 5'bxx1xx: // p0_1HOT_ENCODING: // + begin + if (Ri_MINUS_) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 5'bx1xxx: // p7_1HOT_ENCODING: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + 5'b1xxxx: // p2_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + default: + begin + next_state = 5'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_04 ( + clk, + reset, + Ai_MINUS_, Ai_MINUS__p5_FSM2_TB, + e_Ro_PLUS, e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB, + e_Ro_MINUS, e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p4_FSM2_TB, + e_Ao_PLUS, e_Ao_PLUS_p8_FSM3_TB, + p5, + p8, + p10, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ai_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ai_MINUS__p5_FSM2_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ro_MINUS; + output e_Ao_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB; + input e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p4_FSM2_TB; + input e_Ao_PLUS_p8_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p5; + output p8; + output p10; + output p6; + + reg e_Ro_PLUS; + reg e_Ro_MINUS; + reg e_Ao_PLUS; + wire p5; + wire p8; + wire p10; + wire p6; + + wire Ai_MINUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_PLUS_TB_sync; + assign Ai_MINUS__TB_sync = Ai_MINUS_ & Ai_MINUS__p5_FSM2_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p7_FSM1_TB & e_Ro_PLUS_p6_FSM2_TB & e_Ro_PLUS_p7_FSM3_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p4_FSM1_TB & e_Ro_MINUS_p4_FSM2_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p8_FSM3_TB; + + parameter p5_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p5_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p8_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p8_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p10_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p10_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p6_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p6_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p6_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p10 = (state == p10_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ai_MINUS__TB_sync or e_Ro_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_PLUS = 1'b0; + + casex (state) + 4'bxxx1: // p5_1HOT_ENCODING: // + begin + if (Ai_MINUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bxx1x: // p8_1HOT_ENCODING: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + // next_state = p10_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + end + + 4'bx1xx: // p10_1HOT_ENCODING: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'b1xxx: // p6_1HOT_ENCODING: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + diff --git a/examples/half_MG/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/half_MG/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..547080f --- /dev/null +++ b/examples/half_MG/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,556 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p2_FSM3_TB, + Ai_PLUS_, Ai_PLUS__p3_FSM2_TB, + e_Ro_PLUS, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB, + e_Ro_MINUS, e_Ro_MINUS_p4_FSM2_TB, e_Ro_MINUS_p10_FSM4_TB, + e_Ao_MINUS, e_Ao_MINUS_p1_FSM3_TB, + p9, + p4, + p7, + p3, + p2 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ai_PLUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p2_FSM3_TB; + input Ai_PLUS__p3_FSM2_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ro_MINUS; + output e_Ao_MINUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB; + input e_Ro_MINUS_p4_FSM2_TB, e_Ro_MINUS_p10_FSM4_TB; + input e_Ao_MINUS_p1_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p9; + output p4; + output p7; + output p3; + output p2; + + reg e_Ro_PLUS; + reg e_Ro_MINUS; + reg e_Ao_MINUS; + wire p9; + wire p4; + wire p7; + wire p3; + wire p2; + + wire Ri_PLUS__TB_sync; + wire Ai_PLUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p2_FSM3_TB; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p3_FSM2_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p6_FSM2_TB & e_Ro_PLUS_p7_FSM3_TB & e_Ro_PLUS_p6_FSM4_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p4_FSM2_TB & e_Ro_MINUS_p10_FSM4_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p1_FSM3_TB; + + parameter p9_1HOT_ENCODING = 5'd1; // 5'b00001 // + parameter p4_1HOT_ENCODING = 5'd2; // 5'b00010 // + parameter p7_1HOT_ENCODING = 5'd4; // 5'b00100 // + parameter p3_1HOT_ENCODING = 5'd8; // 5'b01000 // + parameter p2_1HOT_ENCODING = 5'd16; // 5'b10000 // + + reg [4 : 0] state; + reg [4 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p7_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ai_PLUS__TB_sync or e_Ro_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_MINUS = 1'b0; + + case (state) + p9_1HOT_ENCODING: // 5'b00001: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + next_state = p2_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 5'b00010: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 5'b00100: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + next_state = p3_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 5'b01000: // + begin + if (Ai_PLUS__TB_sync) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 5'b10000: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 5'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + Ai_PLUS_, Ai_PLUS__p3_FSM1_TB, + Ai_MINUS_, Ai_MINUS__p5_FSM4_TB, + e_Ro_PLUS, e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB, + e_Ro_MINUS, e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p10_FSM4_TB, + p5, + p4, + p3, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ai_PLUS_; + input Ai_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ai_PLUS__p3_FSM1_TB; + input Ai_MINUS__p5_FSM4_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ro_MINUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p7_FSM3_TB, e_Ro_PLUS_p6_FSM4_TB; + input e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p10_FSM4_TB; + + // FSMs' Synchronisation output Signals // + output p5; + output p4; + output p3; + output p6; + + reg e_Ro_PLUS; + reg e_Ro_MINUS; + wire p5; + wire p4; + wire p3; + wire p6; + + wire Ai_PLUS__TB_sync; + wire Ai_MINUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + assign Ai_PLUS__TB_sync = Ai_PLUS_ & Ai_PLUS__p3_FSM1_TB; + assign Ai_MINUS__TB_sync = Ai_MINUS_ & Ai_MINUS__p5_FSM4_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p7_FSM1_TB & e_Ro_PLUS_p7_FSM3_TB & e_Ro_PLUS_p6_FSM4_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p4_FSM1_TB & e_Ro_MINUS_p10_FSM4_TB; + + parameter p5_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p4_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p3_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p6_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p6_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ai_PLUS__TB_sync or Ai_MINUS__TB_sync or e_Ro_PLUS_TB_sync or e_Ro_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + + case (state) + p5_1HOT_ENCODING: // 4'b0001: // + begin + if (Ai_MINUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 4'b0010: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 4'b0100: // + begin + if (Ai_PLUS__TB_sync) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 4'b1000: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + next_state = p3_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_03 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p2_FSM1_TB, + Ri_MINUS_, + e_Ro_PLUS, e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p6_FSM4_TB, + e_Ao_PLUS, e_Ao_PLUS_p8_FSM4_TB, + e_Ao_MINUS, e_Ao_MINUS_p9_FSM1_TB, + p1, + p8, + p7, + p2 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p2_FSM1_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ao_PLUS; + output e_Ao_MINUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p6_FSM4_TB; + input e_Ao_PLUS_p8_FSM4_TB; + input e_Ao_MINUS_p9_FSM1_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p8; + output p7; + output p2; + + reg e_Ro_PLUS; + reg e_Ao_PLUS; + reg e_Ao_MINUS; + wire p1; + wire p8; + wire p7; + wire p2; + + wire Ri_PLUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ao_PLUS_TB_sync; + wire e_Ao_MINUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p2_FSM1_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p7_FSM1_TB & e_Ro_PLUS_p6_FSM2_TB & e_Ro_PLUS_p6_FSM4_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p8_FSM4_TB; + assign e_Ao_MINUS_TB_sync = e_Ao_MINUS_p9_FSM1_TB; + + parameter p1_1HOT_ENCODING = 5'd1; // 5'b00001 // + parameter p8_1HOT_ENCODING = 5'd2; // 5'b00010 // + parameter p0_1HOT_ENCODING = 5'd4; // 5'b00100 // + parameter p7_1HOT_ENCODING = 5'd8; // 5'b01000 // + parameter p2_1HOT_ENCODING = 5'd16; // 5'b10000 // + + reg [4 : 0] state; + reg [4 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p7_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS_ or e_Ro_PLUS_TB_sync or e_Ao_PLUS_TB_sync or e_Ao_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ao_PLUS = 1'b0; + e_Ao_MINUS = 1'b0; + + case (state) + p1_1HOT_ENCODING: // 5'b00001: // + begin + if (e_Ao_MINUS_TB_sync) + begin + e_Ao_MINUS = 1'b1; + next_state = p2_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 5'b00010: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + next_state = p0_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 5'b00100: // + begin + if (Ri_MINUS_) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 5'b01000: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 5'b10000: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 5'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_04 ( + clk, + reset, + Ai_MINUS_, Ai_MINUS__p5_FSM2_TB, + e_Ro_PLUS, e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB, + e_Ro_MINUS, e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p4_FSM2_TB, + e_Ao_PLUS, e_Ao_PLUS_p8_FSM3_TB, + p5, + p8, + p10, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ai_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ai_MINUS__p5_FSM2_TB; + + // Regular output Signals // + output e_Ro_PLUS; + output e_Ro_MINUS; + output e_Ao_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro_PLUS_p7_FSM1_TB, e_Ro_PLUS_p6_FSM2_TB, e_Ro_PLUS_p7_FSM3_TB; + input e_Ro_MINUS_p4_FSM1_TB, e_Ro_MINUS_p4_FSM2_TB; + input e_Ao_PLUS_p8_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p5; + output p8; + output p10; + output p6; + + reg e_Ro_PLUS; + reg e_Ro_MINUS; + reg e_Ao_PLUS; + wire p5; + wire p8; + wire p10; + wire p6; + + wire Ai_MINUS__TB_sync; + wire e_Ro_PLUS_TB_sync; + wire e_Ro_MINUS_TB_sync; + wire e_Ao_PLUS_TB_sync; + assign Ai_MINUS__TB_sync = Ai_MINUS_ & Ai_MINUS__p5_FSM2_TB; + assign e_Ro_PLUS_TB_sync = e_Ro_PLUS_p7_FSM1_TB & e_Ro_PLUS_p6_FSM2_TB & e_Ro_PLUS_p7_FSM3_TB; + assign e_Ro_MINUS_TB_sync = e_Ro_MINUS_p4_FSM1_TB & e_Ro_MINUS_p4_FSM2_TB; + assign e_Ao_PLUS_TB_sync = e_Ao_PLUS_p8_FSM3_TB; + + parameter p5_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p8_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p10_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p6_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p6_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p10 = (state == p10_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ai_MINUS__TB_sync or e_Ro_PLUS_TB_sync or e_Ro_MINUS_TB_sync or e_Ao_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro_PLUS = 1'b0; + e_Ro_MINUS = 1'b0; + e_Ao_PLUS = 1'b0; + + case (state) + p5_1HOT_ENCODING: // 4'b0001: // + begin + if (Ai_MINUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 4'b0010: // + begin + if (e_Ao_PLUS_TB_sync) + begin + e_Ao_PLUS = 1'b1; + next_state = p10_1HOT_ENCODING; + end + end + + p10_1HOT_ENCODING: // 4'b0100: // + begin + if (e_Ro_MINUS_TB_sync) + begin + e_Ro_MINUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 4'b1000: // + begin + if (e_Ro_PLUS_TB_sync) + begin + e_Ro_PLUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + diff --git a/examples/half_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/half_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..651ae0d --- /dev/null +++ b/examples/half_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,98 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + Ri_PLUS, + Ro_PLUS, + Ro_MINUS, + Ri_MINUS, + Ai_PLUS, + Ao_PLUS, + Ao_MINUS, + Ai_MINUS); + + input clk; + input reset; + input Ri_PLUS; + output Ro_PLUS; + output Ro_MINUS; + input Ri_MINUS; + input Ai_PLUS; + output Ao_PLUS; + output Ao_MINUS; + input Ai_MINUS; + + wire e_Ro_PLUS_FSM1out, e_Ro_MINUS_FSM1out, e_Ao_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p9_FSM1out, p4_FSM1out, p7_FSM1out, p3_FSM1out, p2_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_Ro_PLUS_FSM2out, e_Ro_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p5_FSM2out, p4_FSM2out, p3_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_Ro_PLUS_FSM3out, e_Ao_PLUS_FSM3out, e_Ao_MINUS_FSM3out; // Regular output signals of FSM3 // + wire p1_FSM3out, p8_FSM3out, p0_FSM3out, p7_FSM3out, p2_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_Ro_PLUS_FSM4out, e_Ro_MINUS_FSM4out, e_Ao_PLUS_FSM4out; // Regular output signals of FSM4 // + wire p5_FSM4out, p8_FSM4out, p10_FSM4out, p6_FSM4out; // State Synchronisation output signals of FSM4 // + + assign Ro_PLUS = e_Ro_PLUS_FSM1out & e_Ro_PLUS_FSM2out & e_Ro_PLUS_FSM3out & e_Ro_PLUS_FSM4out; + assign Ro_MINUS = e_Ro_MINUS_FSM1out & e_Ro_MINUS_FSM2out & e_Ro_MINUS_FSM4out; + assign Ao_PLUS = e_Ao_PLUS_FSM3out & e_Ao_PLUS_FSM4out; + assign Ao_MINUS = e_Ao_MINUS_FSM1out & e_Ao_MINUS_FSM3out; + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p2_FSM3_TB(p2_FSM3out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p3_FSM2_TB(p3_FSM2out), + .e_Ro_PLUS(e_Ro_PLUS_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ro_MINUS(e_Ro_MINUS_FSM1out), .e_Ro_MINUS_p4_FSM2_TB(p4_FSM2out), .e_Ro_MINUS_p10_FSM4_TB(p10_FSM4out), + .e_Ao_MINUS(e_Ao_MINUS_FSM1out), .e_Ao_MINUS_p1_FSM3_TB(p1_FSM3out), + .p9(p9_FSM1out), + .p4(p4_FSM1out), + .p7(p7_FSM1out), + .p3(p3_FSM1out), + .p2(p2_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p3_FSM1_TB(p3_FSM1out), + .Ai_MINUS_(Ai_MINUS), .Ai_MINUS__p5_FSM4_TB(p5_FSM4out), + .e_Ro_PLUS(e_Ro_PLUS_FSM2out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ro_MINUS(e_Ro_MINUS_FSM2out), .e_Ro_MINUS_p4_FSM1_TB(p4_FSM1out), .e_Ro_MINUS_p10_FSM4_TB(p10_FSM4out), + .p5(p5_FSM2out), + .p4(p4_FSM2out), + .p3(p3_FSM2out), + .p6(p6_FSM2out) + ); + + + fsm_mealy_behav_03 fsm_mealy_behav_03_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p2_FSM1_TB(p2_FSM1out), + .Ri_MINUS_(Ri_MINUS), + .e_Ro_PLUS(e_Ro_PLUS_FSM3out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ao_PLUS(e_Ao_PLUS_FSM3out), .e_Ao_PLUS_p8_FSM4_TB(p8_FSM4out), + .e_Ao_MINUS(e_Ao_MINUS_FSM3out), .e_Ao_MINUS_p9_FSM1_TB(p9_FSM1out), + .p1(p1_FSM3out), + .p8(p8_FSM3out), + .p7(p7_FSM3out), + .p2(p2_FSM3out) + ); + + + fsm_mealy_behav_04 fsm_mealy_behav_04_inst ( + .clk(clk), + .reset(reset), + .Ai_MINUS_(Ai_MINUS), .Ai_MINUS__p5_FSM2_TB(p5_FSM2out), + .e_Ro_PLUS(e_Ro_PLUS_FSM4out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(e_Ro_MINUS_FSM4out), .e_Ro_MINUS_p4_FSM1_TB(p4_FSM1out), .e_Ro_MINUS_p4_FSM2_TB(p4_FSM2out), + .e_Ao_PLUS(e_Ao_PLUS_FSM4out), .e_Ao_PLUS_p8_FSM3_TB(p8_FSM3out), + .p5(p5_FSM4out), + .p8(p8_FSM4out), + .p10(p10_FSM4out), + .p6(p6_FSM4out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/half_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/half_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..7850c7f --- /dev/null +++ b/examples/half_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,98 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + Ri_PLUS, + Ro_PLUS, + Ro_MINUS, + Ri_MINUS, + Ai_PLUS, + Ao_PLUS, + Ao_MINUS, + Ai_MINUS); + + input clk; + input reset; + input Ri_PLUS; + output Ro_PLUS; + output Ro_MINUS; + input Ri_MINUS; + input Ai_PLUS; + output Ao_PLUS; + output Ao_MINUS; + input Ai_MINUS; + + wire e_Ro_PLUS_FSM1out, e_Ro_MINUS_FSM1out, e_Ao_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p9_FSM1out, p4_FSM1out, p7_FSM1out, p3_FSM1out, p2_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_Ro_PLUS_FSM2out, e_Ro_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p5_FSM2out, p4_FSM2out, p3_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_Ro_PLUS_FSM3out, e_Ao_PLUS_FSM3out, e_Ao_MINUS_FSM3out; // Regular output signals of FSM3 // + wire p1_FSM3out, p8_FSM3out, p0_FSM3out, p7_FSM3out, p2_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_Ro_PLUS_FSM4out, e_Ro_MINUS_FSM4out, e_Ao_PLUS_FSM4out; // Regular output signals of FSM4 // + wire p5_FSM4out, p8_FSM4out, p10_FSM4out, p6_FSM4out; // State Synchronisation output signals of FSM4 // + + assign Ro_PLUS = e_Ro_PLUS_FSM1out & e_Ro_PLUS_FSM2out & e_Ro_PLUS_FSM3out & e_Ro_PLUS_FSM4out; + assign Ro_MINUS = e_Ro_MINUS_FSM1out & e_Ro_MINUS_FSM2out & e_Ro_MINUS_FSM4out; + assign Ao_PLUS = e_Ao_PLUS_FSM3out & e_Ao_PLUS_FSM4out; + assign Ao_MINUS = e_Ao_MINUS_FSM1out & e_Ao_MINUS_FSM3out; + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p2_FSM3_TB(p2_FSM3out), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p3_FSM2_TB(p3_FSM2out), + .e_Ro_PLUS(e_Ro_PLUS_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ro_MINUS(e_Ro_MINUS_FSM1out), .e_Ro_MINUS_p4_FSM2_TB(p4_FSM2out), .e_Ro_MINUS_p10_FSM4_TB(p10_FSM4out), + .e_Ao_MINUS(e_Ao_MINUS_FSM1out), .e_Ao_MINUS_p1_FSM3_TB(p1_FSM3out), + .p9(p9_FSM1out), + .p4(p4_FSM1out), + .p7(p7_FSM1out), + .p3(p3_FSM1out), + .p2(p2_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .Ai_PLUS_(Ai_PLUS), .Ai_PLUS__p3_FSM1_TB(p3_FSM1out), + .Ai_MINUS_(Ai_MINUS), .Ai_MINUS__p5_FSM4_TB(p5_FSM4out), + .e_Ro_PLUS(e_Ro_PLUS_FSM2out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ro_MINUS(e_Ro_MINUS_FSM2out), .e_Ro_MINUS_p4_FSM1_TB(p4_FSM1out), .e_Ro_MINUS_p10_FSM4_TB(p10_FSM4out), + .p5(p5_FSM2out), + .p4(p4_FSM2out), + .p3(p3_FSM2out), + .p6(p6_FSM2out) + ); + + + fsm_mealy_synth_03 fsm_mealy_synth_03_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p2_FSM1_TB(p2_FSM1out), + .Ri_MINUS_(Ri_MINUS), + .e_Ro_PLUS(e_Ro_PLUS_FSM3out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p6_FSM4_TB(p6_FSM4out), + .e_Ao_PLUS(e_Ao_PLUS_FSM3out), .e_Ao_PLUS_p8_FSM4_TB(p8_FSM4out), + .e_Ao_MINUS(e_Ao_MINUS_FSM3out), .e_Ao_MINUS_p9_FSM1_TB(p9_FSM1out), + .p1(p1_FSM3out), + .p8(p8_FSM3out), + .p7(p7_FSM3out), + .p2(p2_FSM3out) + ); + + + fsm_mealy_synth_04 fsm_mealy_synth_04_inst ( + .clk(clk), + .reset(reset), + .Ai_MINUS_(Ai_MINUS), .Ai_MINUS__p5_FSM2_TB(p5_FSM2out), + .e_Ro_PLUS(e_Ro_PLUS_FSM4out), .e_Ro_PLUS_p7_FSM1_TB(p7_FSM1out), .e_Ro_PLUS_p6_FSM2_TB(p6_FSM2out), .e_Ro_PLUS_p7_FSM3_TB(p7_FSM3out), + .e_Ro_MINUS(e_Ro_MINUS_FSM4out), .e_Ro_MINUS_p4_FSM1_TB(p4_FSM1out), .e_Ro_MINUS_p4_FSM2_TB(p4_FSM2out), + .e_Ao_PLUS(e_Ao_PLUS_FSM4out), .e_Ao_PLUS_p8_FSM3_TB(p8_FSM3out), + .p5(p5_FSM4out), + .p8(p8_FSM4out), + .p10(p10_FSM4out), + .p6(p6_FSM4out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/half_MG/half.petrinet.MG.workcraft.g b/examples/half_MG/half.petrinet.MG.workcraft.g new file mode 100644 index 0000000..8de0ceb --- /dev/null +++ b/examples/half_MG/half.petrinet.MG.workcraft.g @@ -0,0 +1,26 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.4 +.model half +.inputs Ri_MINUS Ri_PLUS Ai_MINUS Ai_PLUS +.outputs Ao_MINUS Ao_PLUS Ro_MINUS Ro_PLUS +.graph +Ao_PLUS p0 p10 +Ri_MINUS p1 +Ao_MINUS p2 +Ri_PLUS p7 +Ro_PLUS p3 p8 +Ai_PLUS p4 +Ro_MINUS p5 p9 +Ai_MINUS p6 +p0 Ri_MINUS +p1 Ao_MINUS +p2 Ri_PLUS +p3 Ai_PLUS +p4 Ro_MINUS +p5 Ai_MINUS +p6 Ro_PLUS +p7 Ro_PLUS +p8 Ao_PLUS +p9 Ao_MINUS +p10 Ro_MINUS +.marking {p6 p7} +.end diff --git a/examples/half_MG/msfsms_tool_bm.log b/examples/half_MG/msfsms_tool_bm.log new file mode 100644 index 0000000..d43220b --- /dev/null +++ b/examples/half_MG/msfsms_tool_bm.log @@ -0,0 +1,297 @@ +--------------------------------------------------------------------------- +Benchmark: half_MG/half.petrinet.MG.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/half_MG/half.petrinet.MG.workcraft.g +INFO: Total Nodes : 19 +INFO: Total Transitions : 8 +INFO: Total Places : 11 +INFO: Total Edges : 22 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [1][0]: Label = Ri_PLUS, Type = Transition (is Input) + Predecessors: p2[17][0] + Successors: p7[11][2] +PT-Net [1][1]: Label = p9, Type = Place (is Empty) + Predecessors: Ro_MINUS[5][1] + Successors: Ao_MINUS[13][0] +PT-Net [2][0]: Label = p5, Type = Place (is Empty) + Predecessors: Ro_MINUS[5][1] + Successors: Ai_MINUS[14][0] +PT-Net [3][0]: Label = p1, Type = Place (is Empty) + Predecessors: Ri_MINUS[6][0] + Successors: Ao_MINUS[13][0] +PT-Net [5][0]: Label = Ro_PLUS, Type = Transition (is Output) + Predecessors: p6[16][0], p7[11][2] + Successors: p3[12][0], p8[6][1] +PT-Net [5][1]: Label = Ro_MINUS, Type = Transition (is Output) + Predecessors: p4[7][1], p10[11][1] + Successors: p5[2][0], p9[1][1] +PT-Net [6][0]: Label = Ri_MINUS, Type = Transition (is Input) + Predecessors: p0[8][0] + Successors: p1[3][0] +PT-Net [6][1]: Label = p8, Type = Place (is Empty) + Predecessors: Ro_PLUS[5][0] + Successors: Ao_PLUS[11][0] +PT-Net [7][0]: Label = Ai_PLUS, Type = Transition (is Input) + Predecessors: p3[12][0] + Successors: p4[7][1] +PT-Net [7][1]: Label = p4, Type = Place (is Empty) + Predecessors: Ai_PLUS[7][0] + Successors: Ro_MINUS[5][1] +PT-Net [8][0]: Label = p0, Type = Place (is Empty) + Predecessors: Ao_PLUS[11][0] + Successors: Ri_MINUS[6][0] +PT-Net [11][0]: Label = Ao_PLUS, Type = Transition (is Output) + Predecessors: p8[6][1] + Successors: p0[8][0], p10[11][1] +PT-Net [11][1]: Label = p10, Type = Place (is Empty) + Predecessors: Ao_PLUS[11][0] + Successors: Ro_MINUS[5][1] +PT-Net [11][2]: Label = p7, Type = Place (is Marked) + Predecessors: Ri_PLUS[1][0] + Successors: Ro_PLUS[5][0] +PT-Net [12][0]: Label = p3, Type = Place (is Empty) + Predecessors: Ro_PLUS[5][0] + Successors: Ai_PLUS[7][0] +PT-Net [13][0]: Label = Ao_MINUS, Type = Transition (is Output) + Predecessors: p1[3][0], p9[1][1] + Successors: p2[17][0] +PT-Net [14][0]: Label = Ai_MINUS, Type = Transition (is Input) + Predecessors: p5[2][0] + Successors: p6[16][0] +PT-Net [16][0]: Label = p6, Type = Place (is Marked) + Predecessors: Ai_MINUS[14][0] + Successors: Ro_PLUS[5][0] +PT-Net [17][0]: Label = p2, Type = Place (is Empty) + Predecessors: Ao_MINUS[13][0] + Successors: Ri_PLUS[1][0] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #4 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 10, H-collapsed = 'false' *** +SC S-net (1,1): Ri_PLUS[1][0] + Predecessor Place: p2(1,10)[17,0] + Successor Place: p7(1,7)[11,2] +SC S-net (1,2): p9[1][1] +SC S-net (1,3): Ro_PLUS[5][0] + Predecessor Place: p7(1,7)[11,2] + Successor Place: p3(1,8)[12,0] +SC S-net (1,4): Ro_MINUS[5][1] + Predecessor Place: p4(1,6)[7,1] + Successor Place: p9(1,2)[1,1] +SC S-net (1,5): Ai_PLUS[7][0] + Predecessor Place: p3(1,8)[12,0] + Successor Place: p4(1,6)[7,1] +SC S-net (1,6): p4[7][1] +SC S-net (1,7): p7[11][2] +SC S-net (1,8): p3[12][0] +SC S-net (1,9): Ao_MINUS[13][0] + Predecessor Place: p9(1,2)[1,1] + Successor Place: p2(1,10)[17,0] +SC S-net (1,10): p2[17][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 8, H-collapsed = 'false' *** +SC S-net (2,1): p5[2][0] +SC S-net (2,2): Ro_PLUS[5][0] + Predecessor Place: p6(2,8)[16,0] + Successor Place: p3(2,6)[12,0] +SC S-net (2,3): Ro_MINUS[5][1] + Predecessor Place: p4(2,5)[7,1] + Successor Place: p5(2,1)[2,0] +SC S-net (2,4): Ai_PLUS[7][0] + Predecessor Place: p3(2,6)[12,0] + Successor Place: p4(2,5)[7,1] +SC S-net (2,5): p4[7][1] +SC S-net (2,6): p3[12][0] +SC S-net (2,7): Ai_MINUS[14][0] + Predecessor Place: p5(2,1)[2,0] + Successor Place: p6(2,8)[16,0] +SC S-net (2,8): p6[16][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #3, Total Nodes = 10, H-collapsed = 'false' *** +SC S-net (3,1): Ri_PLUS[1][0] + Predecessor Place: p2(3,10)[17,0] + Successor Place: p7(3,8)[11,2] +SC S-net (3,2): p1[3][0] +SC S-net (3,3): Ro_PLUS[5][0] + Predecessor Place: p7(3,8)[11,2] + Successor Place: p8(3,5)[6,1] +SC S-net (3,4): Ri_MINUS[6][0] + Predecessor Place: p0(3,6)[8,0] + Successor Place: p1(3,2)[3,0] +SC S-net (3,5): p8[6][1] +SC S-net (3,6): p0[8][0] +SC S-net (3,7): Ao_PLUS[11][0] + Predecessor Place: p8(3,5)[6,1] + Successor Place: p0(3,6)[8,0] +SC S-net (3,8): p7[11][2] +SC S-net (3,9): Ao_MINUS[13][0] + Predecessor Place: p1(3,2)[3,0] + Successor Place: p2(3,10)[17,0] +SC S-net (3,10): p2[17][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #4, Total Nodes = 8, H-collapsed = 'false' *** +SC S-net (4,1): p5[2][0] +SC S-net (4,2): Ro_PLUS[5][0] + Predecessor Place: p6(4,8)[16,0] + Successor Place: p8(4,4)[6,1] +SC S-net (4,3): Ro_MINUS[5][1] + Predecessor Place: p10(4,6)[11,1] + Successor Place: p5(4,1)[2,0] +SC S-net (4,4): p8[6][1] +SC S-net (4,5): Ao_PLUS[11][0] + Predecessor Place: p8(4,4)[6,1] + Successor Place: p10(4,6)[11,1] +SC S-net (4,6): p10[11][1] +SC S-net (4,7): Ai_MINUS[14][0] + Predecessor Place: p5(4,1)[2,0] + Successor Place: p6(4,8)[16,0] +SC S-net (4,8): p6[16][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #3 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #4 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 10, H-Collapsed = 'false' *** +FSM (1,1): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p7(0,7) + Predecessor(s): p2(0,10) +FSM (1,2): Label = p9, Type = State (is Initially Inactive) + Successor(s): e/Ao_MINUS(0,9) + Predecessor(s): e/Ro_MINUS(0,4) +FSM (1,3): Label = e/Ro_PLUS, Type = Trans. Function (is Output) + Successor(s): p3(0,8) + Predecessor(s): p7(0,7) +FSM (1,4): Label = e/Ro_MINUS, Type = Trans. Function (is Output) + Successor(s): p9(0,2) + Predecessor(s): p4(0,6) +FSM (1,5): Label = Ai_PLUS/, Type = Trans. Function (is Input) + Successor(s): p4(0,6) + Predecessor(s): p3(0,8) +FSM (1,6): Label = p4, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUS(0,4) + Predecessor(s): Ai_PLUS/(0,5) +FSM (1,7): Label = p7, Type = State (is Initially Active) + Successor(s): e/Ro_PLUS(0,3) + Predecessor(s): Ri_PLUS/(0,1) +FSM (1,8): Label = p3, Type = State (is Initially Inactive) + Successor(s): Ai_PLUS/(0,5) + Predecessor(s): e/Ro_PLUS(0,3) +FSM (1,9): Label = e/Ao_MINUS, Type = Trans. Function (is Output) + Successor(s): p2(0,10) + Predecessor(s): p9(0,2) +FSM (1,10): Label = p2, Type = State (is Initially Inactive) + Successor(s): Ri_PLUS/(0,1) + Predecessor(s): e/Ao_MINUS(0,9) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 8, H-Collapsed = 'false' *** +FSM (2,1): Label = p5, Type = State (is Initially Inactive) + Successor(s): Ai_MINUS/(1,7) + Predecessor(s): e/Ro_MINUS(1,3) +FSM (2,2): Label = e/Ro_PLUS, Type = Trans. Function (is Output) + Successor(s): p3(1,6) + Predecessor(s): p6(1,8) +FSM (2,3): Label = e/Ro_MINUS, Type = Trans. Function (is Output) + Successor(s): p5(1,1) + Predecessor(s): p4(1,5) +FSM (2,4): Label = Ai_PLUS/, Type = Trans. Function (is Input) + Successor(s): p4(1,5) + Predecessor(s): p3(1,6) +FSM (2,5): Label = p4, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUS(1,3) + Predecessor(s): Ai_PLUS/(1,4) +FSM (2,6): Label = p3, Type = State (is Initially Inactive) + Successor(s): Ai_PLUS/(1,4) + Predecessor(s): e/Ro_PLUS(1,2) +FSM (2,7): Label = Ai_MINUS/, Type = Trans. Function (is Input) + Successor(s): p6(1,8) + Predecessor(s): p5(1,1) +FSM (2,8): Label = p6, Type = State (is Initially Active) + Successor(s): e/Ro_PLUS(1,2) + Predecessor(s): Ai_MINUS/(1,7) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 3, Total list Entries = 10, H-Collapsed = 'false' *** +FSM (3,1): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p7(2,8) + Predecessor(s): p2(2,10) +FSM (3,2): Label = p1, Type = State (is Initially Inactive) + Successor(s): e/Ao_MINUS(2,9) + Predecessor(s): Ri_MINUS/(2,4) +FSM (3,3): Label = e/Ro_PLUS, Type = Trans. Function (is Output) + Successor(s): p8(2,5) + Predecessor(s): p7(2,8) +FSM (3,4): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p1(2,2) + Predecessor(s): p0(2,6) +FSM (3,5): Label = p8, Type = State (is Initially Inactive) + Successor(s): e/Ao_PLUS(2,7) + Predecessor(s): e/Ro_PLUS(2,3) +FSM (3,6): Label = p0, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(2,4) + Predecessor(s): e/Ao_PLUS(2,7) +FSM (3,7): Label = e/Ao_PLUS, Type = Trans. Function (is Output) + Successor(s): p0(2,6) + Predecessor(s): p8(2,5) +FSM (3,8): Label = p7, Type = State (is Initially Active) + Successor(s): e/Ro_PLUS(2,3) + Predecessor(s): Ri_PLUS/(2,1) +FSM (3,9): Label = e/Ao_MINUS, Type = Trans. Function (is Output) + Successor(s): p2(2,10) + Predecessor(s): p1(2,2) +FSM (3,10): Label = p2, Type = State (is Initially Inactive) + Successor(s): Ri_PLUS/(2,1) + Predecessor(s): e/Ao_MINUS(2,9) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 4, Total list Entries = 8, H-Collapsed = 'false' *** +FSM (4,1): Label = p5, Type = State (is Initially Inactive) + Successor(s): Ai_MINUS/(3,7) + Predecessor(s): e/Ro_MINUS(3,3) +FSM (4,2): Label = e/Ro_PLUS, Type = Trans. Function (is Output) + Successor(s): p8(3,4) + Predecessor(s): p6(3,8) +FSM (4,3): Label = e/Ro_MINUS, Type = Trans. Function (is Output) + Successor(s): p5(3,1) + Predecessor(s): p10(3,6) +FSM (4,4): Label = p8, Type = State (is Initially Inactive) + Successor(s): e/Ao_PLUS(3,5) + Predecessor(s): e/Ro_PLUS(3,2) +FSM (4,5): Label = e/Ao_PLUS, Type = Trans. Function (is Output) + Successor(s): p10(3,6) + Predecessor(s): p8(3,4) +FSM (4,6): Label = p10, Type = State (is Initially Inactive) + Successor(s): e/Ro_MINUS(3,3) + Predecessor(s): e/Ao_PLUS(3,5) +FSM (4,7): Label = Ai_MINUS/, Type = Trans. Function (is Input) + Successor(s): p6(3,8) + Predecessor(s): p5(3,1) +FSM (4,8): Label = p6, Type = State (is Initially Active) + Successor(s): e/Ro_PLUS(3,2) + Predecessor(s): Ai_MINUS/(3,7) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/msfsms_flow_script.tcl b/examples/msfsms_flow_script.tcl new file mode 100644 index 0000000..d9577cf --- /dev/null +++ b/examples/msfsms_flow_script.tcl @@ -0,0 +1,43 @@ +########################################################### +### Basic TCL script template for MSFSMs Synthesis Tool ### +########################################################### + +### Flow STEP #1 ### +# Load a Well-formed Petri-Net file from '.g' or '.work' file # +read_graph examples/xor-gate_GN/xor-gate.pterinet.GN.workcraft.g + +# Display in command line structure representation of loaded Petri-Net # +list_petrinet + +### Flow STEP #2 ### +# Calculate Strongly Connected S-Nets # +get_SC_Snets + +# Display in command line structure representation of calculated Strongly Connected S-Nets # +list_SC_Snet -all + +### Flow STEP #3 ### +# Extract FSMs from Strongly Connected S-Nets and attempt to horizontally collapse them if possible # +create_FSMs -hcollapse + +# Display in command line structure representation of extracted FSMs # +list_FSM -all + +### Flow STEP #4 ### +# Synchronise FSMs to compose the MSFSMs system # +synchronise_FSMs + +### Flow STEP #5 ### +# Create MSFSMs Files of AFSM internal format # +write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D + +# Create MSFSMs Files of Behavioral Verilog RTL # +write_MSFSMs -format syncmealy_behav + +# Create MSFSMs Files of Synthesisable Verilog RTL # +write_MSFSMs -format syncmealy_synth + +### Terminate Program ### +quit + +########################### EOF ########################### diff --git a/examples/nowick_MG/AsyncMSFSMs/fsm_afsm.afsm b/examples/nowick_MG/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..68f1c0b --- /dev/null +++ b/examples/nowick_MG/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,102 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p19*: a_PLUS_ a_PLUS__p19_FSM2_TB a_PLUS__p19_FSM4_TB a_PLUS__p19_FSM6_TB p0 +p18: e_y_MINUSa e_y_MINUSa_p18_FSM2_TB e_y_MINUSa_p18_FSM3_TB e_y_MINUSa_p18_FSM4_TB e_y_MINUSa_p18_FSM5_TB e_y_MINUSa_p18_FSM6_TB p19 +p4: c_PLUS_ c_PLUS__p5_FSM2_TB c_PLUS__p5_FSM3_TB c_PLUS__p4_FSM4_TB c_PLUS__p4_FSM5_TB c_PLUS__p4_FSM6_TB p6 +p17: e_q_MINUS e_q_MINUS_p17_FSM2_TB e_q_MINUS_p17_FSM3_TB e_q_MINUS_p17_FSM4_TB e_q_MINUS_p17_FSM5_TB e_q_MINUS_p17_FSM6_TB p18 +p15: a_MINUS_ a_MINUS__p15_FSM2_TB a_MINUS__p15_FSM3_TB a_MINUS__p16_FSM4_TB a_MINUS__p15_FSM5_TB a_MINUS__p15_FSM6_TB p17 +p0: e_x_PLUS e_x_PLUS_p0_FSM4_TB e_x_PLUS_p2_FSM5_TB e_x_PLUS_p0_FSM6_TB p4 +p9: e_x_PLUSa e_x_PLUSa_p9_FSM2_TB e_x_PLUSa_p9_FSM3_TB e_x_PLUSa_p9_FSM4_TB e_x_PLUSa_p9_FSM5_TB p11 +p13: e_x_MINUSa e_x_MINUSa_p13_FSM2_TB e_x_MINUSa_p13_FSM3_TB e_x_MINUSa_p13_FSM5_TB e_x_MINUSa_p13_FSM6_TB p15 +p8: c_MINUS_ c_MINUS__p8_FSM2_TB c_MINUS__p8_FSM3_TB c_MINUS__p8_FSM4_TB c_MINUS__p8_FSM5_TB c_MINUS__p8_FSM6_TB p9 +p7: e_x_MINUS e_x_MINUS_p7_FSM2_TB e_x_MINUS_p7_FSM3_TB e_x_MINUS_p7_FSM4_TB e_x_MINUS_p7_FSM5_TB e_x_MINUS_p7_FSM6_TB p8 +p11: b_MINUS_ b_MINUS__p11_FSM2_TB b_MINUS__p11_FSM3_TB b_MINUS__p11_FSM4_TB b_MINUS__p11_FSM5_TB b_MINUS__p12_FSM6_TB p13 +p6: e_q_PLUS e_q_PLUS_p6_FSM2_TB e_q_PLUS_p6_FSM3_TB e_q_PLUS_p6_FSM4_TB e_q_PLUS_p6_FSM5_TB e_q_PLUS_p6_FSM6_TB p7 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p19*: a_PLUS_ a_PLUS__p19_FSM1_TB a_PLUS__p19_FSM4_TB a_PLUS__p19_FSM6_TB p1 +p5: c_PLUS_ c_PLUS__p4_FSM1_TB c_PLUS__p5_FSM3_TB c_PLUS__p4_FSM4_TB c_PLUS__p4_FSM5_TB c_PLUS__p4_FSM6_TB p6 +p18: e_y_MINUSa e_y_MINUSa_p18_FSM1_TB e_y_MINUSa_p18_FSM3_TB e_y_MINUSa_p18_FSM4_TB e_y_MINUSa_p18_FSM5_TB e_y_MINUSa_p18_FSM6_TB p19 +p17: e_q_MINUS e_q_MINUS_p17_FSM1_TB e_q_MINUS_p17_FSM3_TB e_q_MINUS_p17_FSM4_TB e_q_MINUS_p17_FSM5_TB e_q_MINUS_p17_FSM6_TB p18 +p15: a_MINUS_ a_MINUS__p15_FSM1_TB a_MINUS__p15_FSM3_TB a_MINUS__p16_FSM4_TB a_MINUS__p15_FSM5_TB a_MINUS__p15_FSM6_TB p17 +p1: e_y_PLUS e_y_PLUS_p3_FSM3_TB p5 +p9: e_x_PLUSa e_x_PLUSa_p9_FSM1_TB e_x_PLUSa_p9_FSM3_TB e_x_PLUSa_p9_FSM4_TB e_x_PLUSa_p9_FSM5_TB p11 +p13: e_x_MINUSa e_x_MINUSa_p13_FSM1_TB e_x_MINUSa_p13_FSM3_TB e_x_MINUSa_p13_FSM5_TB e_x_MINUSa_p13_FSM6_TB p15 +p8: c_MINUS_ c_MINUS__p8_FSM1_TB c_MINUS__p8_FSM3_TB c_MINUS__p8_FSM4_TB c_MINUS__p8_FSM5_TB c_MINUS__p8_FSM6_TB p9 +p7: e_x_MINUS e_x_MINUS_p7_FSM1_TB e_x_MINUS_p7_FSM3_TB e_x_MINUS_p7_FSM4_TB e_x_MINUS_p7_FSM5_TB e_x_MINUS_p7_FSM6_TB p8 +p11: b_MINUS_ b_MINUS__p11_FSM1_TB b_MINUS__p11_FSM3_TB b_MINUS__p11_FSM4_TB b_MINUS__p11_FSM5_TB b_MINUS__p12_FSM6_TB p13 +p6: e_q_PLUS e_q_PLUS_p6_FSM1_TB e_q_PLUS_p6_FSM3_TB e_q_PLUS_p6_FSM4_TB e_q_PLUS_p6_FSM5_TB e_q_PLUS_p6_FSM6_TB p7 +### End of FSM #02 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#03 Declaration ### +p5: c_PLUS_ c_PLUS__p4_FSM1_TB c_PLUS__p5_FSM2_TB c_PLUS__p4_FSM4_TB c_PLUS__p4_FSM5_TB c_PLUS__p4_FSM6_TB p6 +p18: e_y_MINUSa e_y_MINUSa_p18_FSM1_TB e_y_MINUSa_p18_FSM2_TB e_y_MINUSa_p18_FSM4_TB e_y_MINUSa_p18_FSM5_TB e_y_MINUSa_p18_FSM6_TB p20 +p17: e_q_MINUS e_q_MINUS_p17_FSM1_TB e_q_MINUS_p17_FSM2_TB e_q_MINUS_p17_FSM4_TB e_q_MINUS_p17_FSM5_TB e_q_MINUS_p17_FSM6_TB p18 +p3: e_y_PLUS e_y_PLUS_p1_FSM2_TB p5 +p20*: b_PLUS_ b_PLUS__p20_FSM5_TB p3 +p15: a_MINUS_ a_MINUS__p15_FSM1_TB a_MINUS__p15_FSM2_TB a_MINUS__p16_FSM4_TB a_MINUS__p15_FSM5_TB a_MINUS__p15_FSM6_TB p17 +p9: e_x_PLUSa e_x_PLUSa_p9_FSM1_TB e_x_PLUSa_p9_FSM2_TB e_x_PLUSa_p9_FSM4_TB e_x_PLUSa_p9_FSM5_TB p11 +p13: e_x_MINUSa e_x_MINUSa_p13_FSM1_TB e_x_MINUSa_p13_FSM2_TB e_x_MINUSa_p13_FSM5_TB e_x_MINUSa_p13_FSM6_TB p15 +p8: c_MINUS_ c_MINUS__p8_FSM1_TB c_MINUS__p8_FSM2_TB c_MINUS__p8_FSM4_TB c_MINUS__p8_FSM5_TB c_MINUS__p8_FSM6_TB p9 +p7: e_x_MINUS e_x_MINUS_p7_FSM1_TB e_x_MINUS_p7_FSM2_TB e_x_MINUS_p7_FSM4_TB e_x_MINUS_p7_FSM5_TB e_x_MINUS_p7_FSM6_TB p8 +p11: b_MINUS_ b_MINUS__p11_FSM1_TB b_MINUS__p11_FSM2_TB b_MINUS__p11_FSM4_TB b_MINUS__p11_FSM5_TB b_MINUS__p12_FSM6_TB p13 +p6: e_q_PLUS e_q_PLUS_p6_FSM1_TB e_q_PLUS_p6_FSM2_TB e_q_PLUS_p6_FSM4_TB e_q_PLUS_p6_FSM5_TB e_q_PLUS_p6_FSM6_TB p7 +### End of FSM #03 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#04 Declaration ### +p19*: a_PLUS_ a_PLUS__p19_FSM1_TB a_PLUS__p19_FSM2_TB a_PLUS__p19_FSM6_TB p0 +p18: e_y_MINUSa e_y_MINUSa_p18_FSM1_TB e_y_MINUSa_p18_FSM2_TB e_y_MINUSa_p18_FSM3_TB e_y_MINUSa_p18_FSM5_TB e_y_MINUSa_p18_FSM6_TB p19 +p4: c_PLUS_ c_PLUS__p4_FSM1_TB c_PLUS__p5_FSM2_TB c_PLUS__p5_FSM3_TB c_PLUS__p4_FSM5_TB c_PLUS__p4_FSM6_TB p6 +p17: e_q_MINUS e_q_MINUS_p17_FSM1_TB e_q_MINUS_p17_FSM2_TB e_q_MINUS_p17_FSM3_TB e_q_MINUS_p17_FSM5_TB e_q_MINUS_p17_FSM6_TB p18 +p16: a_MINUS_ a_MINUS__p15_FSM1_TB a_MINUS__p15_FSM2_TB a_MINUS__p15_FSM3_TB a_MINUS__p15_FSM5_TB a_MINUS__p15_FSM6_TB p17 +p14: e_y_PLUSa p16 +p0: e_x_PLUS e_x_PLUS_p0_FSM1_TB e_x_PLUS_p2_FSM5_TB e_x_PLUS_p0_FSM6_TB p4 +p9: e_x_PLUSa e_x_PLUSa_p9_FSM1_TB e_x_PLUSa_p9_FSM2_TB e_x_PLUSa_p9_FSM3_TB e_x_PLUSa_p9_FSM5_TB p11 +p8: c_MINUS_ c_MINUS__p8_FSM1_TB c_MINUS__p8_FSM2_TB c_MINUS__p8_FSM3_TB c_MINUS__p8_FSM5_TB c_MINUS__p8_FSM6_TB p9 +p7: e_x_MINUS e_x_MINUS_p7_FSM1_TB e_x_MINUS_p7_FSM2_TB e_x_MINUS_p7_FSM3_TB e_x_MINUS_p7_FSM5_TB e_x_MINUS_p7_FSM6_TB p8 +p11: b_MINUS_ b_MINUS__p11_FSM1_TB b_MINUS__p11_FSM2_TB b_MINUS__p11_FSM3_TB b_MINUS__p11_FSM5_TB b_MINUS__p12_FSM6_TB p14 +p6: e_q_PLUS e_q_PLUS_p6_FSM1_TB e_q_PLUS_p6_FSM2_TB e_q_PLUS_p6_FSM3_TB e_q_PLUS_p6_FSM5_TB e_q_PLUS_p6_FSM6_TB p7 +### End of FSM #04 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#05 Declaration ### +p18: e_y_MINUSa e_y_MINUSa_p18_FSM1_TB e_y_MINUSa_p18_FSM2_TB e_y_MINUSa_p18_FSM3_TB e_y_MINUSa_p18_FSM4_TB e_y_MINUSa_p18_FSM6_TB p20 +p4: c_PLUS_ c_PLUS__p4_FSM1_TB c_PLUS__p5_FSM2_TB c_PLUS__p5_FSM3_TB c_PLUS__p4_FSM4_TB c_PLUS__p4_FSM6_TB p6 +p17: e_q_MINUS e_q_MINUS_p17_FSM1_TB e_q_MINUS_p17_FSM2_TB e_q_MINUS_p17_FSM3_TB e_q_MINUS_p17_FSM4_TB e_q_MINUS_p17_FSM6_TB p18 +p2: e_x_PLUS e_x_PLUS_p0_FSM1_TB e_x_PLUS_p0_FSM4_TB e_x_PLUS_p0_FSM6_TB p4 +p20*: b_PLUS_ b_PLUS__p20_FSM3_TB p2 +p15: a_MINUS_ a_MINUS__p15_FSM1_TB a_MINUS__p15_FSM2_TB a_MINUS__p15_FSM3_TB a_MINUS__p16_FSM4_TB a_MINUS__p15_FSM6_TB p17 +p9: e_x_PLUSa e_x_PLUSa_p9_FSM1_TB e_x_PLUSa_p9_FSM2_TB e_x_PLUSa_p9_FSM3_TB e_x_PLUSa_p9_FSM4_TB p11 +p13: e_x_MINUSa e_x_MINUSa_p13_FSM1_TB e_x_MINUSa_p13_FSM2_TB e_x_MINUSa_p13_FSM3_TB e_x_MINUSa_p13_FSM6_TB p15 +p8: c_MINUS_ c_MINUS__p8_FSM1_TB c_MINUS__p8_FSM2_TB c_MINUS__p8_FSM3_TB c_MINUS__p8_FSM4_TB c_MINUS__p8_FSM6_TB p9 +p7: e_x_MINUS e_x_MINUS_p7_FSM1_TB e_x_MINUS_p7_FSM2_TB e_x_MINUS_p7_FSM3_TB e_x_MINUS_p7_FSM4_TB e_x_MINUS_p7_FSM6_TB p8 +p11: b_MINUS_ b_MINUS__p11_FSM1_TB b_MINUS__p11_FSM2_TB b_MINUS__p11_FSM3_TB b_MINUS__p11_FSM4_TB b_MINUS__p12_FSM6_TB p13 +p6: e_q_PLUS e_q_PLUS_p6_FSM1_TB e_q_PLUS_p6_FSM2_TB e_q_PLUS_p6_FSM3_TB e_q_PLUS_p6_FSM4_TB e_q_PLUS_p6_FSM6_TB p7 +### End of FSM #05 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#06 Declaration ### +p19*: a_PLUS_ a_PLUS__p19_FSM1_TB a_PLUS__p19_FSM2_TB a_PLUS__p19_FSM4_TB p0 +p18: e_y_MINUSa e_y_MINUSa_p18_FSM1_TB e_y_MINUSa_p18_FSM2_TB e_y_MINUSa_p18_FSM3_TB e_y_MINUSa_p18_FSM4_TB e_y_MINUSa_p18_FSM5_TB p19 +p4: c_PLUS_ c_PLUS__p4_FSM1_TB c_PLUS__p5_FSM2_TB c_PLUS__p5_FSM3_TB c_PLUS__p4_FSM4_TB c_PLUS__p4_FSM5_TB p6 +p17: e_q_MINUS e_q_MINUS_p17_FSM1_TB e_q_MINUS_p17_FSM2_TB e_q_MINUS_p17_FSM3_TB e_q_MINUS_p17_FSM4_TB e_q_MINUS_p17_FSM5_TB p18 +p15: a_MINUS_ a_MINUS__p15_FSM1_TB a_MINUS__p15_FSM2_TB a_MINUS__p15_FSM3_TB a_MINUS__p16_FSM4_TB a_MINUS__p15_FSM5_TB p17 +p0: e_x_PLUS e_x_PLUS_p0_FSM1_TB e_x_PLUS_p0_FSM4_TB e_x_PLUS_p2_FSM5_TB p4 +p13: e_x_MINUSa e_x_MINUSa_p13_FSM1_TB e_x_MINUSa_p13_FSM2_TB e_x_MINUSa_p13_FSM3_TB e_x_MINUSa_p13_FSM5_TB p15 +p8: c_MINUS_ c_MINUS__p8_FSM1_TB c_MINUS__p8_FSM2_TB c_MINUS__p8_FSM3_TB c_MINUS__p8_FSM4_TB c_MINUS__p8_FSM5_TB p10 +p12: b_MINUS_ b_MINUS__p11_FSM1_TB b_MINUS__p11_FSM2_TB b_MINUS__p11_FSM3_TB b_MINUS__p11_FSM4_TB b_MINUS__p11_FSM5_TB p13 +p7: e_x_MINUS e_x_MINUS_p7_FSM1_TB e_x_MINUS_p7_FSM2_TB e_x_MINUS_p7_FSM3_TB e_x_MINUS_p7_FSM4_TB e_x_MINUS_p7_FSM5_TB p8 +p6: e_q_PLUS e_q_PLUS_p6_FSM1_TB e_q_PLUS_p6_FSM2_TB e_q_PLUS_p6_FSM3_TB e_q_PLUS_p6_FSM4_TB e_q_PLUS_p6_FSM5_TB p7 +p10: e_y_MINUS p12 +### End of FSM #06 Declaration ### + diff --git a/examples/nowick_MG/AsyncMSFSMs/msfsms_afsm.v b/examples/nowick_MG/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..6ef5579 --- /dev/null +++ b/examples/nowick_MG/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,221 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + x_PLUS, + q_PLUS, + b_MINUS, + c_PLUS, + x_MINUS, + c_MINUS, + x_MINUSa, + y_MINUS, + x_PLUSa, + b_PLUS, + y_MINUSa, + y_PLUS, + y_PLUSa, + a_PLUS, + a_MINUS, + q_MINUS); + + input reset; + output x_PLUS; + output q_PLUS; + input b_MINUS; + input c_PLUS; + output x_MINUS; + input c_MINUS; + output x_MINUSa; + output y_MINUS; + output x_PLUSa; + input b_PLUS; + output y_MINUSa; + output y_PLUS; + output y_PLUSa; + input a_PLUS; + input a_MINUS; + output q_MINUS; + + wire e_x_PLUS_FSM1out, e_q_PLUS_FSM1out, e_x_MINUS_FSM1out, e_x_MINUSa_FSM1out, e_x_PLUSa_FSM1out, e_y_MINUSa_FSM1out, e_q_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p19_FSM1out, p18_FSM1out, p4_FSM1out, p17_FSM1out, p15_FSM1out, p0_FSM1out, p9_FSM1out, p13_FSM1out, p8_FSM1out, p7_FSM1out, p11_FSM1out, p6_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_q_PLUS_FSM2out, e_x_MINUS_FSM2out, e_x_MINUSa_FSM2out, e_x_PLUSa_FSM2out, e_y_MINUSa_FSM2out, e_y_PLUS_FSM2out, e_q_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p19_FSM2out, p5_FSM2out, p18_FSM2out, p17_FSM2out, p15_FSM2out, p1_FSM2out, p9_FSM2out, p13_FSM2out, p8_FSM2out, p7_FSM2out, p11_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_q_PLUS_FSM3out, e_x_MINUS_FSM3out, e_x_MINUSa_FSM3out, e_x_PLUSa_FSM3out, e_y_MINUSa_FSM3out, e_y_PLUS_FSM3out, e_q_MINUS_FSM3out; // Regular output signals of FSM3 // + wire p5_FSM3out, p18_FSM3out, p17_FSM3out, p3_FSM3out, p20_FSM3out, p15_FSM3out, p9_FSM3out, p13_FSM3out, p8_FSM3out, p7_FSM3out, p11_FSM3out, p6_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_x_PLUS_FSM4out, e_q_PLUS_FSM4out, e_x_MINUS_FSM4out, e_x_PLUSa_FSM4out, e_y_MINUSa_FSM4out, e_y_PLUSa_FSM4out, e_q_MINUS_FSM4out; // Regular output signals of FSM4 // + wire p19_FSM4out, p18_FSM4out, p4_FSM4out, p17_FSM4out, p16_FSM4out, p14_FSM4out, p0_FSM4out, p9_FSM4out, p8_FSM4out, p7_FSM4out, p11_FSM4out, p6_FSM4out; // State Synchronisation output signals of FSM4 // + wire e_x_PLUS_FSM5out, e_q_PLUS_FSM5out, e_x_MINUS_FSM5out, e_x_MINUSa_FSM5out, e_x_PLUSa_FSM5out, e_y_MINUSa_FSM5out, e_q_MINUS_FSM5out; // Regular output signals of FSM5 // + wire p18_FSM5out, p4_FSM5out, p17_FSM5out, p2_FSM5out, p20_FSM5out, p15_FSM5out, p9_FSM5out, p13_FSM5out, p8_FSM5out, p7_FSM5out, p11_FSM5out, p6_FSM5out; // State Synchronisation output signals of FSM5 // + wire e_x_PLUS_FSM6out, e_q_PLUS_FSM6out, e_x_MINUS_FSM6out, e_x_MINUSa_FSM6out, e_y_MINUS_FSM6out, e_y_MINUSa_FSM6out, e_q_MINUS_FSM6out; // Regular output signals of FSM6 // + wire p19_FSM6out, p18_FSM6out, p4_FSM6out, p17_FSM6out, p15_FSM6out, p0_FSM6out, p13_FSM6out, p8_FSM6out, p12_FSM6out, p7_FSM6out, p6_FSM6out, p10_FSM6out; // State Synchronisation output signals of FSM6 // + + assign x_PLUS = e_x_PLUS_FSM1out & e_x_PLUS_FSM4out & e_x_PLUS_FSM5out & e_x_PLUS_FSM6out; + assign q_PLUS = e_q_PLUS_FSM1out & e_q_PLUS_FSM2out & e_q_PLUS_FSM3out & e_q_PLUS_FSM4out & e_q_PLUS_FSM5out & e_q_PLUS_FSM6out; + assign x_MINUS = e_x_MINUS_FSM1out & e_x_MINUS_FSM2out & e_x_MINUS_FSM3out & e_x_MINUS_FSM4out & e_x_MINUS_FSM5out & e_x_MINUS_FSM6out; + assign x_MINUSa = e_x_MINUSa_FSM1out & e_x_MINUSa_FSM2out & e_x_MINUSa_FSM3out & e_x_MINUSa_FSM5out & e_x_MINUSa_FSM6out; + assign y_MINUS = e_y_MINUS_FSM6out; + assign x_PLUSa = e_x_PLUSa_FSM1out & e_x_PLUSa_FSM2out & e_x_PLUSa_FSM3out & e_x_PLUSa_FSM4out & e_x_PLUSa_FSM5out; + assign y_MINUSa = e_y_MINUSa_FSM1out & e_y_MINUSa_FSM2out & e_y_MINUSa_FSM3out & e_y_MINUSa_FSM4out & e_y_MINUSa_FSM5out & e_y_MINUSa_FSM6out; + assign y_PLUS = e_y_PLUS_FSM2out & e_y_PLUS_FSM3out; + assign y_PLUSa = e_y_PLUSa_FSM4out; + assign q_MINUS = e_q_MINUS_FSM1out & e_q_MINUS_FSM2out & e_q_MINUS_FSM3out & e_q_MINUS_FSM4out & e_q_MINUS_FSM5out & e_q_MINUS_FSM6out; + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(p0_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_q_MINUS(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .e/x_PLUS(e/x_PLUS_FSM1out), + .e/q_PLUS(e/q_PLUS_FSM1out), + .e/x_MINUS(e/x_MINUS_FSM1out), + .e/x_MINUSa(e/x_MINUSa_FSM1out), + .e/x_PLUSa(e/x_PLUSa_FSM1out), + .e/y_MINUSa(e/y_MINUSa_FSM1out), + .e/q_MINUS(e/q_MINUS_FSM1out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_q_PLUS(p6_FSM2out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(p7_FSM2out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(p13_FSM2out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(p9_FSM2out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(p18_FSM2out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUS(p1_FSM2out), .e_y_PLUS_p3_FSM3_TB(p3_FSM3out), + .e_q_MINUS(p17_FSM2out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .e/q_PLUS(e/q_PLUS_FSM2out), + .e/x_MINUS(e/x_MINUS_FSM2out), + .e/x_MINUSa(e/x_MINUSa_FSM2out), + .e/x_PLUSa(e/x_PLUSa_FSM2out), + .e/y_MINUSa(e/y_MINUSa_FSM2out), + .e/y_PLUS(e/y_PLUS_FSM2out), + .e/q_MINUS(e/q_MINUS_FSM2out) + ); + + + fsm_afsm_03 fsm_afsm_03_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .b_PLUS_(b_PLUS), .b_PLUS__p20_FSM5_TB(p20_FSM5out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_q_PLUS(p6_FSM3out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(p7_FSM3out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(p13_FSM3out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(p9_FSM3out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(p18_FSM3out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUS(p3_FSM3out), .e_y_PLUS_p1_FSM2_TB(p1_FSM2out), + .e_q_MINUS(p17_FSM3out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .e/q_PLUS(e/q_PLUS_FSM3out), + .e/x_MINUS(e/x_MINUS_FSM3out), + .e/x_MINUSa(e/x_MINUSa_FSM3out), + .e/x_PLUSa(e/x_PLUSa_FSM3out), + .e/y_MINUSa(e/y_MINUSa_FSM3out), + .e/y_PLUS(e/y_PLUS_FSM3out), + .e/q_MINUS(e/q_MINUS_FSM3out) + ); + + + fsm_afsm_04 fsm_afsm_04_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(p0_FSM4out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(p6_FSM4out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(p7_FSM4out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_PLUSa(p9_FSM4out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(p18_FSM4out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUSa(p14_FSM4out), + .e_q_MINUS(p17_FSM4out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .e/x_PLUS(e/x_PLUS_FSM4out), + .e/q_PLUS(e/q_PLUS_FSM4out), + .e/x_MINUS(e/x_MINUS_FSM4out), + .e/x_PLUSa(e/x_PLUSa_FSM4out), + .e/y_MINUSa(e/y_MINUSa_FSM4out), + .e/y_PLUSa(e/y_PLUSa_FSM4out), + .e/q_MINUS(e/q_MINUS_FSM4out) + ); + + + fsm_afsm_05 fsm_afsm_05_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .b_PLUS_(b_PLUS), .b_PLUS__p20_FSM3_TB(p20_FSM3out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(p2_FSM5out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(p6_FSM5out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(p7_FSM5out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(p13_FSM5out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(p9_FSM5out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), + .e_y_MINUSa(p18_FSM5out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_q_MINUS(p17_FSM5out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .e/x_PLUS(e/x_PLUS_FSM5out), + .e/q_PLUS(e/q_PLUS_FSM5out), + .e/x_MINUS(e/x_MINUS_FSM5out), + .e/x_MINUSa(e/x_MINUSa_FSM5out), + .e/x_PLUSa(e/x_PLUSa_FSM5out), + .e/y_MINUSa(e/y_MINUSa_FSM5out), + .e/q_MINUS(e/q_MINUS_FSM5out) + ); + + + fsm_afsm_06 fsm_afsm_06_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), + .e_x_PLUS(p0_FSM6out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), + .e_q_PLUS(p6_FSM6out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), + .e_x_MINUS(p7_FSM6out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), + .e_x_MINUSa(p13_FSM6out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), + .e_y_MINUS(p10_FSM6out), + .e_y_MINUSa(p18_FSM6out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), + .e_q_MINUS(p17_FSM6out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), + .e/x_PLUS(e/x_PLUS_FSM6out), + .e/q_PLUS(e/q_PLUS_FSM6out), + .e/x_MINUS(e/x_MINUS_FSM6out), + .e/x_MINUSa(e/x_MINUSa_FSM6out), + .e/y_MINUS(e/y_MINUS_FSM6out), + .e/y_MINUSa(e/y_MINUSa_FSM6out), + .e/q_MINUS(e/q_MINUS_FSM6out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/nowick_MG/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/nowick_MG/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..002bc4d --- /dev/null +++ b/examples/nowick_MG/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,1998 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + a_PLUS_, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB, + a_MINUS_, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_x_PLUS, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_q_MINUS, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p19, + p18, + p4, + p17, + p15, + p0, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB; + input a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB; + input e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p18; + output p4; + output p17; + output p15; + output p0; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_q_MINUS; + wire p19; + wire p18; + wire p4; + wire p17; + wire p15; + wire p0; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM2_TB & a_PLUS__p19_FSM4_TB & a_PLUS__p19_FSM6_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM4_TB & e_x_PLUS_p2_FSM5_TB & e_x_PLUS_p0_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM5_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM4_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p19_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p18_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p4_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p4_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p17_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p15_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p15_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p0_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p0_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p9_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p13_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p8_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p11_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p6_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p19_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_q_MINUS = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p19_1HOT_ENCODING: // + begin + if (a_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p18_1HOT_ENCODING: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + // next_state = p19_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p4_1HOT_ENCODING: // + begin + if (c_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[11] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p17_1HOT_ENCODING: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + // next_state = p18_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p15_1HOT_ENCODING: // + begin + if (a_MINUS__TB_sync) + begin + // next_state = p17_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p0_1HOT_ENCODING: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxxx1xxxxxx: // p9_1HOT_ENCODING: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + // next_state = p11_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[10] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p13_1HOT_ENCODING: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[4] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p8_1HOT_ENCODING: // + begin + if (c_MINUS__TB_sync) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p7_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[8] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p11_1HOT_ENCODING: // + begin + if (b_MINUS__TB_sync) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[7] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p6_1HOT_ENCODING: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[9] = 1'b1; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + a_PLUS_, a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_y_PLUS, e_y_PLUS_p3_FSM3_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p19, + p5, + p18, + p17, + p15, + p1, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_y_PLUS; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_y_PLUS_p3_FSM3_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p5; + output p18; + output p17; + output p15; + output p1; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_y_PLUS; + reg e_q_MINUS; + wire p19; + wire p5; + wire p18; + wire p17; + wire p15; + wire p1; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_y_PLUS_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM1_TB & a_PLUS__p19_FSM4_TB & a_PLUS__p19_FSM6_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM5_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM4_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_y_PLUS_TB_sync = e_y_PLUS_p3_FSM3_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p19_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p5_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p5_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p18_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p18_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p17_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p15_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p15_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p1_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p1_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p9_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p13_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p8_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p11_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p6_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p19_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_y_PLUS_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_y_PLUS = 1'b0; + e_q_MINUS = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p19_1HOT_ENCODING: // + begin + if (a_PLUS__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p5_1HOT_ENCODING: // + begin + if (c_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[11] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p18_1HOT_ENCODING: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + // next_state = p19_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p17_1HOT_ENCODING: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + // next_state = p18_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p15_1HOT_ENCODING: // + begin + if (a_MINUS__TB_sync) + begin + // next_state = p17_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p1_1HOT_ENCODING: // + begin + if (e_y_PLUS_TB_sync) + begin + e_y_PLUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxxxxx1xxxxxx: // p9_1HOT_ENCODING: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + // next_state = p11_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[10] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p13_1HOT_ENCODING: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[4] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p8_1HOT_ENCODING: // + begin + if (c_MINUS__TB_sync) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p7_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[8] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p11_1HOT_ENCODING: // + begin + if (b_MINUS__TB_sync) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[7] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p6_1HOT_ENCODING: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[9] = 1'b1; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_03 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + b_PLUS_, b_PLUS__p20_FSM5_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_y_PLUS, e_y_PLUS_p1_FSM2_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p5, + p18, + p17, + p3, + p20, + p15, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input b_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input b_PLUS__p20_FSM5_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_y_PLUS; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_y_PLUS_p1_FSM2_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p5; + output p18; + output p17; + output p3; + output p20; + output p15; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_y_PLUS; + reg e_q_MINUS; + wire p5; + wire p18; + wire p17; + wire p3; + wire p20; + wire p15; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire b_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_y_PLUS_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign b_PLUS__TB_sync = b_PLUS_ & b_PLUS__p20_FSM5_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM5_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM4_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_y_PLUS_TB_sync = e_y_PLUS_p1_FSM2_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p5_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p5_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p18_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p17_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p17_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p3_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p3_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p20_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p20_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p15_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p15_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p9_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p13_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p8_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p11_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p6_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p20_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b1; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p20 = (state == p20_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or b_PLUS__TB_sync or a_MINUS__TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_y_PLUS_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_y_PLUS = 1'b0; + e_q_MINUS = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p5_1HOT_ENCODING: // + begin + if (c_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[11] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p18_1HOT_ENCODING: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + // next_state = p20_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[4] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p17_1HOT_ENCODING: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + // next_state = p18_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p3_1HOT_ENCODING: // + begin + if (e_y_PLUS_TB_sync) + begin + e_y_PLUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p20_1HOT_ENCODING: // + begin + if (b_PLUS__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p15_1HOT_ENCODING: // + begin + if (a_MINUS__TB_sync) + begin + // next_state = p17_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxxx1xxxxxx: // p9_1HOT_ENCODING: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + // next_state = p11_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[10] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p13_1HOT_ENCODING: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p8_1HOT_ENCODING: // + begin + if (c_MINUS__TB_sync) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p7_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[8] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p11_1HOT_ENCODING: // + begin + if (b_MINUS__TB_sync) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[7] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p6_1HOT_ENCODING: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[9] = 1'b1; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_04 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + a_PLUS_, a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM6_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_x_PLUS, e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_y_PLUSa, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p19, + p18, + p4, + p17, + p16, + p0, + p9, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM6_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_PLUSa; + output e_y_MINUSa; + output e_y_PLUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB; + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p18; + output p4; + output p17; + output p16; + output p0; + output p9; + output p8; + output p7; + output p11; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_y_PLUSa; + reg e_q_MINUS; + wire p19; + wire p18; + wire p4; + wire p17; + wire p16; + wire p0; + wire p9; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM1_TB & a_PLUS__p19_FSM2_TB & a_PLUS__p19_FSM6_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM1_TB & e_x_PLUS_p2_FSM5_TB & e_x_PLUS_p0_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p19_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p18_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p4_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p4_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p17_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p16_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p16_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p14_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p14_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p0_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p0_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p9_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p9_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p8_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p11_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p6_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p19_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p16 = (state == p16_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_y_PLUSa = 1'b0; + e_q_MINUS = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p19_1HOT_ENCODING: // + begin + if (a_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p18_1HOT_ENCODING: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + // next_state = p19_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p4_1HOT_ENCODING: // + begin + if (c_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[11] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p17_1HOT_ENCODING: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + // next_state = p18_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p16_1HOT_ENCODING: // + begin + if (a_MINUS__TB_sync) + begin + // next_state = p17_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p14_1HOT_ENCODING: // + begin + e_y_PLUSa = 1'b1; + // next_state = p16_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[4] = 1'b1; + end + + 12'bxxxxx1xxxxxx: // p0_1HOT_ENCODING: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p9_1HOT_ENCODING: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + // next_state = p11_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[10] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p8_1HOT_ENCODING: // + begin + if (c_MINUS__TB_sync) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[7] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p7_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[8] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p11_1HOT_ENCODING: // + begin + if (b_MINUS__TB_sync) + begin + // next_state = p14_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p6_1HOT_ENCODING: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[9] = 1'b1; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_05 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM6_TB, + b_PLUS_, b_PLUS__p20_FSM3_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM6_TB, + e_x_PLUS, e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p0_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM6_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM6_TB, + p18, + p4, + p17, + p2, + p20, + p15, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input b_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM6_TB; + input b_PLUS__p20_FSM3_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p0_FSM6_TB; + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM6_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p18; + output p4; + output p17; + output p2; + output p20; + output p15; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_q_MINUS; + wire p18; + wire p4; + wire p17; + wire p2; + wire p20; + wire p15; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire b_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM6_TB; + assign b_PLUS__TB_sync = b_PLUS_ & b_PLUS__p20_FSM3_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM6_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM1_TB & e_x_PLUS_p0_FSM4_TB & e_x_PLUS_p0_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM4_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p18_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p18_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p4_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p4_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p17_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p17_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p2_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p2_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p20_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p20_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p15_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p15_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p9_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p13_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p8_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p11_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p6_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p20_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b1; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p18 = (state == p18_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p20 = (state == p20_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or b_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_q_MINUS = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p18_1HOT_ENCODING: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + // next_state = p20_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[4] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p4_1HOT_ENCODING: // + begin + if (c_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[11] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p17_1HOT_ENCODING: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + // next_state = p18_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p2_1HOT_ENCODING: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p20_1HOT_ENCODING: // + begin + if (b_PLUS__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p15_1HOT_ENCODING: // + begin + if (a_MINUS__TB_sync) + begin + // next_state = p17_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxxx1xxxxxx: // p9_1HOT_ENCODING: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + // next_state = p11_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[10] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p13_1HOT_ENCODING: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p8_1HOT_ENCODING: // + begin + if (c_MINUS__TB_sync) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p7_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[8] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p11_1HOT_ENCODING: // + begin + if (b_MINUS__TB_sync) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[7] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p6_1HOT_ENCODING: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[9] = 1'b1; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_06 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, + a_PLUS_, a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, + e_x_PLUS, e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, + e_y_MINUS, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, + p19, + p18, + p4, + p17, + p15, + p0, + p13, + p8, + p12, + p7, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB; + input a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_y_MINUS; + output e_y_MINUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB; + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p18; + output p4; + output p17; + output p15; + output p0; + output p13; + output p8; + output p12; + output p7; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_y_MINUS; + reg e_y_MINUSa; + reg e_q_MINUS; + wire p19; + wire p18; + wire p4; + wire p17; + wire p15; + wire p0; + wire p13; + wire p8; + wire p12; + wire p7; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM1_TB & a_PLUS__p19_FSM2_TB & a_PLUS__p19_FSM4_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM1_TB & e_x_PLUS_p0_FSM4_TB & e_x_PLUS_p2_FSM5_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p19_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p18_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p4_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p4_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p17_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p15_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p15_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p0_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p0_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p13_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p13_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p8_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p8_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p12_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p12_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p6_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p6_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p10_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p10_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p19_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_y_MINUS = 1'b0; + e_y_MINUSa = 1'b0; + e_q_MINUS = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p19_1HOT_ENCODING: // + begin + if (a_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p18_1HOT_ENCODING: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + // next_state = p19_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p4_1HOT_ENCODING: // + begin + if (c_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[10] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p17_1HOT_ENCODING: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + // next_state = p18_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p15_1HOT_ENCODING: // + begin + if (a_MINUS__TB_sync) + begin + // next_state = p17_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p0_1HOT_ENCODING: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxxx1xxxxxx: // p13_1HOT_ENCODING: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[4] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p8_1HOT_ENCODING: // + begin + if (c_MINUS__TB_sync) + begin + // next_state = p10_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[11] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p12_1HOT_ENCODING: // + begin + if (b_MINUS__TB_sync) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p7_1HOT_ENCODING: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[7] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p6_1HOT_ENCODING: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[9] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p10_1HOT_ENCODING: // + begin + e_y_MINUS = 1'b1; + // next_state = p12_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[8] = 1'b1; + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + diff --git a/examples/nowick_MG/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/nowick_MG/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..8e98cdf --- /dev/null +++ b/examples/nowick_MG/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,1710 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + a_PLUS_, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB, + a_MINUS_, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_x_PLUS, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_q_MINUS, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p19, + p18, + p4, + p17, + p15, + p0, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB; + input a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB; + input e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p18; + output p4; + output p17; + output p15; + output p0; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_q_MINUS; + wire p19; + wire p18; + wire p4; + wire p17; + wire p15; + wire p0; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM2_TB & a_PLUS__p19_FSM4_TB & a_PLUS__p19_FSM6_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM4_TB & e_x_PLUS_p2_FSM5_TB & e_x_PLUS_p0_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM5_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM4_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p4_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p15_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p0_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p19_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_q_MINUS = 1'b0; + + case (state) + p19_1HOT_ENCODING: // 12'b000000000001: // + begin + if (a_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p18_1HOT_ENCODING: // 12'b000000000010: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + next_state = p19_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 12'b000000000100: // + begin + if (c_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p17_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + next_state = p18_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 12'b000000010000: // + begin + if (a_MINUS__TB_sync) + begin + next_state = p17_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 12'b000000100000: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + next_state = p11_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 12'b000010000000: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 12'b000100000000: // + begin + if (c_MINUS__TB_sync) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 12'b001000000000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p11_1HOT_ENCODING: // 12'b010000000000: // + begin + if (b_MINUS__TB_sync) + begin + next_state = p13_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 12'b100000000000: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + a_PLUS_, a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_y_PLUS, e_y_PLUS_p3_FSM3_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p19, + p5, + p18, + p17, + p15, + p1, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM4_TB, a_PLUS__p19_FSM6_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_y_PLUS; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_y_PLUS_p3_FSM3_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p5; + output p18; + output p17; + output p15; + output p1; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_y_PLUS; + reg e_q_MINUS; + wire p19; + wire p5; + wire p18; + wire p17; + wire p15; + wire p1; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_y_PLUS_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM1_TB & a_PLUS__p19_FSM4_TB & a_PLUS__p19_FSM6_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM5_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM4_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_y_PLUS_TB_sync = e_y_PLUS_p3_FSM3_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p5_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p18_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p15_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p1_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p19_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_y_PLUS_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_y_PLUS = 1'b0; + e_q_MINUS = 1'b0; + + case (state) + p19_1HOT_ENCODING: // 12'b000000000001: // + begin + if (a_PLUS__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 12'b000000000010: // + begin + if (c_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p18_1HOT_ENCODING: // 12'b000000000100: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + next_state = p19_1HOT_ENCODING; + end + end + + p17_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + next_state = p18_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 12'b000000010000: // + begin + if (a_MINUS__TB_sync) + begin + next_state = p17_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 12'b000000100000: // + begin + if (e_y_PLUS_TB_sync) + begin + e_y_PLUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + next_state = p11_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 12'b000010000000: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 12'b000100000000: // + begin + if (c_MINUS__TB_sync) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 12'b001000000000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p11_1HOT_ENCODING: // 12'b010000000000: // + begin + if (b_MINUS__TB_sync) + begin + next_state = p13_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 12'b100000000000: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_03 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + b_PLUS_, b_PLUS__p20_FSM5_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_y_PLUS, e_y_PLUS_p1_FSM2_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p5, + p18, + p17, + p3, + p20, + p15, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input b_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input b_PLUS__p20_FSM5_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_y_PLUS; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM5_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM4_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_y_PLUS_p1_FSM2_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p5; + output p18; + output p17; + output p3; + output p20; + output p15; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_y_PLUS; + reg e_q_MINUS; + wire p5; + wire p18; + wire p17; + wire p3; + wire p20; + wire p15; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire b_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_y_PLUS_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign b_PLUS__TB_sync = b_PLUS_ & b_PLUS__p20_FSM5_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM5_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM4_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_y_PLUS_TB_sync = e_y_PLUS_p1_FSM2_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p5_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p17_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p3_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p20_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p15_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p20_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p20 = (state == p20_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or b_PLUS__TB_sync or a_MINUS__TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_y_PLUS_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_y_PLUS = 1'b0; + e_q_MINUS = 1'b0; + + case (state) + p5_1HOT_ENCODING: // 12'b000000000001: // + begin + if (c_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p18_1HOT_ENCODING: // 12'b000000000010: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + next_state = p20_1HOT_ENCODING; + end + end + + p17_1HOT_ENCODING: // 12'b000000000100: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + next_state = p18_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_y_PLUS_TB_sync) + begin + e_y_PLUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p20_1HOT_ENCODING: // 12'b000000010000: // + begin + if (b_PLUS__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 12'b000000100000: // + begin + if (a_MINUS__TB_sync) + begin + next_state = p17_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + next_state = p11_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 12'b000010000000: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 12'b000100000000: // + begin + if (c_MINUS__TB_sync) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 12'b001000000000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p11_1HOT_ENCODING: // 12'b010000000000: // + begin + if (b_MINUS__TB_sync) + begin + next_state = p13_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 12'b100000000000: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_04 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB, + a_PLUS_, a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM6_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB, + e_x_PLUS, e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM5_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB, + e_y_PLUSa, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB, + p19, + p18, + p4, + p17, + p16, + p0, + p9, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM5_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM5_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM5_TB, c_MINUS__p8_FSM6_TB; + input a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM6_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p15_FSM5_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_PLUSa; + output e_y_MINUSa; + output e_y_PLUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p2_FSM5_TB, e_x_PLUS_p0_FSM6_TB; + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM5_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM5_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM5_TB, e_y_MINUSa_p18_FSM6_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM5_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p18; + output p4; + output p17; + output p16; + output p0; + output p9; + output p8; + output p7; + output p11; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_y_PLUSa; + reg e_q_MINUS; + wire p19; + wire p18; + wire p4; + wire p17; + wire p16; + wire p0; + wire p9; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM5_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM5_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM5_TB & c_MINUS__p8_FSM6_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM1_TB & a_PLUS__p19_FSM2_TB & a_PLUS__p19_FSM6_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p15_FSM5_TB & a_MINUS__p15_FSM6_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM1_TB & e_x_PLUS_p2_FSM5_TB & e_x_PLUS_p0_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM5_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM5_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM5_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM5_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p4_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p16_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p14_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p0_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p9_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p19_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p16 = (state == p16_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_y_PLUSa = 1'b0; + e_q_MINUS = 1'b0; + + case (state) + p19_1HOT_ENCODING: // 12'b000000000001: // + begin + if (a_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p18_1HOT_ENCODING: // 12'b000000000010: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + next_state = p19_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 12'b000000000100: // + begin + if (c_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p17_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + next_state = p18_1HOT_ENCODING; + end + end + + p16_1HOT_ENCODING: // 12'b000000010000: // + begin + if (a_MINUS__TB_sync) + begin + next_state = p17_1HOT_ENCODING; + end + end + + p14_1HOT_ENCODING: // 12'b000000100000: // + begin + e_y_PLUSa = 1'b1; + next_state = p16_1HOT_ENCODING; + end + + p0_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 12'b000010000000: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + next_state = p11_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 12'b000100000000: // + begin + if (c_MINUS__TB_sync) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 12'b001000000000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p11_1HOT_ENCODING: // 12'b010000000000: // + begin + if (b_MINUS__TB_sync) + begin + next_state = p14_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 12'b100000000000: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_05 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p12_FSM6_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM6_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM6_TB, + b_PLUS_, b_PLUS__p20_FSM3_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM6_TB, + e_x_PLUS, e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p0_FSM6_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM6_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM6_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM6_TB, + e_x_PLUSa, e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM6_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM6_TB, + p18, + p4, + p17, + p2, + p20, + p15, + p9, + p13, + p8, + p7, + p11, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input b_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p12_FSM6_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM6_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM6_TB; + input b_PLUS__p20_FSM3_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM6_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_x_PLUSa; + output e_y_MINUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p0_FSM6_TB; + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM6_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM6_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM6_TB; + input e_x_PLUSa_p9_FSM1_TB, e_x_PLUSa_p9_FSM2_TB, e_x_PLUSa_p9_FSM3_TB, e_x_PLUSa_p9_FSM4_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM6_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p18; + output p4; + output p17; + output p2; + output p20; + output p15; + output p9; + output p13; + output p8; + output p7; + output p11; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_x_PLUSa; + reg e_y_MINUSa; + reg e_q_MINUS; + wire p18; + wire p4; + wire p17; + wire p2; + wire p20; + wire p15; + wire p9; + wire p13; + wire p8; + wire p7; + wire p11; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire b_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_x_PLUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p12_FSM6_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM6_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM6_TB; + assign b_PLUS__TB_sync = b_PLUS_ & b_PLUS__p20_FSM3_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM6_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM1_TB & e_x_PLUS_p0_FSM4_TB & e_x_PLUS_p0_FSM6_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM6_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM6_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM6_TB; + assign e_x_PLUSa_TB_sync = e_x_PLUSa_p9_FSM1_TB & e_x_PLUSa_p9_FSM2_TB & e_x_PLUSa_p9_FSM3_TB & e_x_PLUSa_p9_FSM4_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM6_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM6_TB; + + parameter p18_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p4_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p17_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p2_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p20_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p15_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p9_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p13_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p8_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p11_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p6_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p20_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p18 = (state == p18_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p20 = (state == p20_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or b_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_x_PLUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_x_PLUSa = 1'b0; + e_y_MINUSa = 1'b0; + e_q_MINUS = 1'b0; + + case (state) + p18_1HOT_ENCODING: // 12'b000000000001: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + next_state = p20_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 12'b000000000010: // + begin + if (c_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p17_1HOT_ENCODING: // 12'b000000000100: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + next_state = p18_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p20_1HOT_ENCODING: // 12'b000000010000: // + begin + if (b_PLUS__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 12'b000000100000: // + begin + if (a_MINUS__TB_sync) + begin + next_state = p17_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_x_PLUSa_TB_sync) + begin + e_x_PLUSa = 1'b1; + next_state = p11_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 12'b000010000000: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 12'b000100000000: // + begin + if (c_MINUS__TB_sync) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 12'b001000000000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p11_1HOT_ENCODING: // 12'b010000000000: // + begin + if (b_MINUS__TB_sync) + begin + next_state = p13_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 12'b100000000000: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_06 ( + clk, + reset, + b_MINUS_, b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB, + c_PLUS_, c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB, + c_MINUS_, c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB, + a_PLUS_, a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB, + a_MINUS_, a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB, + e_x_PLUS, e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB, + e_q_PLUS, e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB, + e_x_MINUS, e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB, + e_x_MINUSa, e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB, + e_y_MINUS, + e_y_MINUSa, e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB, + e_q_MINUS, e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB, + p19, + p18, + p4, + p17, + p15, + p0, + p13, + p8, + p12, + p7, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_MINUS_; + input c_PLUS_; + input c_MINUS_; + input a_PLUS_; + input a_MINUS_; + // Transition Barrier Inputs for input Signals // + input b_MINUS__p11_FSM1_TB, b_MINUS__p11_FSM2_TB, b_MINUS__p11_FSM3_TB, b_MINUS__p11_FSM4_TB, b_MINUS__p11_FSM5_TB; + input c_PLUS__p4_FSM1_TB, c_PLUS__p5_FSM2_TB, c_PLUS__p5_FSM3_TB, c_PLUS__p4_FSM4_TB, c_PLUS__p4_FSM5_TB; + input c_MINUS__p8_FSM1_TB, c_MINUS__p8_FSM2_TB, c_MINUS__p8_FSM3_TB, c_MINUS__p8_FSM4_TB, c_MINUS__p8_FSM5_TB; + input a_PLUS__p19_FSM1_TB, a_PLUS__p19_FSM2_TB, a_PLUS__p19_FSM4_TB; + input a_MINUS__p15_FSM1_TB, a_MINUS__p15_FSM2_TB, a_MINUS__p15_FSM3_TB, a_MINUS__p16_FSM4_TB, a_MINUS__p15_FSM5_TB; + + // Regular output Signals // + output e_x_PLUS; + output e_q_PLUS; + output e_x_MINUS; + output e_x_MINUSa; + output e_y_MINUS; + output e_y_MINUSa; + output e_q_MINUS; + // Transition Barrier outputs for output Signals // + input e_x_PLUS_p0_FSM1_TB, e_x_PLUS_p0_FSM4_TB, e_x_PLUS_p2_FSM5_TB; + input e_q_PLUS_p6_FSM1_TB, e_q_PLUS_p6_FSM2_TB, e_q_PLUS_p6_FSM3_TB, e_q_PLUS_p6_FSM4_TB, e_q_PLUS_p6_FSM5_TB; + input e_x_MINUS_p7_FSM1_TB, e_x_MINUS_p7_FSM2_TB, e_x_MINUS_p7_FSM3_TB, e_x_MINUS_p7_FSM4_TB, e_x_MINUS_p7_FSM5_TB; + input e_x_MINUSa_p13_FSM1_TB, e_x_MINUSa_p13_FSM2_TB, e_x_MINUSa_p13_FSM3_TB, e_x_MINUSa_p13_FSM5_TB; + input e_y_MINUSa_p18_FSM1_TB, e_y_MINUSa_p18_FSM2_TB, e_y_MINUSa_p18_FSM3_TB, e_y_MINUSa_p18_FSM4_TB, e_y_MINUSa_p18_FSM5_TB; + input e_q_MINUS_p17_FSM1_TB, e_q_MINUS_p17_FSM2_TB, e_q_MINUS_p17_FSM3_TB, e_q_MINUS_p17_FSM4_TB, e_q_MINUS_p17_FSM5_TB; + + // FSMs' Synchronisation output Signals // + output p19; + output p18; + output p4; + output p17; + output p15; + output p0; + output p13; + output p8; + output p12; + output p7; + output p6; + + reg e_x_PLUS; + reg e_q_PLUS; + reg e_x_MINUS; + reg e_x_MINUSa; + reg e_y_MINUS; + reg e_y_MINUSa; + reg e_q_MINUS; + wire p19; + wire p18; + wire p4; + wire p17; + wire p15; + wire p0; + wire p13; + wire p8; + wire p12; + wire p7; + wire p6; + + wire b_MINUS__TB_sync; + wire c_PLUS__TB_sync; + wire c_MINUS__TB_sync; + wire a_PLUS__TB_sync; + wire a_MINUS__TB_sync; + wire e_x_PLUS_TB_sync; + wire e_q_PLUS_TB_sync; + wire e_x_MINUS_TB_sync; + wire e_x_MINUSa_TB_sync; + wire e_y_MINUSa_TB_sync; + wire e_q_MINUS_TB_sync; + assign b_MINUS__TB_sync = b_MINUS_ & b_MINUS__p11_FSM1_TB & b_MINUS__p11_FSM2_TB & b_MINUS__p11_FSM3_TB & b_MINUS__p11_FSM4_TB & b_MINUS__p11_FSM5_TB; + assign c_PLUS__TB_sync = c_PLUS_ & c_PLUS__p4_FSM1_TB & c_PLUS__p5_FSM2_TB & c_PLUS__p5_FSM3_TB & c_PLUS__p4_FSM4_TB & c_PLUS__p4_FSM5_TB; + assign c_MINUS__TB_sync = c_MINUS_ & c_MINUS__p8_FSM1_TB & c_MINUS__p8_FSM2_TB & c_MINUS__p8_FSM3_TB & c_MINUS__p8_FSM4_TB & c_MINUS__p8_FSM5_TB; + assign a_PLUS__TB_sync = a_PLUS_ & a_PLUS__p19_FSM1_TB & a_PLUS__p19_FSM2_TB & a_PLUS__p19_FSM4_TB; + assign a_MINUS__TB_sync = a_MINUS_ & a_MINUS__p15_FSM1_TB & a_MINUS__p15_FSM2_TB & a_MINUS__p15_FSM3_TB & a_MINUS__p16_FSM4_TB & a_MINUS__p15_FSM5_TB; + assign e_x_PLUS_TB_sync = e_x_PLUS_p0_FSM1_TB & e_x_PLUS_p0_FSM4_TB & e_x_PLUS_p2_FSM5_TB; + assign e_q_PLUS_TB_sync = e_q_PLUS_p6_FSM1_TB & e_q_PLUS_p6_FSM2_TB & e_q_PLUS_p6_FSM3_TB & e_q_PLUS_p6_FSM4_TB & e_q_PLUS_p6_FSM5_TB; + assign e_x_MINUS_TB_sync = e_x_MINUS_p7_FSM1_TB & e_x_MINUS_p7_FSM2_TB & e_x_MINUS_p7_FSM3_TB & e_x_MINUS_p7_FSM4_TB & e_x_MINUS_p7_FSM5_TB; + assign e_x_MINUSa_TB_sync = e_x_MINUSa_p13_FSM1_TB & e_x_MINUSa_p13_FSM2_TB & e_x_MINUSa_p13_FSM3_TB & e_x_MINUSa_p13_FSM5_TB; + assign e_y_MINUSa_TB_sync = e_y_MINUSa_p18_FSM1_TB & e_y_MINUSa_p18_FSM2_TB & e_y_MINUSa_p18_FSM3_TB & e_y_MINUSa_p18_FSM4_TB & e_y_MINUSa_p18_FSM5_TB; + assign e_q_MINUS_TB_sync = e_q_MINUS_p17_FSM1_TB & e_q_MINUS_p17_FSM2_TB & e_q_MINUS_p17_FSM3_TB & e_q_MINUS_p17_FSM4_TB & e_q_MINUS_p17_FSM5_TB; + + parameter p19_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p18_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p4_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p17_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p15_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p0_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p13_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p8_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p12_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p7_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p6_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p10_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p19_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p19 = (state == p19_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p18 = (state == p18_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p17 = (state == p17_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_MINUS__TB_sync or c_PLUS__TB_sync or c_MINUS__TB_sync or a_PLUS__TB_sync or a_MINUS__TB_sync or e_x_PLUS_TB_sync or e_q_PLUS_TB_sync or e_x_MINUS_TB_sync or e_x_MINUSa_TB_sync or e_y_MINUSa_TB_sync or e_q_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_x_PLUS = 1'b0; + e_q_PLUS = 1'b0; + e_x_MINUS = 1'b0; + e_x_MINUSa = 1'b0; + e_y_MINUS = 1'b0; + e_y_MINUSa = 1'b0; + e_q_MINUS = 1'b0; + + case (state) + p19_1HOT_ENCODING: // 12'b000000000001: // + begin + if (a_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p18_1HOT_ENCODING: // 12'b000000000010: // + begin + if (e_y_MINUSa_TB_sync) + begin + e_y_MINUSa = 1'b1; + next_state = p19_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 12'b000000000100: // + begin + if (c_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p17_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_q_MINUS_TB_sync) + begin + e_q_MINUS = 1'b1; + next_state = p18_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 12'b000000010000: // + begin + if (a_MINUS__TB_sync) + begin + next_state = p17_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 12'b000000100000: // + begin + if (e_x_PLUS_TB_sync) + begin + e_x_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_x_MINUSa_TB_sync) + begin + e_x_MINUSa = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 12'b000010000000: // + begin + if (c_MINUS__TB_sync) + begin + next_state = p10_1HOT_ENCODING; + end + end + + p12_1HOT_ENCODING: // 12'b000100000000: // + begin + if (b_MINUS__TB_sync) + begin + next_state = p13_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 12'b001000000000: // + begin + if (e_x_MINUS_TB_sync) + begin + e_x_MINUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 12'b010000000000: // + begin + if (e_q_PLUS_TB_sync) + begin + e_q_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + p10_1HOT_ENCODING: // 12'b100000000000: // + begin + e_y_MINUS = 1'b1; + next_state = p12_1HOT_ENCODING; + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + diff --git a/examples/nowick_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/nowick_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..28483aa --- /dev/null +++ b/examples/nowick_MG/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,243 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + x_PLUS, + q_PLUS, + b_MINUS, + c_PLUS, + x_MINUS, + c_MINUS, + x_MINUSa, + y_MINUS, + x_PLUSa, + b_PLUS, + y_MINUSa, + y_PLUS, + y_PLUSa, + a_PLUS, + a_MINUS, + q_MINUS); + + input clk; + input reset; + output x_PLUS; + output q_PLUS; + input b_MINUS; + input c_PLUS; + output x_MINUS; + input c_MINUS; + output x_MINUSa; + output y_MINUS; + output x_PLUSa; + input b_PLUS; + output y_MINUSa; + output y_PLUS; + output y_PLUSa; + input a_PLUS; + input a_MINUS; + output q_MINUS; + + wire e_x_PLUS_FSM1out, e_q_PLUS_FSM1out, e_x_MINUS_FSM1out, e_x_MINUSa_FSM1out, e_x_PLUSa_FSM1out, e_y_MINUSa_FSM1out, e_q_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p19_FSM1out, p18_FSM1out, p4_FSM1out, p17_FSM1out, p15_FSM1out, p0_FSM1out, p9_FSM1out, p13_FSM1out, p8_FSM1out, p7_FSM1out, p11_FSM1out, p6_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_q_PLUS_FSM2out, e_x_MINUS_FSM2out, e_x_MINUSa_FSM2out, e_x_PLUSa_FSM2out, e_y_MINUSa_FSM2out, e_y_PLUS_FSM2out, e_q_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p19_FSM2out, p5_FSM2out, p18_FSM2out, p17_FSM2out, p15_FSM2out, p1_FSM2out, p9_FSM2out, p13_FSM2out, p8_FSM2out, p7_FSM2out, p11_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_q_PLUS_FSM3out, e_x_MINUS_FSM3out, e_x_MINUSa_FSM3out, e_x_PLUSa_FSM3out, e_y_MINUSa_FSM3out, e_y_PLUS_FSM3out, e_q_MINUS_FSM3out; // Regular output signals of FSM3 // + wire p5_FSM3out, p18_FSM3out, p17_FSM3out, p3_FSM3out, p20_FSM3out, p15_FSM3out, p9_FSM3out, p13_FSM3out, p8_FSM3out, p7_FSM3out, p11_FSM3out, p6_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_x_PLUS_FSM4out, e_q_PLUS_FSM4out, e_x_MINUS_FSM4out, e_x_PLUSa_FSM4out, e_y_MINUSa_FSM4out, e_y_PLUSa_FSM4out, e_q_MINUS_FSM4out; // Regular output signals of FSM4 // + wire p19_FSM4out, p18_FSM4out, p4_FSM4out, p17_FSM4out, p16_FSM4out, p14_FSM4out, p0_FSM4out, p9_FSM4out, p8_FSM4out, p7_FSM4out, p11_FSM4out, p6_FSM4out; // State Synchronisation output signals of FSM4 // + wire e_x_PLUS_FSM5out, e_q_PLUS_FSM5out, e_x_MINUS_FSM5out, e_x_MINUSa_FSM5out, e_x_PLUSa_FSM5out, e_y_MINUSa_FSM5out, e_q_MINUS_FSM5out; // Regular output signals of FSM5 // + wire p18_FSM5out, p4_FSM5out, p17_FSM5out, p2_FSM5out, p20_FSM5out, p15_FSM5out, p9_FSM5out, p13_FSM5out, p8_FSM5out, p7_FSM5out, p11_FSM5out, p6_FSM5out; // State Synchronisation output signals of FSM5 // + wire e_x_PLUS_FSM6out, e_q_PLUS_FSM6out, e_x_MINUS_FSM6out, e_x_MINUSa_FSM6out, e_y_MINUS_FSM6out, e_y_MINUSa_FSM6out, e_q_MINUS_FSM6out; // Regular output signals of FSM6 // + wire p19_FSM6out, p18_FSM6out, p4_FSM6out, p17_FSM6out, p15_FSM6out, p0_FSM6out, p13_FSM6out, p8_FSM6out, p12_FSM6out, p7_FSM6out, p6_FSM6out, p10_FSM6out; // State Synchronisation output signals of FSM6 // + + assign x_PLUS = e_x_PLUS_FSM1out & e_x_PLUS_FSM4out & e_x_PLUS_FSM5out & e_x_PLUS_FSM6out; + assign q_PLUS = e_q_PLUS_FSM1out & e_q_PLUS_FSM2out & e_q_PLUS_FSM3out & e_q_PLUS_FSM4out & e_q_PLUS_FSM5out & e_q_PLUS_FSM6out; + assign x_MINUS = e_x_MINUS_FSM1out & e_x_MINUS_FSM2out & e_x_MINUS_FSM3out & e_x_MINUS_FSM4out & e_x_MINUS_FSM5out & e_x_MINUS_FSM6out; + assign x_MINUSa = e_x_MINUSa_FSM1out & e_x_MINUSa_FSM2out & e_x_MINUSa_FSM3out & e_x_MINUSa_FSM5out & e_x_MINUSa_FSM6out; + assign y_MINUS = e_y_MINUS_FSM6out; + assign x_PLUSa = e_x_PLUSa_FSM1out & e_x_PLUSa_FSM2out & e_x_PLUSa_FSM3out & e_x_PLUSa_FSM4out & e_x_PLUSa_FSM5out; + assign y_MINUSa = e_y_MINUSa_FSM1out & e_y_MINUSa_FSM2out & e_y_MINUSa_FSM3out & e_y_MINUSa_FSM4out & e_y_MINUSa_FSM5out & e_y_MINUSa_FSM6out; + assign y_PLUS = e_y_PLUS_FSM2out & e_y_PLUS_FSM3out; + assign y_PLUSa = e_y_PLUSa_FSM4out; + assign q_MINUS = e_q_MINUS_FSM1out & e_q_MINUS_FSM2out & e_q_MINUS_FSM3out & e_q_MINUS_FSM4out & e_q_MINUS_FSM5out & e_q_MINUS_FSM6out; + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(e_x_PLUS_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_q_MINUS(e_q_MINUS_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p19(p19_FSM1out), + .p18(p18_FSM1out), + .p4(p4_FSM1out), + .p17(p17_FSM1out), + .p15(p15_FSM1out), + .p0(p0_FSM1out), + .p9(p9_FSM1out), + .p13(p13_FSM1out), + .p8(p8_FSM1out), + .p7(p7_FSM1out), + .p11(p11_FSM1out), + .p6(p6_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM2out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM2out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM2out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM2out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM2out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUS(e_y_PLUS_FSM2out), .e_y_PLUS_p3_FSM3_TB(p3_FSM3out), + .e_q_MINUS(e_q_MINUS_FSM2out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p19(p19_FSM2out), + .p5(p5_FSM2out), + .p18(p18_FSM2out), + .p17(p17_FSM2out), + .p15(p15_FSM2out), + .p1(p1_FSM2out), + .p9(p9_FSM2out), + .p13(p13_FSM2out), + .p8(p8_FSM2out), + .p7(p7_FSM2out), + .p11(p11_FSM2out), + .p6(p6_FSM2out) + ); + + + fsm_mealy_behav_03 fsm_mealy_behav_03_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .b_PLUS_(b_PLUS), .b_PLUS__p20_FSM5_TB(p20_FSM5out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM3out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM3out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM3out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM3out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM3out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUS(e_y_PLUS_FSM3out), .e_y_PLUS_p1_FSM2_TB(p1_FSM2out), + .e_q_MINUS(e_q_MINUS_FSM3out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p5(p5_FSM3out), + .p18(p18_FSM3out), + .p17(p17_FSM3out), + .p3(p3_FSM3out), + .p20(p20_FSM3out), + .p15(p15_FSM3out), + .p9(p9_FSM3out), + .p13(p13_FSM3out), + .p8(p8_FSM3out), + .p7(p7_FSM3out), + .p11(p11_FSM3out), + .p6(p6_FSM3out) + ); + + + fsm_mealy_behav_04 fsm_mealy_behav_04_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(e_x_PLUS_FSM4out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM4out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM4out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM4out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM4out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUSa(e_y_PLUSa_FSM4out), + .e_q_MINUS(e_q_MINUS_FSM4out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p19(p19_FSM4out), + .p18(p18_FSM4out), + .p4(p4_FSM4out), + .p17(p17_FSM4out), + .p16(p16_FSM4out), + .p0(p0_FSM4out), + .p9(p9_FSM4out), + .p8(p8_FSM4out), + .p7(p7_FSM4out), + .p11(p11_FSM4out), + .p6(p6_FSM4out) + ); + + + fsm_mealy_behav_05 fsm_mealy_behav_05_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .b_PLUS_(b_PLUS), .b_PLUS__p20_FSM3_TB(p20_FSM3out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(e_x_PLUS_FSM5out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM5out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM5out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM5out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM5out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), + .e_y_MINUSa(e_y_MINUSa_FSM5out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_q_MINUS(e_q_MINUS_FSM5out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p18(p18_FSM5out), + .p4(p4_FSM5out), + .p17(p17_FSM5out), + .p2(p2_FSM5out), + .p20(p20_FSM5out), + .p15(p15_FSM5out), + .p9(p9_FSM5out), + .p13(p13_FSM5out), + .p8(p8_FSM5out), + .p7(p7_FSM5out), + .p11(p11_FSM5out), + .p6(p6_FSM5out) + ); + + + fsm_mealy_behav_06 fsm_mealy_behav_06_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), + .e_x_PLUS(e_x_PLUS_FSM6out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), + .e_q_PLUS(e_q_PLUS_FSM6out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), + .e_x_MINUS(e_x_MINUS_FSM6out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), + .e_x_MINUSa(e_x_MINUSa_FSM6out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), + .e_y_MINUS(e_y_MINUS_FSM6out), + .e_y_MINUSa(e_y_MINUSa_FSM6out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), + .e_q_MINUS(e_q_MINUS_FSM6out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), + .p19(p19_FSM6out), + .p18(p18_FSM6out), + .p4(p4_FSM6out), + .p17(p17_FSM6out), + .p15(p15_FSM6out), + .p0(p0_FSM6out), + .p13(p13_FSM6out), + .p8(p8_FSM6out), + .p12(p12_FSM6out), + .p7(p7_FSM6out), + .p6(p6_FSM6out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/nowick_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/nowick_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..a94944d --- /dev/null +++ b/examples/nowick_MG/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,243 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + x_PLUS, + q_PLUS, + b_MINUS, + c_PLUS, + x_MINUS, + c_MINUS, + x_MINUSa, + y_MINUS, + x_PLUSa, + b_PLUS, + y_MINUSa, + y_PLUS, + y_PLUSa, + a_PLUS, + a_MINUS, + q_MINUS); + + input clk; + input reset; + output x_PLUS; + output q_PLUS; + input b_MINUS; + input c_PLUS; + output x_MINUS; + input c_MINUS; + output x_MINUSa; + output y_MINUS; + output x_PLUSa; + input b_PLUS; + output y_MINUSa; + output y_PLUS; + output y_PLUSa; + input a_PLUS; + input a_MINUS; + output q_MINUS; + + wire e_x_PLUS_FSM1out, e_q_PLUS_FSM1out, e_x_MINUS_FSM1out, e_x_MINUSa_FSM1out, e_x_PLUSa_FSM1out, e_y_MINUSa_FSM1out, e_q_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p19_FSM1out, p18_FSM1out, p4_FSM1out, p17_FSM1out, p15_FSM1out, p0_FSM1out, p9_FSM1out, p13_FSM1out, p8_FSM1out, p7_FSM1out, p11_FSM1out, p6_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_q_PLUS_FSM2out, e_x_MINUS_FSM2out, e_x_MINUSa_FSM2out, e_x_PLUSa_FSM2out, e_y_MINUSa_FSM2out, e_y_PLUS_FSM2out, e_q_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p19_FSM2out, p5_FSM2out, p18_FSM2out, p17_FSM2out, p15_FSM2out, p1_FSM2out, p9_FSM2out, p13_FSM2out, p8_FSM2out, p7_FSM2out, p11_FSM2out, p6_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_q_PLUS_FSM3out, e_x_MINUS_FSM3out, e_x_MINUSa_FSM3out, e_x_PLUSa_FSM3out, e_y_MINUSa_FSM3out, e_y_PLUS_FSM3out, e_q_MINUS_FSM3out; // Regular output signals of FSM3 // + wire p5_FSM3out, p18_FSM3out, p17_FSM3out, p3_FSM3out, p20_FSM3out, p15_FSM3out, p9_FSM3out, p13_FSM3out, p8_FSM3out, p7_FSM3out, p11_FSM3out, p6_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_x_PLUS_FSM4out, e_q_PLUS_FSM4out, e_x_MINUS_FSM4out, e_x_PLUSa_FSM4out, e_y_MINUSa_FSM4out, e_y_PLUSa_FSM4out, e_q_MINUS_FSM4out; // Regular output signals of FSM4 // + wire p19_FSM4out, p18_FSM4out, p4_FSM4out, p17_FSM4out, p16_FSM4out, p14_FSM4out, p0_FSM4out, p9_FSM4out, p8_FSM4out, p7_FSM4out, p11_FSM4out, p6_FSM4out; // State Synchronisation output signals of FSM4 // + wire e_x_PLUS_FSM5out, e_q_PLUS_FSM5out, e_x_MINUS_FSM5out, e_x_MINUSa_FSM5out, e_x_PLUSa_FSM5out, e_y_MINUSa_FSM5out, e_q_MINUS_FSM5out; // Regular output signals of FSM5 // + wire p18_FSM5out, p4_FSM5out, p17_FSM5out, p2_FSM5out, p20_FSM5out, p15_FSM5out, p9_FSM5out, p13_FSM5out, p8_FSM5out, p7_FSM5out, p11_FSM5out, p6_FSM5out; // State Synchronisation output signals of FSM5 // + wire e_x_PLUS_FSM6out, e_q_PLUS_FSM6out, e_x_MINUS_FSM6out, e_x_MINUSa_FSM6out, e_y_MINUS_FSM6out, e_y_MINUSa_FSM6out, e_q_MINUS_FSM6out; // Regular output signals of FSM6 // + wire p19_FSM6out, p18_FSM6out, p4_FSM6out, p17_FSM6out, p15_FSM6out, p0_FSM6out, p13_FSM6out, p8_FSM6out, p12_FSM6out, p7_FSM6out, p6_FSM6out, p10_FSM6out; // State Synchronisation output signals of FSM6 // + + assign x_PLUS = e_x_PLUS_FSM1out & e_x_PLUS_FSM4out & e_x_PLUS_FSM5out & e_x_PLUS_FSM6out; + assign q_PLUS = e_q_PLUS_FSM1out & e_q_PLUS_FSM2out & e_q_PLUS_FSM3out & e_q_PLUS_FSM4out & e_q_PLUS_FSM5out & e_q_PLUS_FSM6out; + assign x_MINUS = e_x_MINUS_FSM1out & e_x_MINUS_FSM2out & e_x_MINUS_FSM3out & e_x_MINUS_FSM4out & e_x_MINUS_FSM5out & e_x_MINUS_FSM6out; + assign x_MINUSa = e_x_MINUSa_FSM1out & e_x_MINUSa_FSM2out & e_x_MINUSa_FSM3out & e_x_MINUSa_FSM5out & e_x_MINUSa_FSM6out; + assign y_MINUS = e_y_MINUS_FSM6out; + assign x_PLUSa = e_x_PLUSa_FSM1out & e_x_PLUSa_FSM2out & e_x_PLUSa_FSM3out & e_x_PLUSa_FSM4out & e_x_PLUSa_FSM5out; + assign y_MINUSa = e_y_MINUSa_FSM1out & e_y_MINUSa_FSM2out & e_y_MINUSa_FSM3out & e_y_MINUSa_FSM4out & e_y_MINUSa_FSM5out & e_y_MINUSa_FSM6out; + assign y_PLUS = e_y_PLUS_FSM2out & e_y_PLUS_FSM3out; + assign y_PLUSa = e_y_PLUSa_FSM4out; + assign q_MINUS = e_q_MINUS_FSM1out & e_q_MINUS_FSM2out & e_q_MINUS_FSM3out & e_q_MINUS_FSM4out & e_q_MINUS_FSM5out & e_q_MINUS_FSM6out; + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(e_x_PLUS_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_q_MINUS(e_q_MINUS_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p19(p19_FSM1out), + .p18(p18_FSM1out), + .p4(p4_FSM1out), + .p17(p17_FSM1out), + .p15(p15_FSM1out), + .p0(p0_FSM1out), + .p9(p9_FSM1out), + .p13(p13_FSM1out), + .p8(p8_FSM1out), + .p7(p7_FSM1out), + .p11(p11_FSM1out), + .p6(p6_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM2out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM2out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM2out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM2out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM2out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUS(e_y_PLUS_FSM2out), .e_y_PLUS_p3_FSM3_TB(p3_FSM3out), + .e_q_MINUS(e_q_MINUS_FSM2out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p19(p19_FSM2out), + .p5(p5_FSM2out), + .p18(p18_FSM2out), + .p17(p17_FSM2out), + .p15(p15_FSM2out), + .p1(p1_FSM2out), + .p9(p9_FSM2out), + .p13(p13_FSM2out), + .p8(p8_FSM2out), + .p7(p7_FSM2out), + .p11(p11_FSM2out), + .p6(p6_FSM2out) + ); + + + fsm_mealy_synth_03 fsm_mealy_synth_03_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .b_PLUS_(b_PLUS), .b_PLUS__p20_FSM5_TB(p20_FSM5out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM3out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM3out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM3out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM3out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM3out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUS(e_y_PLUS_FSM3out), .e_y_PLUS_p1_FSM2_TB(p1_FSM2out), + .e_q_MINUS(e_q_MINUS_FSM3out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p5(p5_FSM3out), + .p18(p18_FSM3out), + .p17(p17_FSM3out), + .p3(p3_FSM3out), + .p20(p20_FSM3out), + .p15(p15_FSM3out), + .p9(p9_FSM3out), + .p13(p13_FSM3out), + .p8(p8_FSM3out), + .p7(p7_FSM3out), + .p11(p11_FSM3out), + .p6(p6_FSM3out) + ); + + + fsm_mealy_synth_04 fsm_mealy_synth_04_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM6_TB(p19_FSM6out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(e_x_PLUS_FSM4out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM4out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM4out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM4out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM5_TB(p9_FSM5out), + .e_y_MINUSa(e_y_MINUSa_FSM4out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_y_PLUSa(e_y_PLUSa_FSM4out), + .e_q_MINUS(e_q_MINUS_FSM4out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p19(p19_FSM4out), + .p18(p18_FSM4out), + .p4(p4_FSM4out), + .p17(p17_FSM4out), + .p16(p16_FSM4out), + .p0(p0_FSM4out), + .p9(p9_FSM4out), + .p8(p8_FSM4out), + .p7(p7_FSM4out), + .p11(p11_FSM4out), + .p6(p6_FSM4out) + ); + + + fsm_mealy_synth_05 fsm_mealy_synth_05_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p12_FSM6_TB(p12_FSM6out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM6_TB(p4_FSM6out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM6_TB(p8_FSM6out), + .b_PLUS_(b_PLUS), .b_PLUS__p20_FSM3_TB(p20_FSM3out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM6_TB(p15_FSM6out), + .e_x_PLUS(e_x_PLUS_FSM5out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p0_FSM6_TB(p0_FSM6out), + .e_q_PLUS(e_q_PLUS_FSM5out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM6_TB(p6_FSM6out), + .e_x_MINUS(e_x_MINUS_FSM5out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM6_TB(p7_FSM6out), + .e_x_MINUSa(e_x_MINUSa_FSM5out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM6_TB(p13_FSM6out), + .e_x_PLUSa(e_x_PLUSa_FSM5out), .e_x_PLUSa_p9_FSM1_TB(p9_FSM1out), .e_x_PLUSa_p9_FSM2_TB(p9_FSM2out), .e_x_PLUSa_p9_FSM3_TB(p9_FSM3out), .e_x_PLUSa_p9_FSM4_TB(p9_FSM4out), + .e_y_MINUSa(e_y_MINUSa_FSM5out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM6_TB(p18_FSM6out), + .e_q_MINUS(e_q_MINUS_FSM5out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM6_TB(p17_FSM6out), + .p18(p18_FSM5out), + .p4(p4_FSM5out), + .p17(p17_FSM5out), + .p2(p2_FSM5out), + .p20(p20_FSM5out), + .p15(p15_FSM5out), + .p9(p9_FSM5out), + .p13(p13_FSM5out), + .p8(p8_FSM5out), + .p7(p7_FSM5out), + .p11(p11_FSM5out), + .p6(p6_FSM5out) + ); + + + fsm_mealy_synth_06 fsm_mealy_synth_06_inst ( + .clk(clk), + .reset(reset), + .b_MINUS_(b_MINUS), .b_MINUS__p11_FSM1_TB(p11_FSM1out), .b_MINUS__p11_FSM2_TB(p11_FSM2out), .b_MINUS__p11_FSM3_TB(p11_FSM3out), .b_MINUS__p11_FSM4_TB(p11_FSM4out), .b_MINUS__p11_FSM5_TB(p11_FSM5out), + .c_PLUS_(c_PLUS), .c_PLUS__p4_FSM1_TB(p4_FSM1out), .c_PLUS__p5_FSM2_TB(p5_FSM2out), .c_PLUS__p5_FSM3_TB(p5_FSM3out), .c_PLUS__p4_FSM4_TB(p4_FSM4out), .c_PLUS__p4_FSM5_TB(p4_FSM5out), + .c_MINUS_(c_MINUS), .c_MINUS__p8_FSM1_TB(p8_FSM1out), .c_MINUS__p8_FSM2_TB(p8_FSM2out), .c_MINUS__p8_FSM3_TB(p8_FSM3out), .c_MINUS__p8_FSM4_TB(p8_FSM4out), .c_MINUS__p8_FSM5_TB(p8_FSM5out), + .a_PLUS_(a_PLUS), .a_PLUS__p19_FSM1_TB(p19_FSM1out), .a_PLUS__p19_FSM2_TB(p19_FSM2out), .a_PLUS__p19_FSM4_TB(p19_FSM4out), + .a_MINUS_(a_MINUS), .a_MINUS__p15_FSM1_TB(p15_FSM1out), .a_MINUS__p15_FSM2_TB(p15_FSM2out), .a_MINUS__p15_FSM3_TB(p15_FSM3out), .a_MINUS__p16_FSM4_TB(p16_FSM4out), .a_MINUS__p15_FSM5_TB(p15_FSM5out), + .e_x_PLUS(e_x_PLUS_FSM6out), .e_x_PLUS_p0_FSM1_TB(p0_FSM1out), .e_x_PLUS_p0_FSM4_TB(p0_FSM4out), .e_x_PLUS_p2_FSM5_TB(p2_FSM5out), + .e_q_PLUS(e_q_PLUS_FSM6out), .e_q_PLUS_p6_FSM1_TB(p6_FSM1out), .e_q_PLUS_p6_FSM2_TB(p6_FSM2out), .e_q_PLUS_p6_FSM3_TB(p6_FSM3out), .e_q_PLUS_p6_FSM4_TB(p6_FSM4out), .e_q_PLUS_p6_FSM5_TB(p6_FSM5out), + .e_x_MINUS(e_x_MINUS_FSM6out), .e_x_MINUS_p7_FSM1_TB(p7_FSM1out), .e_x_MINUS_p7_FSM2_TB(p7_FSM2out), .e_x_MINUS_p7_FSM3_TB(p7_FSM3out), .e_x_MINUS_p7_FSM4_TB(p7_FSM4out), .e_x_MINUS_p7_FSM5_TB(p7_FSM5out), + .e_x_MINUSa(e_x_MINUSa_FSM6out), .e_x_MINUSa_p13_FSM1_TB(p13_FSM1out), .e_x_MINUSa_p13_FSM2_TB(p13_FSM2out), .e_x_MINUSa_p13_FSM3_TB(p13_FSM3out), .e_x_MINUSa_p13_FSM5_TB(p13_FSM5out), + .e_y_MINUS(e_y_MINUS_FSM6out), + .e_y_MINUSa(e_y_MINUSa_FSM6out), .e_y_MINUSa_p18_FSM1_TB(p18_FSM1out), .e_y_MINUSa_p18_FSM2_TB(p18_FSM2out), .e_y_MINUSa_p18_FSM3_TB(p18_FSM3out), .e_y_MINUSa_p18_FSM4_TB(p18_FSM4out), .e_y_MINUSa_p18_FSM5_TB(p18_FSM5out), + .e_q_MINUS(e_q_MINUS_FSM6out), .e_q_MINUS_p17_FSM1_TB(p17_FSM1out), .e_q_MINUS_p17_FSM2_TB(p17_FSM2out), .e_q_MINUS_p17_FSM3_TB(p17_FSM3out), .e_q_MINUS_p17_FSM4_TB(p17_FSM4out), .e_q_MINUS_p17_FSM5_TB(p17_FSM5out), + .p19(p19_FSM6out), + .p18(p18_FSM6out), + .p4(p4_FSM6out), + .p17(p17_FSM6out), + .p15(p15_FSM6out), + .p0(p0_FSM6out), + .p13(p13_FSM6out), + .p8(p8_FSM6out), + .p12(p12_FSM6out), + .p7(p7_FSM6out), + .p6(p6_FSM6out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/nowick_MG/msfsms_tool_bm.log b/examples/nowick_MG/msfsms_tool_bm.log new file mode 100644 index 0000000..2d6ec69 --- /dev/null +++ b/examples/nowick_MG/msfsms_tool_bm.log @@ -0,0 +1,1008 @@ +--------------------------------------------------------------------------- +Benchmark: nowick_MG/nowick.petrinet.MG.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/nowick_MG/nowick.petrinet.MG.workcraft.g +INFO: Total Nodes : 37 +INFO: Total Transitions : 16 +INFO: Total Places : 21 +INFO: Total Edges : 42 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = x_PLUS, Type = Transition (is Output) + Predecessors: p0[21][0], p2[13][0] + Successors: p4[5][0] +PT-Net [0][1]: Label = p19, Type = Place (is Marked) + Predecessors: y_MINUSa[25][0] + Successors: a_PLUS[31][0] +PT-Net [1][0]: Label = p5, Type = Place (is Empty) + Predecessors: y_PLUS[26][0] + Successors: c_PLUS[9][1] +PT-Net [3][0]: Label = q_PLUS, Type = Transition (is Output) + Predecessors: p6[34][0] + Successors: p7[30][0] +PT-Net [4][0]: Label = b_MINUS, Type = Transition (is Input) + Predecessors: p11[32][0], p12[28][0] + Successors: p13[24][0], p14[20][1] +PT-Net [4][1]: Label = p18, Type = Place (is Empty) + Predecessors: q_MINUS[35][0] + Successors: y_MINUSa[25][0] +PT-Net [5][0]: Label = p4, Type = Place (is Empty) + Predecessors: x_PLUS[0][0] + Successors: c_PLUS[9][1] +PT-Net [8][0]: Label = p17, Type = Place (is Empty) + Predecessors: a_MINUS[34][1] + Successors: q_MINUS[35][0] +PT-Net [9][0]: Label = p3, Type = Place (is Empty) + Predecessors: b_PLUS[20][0] + Successors: y_PLUS[26][0] +PT-Net [9][1]: Label = c_PLUS, Type = Transition (is Input) + Predecessors: p4[5][0], p5[1][0] + Successors: p6[34][0] +PT-Net [10][0]: Label = x_MINUS, Type = Transition (is Output) + Predecessors: p7[30][0] + Successors: p8[26][1] +PT-Net [11][0]: Label = c_MINUS, Type = Transition (is Input) + Predecessors: p8[26][1] + Successors: p10[36][0], p9[22][0] +PT-Net [12][0]: Label = p16, Type = Place (is Empty) + Predecessors: y_PLUSa[26][2] + Successors: a_MINUS[34][1] +PT-Net [13][0]: Label = p2, Type = Place (is Empty) + Predecessors: b_PLUS[20][0] + Successors: x_PLUS[0][0] +PT-Net [15][0]: Label = p20, Type = Place (is Marked) + Predecessors: y_MINUSa[25][0] + Successors: b_PLUS[20][0] +PT-Net [16][0]: Label = x_MINUSa, Type = Transition (is Output) + Predecessors: p13[24][0] + Successors: p15[16][1] +PT-Net [16][1]: Label = p15, Type = Place (is Empty) + Predecessors: x_MINUSa[16][0] + Successors: a_MINUS[34][1] +PT-Net [17][0]: Label = p1, Type = Place (is Empty) + Predecessors: a_PLUS[31][0] + Successors: y_PLUS[26][0] +PT-Net [17][1]: Label = y_MINUS, Type = Transition (is Output) + Predecessors: p10[36][0] + Successors: p12[28][0] +PT-Net [19][0]: Label = x_PLUSa, Type = Transition (is Output) + Predecessors: p9[22][0] + Successors: p11[32][0] +PT-Net [20][0]: Label = b_PLUS, Type = Transition (is Input) + Predecessors: p20[15][0] + Successors: p2[13][0], p3[9][0] +PT-Net [20][1]: Label = p14, Type = Place (is Empty) + Predecessors: b_MINUS[4][0] + Successors: y_PLUSa[26][2] +PT-Net [21][0]: Label = p0, Type = Place (is Empty) + Predecessors: a_PLUS[31][0] + Successors: x_PLUS[0][0] +PT-Net [22][0]: Label = p9, Type = Place (is Empty) + Predecessors: c_MINUS[11][0] + Successors: x_PLUSa[19][0] +PT-Net [24][0]: Label = p13, Type = Place (is Empty) + Predecessors: b_MINUS[4][0] + Successors: x_MINUSa[16][0] +PT-Net [25][0]: Label = y_MINUSa, Type = Transition (is Output) + Predecessors: p18[4][1] + Successors: p19[0][1], p20[15][0] +PT-Net [26][0]: Label = y_PLUS, Type = Transition (is Output) + Predecessors: p1[17][0], p3[9][0] + Successors: p5[1][0] +PT-Net [26][1]: Label = p8, Type = Place (is Empty) + Predecessors: x_MINUS[10][0] + Successors: c_MINUS[11][0] +PT-Net [26][2]: Label = y_PLUSa, Type = Transition (is Output) + Predecessors: p14[20][1] + Successors: p16[12][0] +PT-Net [28][0]: Label = p12, Type = Place (is Empty) + Predecessors: y_MINUS[17][1] + Successors: b_MINUS[4][0] +PT-Net [30][0]: Label = p7, Type = Place (is Empty) + Predecessors: q_PLUS[3][0] + Successors: x_MINUS[10][0] +PT-Net [31][0]: Label = a_PLUS, Type = Transition (is Input) + Predecessors: p19[0][1] + Successors: p0[21][0], p1[17][0] +PT-Net [32][0]: Label = p11, Type = Place (is Empty) + Predecessors: x_PLUSa[19][0] + Successors: b_MINUS[4][0] +PT-Net [34][0]: Label = p6, Type = Place (is Empty) + Predecessors: c_PLUS[9][1] + Successors: q_PLUS[3][0] +PT-Net [34][1]: Label = a_MINUS, Type = Transition (is Input) + Predecessors: p15[16][1], p16[12][0] + Successors: p17[8][0] +PT-Net [35][0]: Label = q_MINUS, Type = Transition (is Output) + Predecessors: p17[8][0] + Successors: p18[4][1] +PT-Net [36][0]: Label = p10, Type = Place (is Empty) + Predecessors: c_MINUS[11][0] + Successors: y_MINUS[17][1] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #6 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 24, H-collapsed = 'false' *** +SC S-net (1,1): x_PLUS[0][0] + Predecessor Place: p0(1,14)[21,0] + Successor Place: p4(1,6)[5,0] +SC S-net (1,2): p19[0][1] +SC S-net (1,3): q_PLUS[3][0] + Predecessor Place: p6(1,22)[34,0] + Successor Place: p7(1,19)[30,0] +SC S-net (1,4): b_MINUS[4][0] + Predecessor Place: p11(1,21)[32,0] + Successor Place: p13(1,16)[24,0] +SC S-net (1,5): p18[4][1] +SC S-net (1,6): p4[5][0] +SC S-net (1,7): p17[8][0] +SC S-net (1,8): c_PLUS[9][1] + Predecessor Place: p4(1,6)[5,0] + Successor Place: p6(1,22)[34,0] +SC S-net (1,9): x_MINUS[10][0] + Predecessor Place: p7(1,19)[30,0] + Successor Place: p8(1,18)[26,1] +SC S-net (1,10): c_MINUS[11][0] + Predecessor Place: p8(1,18)[26,1] + Successor Place: p9(1,15)[22,0] +SC S-net (1,11): x_MINUSa[16][0] + Predecessor Place: p13(1,16)[24,0] + Successor Place: p15(1,12)[16,1] +SC S-net (1,12): p15[16][1] +SC S-net (1,13): x_PLUSa[19][0] + Predecessor Place: p9(1,15)[22,0] + Successor Place: p11(1,21)[32,0] +SC S-net (1,14): p0[21][0] +SC S-net (1,15): p9[22][0] +SC S-net (1,16): p13[24][0] +SC S-net (1,17): y_MINUSa[25][0] + Predecessor Place: p18(1,5)[4,1] + Successor Place: p19(1,2)[0,1] +SC S-net (1,18): p8[26][1] +SC S-net (1,19): p7[30][0] +SC S-net (1,20): a_PLUS[31][0] + Predecessor Place: p19(1,2)[0,1] + Successor Place: p0(1,14)[21,0] +SC S-net (1,21): p11[32][0] +SC S-net (1,22): p6[34][0] +SC S-net (1,23): a_MINUS[34][1] + Predecessor Place: p15(1,12)[16,1] + Successor Place: p17(1,7)[8,0] +SC S-net (1,24): q_MINUS[35][0] + Predecessor Place: p17(1,7)[8,0] + Successor Place: p18(1,5)[4,1] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 24, H-collapsed = 'false' *** +SC S-net (2,1): p19[0][1] +SC S-net (2,2): p5[1][0] +SC S-net (2,3): q_PLUS[3][0] + Predecessor Place: p6(2,22)[34,0] + Successor Place: p7(2,19)[30,0] +SC S-net (2,4): b_MINUS[4][0] + Predecessor Place: p11(2,21)[32,0] + Successor Place: p13(2,15)[24,0] +SC S-net (2,5): p18[4][1] +SC S-net (2,6): p17[8][0] +SC S-net (2,7): c_PLUS[9][1] + Predecessor Place: p5(2,2)[1,0] + Successor Place: p6(2,22)[34,0] +SC S-net (2,8): x_MINUS[10][0] + Predecessor Place: p7(2,19)[30,0] + Successor Place: p8(2,18)[26,1] +SC S-net (2,9): c_MINUS[11][0] + Predecessor Place: p8(2,18)[26,1] + Successor Place: p9(2,14)[22,0] +SC S-net (2,10): x_MINUSa[16][0] + Predecessor Place: p13(2,15)[24,0] + Successor Place: p15(2,11)[16,1] +SC S-net (2,11): p15[16][1] +SC S-net (2,12): p1[17][0] +SC S-net (2,13): x_PLUSa[19][0] + Predecessor Place: p9(2,14)[22,0] + Successor Place: p11(2,21)[32,0] +SC S-net (2,14): p9[22][0] +SC S-net (2,15): p13[24][0] +SC S-net (2,16): y_MINUSa[25][0] + Predecessor Place: p18(2,5)[4,1] + Successor Place: p19(2,1)[0,1] +SC S-net (2,17): y_PLUS[26][0] + Predecessor Place: p1(2,12)[17,0] + Successor Place: p5(2,2)[1,0] +SC S-net (2,18): p8[26][1] +SC S-net (2,19): p7[30][0] +SC S-net (2,20): a_PLUS[31][0] + Predecessor Place: p19(2,1)[0,1] + Successor Place: p1(2,12)[17,0] +SC S-net (2,21): p11[32][0] +SC S-net (2,22): p6[34][0] +SC S-net (2,23): a_MINUS[34][1] + Predecessor Place: p15(2,11)[16,1] + Successor Place: p17(2,6)[8,0] +SC S-net (2,24): q_MINUS[35][0] + Predecessor Place: p17(2,6)[8,0] + Successor Place: p18(2,5)[4,1] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #3, Total Nodes = 24, H-collapsed = 'false' *** +SC S-net (3,1): p5[1][0] +SC S-net (3,2): q_PLUS[3][0] + Predecessor Place: p6(3,22)[34,0] + Successor Place: p7(3,20)[30,0] +SC S-net (3,3): b_MINUS[4][0] + Predecessor Place: p11(3,21)[32,0] + Successor Place: p13(3,16)[24,0] +SC S-net (3,4): p18[4][1] +SC S-net (3,5): p17[8][0] +SC S-net (3,6): p3[9][0] +SC S-net (3,7): c_PLUS[9][1] + Predecessor Place: p5(3,1)[1,0] + Successor Place: p6(3,22)[34,0] +SC S-net (3,8): x_MINUS[10][0] + Predecessor Place: p7(3,20)[30,0] + Successor Place: p8(3,19)[26,1] +SC S-net (3,9): c_MINUS[11][0] + Predecessor Place: p8(3,19)[26,1] + Successor Place: p9(3,15)[22,0] +SC S-net (3,10): p20[15][0] +SC S-net (3,11): x_MINUSa[16][0] + Predecessor Place: p13(3,16)[24,0] + Successor Place: p15(3,12)[16,1] +SC S-net (3,12): p15[16][1] +SC S-net (3,13): x_PLUSa[19][0] + Predecessor Place: p9(3,15)[22,0] + Successor Place: p11(3,21)[32,0] +SC S-net (3,14): b_PLUS[20][0] + Predecessor Place: p20(3,10)[15,0] + Successor Place: p3(3,6)[9,0] +SC S-net (3,15): p9[22][0] +SC S-net (3,16): p13[24][0] +SC S-net (3,17): y_MINUSa[25][0] + Predecessor Place: p18(3,4)[4,1] + Successor Place: p20(3,10)[15,0] +SC S-net (3,18): y_PLUS[26][0] + Predecessor Place: p3(3,6)[9,0] + Successor Place: p5(3,1)[1,0] +SC S-net (3,19): p8[26][1] +SC S-net (3,20): p7[30][0] +SC S-net (3,21): p11[32][0] +SC S-net (3,22): p6[34][0] +SC S-net (3,23): a_MINUS[34][1] + Predecessor Place: p15(3,12)[16,1] + Successor Place: p17(3,5)[8,0] +SC S-net (3,24): q_MINUS[35][0] + Predecessor Place: p17(3,5)[8,0] + Successor Place: p18(3,4)[4,1] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #4, Total Nodes = 24, H-collapsed = 'false' *** +SC S-net (4,1): x_PLUS[0][0] + Predecessor Place: p0(4,14)[21,0] + Successor Place: p4(4,6)[5,0] +SC S-net (4,2): p19[0][1] +SC S-net (4,3): q_PLUS[3][0] + Predecessor Place: p6(4,22)[34,0] + Successor Place: p7(4,19)[30,0] +SC S-net (4,4): b_MINUS[4][0] + Predecessor Place: p11(4,21)[32,0] + Successor Place: p14(4,13)[20,1] +SC S-net (4,5): p18[4][1] +SC S-net (4,6): p4[5][0] +SC S-net (4,7): p17[8][0] +SC S-net (4,8): c_PLUS[9][1] + Predecessor Place: p4(4,6)[5,0] + Successor Place: p6(4,22)[34,0] +SC S-net (4,9): x_MINUS[10][0] + Predecessor Place: p7(4,19)[30,0] + Successor Place: p8(4,17)[26,1] +SC S-net (4,10): c_MINUS[11][0] + Predecessor Place: p8(4,17)[26,1] + Successor Place: p9(4,15)[22,0] +SC S-net (4,11): p16[12][0] +SC S-net (4,12): x_PLUSa[19][0] + Predecessor Place: p9(4,15)[22,0] + Successor Place: p11(4,21)[32,0] +SC S-net (4,13): p14[20][1] +SC S-net (4,14): p0[21][0] +SC S-net (4,15): p9[22][0] +SC S-net (4,16): y_MINUSa[25][0] + Predecessor Place: p18(4,5)[4,1] + Successor Place: p19(4,2)[0,1] +SC S-net (4,17): p8[26][1] +SC S-net (4,18): y_PLUSa[26][2] + Predecessor Place: p14(4,13)[20,1] + Successor Place: p16(4,11)[12,0] +SC S-net (4,19): p7[30][0] +SC S-net (4,20): a_PLUS[31][0] + Predecessor Place: p19(4,2)[0,1] + Successor Place: p0(4,14)[21,0] +SC S-net (4,21): p11[32][0] +SC S-net (4,22): p6[34][0] +SC S-net (4,23): a_MINUS[34][1] + Predecessor Place: p16(4,11)[12,0] + Successor Place: p17(4,7)[8,0] +SC S-net (4,24): q_MINUS[35][0] + Predecessor Place: p17(4,7)[8,0] + Successor Place: p18(4,5)[4,1] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #5, Total Nodes = 24, H-collapsed = 'false' *** +SC S-net (5,1): x_PLUS[0][0] + Predecessor Place: p2(5,10)[13,0] + Successor Place: p4(5,5)[5,0] +SC S-net (5,2): q_PLUS[3][0] + Predecessor Place: p6(5,22)[34,0] + Successor Place: p7(5,20)[30,0] +SC S-net (5,3): b_MINUS[4][0] + Predecessor Place: p11(5,21)[32,0] + Successor Place: p13(5,17)[24,0] +SC S-net (5,4): p18[4][1] +SC S-net (5,5): p4[5][0] +SC S-net (5,6): p17[8][0] +SC S-net (5,7): c_PLUS[9][1] + Predecessor Place: p4(5,5)[5,0] + Successor Place: p6(5,22)[34,0] +SC S-net (5,8): x_MINUS[10][0] + Predecessor Place: p7(5,20)[30,0] + Successor Place: p8(5,19)[26,1] +SC S-net (5,9): c_MINUS[11][0] + Predecessor Place: p8(5,19)[26,1] + Successor Place: p9(5,16)[22,0] +SC S-net (5,10): p2[13][0] +SC S-net (5,11): p20[15][0] +SC S-net (5,12): x_MINUSa[16][0] + Predecessor Place: p13(5,17)[24,0] + Successor Place: p15(5,13)[16,1] +SC S-net (5,13): p15[16][1] +SC S-net (5,14): x_PLUSa[19][0] + Predecessor Place: p9(5,16)[22,0] + Successor Place: p11(5,21)[32,0] +SC S-net (5,15): b_PLUS[20][0] + Predecessor Place: p20(5,11)[15,0] + Successor Place: p2(5,10)[13,0] +SC S-net (5,16): p9[22][0] +SC S-net (5,17): p13[24][0] +SC S-net (5,18): y_MINUSa[25][0] + Predecessor Place: p18(5,4)[4,1] + Successor Place: p20(5,11)[15,0] +SC S-net (5,19): p8[26][1] +SC S-net (5,20): p7[30][0] +SC S-net (5,21): p11[32][0] +SC S-net (5,22): p6[34][0] +SC S-net (5,23): a_MINUS[34][1] + Predecessor Place: p15(5,13)[16,1] + Successor Place: p17(5,6)[8,0] +SC S-net (5,24): q_MINUS[35][0] + Predecessor Place: p17(5,6)[8,0] + Successor Place: p18(5,4)[4,1] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #6, Total Nodes = 24, H-collapsed = 'false' *** +SC S-net (6,1): x_PLUS[0][0] + Predecessor Place: p0(6,14)[21,0] + Successor Place: p4(6,6)[5,0] +SC S-net (6,2): p19[0][1] +SC S-net (6,3): q_PLUS[3][0] + Predecessor Place: p6(6,21)[34,0] + Successor Place: p7(6,19)[30,0] +SC S-net (6,4): b_MINUS[4][0] + Predecessor Place: p12(6,18)[28,0] + Successor Place: p13(6,15)[24,0] +SC S-net (6,5): p18[4][1] +SC S-net (6,6): p4[5][0] +SC S-net (6,7): p17[8][0] +SC S-net (6,8): c_PLUS[9][1] + Predecessor Place: p4(6,6)[5,0] + Successor Place: p6(6,21)[34,0] +SC S-net (6,9): x_MINUS[10][0] + Predecessor Place: p7(6,19)[30,0] + Successor Place: p8(6,17)[26,1] +SC S-net (6,10): c_MINUS[11][0] + Predecessor Place: p8(6,17)[26,1] + Successor Place: p10(6,24)[36,0] +SC S-net (6,11): x_MINUSa[16][0] + Predecessor Place: p13(6,15)[24,0] + Successor Place: p15(6,12)[16,1] +SC S-net (6,12): p15[16][1] +SC S-net (6,13): y_MINUS[17][1] + Predecessor Place: p10(6,24)[36,0] + Successor Place: p12(6,18)[28,0] +SC S-net (6,14): p0[21][0] +SC S-net (6,15): p13[24][0] +SC S-net (6,16): y_MINUSa[25][0] + Predecessor Place: p18(6,5)[4,1] + Successor Place: p19(6,2)[0,1] +SC S-net (6,17): p8[26][1] +SC S-net (6,18): p12[28][0] +SC S-net (6,19): p7[30][0] +SC S-net (6,20): a_PLUS[31][0] + Predecessor Place: p19(6,2)[0,1] + Successor Place: p0(6,14)[21,0] +SC S-net (6,21): p6[34][0] +SC S-net (6,22): a_MINUS[34][1] + Predecessor Place: p15(6,12)[16,1] + Successor Place: p17(6,7)[8,0] +SC S-net (6,23): q_MINUS[35][0] + Predecessor Place: p17(6,7)[8,0] + Successor Place: p18(6,5)[4,1] +SC S-net (6,24): p10[36][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #6 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #6 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #3 (of #6 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #4 (of #6 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #5 (of #6 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #6 (of #6 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#2 ***, identical to #1 +Matching Pairs: +Index 0: Matching pairs (4, 4) +Index 1: Matching pairs (11, 10) +Index 2: Matching pairs (23, 23) +Index 3: Matching pairs (24, 24) +Index 4: Matching pairs (17, 16) +Index 5: Matching pairs (20, 20) +Index 6: Matching pairs (1, 17) +Index 7: Matching pairs (8, 7) +Index 8: Matching pairs (3, 3) +Index 9: Matching pairs (9, 8) +Index 10: Matching pairs (10, 9) +Index 11: Matching pairs (13, 13) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#4 ***, identical to #1 +Matching Pairs: +Index 0: Matching pairs (4, 4) +Index 1: Matching pairs (11, 18) +Index 2: Matching pairs (23, 23) +Index 3: Matching pairs (24, 24) +Index 4: Matching pairs (17, 16) +Index 5: Matching pairs (20, 20) +Index 6: Matching pairs (1, 1) +Index 7: Matching pairs (8, 8) +Index 8: Matching pairs (3, 3) +Index 9: Matching pairs (9, 9) +Index 10: Matching pairs (10, 10) +Index 11: Matching pairs (13, 12) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#6 ***, identical to #1 +Matching Pairs: +Index 0: Matching pairs (4, 4) +Index 1: Matching pairs (11, 11) +Index 2: Matching pairs (23, 22) +Index 3: Matching pairs (24, 23) +Index 4: Matching pairs (17, 16) +Index 5: Matching pairs (20, 20) +Index 6: Matching pairs (1, 1) +Index 7: Matching pairs (8, 8) +Index 8: Matching pairs (3, 3) +Index 9: Matching pairs (9, 9) +Index 10: Matching pairs (10, 10) +Index 11: Matching pairs (13, 13) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#4 ***, identical to #2 +Matching Pairs: +Index 0: Matching pairs (4, 4) +Index 1: Matching pairs (10, 18) +Index 2: Matching pairs (23, 23) +Index 3: Matching pairs (24, 24) +Index 4: Matching pairs (16, 16) +Index 5: Matching pairs (20, 20) +Index 6: Matching pairs (17, 1) +Index 7: Matching pairs (7, 8) +Index 8: Matching pairs (3, 3) +Index 9: Matching pairs (8, 9) +Index 10: Matching pairs (9, 10) +Index 11: Matching pairs (13, 12) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#6 ***, identical to #2 +Matching Pairs: +Index 0: Matching pairs (4, 4) +Index 1: Matching pairs (10, 11) +Index 2: Matching pairs (23, 22) +Index 3: Matching pairs (24, 23) +Index 4: Matching pairs (16, 16) +Index 5: Matching pairs (20, 20) +Index 6: Matching pairs (17, 1) +Index 7: Matching pairs (7, 8) +Index 8: Matching pairs (3, 3) +Index 9: Matching pairs (8, 9) +Index 10: Matching pairs (9, 10) +Index 11: Matching pairs (13, 13) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#5 ***, identical to #3 +Matching Pairs: +Index 0: Matching pairs (3, 3) +Index 1: Matching pairs (11, 12) +Index 2: Matching pairs (23, 23) +Index 3: Matching pairs (24, 24) +Index 4: Matching pairs (17, 18) +Index 5: Matching pairs (14, 15) +Index 6: Matching pairs (18, 1) +Index 7: Matching pairs (7, 7) +Index 8: Matching pairs (2, 2) +Index 9: Matching pairs (8, 8) +Index 10: Matching pairs (9, 9) +Index 11: Matching pairs (13, 14) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#6 ***, identical to #4 +Matching Pairs: +Index 0: Matching pairs (4, 4) +Index 1: Matching pairs (18, 11) +Index 2: Matching pairs (23, 22) +Index 3: Matching pairs (24, 23) +Index 4: Matching pairs (16, 16) +Index 5: Matching pairs (20, 20) +Index 6: Matching pairs (1, 1) +Index 7: Matching pairs (8, 8) +Index 8: Matching pairs (3, 3) +Index 9: Matching pairs (9, 9) +Index 10: Matching pairs (10, 10) +Index 11: Matching pairs (12, 13) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 24, H-Collapsed = 'false' *** +FSM (1,1): Label = e/x_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(0,6) + Predecessor(s): p0(0,14) +FSM (1,2): Label = p19, Type = State (is Initially Active) + Successor(s): a_PLUS/(0,20) + Predecessor(s): e/y_MINUSa(0,17) +FSM (1,3): Label = e/q_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(0,19) + Predecessor(s): p6(0,22) +FSM (1,4): Label = b_MINUS/, Type = Trans. Function (is Input) + Successor(s): p13(0,16) + Predecessor(s): p11(0,21) +FSM (1,5): Label = p18, Type = State (is Initially Inactive) + Successor(s): e/y_MINUSa(0,17) + Predecessor(s): e/q_MINUS(0,24) +FSM (1,6): Label = p4, Type = State (is Initially Inactive) + Successor(s): c_PLUS/(0,8) + Predecessor(s): e/x_PLUS(0,1) +FSM (1,7): Label = p17, Type = State (is Initially Inactive) + Successor(s): e/q_MINUS(0,24) + Predecessor(s): a_MINUS/(0,23) +FSM (1,8): Label = c_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(0,22) + Predecessor(s): p4(0,6) +FSM (1,9): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p8(0,18) + Predecessor(s): p7(0,19) +FSM (1,10): Label = c_MINUS/, Type = Trans. Function (is Input) + Successor(s): p9(0,15) + Predecessor(s): p8(0,18) +FSM (1,11): Label = e/x_MINUSa, Type = Trans. Function (is Output) + Successor(s): p15(0,12) + Predecessor(s): p13(0,16) +FSM (1,12): Label = p15, Type = State (is Initially Inactive) + Successor(s): a_MINUS/(0,23) + Predecessor(s): e/x_MINUSa(0,11) +FSM (1,13): Label = e/x_PLUSa, Type = Trans. Function (is Output) + Successor(s): p11(0,21) + Predecessor(s): p9(0,15) +FSM (1,14): Label = p0, Type = State (is Initially Inactive) + Successor(s): e/x_PLUS(0,1) + Predecessor(s): a_PLUS/(0,20) +FSM (1,15): Label = p9, Type = State (is Initially Inactive) + Successor(s): e/x_PLUSa(0,13) + Predecessor(s): c_MINUS/(0,10) +FSM (1,16): Label = p13, Type = State (is Initially Inactive) + Successor(s): e/x_MINUSa(0,11) + Predecessor(s): b_MINUS/(0,4) +FSM (1,17): Label = e/y_MINUSa, Type = Trans. Function (is Output) + Successor(s): p19(0,2) + Predecessor(s): p18(0,5) +FSM (1,18): Label = p8, Type = State (is Initially Inactive) + Successor(s): c_MINUS/(0,10) + Predecessor(s): e/x_MINUS(0,9) +FSM (1,19): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(0,9) + Predecessor(s): e/q_PLUS(0,3) +FSM (1,20): Label = a_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(0,14) + Predecessor(s): p19(0,2) +FSM (1,21): Label = p11, Type = State (is Initially Inactive) + Successor(s): b_MINUS/(0,4) + Predecessor(s): e/x_PLUSa(0,13) +FSM (1,22): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/q_PLUS(0,3) + Predecessor(s): c_PLUS/(0,8) +FSM (1,23): Label = a_MINUS/, Type = Trans. Function (is Input) + Successor(s): p17(0,7) + Predecessor(s): p15(0,12) +FSM (1,24): Label = e/q_MINUS, Type = Trans. Function (is Output) + Successor(s): p18(0,5) + Predecessor(s): p17(0,7) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 24, H-Collapsed = 'false' *** +FSM (2,1): Label = p19, Type = State (is Initially Active) + Successor(s): a_PLUS/(1,20) + Predecessor(s): e/y_MINUSa(1,16) +FSM (2,2): Label = p5, Type = State (is Initially Inactive) + Successor(s): c_PLUS/(1,7) + Predecessor(s): e/y_PLUS(1,17) +FSM (2,3): Label = e/q_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(1,19) + Predecessor(s): p6(1,22) +FSM (2,4): Label = b_MINUS/, Type = Trans. Function (is Input) + Successor(s): p13(1,15) + Predecessor(s): p11(1,21) +FSM (2,5): Label = p18, Type = State (is Initially Inactive) + Successor(s): e/y_MINUSa(1,16) + Predecessor(s): e/q_MINUS(1,24) +FSM (2,6): Label = p17, Type = State (is Initially Inactive) + Successor(s): e/q_MINUS(1,24) + Predecessor(s): a_MINUS/(1,23) +FSM (2,7): Label = c_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(1,22) + Predecessor(s): p5(1,2) +FSM (2,8): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p8(1,18) + Predecessor(s): p7(1,19) +FSM (2,9): Label = c_MINUS/, Type = Trans. Function (is Input) + Successor(s): p9(1,14) + Predecessor(s): p8(1,18) +FSM (2,10): Label = e/x_MINUSa, Type = Trans. Function (is Output) + Successor(s): p15(1,11) + Predecessor(s): p13(1,15) +FSM (2,11): Label = p15, Type = State (is Initially Inactive) + Successor(s): a_MINUS/(1,23) + Predecessor(s): e/x_MINUSa(1,10) +FSM (2,12): Label = p1, Type = State (is Initially Inactive) + Successor(s): e/y_PLUS(1,17) + Predecessor(s): a_PLUS/(1,20) +FSM (2,13): Label = e/x_PLUSa, Type = Trans. Function (is Output) + Successor(s): p11(1,21) + Predecessor(s): p9(1,14) +FSM (2,14): Label = p9, Type = State (is Initially Inactive) + Successor(s): e/x_PLUSa(1,13) + Predecessor(s): c_MINUS/(1,9) +FSM (2,15): Label = p13, Type = State (is Initially Inactive) + Successor(s): e/x_MINUSa(1,10) + Predecessor(s): b_MINUS/(1,4) +FSM (2,16): Label = e/y_MINUSa, Type = Trans. Function (is Output) + Successor(s): p19(1,1) + Predecessor(s): p18(1,5) +FSM (2,17): Label = e/y_PLUS, Type = Trans. Function (is Output) + Successor(s): p5(1,2) + Predecessor(s): p1(1,12) +FSM (2,18): Label = p8, Type = State (is Initially Inactive) + Successor(s): c_MINUS/(1,9) + Predecessor(s): e/x_MINUS(1,8) +FSM (2,19): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(1,8) + Predecessor(s): e/q_PLUS(1,3) +FSM (2,20): Label = a_PLUS/, Type = Trans. Function (is Input) + Successor(s): p1(1,12) + Predecessor(s): p19(1,1) +FSM (2,21): Label = p11, Type = State (is Initially Inactive) + Successor(s): b_MINUS/(1,4) + Predecessor(s): e/x_PLUSa(1,13) +FSM (2,22): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/q_PLUS(1,3) + Predecessor(s): c_PLUS/(1,7) +FSM (2,23): Label = a_MINUS/, Type = Trans. Function (is Input) + Successor(s): p17(1,6) + Predecessor(s): p15(1,11) +FSM (2,24): Label = e/q_MINUS, Type = Trans. Function (is Output) + Successor(s): p18(1,5) + Predecessor(s): p17(1,6) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 3, Total list Entries = 24, H-Collapsed = 'false' *** +FSM (3,1): Label = p5, Type = State (is Initially Inactive) + Successor(s): c_PLUS/(2,7) + Predecessor(s): e/y_PLUS(2,18) +FSM (3,2): Label = e/q_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(2,20) + Predecessor(s): p6(2,22) +FSM (3,3): Label = b_MINUS/, Type = Trans. Function (is Input) + Successor(s): p13(2,16) + Predecessor(s): p11(2,21) +FSM (3,4): Label = p18, Type = State (is Initially Inactive) + Successor(s): e/y_MINUSa(2,17) + Predecessor(s): e/q_MINUS(2,24) +FSM (3,5): Label = p17, Type = State (is Initially Inactive) + Successor(s): e/q_MINUS(2,24) + Predecessor(s): a_MINUS/(2,23) +FSM (3,6): Label = p3, Type = State (is Initially Inactive) + Successor(s): e/y_PLUS(2,18) + Predecessor(s): b_PLUS/(2,14) +FSM (3,7): Label = c_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(2,22) + Predecessor(s): p5(2,1) +FSM (3,8): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p8(2,19) + Predecessor(s): p7(2,20) +FSM (3,9): Label = c_MINUS/, Type = Trans. Function (is Input) + Successor(s): p9(2,15) + Predecessor(s): p8(2,19) +FSM (3,10): Label = p20, Type = State (is Initially Active) + Successor(s): b_PLUS/(2,14) + Predecessor(s): e/y_MINUSa(2,17) +FSM (3,11): Label = e/x_MINUSa, Type = Trans. Function (is Output) + Successor(s): p15(2,12) + Predecessor(s): p13(2,16) +FSM (3,12): Label = p15, Type = State (is Initially Inactive) + Successor(s): a_MINUS/(2,23) + Predecessor(s): e/x_MINUSa(2,11) +FSM (3,13): Label = e/x_PLUSa, Type = Trans. Function (is Output) + Successor(s): p11(2,21) + Predecessor(s): p9(2,15) +FSM (3,14): Label = b_PLUS/, Type = Trans. Function (is Input) + Successor(s): p3(2,6) + Predecessor(s): p20(2,10) +FSM (3,15): Label = p9, Type = State (is Initially Inactive) + Successor(s): e/x_PLUSa(2,13) + Predecessor(s): c_MINUS/(2,9) +FSM (3,16): Label = p13, Type = State (is Initially Inactive) + Successor(s): e/x_MINUSa(2,11) + Predecessor(s): b_MINUS/(2,3) +FSM (3,17): Label = e/y_MINUSa, Type = Trans. Function (is Output) + Successor(s): p20(2,10) + Predecessor(s): p18(2,4) +FSM (3,18): Label = e/y_PLUS, Type = Trans. Function (is Output) + Successor(s): p5(2,1) + Predecessor(s): p3(2,6) +FSM (3,19): Label = p8, Type = State (is Initially Inactive) + Successor(s): c_MINUS/(2,9) + Predecessor(s): e/x_MINUS(2,8) +FSM (3,20): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(2,8) + Predecessor(s): e/q_PLUS(2,2) +FSM (3,21): Label = p11, Type = State (is Initially Inactive) + Successor(s): b_MINUS/(2,3) + Predecessor(s): e/x_PLUSa(2,13) +FSM (3,22): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/q_PLUS(2,2) + Predecessor(s): c_PLUS/(2,7) +FSM (3,23): Label = a_MINUS/, Type = Trans. Function (is Input) + Successor(s): p17(2,5) + Predecessor(s): p15(2,12) +FSM (3,24): Label = e/q_MINUS, Type = Trans. Function (is Output) + Successor(s): p18(2,4) + Predecessor(s): p17(2,5) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 4, Total list Entries = 24, H-Collapsed = 'false' *** +FSM (4,1): Label = e/x_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(3,6) + Predecessor(s): p0(3,14) +FSM (4,2): Label = p19, Type = State (is Initially Active) + Successor(s): a_PLUS/(3,20) + Predecessor(s): e/y_MINUSa(3,16) +FSM (4,3): Label = e/q_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(3,19) + Predecessor(s): p6(3,22) +FSM (4,4): Label = b_MINUS/, Type = Trans. Function (is Input) + Successor(s): p14(3,13) + Predecessor(s): p11(3,21) +FSM (4,5): Label = p18, Type = State (is Initially Inactive) + Successor(s): e/y_MINUSa(3,16) + Predecessor(s): e/q_MINUS(3,24) +FSM (4,6): Label = p4, Type = State (is Initially Inactive) + Successor(s): c_PLUS/(3,8) + Predecessor(s): e/x_PLUS(3,1) +FSM (4,7): Label = p17, Type = State (is Initially Inactive) + Successor(s): e/q_MINUS(3,24) + Predecessor(s): a_MINUS/(3,23) +FSM (4,8): Label = c_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(3,22) + Predecessor(s): p4(3,6) +FSM (4,9): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p8(3,17) + Predecessor(s): p7(3,19) +FSM (4,10): Label = c_MINUS/, Type = Trans. Function (is Input) + Successor(s): p9(3,15) + Predecessor(s): p8(3,17) +FSM (4,11): Label = p16, Type = State (is Initially Inactive) + Successor(s): a_MINUS/(3,23) + Predecessor(s): e/y_PLUSa(3,18) +FSM (4,12): Label = e/x_PLUSa, Type = Trans. Function (is Output) + Successor(s): p11(3,21) + Predecessor(s): p9(3,15) +FSM (4,13): Label = p14, Type = State (is Initially Inactive) + Successor(s): e/y_PLUSa(3,18) + Predecessor(s): b_MINUS/(3,4) +FSM (4,14): Label = p0, Type = State (is Initially Inactive) + Successor(s): e/x_PLUS(3,1) + Predecessor(s): a_PLUS/(3,20) +FSM (4,15): Label = p9, Type = State (is Initially Inactive) + Successor(s): e/x_PLUSa(3,12) + Predecessor(s): c_MINUS/(3,10) +FSM (4,16): Label = e/y_MINUSa, Type = Trans. Function (is Output) + Successor(s): p19(3,2) + Predecessor(s): p18(3,5) +FSM (4,17): Label = p8, Type = State (is Initially Inactive) + Successor(s): c_MINUS/(3,10) + Predecessor(s): e/x_MINUS(3,9) +FSM (4,18): Label = e/y_PLUSa, Type = Trans. Function (is Output) + Successor(s): p16(3,11) + Predecessor(s): p14(3,13) +FSM (4,19): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(3,9) + Predecessor(s): e/q_PLUS(3,3) +FSM (4,20): Label = a_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(3,14) + Predecessor(s): p19(3,2) +FSM (4,21): Label = p11, Type = State (is Initially Inactive) + Successor(s): b_MINUS/(3,4) + Predecessor(s): e/x_PLUSa(3,12) +FSM (4,22): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/q_PLUS(3,3) + Predecessor(s): c_PLUS/(3,8) +FSM (4,23): Label = a_MINUS/, Type = Trans. Function (is Input) + Successor(s): p17(3,7) + Predecessor(s): p16(3,11) +FSM (4,24): Label = e/q_MINUS, Type = Trans. Function (is Output) + Successor(s): p18(3,5) + Predecessor(s): p17(3,7) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 5, Total list Entries = 24, H-Collapsed = 'false' *** +FSM (5,1): Label = e/x_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(4,5) + Predecessor(s): p2(4,10) +FSM (5,2): Label = e/q_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(4,20) + Predecessor(s): p6(4,22) +FSM (5,3): Label = b_MINUS/, Type = Trans. Function (is Input) + Successor(s): p13(4,17) + Predecessor(s): p11(4,21) +FSM (5,4): Label = p18, Type = State (is Initially Inactive) + Successor(s): e/y_MINUSa(4,18) + Predecessor(s): e/q_MINUS(4,24) +FSM (5,5): Label = p4, Type = State (is Initially Inactive) + Successor(s): c_PLUS/(4,7) + Predecessor(s): e/x_PLUS(4,1) +FSM (5,6): Label = p17, Type = State (is Initially Inactive) + Successor(s): e/q_MINUS(4,24) + Predecessor(s): a_MINUS/(4,23) +FSM (5,7): Label = c_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(4,22) + Predecessor(s): p4(4,5) +FSM (5,8): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p8(4,19) + Predecessor(s): p7(4,20) +FSM (5,9): Label = c_MINUS/, Type = Trans. Function (is Input) + Successor(s): p9(4,16) + Predecessor(s): p8(4,19) +FSM (5,10): Label = p2, Type = State (is Initially Inactive) + Successor(s): e/x_PLUS(4,1) + Predecessor(s): b_PLUS/(4,15) +FSM (5,11): Label = p20, Type = State (is Initially Active) + Successor(s): b_PLUS/(4,15) + Predecessor(s): e/y_MINUSa(4,18) +FSM (5,12): Label = e/x_MINUSa, Type = Trans. Function (is Output) + Successor(s): p15(4,13) + Predecessor(s): p13(4,17) +FSM (5,13): Label = p15, Type = State (is Initially Inactive) + Successor(s): a_MINUS/(4,23) + Predecessor(s): e/x_MINUSa(4,12) +FSM (5,14): Label = e/x_PLUSa, Type = Trans. Function (is Output) + Successor(s): p11(4,21) + Predecessor(s): p9(4,16) +FSM (5,15): Label = b_PLUS/, Type = Trans. Function (is Input) + Successor(s): p2(4,10) + Predecessor(s): p20(4,11) +FSM (5,16): Label = p9, Type = State (is Initially Inactive) + Successor(s): e/x_PLUSa(4,14) + Predecessor(s): c_MINUS/(4,9) +FSM (5,17): Label = p13, Type = State (is Initially Inactive) + Successor(s): e/x_MINUSa(4,12) + Predecessor(s): b_MINUS/(4,3) +FSM (5,18): Label = e/y_MINUSa, Type = Trans. Function (is Output) + Successor(s): p20(4,11) + Predecessor(s): p18(4,4) +FSM (5,19): Label = p8, Type = State (is Initially Inactive) + Successor(s): c_MINUS/(4,9) + Predecessor(s): e/x_MINUS(4,8) +FSM (5,20): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(4,8) + Predecessor(s): e/q_PLUS(4,2) +FSM (5,21): Label = p11, Type = State (is Initially Inactive) + Successor(s): b_MINUS/(4,3) + Predecessor(s): e/x_PLUSa(4,14) +FSM (5,22): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/q_PLUS(4,2) + Predecessor(s): c_PLUS/(4,7) +FSM (5,23): Label = a_MINUS/, Type = Trans. Function (is Input) + Successor(s): p17(4,6) + Predecessor(s): p15(4,13) +FSM (5,24): Label = e/q_MINUS, Type = Trans. Function (is Output) + Successor(s): p18(4,4) + Predecessor(s): p17(4,6) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 6, Total list Entries = 24, H-Collapsed = 'false' *** +FSM (6,1): Label = e/x_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(5,6) + Predecessor(s): p0(5,14) +FSM (6,2): Label = p19, Type = State (is Initially Active) + Successor(s): a_PLUS/(5,20) + Predecessor(s): e/y_MINUSa(5,16) +FSM (6,3): Label = e/q_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(5,19) + Predecessor(s): p6(5,21) +FSM (6,4): Label = b_MINUS/, Type = Trans. Function (is Input) + Successor(s): p13(5,15) + Predecessor(s): p12(5,18) +FSM (6,5): Label = p18, Type = State (is Initially Inactive) + Successor(s): e/y_MINUSa(5,16) + Predecessor(s): e/q_MINUS(5,23) +FSM (6,6): Label = p4, Type = State (is Initially Inactive) + Successor(s): c_PLUS/(5,8) + Predecessor(s): e/x_PLUS(5,1) +FSM (6,7): Label = p17, Type = State (is Initially Inactive) + Successor(s): e/q_MINUS(5,23) + Predecessor(s): a_MINUS/(5,22) +FSM (6,8): Label = c_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(5,21) + Predecessor(s): p4(5,6) +FSM (6,9): Label = e/x_MINUS, Type = Trans. Function (is Output) + Successor(s): p8(5,17) + Predecessor(s): p7(5,19) +FSM (6,10): Label = c_MINUS/, Type = Trans. Function (is Input) + Successor(s): p10(5,24) + Predecessor(s): p8(5,17) +FSM (6,11): Label = e/x_MINUSa, Type = Trans. Function (is Output) + Successor(s): p15(5,12) + Predecessor(s): p13(5,15) +FSM (6,12): Label = p15, Type = State (is Initially Inactive) + Successor(s): a_MINUS/(5,22) + Predecessor(s): e/x_MINUSa(5,11) +FSM (6,13): Label = e/y_MINUS, Type = Trans. Function (is Output) + Successor(s): p12(5,18) + Predecessor(s): p10(5,24) +FSM (6,14): Label = p0, Type = State (is Initially Inactive) + Successor(s): e/x_PLUS(5,1) + Predecessor(s): a_PLUS/(5,20) +FSM (6,15): Label = p13, Type = State (is Initially Inactive) + Successor(s): e/x_MINUSa(5,11) + Predecessor(s): b_MINUS/(5,4) +FSM (6,16): Label = e/y_MINUSa, Type = Trans. Function (is Output) + Successor(s): p19(5,2) + Predecessor(s): p18(5,5) +FSM (6,17): Label = p8, Type = State (is Initially Inactive) + Successor(s): c_MINUS/(5,10) + Predecessor(s): e/x_MINUS(5,9) +FSM (6,18): Label = p12, Type = State (is Initially Inactive) + Successor(s): b_MINUS/(5,4) + Predecessor(s): e/y_MINUS(5,13) +FSM (6,19): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/x_MINUS(5,9) + Predecessor(s): e/q_PLUS(5,3) +FSM (6,20): Label = a_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(5,14) + Predecessor(s): p19(5,2) +FSM (6,21): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/q_PLUS(5,3) + Predecessor(s): c_PLUS/(5,8) +FSM (6,22): Label = a_MINUS/, Type = Trans. Function (is Input) + Successor(s): p17(5,7) + Predecessor(s): p15(5,12) +FSM (6,23): Label = e/q_MINUS, Type = Trans. Function (is Output) + Successor(s): p18(5,5) + Predecessor(s): p17(5,7) +FSM (6,24): Label = p10, Type = State (is Initially Inactive) + Successor(s): e/y_MINUS(5,13) + Predecessor(s): c_MINUS/(5,10) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/nowick_MG/nowick.petrinet.MG.workcraft.g b/examples/nowick_MG/nowick.petrinet.MG.workcraft.g new file mode 100644 index 0000000..992ce2f --- /dev/null +++ b/examples/nowick_MG/nowick.petrinet.MG.workcraft.g @@ -0,0 +1,44 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.5 +.model nowick +.inputs a_MINUS a_PLUS b_MINUS b_PLUS c_MINUS c_PLUS +.outputs x_MINUS x_MINUSa x_PLUS x_PLUSa y_MINUS y_MINUSa y_PLUS y_PLUSa q_MINUS q_PLUS +.graph +a_PLUS p0 p1 +x_PLUS p4 +y_PLUS p5 +b_PLUS p2 p3 +c_PLUS p6 +q_PLUS p7 +x_MINUS p8 +c_MINUS p10 p9 +x_PLUSa p11 +y_MINUS p12 +b_MINUS p13 p14 +x_MINUSa p15 +y_PLUSa p16 +a_MINUS p17 +q_MINUS p18 +y_MINUSa p19 p20 +p0 x_PLUS +p1 y_PLUS +p2 x_PLUS +p3 y_PLUS +p4 c_PLUS +p5 c_PLUS +p6 q_PLUS +p7 x_MINUS +p8 c_MINUS +p9 x_PLUSa +p10 y_MINUS +p11 b_MINUS +p12 b_MINUS +p13 x_MINUSa +p14 y_PLUSa +p15 a_MINUS +p16 a_MINUS +p17 q_MINUS +p18 y_MINUSa +p19 a_PLUS +p20 b_PLUS +.marking {p19 p20} +.end diff --git a/examples/simple-EFC-example_EFC/AsyncMSFSMs/fsm_afsm.afsm b/examples/simple-EFC-example_EFC/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..8395d54 --- /dev/null +++ b/examples/simple-EFC-example_EFC/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,30 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p2: t2_ t2__p2_FSM3_TB p6 +p4: t4_ t4__p4_FSM3_TB p6 +p0*: t0_ t0__p0_FSM2_TB t0__p1_FSM3_TB p2 +p0*: t1_ t1__p0_FSM2_TB t1__p1_FSM3_TB p4 +p6: t6_ t6__p7_FSM2_TB t6__p6_FSM3_TB p0 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p7: t6_ t6__p6_FSM1_TB t6__p6_FSM3_TB p0 +p3: t3_ p7 +p5: t5_ p7 +p0*: t0_ t0__p0_FSM1_TB t0__p1_FSM3_TB p3 +p0*: t1_ t1__p0_FSM1_TB t1__p1_FSM3_TB p5 +### End of FSM #02 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#03 Declaration ### +p2: t2_ t2__p2_FSM1_TB p6 +p4: t4_ t4__p4_FSM1_TB p6 +p6: t6_ t6__p6_FSM1_TB t6__p7_FSM2_TB p1 +p1*: t0_ t0__p0_FSM1_TB t0__p0_FSM2_TB p2 +p1*: t1_ t1__p0_FSM1_TB t1__p0_FSM2_TB p4 +### End of FSM #03 Declaration ### + diff --git a/examples/simple-EFC-example_EFC/AsyncMSFSMs/msfsms_afsm.v b/examples/simple-EFC-example_EFC/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..e974bb0 --- /dev/null +++ b/examples/simple-EFC-example_EFC/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,64 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + t0, + t5, + t1, + t6, + t2, + t3, + t4); + + input reset; + input t0; + input t5; + input t1; + input t6; + input t2; + input t3; + input t4; + + wire p2_FSM1out, p4_FSM1out, p0_FSM1out, p6_FSM1out; // State Synchronisation output signals of FSM1 // + wire p7_FSM2out, p3_FSM2out, p5_FSM2out, p0_FSM2out; // State Synchronisation output signals of FSM2 // + wire p2_FSM3out, p4_FSM3out, p6_FSM3out, p1_FSM3out; // State Synchronisation output signals of FSM3 // + + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t0_(t0), .t0__p0_FSM2_TB(p0_FSM2out), .t0__p1_FSM3_TB(p1_FSM3out), + .t1_(t1), .t1__p0_FSM2_TB(p0_FSM2out), .t1__p1_FSM3_TB(p1_FSM3out), + .t6_(t6), .t6__p7_FSM2_TB(p7_FSM2out), .t6__p6_FSM3_TB(p6_FSM3out), + .t2_(t2), .t2__p2_FSM3_TB(p2_FSM3out), + .t4_(t4), .t4__p4_FSM3_TB(p4_FSM3out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t0_(t0), .t0__p0_FSM1_TB(p0_FSM1out), .t0__p1_FSM3_TB(p1_FSM3out), + .t5_(t5), + .t1_(t1), .t1__p0_FSM1_TB(p0_FSM1out), .t1__p1_FSM3_TB(p1_FSM3out), + .t6_(t6), .t6__p6_FSM1_TB(p6_FSM1out), .t6__p6_FSM3_TB(p6_FSM3out), + .t3_(t3) + ); + + + fsm_afsm_03 fsm_afsm_03_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t0_(t0), .t0__p0_FSM1_TB(p0_FSM1out), .t0__p0_FSM2_TB(p0_FSM2out), + .t1_(t1), .t1__p0_FSM1_TB(p0_FSM1out), .t1__p0_FSM2_TB(p0_FSM2out), + .t6_(t6), .t6__p6_FSM1_TB(p6_FSM1out), .t6__p7_FSM2_TB(p7_FSM2out), + .t2_(t2), .t2__p2_FSM1_TB(p2_FSM1out), + .t4_(t4), .t4__p4_FSM1_TB(p4_FSM1out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..4ed575a --- /dev/null +++ b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,447 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + t0_, t0__p0_FSM2_TB, t0__p1_FSM3_TB, + t1_, t1__p0_FSM2_TB, t1__p1_FSM3_TB, + t6_, t6__p7_FSM2_TB, t6__p6_FSM3_TB, + t2_, t2__p2_FSM3_TB, + t4_, t4__p4_FSM3_TB, + p2, + p4, + p0, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input t1_; + input t6_; + input t2_; + input t4_; + // Transition Barrier Inputs for input Signals // + input t0__p0_FSM2_TB, t0__p1_FSM3_TB; + input t1__p0_FSM2_TB, t1__p1_FSM3_TB; + input t6__p7_FSM2_TB, t6__p6_FSM3_TB; + input t2__p2_FSM3_TB; + input t4__p4_FSM3_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p2; + output p4; + output p0; + output p6; + + wire p2; + wire p4; + wire p0; + wire p6; + + wire t0__TB_sync; + wire t1__TB_sync; + wire t6__TB_sync; + wire t2__TB_sync; + wire t4__TB_sync; + assign t0__TB_sync = t0_ & t0__p0_FSM2_TB & t0__p1_FSM3_TB; + assign t1__TB_sync = t1_ & t1__p0_FSM2_TB & t1__p1_FSM3_TB; + assign t6__TB_sync = t6_ & t6__p7_FSM2_TB & t6__p6_FSM3_TB; + assign t2__TB_sync = t2_ & t2__p2_FSM3_TB; + assign t4__TB_sync = t4_ & t4__p4_FSM3_TB; + + parameter p2_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p2_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p4_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p4_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p0_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p0_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p6_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p6_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p0_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + state[3] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or t1__TB_sync or t6__TB_sync or t2__TB_sync or t4__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 4'bxxx1: // p2_1HOT_ENCODING: // + begin + if (t2__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bxx1x: // p4_1HOT_ENCODING: // + begin + if (t4__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bx1xx: // p0_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + else if (t1__TB_sync) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + 4'b1xxx: // p6_1HOT_ENCODING: // + begin + if (t6__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + t0_, t0__p0_FSM1_TB, t0__p1_FSM3_TB, + t5_, + t1_, t1__p0_FSM1_TB, t1__p1_FSM3_TB, + t6_, t6__p6_FSM1_TB, t6__p6_FSM3_TB, + t3_, + p7, + p0 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input t5_; + input t1_; + input t6_; + input t3_; + // Transition Barrier Inputs for input Signals // + input t0__p0_FSM1_TB, t0__p1_FSM3_TB; + input t1__p0_FSM1_TB, t1__p1_FSM3_TB; + input t6__p6_FSM1_TB, t6__p6_FSM3_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p7; + output p0; + + wire p7; + wire p0; + + wire t0__TB_sync; + wire t1__TB_sync; + wire t6__TB_sync; + assign t0__TB_sync = t0_ & t0__p0_FSM1_TB & t0__p1_FSM3_TB; + assign t1__TB_sync = t1_ & t1__p0_FSM1_TB & t1__p1_FSM3_TB; + assign t6__TB_sync = t6_ & t6__p6_FSM1_TB & t6__p6_FSM3_TB; + + parameter p7_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p7_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p3_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p5_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p5_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p0_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p0_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p0_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or t5_ or t1__TB_sync or t6__TB_sync or t3_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 4'bxxx1: // p7_1HOT_ENCODING: // + begin + if (t6__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bxx1x: // p3_1HOT_ENCODING: // + begin + if (t3_) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'bx1xx: // p5_1HOT_ENCODING: // + begin + if (t5_) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'b1xxx: // p0_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + else if (t1__TB_sync) + begin + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_03 ( + clk, + reset, + t0_, t0__p0_FSM1_TB, t0__p0_FSM2_TB, + t1_, t1__p0_FSM1_TB, t1__p0_FSM2_TB, + t6_, t6__p6_FSM1_TB, t6__p7_FSM2_TB, + t2_, t2__p2_FSM1_TB, + t4_, t4__p4_FSM1_TB, + p2, + p4, + p6, + p1 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input t1_; + input t6_; + input t2_; + input t4_; + // Transition Barrier Inputs for input Signals // + input t0__p0_FSM1_TB, t0__p0_FSM2_TB; + input t1__p0_FSM1_TB, t1__p0_FSM2_TB; + input t6__p6_FSM1_TB, t6__p7_FSM2_TB; + input t2__p2_FSM1_TB; + input t4__p4_FSM1_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p2; + output p4; + output p6; + output p1; + + wire p2; + wire p4; + wire p6; + wire p1; + + wire t0__TB_sync; + wire t1__TB_sync; + wire t6__TB_sync; + wire t2__TB_sync; + wire t4__TB_sync; + assign t0__TB_sync = t0_ & t0__p0_FSM1_TB & t0__p0_FSM2_TB; + assign t1__TB_sync = t1_ & t1__p0_FSM1_TB & t1__p0_FSM2_TB; + assign t6__TB_sync = t6_ & t6__p6_FSM1_TB & t6__p7_FSM2_TB; + assign t2__TB_sync = t2_ & t2__p2_FSM1_TB; + assign t4__TB_sync = t4_ & t4__p4_FSM1_TB; + + parameter p2_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p2_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p4_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p4_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p6_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p6_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p1_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p1_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or t1__TB_sync or t6__TB_sync or t2__TB_sync or t4__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 4'bxxx1: // p2_1HOT_ENCODING: // + begin + if (t2__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[2] = 1'b1; + end + end + + 4'bxx1x: // p4_1HOT_ENCODING: // + begin + if (t4__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + end + + 4'bx1xx: // p6_1HOT_ENCODING: // + begin + if (t6__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'b1xxx: // p1_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[0] = 1'b1; + end + else if (t1__TB_sync) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[1] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + diff --git a/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..4856fc9 --- /dev/null +++ b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,393 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + t0_, t0__p0_FSM2_TB, t0__p1_FSM3_TB, + t1_, t1__p0_FSM2_TB, t1__p1_FSM3_TB, + t6_, t6__p7_FSM2_TB, t6__p6_FSM3_TB, + t2_, t2__p2_FSM3_TB, + t4_, t4__p4_FSM3_TB, + p2, + p4, + p0, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input t1_; + input t6_; + input t2_; + input t4_; + // Transition Barrier Inputs for input Signals // + input t0__p0_FSM2_TB, t0__p1_FSM3_TB; + input t1__p0_FSM2_TB, t1__p1_FSM3_TB; + input t6__p7_FSM2_TB, t6__p6_FSM3_TB; + input t2__p2_FSM3_TB; + input t4__p4_FSM3_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p2; + output p4; + output p0; + output p6; + + wire p2; + wire p4; + wire p0; + wire p6; + + wire t0__TB_sync; + wire t1__TB_sync; + wire t6__TB_sync; + wire t2__TB_sync; + wire t4__TB_sync; + assign t0__TB_sync = t0_ & t0__p0_FSM2_TB & t0__p1_FSM3_TB; + assign t1__TB_sync = t1_ & t1__p0_FSM2_TB & t1__p1_FSM3_TB; + assign t6__TB_sync = t6_ & t6__p7_FSM2_TB & t6__p6_FSM3_TB; + assign t2__TB_sync = t2_ & t2__p2_FSM3_TB; + assign t4__TB_sync = t4_ & t4__p4_FSM3_TB; + + parameter p2_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p4_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p0_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p6_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p0_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or t1__TB_sync or t6__TB_sync or t2__TB_sync or t4__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p2_1HOT_ENCODING: // 4'b0001: // + begin + if (t2__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 4'b0010: // + begin + if (t4__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 4'b0100: // + begin + if (t0__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + else if (t1__TB_sync) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 4'b1000: // + begin + if (t6__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + t0_, t0__p0_FSM1_TB, t0__p1_FSM3_TB, + t5_, + t1_, t1__p0_FSM1_TB, t1__p1_FSM3_TB, + t6_, t6__p6_FSM1_TB, t6__p6_FSM3_TB, + t3_, + p7, + p0 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input t5_; + input t1_; + input t6_; + input t3_; + // Transition Barrier Inputs for input Signals // + input t0__p0_FSM1_TB, t0__p1_FSM3_TB; + input t1__p0_FSM1_TB, t1__p1_FSM3_TB; + input t6__p6_FSM1_TB, t6__p6_FSM3_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p7; + output p0; + + wire p7; + wire p0; + + wire t0__TB_sync; + wire t1__TB_sync; + wire t6__TB_sync; + assign t0__TB_sync = t0_ & t0__p0_FSM1_TB & t0__p1_FSM3_TB; + assign t1__TB_sync = t1_ & t1__p0_FSM1_TB & t1__p1_FSM3_TB; + assign t6__TB_sync = t6_ & t6__p6_FSM1_TB & t6__p6_FSM3_TB; + + parameter p7_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p5_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p0_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p0_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or t5_ or t1__TB_sync or t6__TB_sync or t3_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p7_1HOT_ENCODING: // 4'b0001: // + begin + if (t6__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 4'b0010: // + begin + if (t3_) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 4'b0100: // + begin + if (t5_) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 4'b1000: // + begin + if (t0__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + else if (t1__TB_sync) + begin + next_state = p5_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_03 ( + clk, + reset, + t0_, t0__p0_FSM1_TB, t0__p0_FSM2_TB, + t1_, t1__p0_FSM1_TB, t1__p0_FSM2_TB, + t6_, t6__p6_FSM1_TB, t6__p7_FSM2_TB, + t2_, t2__p2_FSM1_TB, + t4_, t4__p4_FSM1_TB, + p2, + p4, + p6, + p1 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input t1_; + input t6_; + input t2_; + input t4_; + // Transition Barrier Inputs for input Signals // + input t0__p0_FSM1_TB, t0__p0_FSM2_TB; + input t1__p0_FSM1_TB, t1__p0_FSM2_TB; + input t6__p6_FSM1_TB, t6__p7_FSM2_TB; + input t2__p2_FSM1_TB; + input t4__p4_FSM1_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p2; + output p4; + output p6; + output p1; + + wire p2; + wire p4; + wire p6; + wire p1; + + wire t0__TB_sync; + wire t1__TB_sync; + wire t6__TB_sync; + wire t2__TB_sync; + wire t4__TB_sync; + assign t0__TB_sync = t0_ & t0__p0_FSM1_TB & t0__p0_FSM2_TB; + assign t1__TB_sync = t1_ & t1__p0_FSM1_TB & t1__p0_FSM2_TB; + assign t6__TB_sync = t6_ & t6__p6_FSM1_TB & t6__p7_FSM2_TB; + assign t2__TB_sync = t2_ & t2__p2_FSM1_TB; + assign t4__TB_sync = t4_ & t4__p4_FSM1_TB; + + parameter p2_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p4_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p6_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p1_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or t1__TB_sync or t6__TB_sync or t2__TB_sync or t4__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p2_1HOT_ENCODING: // 4'b0001: // + begin + if (t2__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 4'b0010: // + begin + if (t4__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 4'b0100: // + begin + if (t6__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 4'b1000: // + begin + if (t0__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + else if (t1__TB_sync) + begin + next_state = p4_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + diff --git a/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..5ddf2bd --- /dev/null +++ b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,71 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + t0, + t5, + t1, + t6, + t2, + t3, + t4); + + input clk; + input reset; + input t0; + input t5; + input t1; + input t6; + input t2; + input t3; + input t4; + + wire p2_FSM1out, p4_FSM1out, p0_FSM1out, p6_FSM1out; // State Synchronisation output signals of FSM1 // + wire p7_FSM2out, p3_FSM2out, p5_FSM2out, p0_FSM2out; // State Synchronisation output signals of FSM2 // + wire p2_FSM3out, p4_FSM3out, p6_FSM3out, p1_FSM3out; // State Synchronisation output signals of FSM3 // + + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p0_FSM2_TB(p0_FSM2out), .t0__p1_FSM3_TB(p1_FSM3out), + .t1_(t1), .t1__p0_FSM2_TB(p0_FSM2out), .t1__p1_FSM3_TB(p1_FSM3out), + .t6_(t6), .t6__p7_FSM2_TB(p7_FSM2out), .t6__p6_FSM3_TB(p6_FSM3out), + .t2_(t2), .t2__p2_FSM3_TB(p2_FSM3out), + .t4_(t4), .t4__p4_FSM3_TB(p4_FSM3out), + .p2(p2_FSM1out), + .p4(p4_FSM1out), + .p0(p0_FSM1out), + .p6(p6_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p0_FSM1_TB(p0_FSM1out), .t0__p1_FSM3_TB(p1_FSM3out), + .t5_(t5), + .t1_(t1), .t1__p0_FSM1_TB(p0_FSM1out), .t1__p1_FSM3_TB(p1_FSM3out), + .t6_(t6), .t6__p6_FSM1_TB(p6_FSM1out), .t6__p6_FSM3_TB(p6_FSM3out), + .t3_(t3), + .p7(p7_FSM2out), + .p0(p0_FSM2out) + ); + + + fsm_mealy_behav_03 fsm_mealy_behav_03_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p0_FSM1_TB(p0_FSM1out), .t0__p0_FSM2_TB(p0_FSM2out), + .t1_(t1), .t1__p0_FSM1_TB(p0_FSM1out), .t1__p0_FSM2_TB(p0_FSM2out), + .t6_(t6), .t6__p6_FSM1_TB(p6_FSM1out), .t6__p7_FSM2_TB(p7_FSM2out), + .t2_(t2), .t2__p2_FSM1_TB(p2_FSM1out), + .t4_(t4), .t4__p4_FSM1_TB(p4_FSM1out), + .p2(p2_FSM3out), + .p4(p4_FSM3out), + .p6(p6_FSM3out), + .p1(p1_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..cd41f2b --- /dev/null +++ b/examples/simple-EFC-example_EFC/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,71 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + t0, + t5, + t1, + t6, + t2, + t3, + t4); + + input clk; + input reset; + input t0; + input t5; + input t1; + input t6; + input t2; + input t3; + input t4; + + wire p2_FSM1out, p4_FSM1out, p0_FSM1out, p6_FSM1out; // State Synchronisation output signals of FSM1 // + wire p7_FSM2out, p3_FSM2out, p5_FSM2out, p0_FSM2out; // State Synchronisation output signals of FSM2 // + wire p2_FSM3out, p4_FSM3out, p6_FSM3out, p1_FSM3out; // State Synchronisation output signals of FSM3 // + + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p0_FSM2_TB(p0_FSM2out), .t0__p1_FSM3_TB(p1_FSM3out), + .t1_(t1), .t1__p0_FSM2_TB(p0_FSM2out), .t1__p1_FSM3_TB(p1_FSM3out), + .t6_(t6), .t6__p7_FSM2_TB(p7_FSM2out), .t6__p6_FSM3_TB(p6_FSM3out), + .t2_(t2), .t2__p2_FSM3_TB(p2_FSM3out), + .t4_(t4), .t4__p4_FSM3_TB(p4_FSM3out), + .p2(p2_FSM1out), + .p4(p4_FSM1out), + .p0(p0_FSM1out), + .p6(p6_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p0_FSM1_TB(p0_FSM1out), .t0__p1_FSM3_TB(p1_FSM3out), + .t5_(t5), + .t1_(t1), .t1__p0_FSM1_TB(p0_FSM1out), .t1__p1_FSM3_TB(p1_FSM3out), + .t6_(t6), .t6__p6_FSM1_TB(p6_FSM1out), .t6__p6_FSM3_TB(p6_FSM3out), + .t3_(t3), + .p7(p7_FSM2out), + .p0(p0_FSM2out) + ); + + + fsm_mealy_synth_03 fsm_mealy_synth_03_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p0_FSM1_TB(p0_FSM1out), .t0__p0_FSM2_TB(p0_FSM2out), + .t1_(t1), .t1__p0_FSM1_TB(p0_FSM1out), .t1__p0_FSM2_TB(p0_FSM2out), + .t6_(t6), .t6__p6_FSM1_TB(p6_FSM1out), .t6__p7_FSM2_TB(p7_FSM2out), + .t2_(t2), .t2__p2_FSM1_TB(p2_FSM1out), + .t4_(t4), .t4__p4_FSM1_TB(p4_FSM1out), + .p2(p2_FSM3out), + .p4(p4_FSM3out), + .p6(p6_FSM3out), + .p1(p1_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/simple-EFC-example_EFC/msfsms_tool_bm.log b/examples/simple-EFC-example_EFC/msfsms_tool_bm.log new file mode 100644 index 0000000..43f6c35 --- /dev/null +++ b/examples/simple-EFC-example_EFC/msfsms_tool_bm.log @@ -0,0 +1,245 @@ +--------------------------------------------------------------------------- +Benchmark: simple-EFC-example_EFC/simple-EFC-example.petrinet.EFC.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/simple-EFC-example_EFC/simple-EFC-example.petrinet.EFC.workcraft.g +INFO: Total Nodes : 15 +INFO: Total Transitions : 7 +INFO: Total Places : 8 +INFO: Total Edges : 20 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = t0, Type = Transition (is Input) + Predecessors: p0[9][2], p1[12][2] + Successors: p2[0][1], p3[3][0] +PT-Net [0][1]: Label = p2, Type = Place (is Empty) + Predecessors: t0[0][0] + Successors: t2[6][1] +PT-Net [0][2]: Label = p7, Type = Place (is Empty) + Predecessors: t3[9][1], t5[0][3] + Successors: t6[3][2] +PT-Net [0][3]: Label = t5, Type = Transition (is Input) + Predecessors: p5[9][0] + Successors: p7[0][2] +PT-Net [3][0]: Label = p3, Type = Place (is Empty) + Predecessors: t0[0][0] + Successors: t3[9][1] +PT-Net [3][1]: Label = t1, Type = Transition (is Input) + Predecessors: p0[9][2], p1[12][2] + Successors: p4[6][0], p5[9][0] +PT-Net [3][2]: Label = t6, Type = Transition (is Input) + Predecessors: p6[12][0], p7[0][2] + Successors: p0[9][2], p1[12][2] +PT-Net [6][0]: Label = p4, Type = Place (is Empty) + Predecessors: t1[3][1] + Successors: t4[12][1] +PT-Net [6][1]: Label = t2, Type = Transition (is Input) + Predecessors: p2[0][1] + Successors: p6[12][0] +PT-Net [9][0]: Label = p5, Type = Place (is Empty) + Predecessors: t1[3][1] + Successors: t5[0][3] +PT-Net [9][1]: Label = t3, Type = Transition (is Input) + Predecessors: p3[3][0] + Successors: p7[0][2] +PT-Net [9][2]: Label = p0, Type = Place (is Marked) + Predecessors: t6[3][2] + Successors: t0[0][0], t1[3][1] +PT-Net [12][0]: Label = p6, Type = Place (is Empty) + Predecessors: t2[6][1], t4[12][1] + Successors: t6[3][2] +PT-Net [12][1]: Label = t4, Type = Transition (is Input) + Predecessors: p4[6][0] + Successors: p6[12][0] +PT-Net [12][2]: Label = p1, Type = Place (is Marked) + Predecessors: t6[3][2] + Successors: t0[0][0], t1[3][1] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #3 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 9, H-collapsed = 'false' *** +SC S-net (1,1): t0[0][0] + Predecessor Place: p0(1,7)[9,2] + Successor Place: p2(1,2)[0,1] +SC S-net (1,2): p2[0][1] +SC S-net (1,3): t1[3][1] + Predecessor Place: p0(1,7)[9,2] + Successor Place: p4(1,5)[6,0] +SC S-net (1,4): t6[3][2] + Predecessor Place: p6(1,8)[12,0] + Successor Place: p0(1,7)[9,2] +SC S-net (1,5): p4[6][0] +SC S-net (1,6): t2[6][1] + Predecessor Place: p2(1,2)[0,1] + Successor Place: p6(1,8)[12,0] +SC S-net (1,7): p0[9][2] +SC S-net (1,8): p6[12][0] +SC S-net (1,9): t4[12][1] + Predecessor Place: p4(1,5)[6,0] + Successor Place: p6(1,8)[12,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 9, H-collapsed = 'false' *** +SC S-net (2,1): t0[0][0] + Predecessor Place: p0(2,9)[9,2] + Successor Place: p3(2,4)[3,0] +SC S-net (2,2): p7[0][2] +SC S-net (2,3): t5[0][3] + Predecessor Place: p5(2,7)[9,0] + Successor Place: p7(2,2)[0,2] +SC S-net (2,4): p3[3][0] +SC S-net (2,5): t1[3][1] + Predecessor Place: p0(2,9)[9,2] + Successor Place: p5(2,7)[9,0] +SC S-net (2,6): t6[3][2] + Predecessor Place: p7(2,2)[0,2] + Successor Place: p0(2,9)[9,2] +SC S-net (2,7): p5[9][0] +SC S-net (2,8): t3[9][1] + Predecessor Place: p3(2,4)[3,0] + Successor Place: p7(2,2)[0,2] +SC S-net (2,9): p0[9][2] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #3, Total Nodes = 9, H-collapsed = 'false' *** +SC S-net (3,1): t0[0][0] + Predecessor Place: p1(3,9)[12,2] + Successor Place: p2(3,2)[0,1] +SC S-net (3,2): p2[0][1] +SC S-net (3,3): t1[3][1] + Predecessor Place: p1(3,9)[12,2] + Successor Place: p4(3,5)[6,0] +SC S-net (3,4): t6[3][2] + Predecessor Place: p6(3,7)[12,0] + Successor Place: p1(3,9)[12,2] +SC S-net (3,5): p4[6][0] +SC S-net (3,6): t2[6][1] + Predecessor Place: p2(3,2)[0,1] + Successor Place: p6(3,7)[12,0] +SC S-net (3,7): p6[12][0] +SC S-net (3,8): t4[12][1] + Predecessor Place: p4(3,5)[6,0] + Successor Place: p6(3,7)[12,0] +SC S-net (3,9): p1[12][2] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #3 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#3 ***, identical to #1 +Matching Pairs: +Index 0: Matching pairs (1, 1) +Index 1: Matching pairs (3, 3) +Index 2: Matching pairs (6, 6) +Index 3: Matching pairs (9, 8) +Index 4: Matching pairs (4, 4) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 9, H-Collapsed = 'false' *** +FSM (1,1): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p2(0,2) + Predecessor(s): p0(0,7) +FSM (1,2): Label = p2, Type = State (is Initially Inactive) + Successor(s): t2/(0,6) + Predecessor(s): t0/(0,1) +FSM (1,3): Label = t1/, Type = Trans. Function (is Input) + Successor(s): p4(0,5) + Predecessor(s): p0(0,7) +FSM (1,4): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p0(0,7) + Predecessor(s): p6(0,8) +FSM (1,5): Label = p4, Type = State (is Initially Inactive) + Successor(s): t4/(0,9) + Predecessor(s): t1/(0,3) +FSM (1,6): Label = t2/, Type = Trans. Function (is Input) + Successor(s): p6(0,8) + Predecessor(s): p2(0,2) +FSM (1,7): Label = p0, Type = State (is Initially Active) + Successor(s): t0/(0,1) t1/(0,3) + Predecessor(s): t6/(0,4) +FSM (1,8): Label = p6, Type = State (is Initially Inactive) + Successor(s): t6/(0,4) + Predecessor(s): t2/(0,6) t4/(0,9) +FSM (1,9): Label = t4/, Type = Trans. Function (is Input) + Successor(s): p6(0,8) + Predecessor(s): p4(0,5) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 9, H-Collapsed = 'false' *** +FSM (2,1): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p3(1,4) + Predecessor(s): p0(1,9) +FSM (2,2): Label = p7, Type = State (is Initially Inactive) + Successor(s): t6/(1,6) + Predecessor(s): t3/(1,8) t5/(1,3) +FSM (2,3): Label = t5/, Type = Trans. Function (is Input) + Successor(s): p7(1,2) + Predecessor(s): p5(1,7) +FSM (2,4): Label = p3, Type = State (is Initially Inactive) + Successor(s): t3/(1,8) + Predecessor(s): t0/(1,1) +FSM (2,5): Label = t1/, Type = Trans. Function (is Input) + Successor(s): p5(1,7) + Predecessor(s): p0(1,9) +FSM (2,6): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p0(1,9) + Predecessor(s): p7(1,2) +FSM (2,7): Label = p5, Type = State (is Initially Inactive) + Successor(s): t5/(1,3) + Predecessor(s): t1/(1,5) +FSM (2,8): Label = t3/, Type = Trans. Function (is Input) + Successor(s): p7(1,2) + Predecessor(s): p3(1,4) +FSM (2,9): Label = p0, Type = State (is Initially Active) + Successor(s): t0/(1,1) t1/(1,5) + Predecessor(s): t6/(1,6) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 3, Total list Entries = 9, H-Collapsed = 'false' *** +FSM (3,1): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p2(2,2) + Predecessor(s): p1(2,9) +FSM (3,2): Label = p2, Type = State (is Initially Inactive) + Successor(s): t2/(2,6) + Predecessor(s): t0/(2,1) +FSM (3,3): Label = t1/, Type = Trans. Function (is Input) + Successor(s): p4(2,5) + Predecessor(s): p1(2,9) +FSM (3,4): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p1(2,9) + Predecessor(s): p6(2,7) +FSM (3,5): Label = p4, Type = State (is Initially Inactive) + Successor(s): t4/(2,8) + Predecessor(s): t1/(2,3) +FSM (3,6): Label = t2/, Type = Trans. Function (is Input) + Successor(s): p6(2,7) + Predecessor(s): p2(2,2) +FSM (3,7): Label = p6, Type = State (is Initially Inactive) + Successor(s): t6/(2,4) + Predecessor(s): t2/(2,6) t4/(2,8) +FSM (3,8): Label = t4/, Type = Trans. Function (is Input) + Successor(s): p6(2,7) + Predecessor(s): p4(2,5) +FSM (3,9): Label = p1, Type = State (is Initially Active) + Successor(s): t0/(2,1) t1/(2,3) + Predecessor(s): t6/(2,4) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/simple-EFC-example_EFC/simple-EFC-example.petrinet.EFC.workcraft.g b/examples/simple-EFC-example_EFC/simple-EFC-example.petrinet.EFC.workcraft.g new file mode 100644 index 0000000..fc0afeb --- /dev/null +++ b/examples/simple-EFC-example_EFC/simple-EFC-example.petrinet.EFC.workcraft.g @@ -0,0 +1,21 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.0 +.model Untitled +.dummy t0 t1 t2 t3 t4 t5 t6 +.graph +t0 p2 p3 +t1 p4 p5 +t2 p6 +t3 p7 +t4 p6 +t5 p7 +t6 p0 p1 +p0 t0 t1 +p1 t0 t1 +p2 t2 +p3 t3 +p4 t4 +p5 t5 +p6 t6 +p7 t6 +.marking {p0 p1} +.end diff --git a/examples/simple-FC-example_FC/AsyncMSFSMs/fsm_afsm.afsm b/examples/simple-FC-example_FC/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..166459f --- /dev/null +++ b/examples/simple-FC-example_FC/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,33 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p3: t0_ t0__p9_FSM2_TB t0__p7_FSM3_TB t0__p6_FSM4_TB p0 +p2: t4_ p3 +p0*: t1_ p2 +p0*: t2_ p3 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p9: t0_ t0__p3_FSM1_TB t0__p7_FSM3_TB t0__p6_FSM4_TB p1 +p8: t7_ p9 +p1*: t3_ t3__p1_FSM3_TB t3__p1_FSM4_TB p8 +### End of FSM #02 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#03 Declaration ### +p1*: t3_ t3__p1_FSM2_TB t3__p1_FSM4_TB p5 +p7: t0_ t0__p3_FSM1_TB t0__p9_FSM2_TB t0__p6_FSM4_TB p1 +p5: t6_ p7 +### End of FSM #03 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#04 Declaration ### +p1*: t3_ t3__p1_FSM2_TB t3__p1_FSM3_TB p4 +p6: t0_ t0__p3_FSM1_TB t0__p9_FSM2_TB t0__p7_FSM3_TB p1 +p4: t5_ p6 +### End of FSM #04 Declaration ### + diff --git a/examples/simple-FC-example_FC/AsyncMSFSMs/msfsms_afsm.v b/examples/simple-FC-example_FC/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..2838dc0 --- /dev/null +++ b/examples/simple-FC-example_FC/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,72 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + t3, + t2, + t1, + t7, + t0, + t6, + t5, + t4); + + input reset; + input t3; + input t2; + input t1; + input t7; + input t0; + input t6; + input t5; + input t4; + + wire p3_FSM1out, p2_FSM1out, p0_FSM1out; // State Synchronisation output signals of FSM1 // + wire p9_FSM2out, p8_FSM2out, p1_FSM2out; // State Synchronisation output signals of FSM2 // + wire p1_FSM3out, p7_FSM3out, p5_FSM3out; // State Synchronisation output signals of FSM3 // + wire p1_FSM4out, p6_FSM4out, p4_FSM4out; // State Synchronisation output signals of FSM4 // + + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t2_(t2), + .t1_(t1), + .t0_(t0), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p7_FSM3_TB(p7_FSM3out), .t0__p6_FSM4_TB(p6_FSM4out), + .t4_(t4) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t3_(t3), .t3__p1_FSM3_TB(p1_FSM3out), .t3__p1_FSM4_TB(p1_FSM4out), + .t7_(t7), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p7_FSM3_TB(p7_FSM3out), .t0__p6_FSM4_TB(p6_FSM4out) + ); + + + fsm_afsm_03 fsm_afsm_03_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t3_(t3), .t3__p1_FSM2_TB(p1_FSM2out), .t3__p1_FSM4_TB(p1_FSM4out), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p6_FSM4_TB(p6_FSM4out), + .t6_(t6) + ); + + + fsm_afsm_04 fsm_afsm_04_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t3_(t3), .t3__p1_FSM2_TB(p1_FSM2out), .t3__p1_FSM3_TB(p1_FSM3out), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p7_FSM3_TB(p7_FSM3out), + .t5_(t5) + ); + +endmodule // msfsms_mealy // diff --git a/examples/simple-FC-example_FC/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/simple-FC-example_FC/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..aa66f6e --- /dev/null +++ b/examples/simple-FC-example_FC/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,455 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + t2_, + t1_, + t0_, t0__p9_FSM2_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB, + t4_, + p3 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t2_; + input t1_; + input t0_; + input t4_; + // Transition Barrier Inputs for input Signals // + input t0__p9_FSM2_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p3; + + wire p3; + + wire t0__TB_sync; + assign t0__TB_sync = t0_ & t0__p9_FSM2_TB & t0__p7_FSM3_TB & t0__p6_FSM4_TB; + + parameter p3_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p3_1HOT_CASEX_ENCODING = 3'bxx1; // 3'b001 // + parameter p2_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p2_1HOT_CASEX_ENCODING = 3'bx1x; // 3'b010 // + parameter p0_1HOT_ENCODING = 3'd4; // 3'b100 // + parameter p0_1HOT_CASEX_ENCODING = 3'b1xx; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p0_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t2_ or t1_ or t0__TB_sync or t4_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 3'bxx1: // p3_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[2] = 1'b1; + end + end + + 3'bx1x: // p2_1HOT_ENCODING: // + begin + if (t4_) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 3'b1xx: // p0_1HOT_ENCODING: // + begin + if (t1_) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + else if (t2_) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + t3_, t3__p1_FSM3_TB, t3__p1_FSM4_TB, + t7_, + t0_, t0__p3_FSM1_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB, + p9, + p1 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t3_; + input t7_; + input t0_; + // Transition Barrier Inputs for input Signals // + input t3__p1_FSM3_TB, t3__p1_FSM4_TB; + input t0__p3_FSM1_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p9; + output p1; + + wire p9; + wire p1; + + wire t3__TB_sync; + wire t0__TB_sync; + assign t3__TB_sync = t3_ & t3__p1_FSM3_TB & t3__p1_FSM4_TB; + assign t0__TB_sync = t0_ & t0__p3_FSM1_TB & t0__p7_FSM3_TB & t0__p6_FSM4_TB; + + parameter p9_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p9_1HOT_CASEX_ENCODING = 3'bxx1; // 3'b001 // + parameter p8_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p8_1HOT_CASEX_ENCODING = 3'bx1x; // 3'b010 // + parameter p1_1HOT_ENCODING = 3'd4; // 3'b100 // + parameter p1_1HOT_CASEX_ENCODING = 3'b1xx; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t3__TB_sync or t7_ or t0__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 3'bxx1: // p9_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[2] = 1'b1; + end + end + + 3'bx1x: // p8_1HOT_ENCODING: // + begin + if (t7_) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 3'b1xx: // p1_1HOT_ENCODING: // + begin + if (t3__TB_sync) + begin + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_03 ( + clk, + reset, + t3_, t3__p1_FSM2_TB, t3__p1_FSM4_TB, + t0_, t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p6_FSM4_TB, + t6_, + p1, + p7 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t3_; + input t0_; + input t6_; + // Transition Barrier Inputs for input Signals // + input t3__p1_FSM2_TB, t3__p1_FSM4_TB; + input t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p6_FSM4_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p1; + output p7; + + wire p1; + wire p7; + + wire t3__TB_sync; + wire t0__TB_sync; + assign t3__TB_sync = t3_ & t3__p1_FSM2_TB & t3__p1_FSM4_TB; + assign t0__TB_sync = t0_ & t0__p3_FSM1_TB & t0__p9_FSM2_TB & t0__p6_FSM4_TB; + + parameter p1_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p1_1HOT_CASEX_ENCODING = 3'bxx1; // 3'b001 // + parameter p7_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p7_1HOT_CASEX_ENCODING = 3'bx1x; // 3'b010 // + parameter p5_1HOT_ENCODING = 3'd4; // 3'b100 // + parameter p5_1HOT_CASEX_ENCODING = 3'b1xx; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t3__TB_sync or t0__TB_sync or t6_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 3'bxx1: // p1_1HOT_ENCODING: // + begin + if (t3__TB_sync) + begin + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[2] = 1'b1; + end + end + + 3'bx1x: // p7_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 3'b1xx: // p5_1HOT_ENCODING: // + begin + if (t6_) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_04 ( + clk, + reset, + t3_, t3__p1_FSM2_TB, t3__p1_FSM3_TB, + t0_, t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p7_FSM3_TB, + t5_, + p1, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t3_; + input t0_; + input t5_; + // Transition Barrier Inputs for input Signals // + input t3__p1_FSM2_TB, t3__p1_FSM3_TB; + input t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p7_FSM3_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p1; + output p6; + + wire p1; + wire p6; + + wire t3__TB_sync; + wire t0__TB_sync; + assign t3__TB_sync = t3_ & t3__p1_FSM2_TB & t3__p1_FSM3_TB; + assign t0__TB_sync = t0_ & t0__p3_FSM1_TB & t0__p9_FSM2_TB & t0__p7_FSM3_TB; + + parameter p1_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p1_1HOT_CASEX_ENCODING = 3'bxx1; // 3'b001 // + parameter p6_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p6_1HOT_CASEX_ENCODING = 3'bx1x; // 3'b010 // + parameter p4_1HOT_ENCODING = 3'd4; // 3'b100 // + parameter p4_1HOT_CASEX_ENCODING = 3'b1xx; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t3__TB_sync or t0__TB_sync or t5_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 3'bxx1: // p1_1HOT_ENCODING: // + begin + if (t3__TB_sync) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[2] = 1'b1; + end + end + + 3'bx1x: // p6_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 3'b1xx: // p4_1HOT_ENCODING: // + begin + if (t5_) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + diff --git a/examples/simple-FC-example_FC/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/simple-FC-example_FC/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..72ceee7 --- /dev/null +++ b/examples/simple-FC-example_FC/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,405 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + t2_, + t1_, + t0_, t0__p9_FSM2_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB, + t4_, + p3 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t2_; + input t1_; + input t0_; + input t4_; + // Transition Barrier Inputs for input Signals // + input t0__p9_FSM2_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p3; + + wire p3; + + wire t0__TB_sync; + assign t0__TB_sync = t0_ & t0__p9_FSM2_TB & t0__p7_FSM3_TB & t0__p6_FSM4_TB; + + parameter p3_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p2_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p0_1HOT_ENCODING = 3'd4; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p0_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t2_ or t1_ or t0__TB_sync or t4_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p3_1HOT_ENCODING: // 3'b001: // + begin + if (t0__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 3'b010: // + begin + if (t4_) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 3'b100: // + begin + if (t1_) + begin + next_state = p2_1HOT_ENCODING; + end + else if (t2_) + begin + next_state = p3_1HOT_ENCODING; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + t3_, t3__p1_FSM3_TB, t3__p1_FSM4_TB, + t7_, + t0_, t0__p3_FSM1_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB, + p9, + p1 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t3_; + input t7_; + input t0_; + // Transition Barrier Inputs for input Signals // + input t3__p1_FSM3_TB, t3__p1_FSM4_TB; + input t0__p3_FSM1_TB, t0__p7_FSM3_TB, t0__p6_FSM4_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p9; + output p1; + + wire p9; + wire p1; + + wire t3__TB_sync; + wire t0__TB_sync; + assign t3__TB_sync = t3_ & t3__p1_FSM3_TB & t3__p1_FSM4_TB; + assign t0__TB_sync = t0_ & t0__p3_FSM1_TB & t0__p7_FSM3_TB & t0__p6_FSM4_TB; + + parameter p9_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p8_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p1_1HOT_ENCODING = 3'd4; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t3__TB_sync or t7_ or t0__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p9_1HOT_ENCODING: // 3'b001: // + begin + if (t0__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 3'b010: // + begin + if (t7_) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 3'b100: // + begin + if (t3__TB_sync) + begin + next_state = p8_1HOT_ENCODING; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_03 ( + clk, + reset, + t3_, t3__p1_FSM2_TB, t3__p1_FSM4_TB, + t0_, t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p6_FSM4_TB, + t6_, + p1, + p7 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t3_; + input t0_; + input t6_; + // Transition Barrier Inputs for input Signals // + input t3__p1_FSM2_TB, t3__p1_FSM4_TB; + input t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p6_FSM4_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p1; + output p7; + + wire p1; + wire p7; + + wire t3__TB_sync; + wire t0__TB_sync; + assign t3__TB_sync = t3_ & t3__p1_FSM2_TB & t3__p1_FSM4_TB; + assign t0__TB_sync = t0_ & t0__p3_FSM1_TB & t0__p9_FSM2_TB & t0__p6_FSM4_TB; + + parameter p1_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p7_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p5_1HOT_ENCODING = 3'd4; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t3__TB_sync or t0__TB_sync or t6_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p1_1HOT_ENCODING: // 3'b001: // + begin + if (t3__TB_sync) + begin + next_state = p5_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 3'b010: // + begin + if (t0__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 3'b100: // + begin + if (t6_) + begin + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_04 ( + clk, + reset, + t3_, t3__p1_FSM2_TB, t3__p1_FSM3_TB, + t0_, t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p7_FSM3_TB, + t5_, + p1, + p6 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t3_; + input t0_; + input t5_; + // Transition Barrier Inputs for input Signals // + input t3__p1_FSM2_TB, t3__p1_FSM3_TB; + input t0__p3_FSM1_TB, t0__p9_FSM2_TB, t0__p7_FSM3_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p1; + output p6; + + wire p1; + wire p6; + + wire t3__TB_sync; + wire t0__TB_sync; + assign t3__TB_sync = t3_ & t3__p1_FSM2_TB & t3__p1_FSM3_TB; + assign t0__TB_sync = t0_ & t0__p3_FSM1_TB & t0__p9_FSM2_TB & t0__p7_FSM3_TB; + + parameter p1_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p6_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p4_1HOT_ENCODING = 3'd4; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t3__TB_sync or t0__TB_sync or t5_) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p1_1HOT_ENCODING: // 3'b001: // + begin + if (t3__TB_sync) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 3'b010: // + begin + if (t0__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 3'b100: // + begin + if (t5_) + begin + next_state = p6_1HOT_ENCODING; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + diff --git a/examples/simple-FC-example_FC/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/simple-FC-example_FC/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..a04f9b7 --- /dev/null +++ b/examples/simple-FC-example_FC/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,75 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + t3, + t2, + t1, + t7, + t0, + t6, + t5, + t4); + + input clk; + input reset; + input t3; + input t2; + input t1; + input t7; + input t0; + input t6; + input t5; + input t4; + + wire p3_FSM1out, p2_FSM1out, p0_FSM1out; // State Synchronisation output signals of FSM1 // + wire p9_FSM2out, p8_FSM2out, p1_FSM2out; // State Synchronisation output signals of FSM2 // + wire p1_FSM3out, p7_FSM3out, p5_FSM3out; // State Synchronisation output signals of FSM3 // + wire p1_FSM4out, p6_FSM4out, p4_FSM4out; // State Synchronisation output signals of FSM4 // + + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .t2_(t2), + .t1_(t1), + .t0_(t0), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p7_FSM3_TB(p7_FSM3out), .t0__p6_FSM4_TB(p6_FSM4out), + .t4_(t4), + .p3(p3_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .t3_(t3), .t3__p1_FSM3_TB(p1_FSM3out), .t3__p1_FSM4_TB(p1_FSM4out), + .t7_(t7), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p7_FSM3_TB(p7_FSM3out), .t0__p6_FSM4_TB(p6_FSM4out), + .p9(p9_FSM2out), + .p1(p1_FSM2out) + ); + + + fsm_mealy_behav_03 fsm_mealy_behav_03_inst ( + .clk(clk), + .reset(reset), + .t3_(t3), .t3__p1_FSM2_TB(p1_FSM2out), .t3__p1_FSM4_TB(p1_FSM4out), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p6_FSM4_TB(p6_FSM4out), + .t6_(t6), + .p1(p1_FSM3out), + .p7(p7_FSM3out) + ); + + + fsm_mealy_behav_04 fsm_mealy_behav_04_inst ( + .clk(clk), + .reset(reset), + .t3_(t3), .t3__p1_FSM2_TB(p1_FSM2out), .t3__p1_FSM3_TB(p1_FSM3out), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p7_FSM3_TB(p7_FSM3out), + .t5_(t5), + .p1(p1_FSM4out), + .p6(p6_FSM4out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/simple-FC-example_FC/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/simple-FC-example_FC/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..bfb87fe --- /dev/null +++ b/examples/simple-FC-example_FC/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,75 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + t3, + t2, + t1, + t7, + t0, + t6, + t5, + t4); + + input clk; + input reset; + input t3; + input t2; + input t1; + input t7; + input t0; + input t6; + input t5; + input t4; + + wire p3_FSM1out, p2_FSM1out, p0_FSM1out; // State Synchronisation output signals of FSM1 // + wire p9_FSM2out, p8_FSM2out, p1_FSM2out; // State Synchronisation output signals of FSM2 // + wire p1_FSM3out, p7_FSM3out, p5_FSM3out; // State Synchronisation output signals of FSM3 // + wire p1_FSM4out, p6_FSM4out, p4_FSM4out; // State Synchronisation output signals of FSM4 // + + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .t2_(t2), + .t1_(t1), + .t0_(t0), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p7_FSM3_TB(p7_FSM3out), .t0__p6_FSM4_TB(p6_FSM4out), + .t4_(t4), + .p3(p3_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .t3_(t3), .t3__p1_FSM3_TB(p1_FSM3out), .t3__p1_FSM4_TB(p1_FSM4out), + .t7_(t7), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p7_FSM3_TB(p7_FSM3out), .t0__p6_FSM4_TB(p6_FSM4out), + .p9(p9_FSM2out), + .p1(p1_FSM2out) + ); + + + fsm_mealy_synth_03 fsm_mealy_synth_03_inst ( + .clk(clk), + .reset(reset), + .t3_(t3), .t3__p1_FSM2_TB(p1_FSM2out), .t3__p1_FSM4_TB(p1_FSM4out), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p6_FSM4_TB(p6_FSM4out), + .t6_(t6), + .p1(p1_FSM3out), + .p7(p7_FSM3out) + ); + + + fsm_mealy_synth_04 fsm_mealy_synth_04_inst ( + .clk(clk), + .reset(reset), + .t3_(t3), .t3__p1_FSM2_TB(p1_FSM2out), .t3__p1_FSM3_TB(p1_FSM3out), + .t0_(t0), .t0__p3_FSM1_TB(p3_FSM1out), .t0__p9_FSM2_TB(p9_FSM2out), .t0__p7_FSM3_TB(p7_FSM3out), + .t5_(t5), + .p1(p1_FSM4out), + .p6(p6_FSM4out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/simple-FC-example_FC/msfsms_tool_bm.log b/examples/simple-FC-example_FC/msfsms_tool_bm.log new file mode 100644 index 0000000..f538be8 --- /dev/null +++ b/examples/simple-FC-example_FC/msfsms_tool_bm.log @@ -0,0 +1,240 @@ +--------------------------------------------------------------------------- +Benchmark: simple-FC-example_FC/simple-FC-example.petrinet.FC.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/simple-FC-example_FC/simple-FC-example.petrinet.FC.workcraft.g +INFO: Total Nodes : 18 +INFO: Total Transitions : 8 +INFO: Total Places : 10 +INFO: Total Edges : 22 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = p3, Type = Place (is Empty) + Predecessors: t2[3][1], t4[15][0] + Successors: t0[9][0] +PT-Net [0][1]: Label = t3, Type = Transition (is Input) + Predecessors: p1[6][0] + Successors: p4[15][1], p5[12][1], p8[3][2] +PT-Net [0][2]: Label = p9, Type = Place (is Empty) + Predecessors: t7[6][3] + Successors: t0[9][0] +PT-Net [3][0]: Label = p2, Type = Place (is Empty) + Predecessors: t1[6][1] + Successors: t4[15][0] +PT-Net [3][1]: Label = t2, Type = Transition (is Input) + Predecessors: p0[9][1] + Successors: p3[0][0] +PT-Net [3][2]: Label = p8, Type = Place (is Empty) + Predecessors: t3[0][1] + Successors: t7[6][3] +PT-Net [6][0]: Label = p1, Type = Place (is Marked) + Predecessors: t0[9][0] + Successors: t3[0][1] +PT-Net [6][1]: Label = t1, Type = Transition (is Input) + Predecessors: p0[9][1] + Successors: p2[3][0] +PT-Net [6][2]: Label = p7, Type = Place (is Empty) + Predecessors: t6[9][3] + Successors: t0[9][0] +PT-Net [6][3]: Label = t7, Type = Transition (is Input) + Predecessors: p8[3][2] + Successors: p9[0][2] +PT-Net [9][0]: Label = t0, Type = Transition (is Input) + Predecessors: p3[0][0], p6[9][2], p7[6][2], p9[0][2] + Successors: p0[9][1], p1[6][0] +PT-Net [9][1]: Label = p0, Type = Place (is Marked) + Predecessors: t0[9][0] + Successors: t1[6][1], t2[3][1] +PT-Net [9][2]: Label = p6, Type = Place (is Empty) + Predecessors: t5[12][0] + Successors: t0[9][0] +PT-Net [9][3]: Label = t6, Type = Transition (is Input) + Predecessors: p5[12][1] + Successors: p7[6][2] +PT-Net [12][0]: Label = t5, Type = Transition (is Input) + Predecessors: p4[15][1] + Successors: p6[9][2] +PT-Net [12][1]: Label = p5, Type = Place (is Empty) + Predecessors: t3[0][1] + Successors: t6[9][3] +PT-Net [15][0]: Label = t4, Type = Transition (is Input) + Predecessors: p2[3][0] + Successors: p3[0][0] +PT-Net [15][1]: Label = p4, Type = Place (is Empty) + Predecessors: t3[0][1] + Successors: t5[12][0] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #4 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 7, H-collapsed = 'false' *** +SC S-net (1,1): p3[0][0] +SC S-net (1,2): p2[3][0] +SC S-net (1,3): t2[3][1] + Predecessor Place: p0(1,6)[9,1] + Successor Place: p3(1,1)[0,0] +SC S-net (1,4): t1[6][1] + Predecessor Place: p0(1,6)[9,1] + Successor Place: p2(1,2)[3,0] +SC S-net (1,5): t0[9][0] + Predecessor Place: p3(1,1)[0,0] + Successor Place: p0(1,6)[9,1] +SC S-net (1,6): p0[9][1] +SC S-net (1,7): t4[15][0] + Predecessor Place: p2(1,2)[3,0] + Successor Place: p3(1,1)[0,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 6, H-collapsed = 'false' *** +SC S-net (2,1): t3[0][1] + Predecessor Place: p1(2,4)[6,0] + Successor Place: p8(2,3)[3,2] +SC S-net (2,2): p9[0][2] +SC S-net (2,3): p8[3][2] +SC S-net (2,4): p1[6][0] +SC S-net (2,5): t7[6][3] + Predecessor Place: p8(2,3)[3,2] + Successor Place: p9(2,2)[0,2] +SC S-net (2,6): t0[9][0] + Predecessor Place: p9(2,2)[0,2] + Successor Place: p1(2,4)[6,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #3, Total Nodes = 6, H-collapsed = 'false' *** +SC S-net (3,1): t3[0][1] + Predecessor Place: p1(3,2)[6,0] + Successor Place: p5(3,6)[12,1] +SC S-net (3,2): p1[6][0] +SC S-net (3,3): p7[6][2] +SC S-net (3,4): t0[9][0] + Predecessor Place: p7(3,3)[6,2] + Successor Place: p1(3,2)[6,0] +SC S-net (3,5): t6[9][3] + Predecessor Place: p5(3,6)[12,1] + Successor Place: p7(3,3)[6,2] +SC S-net (3,6): p5[12][1] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #4, Total Nodes = 6, H-collapsed = 'false' *** +SC S-net (4,1): t3[0][1] + Predecessor Place: p1(4,2)[6,0] + Successor Place: p4(4,6)[15,1] +SC S-net (4,2): p1[6][0] +SC S-net (4,3): t0[9][0] + Predecessor Place: p6(4,4)[9,2] + Successor Place: p1(4,2)[6,0] +SC S-net (4,4): p6[9][2] +SC S-net (4,5): t5[12][0] + Predecessor Place: p4(4,6)[15,1] + Successor Place: p6(4,4)[9,2] +SC S-net (4,6): p4[15][1] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #3 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #4 (of #4 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 7, H-Collapsed = 'false' *** +FSM (1,1): Label = p3, Type = State (is Initially Inactive) + Successor(s): t0/(0,5) + Predecessor(s): t2/(0,3) t4/(0,7) +FSM (1,2): Label = p2, Type = State (is Initially Inactive) + Successor(s): t4/(0,7) + Predecessor(s): t1/(0,4) +FSM (1,3): Label = t2/, Type = Trans. Function (is Input) + Successor(s): p3(0,1) + Predecessor(s): p0(0,6) +FSM (1,4): Label = t1/, Type = Trans. Function (is Input) + Successor(s): p2(0,2) + Predecessor(s): p0(0,6) +FSM (1,5): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p0(0,6) + Predecessor(s): p3(0,1) +FSM (1,6): Label = p0, Type = State (is Initially Active) + Successor(s): t1/(0,4) t2/(0,3) + Predecessor(s): t0/(0,5) +FSM (1,7): Label = t4/, Type = Trans. Function (is Input) + Successor(s): p3(0,1) + Predecessor(s): p2(0,2) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 6, H-Collapsed = 'false' *** +FSM (2,1): Label = t3/, Type = Trans. Function (is Input) + Successor(s): p8(1,3) + Predecessor(s): p1(1,4) +FSM (2,2): Label = p9, Type = State (is Initially Inactive) + Successor(s): t0/(1,6) + Predecessor(s): t7/(1,5) +FSM (2,3): Label = p8, Type = State (is Initially Inactive) + Successor(s): t7/(1,5) + Predecessor(s): t3/(1,1) +FSM (2,4): Label = p1, Type = State (is Initially Active) + Successor(s): t3/(1,1) + Predecessor(s): t0/(1,6) +FSM (2,5): Label = t7/, Type = Trans. Function (is Input) + Successor(s): p9(1,2) + Predecessor(s): p8(1,3) +FSM (2,6): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p1(1,4) + Predecessor(s): p9(1,2) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 3, Total list Entries = 6, H-Collapsed = 'false' *** +FSM (3,1): Label = t3/, Type = Trans. Function (is Input) + Successor(s): p5(2,6) + Predecessor(s): p1(2,2) +FSM (3,2): Label = p1, Type = State (is Initially Active) + Successor(s): t3/(2,1) + Predecessor(s): t0/(2,4) +FSM (3,3): Label = p7, Type = State (is Initially Inactive) + Successor(s): t0/(2,4) + Predecessor(s): t6/(2,5) +FSM (3,4): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p1(2,2) + Predecessor(s): p7(2,3) +FSM (3,5): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p7(2,3) + Predecessor(s): p5(2,6) +FSM (3,6): Label = p5, Type = State (is Initially Inactive) + Successor(s): t6/(2,5) + Predecessor(s): t3/(2,1) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 4, Total list Entries = 6, H-Collapsed = 'false' *** +FSM (4,1): Label = t3/, Type = Trans. Function (is Input) + Successor(s): p4(3,6) + Predecessor(s): p1(3,2) +FSM (4,2): Label = p1, Type = State (is Initially Active) + Successor(s): t3/(3,1) + Predecessor(s): t0/(3,3) +FSM (4,3): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p1(3,2) + Predecessor(s): p6(3,4) +FSM (4,4): Label = p6, Type = State (is Initially Inactive) + Successor(s): t0/(3,3) + Predecessor(s): t5/(3,5) +FSM (4,5): Label = t5/, Type = Trans. Function (is Input) + Successor(s): p6(3,4) + Predecessor(s): p4(3,6) +FSM (4,6): Label = p4, Type = State (is Initially Inactive) + Successor(s): t5/(3,5) + Predecessor(s): t3/(3,1) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/Basic-FC-v03-PTnet/Basic-FC-v03-PTnet.g b/examples/simple-FC-example_FC/simple-FC-example.petrinet.FC.workcraft.g similarity index 64% rename from examples/Basic-FC-v03-PTnet/Basic-FC-v03-PTnet.g rename to examples/simple-FC-example_FC/simple-FC-example.petrinet.FC.workcraft.g index 6ccdb42..819c649 100644 --- a/examples/Basic-FC-v03-PTnet/Basic-FC-v03-PTnet.g +++ b/examples/simple-FC-example_FC/simple-FC-example.petrinet.FC.workcraft.g @@ -1,22 +1,24 @@ # STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.0 -.model Untitled -.inputs t0 t1 t2 t5 t6 t3 t7 -.outputs t4 +.model simpleFC +.dummy t0 t1 t2 t4 t5 t6 t3 t7 .graph t0 p0 p1 t1 p2 t2 p3 t4 p3 t5 p6 -t6 p6 -t3 p4 -t7 p5 +t6 p7 +t3 p4 p5 p8 +t7 p9 p0 t1 t2 -p1 t3 t7 +p1 t3 p2 t4 p3 t0 p4 t5 p5 t6 p6 t0 +p7 t0 +p8 t7 +p9 t0 .marking {p0 p1} .end diff --git a/examples/testcases.txt b/examples/testcases.txt new file mode 100644 index 0000000..814c553 --- /dev/null +++ b/examples/testcases.txt @@ -0,0 +1,10 @@ +5-dining-philosophers_GN/5-dining-philosophers.petrinet.GN.workcraft.g +and-gate_GN/and-gate.petrinet.GN.workcraft.g +converta_MG/converta.petrinet.MG.workcraft.g +half_MG/half.petrinet.MG.workcraft.g +nowick_MG/nowick.petrinet.MG.workcraft.g +simple-EFC-example_EFC/simple-EFC-example.petrinet.EFC.workcraft.g +simple-FC-example_FC/simple-FC-example.petrinet.FC.workcraft.g +toggle_AC/toggle.petrinet.AC.workcraft.g +vem_AC/vem.petrinet.AC.workcraft.g +xor-gate_GN/xor-gate.pterinet.GN.workcraft.g diff --git a/examples/toggle/script.tcl b/examples/toggle/script.tcl deleted file mode 100644 index 9745316..0000000 --- a/examples/toggle/script.tcl +++ /dev/null @@ -1,6 +0,0 @@ -read_graph -format work toggle.work -get_scover -fsm_collapsing -sync_fsm -write_fsms_to_petrify_format -format sg -multiplefiles 1 -quit diff --git a/examples/toggle/toggle.png b/examples/toggle/toggle.png deleted file mode 100644 index 1f28c5b..0000000 Binary files a/examples/toggle/toggle.png and /dev/null differ diff --git a/examples/toggle/toggle.work b/examples/toggle/toggle.work deleted file mode 100644 index 423cb3c..0000000 Binary files a/examples/toggle/toggle.work and /dev/null differ diff --git a/examples/toggle_AC/AsyncMSFSMs/fsm_afsm.afsm b/examples/toggle_AC/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..fbfdeb8 --- /dev/null +++ b/examples/toggle_AC/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,61 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p0: Ri_MINUS_ Ri_MINUS__p4_FSM2_TB Ri_MINUS__p0_FSM3_TB Ri_MINUS__p4_FSM4_TB Ri_MINUS__p0_FSM5_TB Ri_MINUS__p0_FSM6_TB Ri_MINUS__p4_FSM7_TB p1 +p1*: Ri_PLUS_ Ri_PLUS__p1_FSM2_TB Ri_PLUS__p7_FSM3_TB Ri_PLUS__p1_FSM4_TB Ri_PLUS__p7_FSM5_TB Ri_PLUS__p7_FSM6_TB Ri_PLUS__p1_FSM7_TB p0 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p1*: Ri_PLUS_ Ri_PLUS__p1_FSM1_TB Ri_PLUS__p7_FSM3_TB Ri_PLUS__p1_FSM4_TB Ri_PLUS__p7_FSM5_TB Ri_PLUS__p7_FSM6_TB Ri_PLUS__p1_FSM7_TB p2 +p2: e_Ro1_MINUS e_Ro1_MINUS_p5_FSM4_TB e_Ro1_MINUS_p2_FSM7_TB p4 +p2: e_Ro1_PLUS e_Ro1_PLUS_p2_FSM4_TB e_Ro1_PLUS_p9_FSM7_TB p4 +p4: Ri_MINUS_ Ri_MINUS__p0_FSM1_TB Ri_MINUS__p0_FSM3_TB Ri_MINUS__p4_FSM4_TB Ri_MINUS__p0_FSM5_TB Ri_MINUS__p0_FSM6_TB Ri_MINUS__p4_FSM7_TB p1 +### End of FSM #02 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#03 Declaration ### +p0: Ri_MINUS_ Ri_MINUS__p0_FSM1_TB Ri_MINUS__p4_FSM2_TB Ri_MINUS__p4_FSM4_TB Ri_MINUS__p0_FSM5_TB Ri_MINUS__p0_FSM6_TB Ri_MINUS__p4_FSM7_TB p3 +p3: e_Ro2_MINUS e_Ro2_MINUS_p6_FSM5_TB e_Ro2_MINUS_p3_FSM6_TB p7 +p3: e_Ro2_PLUS e_Ro2_PLUS_p3_FSM5_TB e_Ro2_PLUS_p8_FSM6_TB p7 +p7*: Ri_PLUS_ Ri_PLUS__p1_FSM1_TB Ri_PLUS__p1_FSM2_TB Ri_PLUS__p1_FSM4_TB Ri_PLUS__p7_FSM5_TB Ri_PLUS__p7_FSM6_TB Ri_PLUS__p1_FSM7_TB p0 +### End of FSM #03 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#04 Declaration ### +p1*: Ri_PLUS_ Ri_PLUS__p1_FSM1_TB Ri_PLUS__p1_FSM2_TB Ri_PLUS__p7_FSM3_TB Ri_PLUS__p7_FSM5_TB Ri_PLUS__p7_FSM6_TB Ri_PLUS__p1_FSM7_TB p2 +p2: e_Ro1_PLUS e_Ro1_PLUS_p2_FSM2_TB e_Ro1_PLUS_p9_FSM7_TB p5 +p4: Ri_MINUS_ Ri_MINUS__p0_FSM1_TB Ri_MINUS__p4_FSM2_TB Ri_MINUS__p0_FSM3_TB Ri_MINUS__p0_FSM5_TB Ri_MINUS__p0_FSM6_TB Ri_MINUS__p4_FSM7_TB p1 +p5: e_Ro1_MINUS e_Ro1_MINUS_p2_FSM2_TB e_Ro1_MINUS_p2_FSM7_TB p4 +### End of FSM #04 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#05 Declaration ### +p0: Ri_MINUS_ Ri_MINUS__p0_FSM1_TB Ri_MINUS__p4_FSM2_TB Ri_MINUS__p0_FSM3_TB Ri_MINUS__p4_FSM4_TB Ri_MINUS__p0_FSM6_TB Ri_MINUS__p4_FSM7_TB p3 +p3: e_Ro2_PLUS e_Ro2_PLUS_p3_FSM3_TB e_Ro2_PLUS_p8_FSM6_TB p6 +p6: e_Ro2_MINUS e_Ro2_MINUS_p3_FSM3_TB e_Ro2_MINUS_p3_FSM6_TB p7 +p7*: Ri_PLUS_ Ri_PLUS__p1_FSM1_TB Ri_PLUS__p1_FSM2_TB Ri_PLUS__p7_FSM3_TB Ri_PLUS__p1_FSM4_TB Ri_PLUS__p7_FSM6_TB Ri_PLUS__p1_FSM7_TB p0 +### End of FSM #05 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#06 Declaration ### +p0: Ri_MINUS_ Ri_MINUS__p0_FSM1_TB Ri_MINUS__p4_FSM2_TB Ri_MINUS__p0_FSM3_TB Ri_MINUS__p4_FSM4_TB Ri_MINUS__p0_FSM5_TB Ri_MINUS__p4_FSM7_TB p3 +p3: e_Ro2_MINUS e_Ro2_MINUS_p3_FSM3_TB e_Ro2_MINUS_p6_FSM5_TB p8 +p7*: Ri_PLUS_ Ri_PLUS__p1_FSM1_TB Ri_PLUS__p1_FSM2_TB Ri_PLUS__p7_FSM3_TB Ri_PLUS__p1_FSM4_TB Ri_PLUS__p7_FSM5_TB Ri_PLUS__p1_FSM7_TB p0 +p8*: e_Ro2_PLUS e_Ro2_PLUS_p3_FSM3_TB e_Ro2_PLUS_p3_FSM5_TB p7 +### End of FSM #06 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#07 Declaration ### +p1*: Ri_PLUS_ Ri_PLUS__p1_FSM1_TB Ri_PLUS__p1_FSM2_TB Ri_PLUS__p7_FSM3_TB Ri_PLUS__p1_FSM4_TB Ri_PLUS__p7_FSM5_TB Ri_PLUS__p7_FSM6_TB p2 +p2: e_Ro1_MINUS e_Ro1_MINUS_p2_FSM2_TB e_Ro1_MINUS_p5_FSM4_TB p9 +p4: Ri_MINUS_ Ri_MINUS__p0_FSM1_TB Ri_MINUS__p4_FSM2_TB Ri_MINUS__p0_FSM3_TB Ri_MINUS__p4_FSM4_TB Ri_MINUS__p0_FSM5_TB Ri_MINUS__p0_FSM6_TB p1 +p9*: e_Ro1_PLUS e_Ro1_PLUS_p2_FSM2_TB e_Ro1_PLUS_p2_FSM4_TB p4 +### End of FSM #07 Declaration ### + diff --git a/examples/toggle_AC/AsyncMSFSMs/msfsms_afsm.v b/examples/toggle_AC/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..7a8b91a --- /dev/null +++ b/examples/toggle_AC/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,127 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + Ro1_MINUS, + Ri_PLUS, + Ro2_MINUS, + Ro1_PLUS, + Ri_MINUS, + Ro2_PLUS); + + input reset; + output Ro1_MINUS; + input Ri_PLUS; + output Ro2_MINUS; + output Ro1_PLUS; + input Ri_MINUS; + output Ro2_PLUS; + + wire p0_FSM1out, p1_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_Ro1_MINUS_FSM2out, e_Ro1_PLUS_FSM2out; // Regular output signals of FSM2 // + wire p1_FSM2out, p2_FSM2out, p4_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_Ro2_MINUS_FSM3out, e_Ro2_PLUS_FSM3out; // Regular output signals of FSM3 // + wire p0_FSM3out, p3_FSM3out, p7_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_Ro1_MINUS_FSM4out, e_Ro1_PLUS_FSM4out; // Regular output signals of FSM4 // + wire p1_FSM4out, p2_FSM4out, p4_FSM4out, p5_FSM4out; // State Synchronisation output signals of FSM4 // + wire e_Ro2_MINUS_FSM5out, e_Ro2_PLUS_FSM5out; // Regular output signals of FSM5 // + wire p0_FSM5out, p3_FSM5out, p6_FSM5out, p7_FSM5out; // State Synchronisation output signals of FSM5 // + wire e_Ro2_MINUS_FSM6out, e_Ro2_PLUS_FSM6out; // Regular output signals of FSM6 // + wire p0_FSM6out, p3_FSM6out, p7_FSM6out, p8_FSM6out; // State Synchronisation output signals of FSM6 // + wire e_Ro1_MINUS_FSM7out, e_Ro1_PLUS_FSM7out; // Regular output signals of FSM7 // + wire p1_FSM7out, p2_FSM7out, p4_FSM7out, p9_FSM7out; // State Synchronisation output signals of FSM7 // + + assign Ro1_MINUS = e_Ro1_MINUS_FSM2out & e_Ro1_MINUS_FSM4out & e_Ro1_MINUS_FSM7out; + assign Ro2_MINUS = e_Ro2_MINUS_FSM3out & e_Ro2_MINUS_FSM5out & e_Ro2_MINUS_FSM6out; + assign Ro1_PLUS = e_Ro1_PLUS_FSM2out & e_Ro1_PLUS_FSM4out & e_Ro1_PLUS_FSM7out; + assign Ro2_PLUS = e_Ro2_PLUS_FSM3out & e_Ro2_PLUS_FSM5out & e_Ro2_PLUS_FSM6out; + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro1_MINUS(p2_FSM2out), .e_Ro1_MINUS_p5_FSM4_TB(p5_FSM4out), .e_Ro1_MINUS_p2_FSM7_TB(p2_FSM7out), + .e_Ro1_PLUS(p2_FSM2out), .e_Ro1_PLUS_p2_FSM4_TB(p2_FSM4out), .e_Ro1_PLUS_p9_FSM7_TB(p9_FSM7out), + .e/Ro1_MINUS(e/Ro1_MINUS_FSM2out), + .e/Ro1_PLUS(e/Ro1_PLUS_FSM2out) + ); + + + fsm_afsm_03 fsm_afsm_03_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(p3_FSM3out), .e_Ro2_MINUS_p6_FSM5_TB(p6_FSM5out), .e_Ro2_MINUS_p3_FSM6_TB(p3_FSM6out), + .e_Ro2_PLUS(p3_FSM3out), .e_Ro2_PLUS_p3_FSM5_TB(p3_FSM5out), .e_Ro2_PLUS_p8_FSM6_TB(p8_FSM6out), + .e/Ro2_MINUS(e/Ro2_MINUS_FSM3out), + .e/Ro2_PLUS(e/Ro2_PLUS_FSM3out) + ); + + + fsm_afsm_04 fsm_afsm_04_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro1_MINUS(p5_FSM4out), .e_Ro1_MINUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_MINUS_p2_FSM7_TB(p2_FSM7out), + .e_Ro1_PLUS(p2_FSM4out), .e_Ro1_PLUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_PLUS_p9_FSM7_TB(p9_FSM7out), + .e/Ro1_MINUS(e/Ro1_MINUS_FSM4out), + .e/Ro1_PLUS(e/Ro1_PLUS_FSM4out) + ); + + + fsm_afsm_05 fsm_afsm_05_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(p6_FSM5out), .e_Ro2_MINUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_MINUS_p3_FSM6_TB(p3_FSM6out), + .e_Ro2_PLUS(p3_FSM5out), .e_Ro2_PLUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_PLUS_p8_FSM6_TB(p8_FSM6out), + .e/Ro2_MINUS(e/Ro2_MINUS_FSM5out), + .e/Ro2_PLUS(e/Ro2_PLUS_FSM5out) + ); + + + fsm_afsm_06 fsm_afsm_06_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(p3_FSM6out), .e_Ro2_MINUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_MINUS_p6_FSM5_TB(p6_FSM5out), + .e_Ro2_PLUS(p8_FSM6out), .e_Ro2_PLUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_PLUS_p3_FSM5_TB(p3_FSM5out), + .e/Ro2_MINUS(e/Ro2_MINUS_FSM6out), + .e/Ro2_PLUS(e/Ro2_PLUS_FSM6out) + ); + + + fsm_afsm_07 fsm_afsm_07_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), + .e_Ro1_MINUS(p2_FSM7out), .e_Ro1_MINUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_MINUS_p5_FSM4_TB(p5_FSM4out), + .e_Ro1_PLUS(p9_FSM7out), .e_Ro1_PLUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_PLUS_p2_FSM4_TB(p2_FSM4out), + .e/Ro1_MINUS(e/Ro1_MINUS_FSM7out), + .e/Ro1_PLUS(e/Ro1_PLUS_FSM7out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/toggle_AC/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/toggle_AC/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..1405afd --- /dev/null +++ b/examples/toggle_AC/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,950 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + p0, + p1 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p0; + output p1; + + wire p0; + wire p1; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + + parameter p0_1HOT_ENCODING = 2'd1; // 2'b01 // + parameter p0_1HOT_CASEX_ENCODING = 2'bx1; // 2'b01 // + parameter p1_1HOT_ENCODING = 2'd2; // 2'b10 // + parameter p1_1HOT_CASEX_ENCODING = 2'b1x; // 2'b10 // + + reg [1 : 0] state; + reg [1 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + casex (state) + 2'bx1: // p0_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[1] = 1'b1; + end + end + + 2'b1x: // p1_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + default: + begin + next_state = 2'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro1_MINUS, e_Ro1_MINUS_p5_FSM4_TB, e_Ro1_MINUS_p2_FSM7_TB, + e_Ro1_PLUS, e_Ro1_PLUS_p2_FSM4_TB, e_Ro1_PLUS_p9_FSM7_TB, + p1, + p2, + p4 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro1_MINUS; + output e_Ro1_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro1_MINUS_p5_FSM4_TB, e_Ro1_MINUS_p2_FSM7_TB; + input e_Ro1_PLUS_p2_FSM4_TB, e_Ro1_PLUS_p9_FSM7_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p2; + output p4; + + reg e_Ro1_MINUS; + reg e_Ro1_PLUS; + wire p1; + wire p2; + wire p4; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro1_MINUS_TB_sync; + wire e_Ro1_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro1_MINUS_TB_sync = e_Ro1_MINUS_p5_FSM4_TB & e_Ro1_MINUS_p2_FSM7_TB; + assign e_Ro1_PLUS_TB_sync = e_Ro1_PLUS_p2_FSM4_TB & e_Ro1_PLUS_p9_FSM7_TB; + + parameter p1_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p1_1HOT_CASEX_ENCODING = 3'bxx1; // 3'b001 // + parameter p2_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p2_1HOT_CASEX_ENCODING = 3'bx1x; // 3'b010 // + parameter p4_1HOT_ENCODING = 3'd4; // 3'b100 // + parameter p4_1HOT_CASEX_ENCODING = 3'b1xx; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro1_MINUS_TB_sync or e_Ro1_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro1_MINUS = 1'b0; + e_Ro1_PLUS = 1'b0; + + casex (state) + 3'bxx1: // p1_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[1] = 1'b1; + end + end + + 3'bx1x: // p2_1HOT_ENCODING: // + begin + if (e_Ro1_MINUS_TB_sync) + begin + e_Ro1_MINUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + else if (e_Ro1_PLUS_TB_sync) + begin + e_Ro1_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + end + + 3'b1xx: // p4_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_03 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro2_MINUS, e_Ro2_MINUS_p6_FSM5_TB, e_Ro2_MINUS_p3_FSM6_TB, + e_Ro2_PLUS, e_Ro2_PLUS_p3_FSM5_TB, e_Ro2_PLUS_p8_FSM6_TB, + p0, + p3, + p7 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro2_MINUS; + output e_Ro2_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro2_MINUS_p6_FSM5_TB, e_Ro2_MINUS_p3_FSM6_TB; + input e_Ro2_PLUS_p3_FSM5_TB, e_Ro2_PLUS_p8_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p0; + output p3; + output p7; + + reg e_Ro2_MINUS; + reg e_Ro2_PLUS; + wire p0; + wire p3; + wire p7; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro2_MINUS_TB_sync; + wire e_Ro2_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro2_MINUS_TB_sync = e_Ro2_MINUS_p6_FSM5_TB & e_Ro2_MINUS_p3_FSM6_TB; + assign e_Ro2_PLUS_TB_sync = e_Ro2_PLUS_p3_FSM5_TB & e_Ro2_PLUS_p8_FSM6_TB; + + parameter p0_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p0_1HOT_CASEX_ENCODING = 3'bxx1; // 3'b001 // + parameter p3_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p3_1HOT_CASEX_ENCODING = 3'bx1x; // 3'b010 // + parameter p7_1HOT_ENCODING = 3'd4; // 3'b100 // + parameter p7_1HOT_CASEX_ENCODING = 3'b1xx; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p7_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro2_MINUS_TB_sync or e_Ro2_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro2_MINUS = 1'b0; + e_Ro2_PLUS = 1'b0; + + casex (state) + 3'bxx1: // p0_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[1] = 1'b1; + end + end + + 3'bx1x: // p3_1HOT_ENCODING: // + begin + if (e_Ro2_MINUS_TB_sync) + begin + e_Ro2_MINUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + else if (e_Ro2_PLUS_TB_sync) + begin + e_Ro2_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + end + + 3'b1xx: // p7_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_04 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro1_MINUS, e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p2_FSM7_TB, + e_Ro1_PLUS, e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p9_FSM7_TB, + p1, + p2, + p4, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro1_MINUS; + output e_Ro1_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p2_FSM7_TB; + input e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p9_FSM7_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p2; + output p4; + output p5; + + reg e_Ro1_MINUS; + reg e_Ro1_PLUS; + wire p1; + wire p2; + wire p4; + wire p5; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro1_MINUS_TB_sync; + wire e_Ro1_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro1_MINUS_TB_sync = e_Ro1_MINUS_p2_FSM2_TB & e_Ro1_MINUS_p2_FSM7_TB; + assign e_Ro1_PLUS_TB_sync = e_Ro1_PLUS_p2_FSM2_TB & e_Ro1_PLUS_p9_FSM7_TB; + + parameter p1_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p1_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p2_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p2_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p4_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p4_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p5_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p5_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro1_MINUS_TB_sync or e_Ro1_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro1_MINUS = 1'b0; + e_Ro1_PLUS = 1'b0; + + casex (state) + 4'bxxx1: // p1_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[1] = 1'b1; + end + end + + 4'bxx1x: // p2_1HOT_ENCODING: // + begin + if (e_Ro1_PLUS_TB_sync) + begin + e_Ro1_PLUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bx1xx: // p4_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'b1xxx: // p5_1HOT_ENCODING: // + begin + if (e_Ro1_MINUS_TB_sync) + begin + e_Ro1_MINUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_05 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro2_MINUS, e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p3_FSM6_TB, + e_Ro2_PLUS, e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p8_FSM6_TB, + p0, + p3, + p6, + p7 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro2_MINUS; + output e_Ro2_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p3_FSM6_TB; + input e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p8_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p0; + output p3; + output p6; + output p7; + + reg e_Ro2_MINUS; + reg e_Ro2_PLUS; + wire p0; + wire p3; + wire p6; + wire p7; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro2_MINUS_TB_sync; + wire e_Ro2_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro2_MINUS_TB_sync = e_Ro2_MINUS_p3_FSM3_TB & e_Ro2_MINUS_p3_FSM6_TB; + assign e_Ro2_PLUS_TB_sync = e_Ro2_PLUS_p3_FSM3_TB & e_Ro2_PLUS_p8_FSM6_TB; + + parameter p0_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p0_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p3_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p6_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p6_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p7_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p7_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p7_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro2_MINUS_TB_sync or e_Ro2_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro2_MINUS = 1'b0; + e_Ro2_PLUS = 1'b0; + + casex (state) + 4'bxxx1: // p0_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[1] = 1'b1; + end + end + + 4'bxx1x: // p3_1HOT_ENCODING: // + begin + if (e_Ro2_PLUS_TB_sync) + begin + e_Ro2_PLUS = 1'b1; + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[2] = 1'b1; + end + end + + 4'bx1xx: // p6_1HOT_ENCODING: // + begin + if (e_Ro2_MINUS_TB_sync) + begin + e_Ro2_MINUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'b1xxx: // p7_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[0] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_06 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro2_MINUS, e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p6_FSM5_TB, + e_Ro2_PLUS, e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p3_FSM5_TB, + p0, + p3, + p7, + p8 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro2_MINUS; + output e_Ro2_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p6_FSM5_TB; + input e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p3_FSM5_TB; + + // FSMs' Synchronisation output Signals // + output p0; + output p3; + output p7; + output p8; + + reg e_Ro2_MINUS; + reg e_Ro2_PLUS; + wire p0; + wire p3; + wire p7; + wire p8; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro2_MINUS_TB_sync; + wire e_Ro2_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro2_MINUS_TB_sync = e_Ro2_MINUS_p3_FSM3_TB & e_Ro2_MINUS_p6_FSM5_TB; + assign e_Ro2_PLUS_TB_sync = e_Ro2_PLUS_p3_FSM3_TB & e_Ro2_PLUS_p3_FSM5_TB; + + parameter p0_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p0_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p3_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p7_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p7_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p8_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p8_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p7_1HOT_ENCODING; + // state <= p8_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + state[3] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro2_MINUS_TB_sync or e_Ro2_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro2_MINUS = 1'b0; + e_Ro2_PLUS = 1'b0; + + casex (state) + 4'bxxx1: // p0_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[1] = 1'b1; + end + end + + 4'bxx1x: // p3_1HOT_ENCODING: // + begin + if (e_Ro2_MINUS_TB_sync) + begin + e_Ro2_MINUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bx1xx: // p7_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'b1xxx: // p8_1HOT_ENCODING: // + begin + if (e_Ro2_PLUS_TB_sync) + begin + e_Ro2_PLUS = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_07 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, + e_Ro1_MINUS, e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p5_FSM4_TB, + e_Ro1_PLUS, e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p2_FSM4_TB, + p1, + p2, + p4, + p9 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB; + + // Regular output Signals // + output e_Ro1_MINUS; + output e_Ro1_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p5_FSM4_TB; + input e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p2_FSM4_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p2; + output p4; + output p9; + + reg e_Ro1_MINUS; + reg e_Ro1_PLUS; + wire p1; + wire p2; + wire p4; + wire p9; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro1_MINUS_TB_sync; + wire e_Ro1_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB; + assign e_Ro1_MINUS_TB_sync = e_Ro1_MINUS_p2_FSM2_TB & e_Ro1_MINUS_p5_FSM4_TB; + assign e_Ro1_PLUS_TB_sync = e_Ro1_PLUS_p2_FSM2_TB & e_Ro1_PLUS_p2_FSM4_TB; + + parameter p1_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p1_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p2_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p2_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p4_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p4_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p9_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p9_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + // state <= p9_1HOT_ENCODING; + state[0] <= 1'b1; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro1_MINUS_TB_sync or e_Ro1_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro1_MINUS = 1'b0; + e_Ro1_PLUS = 1'b0; + + casex (state) + 4'bxxx1: // p1_1HOT_ENCODING: // + begin + if (Ri_PLUS__TB_sync) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[1] = 1'b1; + end + end + + 4'bxx1x: // p2_1HOT_ENCODING: // + begin + if (e_Ro1_MINUS_TB_sync) + begin + e_Ro1_MINUS = 1'b1; + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bx1xx: // p4_1HOT_ENCODING: // + begin + if (Ri_MINUS__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'b1xxx: // p9_1HOT_ENCODING: // + begin + if (e_Ro1_PLUS_TB_sync) + begin + e_Ro1_PLUS = 1'b1; + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + diff --git a/examples/toggle_AC/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/toggle_AC/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..fa9d021 --- /dev/null +++ b/examples/toggle_AC/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,850 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + p0, + p1 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + // === EMPTY! === // + // Transition Barrier outputs for output Signals // + // === EMPTY! === // + + // FSMs' Synchronisation output Signals // + output p0; + output p1; + + wire p0; + wire p1; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + + parameter p0_1HOT_ENCODING = 2'd1; // 2'b01 // + parameter p1_1HOT_ENCODING = 2'd2; // 2'b10 // + + reg [1 : 0] state; + reg [1 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + // Empty output Events! // + + case (state) + p0_1HOT_ENCODING: // 2'b01: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 2'b10: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + default: + begin + next_state = 2'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro1_MINUS, e_Ro1_MINUS_p5_FSM4_TB, e_Ro1_MINUS_p2_FSM7_TB, + e_Ro1_PLUS, e_Ro1_PLUS_p2_FSM4_TB, e_Ro1_PLUS_p9_FSM7_TB, + p1, + p2, + p4 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro1_MINUS; + output e_Ro1_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro1_MINUS_p5_FSM4_TB, e_Ro1_MINUS_p2_FSM7_TB; + input e_Ro1_PLUS_p2_FSM4_TB, e_Ro1_PLUS_p9_FSM7_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p2; + output p4; + + reg e_Ro1_MINUS; + reg e_Ro1_PLUS; + wire p1; + wire p2; + wire p4; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro1_MINUS_TB_sync; + wire e_Ro1_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro1_MINUS_TB_sync = e_Ro1_MINUS_p5_FSM4_TB & e_Ro1_MINUS_p2_FSM7_TB; + assign e_Ro1_PLUS_TB_sync = e_Ro1_PLUS_p2_FSM4_TB & e_Ro1_PLUS_p9_FSM7_TB; + + parameter p1_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p2_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p4_1HOT_ENCODING = 3'd4; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro1_MINUS_TB_sync or e_Ro1_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro1_MINUS = 1'b0; + e_Ro1_PLUS = 1'b0; + + case (state) + p1_1HOT_ENCODING: // 3'b001: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 3'b010: // + begin + if (e_Ro1_MINUS_TB_sync) + begin + e_Ro1_MINUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + else if (e_Ro1_PLUS_TB_sync) + begin + e_Ro1_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 3'b100: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_03 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro2_MINUS, e_Ro2_MINUS_p6_FSM5_TB, e_Ro2_MINUS_p3_FSM6_TB, + e_Ro2_PLUS, e_Ro2_PLUS_p3_FSM5_TB, e_Ro2_PLUS_p8_FSM6_TB, + p0, + p3, + p7 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro2_MINUS; + output e_Ro2_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro2_MINUS_p6_FSM5_TB, e_Ro2_MINUS_p3_FSM6_TB; + input e_Ro2_PLUS_p3_FSM5_TB, e_Ro2_PLUS_p8_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p0; + output p3; + output p7; + + reg e_Ro2_MINUS; + reg e_Ro2_PLUS; + wire p0; + wire p3; + wire p7; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro2_MINUS_TB_sync; + wire e_Ro2_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro2_MINUS_TB_sync = e_Ro2_MINUS_p6_FSM5_TB & e_Ro2_MINUS_p3_FSM6_TB; + assign e_Ro2_PLUS_TB_sync = e_Ro2_PLUS_p3_FSM5_TB & e_Ro2_PLUS_p8_FSM6_TB; + + parameter p0_1HOT_ENCODING = 3'd1; // 3'b001 // + parameter p3_1HOT_ENCODING = 3'd2; // 3'b010 // + parameter p7_1HOT_ENCODING = 3'd4; // 3'b100 // + + reg [2 : 0] state; + reg [2 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p7_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro2_MINUS_TB_sync or e_Ro2_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro2_MINUS = 1'b0; + e_Ro2_PLUS = 1'b0; + + case (state) + p0_1HOT_ENCODING: // 3'b001: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 3'b010: // + begin + if (e_Ro2_MINUS_TB_sync) + begin + e_Ro2_MINUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + else if (e_Ro2_PLUS_TB_sync) + begin + e_Ro2_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 3'b100: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + default: + begin + next_state = 3'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_04 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro1_MINUS, e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p2_FSM7_TB, + e_Ro1_PLUS, e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p9_FSM7_TB, + p1, + p2, + p4, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro1_MINUS; + output e_Ro1_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p2_FSM7_TB; + input e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p9_FSM7_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p2; + output p4; + output p5; + + reg e_Ro1_MINUS; + reg e_Ro1_PLUS; + wire p1; + wire p2; + wire p4; + wire p5; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro1_MINUS_TB_sync; + wire e_Ro1_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro1_MINUS_TB_sync = e_Ro1_MINUS_p2_FSM2_TB & e_Ro1_MINUS_p2_FSM7_TB; + assign e_Ro1_PLUS_TB_sync = e_Ro1_PLUS_p2_FSM2_TB & e_Ro1_PLUS_p9_FSM7_TB; + + parameter p1_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p2_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p4_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p5_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro1_MINUS_TB_sync or e_Ro1_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro1_MINUS = 1'b0; + e_Ro1_PLUS = 1'b0; + + case (state) + p1_1HOT_ENCODING: // 4'b0001: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 4'b0010: // + begin + if (e_Ro1_PLUS_TB_sync) + begin + e_Ro1_PLUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 4'b0100: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 4'b1000: // + begin + if (e_Ro1_MINUS_TB_sync) + begin + e_Ro1_MINUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_05 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro2_MINUS, e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p3_FSM6_TB, + e_Ro2_PLUS, e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p8_FSM6_TB, + p0, + p3, + p6, + p7 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM6_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM6_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro2_MINUS; + output e_Ro2_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p3_FSM6_TB; + input e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p8_FSM6_TB; + + // FSMs' Synchronisation output Signals // + output p0; + output p3; + output p6; + output p7; + + reg e_Ro2_MINUS; + reg e_Ro2_PLUS; + wire p0; + wire p3; + wire p6; + wire p7; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro2_MINUS_TB_sync; + wire e_Ro2_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM6_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM6_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro2_MINUS_TB_sync = e_Ro2_MINUS_p3_FSM3_TB & e_Ro2_MINUS_p3_FSM6_TB; + assign e_Ro2_PLUS_TB_sync = e_Ro2_PLUS_p3_FSM3_TB & e_Ro2_PLUS_p8_FSM6_TB; + + parameter p0_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p6_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p7_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p7_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro2_MINUS_TB_sync or e_Ro2_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro2_MINUS = 1'b0; + e_Ro2_PLUS = 1'b0; + + case (state) + p0_1HOT_ENCODING: // 4'b0001: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 4'b0010: // + begin + if (e_Ro2_PLUS_TB_sync) + begin + e_Ro2_PLUS = 1'b1; + next_state = p6_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 4'b0100: // + begin + if (e_Ro2_MINUS_TB_sync) + begin + e_Ro2_MINUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 4'b1000: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_06 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p1_FSM7_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p4_FSM7_TB, + e_Ro2_MINUS, e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p6_FSM5_TB, + e_Ro2_PLUS, e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p3_FSM5_TB, + p0, + p3, + p7, + p8 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p1_FSM7_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p4_FSM7_TB; + + // Regular output Signals // + output e_Ro2_MINUS; + output e_Ro2_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro2_MINUS_p3_FSM3_TB, e_Ro2_MINUS_p6_FSM5_TB; + input e_Ro2_PLUS_p3_FSM3_TB, e_Ro2_PLUS_p3_FSM5_TB; + + // FSMs' Synchronisation output Signals // + output p0; + output p3; + output p7; + output p8; + + reg e_Ro2_MINUS; + reg e_Ro2_PLUS; + wire p0; + wire p3; + wire p7; + wire p8; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro2_MINUS_TB_sync; + wire e_Ro2_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p1_FSM7_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p4_FSM7_TB; + assign e_Ro2_MINUS_TB_sync = e_Ro2_MINUS_p3_FSM3_TB & e_Ro2_MINUS_p6_FSM5_TB; + assign e_Ro2_PLUS_TB_sync = e_Ro2_PLUS_p3_FSM3_TB & e_Ro2_PLUS_p3_FSM5_TB; + + parameter p0_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p7_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p8_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p7_1HOT_ENCODING; + state <= p8_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro2_MINUS_TB_sync or e_Ro2_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro2_MINUS = 1'b0; + e_Ro2_PLUS = 1'b0; + + case (state) + p0_1HOT_ENCODING: // 4'b0001: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 4'b0010: // + begin + if (e_Ro2_MINUS_TB_sync) + begin + e_Ro2_MINUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 4'b0100: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 4'b1000: // + begin + if (e_Ro2_PLUS_TB_sync) + begin + e_Ro2_PLUS = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_07 ( + clk, + reset, + Ri_PLUS_, Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB, + Ri_MINUS_, Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB, + e_Ro1_MINUS, e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p5_FSM4_TB, + e_Ro1_PLUS, e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p2_FSM4_TB, + p1, + p2, + p4, + p9 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input Ri_PLUS_; + input Ri_MINUS_; + // Transition Barrier Inputs for input Signals // + input Ri_PLUS__p1_FSM1_TB, Ri_PLUS__p1_FSM2_TB, Ri_PLUS__p7_FSM3_TB, Ri_PLUS__p1_FSM4_TB, Ri_PLUS__p7_FSM5_TB, Ri_PLUS__p7_FSM6_TB; + input Ri_MINUS__p0_FSM1_TB, Ri_MINUS__p4_FSM2_TB, Ri_MINUS__p0_FSM3_TB, Ri_MINUS__p4_FSM4_TB, Ri_MINUS__p0_FSM5_TB, Ri_MINUS__p0_FSM6_TB; + + // Regular output Signals // + output e_Ro1_MINUS; + output e_Ro1_PLUS; + // Transition Barrier outputs for output Signals // + input e_Ro1_MINUS_p2_FSM2_TB, e_Ro1_MINUS_p5_FSM4_TB; + input e_Ro1_PLUS_p2_FSM2_TB, e_Ro1_PLUS_p2_FSM4_TB; + + // FSMs' Synchronisation output Signals // + output p1; + output p2; + output p4; + output p9; + + reg e_Ro1_MINUS; + reg e_Ro1_PLUS; + wire p1; + wire p2; + wire p4; + wire p9; + + wire Ri_PLUS__TB_sync; + wire Ri_MINUS__TB_sync; + wire e_Ro1_MINUS_TB_sync; + wire e_Ro1_PLUS_TB_sync; + assign Ri_PLUS__TB_sync = Ri_PLUS_ & Ri_PLUS__p1_FSM1_TB & Ri_PLUS__p1_FSM2_TB & Ri_PLUS__p7_FSM3_TB & Ri_PLUS__p1_FSM4_TB & Ri_PLUS__p7_FSM5_TB & Ri_PLUS__p7_FSM6_TB; + assign Ri_MINUS__TB_sync = Ri_MINUS_ & Ri_MINUS__p0_FSM1_TB & Ri_MINUS__p4_FSM2_TB & Ri_MINUS__p0_FSM3_TB & Ri_MINUS__p4_FSM4_TB & Ri_MINUS__p0_FSM5_TB & Ri_MINUS__p0_FSM6_TB; + assign e_Ro1_MINUS_TB_sync = e_Ro1_MINUS_p2_FSM2_TB & e_Ro1_MINUS_p5_FSM4_TB; + assign e_Ro1_PLUS_TB_sync = e_Ro1_PLUS_p2_FSM2_TB & e_Ro1_PLUS_p2_FSM4_TB; + + parameter p1_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p2_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p4_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p9_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + state <= p9_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p1 = (state == p1_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or Ri_PLUS__TB_sync or Ri_MINUS__TB_sync or e_Ro1_MINUS_TB_sync or e_Ro1_PLUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_Ro1_MINUS = 1'b0; + e_Ro1_PLUS = 1'b0; + + case (state) + p1_1HOT_ENCODING: // 4'b0001: // + begin + if (Ri_PLUS__TB_sync) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 4'b0010: // + begin + if (e_Ro1_MINUS_TB_sync) + begin + e_Ro1_MINUS = 1'b1; + next_state = p9_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 4'b0100: // + begin + if (Ri_MINUS__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p9_1HOT_ENCODING: // 4'b1000: // + begin + if (e_Ro1_PLUS_TB_sync) + begin + e_Ro1_PLUS = 1'b1; + next_state = p4_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + diff --git a/examples/toggle_AC/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/toggle_AC/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..2801d25 --- /dev/null +++ b/examples/toggle_AC/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,132 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + Ro1_MINUS, + Ri_PLUS, + Ro2_MINUS, + Ro1_PLUS, + Ri_MINUS, + Ro2_PLUS); + + input clk; + input reset; + output Ro1_MINUS; + input Ri_PLUS; + output Ro2_MINUS; + output Ro1_PLUS; + input Ri_MINUS; + output Ro2_PLUS; + + wire p0_FSM1out, p1_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_Ro1_MINUS_FSM2out, e_Ro1_PLUS_FSM2out; // Regular output signals of FSM2 // + wire p1_FSM2out, p2_FSM2out, p4_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_Ro2_MINUS_FSM3out, e_Ro2_PLUS_FSM3out; // Regular output signals of FSM3 // + wire p0_FSM3out, p3_FSM3out, p7_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_Ro1_MINUS_FSM4out, e_Ro1_PLUS_FSM4out; // Regular output signals of FSM4 // + wire p1_FSM4out, p2_FSM4out, p4_FSM4out, p5_FSM4out; // State Synchronisation output signals of FSM4 // + wire e_Ro2_MINUS_FSM5out, e_Ro2_PLUS_FSM5out; // Regular output signals of FSM5 // + wire p0_FSM5out, p3_FSM5out, p6_FSM5out, p7_FSM5out; // State Synchronisation output signals of FSM5 // + wire e_Ro2_MINUS_FSM6out, e_Ro2_PLUS_FSM6out; // Regular output signals of FSM6 // + wire p0_FSM6out, p3_FSM6out, p7_FSM6out, p8_FSM6out; // State Synchronisation output signals of FSM6 // + wire e_Ro1_MINUS_FSM7out, e_Ro1_PLUS_FSM7out; // Regular output signals of FSM7 // + wire p1_FSM7out, p2_FSM7out, p4_FSM7out, p9_FSM7out; // State Synchronisation output signals of FSM7 // + + assign Ro1_MINUS = e_Ro1_MINUS_FSM2out & e_Ro1_MINUS_FSM4out & e_Ro1_MINUS_FSM7out; + assign Ro2_MINUS = e_Ro2_MINUS_FSM3out & e_Ro2_MINUS_FSM5out & e_Ro2_MINUS_FSM6out; + assign Ro1_PLUS = e_Ro1_PLUS_FSM2out & e_Ro1_PLUS_FSM4out & e_Ro1_PLUS_FSM7out; + assign Ro2_PLUS = e_Ro2_PLUS_FSM3out & e_Ro2_PLUS_FSM5out & e_Ro2_PLUS_FSM6out; + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .p0(p0_FSM1out), + .p1(p1_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro1_MINUS(e_Ro1_MINUS_FSM2out), .e_Ro1_MINUS_p5_FSM4_TB(p5_FSM4out), .e_Ro1_MINUS_p2_FSM7_TB(p2_FSM7out), + .e_Ro1_PLUS(e_Ro1_PLUS_FSM2out), .e_Ro1_PLUS_p2_FSM4_TB(p2_FSM4out), .e_Ro1_PLUS_p9_FSM7_TB(p9_FSM7out), + .p1(p1_FSM2out), + .p2(p2_FSM2out), + .p4(p4_FSM2out) + ); + + + fsm_mealy_behav_03 fsm_mealy_behav_03_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(e_Ro2_MINUS_FSM3out), .e_Ro2_MINUS_p6_FSM5_TB(p6_FSM5out), .e_Ro2_MINUS_p3_FSM6_TB(p3_FSM6out), + .e_Ro2_PLUS(e_Ro2_PLUS_FSM3out), .e_Ro2_PLUS_p3_FSM5_TB(p3_FSM5out), .e_Ro2_PLUS_p8_FSM6_TB(p8_FSM6out), + .p0(p0_FSM3out), + .p3(p3_FSM3out), + .p7(p7_FSM3out) + ); + + + fsm_mealy_behav_04 fsm_mealy_behav_04_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro1_MINUS(e_Ro1_MINUS_FSM4out), .e_Ro1_MINUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_MINUS_p2_FSM7_TB(p2_FSM7out), + .e_Ro1_PLUS(e_Ro1_PLUS_FSM4out), .e_Ro1_PLUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_PLUS_p9_FSM7_TB(p9_FSM7out), + .p1(p1_FSM4out), + .p2(p2_FSM4out), + .p4(p4_FSM4out), + .p5(p5_FSM4out) + ); + + + fsm_mealy_behav_05 fsm_mealy_behav_05_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(e_Ro2_MINUS_FSM5out), .e_Ro2_MINUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_MINUS_p3_FSM6_TB(p3_FSM6out), + .e_Ro2_PLUS(e_Ro2_PLUS_FSM5out), .e_Ro2_PLUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_PLUS_p8_FSM6_TB(p8_FSM6out), + .p0(p0_FSM5out), + .p3(p3_FSM5out), + .p6(p6_FSM5out), + .p7(p7_FSM5out) + ); + + + fsm_mealy_behav_06 fsm_mealy_behav_06_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(e_Ro2_MINUS_FSM6out), .e_Ro2_MINUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_MINUS_p6_FSM5_TB(p6_FSM5out), + .e_Ro2_PLUS(e_Ro2_PLUS_FSM6out), .e_Ro2_PLUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_PLUS_p3_FSM5_TB(p3_FSM5out), + .p0(p0_FSM6out), + .p3(p3_FSM6out), + .p7(p7_FSM6out), + .p8(p8_FSM6out) + ); + + + fsm_mealy_behav_07 fsm_mealy_behav_07_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), + .e_Ro1_MINUS(e_Ro1_MINUS_FSM7out), .e_Ro1_MINUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_MINUS_p5_FSM4_TB(p5_FSM4out), + .e_Ro1_PLUS(e_Ro1_PLUS_FSM7out), .e_Ro1_PLUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_PLUS_p2_FSM4_TB(p2_FSM4out), + .p1(p1_FSM7out), + .p2(p2_FSM7out), + .p4(p4_FSM7out), + .p9(p9_FSM7out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/toggle_AC/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/toggle_AC/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..224c4f8 --- /dev/null +++ b/examples/toggle_AC/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,132 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + Ro1_MINUS, + Ri_PLUS, + Ro2_MINUS, + Ro1_PLUS, + Ri_MINUS, + Ro2_PLUS); + + input clk; + input reset; + output Ro1_MINUS; + input Ri_PLUS; + output Ro2_MINUS; + output Ro1_PLUS; + input Ri_MINUS; + output Ro2_PLUS; + + wire p0_FSM1out, p1_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_Ro1_MINUS_FSM2out, e_Ro1_PLUS_FSM2out; // Regular output signals of FSM2 // + wire p1_FSM2out, p2_FSM2out, p4_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_Ro2_MINUS_FSM3out, e_Ro2_PLUS_FSM3out; // Regular output signals of FSM3 // + wire p0_FSM3out, p3_FSM3out, p7_FSM3out; // State Synchronisation output signals of FSM3 // + wire e_Ro1_MINUS_FSM4out, e_Ro1_PLUS_FSM4out; // Regular output signals of FSM4 // + wire p1_FSM4out, p2_FSM4out, p4_FSM4out, p5_FSM4out; // State Synchronisation output signals of FSM4 // + wire e_Ro2_MINUS_FSM5out, e_Ro2_PLUS_FSM5out; // Regular output signals of FSM5 // + wire p0_FSM5out, p3_FSM5out, p6_FSM5out, p7_FSM5out; // State Synchronisation output signals of FSM5 // + wire e_Ro2_MINUS_FSM6out, e_Ro2_PLUS_FSM6out; // Regular output signals of FSM6 // + wire p0_FSM6out, p3_FSM6out, p7_FSM6out, p8_FSM6out; // State Synchronisation output signals of FSM6 // + wire e_Ro1_MINUS_FSM7out, e_Ro1_PLUS_FSM7out; // Regular output signals of FSM7 // + wire p1_FSM7out, p2_FSM7out, p4_FSM7out, p9_FSM7out; // State Synchronisation output signals of FSM7 // + + assign Ro1_MINUS = e_Ro1_MINUS_FSM2out & e_Ro1_MINUS_FSM4out & e_Ro1_MINUS_FSM7out; + assign Ro2_MINUS = e_Ro2_MINUS_FSM3out & e_Ro2_MINUS_FSM5out & e_Ro2_MINUS_FSM6out; + assign Ro1_PLUS = e_Ro1_PLUS_FSM2out & e_Ro1_PLUS_FSM4out & e_Ro1_PLUS_FSM7out; + assign Ro2_PLUS = e_Ro2_PLUS_FSM3out & e_Ro2_PLUS_FSM5out & e_Ro2_PLUS_FSM6out; + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .p0(p0_FSM1out), + .p1(p1_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro1_MINUS(e_Ro1_MINUS_FSM2out), .e_Ro1_MINUS_p5_FSM4_TB(p5_FSM4out), .e_Ro1_MINUS_p2_FSM7_TB(p2_FSM7out), + .e_Ro1_PLUS(e_Ro1_PLUS_FSM2out), .e_Ro1_PLUS_p2_FSM4_TB(p2_FSM4out), .e_Ro1_PLUS_p9_FSM7_TB(p9_FSM7out), + .p1(p1_FSM2out), + .p2(p2_FSM2out), + .p4(p4_FSM2out) + ); + + + fsm_mealy_synth_03 fsm_mealy_synth_03_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(e_Ro2_MINUS_FSM3out), .e_Ro2_MINUS_p6_FSM5_TB(p6_FSM5out), .e_Ro2_MINUS_p3_FSM6_TB(p3_FSM6out), + .e_Ro2_PLUS(e_Ro2_PLUS_FSM3out), .e_Ro2_PLUS_p3_FSM5_TB(p3_FSM5out), .e_Ro2_PLUS_p8_FSM6_TB(p8_FSM6out), + .p0(p0_FSM3out), + .p3(p3_FSM3out), + .p7(p7_FSM3out) + ); + + + fsm_mealy_synth_04 fsm_mealy_synth_04_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro1_MINUS(e_Ro1_MINUS_FSM4out), .e_Ro1_MINUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_MINUS_p2_FSM7_TB(p2_FSM7out), + .e_Ro1_PLUS(e_Ro1_PLUS_FSM4out), .e_Ro1_PLUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_PLUS_p9_FSM7_TB(p9_FSM7out), + .p1(p1_FSM4out), + .p2(p2_FSM4out), + .p4(p4_FSM4out), + .p5(p5_FSM4out) + ); + + + fsm_mealy_synth_05 fsm_mealy_synth_05_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(e_Ro2_MINUS_FSM5out), .e_Ro2_MINUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_MINUS_p3_FSM6_TB(p3_FSM6out), + .e_Ro2_PLUS(e_Ro2_PLUS_FSM5out), .e_Ro2_PLUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_PLUS_p8_FSM6_TB(p8_FSM6out), + .p0(p0_FSM5out), + .p3(p3_FSM5out), + .p6(p6_FSM5out), + .p7(p7_FSM5out) + ); + + + fsm_mealy_synth_06 fsm_mealy_synth_06_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p1_FSM7_TB(p1_FSM7out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p4_FSM7_TB(p4_FSM7out), + .e_Ro2_MINUS(e_Ro2_MINUS_FSM6out), .e_Ro2_MINUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_MINUS_p6_FSM5_TB(p6_FSM5out), + .e_Ro2_PLUS(e_Ro2_PLUS_FSM6out), .e_Ro2_PLUS_p3_FSM3_TB(p3_FSM3out), .e_Ro2_PLUS_p3_FSM5_TB(p3_FSM5out), + .p0(p0_FSM6out), + .p3(p3_FSM6out), + .p7(p7_FSM6out), + .p8(p8_FSM6out) + ); + + + fsm_mealy_synth_07 fsm_mealy_synth_07_inst ( + .clk(clk), + .reset(reset), + .Ri_PLUS_(Ri_PLUS), .Ri_PLUS__p1_FSM1_TB(p1_FSM1out), .Ri_PLUS__p1_FSM2_TB(p1_FSM2out), .Ri_PLUS__p7_FSM3_TB(p7_FSM3out), .Ri_PLUS__p1_FSM4_TB(p1_FSM4out), .Ri_PLUS__p7_FSM5_TB(p7_FSM5out), .Ri_PLUS__p7_FSM6_TB(p7_FSM6out), + .Ri_MINUS_(Ri_MINUS), .Ri_MINUS__p0_FSM1_TB(p0_FSM1out), .Ri_MINUS__p4_FSM2_TB(p4_FSM2out), .Ri_MINUS__p0_FSM3_TB(p0_FSM3out), .Ri_MINUS__p4_FSM4_TB(p4_FSM4out), .Ri_MINUS__p0_FSM5_TB(p0_FSM5out), .Ri_MINUS__p0_FSM6_TB(p0_FSM6out), + .e_Ro1_MINUS(e_Ro1_MINUS_FSM7out), .e_Ro1_MINUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_MINUS_p5_FSM4_TB(p5_FSM4out), + .e_Ro1_PLUS(e_Ro1_PLUS_FSM7out), .e_Ro1_PLUS_p2_FSM2_TB(p2_FSM2out), .e_Ro1_PLUS_p2_FSM4_TB(p2_FSM4out), + .p1(p1_FSM7out), + .p2(p2_FSM7out), + .p4(p4_FSM7out), + .p9(p9_FSM7out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/toggle_AC/msfsms_tool_bm.log b/examples/toggle_AC/msfsms_tool_bm.log new file mode 100644 index 0000000..31cf27f --- /dev/null +++ b/examples/toggle_AC/msfsms_tool_bm.log @@ -0,0 +1,409 @@ +--------------------------------------------------------------------------- +Benchmark: toggle_AC/toggle.petrinet.AC.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/toggle_AC/toggle.petrinet.AC.workcraft.g +INFO: Total Nodes : 16 +INFO: Total Transitions : 6 +INFO: Total Places : 10 +INFO: Total Edges : 24 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [2][0]: Label = Ro1_MINUS, Type = Transition (is Output) + Predecessors: p2[7][0], p5[10][1] + Successors: p4[9][0], p9[14][0] +PT-Net [3][0]: Label = Ri_PLUS, Type = Transition (is Input) + Predecessors: p1[6][0], p7[12][0] + Successors: p0[5][0], p2[7][0] +PT-Net [3][1]: Label = Ro2_MINUS, Type = Transition (is Output) + Predecessors: p3[8][0], p6[11][2] + Successors: p7[12][0], p8[13][0] +PT-Net [5][0]: Label = p0, Type = Place (is Empty) + Predecessors: Ri_PLUS[3][0] + Successors: Ri_MINUS[11][0] +PT-Net [6][0]: Label = p1, Type = Place (is Marked) + Predecessors: Ri_MINUS[11][0] + Successors: Ri_PLUS[3][0] +PT-Net [7][0]: Label = p2, Type = Place (is Empty) + Predecessors: Ri_PLUS[3][0] + Successors: Ro1_MINUS[2][0], Ro1_PLUS[10][0] +PT-Net [8][0]: Label = p3, Type = Place (is Empty) + Predecessors: Ri_MINUS[11][0] + Successors: Ro2_MINUS[3][1], Ro2_PLUS[11][1] +PT-Net [9][0]: Label = p4, Type = Place (is Empty) + Predecessors: Ro1_PLUS[10][0], Ro1_MINUS[2][0] + Successors: Ri_MINUS[11][0] +PT-Net [10][0]: Label = Ro1_PLUS, Type = Transition (is Output) + Predecessors: p2[7][0], p9[14][0] + Successors: p4[9][0], p5[10][1] +PT-Net [10][1]: Label = p5, Type = Place (is Empty) + Predecessors: Ro1_PLUS[10][0] + Successors: Ro1_MINUS[2][0] +PT-Net [11][0]: Label = Ri_MINUS, Type = Transition (is Input) + Predecessors: p0[5][0], p4[9][0] + Successors: p1[6][0], p3[8][0] +PT-Net [11][1]: Label = Ro2_PLUS, Type = Transition (is Output) + Predecessors: p3[8][0], p8[13][0] + Successors: p6[11][2], p7[12][0] +PT-Net [11][2]: Label = p6, Type = Place (is Empty) + Predecessors: Ro2_PLUS[11][1] + Successors: Ro2_MINUS[3][1] +PT-Net [12][0]: Label = p7, Type = Place (is Marked) + Predecessors: Ro2_PLUS[11][1], Ro2_MINUS[3][1] + Successors: Ri_PLUS[3][0] +PT-Net [13][0]: Label = p8, Type = Place (is Marked) + Predecessors: Ro2_MINUS[3][1] + Successors: Ro2_PLUS[11][1] +PT-Net [14][0]: Label = p9, Type = Place (is Marked) + Predecessors: Ro1_MINUS[2][0] + Successors: Ro1_PLUS[10][0] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #7 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 4, H-collapsed = 'false' *** +SC S-net (1,1): Ri_PLUS[3][0] + Predecessor Place: p1(1,3)[6,0] + Successor Place: p0(1,2)[5,0] +SC S-net (1,2): p0[5][0] +SC S-net (1,3): p1[6][0] +SC S-net (1,4): Ri_MINUS[11][0] + Predecessor Place: p0(1,2)[5,0] + Successor Place: p1(1,3)[6,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 7, H-collapsed = 'false' *** +SC S-net (2,1): Ro1_MINUS[2][0] + Predecessor Place: p2(2,4)[7,0] + Successor Place: p4(2,5)[9,0] +SC S-net (2,2): Ri_PLUS[3][0] + Predecessor Place: p1(2,3)[6,0] + Successor Place: p2(2,4)[7,0] +SC S-net (2,3): p1[6][0] +SC S-net (2,4): p2[7][0] +SC S-net (2,5): p4[9][0] +SC S-net (2,6): Ro1_PLUS[10][0] + Predecessor Place: p2(2,4)[7,0] + Successor Place: p4(2,5)[9,0] +SC S-net (2,7): Ri_MINUS[11][0] + Predecessor Place: p4(2,5)[9,0] + Successor Place: p1(2,3)[6,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #3, Total Nodes = 7, H-collapsed = 'false' *** +SC S-net (3,1): Ri_PLUS[3][0] + Predecessor Place: p7(3,7)[12,0] + Successor Place: p0(3,3)[5,0] +SC S-net (3,2): Ro2_MINUS[3][1] + Predecessor Place: p3(3,4)[8,0] + Successor Place: p7(3,7)[12,0] +SC S-net (3,3): p0[5][0] +SC S-net (3,4): p3[8][0] +SC S-net (3,5): Ri_MINUS[11][0] + Predecessor Place: p0(3,3)[5,0] + Successor Place: p3(3,4)[8,0] +SC S-net (3,6): Ro2_PLUS[11][1] + Predecessor Place: p3(3,4)[8,0] + Successor Place: p7(3,7)[12,0] +SC S-net (3,7): p7[12][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #4, Total Nodes = 8, H-collapsed = 'false' *** +SC S-net (4,1): Ro1_MINUS[2][0] + Predecessor Place: p5(4,7)[10,1] + Successor Place: p4(4,5)[9,0] +SC S-net (4,2): Ri_PLUS[3][0] + Predecessor Place: p1(4,3)[6,0] + Successor Place: p2(4,4)[7,0] +SC S-net (4,3): p1[6][0] +SC S-net (4,4): p2[7][0] +SC S-net (4,5): p4[9][0] +SC S-net (4,6): Ro1_PLUS[10][0] + Predecessor Place: p2(4,4)[7,0] + Successor Place: p5(4,7)[10,1] +SC S-net (4,7): p5[10][1] +SC S-net (4,8): Ri_MINUS[11][0] + Predecessor Place: p4(4,5)[9,0] + Successor Place: p1(4,3)[6,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #5, Total Nodes = 8, H-collapsed = 'false' *** +SC S-net (5,1): Ri_PLUS[3][0] + Predecessor Place: p7(5,8)[12,0] + Successor Place: p0(5,3)[5,0] +SC S-net (5,2): Ro2_MINUS[3][1] + Predecessor Place: p6(5,7)[11,2] + Successor Place: p7(5,8)[12,0] +SC S-net (5,3): p0[5][0] +SC S-net (5,4): p3[8][0] +SC S-net (5,5): Ri_MINUS[11][0] + Predecessor Place: p0(5,3)[5,0] + Successor Place: p3(5,4)[8,0] +SC S-net (5,6): Ro2_PLUS[11][1] + Predecessor Place: p3(5,4)[8,0] + Successor Place: p6(5,7)[11,2] +SC S-net (5,7): p6[11][2] +SC S-net (5,8): p7[12][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #6, Total Nodes = 8, H-collapsed = 'false' *** +SC S-net (6,1): Ri_PLUS[3][0] + Predecessor Place: p7(6,7)[12,0] + Successor Place: p0(6,3)[5,0] +SC S-net (6,2): Ro2_MINUS[3][1] + Predecessor Place: p3(6,4)[8,0] + Successor Place: p8(6,8)[13,0] +SC S-net (6,3): p0[5][0] +SC S-net (6,4): p3[8][0] +SC S-net (6,5): Ri_MINUS[11][0] + Predecessor Place: p0(6,3)[5,0] + Successor Place: p3(6,4)[8,0] +SC S-net (6,6): Ro2_PLUS[11][1] + Predecessor Place: p8(6,8)[13,0] + Successor Place: p7(6,7)[12,0] +SC S-net (6,7): p7[12][0] +SC S-net (6,8): p8[13][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #7, Total Nodes = 8, H-collapsed = 'false' *** +SC S-net (7,1): Ro1_MINUS[2][0] + Predecessor Place: p2(7,4)[7,0] + Successor Place: p9(7,8)[14,0] +SC S-net (7,2): Ri_PLUS[3][0] + Predecessor Place: p1(7,3)[6,0] + Successor Place: p2(7,4)[7,0] +SC S-net (7,3): p1[6][0] +SC S-net (7,4): p2[7][0] +SC S-net (7,5): p4[9][0] +SC S-net (7,6): Ro1_PLUS[10][0] + Predecessor Place: p9(7,8)[14,0] + Successor Place: p4(7,5)[9,0] +SC S-net (7,7): Ri_MINUS[11][0] + Predecessor Place: p4(7,5)[9,0] + Successor Place: p1(7,3)[6,0] +SC S-net (7,8): p9[14][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #7 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #7 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #3 (of #7 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #4 (of #7 total). +INFO: P "p2"[7, 0] should NOT be a predecessor of T "Ro1_MINUS"[2, 0] in S-Net #4. +INFO: P "p4"[9, 0] should NOT be a successor of T "Ro1_PLUS"[10, 0] in S-Net #4. +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #5 (of #7 total). +INFO: P "p3"[8, 0] should NOT be a predecessor of T "Ro2_MINUS"[3, 1] in S-Net #5. +INFO: P "p7"[12, 0] should NOT be a successor of T "Ro2_PLUS"[11, 1] in S-Net #5. +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #6 (of #7 total). +INFO: P "p3"[8, 0] should NOT be a predecessor of T "Ro2_PLUS"[11, 1] in S-Net #6. +INFO: P "p7"[12, 0] should NOT be a successor of T "Ro2_MINUS"[3, 1] in S-Net #6. +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #7 (of #7 total). +INFO: P "p2"[7, 0] should NOT be a predecessor of T "Ro1_PLUS"[10, 0] in S-Net #7. +INFO: P "p4"[9, 0] should NOT be a successor of T "Ro1_MINUS"[2, 0] in S-Net #7. +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#7 ***, identical to #4 +Matching Pairs: +Index 0: Matching pairs (2, 2) +Index 1: Matching pairs (6, 1) +Index 2: Matching pairs (1, 6) +Index 3: Matching pairs (8, 7) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: *** Collapsed FSM#6 ***, identical to #5 +Matching Pairs: +Index 0: Matching pairs (1, 1) +Index 1: Matching pairs (5, 5) +Index 2: Matching pairs (6, 2) +Index 3: Matching pairs (2, 6) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 4, H-Collapsed = 'false' *** +FSM (1,1): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(0,2) + Predecessor(s): p1(0,3) +FSM (1,2): Label = p0, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(0,4) + Predecessor(s): Ri_PLUS/(0,1) +FSM (1,3): Label = p1, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(0,1) + Predecessor(s): Ri_MINUS/(0,4) +FSM (1,4): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p1(0,3) + Predecessor(s): p0(0,2) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 7, H-Collapsed = 'false' *** +FSM (2,1): Label = e/Ro1_MINUS, Type = Trans. Function (is Output) + Successor(s): p4(1,5) + Predecessor(s): p2(1,4) +FSM (2,2): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p2(1,4) + Predecessor(s): p1(1,3) +FSM (2,3): Label = p1, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(1,2) + Predecessor(s): Ri_MINUS/(1,7) +FSM (2,4): Label = p2, Type = State (is Initially Inactive) + Successor(s): e/Ro1_MINUS(1,1) e/Ro1_PLUS(1,6) + Predecessor(s): Ri_PLUS/(1,2) +FSM (2,5): Label = p4, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(1,7) + Predecessor(s): e/Ro1_PLUS(1,6) e/Ro1_MINUS(1,1) +FSM (2,6): Label = e/Ro1_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(1,5) + Predecessor(s): p2(1,4) +FSM (2,7): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p1(1,3) + Predecessor(s): p4(1,5) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 3, Total list Entries = 7, H-Collapsed = 'false' *** +FSM (3,1): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(2,3) + Predecessor(s): p7(2,7) +FSM (3,2): Label = e/Ro2_MINUS, Type = Trans. Function (is Output) + Successor(s): p7(2,7) + Predecessor(s): p3(2,4) +FSM (3,3): Label = p0, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(2,5) + Predecessor(s): Ri_PLUS/(2,1) +FSM (3,4): Label = p3, Type = State (is Initially Inactive) + Successor(s): e/Ro2_MINUS(2,2) e/Ro2_PLUS(2,6) + Predecessor(s): Ri_MINUS/(2,5) +FSM (3,5): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p3(2,4) + Predecessor(s): p0(2,3) +FSM (3,6): Label = e/Ro2_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(2,7) + Predecessor(s): p3(2,4) +FSM (3,7): Label = p7, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(2,1) + Predecessor(s): e/Ro2_PLUS(2,6) e/Ro2_MINUS(2,2) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 4, Total list Entries = 8, H-Collapsed = 'false' *** +FSM (4,1): Label = e/Ro1_MINUS, Type = Trans. Function (is Output) + Successor(s): p4(3,5) + Predecessor(s): p5(3,7) +FSM (4,2): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p2(3,4) + Predecessor(s): p1(3,3) +FSM (4,3): Label = p1, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(3,2) + Predecessor(s): Ri_MINUS/(3,8) +FSM (4,4): Label = p2, Type = State (is Initially Inactive) + Successor(s): e/Ro1_PLUS(3,6) + Predecessor(s): Ri_PLUS/(3,2) +FSM (4,5): Label = p4, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(3,8) + Predecessor(s): e/Ro1_MINUS(3,1) +FSM (4,6): Label = e/Ro1_PLUS, Type = Trans. Function (is Output) + Successor(s): p5(3,7) + Predecessor(s): p2(3,4) +FSM (4,7): Label = p5, Type = State (is Initially Inactive) + Successor(s): e/Ro1_MINUS(3,1) + Predecessor(s): e/Ro1_PLUS(3,6) +FSM (4,8): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p1(3,3) + Predecessor(s): p4(3,5) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 5, Total list Entries = 8, H-Collapsed = 'false' *** +FSM (5,1): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(4,3) + Predecessor(s): p7(4,8) +FSM (5,2): Label = e/Ro2_MINUS, Type = Trans. Function (is Output) + Successor(s): p7(4,8) + Predecessor(s): p6(4,7) +FSM (5,3): Label = p0, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(4,5) + Predecessor(s): Ri_PLUS/(4,1) +FSM (5,4): Label = p3, Type = State (is Initially Inactive) + Successor(s): e/Ro2_PLUS(4,6) + Predecessor(s): Ri_MINUS/(4,5) +FSM (5,5): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p3(4,4) + Predecessor(s): p0(4,3) +FSM (5,6): Label = e/Ro2_PLUS, Type = Trans. Function (is Output) + Successor(s): p6(4,7) + Predecessor(s): p3(4,4) +FSM (5,7): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/Ro2_MINUS(4,2) + Predecessor(s): e/Ro2_PLUS(4,6) +FSM (5,8): Label = p7, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(4,1) + Predecessor(s): e/Ro2_MINUS(4,2) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 6, Total list Entries = 8, H-Collapsed = 'false' *** +FSM (6,1): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(5,3) + Predecessor(s): p7(5,7) +FSM (6,2): Label = e/Ro2_MINUS, Type = Trans. Function (is Output) + Successor(s): p8(5,8) + Predecessor(s): p3(5,4) +FSM (6,3): Label = p0, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(5,5) + Predecessor(s): Ri_PLUS/(5,1) +FSM (6,4): Label = p3, Type = State (is Initially Inactive) + Successor(s): e/Ro2_MINUS(5,2) + Predecessor(s): Ri_MINUS/(5,5) +FSM (6,5): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p3(5,4) + Predecessor(s): p0(5,3) +FSM (6,6): Label = e/Ro2_PLUS, Type = Trans. Function (is Output) + Successor(s): p7(5,7) + Predecessor(s): p8(5,8) +FSM (6,7): Label = p7, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(5,1) + Predecessor(s): e/Ro2_PLUS(5,6) +FSM (6,8): Label = p8, Type = State (is Initially Active) + Successor(s): e/Ro2_PLUS(5,6) + Predecessor(s): e/Ro2_MINUS(5,2) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 7, Total list Entries = 8, H-Collapsed = 'false' *** +FSM (7,1): Label = e/Ro1_MINUS, Type = Trans. Function (is Output) + Successor(s): p9(6,8) + Predecessor(s): p2(6,4) +FSM (7,2): Label = Ri_PLUS/, Type = Trans. Function (is Input) + Successor(s): p2(6,4) + Predecessor(s): p1(6,3) +FSM (7,3): Label = p1, Type = State (is Initially Active) + Successor(s): Ri_PLUS/(6,2) + Predecessor(s): Ri_MINUS/(6,7) +FSM (7,4): Label = p2, Type = State (is Initially Inactive) + Successor(s): e/Ro1_MINUS(6,1) + Predecessor(s): Ri_PLUS/(6,2) +FSM (7,5): Label = p4, Type = State (is Initially Inactive) + Successor(s): Ri_MINUS/(6,7) + Predecessor(s): e/Ro1_PLUS(6,6) +FSM (7,6): Label = e/Ro1_PLUS, Type = Trans. Function (is Output) + Successor(s): p4(6,5) + Predecessor(s): p9(6,8) +FSM (7,7): Label = Ri_MINUS/, Type = Trans. Function (is Input) + Successor(s): p1(6,3) + Predecessor(s): p4(6,5) +FSM (7,8): Label = p9, Type = State (is Initially Active) + Successor(s): e/Ro1_PLUS(6,6) + Predecessor(s): e/Ro1_MINUS(6,1) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +WARNING: Multiple initial active states for FSM(6), continuing... +WARNING: Multiple initial active states for FSM(7), continuing... +WARNING: Multiple Active states for FSMs: |#6|#7| +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +WARNING: Multiple initial active states for FSM(6), continuing... +WARNING: Multiple initial active states for FSM(7), continuing... +WARNING: Multiple Active states for FSMs: |#6|#7| +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +WARNING: Multiple initial active states for FSM(6), continuing... +WARNING: Multiple initial active states for FSM(7), continuing... +WARNING: Multiple Active states for FSMs: |#6|#7| +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/toggle_AC/toggle.petrinet.AC.workcraft.g b/examples/toggle_AC/toggle.petrinet.AC.workcraft.g new file mode 100644 index 0000000..a8adc6b --- /dev/null +++ b/examples/toggle_AC/toggle.petrinet.AC.workcraft.g @@ -0,0 +1,23 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.0 +.model toggle +.inputs Ri_MINUS Ri_PLUS +.outputs Ro1_MINUS Ro1_PLUS Ro2_MINUS Ro2_PLUS +.graph +Ri_PLUS p0 p2 +Ri_MINUS p1 p3 +Ro1_PLUS p4 p5 +Ro1_MINUS p4 p9 +Ro2_PLUS p6 p7 +Ro2_MINUS p7 p8 +p0 Ri_MINUS +p1 Ri_PLUS +p2 Ro1_MINUS Ro1_PLUS +p3 Ro2_MINUS Ro2_PLUS +p4 Ri_MINUS +p5 Ro1_MINUS +p6 Ro2_MINUS +p7 Ri_PLUS +p8 Ro2_PLUS +p9 Ro1_PLUS +.marking {p1 p7 p8 p9} +.end diff --git a/examples/vem_AC/AsyncMSFSMs/fsm_afsm.afsm b/examples/vem_AC/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..6f8fb1b --- /dev/null +++ b/examples/vem_AC/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,38 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p10: e_d_PLUS p11 +p9: d_MINUSa_ d_MINUSa__p9_FSM2_TB p4 +p8: dsr_MINUS_ dsr_MINUS__p8_FSM2_TB p9 +p7: e_dtack_PLUS e_dtack_PLUS_p7_FSM2_TB p8 +p6: e_d_PLUSa e_d_PLUSa_p6_FSM2_TB p7 +p5: ldtack_PLUS_ ldtack_PLUS__p5_FSM2_TB p6 +p4: e_dtack_MINUS p1 +p1*: dsr_PLUS_ p0 +p1*: dsw_PLUS_ p10 +p0: e_lds_PLUS e_lds_PLUS_p2_FSM2_TB p5 +p15: dsw_MINUS_ dsw_MINUS__p15_FSM2_TB p4 +p14: e_dtack_PLUSa e_dtack_PLUSa_p14_FSM2_TB p15 +p13: e_d_MINUS e_d_MINUS_p13_FSM2_TB p14 +p12: ldtack_PLUSa_ ldtack_PLUSa__p12_FSM2_TB p13 +p11: e_lds_MINUS e_lds_MINUS_p2_FSM2_TB p12 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p9: d_MINUSa_ d_MINUSa__p9_FSM1_TB p3 +p8: dsr_MINUS_ dsr_MINUS__p8_FSM1_TB p9 +p7: e_dtack_PLUS e_dtack_PLUS_p7_FSM1_TB p8 +p6: e_d_PLUSa e_d_PLUSa_p6_FSM1_TB p7 +p5: ldtack_PLUS_ ldtack_PLUS__p5_FSM1_TB p6 +p3: e_lds_MINUSa p16 +p2*: e_lds_MINUS e_lds_MINUS_p11_FSM1_TB p12 +p2*: e_lds_PLUS e_lds_PLUS_p0_FSM1_TB p5 +p16: ldtack_MINUS_ p2 +p15: dsw_MINUS_ dsw_MINUS__p15_FSM1_TB p3 +p14: e_dtack_PLUSa e_dtack_PLUSa_p14_FSM1_TB p15 +p13: e_d_MINUS e_d_MINUS_p13_FSM1_TB p14 +p12: ldtack_PLUSa_ ldtack_PLUSa__p12_FSM1_TB p13 +### End of FSM #02 Declaration ### + diff --git a/examples/vem_AC/AsyncMSFSMs/msfsms_afsm.v b/examples/vem_AC/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..12d9d84 --- /dev/null +++ b/examples/vem_AC/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,115 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + dsr_PLUS, + d_PLUS, + ldtack_PLUSa, + lds_MINUS, + d_PLUSa, + dtack_PLUSa, + dsw_PLUS, + dtack_PLUS, + d_MINUSa, + dsw_MINUS, + lds_MINUSa, + lds_PLUS, + ldtack_MINUS, + d_MINUS, + dsr_MINUS, + ldtack_PLUS, + dtack_MINUS); + + input reset; + input dsr_PLUS; + output d_PLUS; + input ldtack_PLUSa; + output lds_MINUS; + output d_PLUSa; + output dtack_PLUSa; + input dsw_PLUS; + output dtack_PLUS; + input d_MINUSa; + input dsw_MINUS; + output lds_MINUSa; + output lds_PLUS; + input ldtack_MINUS; + output d_MINUS; + input dsr_MINUS; + input ldtack_PLUS; + output dtack_MINUS; + + wire e_d_PLUS_FSM1out, e_lds_MINUS_FSM1out, e_d_PLUSa_FSM1out, e_dtack_PLUSa_FSM1out, e_dtack_PLUS_FSM1out, e_lds_PLUS_FSM1out, e_d_MINUS_FSM1out, e_dtack_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p10_FSM1out, p9_FSM1out, p8_FSM1out, p7_FSM1out, p6_FSM1out, p5_FSM1out, p4_FSM1out, p1_FSM1out, p0_FSM1out, p15_FSM1out, p14_FSM1out, p13_FSM1out, p12_FSM1out, p11_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_lds_MINUS_FSM2out, e_d_PLUSa_FSM2out, e_dtack_PLUSa_FSM2out, e_dtack_PLUS_FSM2out, e_lds_MINUSa_FSM2out, e_lds_PLUS_FSM2out, e_d_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p9_FSM2out, p8_FSM2out, p7_FSM2out, p6_FSM2out, p5_FSM2out, p3_FSM2out, p2_FSM2out, p16_FSM2out, p15_FSM2out, p14_FSM2out, p13_FSM2out, p12_FSM2out; // State Synchronisation output signals of FSM2 // + + assign d_PLUS = e_d_PLUS_FSM1out; + assign lds_MINUS = e_lds_MINUS_FSM1out & e_lds_MINUS_FSM2out; + assign d_PLUSa = e_d_PLUSa_FSM1out & e_d_PLUSa_FSM2out; + assign dtack_PLUSa = e_dtack_PLUSa_FSM1out & e_dtack_PLUSa_FSM2out; + assign dtack_PLUS = e_dtack_PLUS_FSM1out & e_dtack_PLUS_FSM2out; + assign lds_MINUSa = e_lds_MINUSa_FSM2out; + assign lds_PLUS = e_lds_PLUS_FSM1out & e_lds_PLUS_FSM2out; + assign d_MINUS = e_d_MINUS_FSM1out & e_d_MINUS_FSM2out; + assign dtack_MINUS = e_dtack_MINUS_FSM1out; + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .dsr_PLUS_(dsr_PLUS), + .ldtack_PLUSa_(ldtack_PLUSa), .ldtack_PLUSa__p12_FSM2_TB(p12_FSM2out), + .dsw_PLUS_(dsw_PLUS), + .d_MINUSa_(d_MINUSa), .d_MINUSa__p9_FSM2_TB(p9_FSM2out), + .dsw_MINUS_(dsw_MINUS), .dsw_MINUS__p15_FSM2_TB(p15_FSM2out), + .dsr_MINUS_(dsr_MINUS), .dsr_MINUS__p8_FSM2_TB(p8_FSM2out), + .ldtack_PLUS_(ldtack_PLUS), .ldtack_PLUS__p5_FSM2_TB(p5_FSM2out), + .e_d_PLUS(p10_FSM1out), + .e_lds_MINUS(p11_FSM1out), .e_lds_MINUS_p2_FSM2_TB(p2_FSM2out), + .e_d_PLUSa(p6_FSM1out), .e_d_PLUSa_p6_FSM2_TB(p6_FSM2out), + .e_dtack_PLUSa(p14_FSM1out), .e_dtack_PLUSa_p14_FSM2_TB(p14_FSM2out), + .e_dtack_PLUS(p7_FSM1out), .e_dtack_PLUS_p7_FSM2_TB(p7_FSM2out), + .e_lds_PLUS(p0_FSM1out), .e_lds_PLUS_p2_FSM2_TB(p2_FSM2out), + .e_d_MINUS(p13_FSM1out), .e_d_MINUS_p13_FSM2_TB(p13_FSM2out), + .e_dtack_MINUS(p4_FSM1out), + .e/d_PLUS(e/d_PLUS_FSM1out), + .e/lds_MINUS(e/lds_MINUS_FSM1out), + .e/d_PLUSa(e/d_PLUSa_FSM1out), + .e/dtack_PLUSa(e/dtack_PLUSa_FSM1out), + .e/dtack_PLUS(e/dtack_PLUS_FSM1out), + .e/lds_PLUS(e/lds_PLUS_FSM1out), + .e/d_MINUS(e/d_MINUS_FSM1out), + .e/dtack_MINUS(e/dtack_MINUS_FSM1out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .ldtack_PLUSa_(ldtack_PLUSa), .ldtack_PLUSa__p12_FSM1_TB(p12_FSM1out), + .d_MINUSa_(d_MINUSa), .d_MINUSa__p9_FSM1_TB(p9_FSM1out), + .dsw_MINUS_(dsw_MINUS), .dsw_MINUS__p15_FSM1_TB(p15_FSM1out), + .ldtack_MINUS_(ldtack_MINUS), + .dsr_MINUS_(dsr_MINUS), .dsr_MINUS__p8_FSM1_TB(p8_FSM1out), + .ldtack_PLUS_(ldtack_PLUS), .ldtack_PLUS__p5_FSM1_TB(p5_FSM1out), + .e_lds_MINUS(p2_FSM2out), .e_lds_MINUS_p11_FSM1_TB(p11_FSM1out), + .e_d_PLUSa(p6_FSM2out), .e_d_PLUSa_p6_FSM1_TB(p6_FSM1out), + .e_dtack_PLUSa(p14_FSM2out), .e_dtack_PLUSa_p14_FSM1_TB(p14_FSM1out), + .e_dtack_PLUS(p7_FSM2out), .e_dtack_PLUS_p7_FSM1_TB(p7_FSM1out), + .e_lds_MINUSa(p3_FSM2out), + .e_lds_PLUS(p2_FSM2out), .e_lds_PLUS_p0_FSM1_TB(p0_FSM1out), + .e_d_MINUS(p13_FSM2out), .e_d_MINUS_p13_FSM1_TB(p13_FSM1out), + .e/lds_MINUS(e/lds_MINUS_FSM2out), + .e/d_PLUSa(e/d_PLUSa_FSM2out), + .e/dtack_PLUSa(e/dtack_PLUSa_FSM2out), + .e/dtack_PLUS(e/dtack_PLUS_FSM2out), + .e/lds_MINUSa(e/lds_MINUSa_FSM2out), + .e/lds_PLUS(e/lds_PLUS_FSM2out), + .e/d_MINUS(e/d_MINUS_FSM2out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/vem_AC/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/vem_AC/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..0c9b2ce --- /dev/null +++ b/examples/vem_AC/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,696 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + dsr_PLUS_, + ldtack_PLUSa_, ldtack_PLUSa__p12_FSM2_TB, + dsw_PLUS_, + d_MINUSa_, d_MINUSa__p9_FSM2_TB, + dsw_MINUS_, dsw_MINUS__p15_FSM2_TB, + dsr_MINUS_, dsr_MINUS__p8_FSM2_TB, + ldtack_PLUS_, ldtack_PLUS__p5_FSM2_TB, + e_d_PLUS, + e_lds_MINUS, e_lds_MINUS_p2_FSM2_TB, + e_d_PLUSa, e_d_PLUSa_p6_FSM2_TB, + e_dtack_PLUSa, e_dtack_PLUSa_p14_FSM2_TB, + e_dtack_PLUS, e_dtack_PLUS_p7_FSM2_TB, + e_lds_PLUS, e_lds_PLUS_p2_FSM2_TB, + e_d_MINUS, e_d_MINUS_p13_FSM2_TB, + e_dtack_MINUS, + p9, + p8, + p7, + p6, + p5, + p0, + p15, + p14, + p13, + p12, + p11 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input dsr_PLUS_; + input ldtack_PLUSa_; + input dsw_PLUS_; + input d_MINUSa_; + input dsw_MINUS_; + input dsr_MINUS_; + input ldtack_PLUS_; + // Transition Barrier Inputs for input Signals // + input ldtack_PLUSa__p12_FSM2_TB; + input d_MINUSa__p9_FSM2_TB; + input dsw_MINUS__p15_FSM2_TB; + input dsr_MINUS__p8_FSM2_TB; + input ldtack_PLUS__p5_FSM2_TB; + + // Regular output Signals // + output e_d_PLUS; + output e_lds_MINUS; + output e_d_PLUSa; + output e_dtack_PLUSa; + output e_dtack_PLUS; + output e_lds_PLUS; + output e_d_MINUS; + output e_dtack_MINUS; + // Transition Barrier outputs for output Signals // + input e_lds_MINUS_p2_FSM2_TB; + input e_d_PLUSa_p6_FSM2_TB; + input e_dtack_PLUSa_p14_FSM2_TB; + input e_dtack_PLUS_p7_FSM2_TB; + input e_lds_PLUS_p2_FSM2_TB; + input e_d_MINUS_p13_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p9; + output p8; + output p7; + output p6; + output p5; + output p0; + output p15; + output p14; + output p13; + output p12; + output p11; + + reg e_d_PLUS; + reg e_lds_MINUS; + reg e_d_PLUSa; + reg e_dtack_PLUSa; + reg e_dtack_PLUS; + reg e_lds_PLUS; + reg e_d_MINUS; + reg e_dtack_MINUS; + wire p9; + wire p8; + wire p7; + wire p6; + wire p5; + wire p0; + wire p15; + wire p14; + wire p13; + wire p12; + wire p11; + + wire ldtack_PLUSa__TB_sync; + wire d_MINUSa__TB_sync; + wire dsw_MINUS__TB_sync; + wire dsr_MINUS__TB_sync; + wire ldtack_PLUS__TB_sync; + wire e_lds_MINUS_TB_sync; + wire e_d_PLUSa_TB_sync; + wire e_dtack_PLUSa_TB_sync; + wire e_dtack_PLUS_TB_sync; + wire e_lds_PLUS_TB_sync; + wire e_d_MINUS_TB_sync; + assign ldtack_PLUSa__TB_sync = ldtack_PLUSa_ & ldtack_PLUSa__p12_FSM2_TB; + assign d_MINUSa__TB_sync = d_MINUSa_ & d_MINUSa__p9_FSM2_TB; + assign dsw_MINUS__TB_sync = dsw_MINUS_ & dsw_MINUS__p15_FSM2_TB; + assign dsr_MINUS__TB_sync = dsr_MINUS_ & dsr_MINUS__p8_FSM2_TB; + assign ldtack_PLUS__TB_sync = ldtack_PLUS_ & ldtack_PLUS__p5_FSM2_TB; + assign e_lds_MINUS_TB_sync = e_lds_MINUS_p2_FSM2_TB; + assign e_d_PLUSa_TB_sync = e_d_PLUSa_p6_FSM2_TB; + assign e_dtack_PLUSa_TB_sync = e_dtack_PLUSa_p14_FSM2_TB; + assign e_dtack_PLUS_TB_sync = e_dtack_PLUS_p7_FSM2_TB; + assign e_lds_PLUS_TB_sync = e_lds_PLUS_p2_FSM2_TB; + assign e_d_MINUS_TB_sync = e_d_MINUS_p13_FSM2_TB; + + parameter p10_1HOT_ENCODING = 14'd1; // 14'b00000000000001 // + parameter p10_1HOT_CASEX_ENCODING = 14'bxxxxxxxxxxxxx1; // 14'b00000000000001 // + parameter p9_1HOT_ENCODING = 14'd2; // 14'b00000000000010 // + parameter p9_1HOT_CASEX_ENCODING = 14'bxxxxxxxxxxxx1x; // 14'b00000000000010 // + parameter p8_1HOT_ENCODING = 14'd4; // 14'b00000000000100 // + parameter p8_1HOT_CASEX_ENCODING = 14'bxxxxxxxxxxx1xx; // 14'b00000000000100 // + parameter p7_1HOT_ENCODING = 14'd8; // 14'b00000000001000 // + parameter p7_1HOT_CASEX_ENCODING = 14'bxxxxxxxxxx1xxx; // 14'b00000000001000 // + parameter p6_1HOT_ENCODING = 14'd16; // 14'b00000000010000 // + parameter p6_1HOT_CASEX_ENCODING = 14'bxxxxxxxxx1xxxx; // 14'b00000000010000 // + parameter p5_1HOT_ENCODING = 14'd32; // 14'b00000000100000 // + parameter p5_1HOT_CASEX_ENCODING = 14'bxxxxxxxx1xxxxx; // 14'b00000000100000 // + parameter p4_1HOT_ENCODING = 14'd64; // 14'b00000001000000 // + parameter p4_1HOT_CASEX_ENCODING = 14'bxxxxxxx1xxxxxx; // 14'b00000001000000 // + parameter p1_1HOT_ENCODING = 14'd128; // 14'b00000010000000 // + parameter p1_1HOT_CASEX_ENCODING = 14'bxxxxxx1xxxxxxx; // 14'b00000010000000 // + parameter p0_1HOT_ENCODING = 14'd256; // 14'b00000100000000 // + parameter p0_1HOT_CASEX_ENCODING = 14'bxxxxx1xxxxxxxx; // 14'b00000100000000 // + parameter p15_1HOT_ENCODING = 14'd512; // 14'b00001000000000 // + parameter p15_1HOT_CASEX_ENCODING = 14'bxxxx1xxxxxxxxx; // 14'b00001000000000 // + parameter p14_1HOT_ENCODING = 14'd1024; // 14'b00010000000000 // + parameter p14_1HOT_CASEX_ENCODING = 14'bxxx1xxxxxxxxxx; // 14'b00010000000000 // + parameter p13_1HOT_ENCODING = 14'd2048; // 14'b00100000000000 // + parameter p13_1HOT_CASEX_ENCODING = 14'bxx1xxxxxxxxxxx; // 14'b00100000000000 // + parameter p12_1HOT_ENCODING = 14'd4096; // 14'b01000000000000 // + parameter p12_1HOT_CASEX_ENCODING = 14'bx1xxxxxxxxxxxx; // 14'b01000000000000 // + parameter p11_1HOT_ENCODING = 14'd8192; // 14'b10000000000000 // + parameter p11_1HOT_CASEX_ENCODING = 14'b1xxxxxxxxxxxxx; // 14'b10000000000000 // + + reg [13 : 0] state; + reg [13 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b0; + state[7] <= 1'b1; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + state[12] <= 1'b0; + state[13] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or dsr_PLUS_ or ldtack_PLUSa__TB_sync or dsw_PLUS_ or d_MINUSa__TB_sync or dsw_MINUS__TB_sync or dsr_MINUS__TB_sync or ldtack_PLUS__TB_sync or e_lds_MINUS_TB_sync or e_d_PLUSa_TB_sync or e_dtack_PLUSa_TB_sync or e_dtack_PLUS_TB_sync or e_lds_PLUS_TB_sync or e_d_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_d_PLUS = 1'b0; + e_lds_MINUS = 1'b0; + e_d_PLUSa = 1'b0; + e_dtack_PLUSa = 1'b0; + e_dtack_PLUS = 1'b0; + e_lds_PLUS = 1'b0; + e_d_MINUS = 1'b0; + e_dtack_MINUS = 1'b0; + + casex (state) + 14'bxxxxxxxxxxxxx1: // p10_1HOT_ENCODING: // + begin + e_d_PLUS = 1'b1; + // next_state = p11_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[13] = 1'b1; + end + + 14'bxxxxxxxxxxxx1x: // p9_1HOT_ENCODING: // + begin + if (d_MINUSa__TB_sync) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[6] = 1'b1; + end + end + + 14'bxxxxxxxxxxx1xx: // p8_1HOT_ENCODING: // + begin + if (dsr_MINUS__TB_sync) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + 14'bxxxxxxxxxx1xxx: // p7_1HOT_ENCODING: // + begin + if (e_dtack_PLUS_TB_sync) + begin + e_dtack_PLUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + 14'bxxxxxxxxx1xxxx: // p6_1HOT_ENCODING: // + begin + if (e_d_PLUSa_TB_sync) + begin + e_d_PLUSa = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 14'bxxxxxxxx1xxxxx: // p5_1HOT_ENCODING: // + begin + if (ldtack_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[4] = 1'b1; + end + end + + 14'bxxxxxxx1xxxxxx: // p4_1HOT_ENCODING: // + begin + e_dtack_MINUS = 1'b1; + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[7] = 1'b1; + end + + 14'bxxxxxx1xxxxxxx: // p1_1HOT_ENCODING: // + begin + if (dsr_PLUS_) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[8] = 1'b1; + end + else if (dsw_PLUS_) + begin + // next_state = p10_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[0] = 1'b1; + end + end + + 14'bxxxxx1xxxxxxxx: // p0_1HOT_ENCODING: // + begin + if (e_lds_PLUS_TB_sync) + begin + e_lds_PLUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[5] = 1'b1; + end + end + + 14'bxxxx1xxxxxxxxx: // p15_1HOT_ENCODING: // + begin + if (dsw_MINUS__TB_sync) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[6] = 1'b1; + end + end + + 14'bxxx1xxxxxxxxxx: // p14_1HOT_ENCODING: // + begin + if (e_dtack_PLUSa_TB_sync) + begin + e_dtack_PLUSa = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[9] = 1'b1; + end + end + + 14'bxx1xxxxxxxxxxx: // p13_1HOT_ENCODING: // + begin + if (e_d_MINUS_TB_sync) + begin + e_d_MINUS = 1'b1; + // next_state = p14_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[10] = 1'b1; + end + end + + 14'bx1xxxxxxxxxxxx: // p12_1HOT_ENCODING: // + begin + if (ldtack_PLUSa__TB_sync) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[12] = 1'b0; + next_state[11] = 1'b1; + end + end + + 14'b1xxxxxxxxxxxxx: // p11_1HOT_ENCODING: // + begin + if (e_lds_MINUS_TB_sync) + begin + e_lds_MINUS = 1'b1; + // next_state = p12_1HOT_CASEX_ENCODING; // + next_state[13] = 1'b0; + next_state[12] = 1'b1; + end + end + + default: + begin + next_state = 14'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + ldtack_PLUSa_, ldtack_PLUSa__p12_FSM1_TB, + d_MINUSa_, d_MINUSa__p9_FSM1_TB, + dsw_MINUS_, dsw_MINUS__p15_FSM1_TB, + ldtack_MINUS_, + dsr_MINUS_, dsr_MINUS__p8_FSM1_TB, + ldtack_PLUS_, ldtack_PLUS__p5_FSM1_TB, + e_lds_MINUS, e_lds_MINUS_p11_FSM1_TB, + e_d_PLUSa, e_d_PLUSa_p6_FSM1_TB, + e_dtack_PLUSa, e_dtack_PLUSa_p14_FSM1_TB, + e_dtack_PLUS, e_dtack_PLUS_p7_FSM1_TB, + e_lds_MINUSa, + e_lds_PLUS, e_lds_PLUS_p0_FSM1_TB, + e_d_MINUS, e_d_MINUS_p13_FSM1_TB, + p9, + p8, + p7, + p6, + p5, + p2, + p15, + p14, + p13, + p12 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input ldtack_PLUSa_; + input d_MINUSa_; + input dsw_MINUS_; + input ldtack_MINUS_; + input dsr_MINUS_; + input ldtack_PLUS_; + // Transition Barrier Inputs for input Signals // + input ldtack_PLUSa__p12_FSM1_TB; + input d_MINUSa__p9_FSM1_TB; + input dsw_MINUS__p15_FSM1_TB; + input dsr_MINUS__p8_FSM1_TB; + input ldtack_PLUS__p5_FSM1_TB; + + // Regular output Signals // + output e_lds_MINUS; + output e_d_PLUSa; + output e_dtack_PLUSa; + output e_dtack_PLUS; + output e_lds_MINUSa; + output e_lds_PLUS; + output e_d_MINUS; + // Transition Barrier outputs for output Signals // + input e_lds_MINUS_p11_FSM1_TB; + input e_d_PLUSa_p6_FSM1_TB; + input e_dtack_PLUSa_p14_FSM1_TB; + input e_dtack_PLUS_p7_FSM1_TB; + input e_lds_PLUS_p0_FSM1_TB; + input e_d_MINUS_p13_FSM1_TB; + + // FSMs' Synchronisation output Signals // + output p9; + output p8; + output p7; + output p6; + output p5; + output p2; + output p15; + output p14; + output p13; + output p12; + + reg e_lds_MINUS; + reg e_d_PLUSa; + reg e_dtack_PLUSa; + reg e_dtack_PLUS; + reg e_lds_MINUSa; + reg e_lds_PLUS; + reg e_d_MINUS; + wire p9; + wire p8; + wire p7; + wire p6; + wire p5; + wire p2; + wire p15; + wire p14; + wire p13; + wire p12; + + wire ldtack_PLUSa__TB_sync; + wire d_MINUSa__TB_sync; + wire dsw_MINUS__TB_sync; + wire dsr_MINUS__TB_sync; + wire ldtack_PLUS__TB_sync; + wire e_lds_MINUS_TB_sync; + wire e_d_PLUSa_TB_sync; + wire e_dtack_PLUSa_TB_sync; + wire e_dtack_PLUS_TB_sync; + wire e_lds_PLUS_TB_sync; + wire e_d_MINUS_TB_sync; + assign ldtack_PLUSa__TB_sync = ldtack_PLUSa_ & ldtack_PLUSa__p12_FSM1_TB; + assign d_MINUSa__TB_sync = d_MINUSa_ & d_MINUSa__p9_FSM1_TB; + assign dsw_MINUS__TB_sync = dsw_MINUS_ & dsw_MINUS__p15_FSM1_TB; + assign dsr_MINUS__TB_sync = dsr_MINUS_ & dsr_MINUS__p8_FSM1_TB; + assign ldtack_PLUS__TB_sync = ldtack_PLUS_ & ldtack_PLUS__p5_FSM1_TB; + assign e_lds_MINUS_TB_sync = e_lds_MINUS_p11_FSM1_TB; + assign e_d_PLUSa_TB_sync = e_d_PLUSa_p6_FSM1_TB; + assign e_dtack_PLUSa_TB_sync = e_dtack_PLUSa_p14_FSM1_TB; + assign e_dtack_PLUS_TB_sync = e_dtack_PLUS_p7_FSM1_TB; + assign e_lds_PLUS_TB_sync = e_lds_PLUS_p0_FSM1_TB; + assign e_d_MINUS_TB_sync = e_d_MINUS_p13_FSM1_TB; + + parameter p9_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p9_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxxx1; // 12'b000000000001 // + parameter p8_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p8_1HOT_CASEX_ENCODING = 12'bxxxxxxxxxx1x; // 12'b000000000010 // + parameter p7_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p7_1HOT_CASEX_ENCODING = 12'bxxxxxxxxx1xx; // 12'b000000000100 // + parameter p6_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p6_1HOT_CASEX_ENCODING = 12'bxxxxxxxx1xxx; // 12'b000000001000 // + parameter p5_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p5_1HOT_CASEX_ENCODING = 12'bxxxxxxx1xxxx; // 12'b000000010000 // + parameter p3_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p3_1HOT_CASEX_ENCODING = 12'bxxxxxx1xxxxx; // 12'b000000100000 // + parameter p2_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p2_1HOT_CASEX_ENCODING = 12'bxxxxx1xxxxxx; // 12'b000001000000 // + parameter p16_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p16_1HOT_CASEX_ENCODING = 12'bxxxx1xxxxxxx; // 12'b000010000000 // + parameter p15_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p15_1HOT_CASEX_ENCODING = 12'bxxx1xxxxxxxx; // 12'b000100000000 // + parameter p14_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p14_1HOT_CASEX_ENCODING = 12'bxx1xxxxxxxxx; // 12'b001000000000 // + parameter p13_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p13_1HOT_CASEX_ENCODING = 12'bx1xxxxxxxxxx; // 12'b010000000000 // + parameter p12_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + parameter p12_1HOT_CASEX_ENCODING = 12'b1xxxxxxxxxxx; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p2_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + state[6] <= 1'b1; + state[7] <= 1'b0; + state[8] <= 1'b0; + state[9] <= 1'b0; + state[10] <= 1'b0; + state[11] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or ldtack_PLUSa__TB_sync or d_MINUSa__TB_sync or dsw_MINUS__TB_sync or ldtack_MINUS_ or dsr_MINUS__TB_sync or ldtack_PLUS__TB_sync or e_lds_MINUS_TB_sync or e_d_PLUSa_TB_sync or e_dtack_PLUSa_TB_sync or e_dtack_PLUS_TB_sync or e_lds_PLUS_TB_sync or e_d_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_lds_MINUS = 1'b0; + e_d_PLUSa = 1'b0; + e_dtack_PLUSa = 1'b0; + e_dtack_PLUS = 1'b0; + e_lds_MINUSa = 1'b0; + e_lds_PLUS = 1'b0; + e_d_MINUS = 1'b0; + + casex (state) + 12'bxxxxxxxxxxx1: // p9_1HOT_ENCODING: // + begin + if (d_MINUSa__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxxxxxxxxxx1x: // p8_1HOT_ENCODING: // + begin + if (dsr_MINUS__TB_sync) + begin + // next_state = p9_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 12'bxxxxxxxxx1xx: // p7_1HOT_ENCODING: // + begin + if (e_dtack_PLUS_TB_sync) + begin + e_dtack_PLUS = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + 12'bxxxxxxxx1xxx: // p6_1HOT_ENCODING: // + begin + if (e_d_PLUSa_TB_sync) + begin + e_d_PLUSa = 1'b1; + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + 12'bxxxxxxx1xxxx: // p5_1HOT_ENCODING: // + begin + if (ldtack_PLUS__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 12'bxxxxxx1xxxxx: // p3_1HOT_ENCODING: // + begin + e_lds_MINUSa = 1'b1; + // next_state = p16_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[7] = 1'b1; + end + + 12'bxxxxx1xxxxxx: // p2_1HOT_ENCODING: // + begin + if (e_lds_MINUS_TB_sync) + begin + e_lds_MINUS = 1'b1; + // next_state = p12_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[11] = 1'b1; + end + else if (e_lds_PLUS_TB_sync) + begin + e_lds_PLUS = 1'b1; + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[6] = 1'b0; + next_state[4] = 1'b1; + end + end + + 12'bxxxx1xxxxxxx: // p16_1HOT_ENCODING: // + begin + if (ldtack_MINUS_) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[7] = 1'b0; + next_state[6] = 1'b1; + end + end + + 12'bxxx1xxxxxxxx: // p15_1HOT_ENCODING: // + begin + if (dsw_MINUS__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[8] = 1'b0; + next_state[5] = 1'b1; + end + end + + 12'bxx1xxxxxxxxx: // p14_1HOT_ENCODING: // + begin + if (e_dtack_PLUSa_TB_sync) + begin + e_dtack_PLUSa = 1'b1; + // next_state = p15_1HOT_CASEX_ENCODING; // + next_state[9] = 1'b0; + next_state[8] = 1'b1; + end + end + + 12'bx1xxxxxxxxxx: // p13_1HOT_ENCODING: // + begin + if (e_d_MINUS_TB_sync) + begin + e_d_MINUS = 1'b1; + // next_state = p14_1HOT_CASEX_ENCODING; // + next_state[10] = 1'b0; + next_state[9] = 1'b1; + end + end + + 12'b1xxxxxxxxxxx: // p12_1HOT_ENCODING: // + begin + if (ldtack_PLUSa__TB_sync) + begin + // next_state = p13_1HOT_CASEX_ENCODING; // + next_state[11] = 1'b0; + next_state[10] = 1'b1; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + diff --git a/examples/vem_AC/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/vem_AC/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..4a2bb37 --- /dev/null +++ b/examples/vem_AC/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,588 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + dsr_PLUS_, + ldtack_PLUSa_, ldtack_PLUSa__p12_FSM2_TB, + dsw_PLUS_, + d_MINUSa_, d_MINUSa__p9_FSM2_TB, + dsw_MINUS_, dsw_MINUS__p15_FSM2_TB, + dsr_MINUS_, dsr_MINUS__p8_FSM2_TB, + ldtack_PLUS_, ldtack_PLUS__p5_FSM2_TB, + e_d_PLUS, + e_lds_MINUS, e_lds_MINUS_p2_FSM2_TB, + e_d_PLUSa, e_d_PLUSa_p6_FSM2_TB, + e_dtack_PLUSa, e_dtack_PLUSa_p14_FSM2_TB, + e_dtack_PLUS, e_dtack_PLUS_p7_FSM2_TB, + e_lds_PLUS, e_lds_PLUS_p2_FSM2_TB, + e_d_MINUS, e_d_MINUS_p13_FSM2_TB, + e_dtack_MINUS, + p9, + p8, + p7, + p6, + p5, + p0, + p15, + p14, + p13, + p12, + p11 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input dsr_PLUS_; + input ldtack_PLUSa_; + input dsw_PLUS_; + input d_MINUSa_; + input dsw_MINUS_; + input dsr_MINUS_; + input ldtack_PLUS_; + // Transition Barrier Inputs for input Signals // + input ldtack_PLUSa__p12_FSM2_TB; + input d_MINUSa__p9_FSM2_TB; + input dsw_MINUS__p15_FSM2_TB; + input dsr_MINUS__p8_FSM2_TB; + input ldtack_PLUS__p5_FSM2_TB; + + // Regular output Signals // + output e_d_PLUS; + output e_lds_MINUS; + output e_d_PLUSa; + output e_dtack_PLUSa; + output e_dtack_PLUS; + output e_lds_PLUS; + output e_d_MINUS; + output e_dtack_MINUS; + // Transition Barrier outputs for output Signals // + input e_lds_MINUS_p2_FSM2_TB; + input e_d_PLUSa_p6_FSM2_TB; + input e_dtack_PLUSa_p14_FSM2_TB; + input e_dtack_PLUS_p7_FSM2_TB; + input e_lds_PLUS_p2_FSM2_TB; + input e_d_MINUS_p13_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p9; + output p8; + output p7; + output p6; + output p5; + output p0; + output p15; + output p14; + output p13; + output p12; + output p11; + + reg e_d_PLUS; + reg e_lds_MINUS; + reg e_d_PLUSa; + reg e_dtack_PLUSa; + reg e_dtack_PLUS; + reg e_lds_PLUS; + reg e_d_MINUS; + reg e_dtack_MINUS; + wire p9; + wire p8; + wire p7; + wire p6; + wire p5; + wire p0; + wire p15; + wire p14; + wire p13; + wire p12; + wire p11; + + wire ldtack_PLUSa__TB_sync; + wire d_MINUSa__TB_sync; + wire dsw_MINUS__TB_sync; + wire dsr_MINUS__TB_sync; + wire ldtack_PLUS__TB_sync; + wire e_lds_MINUS_TB_sync; + wire e_d_PLUSa_TB_sync; + wire e_dtack_PLUSa_TB_sync; + wire e_dtack_PLUS_TB_sync; + wire e_lds_PLUS_TB_sync; + wire e_d_MINUS_TB_sync; + assign ldtack_PLUSa__TB_sync = ldtack_PLUSa_ & ldtack_PLUSa__p12_FSM2_TB; + assign d_MINUSa__TB_sync = d_MINUSa_ & d_MINUSa__p9_FSM2_TB; + assign dsw_MINUS__TB_sync = dsw_MINUS_ & dsw_MINUS__p15_FSM2_TB; + assign dsr_MINUS__TB_sync = dsr_MINUS_ & dsr_MINUS__p8_FSM2_TB; + assign ldtack_PLUS__TB_sync = ldtack_PLUS_ & ldtack_PLUS__p5_FSM2_TB; + assign e_lds_MINUS_TB_sync = e_lds_MINUS_p2_FSM2_TB; + assign e_d_PLUSa_TB_sync = e_d_PLUSa_p6_FSM2_TB; + assign e_dtack_PLUSa_TB_sync = e_dtack_PLUSa_p14_FSM2_TB; + assign e_dtack_PLUS_TB_sync = e_dtack_PLUS_p7_FSM2_TB; + assign e_lds_PLUS_TB_sync = e_lds_PLUS_p2_FSM2_TB; + assign e_d_MINUS_TB_sync = e_d_MINUS_p13_FSM2_TB; + + parameter p10_1HOT_ENCODING = 14'd1; // 14'b00000000000001 // + parameter p9_1HOT_ENCODING = 14'd2; // 14'b00000000000010 // + parameter p8_1HOT_ENCODING = 14'd4; // 14'b00000000000100 // + parameter p7_1HOT_ENCODING = 14'd8; // 14'b00000000001000 // + parameter p6_1HOT_ENCODING = 14'd16; // 14'b00000000010000 // + parameter p5_1HOT_ENCODING = 14'd32; // 14'b00000000100000 // + parameter p4_1HOT_ENCODING = 14'd64; // 14'b00000001000000 // + parameter p1_1HOT_ENCODING = 14'd128; // 14'b00000010000000 // + parameter p0_1HOT_ENCODING = 14'd256; // 14'b00000100000000 // + parameter p15_1HOT_ENCODING = 14'd512; // 14'b00001000000000 // + parameter p14_1HOT_ENCODING = 14'd1024; // 14'b00010000000000 // + parameter p13_1HOT_ENCODING = 14'd2048; // 14'b00100000000000 // + parameter p12_1HOT_ENCODING = 14'd4096; // 14'b01000000000000 // + parameter p11_1HOT_ENCODING = 14'd8192; // 14'b10000000000000 // + + reg [13 : 0] state; + reg [13 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p11 = (state == p11_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or dsr_PLUS_ or ldtack_PLUSa__TB_sync or dsw_PLUS_ or d_MINUSa__TB_sync or dsw_MINUS__TB_sync or dsr_MINUS__TB_sync or ldtack_PLUS__TB_sync or e_lds_MINUS_TB_sync or e_d_PLUSa_TB_sync or e_dtack_PLUSa_TB_sync or e_dtack_PLUS_TB_sync or e_lds_PLUS_TB_sync or e_d_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_d_PLUS = 1'b0; + e_lds_MINUS = 1'b0; + e_d_PLUSa = 1'b0; + e_dtack_PLUSa = 1'b0; + e_dtack_PLUS = 1'b0; + e_lds_PLUS = 1'b0; + e_d_MINUS = 1'b0; + e_dtack_MINUS = 1'b0; + + case (state) + p10_1HOT_ENCODING: // 14'b00000000000001: // + begin + e_d_PLUS = 1'b1; + next_state = p11_1HOT_ENCODING; + end + + p9_1HOT_ENCODING: // 14'b00000000000010: // + begin + if (d_MINUSa__TB_sync) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 14'b00000000000100: // + begin + if (dsr_MINUS__TB_sync) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 14'b00000000001000: // + begin + if (e_dtack_PLUS_TB_sync) + begin + e_dtack_PLUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 14'b00000000010000: // + begin + if (e_d_PLUSa_TB_sync) + begin + e_d_PLUSa = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 14'b00000000100000: // + begin + if (ldtack_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 14'b00000001000000: // + begin + e_dtack_MINUS = 1'b1; + next_state = p1_1HOT_ENCODING; + end + + p1_1HOT_ENCODING: // 14'b00000010000000: // + begin + if (dsr_PLUS_) + begin + next_state = p0_1HOT_ENCODING; + end + else if (dsw_PLUS_) + begin + next_state = p10_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 14'b00000100000000: // + begin + if (e_lds_PLUS_TB_sync) + begin + e_lds_PLUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 14'b00001000000000: // + begin + if (dsw_MINUS__TB_sync) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p14_1HOT_ENCODING: // 14'b00010000000000: // + begin + if (e_dtack_PLUSa_TB_sync) + begin + e_dtack_PLUSa = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 14'b00100000000000: // + begin + if (e_d_MINUS_TB_sync) + begin + e_d_MINUS = 1'b1; + next_state = p14_1HOT_ENCODING; + end + end + + p12_1HOT_ENCODING: // 14'b01000000000000: // + begin + if (ldtack_PLUSa__TB_sync) + begin + next_state = p13_1HOT_ENCODING; + end + end + + p11_1HOT_ENCODING: // 14'b10000000000000: // + begin + if (e_lds_MINUS_TB_sync) + begin + e_lds_MINUS = 1'b1; + next_state = p12_1HOT_ENCODING; + end + end + + default: + begin + next_state = 14'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + ldtack_PLUSa_, ldtack_PLUSa__p12_FSM1_TB, + d_MINUSa_, d_MINUSa__p9_FSM1_TB, + dsw_MINUS_, dsw_MINUS__p15_FSM1_TB, + ldtack_MINUS_, + dsr_MINUS_, dsr_MINUS__p8_FSM1_TB, + ldtack_PLUS_, ldtack_PLUS__p5_FSM1_TB, + e_lds_MINUS, e_lds_MINUS_p11_FSM1_TB, + e_d_PLUSa, e_d_PLUSa_p6_FSM1_TB, + e_dtack_PLUSa, e_dtack_PLUSa_p14_FSM1_TB, + e_dtack_PLUS, e_dtack_PLUS_p7_FSM1_TB, + e_lds_MINUSa, + e_lds_PLUS, e_lds_PLUS_p0_FSM1_TB, + e_d_MINUS, e_d_MINUS_p13_FSM1_TB, + p9, + p8, + p7, + p6, + p5, + p2, + p15, + p14, + p13, + p12 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input ldtack_PLUSa_; + input d_MINUSa_; + input dsw_MINUS_; + input ldtack_MINUS_; + input dsr_MINUS_; + input ldtack_PLUS_; + // Transition Barrier Inputs for input Signals // + input ldtack_PLUSa__p12_FSM1_TB; + input d_MINUSa__p9_FSM1_TB; + input dsw_MINUS__p15_FSM1_TB; + input dsr_MINUS__p8_FSM1_TB; + input ldtack_PLUS__p5_FSM1_TB; + + // Regular output Signals // + output e_lds_MINUS; + output e_d_PLUSa; + output e_dtack_PLUSa; + output e_dtack_PLUS; + output e_lds_MINUSa; + output e_lds_PLUS; + output e_d_MINUS; + // Transition Barrier outputs for output Signals // + input e_lds_MINUS_p11_FSM1_TB; + input e_d_PLUSa_p6_FSM1_TB; + input e_dtack_PLUSa_p14_FSM1_TB; + input e_dtack_PLUS_p7_FSM1_TB; + input e_lds_PLUS_p0_FSM1_TB; + input e_d_MINUS_p13_FSM1_TB; + + // FSMs' Synchronisation output Signals // + output p9; + output p8; + output p7; + output p6; + output p5; + output p2; + output p15; + output p14; + output p13; + output p12; + + reg e_lds_MINUS; + reg e_d_PLUSa; + reg e_dtack_PLUSa; + reg e_dtack_PLUS; + reg e_lds_MINUSa; + reg e_lds_PLUS; + reg e_d_MINUS; + wire p9; + wire p8; + wire p7; + wire p6; + wire p5; + wire p2; + wire p15; + wire p14; + wire p13; + wire p12; + + wire ldtack_PLUSa__TB_sync; + wire d_MINUSa__TB_sync; + wire dsw_MINUS__TB_sync; + wire dsr_MINUS__TB_sync; + wire ldtack_PLUS__TB_sync; + wire e_lds_MINUS_TB_sync; + wire e_d_PLUSa_TB_sync; + wire e_dtack_PLUSa_TB_sync; + wire e_dtack_PLUS_TB_sync; + wire e_lds_PLUS_TB_sync; + wire e_d_MINUS_TB_sync; + assign ldtack_PLUSa__TB_sync = ldtack_PLUSa_ & ldtack_PLUSa__p12_FSM1_TB; + assign d_MINUSa__TB_sync = d_MINUSa_ & d_MINUSa__p9_FSM1_TB; + assign dsw_MINUS__TB_sync = dsw_MINUS_ & dsw_MINUS__p15_FSM1_TB; + assign dsr_MINUS__TB_sync = dsr_MINUS_ & dsr_MINUS__p8_FSM1_TB; + assign ldtack_PLUS__TB_sync = ldtack_PLUS_ & ldtack_PLUS__p5_FSM1_TB; + assign e_lds_MINUS_TB_sync = e_lds_MINUS_p11_FSM1_TB; + assign e_d_PLUSa_TB_sync = e_d_PLUSa_p6_FSM1_TB; + assign e_dtack_PLUSa_TB_sync = e_dtack_PLUSa_p14_FSM1_TB; + assign e_dtack_PLUS_TB_sync = e_dtack_PLUS_p7_FSM1_TB; + assign e_lds_PLUS_TB_sync = e_lds_PLUS_p0_FSM1_TB; + assign e_d_MINUS_TB_sync = e_d_MINUS_p13_FSM1_TB; + + parameter p9_1HOT_ENCODING = 12'd1; // 12'b000000000001 // + parameter p8_1HOT_ENCODING = 12'd2; // 12'b000000000010 // + parameter p7_1HOT_ENCODING = 12'd4; // 12'b000000000100 // + parameter p6_1HOT_ENCODING = 12'd8; // 12'b000000001000 // + parameter p5_1HOT_ENCODING = 12'd16; // 12'b000000010000 // + parameter p3_1HOT_ENCODING = 12'd32; // 12'b000000100000 // + parameter p2_1HOT_ENCODING = 12'd64; // 12'b000001000000 // + parameter p16_1HOT_ENCODING = 12'd128; // 12'b000010000000 // + parameter p15_1HOT_ENCODING = 12'd256; // 12'b000100000000 // + parameter p14_1HOT_ENCODING = 12'd512; // 12'b001000000000 // + parameter p13_1HOT_ENCODING = 12'd1024; // 12'b010000000000 // + parameter p12_1HOT_ENCODING = 12'd2048; // 12'b100000000000 // + + reg [11 : 0] state; + reg [11 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p2_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p9 = (state == p9_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p15 = (state == p15_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p14 = (state == p14_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p13 = (state == p13_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p12 = (state == p12_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or ldtack_PLUSa__TB_sync or d_MINUSa__TB_sync or dsw_MINUS__TB_sync or ldtack_MINUS_ or dsr_MINUS__TB_sync or ldtack_PLUS__TB_sync or e_lds_MINUS_TB_sync or e_d_PLUSa_TB_sync or e_dtack_PLUSa_TB_sync or e_dtack_PLUS_TB_sync or e_lds_PLUS_TB_sync or e_d_MINUS_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_lds_MINUS = 1'b0; + e_d_PLUSa = 1'b0; + e_dtack_PLUSa = 1'b0; + e_dtack_PLUS = 1'b0; + e_lds_MINUSa = 1'b0; + e_lds_PLUS = 1'b0; + e_d_MINUS = 1'b0; + + case (state) + p9_1HOT_ENCODING: // 12'b000000000001: // + begin + if (d_MINUSa__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 12'b000000000010: // + begin + if (dsr_MINUS__TB_sync) + begin + next_state = p9_1HOT_ENCODING; + end + end + + p7_1HOT_ENCODING: // 12'b000000000100: // + begin + if (e_dtack_PLUS_TB_sync) + begin + e_dtack_PLUS = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 12'b000000001000: // + begin + if (e_d_PLUSa_TB_sync) + begin + e_d_PLUSa = 1'b1; + next_state = p7_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 12'b000000010000: // + begin + if (ldtack_PLUS__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 12'b000000100000: // + begin + e_lds_MINUSa = 1'b1; + next_state = p16_1HOT_ENCODING; + end + + p2_1HOT_ENCODING: // 12'b000001000000: // + begin + if (e_lds_MINUS_TB_sync) + begin + e_lds_MINUS = 1'b1; + next_state = p12_1HOT_ENCODING; + end + else if (e_lds_PLUS_TB_sync) + begin + e_lds_PLUS = 1'b1; + next_state = p5_1HOT_ENCODING; + end + end + + p16_1HOT_ENCODING: // 12'b000010000000: // + begin + if (ldtack_MINUS_) + begin + next_state = p2_1HOT_ENCODING; + end + end + + p15_1HOT_ENCODING: // 12'b000100000000: // + begin + if (dsw_MINUS__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p14_1HOT_ENCODING: // 12'b001000000000: // + begin + if (e_dtack_PLUSa_TB_sync) + begin + e_dtack_PLUSa = 1'b1; + next_state = p15_1HOT_ENCODING; + end + end + + p13_1HOT_ENCODING: // 12'b010000000000: // + begin + if (e_d_MINUS_TB_sync) + begin + e_d_MINUS = 1'b1; + next_state = p14_1HOT_ENCODING; + end + end + + p12_1HOT_ENCODING: // 12'b100000000000: // + begin + if (ldtack_PLUSa__TB_sync) + begin + next_state = p13_1HOT_ENCODING; + end + end + + default: + begin + next_state = 12'dx; + end + endcase + end +endmodule + diff --git a/examples/vem_AC/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/vem_AC/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..26d256a --- /dev/null +++ b/examples/vem_AC/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,119 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + dsr_PLUS, + d_PLUS, + ldtack_PLUSa, + lds_MINUS, + d_PLUSa, + dtack_PLUSa, + dsw_PLUS, + dtack_PLUS, + d_MINUSa, + dsw_MINUS, + lds_MINUSa, + lds_PLUS, + ldtack_MINUS, + d_MINUS, + dsr_MINUS, + ldtack_PLUS, + dtack_MINUS); + + input clk; + input reset; + input dsr_PLUS; + output d_PLUS; + input ldtack_PLUSa; + output lds_MINUS; + output d_PLUSa; + output dtack_PLUSa; + input dsw_PLUS; + output dtack_PLUS; + input d_MINUSa; + input dsw_MINUS; + output lds_MINUSa; + output lds_PLUS; + input ldtack_MINUS; + output d_MINUS; + input dsr_MINUS; + input ldtack_PLUS; + output dtack_MINUS; + + wire e_d_PLUS_FSM1out, e_lds_MINUS_FSM1out, e_d_PLUSa_FSM1out, e_dtack_PLUSa_FSM1out, e_dtack_PLUS_FSM1out, e_lds_PLUS_FSM1out, e_d_MINUS_FSM1out, e_dtack_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p10_FSM1out, p9_FSM1out, p8_FSM1out, p7_FSM1out, p6_FSM1out, p5_FSM1out, p4_FSM1out, p1_FSM1out, p0_FSM1out, p15_FSM1out, p14_FSM1out, p13_FSM1out, p12_FSM1out, p11_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_lds_MINUS_FSM2out, e_d_PLUSa_FSM2out, e_dtack_PLUSa_FSM2out, e_dtack_PLUS_FSM2out, e_lds_MINUSa_FSM2out, e_lds_PLUS_FSM2out, e_d_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p9_FSM2out, p8_FSM2out, p7_FSM2out, p6_FSM2out, p5_FSM2out, p3_FSM2out, p2_FSM2out, p16_FSM2out, p15_FSM2out, p14_FSM2out, p13_FSM2out, p12_FSM2out; // State Synchronisation output signals of FSM2 // + + assign d_PLUS = e_d_PLUS_FSM1out; + assign lds_MINUS = e_lds_MINUS_FSM1out & e_lds_MINUS_FSM2out; + assign d_PLUSa = e_d_PLUSa_FSM1out & e_d_PLUSa_FSM2out; + assign dtack_PLUSa = e_dtack_PLUSa_FSM1out & e_dtack_PLUSa_FSM2out; + assign dtack_PLUS = e_dtack_PLUS_FSM1out & e_dtack_PLUS_FSM2out; + assign lds_MINUSa = e_lds_MINUSa_FSM2out; + assign lds_PLUS = e_lds_PLUS_FSM1out & e_lds_PLUS_FSM2out; + assign d_MINUS = e_d_MINUS_FSM1out & e_d_MINUS_FSM2out; + assign dtack_MINUS = e_dtack_MINUS_FSM1out; + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .dsr_PLUS_(dsr_PLUS), + .ldtack_PLUSa_(ldtack_PLUSa), .ldtack_PLUSa__p12_FSM2_TB(p12_FSM2out), + .dsw_PLUS_(dsw_PLUS), + .d_MINUSa_(d_MINUSa), .d_MINUSa__p9_FSM2_TB(p9_FSM2out), + .dsw_MINUS_(dsw_MINUS), .dsw_MINUS__p15_FSM2_TB(p15_FSM2out), + .dsr_MINUS_(dsr_MINUS), .dsr_MINUS__p8_FSM2_TB(p8_FSM2out), + .ldtack_PLUS_(ldtack_PLUS), .ldtack_PLUS__p5_FSM2_TB(p5_FSM2out), + .e_d_PLUS(e_d_PLUS_FSM1out), + .e_lds_MINUS(e_lds_MINUS_FSM1out), .e_lds_MINUS_p2_FSM2_TB(p2_FSM2out), + .e_d_PLUSa(e_d_PLUSa_FSM1out), .e_d_PLUSa_p6_FSM2_TB(p6_FSM2out), + .e_dtack_PLUSa(e_dtack_PLUSa_FSM1out), .e_dtack_PLUSa_p14_FSM2_TB(p14_FSM2out), + .e_dtack_PLUS(e_dtack_PLUS_FSM1out), .e_dtack_PLUS_p7_FSM2_TB(p7_FSM2out), + .e_lds_PLUS(e_lds_PLUS_FSM1out), .e_lds_PLUS_p2_FSM2_TB(p2_FSM2out), + .e_d_MINUS(e_d_MINUS_FSM1out), .e_d_MINUS_p13_FSM2_TB(p13_FSM2out), + .e_dtack_MINUS(e_dtack_MINUS_FSM1out), + .p9(p9_FSM1out), + .p8(p8_FSM1out), + .p7(p7_FSM1out), + .p6(p6_FSM1out), + .p5(p5_FSM1out), + .p0(p0_FSM1out), + .p15(p15_FSM1out), + .p14(p14_FSM1out), + .p13(p13_FSM1out), + .p12(p12_FSM1out), + .p11(p11_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .ldtack_PLUSa_(ldtack_PLUSa), .ldtack_PLUSa__p12_FSM1_TB(p12_FSM1out), + .d_MINUSa_(d_MINUSa), .d_MINUSa__p9_FSM1_TB(p9_FSM1out), + .dsw_MINUS_(dsw_MINUS), .dsw_MINUS__p15_FSM1_TB(p15_FSM1out), + .ldtack_MINUS_(ldtack_MINUS), + .dsr_MINUS_(dsr_MINUS), .dsr_MINUS__p8_FSM1_TB(p8_FSM1out), + .ldtack_PLUS_(ldtack_PLUS), .ldtack_PLUS__p5_FSM1_TB(p5_FSM1out), + .e_lds_MINUS(e_lds_MINUS_FSM2out), .e_lds_MINUS_p11_FSM1_TB(p11_FSM1out), + .e_d_PLUSa(e_d_PLUSa_FSM2out), .e_d_PLUSa_p6_FSM1_TB(p6_FSM1out), + .e_dtack_PLUSa(e_dtack_PLUSa_FSM2out), .e_dtack_PLUSa_p14_FSM1_TB(p14_FSM1out), + .e_dtack_PLUS(e_dtack_PLUS_FSM2out), .e_dtack_PLUS_p7_FSM1_TB(p7_FSM1out), + .e_lds_MINUSa(e_lds_MINUSa_FSM2out), + .e_lds_PLUS(e_lds_PLUS_FSM2out), .e_lds_PLUS_p0_FSM1_TB(p0_FSM1out), + .e_d_MINUS(e_d_MINUS_FSM2out), .e_d_MINUS_p13_FSM1_TB(p13_FSM1out), + .p9(p9_FSM2out), + .p8(p8_FSM2out), + .p7(p7_FSM2out), + .p6(p6_FSM2out), + .p5(p5_FSM2out), + .p2(p2_FSM2out), + .p15(p15_FSM2out), + .p14(p14_FSM2out), + .p13(p13_FSM2out), + .p12(p12_FSM2out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/vem_AC/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/vem_AC/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..9c568d8 --- /dev/null +++ b/examples/vem_AC/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,119 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + dsr_PLUS, + d_PLUS, + ldtack_PLUSa, + lds_MINUS, + d_PLUSa, + dtack_PLUSa, + dsw_PLUS, + dtack_PLUS, + d_MINUSa, + dsw_MINUS, + lds_MINUSa, + lds_PLUS, + ldtack_MINUS, + d_MINUS, + dsr_MINUS, + ldtack_PLUS, + dtack_MINUS); + + input clk; + input reset; + input dsr_PLUS; + output d_PLUS; + input ldtack_PLUSa; + output lds_MINUS; + output d_PLUSa; + output dtack_PLUSa; + input dsw_PLUS; + output dtack_PLUS; + input d_MINUSa; + input dsw_MINUS; + output lds_MINUSa; + output lds_PLUS; + input ldtack_MINUS; + output d_MINUS; + input dsr_MINUS; + input ldtack_PLUS; + output dtack_MINUS; + + wire e_d_PLUS_FSM1out, e_lds_MINUS_FSM1out, e_d_PLUSa_FSM1out, e_dtack_PLUSa_FSM1out, e_dtack_PLUS_FSM1out, e_lds_PLUS_FSM1out, e_d_MINUS_FSM1out, e_dtack_MINUS_FSM1out; // Regular output signals of FSM1 // + wire p10_FSM1out, p9_FSM1out, p8_FSM1out, p7_FSM1out, p6_FSM1out, p5_FSM1out, p4_FSM1out, p1_FSM1out, p0_FSM1out, p15_FSM1out, p14_FSM1out, p13_FSM1out, p12_FSM1out, p11_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_lds_MINUS_FSM2out, e_d_PLUSa_FSM2out, e_dtack_PLUSa_FSM2out, e_dtack_PLUS_FSM2out, e_lds_MINUSa_FSM2out, e_lds_PLUS_FSM2out, e_d_MINUS_FSM2out; // Regular output signals of FSM2 // + wire p9_FSM2out, p8_FSM2out, p7_FSM2out, p6_FSM2out, p5_FSM2out, p3_FSM2out, p2_FSM2out, p16_FSM2out, p15_FSM2out, p14_FSM2out, p13_FSM2out, p12_FSM2out; // State Synchronisation output signals of FSM2 // + + assign d_PLUS = e_d_PLUS_FSM1out; + assign lds_MINUS = e_lds_MINUS_FSM1out & e_lds_MINUS_FSM2out; + assign d_PLUSa = e_d_PLUSa_FSM1out & e_d_PLUSa_FSM2out; + assign dtack_PLUSa = e_dtack_PLUSa_FSM1out & e_dtack_PLUSa_FSM2out; + assign dtack_PLUS = e_dtack_PLUS_FSM1out & e_dtack_PLUS_FSM2out; + assign lds_MINUSa = e_lds_MINUSa_FSM2out; + assign lds_PLUS = e_lds_PLUS_FSM1out & e_lds_PLUS_FSM2out; + assign d_MINUS = e_d_MINUS_FSM1out & e_d_MINUS_FSM2out; + assign dtack_MINUS = e_dtack_MINUS_FSM1out; + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .dsr_PLUS_(dsr_PLUS), + .ldtack_PLUSa_(ldtack_PLUSa), .ldtack_PLUSa__p12_FSM2_TB(p12_FSM2out), + .dsw_PLUS_(dsw_PLUS), + .d_MINUSa_(d_MINUSa), .d_MINUSa__p9_FSM2_TB(p9_FSM2out), + .dsw_MINUS_(dsw_MINUS), .dsw_MINUS__p15_FSM2_TB(p15_FSM2out), + .dsr_MINUS_(dsr_MINUS), .dsr_MINUS__p8_FSM2_TB(p8_FSM2out), + .ldtack_PLUS_(ldtack_PLUS), .ldtack_PLUS__p5_FSM2_TB(p5_FSM2out), + .e_d_PLUS(e_d_PLUS_FSM1out), + .e_lds_MINUS(e_lds_MINUS_FSM1out), .e_lds_MINUS_p2_FSM2_TB(p2_FSM2out), + .e_d_PLUSa(e_d_PLUSa_FSM1out), .e_d_PLUSa_p6_FSM2_TB(p6_FSM2out), + .e_dtack_PLUSa(e_dtack_PLUSa_FSM1out), .e_dtack_PLUSa_p14_FSM2_TB(p14_FSM2out), + .e_dtack_PLUS(e_dtack_PLUS_FSM1out), .e_dtack_PLUS_p7_FSM2_TB(p7_FSM2out), + .e_lds_PLUS(e_lds_PLUS_FSM1out), .e_lds_PLUS_p2_FSM2_TB(p2_FSM2out), + .e_d_MINUS(e_d_MINUS_FSM1out), .e_d_MINUS_p13_FSM2_TB(p13_FSM2out), + .e_dtack_MINUS(e_dtack_MINUS_FSM1out), + .p9(p9_FSM1out), + .p8(p8_FSM1out), + .p7(p7_FSM1out), + .p6(p6_FSM1out), + .p5(p5_FSM1out), + .p0(p0_FSM1out), + .p15(p15_FSM1out), + .p14(p14_FSM1out), + .p13(p13_FSM1out), + .p12(p12_FSM1out), + .p11(p11_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .ldtack_PLUSa_(ldtack_PLUSa), .ldtack_PLUSa__p12_FSM1_TB(p12_FSM1out), + .d_MINUSa_(d_MINUSa), .d_MINUSa__p9_FSM1_TB(p9_FSM1out), + .dsw_MINUS_(dsw_MINUS), .dsw_MINUS__p15_FSM1_TB(p15_FSM1out), + .ldtack_MINUS_(ldtack_MINUS), + .dsr_MINUS_(dsr_MINUS), .dsr_MINUS__p8_FSM1_TB(p8_FSM1out), + .ldtack_PLUS_(ldtack_PLUS), .ldtack_PLUS__p5_FSM1_TB(p5_FSM1out), + .e_lds_MINUS(e_lds_MINUS_FSM2out), .e_lds_MINUS_p11_FSM1_TB(p11_FSM1out), + .e_d_PLUSa(e_d_PLUSa_FSM2out), .e_d_PLUSa_p6_FSM1_TB(p6_FSM1out), + .e_dtack_PLUSa(e_dtack_PLUSa_FSM2out), .e_dtack_PLUSa_p14_FSM1_TB(p14_FSM1out), + .e_dtack_PLUS(e_dtack_PLUS_FSM2out), .e_dtack_PLUS_p7_FSM1_TB(p7_FSM1out), + .e_lds_MINUSa(e_lds_MINUSa_FSM2out), + .e_lds_PLUS(e_lds_PLUS_FSM2out), .e_lds_PLUS_p0_FSM1_TB(p0_FSM1out), + .e_d_MINUS(e_d_MINUS_FSM2out), .e_d_MINUS_p13_FSM1_TB(p13_FSM1out), + .p9(p9_FSM2out), + .p8(p8_FSM2out), + .p7(p7_FSM2out), + .p6(p6_FSM2out), + .p5(p5_FSM2out), + .p2(p2_FSM2out), + .p15(p15_FSM2out), + .p14(p14_FSM2out), + .p13(p13_FSM2out), + .p12(p12_FSM2out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/vem_AC/msfsms_tool_bm.log b/examples/vem_AC/msfsms_tool_bm.log new file mode 100644 index 0000000..1f21a87 --- /dev/null +++ b/examples/vem_AC/msfsms_tool_bm.log @@ -0,0 +1,432 @@ +--------------------------------------------------------------------------- +Benchmark: vem_AC/vem.petrinet.AC.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/vem_AC/vem.petrinet.AC.workcraft.g +INFO: Total Nodes : 34 +INFO: Total Transitions : 17 +INFO: Total Places : 17 +INFO: Total Edges : 38 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = p10, Type = Place (is Empty) + Predecessors: dsw_PLUS[6][0] + Successors: d_PLUS[2][0] +PT-Net [1][0]: Label = dsr_PLUS, Type = Transition (is Input) + Predecessors: p1[20][0] + Successors: p0[21][0] +PT-Net [2][0]: Label = d_PLUS, Type = Transition (is Output) + Predecessors: p10[0][0] + Successors: p11[33][0] +PT-Net [2][1]: Label = ldtack_PLUSa, Type = Transition (is Input) + Predecessors: p12[32][0] + Successors: p13[31][0] +PT-Net [3][0]: Label = lds_MINUS, Type = Transition (is Output) + Predecessors: p2[19][0], p11[33][0] + Successors: p12[32][0] +PT-Net [3][1]: Label = d_PLUSa, Type = Transition (is Output) + Predecessors: p6[15][0] + Successors: p7[14][0] +PT-Net [4][0]: Label = dtack_PLUSa, Type = Transition (is Output) + Predecessors: p14[30][0] + Successors: p15[29][0] +PT-Net [6][0]: Label = dsw_PLUS, Type = Transition (is Input) + Predecessors: p1[20][0] + Successors: p10[0][0] +PT-Net [11][0]: Label = dtack_PLUS, Type = Transition (is Output) + Predecessors: p7[14][0] + Successors: p8[13][1] +PT-Net [12][0]: Label = p9, Type = Place (is Empty) + Predecessors: dsr_MINUS[27][0] + Successors: d_MINUSa[13][0] +PT-Net [13][0]: Label = d_MINUSa, Type = Transition (is Input) + Predecessors: p9[12][0] + Successors: p3[18][0], p4[17][0] +PT-Net [13][1]: Label = p8, Type = Place (is Empty) + Predecessors: dtack_PLUS[11][0] + Successors: dsr_MINUS[27][0] +PT-Net [14][0]: Label = p7, Type = Place (is Empty) + Predecessors: d_PLUSa[3][1] + Successors: dtack_PLUS[11][0] +PT-Net [15][0]: Label = p6, Type = Place (is Empty) + Predecessors: ldtack_PLUS[27][1] + Successors: d_PLUSa[3][1] +PT-Net [16][0]: Label = p5, Type = Place (is Empty) + Predecessors: lds_PLUS[25][0] + Successors: ldtack_PLUS[27][1] +PT-Net [17][0]: Label = p4, Type = Place (is Empty) + Predecessors: dsw_MINUS[22][0], d_MINUSa[13][0] + Successors: dtack_MINUS[27][2] +PT-Net [18][0]: Label = p3, Type = Place (is Empty) + Predecessors: dsw_MINUS[22][0], d_MINUSa[13][0] + Successors: lds_MINUSa[22][1] +PT-Net [19][0]: Label = p2, Type = Place (is Marked) + Predecessors: ldtack_MINUS[25][1] + Successors: lds_MINUS[3][0], lds_PLUS[25][0] +PT-Net [20][0]: Label = p1, Type = Place (is Marked) + Predecessors: dtack_MINUS[27][2] + Successors: dsr_PLUS[1][0], dsw_PLUS[6][0] +PT-Net [21][0]: Label = p0, Type = Place (is Empty) + Predecessors: dsr_PLUS[1][0] + Successors: lds_PLUS[25][0] +PT-Net [22][0]: Label = dsw_MINUS, Type = Transition (is Input) + Predecessors: p15[29][0] + Successors: p3[18][0], p4[17][0] +PT-Net [22][1]: Label = lds_MINUSa, Type = Transition (is Output) + Predecessors: p3[18][0] + Successors: p16[28][0] +PT-Net [25][0]: Label = lds_PLUS, Type = Transition (is Output) + Predecessors: p2[19][0], p0[21][0] + Successors: p5[16][0] +PT-Net [25][1]: Label = ldtack_MINUS, Type = Transition (is Input) + Predecessors: p16[28][0] + Successors: p2[19][0] +PT-Net [26][0]: Label = d_MINUS, Type = Transition (is Output) + Predecessors: p13[31][0] + Successors: p14[30][0] +PT-Net [27][0]: Label = dsr_MINUS, Type = Transition (is Input) + Predecessors: p8[13][1] + Successors: p9[12][0] +PT-Net [27][1]: Label = ldtack_PLUS, Type = Transition (is Input) + Predecessors: p5[16][0] + Successors: p6[15][0] +PT-Net [27][2]: Label = dtack_MINUS, Type = Transition (is Output) + Predecessors: p4[17][0] + Successors: p1[20][0] +PT-Net [28][0]: Label = p16, Type = Place (is Empty) + Predecessors: lds_MINUSa[22][1] + Successors: ldtack_MINUS[25][1] +PT-Net [29][0]: Label = p15, Type = Place (is Empty) + Predecessors: dtack_PLUSa[4][0] + Successors: dsw_MINUS[22][0] +PT-Net [30][0]: Label = p14, Type = Place (is Empty) + Predecessors: d_MINUS[26][0] + Successors: dtack_PLUSa[4][0] +PT-Net [31][0]: Label = p13, Type = Place (is Empty) + Predecessors: ldtack_PLUSa[2][1] + Successors: d_MINUS[26][0] +PT-Net [32][0]: Label = p12, Type = Place (is Empty) + Predecessors: lds_MINUS[3][0] + Successors: ldtack_PLUSa[2][1] +PT-Net [33][0]: Label = p11, Type = Place (is Empty) + Predecessors: d_PLUS[2][0] + Successors: lds_MINUS[3][0] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #2 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 29, H-collapsed = 'false' *** +SC S-net (1,1): p10[0][0] +SC S-net (1,2): dsr_PLUS[1][0] + Predecessor Place: p1(1,17)[20,0] + Successor Place: p0(1,18)[21,0] +SC S-net (1,3): d_PLUS[2][0] + Predecessor Place: p10(1,1)[0,0] + Successor Place: p11(1,29)[33,0] +SC S-net (1,4): ldtack_PLUSa[2][1] + Predecessor Place: p12(1,28)[32,0] + Successor Place: p13(1,27)[31,0] +SC S-net (1,5): lds_MINUS[3][0] + Predecessor Place: p11(1,29)[33,0] + Successor Place: p12(1,28)[32,0] +SC S-net (1,6): d_PLUSa[3][1] + Predecessor Place: p6(1,14)[15,0] + Successor Place: p7(1,13)[14,0] +SC S-net (1,7): dtack_PLUSa[4][0] + Predecessor Place: p14(1,26)[30,0] + Successor Place: p15(1,25)[29,0] +SC S-net (1,8): dsw_PLUS[6][0] + Predecessor Place: p1(1,17)[20,0] + Successor Place: p10(1,1)[0,0] +SC S-net (1,9): dtack_PLUS[11][0] + Predecessor Place: p7(1,13)[14,0] + Successor Place: p8(1,12)[13,1] +SC S-net (1,10): p9[12][0] +SC S-net (1,11): d_MINUSa[13][0] + Predecessor Place: p9(1,10)[12,0] + Successor Place: p4(1,16)[17,0] +SC S-net (1,12): p8[13][1] +SC S-net (1,13): p7[14][0] +SC S-net (1,14): p6[15][0] +SC S-net (1,15): p5[16][0] +SC S-net (1,16): p4[17][0] +SC S-net (1,17): p1[20][0] +SC S-net (1,18): p0[21][0] +SC S-net (1,19): dsw_MINUS[22][0] + Predecessor Place: p15(1,25)[29,0] + Successor Place: p4(1,16)[17,0] +SC S-net (1,20): lds_PLUS[25][0] + Predecessor Place: p0(1,18)[21,0] + Successor Place: p5(1,15)[16,0] +SC S-net (1,21): d_MINUS[26][0] + Predecessor Place: p13(1,27)[31,0] + Successor Place: p14(1,26)[30,0] +SC S-net (1,22): dsr_MINUS[27][0] + Predecessor Place: p8(1,12)[13,1] + Successor Place: p9(1,10)[12,0] +SC S-net (1,23): ldtack_PLUS[27][1] + Predecessor Place: p5(1,15)[16,0] + Successor Place: p6(1,14)[15,0] +SC S-net (1,24): dtack_MINUS[27][2] + Predecessor Place: p4(1,16)[17,0] + Successor Place: p1(1,17)[20,0] +SC S-net (1,25): p15[29][0] +SC S-net (1,26): p14[30][0] +SC S-net (1,27): p13[31][0] +SC S-net (1,28): p12[32][0] +SC S-net (1,29): p11[33][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 25, H-collapsed = 'false' *** +SC S-net (2,1): ldtack_PLUSa[2][1] + Predecessor Place: p12(2,25)[32,0] + Successor Place: p13(2,24)[31,0] +SC S-net (2,2): lds_MINUS[3][0] + Predecessor Place: p2(2,13)[19,0] + Successor Place: p12(2,25)[32,0] +SC S-net (2,3): d_PLUSa[3][1] + Predecessor Place: p6(2,10)[15,0] + Successor Place: p7(2,9)[14,0] +SC S-net (2,4): dtack_PLUSa[4][0] + Predecessor Place: p14(2,23)[30,0] + Successor Place: p15(2,22)[29,0] +SC S-net (2,5): dtack_PLUS[11][0] + Predecessor Place: p7(2,9)[14,0] + Successor Place: p8(2,8)[13,1] +SC S-net (2,6): p9[12][0] +SC S-net (2,7): d_MINUSa[13][0] + Predecessor Place: p9(2,6)[12,0] + Successor Place: p3(2,12)[18,0] +SC S-net (2,8): p8[13][1] +SC S-net (2,9): p7[14][0] +SC S-net (2,10): p6[15][0] +SC S-net (2,11): p5[16][0] +SC S-net (2,12): p3[18][0] +SC S-net (2,13): p2[19][0] +SC S-net (2,14): dsw_MINUS[22][0] + Predecessor Place: p15(2,22)[29,0] + Successor Place: p3(2,12)[18,0] +SC S-net (2,15): lds_MINUSa[22][1] + Predecessor Place: p3(2,12)[18,0] + Successor Place: p16(2,21)[28,0] +SC S-net (2,16): lds_PLUS[25][0] + Predecessor Place: p2(2,13)[19,0] + Successor Place: p5(2,11)[16,0] +SC S-net (2,17): ldtack_MINUS[25][1] + Predecessor Place: p16(2,21)[28,0] + Successor Place: p2(2,13)[19,0] +SC S-net (2,18): d_MINUS[26][0] + Predecessor Place: p13(2,24)[31,0] + Successor Place: p14(2,23)[30,0] +SC S-net (2,19): dsr_MINUS[27][0] + Predecessor Place: p8(2,8)[13,1] + Successor Place: p9(2,6)[12,0] +SC S-net (2,20): ldtack_PLUS[27][1] + Predecessor Place: p5(2,11)[16,0] + Successor Place: p6(2,10)[15,0] +SC S-net (2,21): p16[28][0] +SC S-net (2,22): p15[29][0] +SC S-net (2,23): p14[30][0] +SC S-net (2,24): p13[31][0] +SC S-net (2,25): p12[32][0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #2 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #2 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 29, H-Collapsed = 'false' *** +FSM (1,1): Label = p10, Type = State (is Initially Inactive) + Successor(s): e/d_PLUS(0,3) + Predecessor(s): dsw_PLUS/(0,8) +FSM (1,2): Label = dsr_PLUS/, Type = Trans. Function (is Input) + Successor(s): p0(0,18) + Predecessor(s): p1(0,17) +FSM (1,3): Label = e/d_PLUS, Type = Trans. Function (is Output) + Successor(s): p11(0,29) + Predecessor(s): p10(0,1) +FSM (1,4): Label = ldtack_PLUSa/, Type = Trans. Function (is Input) + Successor(s): p13(0,27) + Predecessor(s): p12(0,28) +FSM (1,5): Label = e/lds_MINUS, Type = Trans. Function (is Output) + Successor(s): p12(0,28) + Predecessor(s): p11(0,29) +FSM (1,6): Label = e/d_PLUSa, Type = Trans. Function (is Output) + Successor(s): p7(0,13) + Predecessor(s): p6(0,14) +FSM (1,7): Label = e/dtack_PLUSa, Type = Trans. Function (is Output) + Successor(s): p15(0,25) + Predecessor(s): p14(0,26) +FSM (1,8): Label = dsw_PLUS/, Type = Trans. Function (is Input) + Successor(s): p10(0,1) + Predecessor(s): p1(0,17) +FSM (1,9): Label = e/dtack_PLUS, Type = Trans. Function (is Output) + Successor(s): p8(0,12) + Predecessor(s): p7(0,13) +FSM (1,10): Label = p9, Type = State (is Initially Inactive) + Successor(s): d_MINUSa/(0,11) + Predecessor(s): dsr_MINUS/(0,22) +FSM (1,11): Label = d_MINUSa/, Type = Trans. Function (is Input) + Successor(s): p4(0,16) + Predecessor(s): p9(0,10) +FSM (1,12): Label = p8, Type = State (is Initially Inactive) + Successor(s): dsr_MINUS/(0,22) + Predecessor(s): e/dtack_PLUS(0,9) +FSM (1,13): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/dtack_PLUS(0,9) + Predecessor(s): e/d_PLUSa(0,6) +FSM (1,14): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/d_PLUSa(0,6) + Predecessor(s): ldtack_PLUS/(0,23) +FSM (1,15): Label = p5, Type = State (is Initially Inactive) + Successor(s): ldtack_PLUS/(0,23) + Predecessor(s): e/lds_PLUS(0,20) +FSM (1,16): Label = p4, Type = State (is Initially Inactive) + Successor(s): e/dtack_MINUS(0,24) + Predecessor(s): dsw_MINUS/(0,19) d_MINUSa/(0,11) +FSM (1,17): Label = p1, Type = State (is Initially Active) + Successor(s): dsr_PLUS/(0,2) dsw_PLUS/(0,8) + Predecessor(s): e/dtack_MINUS(0,24) +FSM (1,18): Label = p0, Type = State (is Initially Inactive) + Successor(s): e/lds_PLUS(0,20) + Predecessor(s): dsr_PLUS/(0,2) +FSM (1,19): Label = dsw_MINUS/, Type = Trans. Function (is Input) + Successor(s): p4(0,16) + Predecessor(s): p15(0,25) +FSM (1,20): Label = e/lds_PLUS, Type = Trans. Function (is Output) + Successor(s): p5(0,15) + Predecessor(s): p0(0,18) +FSM (1,21): Label = e/d_MINUS, Type = Trans. Function (is Output) + Successor(s): p14(0,26) + Predecessor(s): p13(0,27) +FSM (1,22): Label = dsr_MINUS/, Type = Trans. Function (is Input) + Successor(s): p9(0,10) + Predecessor(s): p8(0,12) +FSM (1,23): Label = ldtack_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(0,14) + Predecessor(s): p5(0,15) +FSM (1,24): Label = e/dtack_MINUS, Type = Trans. Function (is Output) + Successor(s): p1(0,17) + Predecessor(s): p4(0,16) +FSM (1,25): Label = p15, Type = State (is Initially Inactive) + Successor(s): dsw_MINUS/(0,19) + Predecessor(s): e/dtack_PLUSa(0,7) +FSM (1,26): Label = p14, Type = State (is Initially Inactive) + Successor(s): e/dtack_PLUSa(0,7) + Predecessor(s): e/d_MINUS(0,21) +FSM (1,27): Label = p13, Type = State (is Initially Inactive) + Successor(s): e/d_MINUS(0,21) + Predecessor(s): ldtack_PLUSa/(0,4) +FSM (1,28): Label = p12, Type = State (is Initially Inactive) + Successor(s): ldtack_PLUSa/(0,4) + Predecessor(s): e/lds_MINUS(0,5) +FSM (1,29): Label = p11, Type = State (is Initially Inactive) + Successor(s): e/lds_MINUS(0,5) + Predecessor(s): e/d_PLUS(0,3) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 25, H-Collapsed = 'false' *** +FSM (2,1): Label = ldtack_PLUSa/, Type = Trans. Function (is Input) + Successor(s): p13(1,24) + Predecessor(s): p12(1,25) +FSM (2,2): Label = e/lds_MINUS, Type = Trans. Function (is Output) + Successor(s): p12(1,25) + Predecessor(s): p2(1,13) +FSM (2,3): Label = e/d_PLUSa, Type = Trans. Function (is Output) + Successor(s): p7(1,9) + Predecessor(s): p6(1,10) +FSM (2,4): Label = e/dtack_PLUSa, Type = Trans. Function (is Output) + Successor(s): p15(1,22) + Predecessor(s): p14(1,23) +FSM (2,5): Label = e/dtack_PLUS, Type = Trans. Function (is Output) + Successor(s): p8(1,8) + Predecessor(s): p7(1,9) +FSM (2,6): Label = p9, Type = State (is Initially Inactive) + Successor(s): d_MINUSa/(1,7) + Predecessor(s): dsr_MINUS/(1,19) +FSM (2,7): Label = d_MINUSa/, Type = Trans. Function (is Input) + Successor(s): p3(1,12) + Predecessor(s): p9(1,6) +FSM (2,8): Label = p8, Type = State (is Initially Inactive) + Successor(s): dsr_MINUS/(1,19) + Predecessor(s): e/dtack_PLUS(1,5) +FSM (2,9): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/dtack_PLUS(1,5) + Predecessor(s): e/d_PLUSa(1,3) +FSM (2,10): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/d_PLUSa(1,3) + Predecessor(s): ldtack_PLUS/(1,20) +FSM (2,11): Label = p5, Type = State (is Initially Inactive) + Successor(s): ldtack_PLUS/(1,20) + Predecessor(s): e/lds_PLUS(1,16) +FSM (2,12): Label = p3, Type = State (is Initially Inactive) + Successor(s): e/lds_MINUSa(1,15) + Predecessor(s): dsw_MINUS/(1,14) d_MINUSa/(1,7) +FSM (2,13): Label = p2, Type = State (is Initially Active) + Successor(s): e/lds_MINUS(1,2) e/lds_PLUS(1,16) + Predecessor(s): ldtack_MINUS/(1,17) +FSM (2,14): Label = dsw_MINUS/, Type = Trans. Function (is Input) + Successor(s): p3(1,12) + Predecessor(s): p15(1,22) +FSM (2,15): Label = e/lds_MINUSa, Type = Trans. Function (is Output) + Successor(s): p16(1,21) + Predecessor(s): p3(1,12) +FSM (2,16): Label = e/lds_PLUS, Type = Trans. Function (is Output) + Successor(s): p5(1,11) + Predecessor(s): p2(1,13) +FSM (2,17): Label = ldtack_MINUS/, Type = Trans. Function (is Input) + Successor(s): p2(1,13) + Predecessor(s): p16(1,21) +FSM (2,18): Label = e/d_MINUS, Type = Trans. Function (is Output) + Successor(s): p14(1,23) + Predecessor(s): p13(1,24) +FSM (2,19): Label = dsr_MINUS/, Type = Trans. Function (is Input) + Successor(s): p9(1,6) + Predecessor(s): p8(1,8) +FSM (2,20): Label = ldtack_PLUS/, Type = Trans. Function (is Input) + Successor(s): p6(1,10) + Predecessor(s): p5(1,11) +FSM (2,21): Label = p16, Type = State (is Initially Inactive) + Successor(s): ldtack_MINUS/(1,17) + Predecessor(s): e/lds_MINUSa(1,15) +FSM (2,22): Label = p15, Type = State (is Initially Inactive) + Successor(s): dsw_MINUS/(1,14) + Predecessor(s): e/dtack_PLUSa(1,4) +FSM (2,23): Label = p14, Type = State (is Initially Inactive) + Successor(s): e/dtack_PLUSa(1,4) + Predecessor(s): e/d_MINUS(1,18) +FSM (2,24): Label = p13, Type = State (is Initially Inactive) + Successor(s): e/d_MINUS(1,18) + Predecessor(s): ldtack_PLUSa/(1,1) +FSM (2,25): Label = p12, Type = State (is Initially Inactive) + Successor(s): ldtack_PLUSa/(1,1) + Predecessor(s): e/lds_MINUS(1,2) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +WARNING: FSM(1) produces multiple(2) active states +WARNING: FSM(1) produces multiple(2) active states +WARNING: FSM(1) produces multiple(2) active states +WARNING: FSM(1) produces multiple(2) active states +WARNING: FSM(1) produces multiple(2) active states +WARNING: FSM(1) produces multiple(2) active states +WARNING: FSM(1) produces multiple(2) active states +WARNING: FSM(1) produces multiple(2) active states +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +WARNING: FSM(1) produces multiple(2) active states +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +WARNING: FSM(1) produces multiple(2) active states +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/vem_AC/vem.petrinet.AC.workcraft.g b/examples/vem_AC/vem.petrinet.AC.workcraft.g new file mode 100644 index 0000000..ed1b008 --- /dev/null +++ b/examples/vem_AC/vem.petrinet.AC.workcraft.g @@ -0,0 +1,41 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.5 +.model vme +.inputs dsr_MINUS dsr_PLUS dsw_MINUS dsw_PLUS d_MINUSa ldtack_MINUS ldtack_PLUS ldtack_PLUSa +.outputs lds_MINUS lds_MINUSa lds_PLUS d_MINUS d_PLUS d_PLUSa dtack_MINUS dtack_PLUS dtack_PLUSa +.graph +dsr_PLUS p0 +dsr_MINUS p9 +lds_PLUS p5 +lds_MINUS p12 +dsw_PLUS p10 +dsw_MINUS p3 p4 +d_PLUS p11 +d_PLUSa p7 +d_MINUS p14 +d_MINUSa p3 p4 +ldtack_PLUS p6 +ldtack_PLUSa p13 +ldtack_MINUS p2 +dtack_PLUS p8 +dtack_PLUSa p15 +dtack_MINUS p1 +lds_MINUSa p16 +p1 dsr_PLUS dsw_PLUS +p2 lds_MINUS lds_PLUS +p3 lds_MINUSa +p4 dtack_MINUS +p0 lds_PLUS +p5 ldtack_PLUS +p6 d_PLUSa +p7 dtack_PLUS +p8 dsr_MINUS +p9 d_MINUSa +p10 d_PLUS +p11 lds_MINUS +p12 ldtack_PLUSa +p13 d_MINUS +p14 dtack_PLUSa +p15 dsw_MINUS +p16 ldtack_MINUS +.marking {p1 p2} +.end diff --git a/examples/xor-gate_GN/AsyncMSFSMs/fsm_afsm.afsm b/examples/xor-gate_GN/AsyncMSFSMs/fsm_afsm.afsm new file mode 100644 index 0000000..f4c6a06 --- /dev/null +++ b/examples/xor-gate_GN/AsyncMSFSMs/fsm_afsm.afsm @@ -0,0 +1,38 @@ +### FSMs' Declaration ### + +### Begin of FSM#01 Declaration ### +p7: e_out_M e_out_M_p7_FSM2_TB e_out_M_p7_FSM3_TB p8 +p3: t7_ t7__p4_FSM2_TB t7__p3_FSM3_TB p7 +p3: t8_ t8__p5_FSM2_TB t8__p3_FSM3_TB p7 +p0*: a_M_ a_M__p0_FSM3_TB p3 +p8: t0_ t0__p8_FSM2_TB t0__p8_FSM3_TB p0 +### End of FSM #01 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#02 Declaration ### +p7: e_out_M e_out_M_p7_FSM1_TB e_out_M_p7_FSM3_TB p8 +p4: t5_ t5__p2_FSM3_TB p6 +p4: t7_ t7__p3_FSM1_TB t7__p3_FSM3_TB p7 +p1*: b_M_ p5 +p1*: b_P_ p4 +p6: e_out_P e_out_P_p6_FSM3_TB p8 +p8: t0_ t0__p8_FSM1_TB t0__p8_FSM3_TB p1 +p5: t6_ t6__p2_FSM3_TB p6 +p5: t8_ t8__p3_FSM1_TB t8__p3_FSM3_TB p7 +### End of FSM #02 Declaration ### + +### FSMs' Declaration ### + +### Begin of FSM#03 Declaration ### +p7: e_out_M e_out_M_p7_FSM1_TB e_out_M_p7_FSM2_TB p8 +p6: e_out_P e_out_P_p6_FSM2_TB p8 +p3: t7_ t7__p3_FSM1_TB t7__p4_FSM2_TB p7 +p3: t8_ t8__p3_FSM1_TB t8__p5_FSM2_TB p7 +p0*: a_M_ a_M__p0_FSM1_TB p3 +p0*: a_P_ p2 +p8: t0_ t0__p8_FSM1_TB t0__p8_FSM2_TB p0 +p2: t5_ t5__p4_FSM2_TB p6 +p2: t6_ t6__p5_FSM2_TB p6 +### End of FSM #03 Declaration ### + diff --git a/examples/xor-gate_GN/AsyncMSFSMs/msfsms_afsm.v b/examples/xor-gate_GN/AsyncMSFSMs/msfsms_afsm.v new file mode 100644 index 0000000..486c76c --- /dev/null +++ b/examples/xor-gate_GN/AsyncMSFSMs/msfsms_afsm.v @@ -0,0 +1,90 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + data, + reset, + b_P, + b_M, + t6, + t0, + a_P, + a_M, + t8, + t5, + out_P, + t7, + out_M); + + input reset; + input b_P; + input b_M; + input t6; + input t0; + input a_P; + input a_M; + input t8; + input t5; + output out_P; + input t7; + output out_M; + + wire e_out_M_FSM1out; // Regular output signals of FSM1 // + wire p7_FSM1out, p3_FSM1out, p0_FSM1out, p8_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_out_P_FSM2out, e_out_M_FSM2out; // Regular output signals of FSM2 // + wire p7_FSM2out, p4_FSM2out, p1_FSM2out, p6_FSM2out, p8_FSM2out, p5_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_out_P_FSM3out, e_out_M_FSM3out; // Regular output signals of FSM3 // + wire p7_FSM3out, p6_FSM3out, p3_FSM3out, p0_FSM3out, p8_FSM3out, p2_FSM3out; // State Synchronisation output signals of FSM3 // + + assign out_P = e_out_P_FSM2out & e_out_P_FSM3out; + assign out_M = e_out_M_FSM1out & e_out_M_FSM2out & e_out_M_FSM3out; + + fsm_afsm_01 fsm_afsm_01_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t0_(t0), .t0__p8_FSM2_TB(p8_FSM2out), .t0__p8_FSM3_TB(p8_FSM3out), + .a_M_(a_M), .a_M__p0_FSM3_TB(p0_FSM3out), + .t8_(t8), .t8__p5_FSM2_TB(p5_FSM2out), .t8__p3_FSM3_TB(p3_FSM3out), + .t7_(t7), .t7__p4_FSM2_TB(p4_FSM2out), .t7__p3_FSM3_TB(p3_FSM3out), + .e_out_M(p7_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), .e_out_M_p7_FSM3_TB(p7_FSM3out), + .e/out_M(e/out_M_FSM1out) + ); + + + fsm_afsm_02 fsm_afsm_02_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .b_P_(b_P), + .b_M_(b_M), + .t6_(t6), .t6__p2_FSM3_TB(p2_FSM3out), + .t0_(t0), .t0__p8_FSM1_TB(p8_FSM1out), .t0__p8_FSM3_TB(p8_FSM3out), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), .t8__p3_FSM3_TB(p3_FSM3out), + .t5_(t5), .t5__p2_FSM3_TB(p2_FSM3out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), .t7__p3_FSM3_TB(p3_FSM3out), + .e_out_P(p6_FSM2out), .e_out_P_p6_FSM3_TB(p6_FSM3out), + .e_out_M(p7_FSM2out), .e_out_M_p7_FSM1_TB(p7_FSM1out), .e_out_M_p7_FSM3_TB(p7_FSM3out), + .e/out_P(e/out_P_FSM2out), + .e/out_M(e/out_M_FSM2out) + ); + + + fsm_afsm_03 fsm_afsm_03_inst ( + .sreset(reset) + .EN(clk) + .D(data), + .t6_(t6), .t6__p5_FSM2_TB(p5_FSM2out), + .t0_(t0), .t0__p8_FSM1_TB(p8_FSM1out), .t0__p8_FSM2_TB(p8_FSM2out), + .a_P_(a_P), + .a_M_(a_M), .a_M__p0_FSM1_TB(p0_FSM1out), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), .t8__p5_FSM2_TB(p5_FSM2out), + .t5_(t5), .t5__p4_FSM2_TB(p4_FSM2out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), .t7__p4_FSM2_TB(p4_FSM2out), + .e_out_P(p6_FSM3out), .e_out_P_p6_FSM2_TB(p6_FSM2out), + .e_out_M(p7_FSM3out), .e_out_M_p7_FSM1_TB(p7_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), + .e/out_P(e/out_P_FSM3out), + .e/out_M(e/out_M_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/xor-gate_GN/SyncMealyMSFSMs/fsm_behav_mealy.v b/examples/xor-gate_GN/SyncMealyMSFSMs/fsm_behav_mealy.v new file mode 100644 index 0000000..911841f --- /dev/null +++ b/examples/xor-gate_GN/SyncMealyMSFSMs/fsm_behav_mealy.v @@ -0,0 +1,586 @@ +`timescale 1ns/1ns + +module fsm_mealy_behav_01 ( + clk, + reset, + t0_, t0__p8_FSM2_TB, t0__p8_FSM3_TB, + a_M_, a_M__p0_FSM3_TB, + t8_, t8__p5_FSM2_TB, t8__p3_FSM3_TB, + t7_, t7__p4_FSM2_TB, t7__p3_FSM3_TB, + e_out_M, e_out_M_p7_FSM2_TB, e_out_M_p7_FSM3_TB, + p7, + p3, + p0, + p8 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input a_M_; + input t8_; + input t7_; + // Transition Barrier Inputs for input Signals // + input t0__p8_FSM2_TB, t0__p8_FSM3_TB; + input a_M__p0_FSM3_TB; + input t8__p5_FSM2_TB, t8__p3_FSM3_TB; + input t7__p4_FSM2_TB, t7__p3_FSM3_TB; + + // Regular output Signals // + output e_out_M; + // Transition Barrier outputs for output Signals // + input e_out_M_p7_FSM2_TB, e_out_M_p7_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p3; + output p0; + output p8; + + reg e_out_M; + wire p7; + wire p3; + wire p0; + wire p8; + + wire t0__TB_sync; + wire a_M__TB_sync; + wire t8__TB_sync; + wire t7__TB_sync; + wire e_out_M_TB_sync; + assign t0__TB_sync = t0_ & t0__p8_FSM2_TB & t0__p8_FSM3_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM3_TB; + assign t8__TB_sync = t8_ & t8__p5_FSM2_TB & t8__p3_FSM3_TB; + assign t7__TB_sync = t7_ & t7__p4_FSM2_TB & t7__p3_FSM3_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM2_TB & e_out_M_p7_FSM3_TB; + + parameter p7_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p7_1HOT_CASEX_ENCODING = 4'bxxx1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p3_1HOT_CASEX_ENCODING = 4'bxx1x; // 4'b0010 // + parameter p0_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p0_1HOT_CASEX_ENCODING = 4'bx1xx; // 4'b0100 // + parameter p8_1HOT_ENCODING = 4'd8; // 4'b1000 // + parameter p8_1HOT_CASEX_ENCODING = 4'b1xxx; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p0_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + state[3] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or a_M__TB_sync or t8__TB_sync or t7__TB_sync or e_out_M_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_M = 1'b0; + + casex (state) + 4'bxxx1: // p7_1HOT_ENCODING: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[3] = 1'b1; + end + end + + 4'bxx1x: // p3_1HOT_ENCODING: // + begin + if (t7__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + else if (t8__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 4'bx1xx: // p0_1HOT_ENCODING: // + begin + if (a_M__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + 4'b1xxx: // p8_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_02 ( + clk, + reset, + b_P_, + b_M_, + t6_, t6__p2_FSM3_TB, + t0_, t0__p8_FSM1_TB, t0__p8_FSM3_TB, + t8_, t8__p3_FSM1_TB, t8__p3_FSM3_TB, + t5_, t5__p2_FSM3_TB, + t7_, t7__p3_FSM1_TB, t7__p3_FSM3_TB, + e_out_P, e_out_P_p6_FSM3_TB, + e_out_M, e_out_M_p7_FSM1_TB, e_out_M_p7_FSM3_TB, + p7, + p4, + p6, + p8, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_P_; + input b_M_; + input t6_; + input t0_; + input t8_; + input t5_; + input t7_; + // Transition Barrier Inputs for input Signals // + input t6__p2_FSM3_TB; + input t0__p8_FSM1_TB, t0__p8_FSM3_TB; + input t8__p3_FSM1_TB, t8__p3_FSM3_TB; + input t5__p2_FSM3_TB; + input t7__p3_FSM1_TB, t7__p3_FSM3_TB; + + // Regular output Signals // + output e_out_P; + output e_out_M; + // Transition Barrier outputs for output Signals // + input e_out_P_p6_FSM3_TB; + input e_out_M_p7_FSM1_TB, e_out_M_p7_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p4; + output p6; + output p8; + output p5; + + reg e_out_P; + reg e_out_M; + wire p7; + wire p4; + wire p6; + wire p8; + wire p5; + + wire t6__TB_sync; + wire t0__TB_sync; + wire t8__TB_sync; + wire t5__TB_sync; + wire t7__TB_sync; + wire e_out_P_TB_sync; + wire e_out_M_TB_sync; + assign t6__TB_sync = t6_ & t6__p2_FSM3_TB; + assign t0__TB_sync = t0_ & t0__p8_FSM1_TB & t0__p8_FSM3_TB; + assign t8__TB_sync = t8_ & t8__p3_FSM1_TB & t8__p3_FSM3_TB; + assign t5__TB_sync = t5_ & t5__p2_FSM3_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM1_TB & t7__p3_FSM3_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM3_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM1_TB & e_out_M_p7_FSM3_TB; + + parameter p7_1HOT_ENCODING = 6'd1; // 6'b000001 // + parameter p7_1HOT_CASEX_ENCODING = 6'bxxxxx1; // 6'b000001 // + parameter p4_1HOT_ENCODING = 6'd2; // 6'b000010 // + parameter p4_1HOT_CASEX_ENCODING = 6'bxxxx1x; // 6'b000010 // + parameter p1_1HOT_ENCODING = 6'd4; // 6'b000100 // + parameter p1_1HOT_CASEX_ENCODING = 6'bxxx1xx; // 6'b000100 // + parameter p6_1HOT_ENCODING = 6'd8; // 6'b001000 // + parameter p6_1HOT_CASEX_ENCODING = 6'bxx1xxx; // 6'b001000 // + parameter p8_1HOT_ENCODING = 6'd16; // 6'b010000 // + parameter p8_1HOT_CASEX_ENCODING = 6'bx1xxxx; // 6'b010000 // + parameter p5_1HOT_ENCODING = 6'd32; // 6'b100000 // + parameter p5_1HOT_CASEX_ENCODING = 6'b1xxxxx; // 6'b100000 // + + reg [5 : 0] state; + reg [5 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p1_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b1; + state[3] <= 1'b0; + state[4] <= 1'b0; + state[5] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_P_ or b_M_ or t6__TB_sync or t0__TB_sync or t8__TB_sync or t5__TB_sync or t7__TB_sync or e_out_P_TB_sync or e_out_M_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_P = 1'b0; + e_out_M = 1'b0; + + casex (state) + 6'bxxxxx1: // p7_1HOT_ENCODING: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[4] = 1'b1; + end + end + + 6'bxxxx1x: // p4_1HOT_ENCODING: // + begin + if (t5__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[3] = 1'b1; + end + else if (t7__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[0] = 1'b1; + end + end + + 6'bxxx1xx: // p1_1HOT_ENCODING: // + begin + if (b_M_) + begin + // next_state = p5_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[5] = 1'b1; + end + else if (b_P_) + begin + // next_state = p4_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[1] = 1'b1; + end + end + + 6'bxx1xxx: // p6_1HOT_ENCODING: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[4] = 1'b1; + end + end + + 6'bx1xxxx: // p8_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p1_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[2] = 1'b1; + end + end + + 6'b1xxxxx: // p5_1HOT_ENCODING: // + begin + if (t6__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[3] = 1'b1; + end + else if (t8__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[0] = 1'b1; + end + end + + default: + begin + next_state = 6'dx; + end + endcase + end +endmodule + +module fsm_mealy_behav_03 ( + clk, + reset, + t6_, t6__p5_FSM2_TB, + t0_, t0__p8_FSM1_TB, t0__p8_FSM2_TB, + a_P_, + a_M_, a_M__p0_FSM1_TB, + t8_, t8__p3_FSM1_TB, t8__p5_FSM2_TB, + t5_, t5__p4_FSM2_TB, + t7_, t7__p3_FSM1_TB, t7__p4_FSM2_TB, + e_out_P, e_out_P_p6_FSM2_TB, + e_out_M, e_out_M_p7_FSM1_TB, e_out_M_p7_FSM2_TB, + p7, + p6, + p3, + p0, + p8, + p2 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t6_; + input t0_; + input a_P_; + input a_M_; + input t8_; + input t5_; + input t7_; + // Transition Barrier Inputs for input Signals // + input t6__p5_FSM2_TB; + input t0__p8_FSM1_TB, t0__p8_FSM2_TB; + input a_M__p0_FSM1_TB; + input t8__p3_FSM1_TB, t8__p5_FSM2_TB; + input t5__p4_FSM2_TB; + input t7__p3_FSM1_TB, t7__p4_FSM2_TB; + + // Regular output Signals // + output e_out_P; + output e_out_M; + // Transition Barrier outputs for output Signals // + input e_out_P_p6_FSM2_TB; + input e_out_M_p7_FSM1_TB, e_out_M_p7_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p6; + output p3; + output p0; + output p8; + output p2; + + reg e_out_P; + reg e_out_M; + wire p7; + wire p6; + wire p3; + wire p0; + wire p8; + wire p2; + + wire t6__TB_sync; + wire t0__TB_sync; + wire a_M__TB_sync; + wire t8__TB_sync; + wire t5__TB_sync; + wire t7__TB_sync; + wire e_out_P_TB_sync; + wire e_out_M_TB_sync; + assign t6__TB_sync = t6_ & t6__p5_FSM2_TB; + assign t0__TB_sync = t0_ & t0__p8_FSM1_TB & t0__p8_FSM2_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM1_TB; + assign t8__TB_sync = t8_ & t8__p3_FSM1_TB & t8__p5_FSM2_TB; + assign t5__TB_sync = t5_ & t5__p4_FSM2_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM1_TB & t7__p4_FSM2_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM2_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM1_TB & e_out_M_p7_FSM2_TB; + + parameter p7_1HOT_ENCODING = 6'd1; // 6'b000001 // + parameter p7_1HOT_CASEX_ENCODING = 6'bxxxxx1; // 6'b000001 // + parameter p6_1HOT_ENCODING = 6'd2; // 6'b000010 // + parameter p6_1HOT_CASEX_ENCODING = 6'bxxxx1x; // 6'b000010 // + parameter p3_1HOT_ENCODING = 6'd4; // 6'b000100 // + parameter p3_1HOT_CASEX_ENCODING = 6'bxxx1xx; // 6'b000100 // + parameter p0_1HOT_ENCODING = 6'd8; // 6'b001000 // + parameter p0_1HOT_CASEX_ENCODING = 6'bxx1xxx; // 6'b001000 // + parameter p8_1HOT_ENCODING = 6'd16; // 6'b010000 // + parameter p8_1HOT_CASEX_ENCODING = 6'bx1xxxx; // 6'b010000 // + parameter p2_1HOT_ENCODING = 6'd32; // 6'b100000 // + parameter p2_1HOT_CASEX_ENCODING = 6'b1xxxxx; // 6'b100000 // + + reg [5 : 0] state; + reg [5 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + // state <= p0_1HOT_ENCODING; + state[0] <= 1'b0; + state[1] <= 1'b0; + state[2] <= 1'b0; + state[3] <= 1'b1; + state[4] <= 1'b0; + state[5] <= 1'b0; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_CASEX_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t6__TB_sync or t0__TB_sync or a_P_ or a_M__TB_sync or t8__TB_sync or t5__TB_sync or t7__TB_sync or e_out_P_TB_sync or e_out_M_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_P = 1'b0; + e_out_M = 1'b0; + + casex (state) + 6'bxxxxx1: // p7_1HOT_ENCODING: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[0] = 1'b0; + next_state[4] = 1'b1; + end + end + + 6'bxxxx1x: // p6_1HOT_ENCODING: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + // next_state = p8_1HOT_CASEX_ENCODING; // + next_state[1] = 1'b0; + next_state[4] = 1'b1; + end + end + + 6'bxxx1xx: // p3_1HOT_ENCODING: // + begin + if (t7__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + else if (t8__TB_sync) + begin + // next_state = p7_1HOT_CASEX_ENCODING; // + next_state[2] = 1'b0; + next_state[0] = 1'b1; + end + end + + 6'bxx1xxx: // p0_1HOT_ENCODING: // + begin + if (a_M__TB_sync) + begin + // next_state = p3_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[2] = 1'b1; + end + end + else if (a_P_) + begin + // next_state = p2_1HOT_CASEX_ENCODING; // + next_state[3] = 1'b0; + next_state[5] = 1'b1; + end + + 6'bx1xxxx: // p8_1HOT_ENCODING: // + begin + if (t0__TB_sync) + begin + // next_state = p0_1HOT_CASEX_ENCODING; // + next_state[4] = 1'b0; + next_state[3] = 1'b1; + end + end + + 6'b1xxxxx: // p2_1HOT_ENCODING: // + begin + if (t5__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[1] = 1'b1; + end + else if (t6__TB_sync) + begin + // next_state = p6_1HOT_CASEX_ENCODING; // + next_state[5] = 1'b0; + next_state[1] = 1'b1; + end + end + + default: + begin + next_state = 6'dx; + end + endcase + end +endmodule + diff --git a/examples/xor-gate_GN/SyncMealyMSFSMs/fsm_synth_mealy.v b/examples/xor-gate_GN/SyncMealyMSFSMs/fsm_synth_mealy.v new file mode 100644 index 0000000..ded1cda --- /dev/null +++ b/examples/xor-gate_GN/SyncMealyMSFSMs/fsm_synth_mealy.v @@ -0,0 +1,508 @@ +`timescale 1ns/1ns + +module fsm_mealy_synth_01 ( + clk, + reset, + t0_, t0__p8_FSM2_TB, t0__p8_FSM3_TB, + a_M_, a_M__p0_FSM3_TB, + t8_, t8__p5_FSM2_TB, t8__p3_FSM3_TB, + t7_, t7__p4_FSM2_TB, t7__p3_FSM3_TB, + e_out_M, e_out_M_p7_FSM2_TB, e_out_M_p7_FSM3_TB, + p7, + p3, + p0, + p8 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t0_; + input a_M_; + input t8_; + input t7_; + // Transition Barrier Inputs for input Signals // + input t0__p8_FSM2_TB, t0__p8_FSM3_TB; + input a_M__p0_FSM3_TB; + input t8__p5_FSM2_TB, t8__p3_FSM3_TB; + input t7__p4_FSM2_TB, t7__p3_FSM3_TB; + + // Regular output Signals // + output e_out_M; + // Transition Barrier outputs for output Signals // + input e_out_M_p7_FSM2_TB, e_out_M_p7_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p3; + output p0; + output p8; + + reg e_out_M; + wire p7; + wire p3; + wire p0; + wire p8; + + wire t0__TB_sync; + wire a_M__TB_sync; + wire t8__TB_sync; + wire t7__TB_sync; + wire e_out_M_TB_sync; + assign t0__TB_sync = t0_ & t0__p8_FSM2_TB & t0__p8_FSM3_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM3_TB; + assign t8__TB_sync = t8_ & t8__p5_FSM2_TB & t8__p3_FSM3_TB; + assign t7__TB_sync = t7_ & t7__p4_FSM2_TB & t7__p3_FSM3_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM2_TB & e_out_M_p7_FSM3_TB; + + parameter p7_1HOT_ENCODING = 4'd1; // 4'b0001 // + parameter p3_1HOT_ENCODING = 4'd2; // 4'b0010 // + parameter p0_1HOT_ENCODING = 4'd4; // 4'b0100 // + parameter p8_1HOT_ENCODING = 4'd8; // 4'b1000 // + + reg [3 : 0] state; + reg [3 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p0_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t0__TB_sync or a_M__TB_sync or t8__TB_sync or t7__TB_sync or e_out_M_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_M = 1'b0; + + case (state) + p7_1HOT_ENCODING: // 4'b0001: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 4'b0010: // + begin + if (t7__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + else if (t8__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 4'b0100: // + begin + if (a_M__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 4'b1000: // + begin + if (t0__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + default: + begin + next_state = 4'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_02 ( + clk, + reset, + b_P_, + b_M_, + t6_, t6__p2_FSM3_TB, + t0_, t0__p8_FSM1_TB, t0__p8_FSM3_TB, + t8_, t8__p3_FSM1_TB, t8__p3_FSM3_TB, + t5_, t5__p2_FSM3_TB, + t7_, t7__p3_FSM1_TB, t7__p3_FSM3_TB, + e_out_P, e_out_P_p6_FSM3_TB, + e_out_M, e_out_M_p7_FSM1_TB, e_out_M_p7_FSM3_TB, + p7, + p4, + p6, + p8, + p5 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input b_P_; + input b_M_; + input t6_; + input t0_; + input t8_; + input t5_; + input t7_; + // Transition Barrier Inputs for input Signals // + input t6__p2_FSM3_TB; + input t0__p8_FSM1_TB, t0__p8_FSM3_TB; + input t8__p3_FSM1_TB, t8__p3_FSM3_TB; + input t5__p2_FSM3_TB; + input t7__p3_FSM1_TB, t7__p3_FSM3_TB; + + // Regular output Signals // + output e_out_P; + output e_out_M; + // Transition Barrier outputs for output Signals // + input e_out_P_p6_FSM3_TB; + input e_out_M_p7_FSM1_TB, e_out_M_p7_FSM3_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p4; + output p6; + output p8; + output p5; + + reg e_out_P; + reg e_out_M; + wire p7; + wire p4; + wire p6; + wire p8; + wire p5; + + wire t6__TB_sync; + wire t0__TB_sync; + wire t8__TB_sync; + wire t5__TB_sync; + wire t7__TB_sync; + wire e_out_P_TB_sync; + wire e_out_M_TB_sync; + assign t6__TB_sync = t6_ & t6__p2_FSM3_TB; + assign t0__TB_sync = t0_ & t0__p8_FSM1_TB & t0__p8_FSM3_TB; + assign t8__TB_sync = t8_ & t8__p3_FSM1_TB & t8__p3_FSM3_TB; + assign t5__TB_sync = t5_ & t5__p2_FSM3_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM1_TB & t7__p3_FSM3_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM3_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM1_TB & e_out_M_p7_FSM3_TB; + + parameter p7_1HOT_ENCODING = 6'd1; // 6'b000001 // + parameter p4_1HOT_ENCODING = 6'd2; // 6'b000010 // + parameter p1_1HOT_ENCODING = 6'd4; // 6'b000100 // + parameter p6_1HOT_ENCODING = 6'd8; // 6'b001000 // + parameter p8_1HOT_ENCODING = 6'd16; // 6'b010000 // + parameter p5_1HOT_ENCODING = 6'd32; // 6'b100000 // + + reg [5 : 0] state; + reg [5 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p1_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p4 = (state == p4_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p5 = (state == p5_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or b_P_ or b_M_ or t6__TB_sync or t0__TB_sync or t8__TB_sync or t5__TB_sync or t7__TB_sync or e_out_P_TB_sync or e_out_M_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_P = 1'b0; + e_out_M = 1'b0; + + case (state) + p7_1HOT_ENCODING: // 6'b000001: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p4_1HOT_ENCODING: // 6'b000010: // + begin + if (t5__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + else if (t7__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p1_1HOT_ENCODING: // 6'b000100: // + begin + if (b_M_) + begin + next_state = p5_1HOT_ENCODING; + end + else if (b_P_) + begin + next_state = p4_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 6'b001000: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p8_1HOT_ENCODING: // 6'b010000: // + begin + if (t0__TB_sync) + begin + next_state = p1_1HOT_ENCODING; + end + end + + p5_1HOT_ENCODING: // 6'b100000: // + begin + if (t6__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + else if (t8__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + default: + begin + next_state = 6'dx; + end + endcase + end +endmodule + +module fsm_mealy_synth_03 ( + clk, + reset, + t6_, t6__p5_FSM2_TB, + t0_, t0__p8_FSM1_TB, t0__p8_FSM2_TB, + a_P_, + a_M_, a_M__p0_FSM1_TB, + t8_, t8__p3_FSM1_TB, t8__p5_FSM2_TB, + t5_, t5__p4_FSM2_TB, + t7_, t7__p3_FSM1_TB, t7__p4_FSM2_TB, + e_out_P, e_out_P_p6_FSM2_TB, + e_out_M, e_out_M_p7_FSM1_TB, e_out_M_p7_FSM2_TB, + p7, + p6, + p3, + p0, + p8, + p2 +); + + // Regular Synchronous FSM input Signals // + input clk; + input reset; + + // Regular input Signals // + input t6_; + input t0_; + input a_P_; + input a_M_; + input t8_; + input t5_; + input t7_; + // Transition Barrier Inputs for input Signals // + input t6__p5_FSM2_TB; + input t0__p8_FSM1_TB, t0__p8_FSM2_TB; + input a_M__p0_FSM1_TB; + input t8__p3_FSM1_TB, t8__p5_FSM2_TB; + input t5__p4_FSM2_TB; + input t7__p3_FSM1_TB, t7__p4_FSM2_TB; + + // Regular output Signals // + output e_out_P; + output e_out_M; + // Transition Barrier outputs for output Signals // + input e_out_P_p6_FSM2_TB; + input e_out_M_p7_FSM1_TB, e_out_M_p7_FSM2_TB; + + // FSMs' Synchronisation output Signals // + output p7; + output p6; + output p3; + output p0; + output p8; + output p2; + + reg e_out_P; + reg e_out_M; + wire p7; + wire p6; + wire p3; + wire p0; + wire p8; + wire p2; + + wire t6__TB_sync; + wire t0__TB_sync; + wire a_M__TB_sync; + wire t8__TB_sync; + wire t5__TB_sync; + wire t7__TB_sync; + wire e_out_P_TB_sync; + wire e_out_M_TB_sync; + assign t6__TB_sync = t6_ & t6__p5_FSM2_TB; + assign t0__TB_sync = t0_ & t0__p8_FSM1_TB & t0__p8_FSM2_TB; + assign a_M__TB_sync = a_M_ & a_M__p0_FSM1_TB; + assign t8__TB_sync = t8_ & t8__p3_FSM1_TB & t8__p5_FSM2_TB; + assign t5__TB_sync = t5_ & t5__p4_FSM2_TB; + assign t7__TB_sync = t7_ & t7__p3_FSM1_TB & t7__p4_FSM2_TB; + assign e_out_P_TB_sync = e_out_P_p6_FSM2_TB; + assign e_out_M_TB_sync = e_out_M_p7_FSM1_TB & e_out_M_p7_FSM2_TB; + + parameter p7_1HOT_ENCODING = 6'd1; // 6'b000001 // + parameter p6_1HOT_ENCODING = 6'd2; // 6'b000010 // + parameter p3_1HOT_ENCODING = 6'd4; // 6'b000100 // + parameter p0_1HOT_ENCODING = 6'd8; // 6'b001000 // + parameter p8_1HOT_ENCODING = 6'd16; // 6'b010000 // + parameter p2_1HOT_ENCODING = 6'd32; // 6'b100000 // + + reg [5 : 0] state; + reg [5 : 0] next_state; + + always @(posedge clk) + begin + if (reset) + begin + state <= p0_1HOT_ENCODING; + end + else + begin + state <= next_state; + end + end + + assign p7 = (state == p7_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p6 = (state == p6_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p3 = (state == p3_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p0 = (state == p0_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p8 = (state == p8_1HOT_ENCODING) ? 1'b1 : 1'b0; + assign p2 = (state == p2_1HOT_ENCODING) ? 1'b1 : 1'b0; + + always @(state or t6__TB_sync or t0__TB_sync or a_P_ or a_M__TB_sync or t8__TB_sync or t5__TB_sync or t7__TB_sync or e_out_P_TB_sync or e_out_M_TB_sync) + begin + // MEALY FSMs - Blocking Operations // + next_state = state; + + e_out_P = 1'b0; + e_out_M = 1'b0; + + case (state) + p7_1HOT_ENCODING: // 6'b000001: // + begin + if (e_out_M_TB_sync) + begin + e_out_M = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p6_1HOT_ENCODING: // 6'b000010: // + begin + if (e_out_P_TB_sync) + begin + e_out_P = 1'b1; + next_state = p8_1HOT_ENCODING; + end + end + + p3_1HOT_ENCODING: // 6'b000100: // + begin + if (t7__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + else if (t8__TB_sync) + begin + next_state = p7_1HOT_ENCODING; + end + end + + p0_1HOT_ENCODING: // 6'b001000: // + begin + if (a_M__TB_sync) + begin + next_state = p3_1HOT_ENCODING; + end + end + else if (a_P_) + begin + next_state = p2_1HOT_ENCODING; + end + + p8_1HOT_ENCODING: // 6'b010000: // + begin + if (t0__TB_sync) + begin + next_state = p0_1HOT_ENCODING; + end + end + + p2_1HOT_ENCODING: // 6'b100000: // + begin + if (t5__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + else if (t6__TB_sync) + begin + next_state = p6_1HOT_ENCODING; + end + end + + default: + begin + next_state = 6'dx; + end + endcase + end +endmodule + diff --git a/examples/xor-gate_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v b/examples/xor-gate_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v new file mode 100644 index 0000000..cfa2b6b --- /dev/null +++ b/examples/xor-gate_GN/SyncMealyMSFSMs/msfsms_behav_mealy.v @@ -0,0 +1,97 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + b_P, + b_M, + t6, + t0, + a_P, + a_M, + t8, + t5, + out_P, + t7, + out_M); + + input clk; + input reset; + input b_P; + input b_M; + input t6; + input t0; + input a_P; + input a_M; + input t8; + input t5; + output out_P; + input t7; + output out_M; + + wire e_out_M_FSM1out; // Regular output signals of FSM1 // + wire p7_FSM1out, p3_FSM1out, p0_FSM1out, p8_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_out_P_FSM2out, e_out_M_FSM2out; // Regular output signals of FSM2 // + wire p7_FSM2out, p4_FSM2out, p1_FSM2out, p6_FSM2out, p8_FSM2out, p5_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_out_P_FSM3out, e_out_M_FSM3out; // Regular output signals of FSM3 // + wire p7_FSM3out, p6_FSM3out, p3_FSM3out, p0_FSM3out, p8_FSM3out, p2_FSM3out; // State Synchronisation output signals of FSM3 // + + assign out_P = e_out_P_FSM2out & e_out_P_FSM3out; + assign out_M = e_out_M_FSM1out & e_out_M_FSM2out & e_out_M_FSM3out; + + fsm_mealy_behav_01 fsm_mealy_behav_01_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p8_FSM2_TB(p8_FSM2out), .t0__p8_FSM3_TB(p8_FSM3out), + .a_M_(a_M), .a_M__p0_FSM3_TB(p0_FSM3out), + .t8_(t8), .t8__p5_FSM2_TB(p5_FSM2out), .t8__p3_FSM3_TB(p3_FSM3out), + .t7_(t7), .t7__p4_FSM2_TB(p4_FSM2out), .t7__p3_FSM3_TB(p3_FSM3out), + .e_out_M(e_out_M_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), .e_out_M_p7_FSM3_TB(p7_FSM3out), + .p7(p7_FSM1out), + .p3(p3_FSM1out), + .p0(p0_FSM1out), + .p8(p8_FSM1out) + ); + + + fsm_mealy_behav_02 fsm_mealy_behav_02_inst ( + .clk(clk), + .reset(reset), + .b_P_(b_P), + .b_M_(b_M), + .t6_(t6), .t6__p2_FSM3_TB(p2_FSM3out), + .t0_(t0), .t0__p8_FSM1_TB(p8_FSM1out), .t0__p8_FSM3_TB(p8_FSM3out), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), .t8__p3_FSM3_TB(p3_FSM3out), + .t5_(t5), .t5__p2_FSM3_TB(p2_FSM3out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), .t7__p3_FSM3_TB(p3_FSM3out), + .e_out_P(e_out_P_FSM2out), .e_out_P_p6_FSM3_TB(p6_FSM3out), + .e_out_M(e_out_M_FSM2out), .e_out_M_p7_FSM1_TB(p7_FSM1out), .e_out_M_p7_FSM3_TB(p7_FSM3out), + .p7(p7_FSM2out), + .p4(p4_FSM2out), + .p6(p6_FSM2out), + .p8(p8_FSM2out), + .p5(p5_FSM2out) + ); + + + fsm_mealy_behav_03 fsm_mealy_behav_03_inst ( + .clk(clk), + .reset(reset), + .t6_(t6), .t6__p5_FSM2_TB(p5_FSM2out), + .t0_(t0), .t0__p8_FSM1_TB(p8_FSM1out), .t0__p8_FSM2_TB(p8_FSM2out), + .a_P_(a_P), + .a_M_(a_M), .a_M__p0_FSM1_TB(p0_FSM1out), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), .t8__p5_FSM2_TB(p5_FSM2out), + .t5_(t5), .t5__p4_FSM2_TB(p4_FSM2out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), .t7__p4_FSM2_TB(p4_FSM2out), + .e_out_P(e_out_P_FSM3out), .e_out_P_p6_FSM2_TB(p6_FSM2out), + .e_out_M(e_out_M_FSM3out), .e_out_M_p7_FSM1_TB(p7_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), + .p7(p7_FSM3out), + .p6(p6_FSM3out), + .p3(p3_FSM3out), + .p0(p0_FSM3out), + .p8(p8_FSM3out), + .p2(p2_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/xor-gate_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v b/examples/xor-gate_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v new file mode 100644 index 0000000..51ab61c --- /dev/null +++ b/examples/xor-gate_GN/SyncMealyMSFSMs/msfsms_synth_mealy.v @@ -0,0 +1,97 @@ +`timescale 1ns/1ns + +module msfsms_mealy ( + clk, + reset, + b_P, + b_M, + t6, + t0, + a_P, + a_M, + t8, + t5, + out_P, + t7, + out_M); + + input clk; + input reset; + input b_P; + input b_M; + input t6; + input t0; + input a_P; + input a_M; + input t8; + input t5; + output out_P; + input t7; + output out_M; + + wire e_out_M_FSM1out; // Regular output signals of FSM1 // + wire p7_FSM1out, p3_FSM1out, p0_FSM1out, p8_FSM1out; // State Synchronisation output signals of FSM1 // + wire e_out_P_FSM2out, e_out_M_FSM2out; // Regular output signals of FSM2 // + wire p7_FSM2out, p4_FSM2out, p1_FSM2out, p6_FSM2out, p8_FSM2out, p5_FSM2out; // State Synchronisation output signals of FSM2 // + wire e_out_P_FSM3out, e_out_M_FSM3out; // Regular output signals of FSM3 // + wire p7_FSM3out, p6_FSM3out, p3_FSM3out, p0_FSM3out, p8_FSM3out, p2_FSM3out; // State Synchronisation output signals of FSM3 // + + assign out_P = e_out_P_FSM2out & e_out_P_FSM3out; + assign out_M = e_out_M_FSM1out & e_out_M_FSM2out & e_out_M_FSM3out; + + fsm_mealy_synth_01 fsm_mealy_synth_01_inst ( + .clk(clk), + .reset(reset), + .t0_(t0), .t0__p8_FSM2_TB(p8_FSM2out), .t0__p8_FSM3_TB(p8_FSM3out), + .a_M_(a_M), .a_M__p0_FSM3_TB(p0_FSM3out), + .t8_(t8), .t8__p5_FSM2_TB(p5_FSM2out), .t8__p3_FSM3_TB(p3_FSM3out), + .t7_(t7), .t7__p4_FSM2_TB(p4_FSM2out), .t7__p3_FSM3_TB(p3_FSM3out), + .e_out_M(e_out_M_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), .e_out_M_p7_FSM3_TB(p7_FSM3out), + .p7(p7_FSM1out), + .p3(p3_FSM1out), + .p0(p0_FSM1out), + .p8(p8_FSM1out) + ); + + + fsm_mealy_synth_02 fsm_mealy_synth_02_inst ( + .clk(clk), + .reset(reset), + .b_P_(b_P), + .b_M_(b_M), + .t6_(t6), .t6__p2_FSM3_TB(p2_FSM3out), + .t0_(t0), .t0__p8_FSM1_TB(p8_FSM1out), .t0__p8_FSM3_TB(p8_FSM3out), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), .t8__p3_FSM3_TB(p3_FSM3out), + .t5_(t5), .t5__p2_FSM3_TB(p2_FSM3out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), .t7__p3_FSM3_TB(p3_FSM3out), + .e_out_P(e_out_P_FSM2out), .e_out_P_p6_FSM3_TB(p6_FSM3out), + .e_out_M(e_out_M_FSM2out), .e_out_M_p7_FSM1_TB(p7_FSM1out), .e_out_M_p7_FSM3_TB(p7_FSM3out), + .p7(p7_FSM2out), + .p4(p4_FSM2out), + .p6(p6_FSM2out), + .p8(p8_FSM2out), + .p5(p5_FSM2out) + ); + + + fsm_mealy_synth_03 fsm_mealy_synth_03_inst ( + .clk(clk), + .reset(reset), + .t6_(t6), .t6__p5_FSM2_TB(p5_FSM2out), + .t0_(t0), .t0__p8_FSM1_TB(p8_FSM1out), .t0__p8_FSM2_TB(p8_FSM2out), + .a_P_(a_P), + .a_M_(a_M), .a_M__p0_FSM1_TB(p0_FSM1out), + .t8_(t8), .t8__p3_FSM1_TB(p3_FSM1out), .t8__p5_FSM2_TB(p5_FSM2out), + .t5_(t5), .t5__p4_FSM2_TB(p4_FSM2out), + .t7_(t7), .t7__p3_FSM1_TB(p3_FSM1out), .t7__p4_FSM2_TB(p4_FSM2out), + .e_out_P(e_out_P_FSM3out), .e_out_P_p6_FSM2_TB(p6_FSM2out), + .e_out_M(e_out_M_FSM3out), .e_out_M_p7_FSM1_TB(p7_FSM1out), .e_out_M_p7_FSM2_TB(p7_FSM2out), + .p7(p7_FSM3out), + .p6(p6_FSM3out), + .p3(p3_FSM3out), + .p0(p0_FSM3out), + .p8(p8_FSM3out), + .p2(p2_FSM3out) + ); + +endmodule // msfsms_mealy // diff --git a/examples/xor-gate_GN/msfsms_tool_bm.log b/examples/xor-gate_GN/msfsms_tool_bm.log new file mode 100644 index 0000000..9e94055 --- /dev/null +++ b/examples/xor-gate_GN/msfsms_tool_bm.log @@ -0,0 +1,316 @@ +--------------------------------------------------------------------------- +Benchmark: xor-gate_GN/xor-gate.pterinet.GN.workcraft.g +--------------------------------------------------------------------------- +[MSFSMs Syntehsis Tool v1.00]%> read_graph /home/dvaliantzas/WORK/MSFSMs/Benchmarks/GitHub_Repo/xor-gate_GN/xor-gate.pterinet.GN.workcraft.g +INFO: Total Nodes : 20 +INFO: Total Transitions : 11 +INFO: Total Places : 9 +INFO: Total Edges : 27 +INFO-TCL: Successfully loaded Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> list_petrinet +PT-Net [0][0]: Label = p7, Type = Place (is Empty) + Predecessors: t8[9][1], t7[16][1] + Successors: out_M[17][0] +PT-Net [1][0]: Label = p4, Type = Place (is Empty) + Predecessors: b_P[2][1] + Successors: t5[10][0], t7[16][1] +PT-Net [2][0]: Label = p1, Type = Place (is Marked) + Predecessors: t0[5][0] + Successors: b_M[3][0], b_P[2][1] +PT-Net [2][1]: Label = b_P, Type = Transition (is Input) + Predecessors: p1[2][0] + Successors: p4[1][0] +PT-Net [3][0]: Label = b_M, Type = Transition (is Input) + Predecessors: p1[2][0] + Successors: p5[14][0] +PT-Net [3][1]: Label = t6, Type = Transition (is Input) + Predecessors: p5[14][0], p2[15][0] + Successors: p6[7][0] +PT-Net [5][0]: Label = t0, Type = Transition (is Input) + Predecessors: p8[13][0] + Successors: p0[9][0], p1[2][0] +PT-Net [5][1]: Label = a_P, Type = Transition (is Input) + Predecessors: p0[9][0] + Successors: p2[15][0] +PT-Net [6][0]: Label = a_M, Type = Transition (is Input) + Predecessors: p0[9][0] + Successors: p3[8][0] +PT-Net [7][0]: Label = p6, Type = Place (is Empty) + Predecessors: t5[10][0], t6[3][1] + Successors: out_P[16][0] +PT-Net [8][0]: Label = p3, Type = Place (is Empty) + Predecessors: a_M[6][0] + Successors: t7[16][1], t8[9][1] +PT-Net [9][0]: Label = p0, Type = Place (is Marked) + Predecessors: t0[5][0] + Successors: a_M[6][0], a_P[5][1] +PT-Net [9][1]: Label = t8, Type = Transition (is Input) + Predecessors: p3[8][0], p5[14][0] + Successors: p7[0][0] +PT-Net [10][0]: Label = t5, Type = Transition (is Input) + Predecessors: p4[1][0], p2[15][0] + Successors: p6[7][0] +PT-Net [13][0]: Label = p8, Type = Place (is Empty) + Predecessors: out_P[16][0], out_M[17][0] + Successors: t0[5][0] +PT-Net [14][0]: Label = p5, Type = Place (is Empty) + Predecessors: b_M[3][0] + Successors: t6[3][1], t8[9][1] +PT-Net [15][0]: Label = p2, Type = Place (is Empty) + Predecessors: a_P[5][1] + Successors: t5[10][0], t6[3][1] +PT-Net [16][0]: Label = out_P, Type = Transition (is Output) + Predecessors: p6[7][0] + Successors: p8[13][0] +PT-Net [16][1]: Label = t7, Type = Transition (is Input) + Predecessors: p4[1][0], p3[8][0] + Successors: p7[0][0] +PT-Net [17][0]: Label = out_M, Type = Transition (is Output) + Predecessors: p7[0][0] + Successors: p8[13][0] + +INFO-TCL: Successfully displayed Petri-Net. +[MSFSMs Syntehsis Tool v1.00]%> get_SC_Snets +INFO-TCL: Successfully extracted #3 Strongly Connected S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> list_SC_Snet -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #1, Total Nodes = 9, H-collapsed = 'false' *** +SC S-net (1,1): p7[0][0] +SC S-net (1,2): t0[5][0] + Predecessor Place: p8(1,7)[13,0] + Successor Place: p0(1,5)[9,0] +SC S-net (1,3): a_M[6][0] + Predecessor Place: p0(1,5)[9,0] + Successor Place: p3(1,4)[8,0] +SC S-net (1,4): p3[8][0] +SC S-net (1,5): p0[9][0] +SC S-net (1,6): t8[9][1] + Predecessor Place: p3(1,4)[8,0] + Successor Place: p7(1,1)[0,0] +SC S-net (1,7): p8[13][0] +SC S-net (1,8): t7[16][1] + Predecessor Place: p3(1,4)[8,0] + Successor Place: p7(1,1)[0,0] +SC S-net (1,9): out_M[17][0] + Predecessor Place: p7(1,1)[0,0] + Successor Place: p8(1,7)[13,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #2, Total Nodes = 15, H-collapsed = 'false' *** +SC S-net (2,1): p7[0][0] +SC S-net (2,2): p4[1][0] +SC S-net (2,3): p1[2][0] +SC S-net (2,4): b_P[2][1] + Predecessor Place: p1(2,3)[2,0] + Successor Place: p4(2,2)[1,0] +SC S-net (2,5): b_M[3][0] + Predecessor Place: p1(2,3)[2,0] + Successor Place: p5(2,12)[14,0] +SC S-net (2,6): t6[3][1] + Predecessor Place: p5(2,12)[14,0] + Successor Place: p6(2,8)[7,0] +SC S-net (2,7): t0[5][0] + Predecessor Place: p8(2,11)[13,0] + Successor Place: p1(2,3)[2,0] +SC S-net (2,8): p6[7][0] +SC S-net (2,9): t8[9][1] + Predecessor Place: p5(2,12)[14,0] + Successor Place: p7(2,1)[0,0] +SC S-net (2,10): t5[10][0] + Predecessor Place: p4(2,2)[1,0] + Successor Place: p6(2,8)[7,0] +SC S-net (2,11): p8[13][0] +SC S-net (2,12): p5[14][0] +SC S-net (2,13): out_P[16][0] + Predecessor Place: p6(2,8)[7,0] + Successor Place: p8(2,11)[13,0] +SC S-net (2,14): t7[16][1] + Predecessor Place: p4(2,2)[1,0] + Successor Place: p7(2,1)[0,0] +SC S-net (2,15): out_M[17][0] + Predecessor Place: p7(2,1)[0,0] + Successor Place: p8(2,11)[13,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** SC S-net #3, Total Nodes = 15, H-collapsed = 'false' *** +SC S-net (3,1): p7[0][0] +SC S-net (3,2): t6[3][1] + Predecessor Place: p2(3,12)[15,0] + Successor Place: p6(3,6)[7,0] +SC S-net (3,3): t0[5][0] + Predecessor Place: p8(3,11)[13,0] + Successor Place: p0(3,8)[9,0] +SC S-net (3,4): a_P[5][1] + Predecessor Place: p0(3,8)[9,0] + Successor Place: p2(3,12)[15,0] +SC S-net (3,5): a_M[6][0] + Predecessor Place: p0(3,8)[9,0] + Successor Place: p3(3,7)[8,0] +SC S-net (3,6): p6[7][0] +SC S-net (3,7): p3[8][0] +SC S-net (3,8): p0[9][0] +SC S-net (3,9): t8[9][1] + Predecessor Place: p3(3,7)[8,0] + Successor Place: p7(3,1)[0,0] +SC S-net (3,10): t5[10][0] + Predecessor Place: p2(3,12)[15,0] + Successor Place: p6(3,6)[7,0] +SC S-net (3,11): p8[13][0] +SC S-net (3,12): p2[15][0] +SC S-net (3,13): out_P[16][0] + Predecessor Place: p6(3,6)[7,0] + Successor Place: p8(3,11)[13,0] +SC S-net (3,14): t7[16][1] + Predecessor Place: p3(3,7)[8,0] + Successor Place: p7(3,1)[0,0] +SC S-net (3,15): out_M[17][0] + Predecessor Place: p7(3,1)[0,0] + Successor Place: p8(3,11)[13,0] +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Successfully displayed all SC S-Nets. +[MSFSMs Syntehsis Tool v1.00]%> create_FSMs -hcollapse +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #1 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #2 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO: Creation of FSM #3 (of #3 total). +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- + +INFO-TCL: Created FSMs and Horizontally Collapsed redundant FSMs. +[MSFSMs Syntehsis Tool v1.00]%> list_FSM -all +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 1, Total list Entries = 9, H-Collapsed = 'false' *** +FSM (1,1): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/out_M(0,9) + Predecessor(s): t8/(0,6) t7/(0,8) +FSM (1,2): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p0(0,5) + Predecessor(s): p8(0,7) +FSM (1,3): Label = a_M/, Type = Trans. Function (is Input) + Successor(s): p3(0,4) + Predecessor(s): p0(0,5) +FSM (1,4): Label = p3, Type = State (is Initially Inactive) + Successor(s): t7/(0,8) t8/(0,6) + Predecessor(s): a_M/(0,3) +FSM (1,5): Label = p0, Type = State (is Initially Active) + Successor(s): a_M/(0,3) + Predecessor(s): t0/(0,2) +FSM (1,6): Label = t8/, Type = Trans. Function (is Input) + Successor(s): p7(0,1) + Predecessor(s): p3(0,4) +FSM (1,7): Label = p8, Type = State (is Initially Inactive) + Successor(s): t0/(0,2) + Predecessor(s): e/out_M(0,9) +FSM (1,8): Label = t7/, Type = Trans. Function (is Input) + Successor(s): p7(0,1) + Predecessor(s): p3(0,4) +FSM (1,9): Label = e/out_M, Type = Trans. Function (is Output) + Successor(s): p8(0,7) + Predecessor(s): p7(0,1) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 2, Total list Entries = 15, H-Collapsed = 'false' *** +FSM (2,1): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/out_M(1,15) + Predecessor(s): t8/(1,9) t7/(1,14) +FSM (2,2): Label = p4, Type = State (is Initially Inactive) + Successor(s): t5/(1,10) t7/(1,14) + Predecessor(s): b_P/(1,4) +FSM (2,3): Label = p1, Type = State (is Initially Active) + Successor(s): b_M/(1,5) b_P/(1,4) + Predecessor(s): t0/(1,7) +FSM (2,4): Label = b_P/, Type = Trans. Function (is Input) + Successor(s): p4(1,2) + Predecessor(s): p1(1,3) +FSM (2,5): Label = b_M/, Type = Trans. Function (is Input) + Successor(s): p5(1,12) + Predecessor(s): p1(1,3) +FSM (2,6): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p6(1,8) + Predecessor(s): p5(1,12) +FSM (2,7): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p1(1,3) + Predecessor(s): p8(1,11) +FSM (2,8): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/out_P(1,13) + Predecessor(s): t5/(1,10) t6/(1,6) +FSM (2,9): Label = t8/, Type = Trans. Function (is Input) + Successor(s): p7(1,1) + Predecessor(s): p5(1,12) +FSM (2,10): Label = t5/, Type = Trans. Function (is Input) + Successor(s): p6(1,8) + Predecessor(s): p4(1,2) +FSM (2,11): Label = p8, Type = State (is Initially Inactive) + Successor(s): t0/(1,7) + Predecessor(s): e/out_P(1,13) e/out_M(1,15) +FSM (2,12): Label = p5, Type = State (is Initially Inactive) + Successor(s): t6/(1,6) t8/(1,9) + Predecessor(s): b_M/(1,5) +FSM (2,13): Label = e/out_P, Type = Trans. Function (is Output) + Successor(s): p8(1,11) + Predecessor(s): p6(1,8) +FSM (2,14): Label = t7/, Type = Trans. Function (is Input) + Successor(s): p7(1,1) + Predecessor(s): p4(1,2) +FSM (2,15): Label = e/out_M, Type = Trans. Function (is Output) + Successor(s): p8(1,11) + Predecessor(s): p7(1,1) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +*** FSM 3, Total list Entries = 15, H-Collapsed = 'false' *** +FSM (3,1): Label = p7, Type = State (is Initially Inactive) + Successor(s): e/out_M(2,15) + Predecessor(s): t8/(2,9) t7/(2,14) +FSM (3,2): Label = t6/, Type = Trans. Function (is Input) + Successor(s): p6(2,6) + Predecessor(s): p2(2,12) +FSM (3,3): Label = t0/, Type = Trans. Function (is Input) + Successor(s): p0(2,8) + Predecessor(s): p8(2,11) +FSM (3,4): Label = a_P/, Type = Trans. Function (is Input) + Successor(s): p2(2,12) + Predecessor(s): p0(2,8) +FSM (3,5): Label = a_M/, Type = Trans. Function (is Input) + Successor(s): p3(2,7) + Predecessor(s): p0(2,8) +FSM (3,6): Label = p6, Type = State (is Initially Inactive) + Successor(s): e/out_P(2,13) + Predecessor(s): t5/(2,10) t6/(2,2) +FSM (3,7): Label = p3, Type = State (is Initially Inactive) + Successor(s): t7/(2,14) t8/(2,9) + Predecessor(s): a_M/(2,5) +FSM (3,8): Label = p0, Type = State (is Initially Active) + Successor(s): a_M/(2,5) a_P/(2,4) + Predecessor(s): t0/(2,3) +FSM (3,9): Label = t8/, Type = Trans. Function (is Input) + Successor(s): p7(2,1) + Predecessor(s): p3(2,7) +FSM (3,10): Label = t5/, Type = Trans. Function (is Input) + Successor(s): p6(2,6) + Predecessor(s): p2(2,12) +FSM (3,11): Label = p8, Type = State (is Initially Inactive) + Successor(s): t0/(2,3) + Predecessor(s): e/out_P(2,13) e/out_M(2,15) +FSM (3,12): Label = p2, Type = State (is Initially Inactive) + Successor(s): t5/(2,10) t6/(2,2) + Predecessor(s): a_P/(2,4) +FSM (3,13): Label = e/out_P, Type = Trans. Function (is Output) + Successor(s): p8(2,11) + Predecessor(s): p6(2,6) +FSM (3,14): Label = t7/, Type = Trans. Function (is Input) + Successor(s): p7(2,1) + Predecessor(s): p3(2,7) +FSM (3,15): Label = e/out_M, Type = Trans. Function (is Output) + Successor(s): p8(2,11) + Predecessor(s): p7(2,1) +--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- +INFO-TCL: Successfully displayed all FSMs. +[MSFSMs Syntehsis Tool v1.00]%> synchronise_FSMs +INFO-TCL: Successfully Synchronised FSMs. +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format afsm_format -dlatchimplementation clk EN data D +INFO-TCL: FSMs Verilog Code generated for "-format afsm_format". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_behav +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_behav". +[MSFSMs Syntehsis Tool v1.00]%> write_MSFSMs -format syncmealy_synth +INFO-TCL: FSMs Verilog Code generated for "-format syncmealy_synth". +[MSFSMs Syntehsis Tool v1.00]%> quit diff --git a/examples/xor-gate_GN/xor-gate.pterinet.GN.workcraft.g b/examples/xor-gate_GN/xor-gate.pterinet.GN.workcraft.g new file mode 100644 index 0000000..787137e --- /dev/null +++ b/examples/xor-gate_GN/xor-gate.pterinet.GN.workcraft.g @@ -0,0 +1,28 @@ +# STG file generated by Workcraft 3 (Return of the Hazard), version 3.2.0 +.model xorGATE +.dummy a_M a_P b_M b_P +.outputs out_M out_P +.internal t0 t5 t6 t8 t7 +.graph +b_M p5 +t0 p0 p1 +a_M p3 +b_P p4 +out_P p8 +t5 p6 +t6 p6 +t8 p7 +a_P p2 +out_M p8 +t7 p7 +p7 out_M +p4 t5 t7 +p3 t7 t8 +p1 b_M b_P +p0 a_M a_P +p6 out_P +p5 t6 t8 +p8 t0 +p2 t5 t6 +.marking {p0 p1} +.end