vcd.md

vcd

Value change dump

Simple, human readable, but not very efficient not general.

Defined in the Verilog standard, and generated by the $dump* Verilog commands.

Represents signals in function of type on all observed wires.

https://en.wikipedia.org/wiki/Value_change_dump

Defined with the VHDL standard.

Can be generated by VHDL simulations tools like GHDL.

ASCII based.

Only shows signals that changed at each point in time.

Use VCD as input for Verilog simulation:

• https://groups.google.com/forum/#!topic/comp.lang.verilog/LZOfMlAhr5U says signal strength is missing. But this is notably possible in extended VCD.

VCD tooling

Dominant open source GUI viewer: GTKWave: https://sourceforge.net/projects/gtkwave/

Other viewers:

• CLI! https://github.com/cirosantilli/vcdvcd/blob/master/vcdcat
• browser
  • https://github.com/dosadih/weView
  • https://github.com/rakeshkkrao/BAR-waveform-viewer

Parser libraries:

• https://github.com/GordonMcGregor/vcd_parser
• https://pypi.python.org/pypi/Verilog_VCD not version tracked? Already contacted author but no reply.

Writers (but why?):

• https://github.com/SanDisk-Open-Source/pyvcd

Cross Module Reference

XMR

Unique path to a wire / module, e.g.:

top.submodule1.another_module.thewire

Simple canonical way to refer to a given thing in the design.

Enumerations

Strings

It would be awesome to be able to view the names of enumerations in VCD.

GTKWave supports this, but I don't know how to automate it:

• http://stackoverflow.com/a/9661682/895245
• https://sourceforge.net/p/gtkwave/mailman/gtkwave-users/thread/[email protected]/