-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathReceiver_TB.vhd
206 lines (176 loc) · 5.16 KB
/
Receiver_TB.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Receiver_TB IS
END Receiver_TB;
ARCHITECTURE behavior OF Receiver_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Receiver
PORT(
RESET_RECEIV: IN std_logic;
CLOCK : IN std_logic;
RX_IN : IN std_logic;
STOP_RX_IN : IN std_logic;
DATA_OUT : OUT std_logic_vector(6 downto 0);
RTS_OUT : OUT std_logic;
END_ERR_OUT : OUT std_logic;
PAR_ERR_OUT : OUT std_logic;
READY_OUT : OUT std_logic
);
END COMPONENT;
--Inputs
signal L_RESET_RECEIV : std_logic;
signal L_CLOCK : std_logic;
signal L_RX_IN : std_logic;
signal L_STOP_RX_IN : std_logic;
--Outputs
signal L_DATA_OUT : std_logic_vector(6 downto 0);
signal L_RTS_OUT : std_logic;
signal L_END_ERR_OUT : std_logic;
signal L_PAR_ERR_OUT : std_logic;
signal L_READY_OUT : std_logic;
-- Clock period definitions
constant Tick_period : time := 320 ns;
constant CLOCK_period : time := Tick_period/16;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Receiver PORT MAP (
RESET_RECEIV => L_RESET_RECEIV,
CLOCK => L_CLOCK,
RX_IN => L_RX_IN,
STOP_RX_IN => L_STOP_RX_IN,
DATA_OUT => L_DATA_OUT,
RTS_OUT => L_RTS_OUT,
END_ERR_OUT => L_END_ERR_OUT,
PAR_ERR_OUT => L_PAR_ERR_OUT,
READY_OUT => L_READY_OUT
);
-- Clock process definitions
CLOCK_process :process
begin
L_CLOCK <= '0';
wait for CLOCK_period/2;
L_CLOCK <= '1';
wait for CLOCK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
L_RESET_RECEIV <= '1';
wait for 100 ns;
L_RESET_RECEIV <= '0';
L_STOP_RX_IN <= '0';
L_RX_IN <= '1';
wait for Tick_period*2;
-- Start bit = 0, D_IN = "0010101", Parity bit = 1, stop bit = 1
L_RX_IN <= '0'; --start bit (320ns)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(6)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(5)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(4)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(3)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(2)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(1)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(0)
wait for Tick_period;
L_RX_IN <= '1'; --parity bit
wait for Tick_period;
L_RX_IN <= '1'; --stop bit
wait for Tick_period*3;
-- Start bit = 0, D_IN = "1100100", Parity bit = 0(ERR), stop bit = 1
L_RX_IN <= '0'; --start bit (2240ns)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(6)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(5)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(4)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(3)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(2)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(1)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(0)
wait for Tick_period;
L_RX_IN <= '0'; --parity bit
wait for Tick_period;
L_RX_IN <= '1'; --stop bit
wait for Tick_period*3;
-- Start bit = 0, D_IN = "1010110", Parity bit = 0, stop bit = 1
-- stop_rx=1 dopo 2 tick period
L_RX_IN <= '0'; --start bit (4160ns)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(6)
wait for Tick_period;
L_STOP_RX_IN <= '1';
L_RX_IN <= '0'; --D_IN(5)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(4)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(3)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(2)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(1)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(0)
wait for Tick_period;
L_RX_IN <= '0'; --parity bit
wait for Tick_period;
L_RX_IN <= '1'; --stop bit
wait for Tick_period*6;
L_STOP_RX_IN <= '0';
wait for Tick_period;
-- Start bit = 0, D_IN = "1100100", Parity bit = 1, stop bit = 0 (ERR)
L_RX_IN <= '0'; --start bit (6080ns)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(6)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(5)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(4)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(3)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(2)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(1)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(0)
wait for Tick_period;
L_RX_IN <= '1'; --parity bit
wait for Tick_period;
L_RX_IN <= '0'; --stop bit
wait for Tick_period;
-- Start bit = 0, D_IN = "1101110", Parity bit = 1, stop bit = 1 (ERR)
L_RX_IN <= '0'; --start bit (6080ns)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(6)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(5)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(4)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(3)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(2)
wait for Tick_period;
L_RX_IN <= '1'; --D_IN(1)
wait for Tick_period;
L_RX_IN <= '0'; --D_IN(0)
wait for Tick_period;
L_RX_IN <= '1'; --parity bit
wait for Tick_period;
L_RX_IN <= '1'; --stop bit
wait for Tick_period;
wait;
end process;
END;