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Updates for upcoming 6.1.0 release:
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- Bump versions
- Add release history
- Fix core tests lit execution (returns 1 on failing tests)
- Provide define CMSIS_DISABLE_DEPRECATED to hide deprecated symbols
- Add link to CM52 TRM fo documentation
- Update compiler versions used for verification
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JonatanAntoni committed May 6, 2024
1 parent 9742ff5 commit 0c84a51
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Showing 17 changed files with 156 additions and 117 deletions.
26 changes: 5 additions & 21 deletions ARM.CMSIS.pdsc
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Expand Up @@ -13,28 +13,12 @@
<url>https://www.keil.com/pack/</url>

<releases>
<release version="6.0.0">
<release version="6.1.0">
Active development ...
CMSIS-Core: 6.0.0
- Core(M) and Core(A) joined into single Core component
- Core header files reworked, aligned with TRMs
- Previously deprecated features removed
- Dropped support for Arm Compiler 5
CMSIS-DSP: Moved into separate pack!
CMSIS-NN: Moved into separate pack!
CMSIS-RTOS: Deprecated and removed!
- RTX4 Deprecated and removed!
CMSIS-RTOS2: 2.3.0 (see revision history for details)
- OS Tick moved from Device to CMSIS class
- Provisional support for processor affinity in SMP systems
- RTX5 Moved into separate pack!
CMSIS-Driver: 2.9.0 (see revision history for details)
- Updated VIO API 1.0.0
- Added GPIO Driver API 1.0.0
CMSIS-DAP: Moved into separate pack!
CMSIS-Pack: Moved to Open-CMSIS-Pack!
CMSIS-SVD: Moved to Open-CMSIS-Pack!
Utilities: Moved to CMSIS-Toolbox!
CMSIS-Core: 6.1.0
- Added support for Cortex-M52
- Added deprecated CoreDebug symbols for CMSIS 5 compatibility
- Added define CMSIS_DISABLE_DEPRECATED to hide deprecated symbols
</release>
<release version="5.9.0" date="2022-05-02">
CMSIS-Core(M): 5.6.0
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8 changes: 6 additions & 2 deletions CMSIS/Core/Include/core_cm23.h
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Expand Up @@ -1282,6 +1282,8 @@ typedef struct
@{
*/

#ifndef CMSIS_DISABLE_DEPRECATED

#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

Expand Down Expand Up @@ -1374,11 +1376,13 @@ typedef struct
#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos
#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#endif

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */


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6 changes: 5 additions & 1 deletion CMSIS/Core/Include/core_cm3.h
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Expand Up @@ -1404,6 +1404,8 @@ typedef struct
@{
*/

#ifndef CMSIS_DISABLE_DEPRECATED

#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

Expand Down Expand Up @@ -1500,7 +1502,9 @@ typedef struct
#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos
#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */

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8 changes: 6 additions & 2 deletions CMSIS/Core/Include/core_cm33.h
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Expand Up @@ -2102,6 +2102,8 @@ typedef struct
@{
*/

#ifndef CMSIS_DISABLE_DEPRECATED

#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

Expand Down Expand Up @@ -2227,11 +2229,13 @@ typedef struct
#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos
#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#endif

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */


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8 changes: 6 additions & 2 deletions CMSIS/Core/Include/core_cm35p.h
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Expand Up @@ -2102,6 +2102,8 @@ typedef struct
@{
*/

#ifndef CMSIS_DISABLE_DEPRECATED

#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

Expand Down Expand Up @@ -2227,11 +2229,13 @@ typedef struct
#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos
#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#endif

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */


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6 changes: 5 additions & 1 deletion CMSIS/Core/Include/core_cm4.h
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Expand Up @@ -1583,6 +1583,8 @@ typedef struct
@{
*/

#ifndef CMSIS_DISABLE_DEPRECATED

#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

Expand Down Expand Up @@ -1679,7 +1681,9 @@ typedef struct
#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos
#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */

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8 changes: 6 additions & 2 deletions CMSIS/Core/Include/core_cm55.h
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Expand Up @@ -3614,6 +3614,8 @@ typedef struct
#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

#ifndef CMSIS_DISABLE_DEPRECATED

/* deprecated, CMSIS_5 backward compatibility */
typedef struct
{
Expand Down Expand Up @@ -3773,11 +3775,13 @@ typedef struct
#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos
#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#endif

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */


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6 changes: 5 additions & 1 deletion CMSIS/Core/Include/core_cm7.h
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Expand Up @@ -1802,6 +1802,8 @@ typedef struct
@{
*/

#ifndef CMSIS_DISABLE_DEPRECATED

#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

Expand Down Expand Up @@ -1898,7 +1900,9 @@ typedef struct
#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos
#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */

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6 changes: 4 additions & 2 deletions CMSIS/Core/Include/core_cm85.h
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Expand Up @@ -3797,11 +3797,13 @@ typedef struct
#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos
#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
#endif

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */


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6 changes: 5 additions & 1 deletion CMSIS/Core/Include/core_sc300.h
Original file line number Diff line number Diff line change
Expand Up @@ -1390,6 +1390,8 @@ typedef struct
#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk

#ifndef CMSIS_DISABLE_DEPRECATED

/* deprecated, CMSIS_5 backward compatibility */
typedef struct
{
Expand Down Expand Up @@ -1483,7 +1485,9 @@ typedef struct
#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos
#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk

#define CoreDebug ((CoreDebug_Type *) DCB_BASE)
#define CoreDebug ((CoreDebug_Type *) DCB_BASE)

#endif // CMSIS_DISABLE_DEPRECATED

/*@} */

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2 changes: 1 addition & 1 deletion CMSIS/Core/Test/build.py
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Expand Up @@ -77,7 +77,7 @@ def timestamp():
return datetime.now().strftime('%Y%m%d%H%M%S')


@matrix_command(test_report=FileReport(f"lit.xml") | JUnitReport())
@matrix_command(exit_code=[0, 1], test_report=FileReport(f"lit.xml") | JUnitReport())
def run_lit(toolchain, device, optimize):
return ["lit", "--xunit-xml-output", f"lit.xml", "-D", f"toolchain={toolchain}", "-D", f"device={device}", "-D", f"optimize={optimize}", "src" ]

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2 changes: 1 addition & 1 deletion CMSIS/Documentation/Doxygen/Core/Core.dxy.in
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Expand Up @@ -47,7 +47,7 @@ PROJECT_NAME = "CMSIS-Core (Cortex-M)"
# could be handy for archiving the generated documentation or if some version
# control system is used.

PROJECT_NUMBER = "Version 6.0.0"
PROJECT_NUMBER = "Version 6.1.0"

# Using the PROJECT_BRIEF tag one can provide an optional one line description
# for a project that appears at the top of each page and should give viewer a
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