Enable CoreValidation on CM52 with LLVM/Clang 19

CMSIS/Core/Test/README.md

@@ -71,19 +71,16 @@ Currently, the following build configurations are provided:
 
 ## Prerequisites
 
-The following tools are required to build and run the CoreValidation tests:
-
-- [CMSIS-Toolbox 2.1.0](https://artifacts.keil.arm.com/cmsis-toolbox/2.1.0/)*
-- [CMake 3.25.2](https://cmake.org/download/)*
-- [Ninja 1.10.2](https://github.com/ninja-build/ninja/releases)*
-- [Arm Compiler 6.22](https://artifacts.tools.arm.com/arm-compiler/6.22/45/)*
-- [GCC Compiler 13.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/13.2.1/)*
-- [Clang Compiler 18.1.3](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-18.1.3)*
-- [Arm Virtual Hardware for Cortex-M based on FastModels 11.22.39](https://artifacts.keil.arm.com/avh/11.22.39/)*
+The following tools are required to build and run the Core tests:
+
+- [Arm Compiler 6.23](https://artifacts.tools.arm.com/arm-compiler/6.23/32/)*
+- [GCC Compiler 14.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/14.2.1/)*
+- [Clang Compiler 19.1.5](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-19.1.5)*
 - [Python 3.9](https://www.python.org/downloads/)
 - [LLVM FileCheck](https://github.com/llvm/llvm-project/releases/)
   - Ubuntu package `llvm-<version>-tools`
   - MacOS Homebrew formula `llvm`
+    Symlink FileCheck binary `ln -s /opt/homebrew/opt/llvm/bin/FileCheck /opt/homebrew/bin`
 
 The executables need to be present on the `PATH`.
 For tools distributed via vcpkg (*) this can be achieved automatically:
@@ -126,7 +123,7 @@ GCC         Cortex-M3  none        33/33
 
 The summary lists the amount of test cases executed and passed.
 
-## Analyse failing test cases
+## Analyze failing test cases
 
 In case of failing test cases, one can run a single test case with verbose output like this:
 
@@ -146,7 +143,7 @@ Testing Time: 0.10s
   Passed: 1
 ```
 
-The output reveales wich commands are chained and their error output if any.
+The output reveals which commands are chained and their error output if any.
 
 Failing FileCheck requires in detail analysis of the `// CHECK` annotations in the test source file
 against the `llvm-objdump` output of the test compilation.

CMSIS/Core/Test/lit.cfg.py

@@ -791,38 +791,38 @@ def get_ccflags(self):
 
 class Toolchain_Clang(Toolchain):
     TARGET = {
-        'CM0': 'thumbv6m-none-unknown-eabi',
-        'CM0plus': 'thumbv6m-none-unknown-eabi',
-        'CM3': 'thumbv7m-none-unknown-eabi',
-        'CM4': 'thumbv7em-none-unknown-eabi',
-        'CM4FP': 'thumbv7em-none-unknown-eabihf',
-        'CM7': 'thumbv7em-none-unknown-eabi',
-        'CM7SP': 'thumbv7em-none-unknown-eabihf',
-        'CM7DP': 'thumbv7em-none-unknown-eabihf',
-        'CM23': 'thumbv8m.base-none-unknown-eabi',
-        'CM23S': 'thumbv8m.base-none-unknown-eabi',
-        'CM23NS': 'thumbv8m.base-none-unknown-eabi',
-        'CM33': 'thumbv8m.main-none-unknown-eabihf',
-        'CM33S': 'thumbv8m.main-none-unknown-eabihf',
-        'CM33NS': 'thumbv8m.main-none-unknown-eabihf',
-        'CM35P': 'thumbv8m.main-none-unknown-eabihf',
-        'CM35PS': 'thumbv8m.main-none-unknown-eabihf',
-        'CM35PNS': 'thumbv8m.main-none-unknown-eabihf',
-        'CM52': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM52S': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM52NS': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM55': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM55S': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM55NS': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM85': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM85S': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM85NS': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CA5': 'armv7-none-unknown-eabi',
-        'CA5neon': 'armv7-none-unknown-eabihf',
-        'CA7': 'armv7-none-unknown-eabi',
-        'CA7neon': 'armv7-none-unknown-eabihf',
-        'CA9': 'armv7-none-unknown-eabi',
-        'CA9neon': 'armv7-none-unknown-eabihf'
+        'CM0': 'thumbv6m-none-eabi',
+        'CM0plus': 'thumbv6m-none-eabi',
+        'CM3': 'thumbv7m-none-eabi',
+        'CM4': 'thumbv7em-none-eabi',
+        'CM4FP': 'thumbv7em-none-eabihf',
+        'CM7': 'thumbv7em-none-eabi',
+        'CM7SP': 'thumbv7em-none-eabihf',
+        'CM7DP': 'thumbv7em-none-eabihf',
+        'CM23': 'thumbv8m.base-none-eabi',
+        'CM23S': 'thumbv8m.base-none-eabi',
+        'CM23NS': 'thumbv8m.base-none-eabi',
+        'CM33': 'thumbv8m.main-none-eabihf',
+        'CM33S': 'thumbv8m.main-none-eabihf',
+        'CM33NS': 'thumbv8m.main-none-eabihf',
+        'CM35P': 'thumbv8m.main-none-eabihf',
+        'CM35PS': 'thumbv8m.main-none-eabihf',
+        'CM35PNS': 'thumbv8m.main-none-eabihf',
+        'CM52': 'thumbv8.1m.main-none-eabihf',
+        'CM52S': 'thumbv8.1m.main-none-eabihf',
+        'CM52NS': 'thumbv8.1m.main-none-eabihf',
+        'CM55': 'thumbv8.1m.main-none-eabihf',
+        'CM55S': 'thumbv8.1m.main-none-eabihf',
+        'CM55NS': 'thumbv8.1m.main-none-eabihf',
+        'CM85': 'thumbv8.1m.main-none-eabihf',
+        'CM85S': 'thumbv8.1m.main-none-eabihf',
+        'CM85NS': 'thumbv8.1m.main-none-eabihf',
+        'CA5': 'armv7-none-eabi',
+        'CA5neon': 'armv7-none-eabihf',
+        'CA7': 'armv7-none-eabi',
+        'CA7neon': 'armv7-none-eabihf',
+        'CA9': 'armv7-none-eabi',
+        'CA9neon': 'armv7-none-eabihf'
     }
     OPTIMIZE = {
         'none': '-O1',

CMSIS/Core/Test/src/ror.c

@@ -7,8 +7,8 @@ static volatile uint32_t b = 2u;
 
 void ror() {
     // CHECK-LABEL: <ror>:
-    // CHECK-THUMB: ror{{s|.w}} {{r[0-9]+}}, {{r[0-9]+}}
-    // CHECK-ARM: ror {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-THUMB: ror{{ne|s|.w}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-ARM: {{ror|rorne}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
     volatile uint32_t c = __ROR(a, b);
     // CHECK: {{(bx lr)|(pop {.*pc})}}
 }

CMSIS/Core/Test/vcpkg-configuration.json

@@ -1,15 +1,14 @@
 {
     "registries": [
-      {
-        "kind": "artifact",
-        "location": "https://artifacts.tools.arm.com/vcpkg-registry",
-        "name": "arm"
-      }
+        {
+            "name": "arm",
+            "kind": "artifact",
+            "location": "https://artifacts.tools.arm.com/vcpkg-registry"
+        }
     ],
     "requires": {
-      "arm:compilers/arm/armclang":"^6.22.0",
-      "arm:compilers/arm/arm-none-eabi-gcc": "^13.2.1",
-      "arm:compilers/arm/llvm-embedded": "^18.1.3"
+        "arm:compilers/arm/armclang": "6.23.0",
+        "arm:compilers/arm/arm-none-eabi-gcc": "14.2.1",
+        "arm:compilers/arm/llvm-embedded": "19.1.5"
     }
-  }
-
+}

CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml

@@ -5,7 +5,7 @@ layer:
   components:
     # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
     - component: ARM::CMSIS:CORE
-    - component: Device:Startup
+    - component: Device:Startup&C Startup
     - component: Device:IRQ Controller:GIC
 
   misc:

CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml

@@ -5,7 +5,7 @@ layer:
   components:
     # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
     - component: ARM::CMSIS:CORE
-    - component: Device:Startup
+    - component: Device:Startup&C Startup
     - component: Device:IRQ Controller:GIC
 
   misc:

CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml

@@ -5,7 +5,7 @@ layer:
   components:
     # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
     - component: ARM::CMSIS:CORE
-    - component: Device:Startup
+    - component: Device:Startup&C Startup
     - component: Device:IRQ Controller:GIC
 
   misc:

CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt

@@ -14,8 +14,6 @@ armcortexm7ct.semihosting-cwd=""                      # (string, init-time) defa
 armcortexm7ct.DP_FLOAT=1                              # (bool  , init-time) default = '1'      : Support 8-byte floats
 armcortexm7ct.dcache-size=32768                       # (int   , init-time) default = '0x8000' : L1 D-cache size in bytes
 armcortexm7ct.dcache-state_modelled=1                 # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation
-armcortexm7ct.dcache-ways=4                           # (int   , init-time) default = '0x4'    : L1 D-cache ways (sets are implicit from size)
 armcortexm7ct.icache-size=32768                       # (int   , init-time) default = '0x8000' : L1 I-cache size in bytes
 armcortexm7ct.icache-state_modelled=1                 # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation
-armcortexm7ct.icache-ways=2                           # (int   , init-time) default = '0x2'    : L1 I-cache ways (sets are implicit from size)
 #----------------------------------------------------------------------------------------------

CMSIS/CoreValidation/Layer/Target/CM85/model_config.txt

@@ -5,8 +5,7 @@ fvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) defa
 fvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic
 cpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support
 cpu0.MVE=1                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
-cpu0.ID_ISAR5.PACBTI=1                                # (int   , init-time) default = '0x0'    : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI
-# cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
+cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
 cpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
 cpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
 cpu0.semihosting-cmd_line=""                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls

CMSIS/CoreValidation/Layer/Target/CM85NS/model_config.txt

@@ -5,8 +5,7 @@ fvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) defa
 fvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic
 cpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support
 cpu0.MVE=1                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
-cpu0.ID_ISAR5.PACBTI=1                                # (int   , init-time) default = '0x0'    : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI
-# cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
+cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
 cpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
 cpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
 cpu0.semihosting-cmd_line=""                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls

CMSIS/CoreValidation/Layer/Target/CM85S/model_config.txt

@@ -5,8 +5,7 @@ fvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) defa
 fvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic
 cpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support
 cpu0.MVE=1                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
-cpu0.ID_ISAR5.PACBTI=1                                # (int   , init-time) default = '0x0'    : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI
-# cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
+cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
 cpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
 cpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
 cpu0.semihosting-cmd_line=""                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls

CMSIS/CoreValidation/Project/Bootloader.cproject.yml → CMSIS/CoreValidation/Project/Bootloader/Bootloader.cproject.yml

@@ -2,28 +2,28 @@
 
 project:
   layers:
-    - layer: ../Layer/App/Bootloader_Cortex-M/App.clayer.yml
+    - layer: ../../Layer/App/Bootloader_Cortex-M/App.clayer.yml
 
-    - layer: ../Layer/Target/CM23S/Target.clayer.yml
+    - layer: ../../Layer/Target/CM23S/Target.clayer.yml
       for-context:
         - +CM23NS
 
-    - layer: ../Layer/Target/CM33S/Target.clayer.yml
+    - layer: ../../Layer/Target/CM33S/Target.clayer.yml
       for-context:
         - +CM33NS
 
-    - layer: ../Layer/Target/CM35PS/Target.clayer.yml
+    - layer: ../../Layer/Target/CM35PS/Target.clayer.yml
       for-context:
         - +CM35PNS
 
-    - layer: ../Layer/Target/CM52S/Target.clayer.yml
+    - layer: ../../Layer/Target/CM52S/Target.clayer.yml
       for-context:
         - +CM52NS
 
-    - layer: ../Layer/Target/CM55S/Target.clayer.yml
+    - layer: ../../Layer/Target/CM55S/Target.clayer.yml
       for-context:
         - +CM55NS
 
-    - layer: ../Layer/Target/CM85S/Target.clayer.yml
+    - layer: ../../Layer/Target/CM85S/Target.clayer.yml
       for-context:
         - +CM85NS

CMSIS/CoreValidation/Project/Validation.csolution.yml

@@ -1,5 +1,5 @@
 solution:
-  created-for: cmsis-toolbox@2.5.0
+  created-for: cmsis-toolbox@2.7.0
 
   cdefault:
 
@@ -146,8 +146,8 @@ solution:
       debug: on
 
   projects:
-    - project: ./Validation.cproject.yml
-    - project: ./Bootloader.cproject.yml
+    - project: ./Validation/Validation.cproject.yml
+    - project: ./Bootloader/Bootloader.cproject.yml
       for-context:
         - +CM23NS
         - +CM33NS