Skip to content

Commit

Permalink
Enhance tests for Core(A)
Browse files Browse the repository at this point in the history
  • Loading branch information
@JonatanAntoni
JonatanAntoni authored Oct 26, 2023
1 parent 97b5850 commit b7a15a7
Show file tree
Hide file tree
Showing 22 changed files with 1,592 additions and 100 deletions.
11 changes: 1 addition & 10 deletions .github/workflows/corevalidation.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -86,16 +86,7 @@ jobs:
echo "Patch CMSIS-Toolbox"
pushd $(dirname $(which cbuild))/../etc
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/buildmgr/cbuildgen/config/AC6.6.18.0.cmake
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/buildmgr/cbuildgen/config/GCC.10.3.1.cmake
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/buildmgr/cbuildgen/config/CLANG.16.0.0.cmake
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/buildmgr/cbuildgen/config/IAR.9.32.1.cmake
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/buildmgr/cbuildgen/config/CMSIS-Build-Utils.cmake
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/projmgr/templates/cdefault.yml
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/projmgr/templates/ac6_linker_script.sct
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/projmgr/templates/clang_linker_script.ld
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/projmgr/templates/gcc_linker_script.ld
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/projmgr/templates/iar_linker_script.ifc
curl -O https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/buildmgr/cbuildgen/config/CLANG.17.0.1.cmake
popd
- name: Activate Arm tool license
Expand Down
5 changes: 0 additions & 5 deletions CMSIS/Core/Test/build.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -79,10 +79,5 @@ def filter_iar(config):
def filter_gcc_cm85(config):
return config.compiler == CompilerAxis.GCC and config.device.match('CM85*')

#@matrix_filter
#def filter_clang_cortex_a(config):
# return config.compiler == CompilerAxis.CLANG and config.device.match('CA*')


if __name__ == "__main__":
main()
293 changes: 293 additions & 0 deletions CMSIS/Core/Test/cp15.c
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,293 @@
// REQUIRES: armv7a
// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s

#include "cmsis_compiler.h"

static volatile uint32_t u32;

void get_actlr() {
// CHECK-LABEL: <get_actlr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c1, c0, #0x1
volatile uint32_t result = __get_ACTLR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_actlr() {
// CHECK-LABEL: <set_actlr>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c1, c0, #0x1
__set_ACTLR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_cpacr() {
// CHECK-LABEL: <get_cpacr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c1, c0, #0x2
volatile uint32_t result = __get_CPACR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_cpacr() {
// CHECK-LABEL: <set_cpacr>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c1, c0, #0x2
__set_CPACR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_dfsr() {
// CHECK-LABEL: <get_dfsr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c5, c0, #0x0
volatile uint32_t result = __get_DFSR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dfsr() {
// CHECK-LABEL: <set_dfsr>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c5, c0, #0x0
__set_DFSR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_ifsr() {
// CHECK-LABEL: <get_ifsr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c5, c0, #0x1
volatile uint32_t result = __get_IFSR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_ifsr() {
// CHECK-LABEL: <set_ifsr>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c5, c0, #0x1
__set_IFSR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_isr() {
// CHECK-LABEL: <get_isr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c12, c1, #0x0
volatile uint32_t result = __get_ISR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_cbar() {
// CHECK-LABEL: <get_cbar>:
// CHECK: mrc p15, #0x4, {{r[0-9]+}}, c15, c0, #0x0
volatile uint32_t result = __get_CBAR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_ttbr0() {
// CHECK-LABEL: <get_ttbr0>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c2, c0, #0x0
volatile uint32_t result = __get_TTBR0();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_ttbr0() {
// CHECK-LABEL: <set_ttbr0>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c2, c0, #0x0
__set_TTBR0(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_dacr() {
// CHECK-LABEL: <get_dacr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c3, c0, #0x0
volatile uint32_t result = __get_DACR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dacr() {
// CHECK-LABEL: <set_dacr>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c3, c0, #0x0
__set_DACR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_sctlr() {
// CHECK-LABEL: <get_sctlr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c1, c0, #0x0
volatile uint32_t result = __get_SCTLR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_sctlr() {
// CHECK-LABEL: <set_sctlr>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c1, c0, #0x0
__set_SCTLR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_mpidr() {
// CHECK-LABEL: <get_mpidr>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c0, c0, #0x5
volatile uint32_t result = __get_MPIDR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_vbar() {
// CHECK-LABEL: <get_vbar>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c12, c0, #0x0
volatile uint32_t result = __get_VBAR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_vbar() {
// CHECK-LABEL: <set_vbar>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c12, c0, #0x0
__set_VBAR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_mvbar() {
// CHECK-LABEL: <get_mvbar>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c12, c0, #0x1
volatile uint32_t result = __get_MVBAR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_mvbar() {
// CHECK-LABEL: <set_mvbar>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c12, c0, #0x1
__set_MVBAR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_cntfrq() {
// CHECK-LABEL: <get_cntfrq>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c14, c0, #0x0
volatile uint32_t result = __get_CNTFRQ();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_cntfrq() {
// CHECK-LABEL: <set_cntfrq>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c14, c0, #0x0
__set_CNTFRQ(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_cntp_tval() {
// CHECK-LABEL: <get_cntp_tval>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c14, c2, #0x0
volatile uint32_t result = __get_CNTP_TVAL();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_cntp_tval() {
// CHECK-LABEL: <set_cntp_tval>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c14, c2, #0x0
__set_CNTP_TVAL(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_cntp_ctl() {
// CHECK-LABEL: <get_cntp_ctl>:
// CHECK: mrc p15, #0x0, {{r[0-9]+}}, c14, c2, #0x1
volatile uint32_t result = __get_CNTP_CTL();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_cntp_ctl() {
// CHECK-LABEL: <set_cntp_ctl>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c14, c2, #0x1
__set_CNTP_CTL(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_tlbiall() {
// CHECK-LABEL: <set_tlbiall>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c8, c7, #0x0
__set_TLBIALL(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_bpiall() {
// CHECK-LABEL: <set_bpiall>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c5, #0x6
__set_BPIALL(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_iciallu() {
// CHECK-LABEL: <set_iciallu>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c5, #0x0
__set_ICIALLU(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_icimvac() {
// CHECK-LABEL: <set_icimvac>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c5, #0x1
__set_ICIMVAC(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dccmvac() {
// CHECK-LABEL: <set_dccmvac>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c10, #0x1
__set_DCCMVAC(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dcimvac() {
// CHECK-LABEL: <set_dcimvac>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c6, #0x1
__set_DCIMVAC(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dccimvac() {
// CHECK-LABEL: <set_dccimvac>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c14, #0x1
__set_DCCIMVAC(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_csselr() {
// CHECK-LABEL: <get_csselr>:
// CHECK: mrc p15, #0x2, {{r[0-9]+}}, c0, c0, #0x0
volatile uint32_t result = __get_CSSELR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_csselr() {
// CHECK-LABEL: <set_csselr>:
// CHECK: mcr p15, #0x2, {{r[0-9]+}}, c0, c0, #0x0
__set_CSSELR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_ccsidr() {
// CHECK-LABEL: <get_ccsidr>:
// CHECK: mrc p15, #0x1, {{r[0-9]+}}, c0, c0, #0x0
volatile uint32_t result = __get_CCSIDR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_clidr() {
// CHECK-LABEL: <get_clidr>:
// CHECK: mrc p15, #0x1, {{r[0-9]+}}, c0, c0, #0x1
volatile uint32_t result = __get_CLIDR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dcisw() {
// CHECK-LABEL: <set_dcisw>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c6, #0x2
__set_DCISW(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dccsw() {
// CHECK-LABEL: <set_dccsw>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c10, #0x2
__set_DCCSW(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_dccisw() {
// CHECK-LABEL: <set_dccisw>:
// CHECK: mcr p15, #0x0, {{r[0-9]+}}, c7, c14, #0x2
__set_DCCISW(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}
35 changes: 35 additions & 0 deletions CMSIS/Core/Test/cpsr.c
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
// REQUIRES: armv7a
// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s

#include "cmsis_compiler.h"

static volatile uint32_t u32;

void get_cpsr() {
// CHECK-LABEL: <get_cpsr>:
// CHECK: mrs {{r[0-9]+}}, apsr
volatile uint32_t result = __get_CPSR();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_cpsr() {
// CHECK-LABEL: <set_cpsr>:
// CHECK: msr CPSR_fc, {{r[0-9]+}}
__set_CPSR(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void get_mode() {
// CHECK-LABEL: <get_mode>:
// CHECK: mrs [[REG:r[0-9]+]], apsr
// CHECK: and [[REG]], [[REG]], #{{31|0x1f}}
volatile uint32_t result = __get_mode();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_mode() {
// CHECK-LABEL: <set_mode>:
// CHECK: msr CPSR_c, {{r[0-9]+}}
__set_mode(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}
20 changes: 20 additions & 0 deletions CMSIS/Core/Test/fpexc.c
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@
// REQUIRES: armv7a, fpu
// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s

#include "cmsis_compiler.h"

static volatile uint32_t u32;

void get_fpexc() {
// CHECK-LABEL: <get_fpexc>:
// CHECK: vmrs {{r[0-9]+}}, fpexc
volatile uint32_t result = __get_FPEXC();
// CHECK: {{(bx lr)|(pop {.*pc})}}
}

void set_fpexc() {
// CHECK-LABEL: <set_fpexc>:
// CHECK: vmsr fpexc, {{r[0-9]+}}
__set_FPEXC(u32);
// CHECK: {{(bx lr)|(pop {.*pc})}}
}
Loading

0 comments on commit b7a15a7

Please sign in to comment.