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Added ARMCM52 support to CoreValidation
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Co-authored-by: Jonatan Antoni <jonatan.antoni@arm.com>
Martin Günther and JonatanAntoni authored Apr 30, 2024
1 parent f726986 commit f2c8866
Showing 42 changed files with 6,400 additions and 22 deletions.
13 changes: 4 additions & 9 deletions .devcontainer/ubuntu-22.04/vcpkg-configuration.json
Original file line number Diff line number Diff line change
@@ -1,24 +1,19 @@
{
"registries": [
{
"kind": "artifact",
"location": "https://aka.ms/vcpkg-ce-default",
"name": "microsoft"
},
{
"kind": "artifact",
"location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip",
"name": "arm"
}
],
"requires": {
"microsoft:tools/kitware/cmake": "^3.25.2",
"microsoft:ninja": "^1.10.2",
"arm:compilers/arm/armclang":"^6.20.0",
"arm:tools/kitware/cmake": "^3.25.2",
"arm:ninja": "^1.10.2",
"arm:compilers/arm/armclang":"^6.22.0",
"arm:compilers/arm/arm-none-eabi-gcc": "^13.2.1",
"arm:compilers/arm/llvm-embedded": "^17.0.1-0",
"arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0",
"arm:models/arm/avh-fvp": "^11.22.39",
"arm:models/arm/avh-fvp": "11.22.39",
"arm:debuggers/arm/armdbg": "^6.0.0"
}
}
Original file line number Diff line number Diff line change
@@ -55,6 +55,9 @@ layer:
- +CM35P
- +CM35PS
- +CM35PNS
- +CM52
- +CM52S
- +CM52NS
- +CM55
- +CM55S
- +CM55NS
Original file line number Diff line number Diff line change
@@ -0,0 +1,108 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
*(Veneer$$CMSE)
}
#endif

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*(.bss.noinit)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif

#if __RAM1_SIZE > 0
RW_RAM1 __RAM1_BASE __RAM1_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM2_SIZE > 0
RW_RAM2 __RAM2_BASE __RAM2_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM3_SIZE > 0
RW_RAM3 __RAM3_BASE __RAM3_SIZE {
.ANY (+RW +ZI)
}
#endif
}

#if __ROM1_SIZE > 0
LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 +0 __ROM1_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM2_SIZE > 0
LR_ROM2 __ROM2_BASE __ROM2_SIZE {
ER_ROM2 +0 __ROM2_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM3_SIZE > 0
LR_ROM3 __ROM3_BASE __ROM3_SIZE {
ER_ROM3 +0 __ROM3_SIZE {
.ANY (+RO +XO)
}
}
#endif
Original file line number Diff line number Diff line change
@@ -0,0 +1,361 @@
/*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright © 2019 Keith Packard
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif

/* ----------------------------------------------------------------------------
Memory definition
*----------------------------------------------------------------------------*/
MEMORY
{
ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
#if __ROM1_SIZE > 0
ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
#endif
#if __ROM2_SIZE > 0
ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
#endif
#if __ROM3_SIZE > 0
ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
#endif

RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
#if __RAM1_SIZE > 0
RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
#endif
#if __RAM2_SIZE > 0
RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
#endif
#if __RAM3_SIZE > 0
RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
#endif
}

ENTRY(Reset_Handler)

PHDRS
{
text PT_LOAD;
ram PT_LOAD;
ram_init PT_LOAD;
tls PT_TLS;
}

SECTIONS
{
.init : {
KEEP (*(.vectors))
KEEP (*(.text.init.enter))
KEEP (*(.data.init.enter))
KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
} >ROM0 AT>ROM0 :text

.text : {

/* code */
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.* .opd .opd.*)
*(.gnu.linkonce.t.*)
KEEP (*(.fini .fini.*))
__text_end = .;

PROVIDE (__etext = __text_end);
PROVIDE (_etext = __text_end);
PROVIDE (etext = __text_end);

/* read-only data */
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)

*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
*(.data.rel.ro .data.rel.ro.*)
*(.got .got.*)

/* Need to pre-align so that the symbols come after padding */
. = ALIGN(8);

/* lists of constructors and destructors */
PROVIDE_HIDDEN ( __preinit_array_start = . );
KEEP (*(.preinit_array))
PROVIDE_HIDDEN ( __preinit_array_end = . );

PROVIDE_HIDDEN ( __init_array_start = . );
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array .ctors))
PROVIDE_HIDDEN ( __init_array_end = . );

PROVIDE_HIDDEN ( __fini_array_start = . );
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array .dtors))
PROVIDE_HIDDEN ( __fini_array_end = . );

} >ROM0 AT>ROM0 :text

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
.veneers :
{
. = ALIGN(32);
KEEP(*(.gnu.sgstubs))
} > ROM0 AT>ROM0 :text
#endif

.toc : {
*(.toc .toc.*)
} >ROM0 AT>ROM0 :text

/* additional sections when compiling with C++ exception support */

.except_ordered : {
*(.gcc_except_table *.gcc_except_table.*)
KEEP (*(.eh_frame .eh_frame.*))
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >ROM0 AT>ROM0 :text

.except_unordered : {
. = ALIGN(8);

PROVIDE(__exidx_start = .);
*(.ARM.exidx*)
PROVIDE(__exidx_end = .);
} >ROM0 AT>ROM0 :text


/*
* Data values which are preserved across reset
*/
.preserve (NOLOAD) : {
PROVIDE(__preserve_start__ = .);
KEEP(*(SORT_BY_NAME(.preserve.*)))
KEEP(*(.preserve))
PROVIDE(__preserve_end__ = .);
} >RAM0 AT>RAM0 :ram

.data : {
*(.data .data.*)
*(.gnu.linkonce.d.*)

/* Need to pre-align so that the symbols come after padding */
. = ALIGN(8);

PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.* .sdata2.*)
*(.gnu.linkonce.s.*)
} >RAM0 AT>ROM0 :ram_init
PROVIDE(__data_start = ADDR(.data));
PROVIDE(__data_source = LOADADDR(.data));

/* Thread local initialized data. This gets
* space allocated as it is expected to be placed
* in ram to be used as a template for TLS data blocks
* allocated at runtime. We're slightly abusing that
* by placing the data in flash where it will be copied
* into the allocate ram addresses by the existing
* data initialization code in crt0
*/
.tdata : {
*(.tdata .tdata.* .gnu.linkonce.td.*)
PROVIDE(__data_end = .);
PROVIDE(__tdata_end = .);
} >RAM0 AT>ROM0 :tls :ram_init
PROVIDE( __tls_base = ADDR(.tdata));
PROVIDE( __tdata_start = ADDR(.tdata));
PROVIDE( __tdata_source = LOADADDR(.tdata) );
PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
PROVIDE( __data_source_end = __tdata_source_end );
PROVIDE( __tdata_size = SIZEOF(.tdata) );
PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );

PROVIDE( __edata = __data_end );
PROVIDE( _edata = __data_end );
PROVIDE( edata = __data_end );
PROVIDE( __data_size = __data_end - __data_start );
PROVIDE( __data_source_size = __data_source_end - __data_source );

.tbss (NOLOAD) : {
*(.tbss .tbss.* .gnu.linkonce.tb.*)
*(.tcommon)
PROVIDE( __tls_end = . );
PROVIDE( __tbss_end = . );
} >RAM0 AT>RAM0 :tls :ram
PROVIDE( __bss_start = ADDR(.tbss));
PROVIDE( __tbss_start = ADDR(.tbss));
PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
PROVIDE( __tbss_size = SIZEOF(.tbss) );
PROVIDE( __tls_size = __tls_end - __tls_base );
PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );

/*
* The linker special cases .tbss segments which are
* identified as segments which are not loaded and are
* thread_local.
*
* For these segments, the linker does not advance 'dot'
* across them. We actually need memory allocated for tbss,
* so we create a special segment here just to make room
*/
/*
.tbss_space (NOLOAD) : {
. = ADDR(.tbss);
. = . + SIZEOF(.tbss);
} >RAM0 AT>RAM0 :ram
*/

.bss (NOLOAD) : {
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)

/* Align the heap */
. = ALIGN(8);
__bss_end = .;
} >RAM0 AT>RAM0 :ram
PROVIDE( __non_tls_bss_start = ADDR(.bss) );
PROVIDE( __end = __bss_end );
PROVIDE( _end = __bss_end );
PROVIDE( end = __bss_end );
PROVIDE( __bss_size = __bss_end - __bss_start );

/* Make the rest of memory available for heap storage */
PROVIDE (__heap_start = __end);
#ifdef __HEAP_SIZE
PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
PROVIDE (__heap_size = __HEAP_SIZE);
#else
PROVIDE (__heap_end = __stack - __STACK_SIZE);
PROVIDE (__heap_size = __heap_end - __heap_start);
#endif
.heap (NOLOAD) : {
. += __heap_size;
} >RAM0 :ram

/* Define a stack region to make sure it fits in memory */
PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
PROVIDE(__stack_limit = __stack - __STACK_SIZE);
.stack (__stack_limit) (NOLOAD) : {
. += __STACK_SIZE;
} >RAM0 :ram

#if __STACKSEAL_SIZE > 0
PROVIDE(__stack_seal = __stack);
.stackseal (__stack) (NOLOAD) :
{
. += __STACKSEAL_SIZE;
} >RAM0 :ram
#endif

/* Throw away C++ exception handling information */

/*

/DISCARD/ : {
*(.note .note.*)
*(.eh_frame .eh_frame.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.ARM.exidx*)
}

*/

/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1. */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions. */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2. */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2. */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions. */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3. */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF 5. */
.debug_addr 0 : { *(.debug_addr) }
.debug_line_str 0 : { *(.debug_line_str) }
.debug_loclists 0 : { *(.debug_loclists) }
.debug_macro 0 : { *(.debug_macro) }
.debug_names 0 : { *(.debug_names) }
.debug_rnglists 0 : { *(.debug_rnglists) }
.debug_str_offsets 0 : { *(.debug_str_offsets) }
.debug_sup 0 : { *(.debug_sup) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
}
/*
* Check that sections that are copied from flash to RAM have matching
* padding, so that a single memcpy() of __data_size copies the correct bytes.
*/
ASSERT( __data_size == __data_source_size,
"ERROR: .data/.tdata flash size does not match RAM size");
Original file line number Diff line number Diff line change
@@ -0,0 +1,294 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif

/* ----------------------------------------------------------------------------
Memory definition
*----------------------------------------------------------------------------*/
MEMORY
{
ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
#if __ROM1_SIZE > 0
ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
#endif
#if __ROM2_SIZE > 0
ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
#endif
#if __ROM3_SIZE > 0
ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
#endif

RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
#if __RAM1_SIZE > 0
RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
#endif
#if __RAM2_SIZE > 0
RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
#endif
#if __RAM3_SIZE > 0
RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
#endif
}

/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext (deprecated)
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)

SECTIONS
{
.text :
{
KEEP(*(.vectors))
*(.text*)

KEEP(*(.init))
KEEP(*(.fini))

/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)

/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)

*(.rodata*)

KEEP(*(.eh_frame*))
} > ROM0

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
.gnu.sgstubs :
{
. = ALIGN(32);
} > ROM0
#endif

.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM0

__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM0
__exidx_end = .;

.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;

LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data) / 4)

/* Add each additional data section here */
/*
LONG (LOADADDR(.data2))
LONG (ADDR(.data2))
LONG (SIZEOF(.data2) / 4)
*/
__copy_table_end__ = .;
} > ROM0

.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;

/* .bss initialization to zero is already done during C Run-Time Startup.
LONG (ADDR(.bss))
LONG (SIZEOF(.bss) / 4)
*/

/* Add each additional bss section here */
/*
LONG (ADDR(.bss2))
LONG (SIZEOF(.bss2) / 4)
*/
__zero_table_end__ = .;
} > ROM0

/*
* This __etext variable is kept for backward compatibility with older,
* ASM based startup files.
*/
PROVIDE(__etext = LOADADDR(.data));

.data : ALIGN(4)
{
__data_start__ = .;
*(vtable)
*(.data)
*(.data.*)

. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);

. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);

. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);

KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;

} > RAM0 AT > ROM0

/*
* Secondary data section, optional
*
* Remember to add each additional data section
* to the .copy.table above to assure proper
* initialization during startup.
*/
/*
.data2 : ALIGN(4)
{
. = ALIGN(4);
__data2_start__ = .;
*(.data2)
*(.data2.*)
. = ALIGN(4);
__data2_end__ = .;

} > RAM1 AT > ROM0
*/

.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM0 AT > RAM0

/*
* Secondary bss section, optional
*
* Remember to add each additional bss section
* to the .zero.table above to assure proper
* initialization during startup.
*/
/*
.bss2 :
{
. = ALIGN(4);
__bss2_start__ = .;
*(.bss2)
*(.bss2.*)
. = ALIGN(4);
__bss2_end__ = .;
} > RAM1 AT > RAM1
*/

.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
} > RAM0

.stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
} > RAM0
PROVIDE(__stack = __StackTop);

#if __STACKSEAL_SIZE > 0
.stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
{
. = ALIGN(8);
__StackSeal = .;
. = . + 8;
. = ALIGN(8);
} > RAM0
#endif

/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,94 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

define memory mem with size = 4G;

#if __ROM0_SIZE > 0
define region ROM0_region = mem:[from __ROM0_BASE to (__ROM0_BASE+__ROM0_SIZE-1)];
#else
define region ROM0_region = [];
#endif

#if __ROM1_SIZE > 0
define region ROM1_region = mem:[from __ROM1_BASE to (__ROM0_BASE+__ROM1_SIZE-1)];
#else
define region ROM1_region = [];
#endif

#if __ROM2_SIZE > 0
define region ROM2_region = mem:[from __ROM2_BASE to (__ROM2_BASE+__ROM2_SIZE-1)];
#else
define region ROM2_region = [];
#endif

#if __ROM3_SIZE > 0
define region ROM3_region = mem:[from __ROM3_BASE to (__ROM3_BASE+__ROM3_SIZE-1)];
#else
define region ROM3_region = [];
#endif

define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_region;

#if __RAM0_SIZE > 0
define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)];
#else
define region RAM0_region = [];
#endif

#if __RAM1_SIZE > 0
define region RAM1_region = mem:[from __RAM1_BASE to (__RAM0_BASE+__RAM1_SIZE-1)];
#else
define region RAM1_region = [];
#endif

#if __RAM2_SIZE > 0
define region RAM2_region = mem:[from __RAM2_BASE to (__RAM2_BASE+__RAM2_SIZE-1)];
#else
define region RAM2_region = [];
#endif

#if __RAM3_SIZE > 0
define region RAM3_region = mem:[from __RAM3_BASE to (__RAM3_BASE+__RAM3_SIZE-1)];
#else
define region RAM3_region = [];
#endif

define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region;

do not initialize { section .noinit };
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}

place at address mem:__ROM0_BASE { readonly section .intvec };

if (!isempty(ROM_region))
{
place in ROM_region { readonly };
}

if (!isempty(RAM_region))
{
define block CSTACK with alignment = 8, size = __STACK_SIZE { };
define block PROC_STACK with alignment = 8, size = 0 { };
define block HEAP with alignment = 8, size = __HEAP_SIZE { };
place in RAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,94 @@
#ifndef REGIONS_ARMCM52_H
#define REGIONS_ARMCM52_H


//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------

// <n>Device pack: ARM::Cortex_DFP@1.0.0-dev16
// <i>Device pack used to generate this file

// <h>ROM Configuration
// =======================
// <h> ROM_S=<__ROM0>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x00000000
#define __ROM0_BASE 0x00000000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00200000
#define __ROM0_SIZE 0x00200000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __ROM0_DEFAULT 1
// <q>Startup
// <i> Selects region to be used for startup code.
#define __ROM0_STARTUP 1
// </h>

// <h> ROM_NS=<__ROM1>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x00200000
#define __ROM1_BASE 0x00200000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00200000
#define __ROM1_SIZE 0x00200000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __ROM1_DEFAULT 1
// <q>Startup
// <i> Selects region to be used for startup code.
#define __ROM1_STARTUP 1
// </h>

// </h>

// <h>RAM Configuration
// =======================
// <h> RAM_S=<__RAM0>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x20000000
#define __RAM0_BASE 0x20000000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00020000
#define __RAM0_SIZE 0x00020000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __RAM0_DEFAULT 1
// <q>No zero initialize
// <i> Excludes region from zero initialization.
#define __RAM0_NOINIT 0
// </h>

// <h> RAM_NS=<__RAM1>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x20200000
#define __RAM1_BASE 0x20200000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00020000
#define __RAM1_SIZE 0x00020000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __RAM1_DEFAULT 1
// <q>No zero initialize
// <i> Excludes region from zero initialization.
#define __RAM1_NOINIT 0
// </h>

// </h>

// <h>Stack / Heap Configuration
// <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
// </h>


#endif /* REGIONS_ARMCM52_H */
Original file line number Diff line number Diff line change
@@ -0,0 +1,164 @@
/******************************************************************************
* @file startup_ARMCM52.c
* @brief CMSIS-Core Device Startup File for Cortex-M52 Device
* @version V1.0.0
* @date 08. April 2024
******************************************************************************/
/*
* Copyright (c) 2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#if defined (ARMCM52)
#include "ARMCM52.h"
#else
#error device not specified!
#endif

/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif

extern __NO_RETURN void __PROGRAM_START(void);

/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);

/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));

void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));


/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/

#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif

extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */

/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};

#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif

/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));

__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif

SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}


#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif

/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}

/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif

Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
/**************************************************************************//**
* @file system_ARMCM52.c
* @brief CMSIS Device System Source File for ARMCM52 Device
* @version V1.0.0
* @date 08. April 2024
******************************************************************************/
/*
* Copyright (c) 2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#if defined (ARMCM52)
#include "ARMCM52.h"
#else
#error device not specified!
#endif

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM52.h"
#endif

/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */

#define SYSTEM_CLOCK (5U * XTAL)


/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];


/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;


/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}

/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{

#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif

#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif

#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif

/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
__DSB();
__ISB();

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif

SystemCoreClock = SYSTEM_CLOCK;
}
35 changes: 35 additions & 0 deletions CMSIS/CoreValidation/Layer/Target/CM52/Target.clayer.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
layer:
type: Target
description: CM52 target components and files

packs:
- pack: ARM::Cortex_DFP

device: ARMCM52

processor:
trustzone: off

components:
# [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
- component: ARM::CMSIS:CORE
- component: Device:Startup&C Startup

groups:
- group: FVP
files:
- file: ./model_config.txt

linker:
- for-compiler: AC6
script: RTE/Device/$Dname$/ac6_linker_script.sct
regions: RTE/Device/$Dname$/regions_$Dname$.h
- for-compiler: GCC
script: RTE/Device/$Dname$/gcc_linker_script.ld
regions: RTE/Device/$Dname$/regions_$Dname$.h
- for-compiler: CLANG
script: RTE/Device/$Dname$/clang_linker_script.ld
regions: RTE/Device/$Dname$/regions_$Dname$.h
- for-compiler: IAR
script: RTE/Device/$Dname$/iar_linker_script.icf
regions: RTE/Device/$Dname$/regions_$Dname$.h
28 changes: 28 additions & 0 deletions CMSIS/CoreValidation/Layer/Target/CM52/model_config.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
cpu0.FPMVE=5 # (int , init-time) default = '0x5' : Set whether the model has FP and / or MVE support. 0: No FP and MVE support. 1: FP half and single precision. 2: FP half, single and double precision. 3: MVE integer. 4: FP half and single precision and MVE integer. 5: FP half, single and double precision and MVE floating point.
cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
#----------------------------------------------------------------------------------------------
Original file line number Diff line number Diff line change
@@ -0,0 +1,108 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
*(Veneer$$CMSE)
}
#endif

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*(.bss.noinit)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif

#if __RAM1_SIZE > 0
RW_RAM1 __RAM1_BASE __RAM1_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM2_SIZE > 0
RW_RAM2 __RAM2_BASE __RAM2_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM3_SIZE > 0
RW_RAM3 __RAM3_BASE __RAM3_SIZE {
.ANY (+RW +ZI)
}
#endif
}

#if __ROM1_SIZE > 0
LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 +0 __ROM1_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM2_SIZE > 0
LR_ROM2 __ROM2_BASE __ROM2_SIZE {
ER_ROM2 +0 __ROM2_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM3_SIZE > 0
LR_ROM3 __ROM3_BASE __ROM3_SIZE {
ER_ROM3 +0 __ROM3_SIZE {
.ANY (+RO +XO)
}
}
#endif
Original file line number Diff line number Diff line change
@@ -0,0 +1,361 @@
/*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright © 2019 Keith Packard
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif

/* ----------------------------------------------------------------------------
Memory definition
*----------------------------------------------------------------------------*/
MEMORY
{
ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
#if __ROM1_SIZE > 0
ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
#endif
#if __ROM2_SIZE > 0
ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
#endif
#if __ROM3_SIZE > 0
ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
#endif

RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
#if __RAM1_SIZE > 0
RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
#endif
#if __RAM2_SIZE > 0
RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
#endif
#if __RAM3_SIZE > 0
RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
#endif
}

ENTRY(Reset_Handler)

PHDRS
{
text PT_LOAD;
ram PT_LOAD;
ram_init PT_LOAD;
tls PT_TLS;
}

SECTIONS
{
.init : {
KEEP (*(.vectors))
KEEP (*(.text.init.enter))
KEEP (*(.data.init.enter))
KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
} >ROM0 AT>ROM0 :text

.text : {

/* code */
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.* .opd .opd.*)
*(.gnu.linkonce.t.*)
KEEP (*(.fini .fini.*))
__text_end = .;

PROVIDE (__etext = __text_end);
PROVIDE (_etext = __text_end);
PROVIDE (etext = __text_end);

/* read-only data */
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)

*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
*(.data.rel.ro .data.rel.ro.*)
*(.got .got.*)

/* Need to pre-align so that the symbols come after padding */
. = ALIGN(8);

/* lists of constructors and destructors */
PROVIDE_HIDDEN ( __preinit_array_start = . );
KEEP (*(.preinit_array))
PROVIDE_HIDDEN ( __preinit_array_end = . );

PROVIDE_HIDDEN ( __init_array_start = . );
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array .ctors))
PROVIDE_HIDDEN ( __init_array_end = . );

PROVIDE_HIDDEN ( __fini_array_start = . );
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array .dtors))
PROVIDE_HIDDEN ( __fini_array_end = . );

} >ROM0 AT>ROM0 :text

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
.veneers :
{
. = ALIGN(32);
KEEP(*(.gnu.sgstubs))
} > ROM0 AT>ROM0 :text
#endif

.toc : {
*(.toc .toc.*)
} >ROM0 AT>ROM0 :text

/* additional sections when compiling with C++ exception support */

.except_ordered : {
*(.gcc_except_table *.gcc_except_table.*)
KEEP (*(.eh_frame .eh_frame.*))
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >ROM0 AT>ROM0 :text

.except_unordered : {
. = ALIGN(8);

PROVIDE(__exidx_start = .);
*(.ARM.exidx*)
PROVIDE(__exidx_end = .);
} >ROM0 AT>ROM0 :text


/*
* Data values which are preserved across reset
*/
.preserve (NOLOAD) : {
PROVIDE(__preserve_start__ = .);
KEEP(*(SORT_BY_NAME(.preserve.*)))
KEEP(*(.preserve))
PROVIDE(__preserve_end__ = .);
} >RAM0 AT>RAM0 :ram

.data : {
*(.data .data.*)
*(.gnu.linkonce.d.*)

/* Need to pre-align so that the symbols come after padding */
. = ALIGN(8);

PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.* .sdata2.*)
*(.gnu.linkonce.s.*)
} >RAM0 AT>ROM0 :ram_init
PROVIDE(__data_start = ADDR(.data));
PROVIDE(__data_source = LOADADDR(.data));

/* Thread local initialized data. This gets
* space allocated as it is expected to be placed
* in ram to be used as a template for TLS data blocks
* allocated at runtime. We're slightly abusing that
* by placing the data in flash where it will be copied
* into the allocate ram addresses by the existing
* data initialization code in crt0
*/
.tdata : {
*(.tdata .tdata.* .gnu.linkonce.td.*)
PROVIDE(__data_end = .);
PROVIDE(__tdata_end = .);
} >RAM0 AT>ROM0 :tls :ram_init
PROVIDE( __tls_base = ADDR(.tdata));
PROVIDE( __tdata_start = ADDR(.tdata));
PROVIDE( __tdata_source = LOADADDR(.tdata) );
PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
PROVIDE( __data_source_end = __tdata_source_end );
PROVIDE( __tdata_size = SIZEOF(.tdata) );
PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );

PROVIDE( __edata = __data_end );
PROVIDE( _edata = __data_end );
PROVIDE( edata = __data_end );
PROVIDE( __data_size = __data_end - __data_start );
PROVIDE( __data_source_size = __data_source_end - __data_source );

.tbss (NOLOAD) : {
*(.tbss .tbss.* .gnu.linkonce.tb.*)
*(.tcommon)
PROVIDE( __tls_end = . );
PROVIDE( __tbss_end = . );
} >RAM0 AT>RAM0 :tls :ram
PROVIDE( __bss_start = ADDR(.tbss));
PROVIDE( __tbss_start = ADDR(.tbss));
PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
PROVIDE( __tbss_size = SIZEOF(.tbss) );
PROVIDE( __tls_size = __tls_end - __tls_base );
PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );

/*
* The linker special cases .tbss segments which are
* identified as segments which are not loaded and are
* thread_local.
*
* For these segments, the linker does not advance 'dot'
* across them. We actually need memory allocated for tbss,
* so we create a special segment here just to make room
*/
/*
.tbss_space (NOLOAD) : {
. = ADDR(.tbss);
. = . + SIZEOF(.tbss);
} >RAM0 AT>RAM0 :ram
*/

.bss (NOLOAD) : {
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)

/* Align the heap */
. = ALIGN(8);
__bss_end = .;
} >RAM0 AT>RAM0 :ram
PROVIDE( __non_tls_bss_start = ADDR(.bss) );
PROVIDE( __end = __bss_end );
PROVIDE( _end = __bss_end );
PROVIDE( end = __bss_end );
PROVIDE( __bss_size = __bss_end - __bss_start );

/* Make the rest of memory available for heap storage */
PROVIDE (__heap_start = __end);
#ifdef __HEAP_SIZE
PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
PROVIDE (__heap_size = __HEAP_SIZE);
#else
PROVIDE (__heap_end = __stack - __STACK_SIZE);
PROVIDE (__heap_size = __heap_end - __heap_start);
#endif
.heap (NOLOAD) : {
. += __heap_size;
} >RAM0 :ram

/* Define a stack region to make sure it fits in memory */
PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
PROVIDE(__stack_limit = __stack - __STACK_SIZE);
.stack (__stack_limit) (NOLOAD) : {
. += __STACK_SIZE;
} >RAM0 :ram

#if __STACKSEAL_SIZE > 0
PROVIDE(__stack_seal = __stack);
.stackseal (__stack) (NOLOAD) :
{
. += __STACKSEAL_SIZE;
} >RAM0 :ram
#endif

/* Throw away C++ exception handling information */

/*

/DISCARD/ : {
*(.note .note.*)
*(.eh_frame .eh_frame.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.ARM.exidx*)
}

*/

/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1. */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions. */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2. */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2. */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions. */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3. */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF 5. */
.debug_addr 0 : { *(.debug_addr) }
.debug_line_str 0 : { *(.debug_line_str) }
.debug_loclists 0 : { *(.debug_loclists) }
.debug_macro 0 : { *(.debug_macro) }
.debug_names 0 : { *(.debug_names) }
.debug_rnglists 0 : { *(.debug_rnglists) }
.debug_str_offsets 0 : { *(.debug_str_offsets) }
.debug_sup 0 : { *(.debug_sup) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
}
/*
* Check that sections that are copied from flash to RAM have matching
* padding, so that a single memcpy() of __data_size copies the correct bytes.
*/
ASSERT( __data_size == __data_source_size,
"ERROR: .data/.tdata flash size does not match RAM size");
Original file line number Diff line number Diff line change
@@ -0,0 +1,294 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif

/* ----------------------------------------------------------------------------
Memory definition
*----------------------------------------------------------------------------*/
MEMORY
{
ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
#if __ROM1_SIZE > 0
ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
#endif
#if __ROM2_SIZE > 0
ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
#endif
#if __ROM3_SIZE > 0
ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
#endif

RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
#if __RAM1_SIZE > 0
RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
#endif
#if __RAM2_SIZE > 0
RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
#endif
#if __RAM3_SIZE > 0
RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
#endif
}

/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext (deprecated)
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)

SECTIONS
{
.text :
{
KEEP(*(.vectors))
*(.text*)

KEEP(*(.init))
KEEP(*(.fini))

/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)

/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)

*(.rodata*)

KEEP(*(.eh_frame*))
} > ROM0

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
.gnu.sgstubs :
{
. = ALIGN(32);
} > ROM0
#endif

.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM0

__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM0
__exidx_end = .;

.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;

LONG (LOADADDR(.data))
LONG (ADDR(.data))
LONG (SIZEOF(.data) / 4)

/* Add each additional data section here */
/*
LONG (LOADADDR(.data2))
LONG (ADDR(.data2))
LONG (SIZEOF(.data2) / 4)
*/
__copy_table_end__ = .;
} > ROM0

.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;

/* .bss initialization to zero is already done during C Run-Time Startup.
LONG (ADDR(.bss))
LONG (SIZEOF(.bss) / 4)
*/

/* Add each additional bss section here */
/*
LONG (ADDR(.bss2))
LONG (SIZEOF(.bss2) / 4)
*/
__zero_table_end__ = .;
} > ROM0

/*
* This __etext variable is kept for backward compatibility with older,
* ASM based startup files.
*/
PROVIDE(__etext = LOADADDR(.data));

.data : ALIGN(4)
{
__data_start__ = .;
*(vtable)
*(.data)
*(.data.*)

. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);

. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);

. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);

KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;

} > RAM0 AT > ROM0

/*
* Secondary data section, optional
*
* Remember to add each additional data section
* to the .copy.table above to assure proper
* initialization during startup.
*/
/*
.data2 : ALIGN(4)
{
. = ALIGN(4);
__data2_start__ = .;
*(.data2)
*(.data2.*)
. = ALIGN(4);
__data2_end__ = .;

} > RAM1 AT > ROM0
*/

.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM0 AT > RAM0

/*
* Secondary bss section, optional
*
* Remember to add each additional bss section
* to the .zero.table above to assure proper
* initialization during startup.
*/
/*
.bss2 :
{
. = ALIGN(4);
__bss2_start__ = .;
*(.bss2)
*(.bss2.*)
. = ALIGN(4);
__bss2_end__ = .;
} > RAM1 AT > RAM1
*/

.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
} > RAM0

.stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
{
. = ALIGN(8);
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
} > RAM0
PROVIDE(__stack = __StackTop);

#if __STACKSEAL_SIZE > 0
.stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
{
. = ALIGN(8);
__StackSeal = .;
. = . + 8;
. = ALIGN(8);
} > RAM0
#endif

/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,94 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

define memory mem with size = 4G;

#if __ROM0_SIZE > 0
define region ROM0_region = mem:[from __ROM0_BASE to (__ROM0_BASE+__ROM0_SIZE-1)];
#else
define region ROM0_region = [];
#endif

#if __ROM1_SIZE > 0
define region ROM1_region = mem:[from __ROM1_BASE to (__ROM0_BASE+__ROM1_SIZE-1)];
#else
define region ROM1_region = [];
#endif

#if __ROM2_SIZE > 0
define region ROM2_region = mem:[from __ROM2_BASE to (__ROM2_BASE+__ROM2_SIZE-1)];
#else
define region ROM2_region = [];
#endif

#if __ROM3_SIZE > 0
define region ROM3_region = mem:[from __ROM3_BASE to (__ROM3_BASE+__ROM3_SIZE-1)];
#else
define region ROM3_region = [];
#endif

define region ROM_region = ROM0_region | ROM1_region | ROM2_region | ROM3_region;

#if __RAM0_SIZE > 0
define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)];
#else
define region RAM0_region = [];
#endif

#if __RAM1_SIZE > 0
define region RAM1_region = mem:[from __RAM1_BASE to (__RAM0_BASE+__RAM1_SIZE-1)];
#else
define region RAM1_region = [];
#endif

#if __RAM2_SIZE > 0
define region RAM2_region = mem:[from __RAM2_BASE to (__RAM2_BASE+__RAM2_SIZE-1)];
#else
define region RAM2_region = [];
#endif

#if __RAM3_SIZE > 0
define region RAM3_region = mem:[from __RAM3_BASE to (__RAM3_BASE+__RAM3_SIZE-1)];
#else
define region RAM3_region = [];
#endif

define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region;

do not initialize { section .noinit };
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}

place at address mem:__ROM0_BASE { readonly section .intvec };

if (!isempty(ROM_region))
{
place in ROM_region { readonly };
}

if (!isempty(RAM_region))
{
define block CSTACK with alignment = 8, size = __STACK_SIZE { };
define block PROC_STACK with alignment = 8, size = 0 { };
define block HEAP with alignment = 8, size = __HEAP_SIZE { };
place in RAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,94 @@
#ifndef REGIONS_ARMCM52_H
#define REGIONS_ARMCM52_H


//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------

// <n>Device pack: ARM::Cortex_DFP@1.0.0-dev16
// <i>Device pack used to generate this file

// <h>ROM Configuration
// =======================
// <h> ROM_S=<__ROM0>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x00000000
#define __ROM0_BASE 0x00200000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00200000
#define __ROM0_SIZE 0x00200000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __ROM0_DEFAULT 1
// <q>Startup
// <i> Selects region to be used for startup code.
#define __ROM0_STARTUP 1
// </h>

// <h> ROM_NS=<__ROM1>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x00200000
#define __ROM1_BASE 0x00000000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00200000
#define __ROM1_SIZE 0x00200000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __ROM1_DEFAULT 0
// <q>Startup
// <i> Selects region to be used for startup code.
#define __ROM1_STARTUP 0
// </h>

// </h>

// <h>RAM Configuration
// =======================
// <h> RAM_S=<__RAM0>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x20000000
#define __RAM0_BASE 0x20200000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00020000
#define __RAM0_SIZE 0x00020000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __RAM0_DEFAULT 1
// <q>No zero initialize
// <i> Excludes region from zero initialization.
#define __RAM0_NOINIT 0
// </h>

// <h> RAM_NS=<__RAM1>
// <o> Base address <0x0-0xFFFFFFFF:8>
// <i> Defines base address of memory region.
// <i> Default: 0x20200000
#define __RAM1_BASE 0x20000000
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
// <i> Defines size of memory region.
// <i> Default: 0x00020000
#define __RAM1_SIZE 0x00020000
// <q>Default region
// <i> Enables memory region globally for the application.
#define __RAM1_DEFAULT 0
// <q>No zero initialize
// <i> Excludes region from zero initialization.
#define __RAM1_NOINIT 0
// </h>

// </h>

// <h>Stack / Heap Configuration
// <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
// </h>


#endif /* REGIONS_ARMCM52_H */
Original file line number Diff line number Diff line change
@@ -0,0 +1,164 @@
/******************************************************************************
* @file startup_ARMCM52.c
* @brief CMSIS-Core Device Startup File for Cortex-M52 Device
* @version V1.0.0
* @date 08. April 2024
******************************************************************************/
/*
* Copyright (c) 2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#if defined (ARMCM52)
#include "ARMCM52.h"
#else
#error device not specified!
#endif

/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif

extern __NO_RETURN void __PROGRAM_START(void);

/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);

/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));

void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));


/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/

#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif

extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */

/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};

#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif

/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));

__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif

SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}


#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif

/*----------------------------------------------------------------------------
Hard Fault Handler
*----------------------------------------------------------------------------*/
void HardFault_Handler(void)
{
while(1);
}

/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif

Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
/**************************************************************************//**
* @file system_ARMCM52.c
* @brief CMSIS Device System Source File for ARMCM52 Device
* @version V1.0.0
* @date 08. April 2024
******************************************************************************/
/*
* Copyright (c) 2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#if defined (ARMCM52)
#include "ARMCM52.h"
#else
#error device not specified!
#endif

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM52.h"
#endif

/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */

#define SYSTEM_CLOCK (5U * XTAL)


/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];


/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;


/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}

/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{

#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif

#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif

#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif

/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
__DSB();
__ISB();

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif

SystemCoreClock = SYSTEM_CLOCK;
}
35 changes: 35 additions & 0 deletions CMSIS/CoreValidation/Layer/Target/CM52NS/Target.clayer.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
layer:
type: Target
description: CM52NS target components and files

packs:
- pack: ARM::Cortex_DFP

device: ARMCM52

processor:
trustzone: non-secure

components:
# [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
- component: ARM::CMSIS:CORE
- component: Device:Startup&C Startup

groups:
- group: FVP
files:
- file: ./model_config.txt

linker:
- for-compiler: AC6
script: RTE/Device/$Dname$/ac6_linker_script.sct
regions: RTE/Device/$Dname$/regions_$Dname$.h
- for-compiler: GCC
script: RTE/Device/$Dname$/gcc_linker_script.ld
regions: RTE/Device/$Dname$/regions_$Dname$.h
- for-compiler: CLANG
script: RTE/Device/$Dname$/clang_linker_script.ld
regions: RTE/Device/$Dname$/regions_$Dname$.h
- for-compiler: IAR
script: RTE/Device/$Dname$/iar_linker_script.icf
regions: RTE/Device/$Dname$/regions_$Dname$.h
28 changes: 28 additions & 0 deletions CMSIS/CoreValidation/Layer/Target/CM52NS/model_config.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
cpu0.FPMVE=5 # (int , init-time) default = '0x5' : Set whether the model has FP and / or MVE support. 0: No FP and MVE support. 1: FP half and single precision. 2: FP half, single and double precision. 3: MVE integer. 4: FP half and single precision and MVE integer. 5: FP half, single and double precision and MVE floating point.
cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
#----------------------------------------------------------------------------------------------
Original file line number Diff line number Diff line change
@@ -0,0 +1,108 @@
/*
* Copyright (c) 2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE 8
#else
#define __STACKSEAL_SIZE 0
#endif

/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/

LR_ROM0 __ROM0_BASE __ROM0_SIZE {

ER_ROM0 __ROM0_BASE __ROM0_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO +XO)
}

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
*(Veneer$$CMSE)
}
#endif

RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
*(.bss.noinit)
}

RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
*(+RW +ZI)
}

#if __HEAP_SIZE > 0
ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif

ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}

#if __STACKSEAL_SIZE > 0
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif

#if __RAM1_SIZE > 0
RW_RAM1 __RAM1_BASE __RAM1_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM2_SIZE > 0
RW_RAM2 __RAM2_BASE __RAM2_SIZE {
.ANY (+RW +ZI)
}
#endif

#if __RAM3_SIZE > 0
RW_RAM3 __RAM3_BASE __RAM3_SIZE {
.ANY (+RW +ZI)
}
#endif
}

#if __ROM1_SIZE > 0
LR_ROM1 __ROM1_BASE __ROM1_SIZE {
ER_ROM1 +0 __ROM1_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM2_SIZE > 0
LR_ROM2 __ROM2_BASE __ROM2_SIZE {
ER_ROM2 +0 __ROM2_SIZE {
.ANY (+RO +XO)
}
}
#endif

#if __ROM3_SIZE > 0
LR_ROM3 __ROM3_BASE __ROM3_SIZE {
ER_ROM3 +0 __ROM3_SIZE {
.ANY (+RO +XO)
}
}
#endif
Original file line number Diff line number Diff line change
@@ -0,0 +1,361 @@
/*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright © 2019 Keith Packard
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/

/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif

/* ----------------------------------------------------------------------------
Memory definition
*----------------------------------------------------------------------------*/
MEMORY
{
ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
#if __ROM1_SIZE > 0
ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
#endif
#if __ROM2_SIZE > 0
ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
#endif
#if __ROM3_SIZE > 0
ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
#endif

RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
#if __RAM1_SIZE > 0
RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
#endif
#if __RAM2_SIZE > 0
RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
#endif
#if __RAM3_SIZE > 0
RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
#endif
}

ENTRY(Reset_Handler)

PHDRS
{
text PT_LOAD;
ram PT_LOAD;
ram_init PT_LOAD;
tls PT_TLS;
}

SECTIONS
{
.init : {
KEEP (*(.vectors))
KEEP (*(.text.init.enter))
KEEP (*(.data.init.enter))
KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
} >ROM0 AT>ROM0 :text

.text : {

/* code */
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.* .opd .opd.*)
*(.gnu.linkonce.t.*)
KEEP (*(.fini .fini.*))
__text_end = .;

PROVIDE (__etext = __text_end);
PROVIDE (_etext = __text_end);
PROVIDE (etext = __text_end);

/* read-only data */
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)

*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
*(.data.rel.ro .data.rel.ro.*)
*(.got .got.*)

/* Need to pre-align so that the symbols come after padding */
. = ALIGN(8);

/* lists of constructors and destructors */
PROVIDE_HIDDEN ( __preinit_array_start = . );
KEEP (*(.preinit_array))
PROVIDE_HIDDEN ( __preinit_array_end = . );

PROVIDE_HIDDEN ( __init_array_start = . );
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array .ctors))
PROVIDE_HIDDEN ( __init_array_end = . );

PROVIDE_HIDDEN ( __fini_array_start = . );
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array .dtors))
PROVIDE_HIDDEN ( __fini_array_end = . );

} >ROM0 AT>ROM0 :text

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
.veneers :
{
. = ALIGN(32);
KEEP(*(.gnu.sgstubs))
} > ROM0 AT>ROM0 :text
#endif

.toc : {
*(.toc .toc.*)
} >ROM0 AT>ROM0 :text

/* additional sections when compiling with C++ exception support */

.except_ordered : {
*(.gcc_except_table *.gcc_except_table.*)
KEEP (*(.eh_frame .eh_frame.*))
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >ROM0 AT>ROM0 :text

.except_unordered : {
. = ALIGN(8);

PROVIDE(__exidx_start = .);
*(.ARM.exidx*)
PROVIDE(__exidx_end = .);
} >ROM0 AT>ROM0 :text


/*
* Data values which are preserved across reset
*/
.preserve (NOLOAD) : {
PROVIDE(__preserve_start__ = .);
KEEP(*(SORT_BY_NAME(.preserve.*)))
KEEP(*(.preserve))
PROVIDE(__preserve_end__ = .);
} >RAM0 AT>RAM0 :ram

.data : {
*(.data .data.*)
*(.gnu.linkonce.d.*)

/* Need to pre-align so that the symbols come after padding */
. = ALIGN(8);

PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.* .sdata2.*)
*(.gnu.linkonce.s.*)
} >RAM0 AT>ROM0 :ram_init
PROVIDE(__data_start = ADDR(.data));
PROVIDE(__data_source = LOADADDR(.data));

/* Thread local initialized data. This gets
* space allocated as it is expected to be placed
* in ram to be used as a template for TLS data blocks
* allocated at runtime. We're slightly abusing that
* by placing the data in flash where it will be copied
* into the allocate ram addresses by the existing
* data initialization code in crt0
*/
.tdata : {
*(.tdata .tdata.* .gnu.linkonce.td.*)
PROVIDE(__data_end = .);
PROVIDE(__tdata_end = .);
} >RAM0 AT>ROM0 :tls :ram_init
PROVIDE( __tls_base = ADDR(.tdata));
PROVIDE( __tdata_start = ADDR(.tdata));
PROVIDE( __tdata_source = LOADADDR(.tdata) );
PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
PROVIDE( __data_source_end = __tdata_source_end );
PROVIDE( __tdata_size = SIZEOF(.tdata) );
PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );

PROVIDE( __edata = __data_end );
PROVIDE( _edata = __data_end );
PROVIDE( edata = __data_end );
PROVIDE( __data_size = __data_end - __data_start );
PROVIDE( __data_source_size = __data_source_end - __data_source );

.tbss (NOLOAD) : {
*(.tbss .tbss.* .gnu.linkonce.tb.*)
*(.tcommon)
PROVIDE( __tls_end = . );
PROVIDE( __tbss_end = . );
} >RAM0 AT>RAM0 :tls :ram
PROVIDE( __bss_start = ADDR(.tbss));
PROVIDE( __tbss_start = ADDR(.tbss));
PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
PROVIDE( __tbss_size = SIZEOF(.tbss) );
PROVIDE( __tls_size = __tls_end - __tls_base );
PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );

/*
* The linker special cases .tbss segments which are
* identified as segments which are not loaded and are
* thread_local.
*
* For these segments, the linker does not advance 'dot'
* across them. We actually need memory allocated for tbss,
* so we create a special segment here just to make room
*/
/*
.tbss_space (NOLOAD) : {
. = ADDR(.tbss);
. = . + SIZEOF(.tbss);
} >RAM0 AT>RAM0 :ram
*/

.bss (NOLOAD) : {
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)

/* Align the heap */
. = ALIGN(8);
__bss_end = .;
} >RAM0 AT>RAM0 :ram
PROVIDE( __non_tls_bss_start = ADDR(.bss) );
PROVIDE( __end = __bss_end );
PROVIDE( _end = __bss_end );
PROVIDE( end = __bss_end );
PROVIDE( __bss_size = __bss_end - __bss_start );

/* Make the rest of memory available for heap storage */
PROVIDE (__heap_start = __end);
#ifdef __HEAP_SIZE
PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
PROVIDE (__heap_size = __HEAP_SIZE);
#else
PROVIDE (__heap_end = __stack - __STACK_SIZE);
PROVIDE (__heap_size = __heap_end - __heap_start);
#endif
.heap (NOLOAD) : {
. += __heap_size;
} >RAM0 :ram

/* Define a stack region to make sure it fits in memory */
PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
PROVIDE(__stack_limit = __stack - __STACK_SIZE);
.stack (__stack_limit) (NOLOAD) : {
. += __STACK_SIZE;
} >RAM0 :ram

#if __STACKSEAL_SIZE > 0
PROVIDE(__stack_seal = __stack);
.stackseal (__stack) (NOLOAD) :
{
. += __STACKSEAL_SIZE;
} >RAM0 :ram
#endif

/* Throw away C++ exception handling information */

/*

/DISCARD/ : {
*(.note .note.*)
*(.eh_frame .eh_frame.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.ARM.exidx*)
}

*/

/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1. */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions. */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2. */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2. */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions. */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3. */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF 5. */
.debug_addr 0 : { *(.debug_addr) }
.debug_line_str 0 : { *(.debug_line_str) }
.debug_loclists 0 : { *(.debug_loclists) }
.debug_macro 0 : { *(.debug_macro) }
.debug_names 0 : { *(.debug_names) }
.debug_rnglists 0 : { *(.debug_rnglists) }
.debug_str_offsets 0 : { *(.debug_str_offsets) }
.debug_sup 0 : { *(.debug_sup) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
}
/*
* Check that sections that are copied from flash to RAM have matching
* padding, so that a single memcpy() of __data_size copies the correct bytes.
*/
ASSERT( __data_size == __data_source_size,
"ERROR: .data/.tdata flash size does not match RAM size");
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