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Core: align CoreValidation model configuration with Cortex_DFP #138

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Feb 22, 2024
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Core: align CoreValidation model configuration with Cortex_DFP #138

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15 changes: 10 additions & 5 deletions CMSIS/CoreValidation/Layer/Target/CM0/model_config.txt
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@@ -1,8 +1,13 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output
#----------------------------------------------------------------------------------------------
fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
#------------------------------------------------------------------------------
armcortexm0ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
armcortexm0ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
armcortexm0ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
armcortexm0ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
armcortexm0ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
armcortexm0ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
armcortexm0ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
#----------------------------------------------------------------------------------------------
16 changes: 11 additions & 5 deletions CMSIS/CoreValidation/Layer/Target/CM0plus/model_config.txt
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Original file line number Diff line number Diff line change
@@ -1,8 +1,14 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#------------------------------------------------------------------------------
fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output
#----------------------------------------------------------------------------------------------
fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation
#------------------------------------------------------------------------------
armcortexm0plusct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0plusct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
armcortexm0plusct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
armcortexm0plusct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
armcortexm0plusct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
armcortexm0plusct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
armcortexm0plusct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
armcortexm0plusct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
armcortexm0plusct.NUM_MPU_REGION=0x8 # (int , init-time) default = '0x0' : Number of MPU regions : [0x0..0x8]
#----------------------------------------------------------------------------------------------
6 changes: 6 additions & 0 deletions CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt
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Expand Up @@ -12,4 +12,10 @@ armcortexm7ct.semihosting-stack_base=0x0 # (int , init-time) defa
armcortexm7ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
armcortexm7ct.DP_FLOAT=1 # (bool , init-time) default = '1' : Support 8-byte floats
armcortexm7ct.dcache-size=32768 # (int , init-time) default = '0x8000' : L1 D-cache size in bytes
armcortexm7ct.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation
armcortexm7ct.dcache-ways=4 # (int , init-time) default = '0x4' : L1 D-cache ways (sets are implicit from size)
armcortexm7ct.icache-size=32768 # (int , init-time) default = '0x8000' : L1 I-cache size in bytes
armcortexm7ct.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation
armcortexm7ct.icache-ways=2 # (int , init-time) default = '0x2' : L1 I-cache ways (sets are implicit from size)
#----------------------------------------------------------------------------------------------
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