added ARMCM52 support to CoreValidation

.devcontainer/ubuntu-22.04/vcpkg-configuration.json

@@ -1,24 +1,19 @@
 {
     "registries": [
-      {
-        "kind": "artifact",
-        "location": "https://aka.ms/vcpkg-ce-default",
-        "name": "microsoft"
-      },
       {
         "kind": "artifact",
         "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip",
         "name": "arm"
       }
     ],
     "requires": {
-      "microsoft:tools/kitware/cmake": "^3.25.2",
-      "microsoft:ninja": "^1.10.2",
-      "arm:compilers/arm/armclang":"^6.20.0",
+      "arm:tools/kitware/cmake": "^3.25.2",
+      "arm:ninja": "^1.10.2",
+      "arm:compilers/arm/armclang":"^6.22.0",
       "arm:compilers/arm/arm-none-eabi-gcc": "^13.2.1",
       "arm:compilers/arm/llvm-embedded": "^17.0.1-0",
       "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0",
-      "arm:models/arm/avh-fvp": "^11.22.39",
+      "arm:models/arm/avh-fvp": "11.22.39",
       "arm:debuggers/arm/armdbg": "^6.0.0"
     }
   }

CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml

@@ -55,6 +55,9 @@ layer:
             - +CM35P
             - +CM35PS
             - +CM35PNS
+            - +CM52
+            - +CM52S
+            - +CM52NS
             - +CM55
             - +CM55S
             - +CM55NS

CMSIS/CoreValidation/Layer/Target/CM52/RTE/Device/ARMCM52/ac6_linker_script.sct

@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE 8
+#else
+#define __STACKSEAL_SIZE 0
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+  ER_ROM0 __ROM0_BASE __ROM0_SIZE {
+    *.o (RESET, +First)
+    *(InRoot$$Sections)
+    *(+RO +XO)
+  }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
+    *(Veneer$$CMSE)
+  }
+#endif
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
+    *(.bss.noinit)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif