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added vgetq_lane and moved vget intrinsics to their correct location
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@Lukacma
Lukacma committed Jan 28, 2025
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5 changes: 3 additions & 2 deletions neon_intrinsics/advsimd.md
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Expand Up @@ -3411,6 +3411,8 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
| <code>int64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64" target="_blank">vget_lane_s64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int64x1_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `lane==0`<br>`v -> Vn.1D` | `UMOV Rd,Vn.D[lane]` | `Rd -> result` | `v7/A32/A64` |
| <code>poly8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8" target="_blank">vget_lane_p8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly8x8_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=7`<br>`v -> Vn.8B` | `UMOV Rd,Vn.B[lane]` | `Rd -> result` | `v7/A32/A64` |
| <code>poly16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16" target="_blank">vget_lane_p16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x4_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=3`<br>`v -> Vn.4H` | `UMOV Rd,Vn.H[lane]` | `Rd -> result` | `v7/A32/A64` |
| <code>mfloat8_t vget_lane_mf8(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=7`<br>`v -> Vn.8B` | `DUP Bd,Vn.B[lane]` | `Bd -> result` | `v7/A32/A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16" target="_blank">vget_lane_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x4_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=3`<br>`v -> Vn.4H` | `DUP Hd,Vn.H[lane]` | `Hd -> result` | `v7/A32/A64` |
| <code>float32_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32" target="_blank">vget_lane_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=1`<br>`v -> Vn.2S` | `DUP Sd,Vn.S[lane]` | `Sd -> result` | `v7/A32/A64` |
| <code>float64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f64" target="_blank">vget_lane_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `lane==0`<br>`v -> Vn.1D` | `DUP Dd,Vn.D[lane]` | `Dd -> result` | `A64` |
| <code>uint8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8" target="_blank">vgetq_lane_u8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x16_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=15`<br>`v -> Vn.16B` | `UMOV Rd,Vn.B[lane]` | `Rd -> result` | `v7/A32/A64` |
Expand All @@ -3424,8 +3426,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
| <code>int64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64" target="_blank">vgetq_lane_s64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int64x2_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=1`<br>`v -> Vn.2D` | `UMOV Rd,Vn.D[lane]` | `Rd -> result` | `v7/A32/A64` |
| <code>poly8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8" target="_blank">vgetq_lane_p8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly8x16_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=15`<br>`v -> Vn.16B` | `UMOV Rd,Vn.B[lane]` | `Rd -> result` | `v7/A32/A64` |
| <code>poly16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16" target="_blank">vgetq_lane_p16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x8_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=7`<br>`v -> Vn.8H` | `UMOV Rd,Vn.H[lane]` | `Rd -> result` | `v7/A32/A64` |
| <code>mfloat8_t vget_lane_mf8(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=15`<br>`v -> Vn.16B` | `DUP Bd,Vn.B[lane]` | `Bd -> result` | `v7/A32/A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16" target="_blank">vget_lane_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x4_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=3`<br>`v -> Vn.4H` | `DUP Hd,Vn.H[lane]` | `Hd -> result` | `v7/A32/A64` |
| <code>mfloat8_t vgetq_lane_mf8(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x16_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=15`<br>`v -> Vn.16B` | `DUP Bd,Vn.B[lane]` | `Bd -> result` | `v7/A32/A64` |
| <code>float16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16" target="_blank">vgetq_lane_f16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float16x8_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=7`<br>`v -> Vn.8H` | `DUP Hd,Vn.H[lane]` | `Hd -> result` | `v7/A32/A64` |
| <code>float32_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32" target="_blank">vgetq_lane_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=3`<br>`v -> Vn.4S` | `DUP Sd,Vn.S[lane]` | `Sd -> result` | `v7/A32/A64` |
| <code>float64_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64" target="_blank">vgetq_lane_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t v,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `0<=lane<=1`<br>`v -> Vn.2D` | `DUP Dd,Vn.D[lane]` | `Dd -> result` | `A64` |
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