Merge pull request #6 from Accelergy-Project/allow_custom_art_ert

Add the option to provide ART and ERT keywords

run_tests.py

@@ -1,5 +1,7 @@
 from tests import (
+    test_art,
     test_constraints,
+    test_ert,
     test_nest,
     test_node,
     test_math_parsing,
@@ -17,7 +19,9 @@
 if __name__ == "__main__":
     loader = unittest.TestLoader()
     suite = unittest.TestSuite()
+    suite.addTests(loader.loadTestsFromModule(test_art))
     suite.addTests(loader.loadTestsFromModule(test_constraints))
+    suite.addTests(loader.loadTestsFromModule(test_ert))
     suite.addTests(loader.loadTestsFromModule(test_nest))
     suite.addTests(loader.loadTestsFromModule(test_node))
     suite.addTests(loader.loadTestsFromModule(test_math_parsing))

tests/art.yaml

@@ -0,0 +1,7 @@
+ART:
+    version: 0.4
+    tables:
+    - name: ComponentA
+      area: 1.0
+    - name: ComponentB
+      area: 2.0

tests/ert.yaml

@@ -0,0 +1,22 @@
+ERT:
+    version: '0.4'
+    tables:
+      - name: ComponentA
+        actions:
+          - name: ActionA1
+            arguments:
+                global_cycle_seconds: 1e-09
+                action_latency_cycles: 1
+            energy: 1.0
+          - name: ActionA2
+            arguments:
+                global_cycle_seconds: 1e-09
+                action_latency_cycles: 1
+            energy: 2.0
+      - name: ComponentB
+        actions:
+          - name: ActionB1
+            arguments:
+                global_cycle_seconds: 1e-09
+                action_latency_cycles: 1
+            energy: 3.0

tests/test_art.py

@@ -0,0 +1,19 @@
+from pathlib import Path
+import unittest
+
+from timeloopfe.v4.specification import Specification
+
+
+class TestArt(unittest.TestCase):
+    TEST_DIR = Path(__file__).parent
+    ARCH_NEST_PATH = str(TEST_DIR / 'arch_nest.yaml')
+    ART_PATH = str(TEST_DIR / 'art.yaml')
+
+    def test_art(self):
+        spec = Specification.from_yaml_files(
+            TestArt.ARCH_NEST_PATH, TestArt.ART_PATH
+        )
+        self.assertEqual(spec.ART.tables[0].name, "ComponentA")
+        self.assertEqual(spec.ART.tables[0].area, 1.0)
+        self.assertEqual(spec.ART.tables[1].name, "ComponentB")
+        self.assertEqual(spec.ART.tables[1].area, 2.0)

tests/test_ert.py

@@ -0,0 +1,27 @@
+from pathlib import Path
+import unittest
+
+from timeloopfe.v4.specification import Specification
+
+
+class TestErt(unittest.TestCase):
+    TEST_DIR = Path(__file__).parent
+    ARCH_NEST_PATH = str(TEST_DIR / 'arch_nest.yaml')
+    ERT_PATH = str(TEST_DIR / 'ert.yaml')
+
+    def test_ert(self):
+        spec = Specification.from_yaml_files(
+            TestErt.ARCH_NEST_PATH, TestErt.ERT_PATH
+        )
+
+        ert = spec.ERT.tables
+
+        self.assertEqual(ert[0].name, 'ComponentA')
+        self.assertEqual(ert[0].actions[0].name, 'ActionA1')
+        self.assertEqual(ert[0].actions[0].energy, 1.0)
+        self.assertEqual(ert[0].actions[1].name, 'ActionA2')
+        self.assertEqual(ert[0].actions[1].energy, 2.0)
+
+        self.assertEqual(ert[1].name, 'ComponentB')
+        self.assertEqual(ert[1].actions[0].name, 'ActionB1')
+        self.assertEqual(ert[1].actions[0].energy, 3.0)

tests/test_node.py

@@ -4,7 +4,7 @@
     ConstraintAttacherProcessor,
 )
 from timeloopfe.common.processor import Processor
-from timeloopfe.common.nodes import ParseError
+from timeloopfe.common.nodes import DictNode, ParseError
 from timeloopfe.v4.specification import Specification
 from timeloopfe.v4.arch import (
     Component,
@@ -74,6 +74,7 @@ def process(self, spec: Specification):
                     print(f"Checking {e.name} {e.__class__.__name__}")
                     e.pop("for_testing_ignoreme", None)
 
+
         spec = self.get_spec(processors=[Test])
         spec.architecture.nodes.insert(
             0, Component({"name": ".", "class": "storage", "for_testing_ignoreme": "."})

timeloopfe/common/nodes.py

@@ -42,6 +42,7 @@ def __repr__(self):
 
 default_unspecified_ = Unspecified()
 
+
 T = TypeVar("T", bound="Node")
 
 
@@ -192,6 +193,7 @@ def check_type(self, value: Any, node: "Node", key: str):
             if isinstance(self.required_type, tuple)
             else (self.required_type,)
         )
+
         for s in t:
             if isinstance(s, str) and str(value) == s:
                 return True

timeloopfe/common/version_transpilers/v4_to_v3.py

@@ -3,6 +3,7 @@
 from ...v4.specification import Specification
 from ...v4 import arch, constraints
 from ...v4.arch import Attributes, Nothing, Spatial
+from ..nodes import isempty
 import logging
 
 
@@ -196,4 +197,8 @@ def transpile(spec: Specification, for_model: bool = False):
         rval["mapspace"] = spec.mapspace
     if spec.get("globals", None):
         rval["globals"] = spec.globals
+    if not isempty(spec.get("ART", None)):
+        rval["ART"] = spec.ART
+    if not isempty(spec.get("ART", None)):
+        rval["ERT"] = spec.ERT
     return rval

timeloopfe/v4/art.py

@@ -0,0 +1,32 @@
+from ..common.nodes import DictNode, ListNode
+
+
+class Art(DictNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+        super().add_attr("version", default="0.4")
+        super().add_attr("tables", Tables)
+
+    def isempty(self) -> bool:
+        return self.tables.isempty()
+
+
+class Tables(ListNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+        super().add_attr("", Table)
+
+
+class Table(DictNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+        super().add_attr("name", str)
+        super().add_attr("area", float)
+
+
+Art.declare_attrs()
+Tables.declare_attrs()
+Table.declare_attrs()

timeloopfe/v4/ert.py

@@ -0,0 +1,58 @@
+from ..common.nodes import DictNode, ListNode
+
+
+class Ert(DictNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+
+        super().add_attr("version", default="0.4")
+        super().add_attr("tables", Tables)
+
+    def isempty(self) -> bool:
+        return self.tables.isempty()
+
+
+class Tables(ListNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+
+        super().add_attr("", Table)
+
+
+class Table(DictNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+
+        super().add_attr("name", str)
+        super().add_attr("actions", Actions)
+
+
+class Actions(ListNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+
+        super().add_attr("", Action)
+
+
+class Action(DictNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+
+        super().add_attr("name", str)
+        super().add_attr("arguments", ActionArguments)
+        super().add_attr("energy", float)
+
+
+class ActionArguments(DictNode):
+    @classmethod
+    def declare_attrs(cls, *args, **kwargs):
+        super().declare_attrs(*args, **kwargs)
+
+
+for cls in [Ert, Tables, Table, Actions, Action, ActionArguments]:
+    cls.declare_attrs()

timeloopfe/v4/specification.py

@@ -2,7 +2,9 @@
 from . import arch, constraints, problem, variables
 from ..common.nodes import ListNode
 from .arch import Architecture
+from .art import Art
 from .constraints import Constraints, ConstraintsList
+from .ert import Ert
 from .problem import Problem
 from .variables import Variables
 from .components import Components
@@ -53,6 +55,8 @@ def declare_attrs(cls, *args, **kwargs):
         super().add_attr("variables", Variables, {"version": 0.4})
         super().add_attr("mapspace", Mapspace, {"version": 0.4})
         super().add_attr("globals", Globals, {"version": 0.4}, part_name_match=True)
+        super().add_attr("ERT", Ert, {"version": 0.4, "tables": []})
+        super().add_attr("ART", Art, {"version": 0.4, "tables": []})
 
     def __init__(self, *args, **kwargs):
         from .processors import REQUIRED_PROCESSORS