AES-256 Modification with Dynamic SBox and Custom PRNG

Overview

This project implements a modified version of the AES-256 encryption algorithm. The enhancements include a dynamic SBox substitution mechanism powered by a ChaCha20-based pseudo-random number generator (PRNG) and flexible parameterization to explore new cryptographic techniques. This implementation provides a balance between strong encryption and a modular design for customization and experimentation.

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Key Features

Dynamic SBox Substitution

• Utilizes a ChaCha20-based PRNG to dynamically generate constants for SBox substitution.
• Enhances security by introducing round-dependent randomness to the substitution process.
• Increases resilience against attacks targeting static substitution tables.

Modified AES-256 Workflow

• Retains the core AES structure with 14 rounds of transformations.
• Includes:
  • AddRoundKey: XORs the state with round-specific keys.
  • Dynamic SBox Substitution: Replaces static SBoxes with PRNG-generated transformations.
  • ShiftRows: Circular byte shifts for diffusion.
  • MixColumns: Multiplication in GF(2^8) for further diffusion in encryption; InverseMixColumns for decryption.

ChaCha20-based PRNG

• Generates pseudo-random values for SBox transformations.
• Incorporates a 256-bit seed and round-dependent input to ensure unique outputs for each encryption round.

Flexible Design

• Parameterized for easy experimentation with:
  • Number of rounds (default: 14).
  • Key size (default: 256 bits).
  • Custom PRNG integration.

Comprehensive Decryption Path

• Implements inverse transformations:
  • InverseShiftRows: Reverses the byte shifts.
  • InverseSubBytes: Uses PRNG outputs to reverse dynamic SBox transformations.
  • InverseMixColumns: Undoes column mixing for decryption.

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Architecture

The system is designed using modular Verilog code, with each AES transformation encapsulated in its module:

• Encryption Path: Implements the full encryption process, including MixColumns for rounds 1–13 and the final round with no mixing.
• Decryption Path: Mirrors the encryption process using inverse transformations, with InverseMixColumns applied in all rounds except the final round.
• Key Expansion Module: Generates round keys for all transformations.
• PRNG Module: Dynamically generates round-specific constants.

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Code Highlights

• Encryption Module:

  • Chains all AES rounds with dynamic SBox substitutions and applies MixColumns in rounds 1–13 for diffusion.
  • The last round skips MixColumns but still applies the other transformations.
  • Displays intermediate states for debugging and verification.

• Decryption Module:

  • Applies inverse transformations in reverse order for seamless plaintext recovery, skipping InverseMixColumns in the last round.

• PRNG:

  • ChaCha20-inspired generator ensures reproducible randomness for cryptographic strength.

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Usage

Encryption Example

In the encryption process, each round involves the following transformations:

1. AddRoundKey: The plaintext is XORed with a round key.
2. Dynamic SBox Substitution: The bytes are substituted using a dynamic SBox generated by the ChaCha20-based PRNG.
3. ShiftRows: The rows are cyclically shifted.
4. MixColumns: For rounds 1–13, the bytes undergo a matrix multiplication in GF(2^8), spreading the influence of each byte across the columns.

The last round (round 14) skips MixColumns and performs the following:

• AddRoundKey.
• Dynamic SBox Substitution.
• ShiftRows.

Decryption Example

In the decryption process, the operations are applied in reverse order:

1. AddRoundKey: The ciphertext is XORed with the round key in reverse.
2. InverseSubBytes: Each byte is substituted using the inverse of the dynamic SBox.
3. InverseShiftRows: The rows are cyclically shifted back to their original position.
4. InverseMixColumns: For rounds 1–13, the inverse of the MixColumns operation is applied to undo the mixing in the encryption process.

The last round (round 14) skips InverseMixColumns and performs the following:

• AddRoundKey.
• InverseSubBytes.
• InverseShiftRows.

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Future Enhancements

• Integration of UVM and proper test benches to test it against benchmarks effectively.
• Optimizations for FPGA and ASIC implementations.
• Exploration of hybrid cryptographic techniques by combining AES with other ciphers.

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Getting Started

1. Clone the repository.
2. Simulate the design using a Verilog simulator (e.g., ModelSim, Vivado).
3. Use the provided basic test benches provided to encrypt and decrypt.

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Contributions

We welcome contributions to:

• Improve the modularity of the code.
• Enhance the randomness mechanisms.
• Test the implementation against known cryptographic attacks.

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Acknowledgments

Inspired by the principles of AES and ChaCha20, this project combines the strengths of both algorithms to push the boundaries of cryptographic design.