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jakubcabal committed Apr 12, 2024
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Expand Down Expand Up @@ -569,6 +569,16 @@ <h2>Ports and generics of the Application<a class="headerlink" href="#ports-and-
<td><p>in</p></td>
<td><p>reset input synchronized with CLK_USER_X4</p></td>
</tr>
<tr class="row-odd" id="vhdl-portsignal-application_core-clk_eth"><td><p>CLK_ETH</p></td>
<td><p>std_logic_vector(ETH_STREAMS-1 downto 0)</p></td>
<td><p>in</p></td>
<td><p>clock input with ethernet core frequency for each ETH stream</p></td>
</tr>
<tr class="row-even" id="vhdl-portsignal-application_core-reset_eth"><td><p>RESET_ETH</p></td>
<td><p>std_logic_vector(ETH_STREAMS-1 downto 0)</p></td>
<td><p>in</p></td>
<td><p>reset input synchronized with CLK_ETH for each ETH stream</p></td>
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<tr class="row-odd"><td><p>=====</p></td>
<td><p>CLOCK AND RESET OUTPUTS (DEFINED BY APPLICATION)</p></td>
<td><p>=====</p></td>
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