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qasm reject incomplete cl registers #1655

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1 change: 1 addition & 0 deletions pytket/docs/changelog.rst
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ Fixes:
* Support converting conditional `RangePredicate`s to QASM.
* Fix `maxwidth` parameter of `circuit_from_qasm_str`
* Add `scratch_reg_resize_pass` to `circuit_from_qasm_str`
* Reject incompete classical registers in pytket to qasm conversion

1.34.0 (October 2024)
---------------------
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6 changes: 6 additions & 0 deletions pytket/pytket/qasm/qasm.py
Original file line number Diff line number Diff line change
Expand Up @@ -1142,6 +1142,12 @@ def check_can_convert_circuit(circ: Circuit, header: str, maxwidth: int) -> None
f"Circuit contains a classical register larger than {maxwidth}: try "
"setting the `maxwidth` parameter to a higher value."
)
set_circ_register = set([creg.name for creg in circ.c_registers])
for b in set([b.reg_name for b in circ.bits]):
if b not in set_circ_register:
raise QASMUnsupportedError(
f"Circuit contains a invalid classical register {b}."
)
# Empty CustomGates should have been removed by DecomposeBoxes().
for cmd in circ:
assert not is_empty_customgate(cmd.op)
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13 changes: 13 additions & 0 deletions pytket/tests/qasm_test.py
Original file line number Diff line number Diff line change
Expand Up @@ -114,6 +114,16 @@ def test_long_registers_2() -> None:
assert creg.size <= 100


def test_incompete_registers() -> None:
c = Circuit(1)
c.add_bit(Bit("d", 1))
c.add_bit(Bit("d", 2))
c.Measure(Qubit(0), Bit("d", 1))
with pytest.raises(QASMUnsupportedError) as errorinfo:
circuit_to_qasm_str(c, header="hqslib1")
assert "Circuit contains a invalid classical register d." in str(errorinfo.value)


def test_qasm_qubit() -> None:
with pytest.raises(RuntimeError) as errorinfo:
fname = str(curr_file_path / "qasm_test_files/test2.qasm")
Expand Down Expand Up @@ -240,6 +250,9 @@ def test_conditional_gates() -> None:

def test_named_conditional_barrier() -> None:
circ = Circuit(2, 2)
circ.add_bit(Bit("test", 0))
circ.add_bit(Bit("test", 1))
circ.add_bit(Bit("test", 2))
circ.add_bit(Bit("test", 3))
circ.Z(0, condition_bits=[0, 1], condition_value=2)
circ.add_conditional_barrier(
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