Refactor DataDepGraph to facilitate unit testing

include/opt-sched/Scheduler/data_dep.h

@@ -173,11 +173,12 @@ class DataDepGraph : public llvm::opt_sched::OptSchedDDGWrapperBase,
                      public DirAcycGraph,
                      public DataDepStruct {
 public:
-  DataDepGraph(MachineModel *machMdl, LATENCY_PRECISION ltncyPcsn);
+  DataDepGraph(MachineModel *machMdl);
   virtual ~DataDepGraph();
 
   // Reads the data dependence graph from a text file.
   FUNC_RESULT ReadFrmFile(SpecsBuffer *buf, bool &endOfFileReached);
+  FUNC_RESULT ReadFromString(const std::string &Str);
   // Continues reading until the end of the current graph definition,
   // discarding the data.
   FUNC_RESULT SkipGraph(SpecsBuffer *buf, bool &endOfFileReached);
@@ -367,7 +368,6 @@ class DataDepGraph : public llvm::opt_sched::OptSchedDDGWrapperBase,
   int entryInstCnt_;
   int exitInstCnt_;
 
-  LATENCY_PRECISION ltncyPrcsn_;
   int edgeCntPerLtncy_[MAX_LATENCY_VALUE + 1];
 
   // Tracks all registers in the scheduling region. Each RegisterFile

lib/Scheduler/data_dep.cpp

@@ -144,8 +144,7 @@ InstCount DataDepStruct::CmputAbslutUprBound_() {
   return schedUprBound_;
 }
 
-DataDepGraph::DataDepGraph(MachineModel *machMdl, LATENCY_PRECISION ltncyPrcsn)
-    : DataDepStruct(machMdl) {
+DataDepGraph::DataDepGraph(MachineModel *machMdl) : DataDepStruct(machMdl) {
   int i;
 
   type_ = DGT_FULL;
@@ -154,7 +153,6 @@ DataDepGraph::DataDepGraph(MachineModel *machMdl, LATENCY_PRECISION ltncyPrcsn)
   weight_ = 1.0;
   outptDags_ = ODG_ALL;
   maxOutptDagSize_ = 1000;
-  ltncyPrcsn_ = ltncyPrcsn;
   includesCall_ = false;
   includesUnpipelined_ = false;
 
@@ -339,6 +337,16 @@ void DataDepGraph::SetDynmcLwrBounds() {
   }
 }
 
+FUNC_RESULT DataDepGraph::ReadFromString(const std::string &Str) {
+  char *BufData = new char[Str.size() + 1];
+  std::copy_n(Str.data(), Str.size() + 1, BufData);
+  SpecsBuffer Buf;
+  Buf.SetBuf(BufData, Str.size() + 1);
+
+  bool EndReached = false;
+  return ReadFrmFile(&Buf, EndReached);
+}
+
 FUNC_RESULT DataDepGraph::ReadFrmFile(SpecsBuffer *buf,
                                       bool &endOfFileReached) {
   int pieceCnt;

lib/Wrapper/OptSchedDDGWrapperBasic.cpp

@@ -52,8 +52,8 @@ OptSchedDDGWrapperBasic::OptSchedDDGWrapperBasic(
     MachineSchedContext *Context, ScheduleDAGOptSched *DAG,
     OptSchedMachineModel *MM, LATENCY_PRECISION LatencyPrecision,
     const std::string &RegionID)
-    : DataDepGraph(MM, LatencyPrecision), MM(MM), Contex(Context), DAG(DAG),
-      RTFilter(nullptr) {
+    : DataDepGraph(MM), MM(MM), Contex(Context), DAG(DAG),
+      LatencyPrecision(LatencyPrecision), RTFilter(nullptr) {
   dagFileFormat_ = DFF_BB;
   isTraceFormat_ = false;
   TreatOrderDepsAsDataDeps =
@@ -447,11 +447,14 @@ void OptSchedDDGWrapperBasic::convertEdges(const SUnit &SU,
     }
 
     int16_t Latency;
-    if (ltncyPrcsn_ == LTP_PRECISE) { // get latency from the machine model
+    switch (LatencyPrecision) {
+    case LTP_PRECISE: { // get latency from the machine model
       const auto &InstName = DAG->TII->getName(instr->getOpcode());
       const auto &InstType = MM->GetInstTypeByName(InstName);
       Latency = MM->GetLatency(InstType, DepType);
-    } else if (ltncyPrcsn_ == LTP_ROUGH) { // rough latency = llvm latency
+      break;
+    }
+    case LTP_ROUGH: { // rough latency = llvm latency
       Latency = I->getLatency();
       // If latency is above a specified target then reduce the latency
       // by the specified divisor
@@ -468,12 +471,16 @@ void OptSchedDDGWrapperBasic::convertEdges(const SUnit &SU,
         Logger::Event("ReduceLatency", "FromInstruction", InstFromName.c_str(),
                       "ToInstruction", InstToName.c_str(), "OriginalLatency",
                       OldLatency, "NewLatency", Latency);
+        break;
       }
-    } else
+    }
+    case LTP_UNITY:
       Latency = 1; // unit latency = ignore ilp
 
-    CreateEdge_(SU.NodeNum, I->getSUnit()->NodeNum, Latency, DepType,
-                IsArtificial);
+      CreateEdge_(SU.NodeNum, I->getSUnit()->NodeNum, Latency, DepType,
+                  IsArtificial);
+      break;
+    }
   }
 }
 

unittests/Basic/CMakeLists.txt

@@ -5,4 +5,5 @@ add_optsched_unittest(OptSchedBasicTests
   LoggerTest.cpp
   UtilitiesTest.cpp
   simple_machine_model_test.cpp
+  ddg_test.cpp
   )

unittests/Basic/ddg.h

@@ -0,0 +1,45 @@
+#ifndef OPTSCHED_TESTS_DDG_H
+#define OPTSCHED_TESTS_DDG_H
+
+#include "opt-sched/Scheduler/data_dep.h"
+#include "simple_machine_model.h"
+#include "gtest/gtest.h"
+#include <memory>
+#include <string>
+
+std::shared_ptr<llvm::opt_sched::DataDepGraph>
+makeDDG(const std::string &DDG,
+        llvm::opt_sched::MachineModel *Model = nullptr) {
+  using namespace llvm::opt_sched;
+
+  class SimpleDDG : public DataDepGraph {
+  public:
+    using DataDepGraph::DataDepGraph;
+
+    void convertSUnits(bool, bool) override {
+      FAIL() << "Unsupported operation convertSUnits()";
+    }
+    void convertRegFiles() override {
+      FAIL() << "Unsupported operation convertRegFiles()";
+    }
+  };
+
+  struct DDGData {
+    std::unique_ptr<MachineModel> Model = nullptr;
+    SimpleDDG DDG;
+
+    DDGData(MachineModel *Model) : DDG(Model) {}
+    DDGData()
+        : Model(llvm::make_unique<MachineModel>(simpleMachineModel())),
+          DDG(Model.get()) {}
+  };
+
+  auto Result =
+      Model ? std::make_shared<DDGData>(Model) : std::make_shared<DDGData>();
+  auto Ret = Result->DDG.ReadFromString(DDG);
+  EXPECT_TRUE(Ret != RES_ERROR && Ret != RES_FAIL && Ret != RES_TIMEOUT)
+      << "Failed to parse DDG";
+  return std::shared_ptr<DataDepGraph>(Result, &Result->DDG);
+}
+
+#endif

unittests/Basic/ddg_test.cpp

@@ -0,0 +1,163 @@
+#include "ddg.h"
+
+#include "gtest/gtest-spi.h"
+#include "gtest/gtest.h"
+
+using namespace llvm::opt_sched;
+
+namespace {
+TEST(SimpleDDG, CanBeMade) {
+  std::shared_ptr<DataDepGraph> DDG = makeDDG(R"(
+dag 7 "Simple"
+{
+dag_id fake:3
+dag_weight 1.000000
+compiler LLVM
+dag_lb -1
+dag_ub -1
+nodes
+node 0 "Inst"
+    sched_order 0
+    issue_cycle 0
+node 1 "Inst"
+    sched_order 1
+    issue_cycle 1
+node 2 "Inst"
+    sched_order 2
+    issue_cycle 2
+node 3 "Inst"
+    sched_order 3
+    issue_cycle 3
+node 4 "Inst"
+    sched_order 4
+    issue_cycle 4
+node 5 "artificial"  "__optsched_entry"
+node 6 "artificial"
+dependencies
+dep 0 1 "other" 0
+dep 1 2 "other" 0
+dep 2 6 "other" 0
+dep 3 4 "data" 1
+dep 4 6 "other" 0
+dep 5 3 "other" 0
+dep 5 0 "other" 0
+}
+  )");
+
+  EXPECT_EQ(7, DDG->GetNodeCnt());
+}
+
+TEST(SimpleDDG, CanBeMadeWithRealData) {
+  MachineModel Model = simpleMachineModel();
+  {
+    InstTypeInfo Info;
+    Info.issuType = Model.getDefaultIssueType();
+    Info.name = "ATOMIC_FENCE";
+    Info.isCntxtDep = false;
+    Info.ltncy = 0;
+    Info.pipelined = true;
+    Info.sprtd = true;
+    Info.blksCycle = true;
+    Model.AddInstType(Info);
+
+    Info.name = "S_BARRIER";
+    Model.AddInstType(Info);
+
+    Info.name = "S_ADD_I32";
+    Info.ltncy = 1;
+    Model.AddInstType(Info);
+
+    Info.name = "S_CMP_LT_U32";
+    Info.ltncy = 1;
+    Model.AddInstType(Info);
+  }
+
+  std::shared_ptr<DataDepGraph> DDG = makeDDG(R"(
+dag 7 "Simple"
+{
+dag_id kernel_c18_sdk_94:3
+dag_weight 1.000000
+compiler LLVM
+dag_lb -1
+dag_ub -1
+nodes
+node 0 "ATOMIC_FENCE"
+    sched_order 0
+    issue_cycle 0
+node 1 "S_BARRIER"  "S_BARRIER"
+    sched_order 1
+    issue_cycle 1
+node 2 "ATOMIC_FENCE"  "ATOMIC_FENCE"
+    sched_order 2
+    issue_cycle 2
+node 3 "S_ADD_I32"  "S_ADD_I32"
+    sched_order 3
+    issue_cycle 3
+node 4 "S_CMP_LT_U32"  "S_CMP_LT_U32"
+    sched_order 4
+    issue_cycle 4
+node 5 "artificial"  "__optsched_entry"
+node 6 "artificial"
+dependencies
+dep 0 1 "other" 0
+dep 1 2 "other" 0
+dep 2 6 "other" 0
+dep 3 4 "data" 1
+dep 4 6 "other" 0
+dep 5 3 "other" 0
+dep 5 0 "other" 0
+}
+  )",
+                                              &Model);
+
+  EXPECT_EQ(7, DDG->GetNodeCnt());
+}
+
+TEST(SimpleDDG, VirtualFunctionsFailWell) {
+  static std::shared_ptr<DataDepGraph> DDG = makeDDG(R"(
+dag 3 "Simple"
+{
+dag_id fake:3
+dag_weight 1.000000
+compiler LLVM
+dag_lb -1
+dag_ub -1
+nodes
+node 0 "Inst"
+    sched_order 0
+    issue_cycle 0
+node 1 "artificial"  "__optsched_entry"
+node 2 "artificial"
+dependencies
+dep 0 1 "other" 0
+dep 1 2 "other" 0
+}
+  )");
+
+  EXPECT_FATAL_FAILURE(DDG->convertRegFiles(),
+                       "Unsupported operation convertRegFiles");
+  EXPECT_FATAL_FAILURE(DDG->convertSUnits(true, true),
+                       "Unsupported operation convertSUnits");
+}
+
+TEST(SimpleDDG, MakeInvalidDDGFailsWell) {
+  EXPECT_NONFATAL_FAILURE(makeDDG(R"(
+dag 3 "Simple"
+{
+dag_id fake:3
+dag_weight 1.000000
+compiler LLVM
+dag_lb -1
+dag_ub -1
+nodes
+node 0 "Inst"
+    sched_order 0
+    issue_cycle 0
+node 1 "artificial"  "__optsched_entry"
+node 2 "artificial"
+dependencies
+}
+  )"),
+                          "parse DDG");
+}
+} // namespace