An AXI4L hardware vector adder. The AXI4L interface is based on https://github.com/ZipCPU/wb2axip. The testbench uses resources from AMD's Vivado. The host app uses resources generated by AMD's Vitis.
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This repository contains the Verilog code and testbenches for a hardware vector adder. The vector adder is designed to perform element-wise addition of two vectors.
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Eduardo-bat/verilog-hardware-vector-adder
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This repository contains the Verilog code and testbenches for a hardware vector adder. The vector adder is designed to perform element-wise addition of two vectors.
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