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UHD 4.0.0.0 Release Candidate 1

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@michael-west michael-west released this 14 Sep 03:58
· 2204 commits to master since this release
v4.0.0.0-rc1
4c8ba57

004.000.000.000

  • b200:
    • Enable power calibration API
    • Add a prop tree node usb_version
  • cal:
    • Add utility to update all .fbs files, or check the generated ones
    • Add pwr_cal container
  • cmake:
    • Add ability to pass CXXFLAGS to CMake environment
  • docs:
    • Update PCIe xport instructions for NI Repos
    • n3xx: Include WX in table of N320 images
    • Add stream and transport args documentation
    • Update Basic/LF dboard references to use new operating mode
    • e3xx/n3xx: Add sections on FP-GPIOs and how to drive them
    • n3xx: Document eeprom flags
    • Add note about DPDK needing to be built as shared libraries
    • Change DPDK version to 18.11 and make args use underscores
    • Clarifying which devices support DPDK
  • dpdk:
    • Add new DPDK stack to integrate with I/O services
  • e31x:
    • Change RFNoC Ctrl clock to 40 MHz
    • Fix timeout for timekeeper registers
    • Fix filter bank and antenna switching for channel 0
    • Swap out liberio for internal Ethernet
  • e320:
    • Fix timeout for timekeeper registers
    • Swap out liberio for internal Ethernet
  • examples:
    • Add usrp_power_meter example
    • Update test_messages example
    • Update gpio example
    • Add options to benchmark_rate
    • Add example out-of-tree module for RFNoC modules
    • Remove thread priority elevation
  • fpga:
    • Replaced RFNoC architecture with new 4.0 version
    • Added modelsim make simulation target
    • Upgrade to Vivade 2019.1
    • Removed unused coregen files and modules
    • Removed fpga submodule and merged into uhd repo
    • lib: Change max FFT size to 1024
    • lib: add Intel MAX10 architecture for 2clk FIFO
    • rfnoc: Port RFNoC Keep One in N block to new RFNoC architecture
    • rfnoc: Port RFNoC Replay block to new RFNoC architecture
    • rfnoc: Port Signal Generator RFNoC block to new RFNoC architecture
    • Add Switchboard RFNoC block
    • Remove liberio
    • rfnoc: Port RFNoC Moving Average block to new RFNoC architecture
    • rfnoc: Port Log-Power block to new RFNoC architecture
    • rfnoc: Port RFNoC Window block to new RFNoC architecture
    • lib: Add synthesizable AXI4-Stream SV components
    • lib: Add interface and model for AXI4-Lite
    • rfnoc: Add support for 512-bit CHDR widths
    • rfnoc: Port RFNoC Add/Sub block to new RFNoC architecture
    • rfnoc: Port Vector IIR RFNoC block to new RFNoC architecture
    • lib: Add AXI-Stream splitter (axis_split)
  • lib:
    • Add power cal manager
    • deps: Add FlatBuffers 1.11.0 header files
    • Add DPDK service queue
  • mpm:
    • Exclude internal NIC for network hosts
    • Add ability to run scripts to MPM shell
    • n3xx: Remove eth1, eth2 from interface list
    • Default virtual NIC CHDR IP selection
    • Enable internal NIC on the N3xx
    • Clean up code, improve Pylint score
    • Move common mboard regs code to common location
  • mpmd:
    • Remove liberio
  • multi_usrp:
    • Fix connect/disconnect of RFNoC chains
    • Various multi_usrp_rfnoc fixes
  • n310:
    • Fix GPIO registers
  • n320:
    • Double radio ingress buffer size
    • Enable inverse sinc filter for DAC37J82
  • n3xx:
    • Fix timeout for timekeeper registers
    • Swap out liberio for internal Ethernet
  • python:
    • Add Keep One in N block controller bindings
    • Add replay RFNoC block controller bindings
    • Add siggen RFNoC block controller bindings
    • Add Switchboard block python bindings
    • Add moving average RFNoC block controller bindings
    • Add bindings for C++ CHDR Parser
    • Add window RFNoC block controller bindings
    • Add FFT RFNoC block controller bindings
    • Add null RFNoC block controller bindings
    • Add vector IIR RFNoC block controller bindings
    • Add radio RFNoC block controller bindings
    • Add FIR filter RFNoC block controller bindings
    • Add Fosphor RFNoC block controller bindings
    • Add DUC RFNoC block controller bindings
    • Add DDC RFNoC block controller bindings
    • Added new RFNoC image builder module under the uhd module
    • Remove Python2-specific code
    • Included complex.h to allow pybind to convert that data type
  • rfnoc:
    • Add multichannel register interface
    • Added support for destruction of streamers
    • Add Keep One in N block support
    • Port siggen RFNoC block controller support to new RFNoC architecture
    • Add Switchboard block support
    • Port Moving Average block controller to new RFNoC architecture
    • Port Log Power RFNoC block support to new RFNoC architecture
    • Port window RFNoC block controller to new RFNoC architecture
    • Port Add/Sub RFNoC block support to new RFNoC architecture
    • Add USE_MAP prop/action forwarding policy
    • Port Split Stream RFNoC block to new RFNoC architecture
    • Port Vector IIR RFNoC block support to new RFNoC architecture
    • Port RFNoC fosphor block to new RFNoC architecture
    • Port FIR filter RFNoC block controller to new RFNoC architecture
    • Add multichannel register interface
    • Add RFNoC Python API
    • Unify endianness of transports
    • Add DMA FIFO block controller
    • examples: Port examples to new RFNoC
    • Implement flushing on overrun
    • client_zero can track num SEPs and num ctrl EPs separately
    • Add basic round-robin allocation for links
    • Add ability to select transport for streamers to user APIs
    • Use link_stream_manager's mgmt_portal for all mgmt packets
    • graph: Optimize property propagation algorithm
    • Port DUC block controller to new RFNoC architecture
    • Add MTU tracking
    • Implement overrun handling using action API
    • Port null block controller to new RFNoC architecture
    • Add mb_controller API
    • Port radio block controller to new RFNoC architecture
    • Port default block controller to new RFNoC architecture
    • Port DDC block controller to new RFNoC architecture
    • Add rfnoc_graph class
    • Add action API
    • Refactored CHDR packet interfaces
    • Add noc_block_base class
  • tests:
    • Add unit tests for new RFNoC block controllers
    • Fix multi_usrp_test
    • Add unit tests for pwr_cal_mgr
    • Migrated rfnoc block tests to dedicated subdirectory
    • Add more tests for max rate streaming
    • Add tests to exercise max streaming rates and report results
  • tools:
    • Update dissectors for Wireshark major version 3, new CHDR
    • Update FPGA functional verification tests for X3x0 mcr's & dpdk
  • transport:
    • Implement eov indications for Rx and Tx streams
    • Implement an I/O service that uses an offload thread
    • Implement a single-threaded I/O service
  • twinrx:
    • Update synthesizer register values for improved rf performance
    • Fix increased noise floor
    • Remove decimation from frontend
  • uhd:
    • Disable optimizations for Mac for build speed
    • remove liberio
    • improved handling of empty serial number hints
    • Add discoverable_features API
    • Add reference power level API to multi_usrp and radio_control
    • Add fuzzy serial number checking
    • paths: Harmonize around XDG Base Directory specification
    • cal: Use usrp::cal::database instead of CSV files
    • cal: Add iq_cal calibration data container class
    • cal: Add calibration container class
    • cal: Add database class
    • Introduce I/O service manager
    • Replace usage of boost smart pointers with C++11 counterparts
    • add udp boost asio implementation of transport interface
    • Add thread affinity utility functions
    • types: Extend stream_cmd_t::num_samps to 64 bits
  • utils:
    • Expose CHDR Parsing API
    • Expose CHDR Types in Public API
    • Support expressions for num_ports in block defs
    • Let uhd_images_downloader also use HTTPS proxies
    • Fix FPGA search in rfnoc_image_builder from fpga-src to fpga
    • Add convert_cal_data utility
    • image_builder: Support parameterized number of ports on blocks
  • x300:
    • Update frame sizes for 10GbE
    • Fix for incorrect PCIe buffer size values
    • Change default dboard clock rate from 50 to 100 MHz
    • Update maximum bitstream size
    • Enable power reference API
    • Expand DRAM address space to 1G
    • Add front-panel GPIO source control
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