v0.2.3

• Testbenches moved to the icewire-TB collection (by @Obijuan )
• Blocks and examples works ok with Icestudio 0.12 (Fix verify errors) (by @Obijuan )

Full Changelog: v0.2.2...v0.2.3

v0.2.2

Refactoring and verilog implementation:

• Copy: 2,3,4,5,6,7,8,9,10,11,12,16,20,24,26,27,28,29,30,31,32 bits
• Reversal: 2,3,4,5 bits
• SR1: 2,3,4,8,16,32 bits
• SL1: 2,3,4,8,16,32 bits
• Uint2
• Uint4-1,2,3 bits
• Uint8-1,2,3,4,5,7 bits
• Uint12 bits
• Uint32-31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16, 8, 2 bits
• Uint16-14,13,12,11,10,9,8 bits
• Sign-32,20,16,12,8,7,6,5,4,3,2 bits

v0.2.1

• Uint16: 10, 11, 12, 13, 14, 15bits
• Uint32: 2, 8, 16,17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31bits
• Join 16-bits: 06-10, 5-11, 03-13
• Join 32-bits: 11-21, 15-17, 14-18, 13-19, 11-21, 10-22, 9-23, 6-26, 5-27, 2-30, 12-20, 2-14, 14-2, 30-2
• Join 64bits half
• Split 64bits half
• Split 8 quarter
• Join 24-bits half
• Join 8 bits quarter
• copy-12-bits
• Github actions added

v0.2.0

Components

• Copy. Bits: 3-9
• Join blocks. Bits: 3-12, 15-16, 19-20, 22-24, 27-28, 31-32
• Split blocks. Bits: 3-12, 15-17, 19-20, 22-24, 27-28, 31-32
• Reversal. Bits: 2-4
• Shift (right,left). Bits: 2-4, 8, 16, 32
• Sign-int. Bits: 2-8, 12, 16, 20, 32
• Uint. Bits: 2,4,8,12,16
• Wire. Bits: 3-8

Examples

• Test circuits for all the components (Alhambra-II board)
• 2 more index added (02-index, 03-index)

Documentation

• Initial documentation added to the wiki

Translations

• Translated into Spanish

v0.1

Initial release

Components

• Wire
• Bus2
• Bus2-Split-all
• Bus2-Join-all
• Copy-2

Examples

• Test circuits for all the components (Alhambra-II board)
• Initial Index