Rename ARM_CA53_64_BIT/_SRE to Arm_AARCH64/_SRE

CMakeLists.txt

@@ -58,8 +58,8 @@ if(NOT FREERTOS_PORT)
         " CODEWARRIOR_COLDFIRE_V2          - Compiler: CoreWarrior   Target: ColdFire V2\n"
         " CODEWARRIOR_HCS12                - Compiler: CoreWarrior   Target: HCS12\n"
         " GCC_ARM_CA9                      - Compiler: GCC           Target: ARM Cortex-A9\n"
-        " GCC_ARM_CA53_64_BIT              - Compiler: GCC           Target: ARM Cortex-A53 64 bit\n"
-        " GCC_ARM_CA53_64_BIT_SRE          - Compiler: GCC           Target: ARM Cortex-A53 64 bit SRE\n"
+        " GCC_ARM_AARCH64                  - Compiler: GCC           Target: ARM v8-A\n"
+        " GCC_ARM_AARCH64_SRE              - Compiler: GCC           Target: ARM v8-A SRE\n"
         " GCC_ARM_CM0                      - Compiler: GCC           Target: ARM Cortex-M0\n"
         " GCC_ARM_CM3                      - Compiler: GCC           Target: ARM Cortex-M3\n"
         " GCC_ARM_CM3_MPU                  - Compiler: GCC           Target: ARM Cortex-M3 with MPU\n"

portable/CMakeLists.txt

@@ -67,13 +67,13 @@ add_library(freertos_kernel_port STATIC
         GCC/ARM_CA9/portASM.S>
 
     # ARMv8-A ports for GCC
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT>:
-        GCC/ARM_CA53_64_BIT/port.c
-        GCC/ARM_CA53_64_BIT/portASM.S>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:
+        GCC/Arm_AARCH64/port.c
+        GCC/Arm_AARCH64/portASM.S>
 
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT_SRE>:
-        GCC/ARM_CA53_64_BIT_SRE/port.c
-        GCC/ARM_CA53_64_BIT_SRE/portASM.S>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:
+        GCC/Arm_AARCH64_SRE/port.c
+        GCC/Arm_AARCH64_SRE/portASM.S>
 
     # ARMv6-M port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:
@@ -761,8 +761,8 @@ target_include_directories(freertos_kernel_port PUBLIC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA9>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9>
 
     # ARMv8-A ports for GCC
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT>
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT_SRE>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64_SRE>
 
     # ARMv6-M port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0>

portable/GCC/ARM_CA53_64_BIT/README.md

@@ -0,0 +1,16 @@
+# ARM_CA53_64_BIT port
+
+Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
+Arm Cortex-A53 processor.
+
+* ARM_CA53_64_BIT
+    * Memory mapped interace to access Arm GIC registers
+
+This port is generic and can be used as a starting point for other Armv8-A
+application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
+`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
+should migrate to renamed port `Arm_AARCH64`.
+
+**NOTE**
+
+This port uses memory mapped interace to access Arm GIC registers.

portable/GCC/ARM_CA53_64_BIT_SRE/README.md

@@ -0,0 +1,16 @@
+# ARM_CA53_64_BIT_SRE port
+
+Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
+Arm Cortex-A53 processor.
+
+* ARM_CA53_64_BIT_SRE
+    * System Register interace to access Arm GIC registers
+
+This port is generic and can be used as a starting point for other Armv8-A
+application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as
+`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`,
+should migrate to renamed port `Arm_AARCH64_SRE`.
+
+**NOTE**
+
+This port uses System Register interace to access Arm GIC registers.

portable/GCC/Arm_AARCH64/README.md

@@ -0,0 +1,23 @@
+# Armv8-A architecture support
+
+The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
+Execution states, known as AArch64 and AArch32 respectively. The AArch64
+Execution state supports the A64 instruction set. It holds addresses in 64-bit
+registers and allows instructions in the base instruction set to use 64-bit
+registers for their processing.
+
+The AArch32 Execution state is a 32-bit Execution state that preserves
+backwards compatibility with the Armv7-A architecture, enhancing that profile
+so that it can support some features included in the AArch64 state. It supports
+the T32 and A32 instruction sets. Follow the
+[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
+for more information.
+
+## Arm_AARCH64 port
+
+This port adds support for Armv8-A architecture AArch64 execution state.
+This port is generic and can be used as a starting point for Armv8-A
+application processors.
+
+* Arm_AARCH64
+    * Memory mapped interace to access Arm GIC registers

portable/GCC/Arm_AARCH64_SRE/README.md

@@ -0,0 +1,23 @@
+# Armv8-A architecture support
+
+The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
+Execution states, known as AArch64 and AArch32 respectively. The AArch64
+Execution state supports the A64 instruction set. It holds addresses in 64-bit
+registers and allows instructions in the base instruction set to use 64-bit
+registers for their processing.
+
+The AArch32 Execution state is a 32-bit Execution state that preserves
+backwards compatibility with the Armv7-A architecture, enhancing that profile
+so that it can support some features included in the AArch64 state. It supports
+the T32 and A32 instruction sets. Follow the
+[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
+for more information.
+
+## Arm_AARCH64_SRE port
+
+This port adds support for Armv8-A architecture AArch64 execution state.
+This port is generic and can be used as a starting point for Armv8-A
+application processors.
+
+* Arm_AARCH64_SRE
+    * System Register interace to access Arm GIC registers