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GallianoDean/README.md
  • 👋 Hi, I’m @GallianoDean. I currently have 2 years experience as an Engineering Technician II in the Systems Level Testing (SLT) laboratory at Qualcomm, where we perform

  • NPI (new Product Introduction) post-ATE testing on Qualcomm's flagship SoC devices: Including the Snapdragon(MSM) as well as RF modules. We "test the devices at the system

  • level" by emulating the end user envrionments (boot to Android, Windows) on evaluation and debugging boards: flashing builds, analyzing crashdumps, performing SLT Regression

  • tests, and most of all validating and packaging the Test Programs and DFT Test Patterns that will be used for production.

  • 👀 I’m interested in all things to do with Electrical Engineering, especially ASICs architecture, design, and verification processes and methodologies, as well as FPGA Design

  • and applications, generally anything to do with Digital Electronics, Computer Architetcure, and Embedded Systems.

  • I'm pursuing an MS-EE @ CU Boulder and am working towards transitioning to the position of Engineer in SLT at Qualcomm. I earned a BS in Applied Physics & Applied Mathematics from

  • Humboldt State University, and thanks to the skills and knowledge I continue to gain and apply in my role at Qualcomm, I have developed a strong passion in Electrical Engineering.

  • Indeed, I have finally gained the industry experiences to help me decide to focus on the career path that I most desire.

  • I continue to learn and strengthen my unerstanding of the Electrical Engineering subject areas that I had not previously studied as in-depth in my college curriculum, and am always

  • looking for great educational resources.

  • My current educational focus is on FPGA Design for Embedded Systems: given the similiar design and prototyping flow of FPGAs to ASICs, my interest really peaked in FPGAs! In fact,

  • the first pathway of courses that I am taking in the MS-EE program is on FPGA Design: Introduction to FPGAs, with heavy use of Quartus Primem including Qsys to implement the

  • Nios-II Soft Processor via the Avalaon-MM Interconnect; and of course Verilog/VHDL. As the courses use Quartus Prime, I am looking forward to getting used to Xilinx Vivado.

  • 📫 How to reach me: [email protected] or [email protected]

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