tidying up

software/glasgow/gateware/hyperram.py

@@ -100,12 +100,8 @@ class PHYx1(wiring.Component):
         })))
     })
 
-    def __init__(self, resource, *, cs_count=1):
-        if not isinstance(cs_count, int) or not cs_count >= 1:
-            raise ValueError(f"CS# count must be a positive integer, not {cs_count!r}")
-
+    def __init__(self, resource):
         self.resource = resource
-        self.cs_count = cs_count
 
         super().__init__(self.Signature.flip())
 
@@ -195,7 +191,7 @@ def elaborate(self, platform):
                 m.d.sync += clocked.eq(0)
                 with m.If(self.o.valid & (self.o.p.mode == PHYMode.Select)):
                     m.d.comb += self.o.ready.eq(1)
-                    cs_decoded = Cat(self.o.p.data == n for n in range(1, self.cs_count + 1))
+                    cs_decoded = Cat(self.o.p.data == n for n in range(1, len(pins_cs_o) + 1))
                     m.d.comb += pins_cs_o.eq(cs_decoded)
                     with m.If(cs_decoded != 0):
                         m.next = "Sample-Latency"
@@ -331,15 +327,19 @@ def address(self):
 
 
 class Sequencer(wiring.Component):
-    def __init__(self, phy):
-        self.phy = phy
-
+    def __init__(self, *, cs_count):
         super().__init__(Signature({
+            "rst": In(1),
+            "phy": Out(PHYx1.Signature),
             "ctl": In(StreamSignature(data.StructLayout({
-                "select"    : range(self.phy.cs_count + 1),
+                "select"    : range(cs_count + 1),
                 "cmd_addr"  : CommandAddress,
                 "latency"   : range(0, 16 + 1)
             }))),
+            # The memory has to be "pumped" when reading; that is, for each `i`nput transfer to
+            # happen, an `o`utput transfer has to happen first. Whether the input transfer will
+            # be the last one (with the sequencer getting another command from `ctl`) or not is
+            # determined by `o.last`. During reads, `o.data` and `o.mask` are not used.
             "o": In(StreamSignature(data.StructLayout({
                 "data"  : 16,
                 "mask"  : 2,

software/tests/gateware/test_hyperram.py

@@ -30,8 +30,9 @@ def elaborate(self, platform):
 
         m = Module()
 
-        m.submodules.phy = Fragment.get(phy := hyperram.PHYx1(resource=("hyperram", 0)), platform)
-        m.submodules.seq = seq = hyperram.Sequencer(phy)
+        m.submodules.phy = phy = hyperram.PHYx1(resource=("hyperram", 0))
+        m.submodules.seq = seq = hyperram.Sequencer(cs_count=1)
+        wiring.connect(m, seq.phy, phy)
 
         trigger_reg = Signal.like(self.trigger)
         m.d.sync += trigger_reg.eq(self.trigger)