resets

software/tests/gateware/test_hyperram.py

@@ -10,7 +10,7 @@
 
 
 class HyperRAMSequencerTestbench(wiring.Component):
-    ram_rst : In(1)
+    rst     : In(1)
     cmd_addr: In(hyperram.CommandAddress)
     latency : In(range(3, 17))
     length  : In(24)
@@ -32,7 +32,7 @@ def elaborate(self, platform):
         wiring.connect(m, seq.phy, phy)
 
         m.d.comb += [
-            seq.rst.eq(self.ram_rst),
+            seq.rst.eq(self.rst),
             seq.ctl.payload.select.eq(1),
             seq.ctl.payload.cmd_addr.eq(self.cmd_addr),
             seq.ctl.payload.latency.eq(self.latency),
@@ -47,10 +47,10 @@ def elaborate(self, platform):
 
         with m.FSM(name="output_fsm"):
             r_data_reg = Signal.like(self.out_fifo.r_data)
-            remaining = Signal.like(self.length)
+            remain = Signal.like(self.length)
 
             with m.State("Idle"):
-                m.d.sync += remaining.eq(self.length)
+                m.d.sync += remain.eq(self.length)
                 with m.If(seq.ctl.valid & seq.ctl.ready):
                     with m.If(seq.ctl.payload.cmd_addr.operation == hyperram.Operation.Read):
                         m.next = "Read"
@@ -59,14 +59,14 @@ def elaborate(self, platform):
 
             with m.State("Read"):
                 m.d.comb += [
-                    seq.o.payload.last.eq(remaining == 1),
+                    seq.o.payload.last.eq(remain == 1),
                     seq.o.valid.eq(1),
                 ]
                 with m.If(seq.o.ready):
-                    with m.If(remaining == 1):
+                    with m.If(remain == 1):
                         m.next = "Idle"
                     with m.Else():
-                        m.d.sync += remaining.eq(remaining - 1)
+                        m.d.sync += remain.eq(remain - 1)
 
             with m.State("Write-MSB"):
                 m.d.sync += [
@@ -82,15 +82,15 @@ def elaborate(self, platform):
                 m.d.comb += [
                     seq.o.payload.data[8:].eq(r_data_reg),
                     seq.o.payload.data[:8].eq(self.out_fifo.r_data),
-                    seq.o.payload.last.eq(remaining == 1),
+                    seq.o.payload.last.eq(remain == 1),
                     seq.o.valid.eq(self.out_fifo.r_rdy),
                     self.out_fifo.r_en.eq(seq.o.ready),
                 ]
                 with m.If(self.out_fifo.r_rdy & self.out_fifo.r_en):
-                    with m.If(remaining == 1):
+                    with m.If(remain == 1):
                         m.next = "Idle"
                     with m.Else():
-                        m.d.sync += remaining.eq(remaining - 1)
+                        m.d.sync += remain.eq(remain - 1)
                         m.next = "Write-MSB"
 
         with m.FSM(name="input_fsm"):
@@ -128,33 +128,28 @@ async def main():
 
     device = GlasgowHardwareDevice()
     target = GlasgowHardwareTarget(revision=device.revision)
-    reset, reset_addr = target.registers.add_rw(1, reset=1)
-    target.add_submodule(testbench := ResetInserter(reset)(
+    tb_rst, tb_rst_addr = target.registers.add_rw(1, reset=1)
+    target.add_submodule(testbench := ResetInserter(tb_rst)(
         HyperRAMSequencerTestbench(
-            out_fifo=target.fx2_crossbar.get_out_fifo(0, depth=1024, reset=reset),
-            in_fifo=target.fx2_crossbar.get_in_fifo(0, reset=reset))))
-    ram_rst_addr  = target.registers.add_existing_rw(testbench.ram_rst)
+            out_fifo=target.fx2_crossbar.get_out_fifo(0, reset=tb_rst),
+            in_fifo=target.fx2_crossbar.get_in_fifo(0, reset=tb_rst))))
+    ram_rst_addr  = target.registers.add_existing_rw(testbench.rst)
     cmd_addr_addr = target.registers.add_existing_rw(testbench.cmd_addr)
     latency_addr  = target.registers.add_existing_rw(testbench.latency)
     length_addr   = target.registers.add_existing_rw(testbench.length)
     trigger_addr  = target.registers.add_existing_rw(testbench.trigger)
-    await device.download_target(target.build_plan())
-
-    await device.write_register(ram_rst_addr, 1)
-    await device.write_register(ram_rst_addr, 0)
+    await device.download_target(target.build_plan(), reload=True)
 
     print("Running...")
     device.usb_handle.setConfiguration(1)
     device.usb_handle.claimInterface(0)
     device.usb_handle.setInterfaceAltSetting(0, 1)
+    await device.write_register(tb_rst_addr, 0)
 
-    async def prepare(addr_space, operation, latency, offset, length):
-        # reset testbench and clear FIFOs
-        await device.write_register(reset_addr, 1)
-        await device.write_register(trigger_addr, 0)
-        device.usb_handle.setInterfaceAltSetting(0, 1)
-        await device.write_register(reset_addr, 0)
+    await device.write_register(ram_rst_addr, 1)
+    await device.write_register(ram_rst_addr, 0)
 
+    async def prepare(addr_space, operation, latency, offset, length):
         await device.write_register(cmd_addr_addr, hyperram.CommandAddress.const({
             "operation": operation,
             "burst_type": hyperram.BurstType.Linear,
@@ -163,6 +158,7 @@ async def prepare(addr_space, operation, latency, offset, length):
         }).as_value().value, width=6)
         await device.write_register(latency_addr, latency)
         await device.write_register(length_addr, length, width=3)
+        await device.write_register(trigger_addr, 0)
         await device.write_register(trigger_addr, 1)
 
     def display(addr_space, operation, offset, data):