applet.interface.spi_controller: remove ad-hoc CS# inversion.

No longer needed as the same result can be achieved with `--pin-cs 0#`
instead of `--cs-active 1`.

software/glasgow/applet/display/pdi/__init__.py

@@ -403,7 +403,6 @@ def build(self, target, args):
             delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
             sck_idle=0,
             sck_edge="rising",
-            cs_active=0,
         )
 
         cog_power, self.__addr_cog_power = target.registers.add_rw(1)

software/glasgow/applet/interface/spi_controller/__init__.py

@@ -11,16 +11,15 @@
 
 
 class SPIControllerBus(Elaboratable):
-    def __init__(self, pads, sck_idle, sck_edge, cs_active):
+    def __init__(self, pads, sck_idle, sck_edge):
         self.pads = pads
         self.sck_idle = sck_idle
         self.sck_edge = sck_edge
-        self.cs_active = cs_active
 
         self.oe   = Signal(init=1)
 
         self.sck  = Signal(init=sck_idle)
-        self.cs   = Signal(init=not cs_active)
+        self.cs   = Signal()
         self.copi = Signal()
         self.cipo = Signal()
 
@@ -37,7 +36,7 @@ def elaborate(self, platform):
         if hasattr(self.pads, "cs_t"):
             m.d.comb += [
                 self.pads.cs_t.oe.eq(1),
-                self.pads.cs_t.o.eq(self.cs),
+                self.pads.cs_t.o.eq(~self.cs),
             ]
         if hasattr(self.pads, "copi_t"):
             m.d.comb += [
@@ -78,15 +77,14 @@ def elaborate(self, platform):
 
 class SPIControllerSubtarget(Elaboratable):
     def __init__(self, pads, out_fifo, in_fifo, period_cyc, delay_cyc,
-                 sck_idle, sck_edge, cs_active):
+                 sck_idle, sck_edge):
         self.pads = pads
         self.out_fifo = out_fifo
         self.in_fifo = in_fifo
         self.period_cyc = period_cyc
         self.delay_cyc = delay_cyc
-        self.cs_active = cs_active
 
-        self.bus = SPIControllerBus(pads, sck_idle, sck_edge, cs_active)
+        self.bus = SPIControllerBus(pads, sck_idle, sck_edge)
 
     def elaborate(self, platform):
         m = Module()
@@ -129,7 +127,7 @@ def elaborate(self, platform):
                     m.d.comb += self.out_fifo.r_en.eq(1)
                     m.d.sync += cmd.eq(self.out_fifo.r_data)
                     with m.If((self.out_fifo.r_data & CMD_MASK) == CMD_SELECT):
-                        m.d.sync += self.bus.cs.eq(self.out_fifo.r_data[0] ^ (not self.cs_active))
+                        m.d.sync += self.bus.cs.eq(self.out_fifo.r_data[0])
                     with m.Elif((self.out_fifo.r_data & CMD_MASK) == CMD_SYNC):
                         m.next = "SYNC"
                     with m.Else():
@@ -325,9 +323,6 @@ def add_build_arguments(cls, parser, access, omit_pins=False):
             "--sck-edge", metavar="EDGE", type=str, choices=["r", "rising", "f", "falling"],
             default="rising",
             help="latch data at clock edge EDGE (default: %(default)s)")
-        parser.add_argument(
-            "--cs-active", metavar="LEVEL", type=int, choices=[0, 1], default=0,
-            help="set active chip select level to LEVEL (default: %(default)s)")
 
     def build_subtarget(self, target, args, pins=__pins):
         iface = self.mux_interface
@@ -346,7 +341,6 @@ def build_subtarget(self, target, args, pins=__pins):
                                         clock_name="delay"),
             sck_idle=args.sck_idle,
             sck_edge=args.sck_edge,
-            cs_active=args.cs_active,
         )
 
     def build(self, target, args):

software/glasgow/applet/interface/spi_flashrom/__init__.py

@@ -183,7 +183,7 @@ def build_subtarget(self, target, args):
             hold_t = self.mux_interface.get_deprecated_pad(args.pin_hold)
         else:
             hold_t = None
-        return Memory25xSubtarget(subtarget, hold_t, args.cs_active)
+        return Memory25xSubtarget(subtarget, hold_t)
 
     async def run(self, device, args):
         spi_iface = await self.run_lower(SPIFlashromApplet, device, args)

software/glasgow/applet/memory/_25x/__init__.py

@@ -28,17 +28,16 @@ class Memory25xError(GlasgowAppletError):
 
 # This is also used in SPIFlashromApplet.
 class Memory25xSubtarget(Elaboratable):
-    def __init__(self, controller, hold_t, cs_active):
+    def __init__(self, controller, hold_t):
         self.controller = controller
         self.hold_t = hold_t
-        self.cs_active = cs_active
 
     def elaborate(self, platform):
         m = Module()
 
         m.submodules.controller = self.controller
 
-        m.d.comb += self.controller.bus.oe.eq(self.controller.bus.cs == self.cs_active)
+        m.d.comb += self.controller.bus.oe.eq(self.controller.bus.cs == 1)
 
         if self.hold_t is not None:
             m.d.comb += [
@@ -288,7 +287,7 @@ def build_subtarget(self, target, args):
             hold_t = self.mux_interface.get_deprecated_pad(args.pin_hold)
         else:
             hold_t = None
-        return Memory25xSubtarget(subtarget, hold_t, args.cs_active)
+        return Memory25xSubtarget(subtarget, hold_t)
 
     async def run(self, device, args):
         spi_iface = await self.run_lower(Memory25xApplet, device, args)

software/glasgow/applet/program/avr/spi/__init__.py

@@ -242,7 +242,6 @@ def build(self, target, args):
             delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
             sck_idle=0,
             sck_edge="rising",
-            cs_active=0,
         )
 
         dut_reset, self.__addr_dut_reset = target.registers.add_rw(1)

software/glasgow/applet/program/nrf24lx1/__init__.py

@@ -212,7 +212,6 @@ def build(self, target, args):
             delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
             sck_idle=0,
             sck_edge="rising",
-            cs_active=0,
         )
 
         return iface.add_subtarget(ProgramNRF24Lx1Subtarget(

software/glasgow/applet/radio/nrf24l01/__init__.py

@@ -230,7 +230,6 @@ def build(self, target, args):
             delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
             sck_idle=0,
             sck_edge="rising",
-            cs_active=0,
         )
 
         subtarget = RadioNRF24L01Subtarget(controller, pads.ce_t, dut_ce)