Refactor everything around IOStreamer, and QSPIController

There is a slight change in behavior, because the "bypass" feature has been removed,
CS clock pulses must now be at least 1 QPSI cycle long.

`sample_delay_half_clocks` is now runtime-selectable.

`max_sample_delay_half_clocks` is now a configuration option, for the IOStreamerTop to know how many resources to allocate.

`min_divisor` is now a configuration option, that if set to > 0, allows IOStreamer to optimize away some uneeded resources.

The bulk of the changes is about cutting up the functionality into smaller sub-components.

software/glasgow/applet/interface/qspi_controller/__init__.py

@@ -32,8 +32,10 @@ def elaborate(self, platform):
         m = Module()
 
         m.submodules.qspi = qspi = QSPIController(self._ports, use_ddr_buffers=True,
-                                                  sample_delay_half_clocks = self._sample_delay_half_clocks)
+                                                  max_sample_delay_half_clocks=self._sample_delay_half_clocks,
+                                                  min_divisor=self._divisor)
         m.d.comb += qspi.divisor.eq(self._divisor)
+        m.d.comb += qspi.sample_delay_half_clocks.eq(self._sample_delay_half_clocks)
 
         o_fifo  = self._out_fifo.stream
         i_fifo  = self._in_fifo.stream