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applet.interface.i2c_{initiator,target}: modify to use port groups #631

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Jul 23, 2024
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applet.interface.i2c_{initiator,target}: modify to use port groups #631

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14 changes: 6 additions & 8 deletions software/glasgow/applet/interface/i2c_initiator/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -16,16 +16,16 @@


class I2CInitiatorSubtarget(Elaboratable):
def __init__(self, pads, out_fifo, in_fifo, period_cyc):
self.pads = pads
def __init__(self, ports, out_fifo, in_fifo, period_cyc):
self.ports = ports
self.out_fifo = out_fifo
self.in_fifo = in_fifo
self.period_cyc = period_cyc

def elaborate(self, platform):
m = Module()

m.submodules.i2c_initiator = i2c_initiator = I2CInitiator(self.pads, self.period_cyc)
m.submodules.i2c_initiator = i2c_initiator = I2CInitiator(self.ports, self.period_cyc)

###

Expand Down Expand Up @@ -270,14 +270,12 @@ class I2CInitiatorApplet(GlasgowApplet):
"""
required_revision = "C0"

__pins = ("scl", "sda")

@classmethod
def add_build_arguments(cls, parser, access):
super().add_build_arguments(parser, access)

for pin in cls.__pins:
access.add_pin_argument(parser, pin, default=True)
access.add_pin_argument(parser, "scl", default=True)
access.add_pin_argument(parser, "sda", default=True)

parser.add_argument(
"-b", "--bit-rate", metavar="FREQ", type=int, default=100,
Expand All @@ -286,7 +284,7 @@ def add_build_arguments(cls, parser, access):
def build(self, target, args):
self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
iface.add_subtarget(I2CInitiatorSubtarget(
pads=iface.get_deprecated_pads(args, pins=self.__pins),
ports=iface.get_port_group(scl=args.pin_scl, sda=args.pin_sda),
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(),
period_cyc=math.ceil(target.sys_clk_freq / (args.bit_rate * 1000))
Expand Down
13 changes: 6 additions & 7 deletions software/glasgow/applet/interface/i2c_target/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -18,16 +18,16 @@ class Event(enum.IntEnum):


class I2CTargetSubtarget(Elaboratable):
def __init__(self, pads, out_fifo, in_fifo, address):
self.pads = pads
def __init__(self, ports, out_fifo, in_fifo, address):
self.ports = ports
self.out_fifo = out_fifo
self.in_fifo = in_fifo
self.address = address

def elaborate(self, platform):
m = Module()

m.submodules.i2c_target = i2c_target = I2CTarget(self.pads)
m.submodules.i2c_target = i2c_target = I2CTarget(self.ports)
m.d.comb += i2c_target.address.eq(self.address)

with m.FSM():
Expand Down Expand Up @@ -204,15 +204,14 @@ class I2CTargetApplet(GlasgowApplet):
"""
required_revision = "C0"

__pins = ("scl", "sda")
interface_cls = _DummyI2CTargetInterface

@classmethod
def add_build_arguments(cls, parser, access):
super().add_build_arguments(parser, access)

for pin in cls.__pins:
access.add_pin_argument(parser, pin, default=True)
access.add_pin_argument(parser, "scl", default=True)
access.add_pin_argument(parser, "sda", default=True)

def i2c_address(arg):
return int(arg, 0)
Expand All @@ -223,7 +222,7 @@ def i2c_address(arg):
def build(self, target, args):
self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
iface.add_subtarget(I2CTargetSubtarget(
pads=iface.get_deprecated_pads(args, pins=self.__pins),
ports=iface.get_port_group(scl=args.pin_scl, sda=args.pin_sda),
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(),
address=args.address,
Expand Down
21 changes: 9 additions & 12 deletions software/glasgow/gateware/i2c.py
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,7 @@ class I2CBus(Elaboratable):
Decodes bus conditions (start, stop, sample and setup) and provides synchronization.
"""
def __init__(self, pads):
self.scl_t = pads.scl_t if hasattr(pads, "scl_t") else io.Buffer("io", pads.scl)
self.sda_t = pads.sda_t if hasattr(pads, "sda_t") else io.Buffer("io", pads.sda)
self.pads = pads

self.scl_i = Signal()
self.scl_o = Signal(init=1)
Expand All @@ -31,19 +30,17 @@ def __init__(self, pads):
def elaborate(self, platform):
m = Module()

if isinstance(self.scl_t, io.Buffer):
m.submodules.io_scl = self.scl_t
if isinstance(self.sda_t, io.Buffer):
m.submodules.io_sda = self.sda_t
m.submodules.io_scl = scl_t = io.Buffer("io", self.pads.scl)
m.submodules.io_sda = sda_t = io.Buffer("io", self.pads.sda)

scl_r = Signal(init=1)
sda_r = Signal(init=1)

m.d.comb += [
self.scl_t.o.eq(0),
self.scl_t.oe.eq(~self.scl_o),
self.sda_t.o.eq(0),
self.sda_t.oe.eq(~self.sda_o),
scl_t.o.eq(0),
scl_t.oe.eq(~self.scl_o),
sda_t.o.eq(0),
sda_t.oe.eq(~self.sda_o),

self.sample.eq(~scl_r & self.scl_i),
self.setup.eq(scl_r & ~self.scl_i),
Expand All @@ -55,8 +52,8 @@ def elaborate(self, platform):
sda_r.eq(self.sda_i),
]
m.submodules += [
FFSynchronizer(self.scl_t.i, self.scl_i, init=1),
FFSynchronizer(self.sda_t.i, self.sda_i, init=1),
FFSynchronizer(scl_t.i, self.scl_i, init=1),
FFSynchronizer(sda_t.i, self.sda_i, init=1),
]

return m
Expand Down
12 changes: 6 additions & 6 deletions software/tests/gateware/test_i2c.py
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Original file line number Diff line number Diff line change
Expand Up @@ -8,12 +8,12 @@

class I2CTestbench(Elaboratable):
def __init__(self):
self.scl_t = io.Buffer.Signature(direction="io", width=1).create()
self.sda_t = io.Buffer.Signature(direction="io", width=1).create()
self.scl = io.SimulationPort("io", 1)
self.sda = io.SimulationPort("io", 1)

self.scl_i = self.scl_t.i
self.scl_i = self.scl.i
self.scl_o = Signal(init=1)
self.sda_i = self.sda_t.i
self.sda_i = self.sda.i
self.sda_o = Signal(init=1)

self.period_cyc = 16
Expand All @@ -24,8 +24,8 @@ def elaborate(self, platform):
m.submodules.dut = self.dut

m.d.comb += [
self.scl_t.i.eq((self.scl_t.o | ~self.scl_t.oe) & self.scl_o),
self.sda_t.i.eq((self.sda_t.o | ~self.sda_t.oe) & self.sda_o),
self.scl.i.eq((self.scl.o | ~self.scl.oe) & self.scl_o),
self.sda.i.eq((self.sda.o | ~self.sda.oe) & self.sda_o),
]

return m
Expand Down
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