First commit adding vhdl files

KelvinThomasYB17 · Oct 6, 2024 · 5e83b8f · 5e83b8f
commit 5e83b8f
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diff --git a/bintobcd.vhd b/bintobcd.vhd
@@ -0,0 +1,87 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bintobcd is
+  port(signal a  :  in std_logic_vector(5 downto 0);
+	   signal f  : out std_logic_vector(7 downto 0)) ;
+end bintobcd;
+
+architecture structural of bintobcd is
+
+  constant DONT_CARE : std_logic_vector(7 downto 0):= (others => '-');
+
+  signal a_int : std_logic_vector(7 downto 0);
+
+begin
+
+  a_int <= "00" & a;
+
+  with a_int select
+    f <= x"00" when x"00",
+         x"01" when x"01",
+         x"02" when x"02",
+         x"03" when x"03",
+         x"04" when x"04",
+         x"05" when x"05",
+         x"06" when x"06",
+         x"07" when x"07",
+         x"08" when x"08",
+         x"09" when x"09",			 
+         x"10" when x"0A",
+         x"11" when x"0b",
+         x"12" when x"0C",
+         x"13" when x"0d",
+         x"14" when x"0E",
+         x"15" when x"0F",
+         x"16" when x"10",
+         x"17" when x"11",		 
+         x"18" when x"12",
+         x"19" when x"13",
+         x"20" when x"14",	
+         x"21" when x"15",
+         x"22" when x"16",		 
+         x"23" when x"17",
+         x"24" when x"18",
+         x"25" when x"19",	
+         x"26" when x"1A",
+         x"27" when x"1b",		 
+         x"28" when x"1C",
+         x"29" when x"1d",
+         x"30" when x"1E",	
+         x"31" when x"1F",	 
+         x"32" when x"20",
+         x"33" when x"21",
+         x"34" when x"22",
+         x"35" when x"23",
+         x"36" when x"24",
+         x"37" when x"25",
+         x"38" when x"26",
+         x"39" when x"27",
+         x"40" when x"28",
+         x"41" when x"29",			 
+         x"42" when x"2A",
+         x"43" when x"2b",
+         x"44" when x"2C",
+         x"45" when x"2d",
+         x"46" when x"2E",
+         x"47" when x"2F",
+         x"48" when x"30",
+         x"49" when x"31",		 
+         x"50" when x"32",
+         x"51" when x"33",
+         x"52" when x"34",	
+         x"53" when x"35",
+         x"54" when x"36",		 
+         x"55" when x"37",
+         x"56" when x"38",
+         x"57" when x"39",	
+         x"58" when x"3A",
+         x"59" when x"3b",		 
+         x"60" when x"3C",
+         x"61" when x"3D",
+         x"62" when x"3E",	
+         x"63" when x"3F",
+         DONT_CARE when others;
+
+end structural;
diff --git a/db/.cmp.kpt b/db/.cmp.kpt
diff --git a/db/prev_cmp_traffic_light_system.qmsg b/db/prev_cmp_traffic_light_system.qmsg
diff --git a/db/traffic_light_system.db_info b/db/traffic_light_system.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+Version_Index = 486699264
+Creation_Time = Sun Apr 14 00:21:48 2024
diff --git a/db/traffic_light_system.pplq.rdb b/db/traffic_light_system.pplq.rdb
diff --git a/db/traffic_light_system.sld_design_entry.sci b/db/traffic_light_system.sld_design_entry.sci
diff --git a/db/traffic_light_system_partition_pins.json b/db/traffic_light_system_partition_pins.json
@@ -0,0 +1,193 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "red",
+					"strict" : false
+				},
+				{
+					"name" : "green",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg[0]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg[1]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg[2]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg[3]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg[4]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg[5]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg[6]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg[0]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg[1]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg[2]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg[3]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg[4]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg[5]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg[6]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_red[0]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_red[1]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_red[2]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_red[3]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_red[4]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_red[5]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_red[6]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_red[0]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_red[1]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_red[2]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_red[3]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_red[4]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_red[5]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_red[6]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_green[0]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_green[1]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_green[2]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_green[3]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_green[4]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_green[5]",
+					"strict" : false
+				},
+				{
+					"name" : "u_7seg_green[6]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_green[0]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_green[1]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_green[2]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_green[3]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_green[4]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_green[5]",
+					"strict" : false
+				},
+				{
+					"name" : "d_7seg_green[6]",
+					"strict" : false
+				},
+				{
+					"name" : "clk",
+					"strict" : false
+				},
+				{
+					"name" : "reset_n",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
diff --git a/divisor_freq.vhd b/divisor_freq.vhd
@@ -0,0 +1,46 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity divisor_freq is
+  generic (N         : natural := 50000000;        
+           BUS_WIDTH : natural := 26);
+  port (signal reset_n :  in std_logic;
+        signal clk     :  in std_logic;
+        signal clk_o   : out std_logic);
+end divisor_freq;
+
+architecture structural of divisor_freq is
+
+  signal clk_o_reg  : std_logic;
+  signal clk_o_next : std_logic;
+  signal q_reg      : unsigned(BUS_WIDTH-1 downto 0);
+  signal q_next     : unsigned(BUS_WIDTH-1 downto 0);
+
+begin
+
+  seq: process(reset_n,clk)
+  begin
+    if (reset_n = '0') then
+	  clk_o_reg <= '0';
+      q_reg <= (others => '0');
+    elsif rising_edge(clk) then
+	  clk_o_reg <= clk_o_next;
+      q_reg <= q_next;  
+    end if;
+  end process seq;
+
+  comb: process(q_reg)
+  begin
+	if (q_reg = (N-1)) then
+	  clk_o_next <= '1'; 
+	  q_next <= (others => '0');
+	else
+      clk_o_next <= '0'; 	  
+	  q_next <= q_reg + 1;
+	end if; 	
+  end process comb;
+
+  clk_o <= clk_o_reg; 
+
+end structural;
diff --git a/divisor_freq.vhd.bak b/divisor_freq.vhd.bak
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------------
+-- Archivo: divisor_freq.vhd
+----------------------------------------------------------------------------------------
+-- Autor:     Mg. Ing. Mario Raffo
+-- Email:     [email protected]
+-- Entidad:   Pontificia Universidad Católica del Perú (PUCP)
+-- Facultad:  Estudios Generales Ciencias (EE.GG.CC) 
+-- Curso:     1IEE04 - Diseño Digital
+----------------------------------------------------------------------------------------
+-- Historia de Versión:
+-- Versión 1.0 (01/10/2017) - Mario Raffo 
+----------------------------------------------------------------------------------------
+-- Descripción:
+-- Circuito basado en un contador mod N
+----------------------------------------------------------------------------------------
+
+Library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity divisor_freq is
+  generic (n     : natural := 10;        
+           width : natural := 4);
+  port (signal reset_n :  in std_logic;
+        signal clk     :  in std_logic;
+        signal clk_o   : out std_logic);
+end divisor_freq;
+
+architecture structural of divisor_freq is
+
+  signal clk_o_reg  : std_logic;
+  signal clk_o_next : std_logic;
+  signal q_reg      : unsigned(width-1 downto 0);
+  signal q_next     : unsigned(width-1 downto 0);
+
+begin
+
+  seq: process(reset_n,clk)
+  begin
+    if (reset_n = '0') then
+	  clk_o_reg <= '0';
+      q_reg <= (others => '0');
+    elsif rising_edge(clk) then
+	  clk_o_reg <= clk_o_next;
+      q_reg <= q_next;  
+    end if;
+  end process seq;
+
+  comb: process(q_reg)
+  begin
+	if (q_reg = (n-1)) then
+	  clk_o_next <= '1'; 
+	  q_next <= (others => '0');
+	else
+      clk_o_next <= '0'; 	  
+	  q_next <= q_reg + 1;
+	end if; 	
+  end process comb;
+
+  clk_o <= clk_o_reg; 
+
+end structural;