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  1. Face3D-Pytorch Face3D-Pytorch Public

    Forked from gokulsg/Face3D-Pytorch

    3D Face Recognition, implemented with PyTorch

    Jupyter Notebook

  2. ofdm ofdm Public

    Forked from freecores/ofdm

    OFDM modem

    VHDL

  3. ip-cores ip-cores Public

    Forked from fabriziotappero/ip-cores

    A huge collection of VHDL/Verilog open-source IP cores scraped from the web

  4. Phase-Locked-Loop Phase-Locked-Loop Public

    Forked from Electro-SPY/Phase-Locked-Loop

    We are designing a CP-PLL. The following link provides resources about PLL design.

  5. Basic-SIMD-Processor-Verilog-Tutorial Basic-SIMD-Processor-Verilog-Tutorial Public

    Forked from zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

    Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

    Verilog

  6. turbo-3gpp-matlab turbo-3gpp-matlab Public

    Forked from robmaunder/turbo-3gpp-matlab

    Matlab simulations of the encoder and decoder for the LTE turbo code from 3GPP Release 15

    MATLAB