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Cologne Chip GateMate CCGM1A1 FPGA symbol is created #2578

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@ak-fau ak-fau commented Mar 27, 2020

Cologne Chip GateMate CCGM1A1 FPGA symbol is created

A separate PR is created for the kicad-footprints library to add BGA-320 footprint
(18x18 matrix with 4 balls removed), KiCad/kicad-footprints#2183.

Datasheet

Schematic page with all parts of the CCGM1A1 symbol

KLC violations:
S3.1 for unit 8 -- to make the unit itself symmetrical
S4.2 too many ground and power pins to place on top/bottom of a unit
S5.1 corresponding footprint is submitted with pull request KiCad/kicad-footprints#2183


All contributions to the kicad library must follow the KiCad library convention

Thanks for creating a pull request to contribute to the KiCad libraries! To speed up integration of your PR, please check the following items:

  • Provide a URL to a datasheet for the symbol(s) you are contributing
  • An example screenshot image is very helpful
  • Ensure that the associated footprints match the official footprint library
    • A new fitting footprint must be submitted if the library does not yet contain one.
  • If there are matching footprint PRs, provide link(s) as appropriate
  • Check the output of the Travis automated check scripts - fix any errors as required
  • Give a reason behind any intentional library convention rule violation.

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CLAassistant commented Mar 27, 2020

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@myfreescalewebpage myfreescalewebpage added Addition Adds new symbols to library Pending reviewer A pull request waiting for a reviewer labels Mar 27, 2020
@ak-fau ak-fau force-pushed the ccgm branch 5 times, most recently from a4e0a58 to b62a598 Compare March 29, 2020 13:01
@ak-fau ak-fau marked this pull request as ready for review March 29, 2020 13:34
@myfreescalewebpage myfreescalewebpage self-assigned this Apr 26, 2020
@myfreescalewebpage myfreescalewebpage removed the Pending reviewer A pull request waiting for a reviewer label Apr 26, 2020
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Closing/opening to refresh the Travis test.

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myfreescalewebpage commented Apr 26, 2020

Hi @ak-fau , thanks for contributing,

A few comments I have during my review:

  • This is a new library, you should add it to "sym-lib-table" file
  • Description should be terminated with the package name: Cologne Chip GateMate FPGA, BGA-320
  • The footprint name will maybe need to be changed (will see what the footprint experts say), anyway at the moment the footprint filter should be BGA*15.0x15.0mm*Layout18x18*P0.8mm*
  • Pin length should be 150mil

Unit A:

  • Pin style should be line

Unit G:

  • VDD pin should go on the corresponding bank: VDD_N1/VDD_N2 on unit C, VDD_E1/VDD_E2 on unit D, etc. They should go on the top, we accept to have the pins with the same name stacked.

Units H and I:

  • To be grouped on the same unit
  • VDD pins all stacked on the top
  • GND pins all stacked on the bottom
  • The other VDD on the top

I attach the excel sheet I used for the review (extract of datasheet):
pinout.xlsx

Cheers,
Joel

@myfreescalewebpage myfreescalewebpage added the Pending footprint Pending footprint acceptance before merging label Apr 26, 2020
ak-fau added 2 commits May 12, 2020 00:23
Everything should be correct now, with possible exception of a footprint name --
still waiting for a review comments on a separate PR with the footprint.
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ak-fau commented May 11, 2020

Hello Joel, thank you for your review and comments.

  • This is a new library, you should add it to "sym-lib-table" file
  • Description should be terminated with the package name: Cologne Chip GateMate FPGA, BGA-320
  • The footprint name will maybe need to be changed (will see what the footprint experts say), anyway at the moment the footprint filter should be BGA*15.0x15.0mm*Layout18x18*P0.8mm*

Understood, a PR with the footprint is still pending review.

  • Pin length should be 150mil

Unit A:

  • Pin style should be line

Unit G:

  • VDD pin should go on the corresponding bank: VDD_N1/VDD_N2 on unit C, VDD_E1/VDD_E2 on unit D, etc. They should go on the top, we accept to have the pins with the same name stacked.

Units H and I:

  • To be grouped on the same unit

It is now unit G

  • VDD pins all stacked on the top
  • GND pins all stacked on the bottom
  • The other VDD on the top

I attach the excel sheet I used for the review (extract of datasheet):
pinout.xlsx

An error in the data sheet with pin J1 (IO_W2_B3) seems to
be a rather obvious typo, nevertheless, thank you for pointing it out.
I'll go ahead and report it to Cologne Chip.

Cheers,
Joel

Best regards,

Anton

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Thanks for the fixes! I think now just need to wait the footprint.

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ghost commented Sep 9, 2020

Unfortunately there will be more changes. But it has to wait for new documentation from CologneChip to become available.
See pointhi/kicad-footprint-generator#611 (comment)

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@cp-aquila thanks for the info. This is exactly why we always wait for the footprint to be integrated before merging the symbol, because the definition of the footprint may change. In this case of course the symbol PR should be updated.
Joel

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3 participants