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Add IS43LQ32256A-062BLI and alias IS43LQ32256AL-062BLI. #2951

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merged 8 commits into from
Sep 20, 2020

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mhrdmhrd
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@mhrdmhrd mhrdmhrd commented Aug 30, 2020

Added IS43LQ32256A-062BLI (LPDDR4 SDRAM) and alias IS43LQ32256AL-062BLI (LPDDR4X SDRAM).
Both of the two components shared the same symbol, footprint, and package dimensions. Only the difference is the voltage of VDDQ.

Datesheet: http://www.issi.com/WW/pdf/43-46LQ32256A-AL.pdf

Unit A contains function pins of channel A:
image

Unit B contains function pins of channel B:
image

Unit C mainly contains power, ground, an DNU (do not use) pins of channel A:
image

Unit D mainly contains power, ground, an DNU (do not use) pins of channel B:
image


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All contributions to the kicad library must follow the KiCad library convention

Thanks for creating a pull request to contribute to the KiCad libraries! To speed up integration of your PR, please check the following items:

  • Provide a URL to a datasheet for the symbol(s) you are contributing
  • Provide a screenshot of the symbol(s) from the symbol editor with the pin types visible
  • Ensure that the associated footprints match the official footprint library
    • A new fitting footprint must be submitted if the library does not yet contain one.
  • If there are matching footprint PRs, provide link(s) as appropriate
    Footprint PR: Added BGA-200 pitch 0.80x0.65 mm for LPDDR4/4X SDRAM. kicad-footprints#2437
    3D model PR: Added 3D model for IS43LQ32256A-062BLI. kicad-packages3D#723
  • Check the output of the Travis automated check scripts - fix any errors as required
  • Give a reason behind any intentional library convention rule violation.
    It has S4.2 violation. I put power and ground pins separate unit C and D because the devices have too many power and ground pins. If I obeyed the rule, the width of unit A and B become too wide. It makes the schematic a bit ugly.

Note 1: Some NC pins are next to function pins like CS, CKE, ZQ because future products may use the NCs as the 2nd and 3rd one each. The pin arrangement will make easier to enhance the variation of LPDDR4/4X symbol library.
(The international standard of LPDDR4/4X defines up to three pairs of CS/CKE/ZQ.)

Note 2: Why I put DNU pins on Unit C and D was that some LPDDR4/4X vendors allow the pins to connect VSS, so it might be convenient to be there. ISSI does not support such usage, but it can be useful if someone reuse this symbol for other vendors' devices.


Be patient, we maintainers are volunteers with limited time and need to check your contribution against the datasheet. You can speed up the process by providing all the necessary information (see above). And you can speed up the process even more by providing additional info like the screenshot of the symbol editor pin table (or for high pin counts converted to csv) sorted in the same way as the pin table in the datasheet and a direct link to the datasheet page that contains the pin table.

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CLAassistant commented Aug 30, 2020

CLA assistant check
All committers have signed the CLA.

@mhrdmhrd
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Thank you for reviewing my PR.
There is S4.2 violation because I put power and ground pins on separate units C and D because the device has too many power and ground pins. If I obeyed the rule, the width of unit A and B become too wide. It makes schematics a bit ugly.

@myfreescalewebpage myfreescalewebpage self-assigned this Sep 5, 2020
@myfreescalewebpage myfreescalewebpage removed the Pending reviewer A pull request waiting for a reviewer label Sep 5, 2020
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myfreescalewebpage commented Sep 5, 2020

Hello @mhrdmhrd thanks for this contribution

Partial review:

  • Pin length should be 200mil for this symbol (4 characters for pin name, 50mil per character)
  • You should stack VSS together, and VDD1 together and VDD2 together and VDDQ together. You can do it on a separated unit which will be very small. Moreover Positive power pin should go to the top, and negative to the bottom
  • NC pins go on the border outline of the symbol
  • Size of the unit 1 and unit B can be reduce, you have plenty of space lost at the top and the bottom

Joel

Stacked VDD1/VDD2/VDDQ/VSS together each, and pins behind were set as invisible and passive.
Moved VDD1/VDD2/VDDQ/VSS to unit A/B, and removed unit C and D.
NC pins went on the border outline of the symbol.
Reduced the size of units as much as possible.
@mhrdmhrd
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mhrdmhrd commented Sep 6, 2020

Hello Joel,

Thank you for taking time to review my PR.
I have corrected this symbol. Unit C and D are removed because stacking power pins reduced area so the pins could move to unit A and B.

  • Pin length should be 200mil for this symbol (4 characters for pin name, 50mil per character)
  • You should stack VSS together, and VDD1 together and VDD2 together and VDDQ together. You can do it on a separated unit which will be very small. Moreover Positive power pin should go to the top, and negative to the bottom
  • NC pins go on the border outline of the symbol
  • Size of the unit 1 and unit B can be reduce, you have plenty of space lost at the top and the bottom

Unit A:
image

Unit B:
image

Thank you!
Minori

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myfreescalewebpage commented Sep 6, 2020

Thanks, great job! Continue the review now:

  • Package at the end of the descriptions should be "BGA-200"
  • Name of H4 is "CS0_A" and name of R4 is "CS0_B"
  • P4 is CKE0_B and P5 is NC (you have cross the pins!)

Joel

@myfreescalewebpage myfreescalewebpage added the Pending footprint Pending footprint acceptance before merging label Sep 6, 2020
- Package info at the end of the desctiptions. (BGA 200-ball -> BGA-200)
- CS_A/B -> CS0_A/B
- Pin P4: NC -> CKE0_B
- Pin P5: CKE0_B -> NC
@mhrdmhrd
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mhrdmhrd commented Sep 6, 2020

Thank you for your checking.
I have corrected the mistakes and checked if the all pin numbers and names corresponding the definitions in the datasheet again.

  • Package at the end of the descriptions should be "BGA-200"
  • Name of H4 is "CS0_A" and name of R4 is "CS0_B"
  • P4 is CKE0_B and P5 is NC (you have cross the pins!)

Unit A:
image

Unit B:
image

Thank you!
Minori

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BGA-200 in the description of the alias too please ;)

@mhrdmhrd
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mhrdmhrd commented Sep 6, 2020

I have also corrected the alias. Sorry for the mistake.
I completely forgot that aliases have the different description...

@myfreescalewebpage
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No problem, thanks for the update. Just need to wait the footprint now.

@mhrdmhrd
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Just let you know that the footprint PR has been merged.
I'm not in a rush. When you get some time, can you merge this PR.

@myfreescalewebpage
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Sure :)

@myfreescalewebpage
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Closing/opening to refresh the Travis test.

@myfreescalewebpage myfreescalewebpage removed the Pending footprint Pending footprint acceptance before merging label Sep 20, 2020
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Thanks, no more comment, merging.

@myfreescalewebpage myfreescalewebpage merged commit b2dfb94 into KiCad:master Sep 20, 2020
@mhrdmhrd mhrdmhrd deleted the feature/IS43LQ32256A-062BLI branch September 21, 2020 15:27
@mhrdmhrd
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Thank you so much for your time and all the effort!

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