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Adicionando macros de sintese para FPGAs xilinx #8

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Adicionando macros de sintese para FPGAs xilinx

Adicionando macros de sintese para FPGAs xilinx #8

Triggered via push November 28, 2024 12:15
@JN513JN513
pushed 01e3096
main
Status Success
Total duration 15s
Artifacts –

blue.yml

on: push
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