update some tests to run with dft

M0stafaRady · Mar 14, 2024 · b4b0ca0 · b4b0ca0
1 parent 50efdc9
commit b4b0ca0
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Showing 42 changed files with 220 additions and 180 deletions.
diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_i.c b/verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_i.c
@@ -1,6 +1,7 @@
 #include <firmware_apis.h>
 
 #include <bitbang.h>
+#include <dft.h>
 
 void main(){
     enable_debug();
@@ -27,7 +28,7 @@ void main(){
 
 void wait_over_input_l(unsigned int start_code, unsigned int exp_val){
     set_debug_reg1(start_code); // configuration done wait environment to send exp_val to reg_mprj_datal
-    GPIOs_waitLow(exp_val);
+    GPIOs_waitLow_dft(exp_val);
     set_debug_reg2(GPIOs_readLow());
 
 }

diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_spi_i.c b/verilog/dv/cocotb/all_tests/bitbang/bitbang_spi_i.c
@@ -1,4 +1,5 @@
 #include <firmware_apis.h>
+#include <dft.h>
 
 
 
@@ -34,7 +35,7 @@ void main()
 
 void wait_over_input_l(unsigned int start_code, unsigned int exp_val){
     set_debug_reg1(start_code); // configuration done wait environment to send exp_val to reg_mprj_datal
-    GPIOs_waitLow(exp_val);
+    GPIOs_waitLow_dft(exp_val);
     set_debug_reg2(GPIOs_readLow());
 
 }

diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests.py
@@ -3,7 +3,7 @@
 import cocotb.log
 from caravel_cocotb.interfaces.cpu import RiskV 
 from caravel_cocotb.interfaces.defsParser import Regs
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 
 from caravel_cocotb.caravel_interfaces import GPIO_MODE
@@ -14,7 +14,7 @@
 @cocotb.test()
 @report_test
 async def bitbang_no_cpu_all_o(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=119373)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=119373)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     await cpu.drive_data2address(
@@ -217,7 +217,7 @@ async def bitbang_no_cpu_all_o(dut):
 @cocotb.test()
 @report_test
 async def bitbang_no_cpu_all_i(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=117351)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=117351)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     await cpu.drive_data2address(

diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests_cpu.py
@@ -2,7 +2,7 @@
 from cocotb.triggers import ClockCycles
 import cocotb.log
 from caravel_cocotb.interfaces.defsParser import Regs
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 from caravel_cocotb.caravel_interfaces import GPIO_MODE
 from all_tests.gpio.gpio_seq import gpio_all_o_seq
@@ -17,15 +17,15 @@
 @cocotb.test()
 @report_test
 async def bitbang_cpu_all_o(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=5004275)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=5004275)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_o_seq(dut, caravelEnv, debug_regs)
 
 
 @cocotb.test()
 @report_test
 async def bitbang_cpu_all_i(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=3311179)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=3311179)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_i_seq(dut, caravelEnv, debug_regs)
 
@@ -36,7 +36,7 @@ async def bitbang_cpu_all_i(dut):
 @cocotb.test()
 @report_test
 async def bitbang_spi_o(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=2008592)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=2008592)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_o_seq(dut, caravelEnv, debug_regs, bitbang_spi_o_configure)
 
@@ -47,7 +47,7 @@ async def bitbang_spi_o(dut):
 @cocotb.test()
 @report_test
 async def bitbang_spi_i(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=316406)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=316406)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_i_seq(dut, caravelEnv, debug_regs, bitbang_spi_i_configure)
 

diff --git a/verilog/dv/cocotb/all_tests/check_defaults/check_defaults.py b/verilog/dv/cocotb/all_tests/check_defaults/check_defaults.py
@@ -4,14 +4,14 @@
 from cocotb.queue import Queue
 from cocotb.triggers import Combine
 from user_design import configure_userdesign
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 from user_monitor_driver import UserPins
 
 @cocotb.test()
 @report_test
 async def check_defaults(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=1145328)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=1145328)
     debug_regs = await configure_userdesign(caravelEnv)
     user_pins = UserPins(caravelEnv)
     gpio_test = GPIOsDefaultTests(caravelEnv, user_pins, debug_regs)

diff --git a/verilog/dv/cocotb/all_tests/common/common.py b/verilog/dv/cocotb/all_tests/common/common.py
@@ -0,0 +1,31 @@
+import cocotb
+from caravel_cocotb.interfaces.common_functions.test_functions import read_config_file, test_configure
+
+
+from cocotb.triggers import ClockCycles
+
+async def test_configure_dft(dut: cocotb.handle.SimHandle,
+    timeout_cycles=1000000,
+    clk=read_config_file()['clock'],
+    timeout_precision=0.2,
+    num_error=int(read_config_file()['max_err']),
+    start_up=True):
+    disable_jtag_testmode(dut)
+    caravelEnv = await test_configure(dut, timeout_cycles, clk, timeout_precision, num_error, start_up=False)
+    # manual start udisable_jtag_testmodep
+    await caravelEnv.power_up()
+    await caravelEnv.disable_csb()  # no need for this anymore as default for gpio3 is now pullup
+    await caravelEnv.reset()
+    await caravelEnv.disable_bins(ignore_bins=[3, 4, 28, 29, 30, 31])
+    await ClockCycles(caravelEnv.clk, 10)
+    return caravelEnv
+
+def disable_jtag_testmode(dut):
+    dut.gpio28_en.value = 1
+    dut.gpio28.value = 0
+    dut.gpio29_en.value = 1
+    dut.gpio29.value = 0
+    dut.gpio30_en.value = 1
+    dut.gpio30.value = 0
+    dut.gpio31_en.value = 1
+    dut.gpio31.value = 0
diff --git a/verilog/dv/cocotb/all_tests/cpu/cpu_reset.py b/verilog/dv/cocotb/all_tests/cpu/cpu_reset.py
@@ -1,7 +1,7 @@
 import cocotb
 from cocotb.triggers import ClockCycles
 import cocotb.log
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 from caravel_cocotb.caravel_interfaces import SPI
 from user_design import configure_userdesign
@@ -10,7 +10,7 @@
 @cocotb.test()
 @report_test
 async def cpu_reset(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=121372)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=121372)
     spi_master = SPI(caravelEnv)
     debug_regs = await configure_userdesign(caravelEnv)
     cocotb.log.info("[TEST] Start cpu_reset test")

diff --git a/verilog/dv/cocotb/all_tests/cpu/cpu_stress.py b/verilog/dv/cocotb/all_tests/cpu/cpu_stress.py
@@ -1,7 +1,7 @@
 import cocotb
 from cocotb.triggers import ClockCycles
 import cocotb.log
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 
 from user_design import configure_userdesign
@@ -11,7 +11,7 @@
 @cocotb.test()
 @report_test
 async def cpu_stress(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=1747660)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=1747660)
     debug_regs = await configure_userdesign(caravelEnv)
     cocotb.log.info("[TEST] Start CPU stress test")
     pass_list = (0x1B, 0x2B, 0x3B, 0x4B, 0x5B)

diff --git a/verilog/dv/cocotb/all_tests/debug/debug.py b/verilog/dv/cocotb/all_tests/debug/debug.py
@@ -2,7 +2,7 @@
 import cocotb
 from cocotb.triggers import Timer
 import cocotb.log
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 from user_design import configure_userdesign
 
@@ -12,7 +12,7 @@
 @cocotb.test()
 @report_test
 async def debug(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=81933)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=81933)
     debug_regs = await configure_userdesign(caravelEnv)
     # calculate bit time
     clock = caravelEnv.get_clock_obj()

diff --git a/verilog/dv/cocotb/all_tests/debug/debug_swd.py b/verilog/dv/cocotb/all_tests/debug/debug_swd.py
@@ -2,7 +2,7 @@
 import cocotb
 from cocotb.triggers import FallingEdge, RisingEdge, ClockCycles, Timer
 import cocotb.log
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 from collections import namedtuple
 from cocotb.handle import Force
@@ -23,7 +23,7 @@
 async def debug_swd(dut):
     dut._id(f"gpio{35}", False).value = 0
     dut._id(f"gpio{35}_en", False).value = Force(1)
-    caravelEnv = await test_configure(dut, timeout_cycles=1131011)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=1131011)
     debug_regs = await configure_userdesign(caravelEnv)
     caravelEnv.drive_gpio_in(0, 1)
     caravelEnv.drive_gpio_in(35, 0)

diff --git a/verilog/dv/cocotb/all_tests/flash_clk/flash_clk.py b/verilog/dv/cocotb/all_tests/flash_clk/flash_clk.py
@@ -1,11 +1,11 @@
 import cocotb
 from cocotb.triggers import Edge, RisingEdge, FallingEdge, ClockCycles
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 @cocotb.test()
 @report_test
 async def flash_clk(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=1999191)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=1999191)
     clock = caravelEnv.get_clock_period()
     csb = dut.flash_csb_tb
     clk = dut.flash_clk_tb

diff --git a/verilog/dv/cocotb/all_tests/gpio/gpio.py b/verilog/dv/cocotb/all_tests/gpio/gpio.py
@@ -1,5 +1,5 @@
 import cocotb
-from caravel_cocotb.caravel_interfaces import test_configure
+from all_tests.common.common import test_configure_dft
 from caravel_cocotb.caravel_interfaces import report_test
 from all_tests.gpio.gpio_seq import gpio_all_o_seq
 from all_tests.gpio.gpio_seq import gpio_all_i_seq
@@ -11,30 +11,30 @@
 @cocotb.test()
 @report_test
 async def gpio_all_o(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=1999191)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=1999191)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_o_seq(dut, caravelEnv, debug_regs)
 
 
 @cocotb.test()
 @report_test
 async def gpio_all_i(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=295677)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=22014)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_i_seq(dut, caravelEnv, debug_regs)
 
 
 @cocotb.test()
 @report_test
 async def gpio_all_i_pu(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=69978)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=16815)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_i_pu_seq(dut, caravelEnv, debug_regs)
 
 
 @cocotb.test()
 @report_test
 async def gpio_all_i_pd(dut):
-    caravelEnv = await test_configure(dut, timeout_cycles=69978)
+    caravelEnv = await test_configure_dft(dut, timeout_cycles=69978)
     debug_regs = await configure_userdesign(caravelEnv)
     await gpio_all_i_pd_seq(dut, caravelEnv, debug_regs)
diff --git a/verilog/dv/cocotb/all_tests/gpio/gpio_all_i.c b/verilog/dv/cocotb/all_tests/gpio/gpio_all_i.c
@@ -1,5 +1,5 @@
 #include <firmware_apis.h>
-
+#include <dft.h>
 void main(){
     enable_debug();
     enableHkSpi(0);
@@ -26,7 +26,7 @@ void main(){
 
 void wait_over_input_l(unsigned int start_code, unsigned int exp_val){
     set_debug_reg1(start_code); // configuration done wait environment to send exp_val to reg_mprj_datal
-    GPIOs_waitLow(exp_val);
+    GPIOs_waitLow_dft(exp_val);
     set_debug_reg2(GPIOs_readLow());
 
 }