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This fixes a lockup seen on the MEGA65, and could be related to issue #8
MJoergen · Jul 11, 2024 · f839818 · f839818
1 parent ce07e8a
commit f839818
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Showing 8 changed files with 130 additions and 172 deletions.
diff --git a/src/Example_Design/top-R4.xdc b/src/Example_Design/top-R4.xdc
@@ -80,6 +80,10 @@ set_max_delay 2 -datapath_only -from [get_cells i_core/i_hyperram/hyperram_rx_in
 # Prevent insertion of extra BUFG
 set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_pins i_core/i_hyperram/hyperram_rx_inst/delay_rwds_inst/DATAOUT]]
 
+# Receive FIFO: There is a CDC in the LUTRAM.
+# There is approx 1.1 ns Clock->Data delay for the LUTRAM itself, plus 0.5 ns routing delay to the capture flip-flop.
+set_max_delay 2 -datapath_only -from [get_clocks hr_rwds] -to [get_clocks hr_clk]
+
 ################################################################################
 # HyperRAM timing (correct for IS66WVH8M8DBLL-100B1LI)
 

diff --git a/src/Example_Design/top.vhd b/src/Example_Design/top.vhd
@@ -61,7 +61,7 @@ architecture synthesis of top is
    signal sys_data_read        : std_logic_vector(31 downto 0);
    signal sys_count_long       : unsigned(31 downto 0);
    signal sys_count_short      : unsigned(31 downto 0);
-   signal sys_count_error      : unsigned(31 downto 0);
+   signal sys_count_error      : std_logic_vector(31 downto 0);
 
    -- Interface to MEGA65 video
    signal sys_digits           : std_logic_vector(191 downto 0);

diff --git a/src/Example_Design/top.xdc b/src/Example_Design/top.xdc
@@ -80,6 +80,10 @@ set_max_delay 2 -datapath_only -from [get_cells i_core/i_hyperram/hyperram_rx_in
 # Prevent insertion of extra BUFG
 set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_pins i_core/i_hyperram/hyperram_rx_inst/delay_rwds_inst/DATAOUT]]
 
+# Receive FIFO: There is a CDC in the LUTRAM.
+# There is approx 1.1 ns Clock->Data delay for the LUTRAM itself, plus 0.5 ns routing delay to the capture flip-flop.
+set_max_delay 2 -datapath_only -from [get_clocks hr_rwds] -to [get_clocks hr_clk]
+
 ################################################################################
 # HyperRAM timing (correct for IS66WVH8M8DBLL-100B1LI)
 

diff --git a/src/Example_Design/top.xpr b/src/Example_Design/top.xpr
@@ -88,12 +88,6 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/bytewrite_tdp_ram_wf.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/MEGA65/types_pkg.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -146,6 +140,18 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/spram_be.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/axi_fifo_small.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/avm_verifier.vhd">
         <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>

diff --git a/src/hyperram/hyperram.vhd b/src/hyperram/hyperram.vhd
@@ -92,24 +92,6 @@ architecture synthesis of hyperram is
    signal   ctrl_rwds_oe      : std_logic;
    signal   ctrl_rwds_in      : std_logic;
    signal   ctrl_read         : std_logic;
-   signal   ctrl_dq_error     : std_logic;
-
-   signal   stat_underrun : std_logic;
-   signal   stat_timeout  : std_logic;
-
---   attribute mark_debug : string;
---   attribute mark_debug of ctrl_ck_ddr       : signal is "true";
---   attribute mark_debug of ctrl_dq_ddr_in    : signal is "true";
---   attribute mark_debug of ctrl_dq_ddr_out   : signal is "true";
---   attribute mark_debug of ctrl_dq_oe        : signal is "true";
---   attribute mark_debug of ctrl_dq_ie        : signal is "true";
---   attribute mark_debug of ctrl_rwds_ddr_out : signal is "true";
---   attribute mark_debug of ctrl_rwds_oe      : signal is "true";
---   attribute mark_debug of ctrl_rwds_in      : signal is "true";
---   attribute mark_debug of ctrl_read         : signal is "true";
---   attribute mark_debug of ctrl_dq_error     : signal is "true";
---   attribute mark_debug of stat_underrun     : signal is "true";
---   attribute mark_debug of stat_timeout      : signal is "true";
 
 begin
 
@@ -216,8 +198,6 @@ begin
          avm_waitrequest_o   => cfg_waitrequest,
          count_long_o        => count_long_o,
          count_short_o       => count_short_o,
-         underrun_o          => stat_underrun,
-         timeout_o           => stat_timeout,
          hb_rstn_o           => ctrl_rstn,
          hb_csn_o            => ctrl_csn,
          hb_ck_ddr_o         => ctrl_ck_ddr,
@@ -248,7 +228,6 @@ begin
          ctrl_dq_ie_o     => ctrl_dq_ie,
          ctrl_rwds_in_o   => ctrl_rwds_in,
          ctrl_read_i      => ctrl_read,
-         ctrl_dq_error_o  => ctrl_dq_error,
          hr_rwds_in_i     => hr_rwds_in_i,
          hr_dq_in_i       => hr_dq_in_i
       ); -- hyperram_rx_inst

diff --git a/src/hyperram/hyperram_ctrl.vhd b/src/hyperram/hyperram_ctrl.vhd
@@ -33,8 +33,6 @@ entity hyperram_ctrl is
       -- Statistics
       count_long_o        : out unsigned(31 downto 0);
       count_short_o       : out unsigned(31 downto 0);
-      underrun_o          : out std_logic;
-      timeout_o           : out std_logic;
 
       -- HyperBus control signals
       hb_rstn_o           : out std_logic;
@@ -91,8 +89,6 @@ architecture synthesis of hyperram_ctrl is
    -- Statistics
    signal count_long  : unsigned(31 downto 0);
    signal count_short : unsigned(31 downto 0);
-   signal hb_dq_ie_d  : std_logic;
-   signal timeout_count : natural range 0 to 15;
 
 begin
 
@@ -103,9 +99,6 @@ begin
          hb_dq_oe_o          <= '0';
          hb_rwds_oe_o        <= '0';
          hb_read_o           <= '0';
-         underrun_o          <= '0';
-         timeout_o           <= '0';
-         hb_dq_ie_d          <= hb_dq_ie_i;
 
          case state is
             when INIT_ST =>
@@ -171,7 +164,6 @@ begin
                      read_clk_count    <= burst_count+1;
                      read_return_count <= burst_count;
                      hb_read_o         <= '1';
-                     timeout_count     <= 15;
                      state             <= READ_ST;
                   else
                      write_clk_count <= burst_count;
@@ -189,18 +181,7 @@ begin
                   hb_ck_ddr_o <= "00";
                end if;
 
-               if hb_dq_ie_d = '1' and hb_dq_ie_i = '0' then
-                  underrun_o <= '1';
-               end if;
-
-               if timeout_count > 0 then
-                  timeout_count <= timeout_count - 1;
-               else
-                  timeout_o <= '1';
-               end if;
-
                if hb_dq_ie_i = '1' then
-                  timeout_count     <= 1;
                   read_return_count <= read_return_count - 1;
                   if read_return_count = 1 then
                      hb_csn_o       <= '1';