Mega/Xmega soft core RTL design.
A preety complete implementation of ATmega/ATxmega soft core.
This design include all most used IO's, priority interrupt module and watchdog module, except UART that is in development.
-Fix SBIW instruction due to wrong description in oficial documentation.
-Add simple UART interface.
-Optimize core code and make it more readable.
TO DO:
Observed some issues with TIM3 on 'arduboy-rtl-emulator' project, so is needed to
"Fix situations where on random times at core reset the TIM3 prescaller is setup at
wrong value ( at /64 instead of /8 core clock )" need to check in what situation
this issue is manifesting.
Initial commit.
Tested on Digilent Nexis Video board.
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