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Merge upstream repository into noop #5

Merged
merged 106 commits into from
Oct 30, 2024
Merged

Merge upstream repository into noop #5

merged 106 commits into from
Oct 30, 2024

Commits on Jul 13, 2023

  1. Add an exclude list for known failing Hifive1 tests (riscv-software-s…

    …rc#485)
    
    * Add an exclude list for known failing Hifive1 tests
    
    This commit adds a list of known failing tests based on: riscv-collab/riscv-openocd#869 (comment)
    
    * Fix name of the HiFive1 flash target 
    
    Signed-off-by: Marek Vrbka <[email protected]>
    
    ---------
    
    Signed-off-by: Marek Vrbka <[email protected]>
    MarekVCodasip authored Jul 13, 2023
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  2. debug: flushregs -> maintenance flush register-cache

    flushregs is deprecated.
    timsifive committed Jul 13, 2023
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  3. Merge pull request riscv-software-src#490 from riscv-software-src/flu…

    …shregs
    
    debug: flushregs -> maintenance flush register-cache
    timsifive authored Jul 13, 2023
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Commits on Jul 14, 2023

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Commits on Jul 17, 2023

  1. Move import random

    Just so it's easier to quickly comment out code and hard-code the target
    to use without pylint complaining. This really should be a command line
    option.
    timsifive committed Jul 17, 2023
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  5. Interact with OpenOCD CLI over stdin/stdout.

    It's a bit messy to read the log file to get the output, but it seems to
    be flushed often so that this works.
    
    Also, added the `targets` method for retrieving the list of targets,
    and `wait_until_running` method to wait until all targets are in a
    running state.
    timsifive committed Jul 17, 2023
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  6. debug: CeaseMultiTest -> UnavailableMultiTest

    Use the new spike mechanism to test OpenOCD behavior when a hart becomes
    unavailable while running.
    
    Create CommandException.
    timsifive committed Jul 17, 2023
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  7. debug: CeaseRunTest -> UnavailableRunTest

    Use new spike mechanism to test OpenOCD behavior when the current hart
    becomes unavailable while running.
    
    Create ThreadTerminated exception.
    timsifive committed Jul 17, 2023
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  8. debug: Create UnavailableCycleTest

    Use new spike mechanism to test OpenOCD behavior when a hart becomes
    unavailable, and then available again.
    timsifive committed Jul 17, 2023
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  9. Merge pull request riscv-software-src#489 from riscv-software-src/pow…

    …er_dance
    
    debug: Test OpenOCD behavior when harts become unavailable, using new spike mechanism
    timsifive authored Jul 17, 2023
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Commits on Jul 18, 2023

  1. debug: Disable unavailable tests.

    They have issues when run in a github workflow.
    timsifive committed Jul 18, 2023
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  2. Merge pull request riscv-software-src#493 from riscv-software-src/dis…

    …able_unavailable
    
    debug: Disable unavailable tests.
    timsifive authored Jul 18, 2023
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Commits on Jul 19, 2023

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  2. debug: Better comment the privilege tests.

    Just doing this to make a change in the debug files, which should now
    cause the pylint workflow to execute.
    timsifive committed Jul 19, 2023
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Commits on Jul 20, 2023

  1. Merge pull request riscv-software-src#496 from riscv-software-src/pyl…

    …int_workflow
    
    debug: Only run pylint if debug files changed.
    timsifive authored Jul 20, 2023
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Commits on Jul 21, 2023

  1. debug: Actually run tests in github workflow.

    This should avoid problems like we just had where bad tests can break
    the OpenOCD workflow. These tests only run if any debug files are
    changed, so should have no impact at all on non-debug tests in this
    repo.
    
    This file is copied and then slightly changed from riscv-openocd. New
    changes are that cacheable steps (building spike, OpenOCD) are stored to
    the cache even if running the tests fails.
    timsifive committed Jul 21, 2023
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Commits on Jul 24, 2023

  1. Merge pull request riscv-software-src#499 from riscv-software-src/deb…

    …ug_workflow
    
    debug: Actually run tests in github workflow.
    timsifive authored Jul 24, 2023
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  3. debug: Tolerate more whitespace from OpenOCD CLI

    During the github workflow this character is \n, while on my computer
    it's ' '. I'm sure there's a good reason for that, but it doesn't seem
    worth figuring out what that reason is.
    timsifive committed Jul 24, 2023
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  4. Merge pull request riscv-software-src#497 from riscv-software-src/una…

    …vailable
    
    debug: Re-enable unavailable tests, and fix them for github
    timsifive authored Jul 24, 2023
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Commits on Sep 28, 2023

  1. debug: Add --hart command line option to gdbserver.py

    This lets you reproduce a test running on a specific hart.
    timsifive committed Sep 28, 2023
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  4. debug: Better interlock when interacting with gdb CLI.

    Actually wait for the command to be echoed back. This means we won't be
    confused if there are extra newlines in gdb output.
    timsifive committed Sep 28, 2023
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Commits on Sep 29, 2023

  1. Merge pull request riscv-software-src#505 from riscv-software-src/deb…

    …ug_hart
    
    debug: Add --hart command line option to gdbserver.py
    timsifive authored Sep 29, 2023
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  2. Merge pull request riscv-software-src#506 from riscv-software-src/int…

    …errupt_all
    
    debug: Fix interrupt_all() to restore state.
    timsifive authored Sep 29, 2023
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  3. Merge pull request riscv-software-src#507 from riscv-software-src/tar…

    …gets
    
    debug: Make Openocd.targets() tolerate blank lines.
    timsifive authored Sep 29, 2023
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  4. debug: Add Openocd.set_available()

    This helper uses dmi_write commands to mark harts
    available/unavailable.
    timsifive committed Sep 29, 2023
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  5. Merge pull request riscv-software-src#509 from riscv-software-src/int…

    …erlock
    
    debug: Better interlock when interacting with gdb CLI.
    timsifive authored Sep 29, 2023
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Commits on Oct 3, 2023

  1. Merge pull request riscv-software-src#508 from riscv-software-src/set…

    …_available
    
    debug: Add Openocd.set_available()
    timsifive authored Oct 3, 2023
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Commits on Oct 10, 2023

  1. Disable timer interrupt to fix some bugs

    Signed-off-by: liangzhen <[email protected]>
    lz-bro committed Oct 10, 2023
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Commits on Oct 11, 2023

  1. Merge pull request riscv-software-src#503 from lz-bro/dis_timer

    Disable timer interrupt to fix some bugs
    timsifive authored Oct 11, 2023
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Commits on Oct 13, 2023

  1. Merge pull request riscv-software-src#512 from riscv-software-src/pex…

    …pect
    
    debug: Document that pexpect is needed.
    timsifive authored Oct 13, 2023
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  2. debug: Add UnavailableHaltedTest

    Test behavior when a hart becomes unavailable while halted.
    timsifive committed Oct 13, 2023
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Commits on Oct 16, 2023

  1. Make CLINT address configurable

    Signed-off-by: liangzhen <[email protected]>
    lz-bro committed Oct 16, 2023
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Commits on Oct 17, 2023

  1. Make the non-existent csr configurable

    Signed-off-by: liangzhen <[email protected]>
    lz-bro committed Oct 17, 2023
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  2. Merge pull request riscv-software-src#515 from riscv-software-src/una…

    …vailable_halted2
    
    debug: Add UnavailableHaltedTest
    timsifive authored Oct 17, 2023
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  3. Merge pull request riscv-software-src#514 from lz-bro/timer_configurable

    Make CLINT address configurable
    timsifive authored Oct 17, 2023
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  4. Merge pull request riscv-software-src#513 from lz-bro/nonexist_csr

    Make the non-existent csr configurable
    timsifive authored Oct 17, 2023
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Commits on Oct 24, 2023

  1. Support instruction count limit in IcountTest

    This is taking into account that the hardware limits count to 1.
    
    Signed-off-by: liangzhen <[email protected]>
    lz-bro committed Oct 24, 2023
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Commits on Oct 25, 2023

  1. Merge pull request riscv-software-src#519 from lz-bro/fix_icount

    Support limits_icount_to_one in IcountTest
    timsifive authored Oct 25, 2023
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Commits on Nov 9, 2023

  1. debug: use TCL-RPC to fetch results of OpenOCD commands instead of pa…

    …rsing log file
    
    Quick and dirty fix for riscv-software-src#520
    aap-sc committed Nov 9, 2023
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Commits on Nov 10, 2023

  1. Merge pull request riscv-software-src#522 from aap-sc/aap-sc/unavaila…

    …ble_fixup
    
    debug: use TCL-RPC to fetch results of OpenOCD commands instead of parsing log file
    timsifive authored Nov 10, 2023
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Commits on Jan 23, 2024

  1. Disable mmu after test translate

    Signed-off-by: liangzhen <[email protected]>
    lz-bro committed Jan 23, 2024
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Commits on Jan 29, 2024

  1. Uses appropriate addi instruction in lrsc test.

    Lucas Clemente Vella committed Jan 29, 2024
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Commits on Jan 30, 2024

  1. Merge pull request riscv-software-src#528 from powdr-labs/master

    Uses appropriate addi instruction in lrsc test.
    aswaterman authored Jan 30, 2024
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Commits on Feb 1, 2024

  1. [debug tests] print selected seed for PRNG

    Previously the seed was not printed and this created problems with
    reproduction of the issues. It's still not an ideal - meaning
    interactions between spike/gdb/openocd are inherently non-determistic
    (since time is involved), but at least we should get the same sources
    for the same seed now.
    aap-sc committed Feb 1, 2024
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  2. [debug tests] add option to log GDB remote serial protocol

    introduce a new option to log communications over GDB remote serial
    protocol which is helpful for debugging some tests.
    aap-sc committed Feb 1, 2024
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  3. [debug tests] fix setting of remotetimeout

    fixes setting of `remotetimeout`. It was silently overwritten by default
    values from platform definition even if user specified one.
    aap-sc committed Feb 1, 2024
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Commits on Feb 2, 2024

  1. Add virtual memory synchronization after completing the page tables

    Signed-off-by: liangzhen <[email protected]>
    Change-Id: Ida1490338d204541c5c7f143aec3b8d79d83d7f4
    lz-bro committed Feb 2, 2024
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  2. Clear breakpoints so that gdb will not single step

    Signed-off-by: liangzhen <[email protected]>
    Change-Id: I7a4a24972cfa2ddc307a5f06fe3fd5380794719f
    lz-bro committed Feb 2, 2024
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Commits on Feb 3, 2024

  1. If Svnapot is not implemented, skip the test.

    If Svnapot is not implemented, a page fault will occur when accessing a page with napot specified.
    In this case, let the test pass.
    eiji-y committed Feb 3, 2024
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  2. Merge pull request riscv-software-src#536 from eiji-y/check_svnapot

    If Svnapot is not implemented, skip the test.
    aswaterman authored Feb 3, 2024
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Commits on Feb 4, 2024

  1. Check the mcontrol triggers, no other triggers.

    Signed-off-by: liangzhen <[email protected]>
    Change-Id: Iac914aef8080411e6acd9039c4bdfa728533103c
    lz-bro committed Feb 4, 2024
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Commits on Feb 19, 2024

  1. Add zba test cases

    Signed-off-by: Roger Chang <[email protected]>
    rogerchang23424 committed Feb 19, 2024
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  2. Add zbb test cases

    Signed-off-by: Roger Chang <[email protected]>
    rogerchang23424 committed Feb 19, 2024
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  3. Add zbc test cases

    Signed-off-by: Roger Chang <[email protected]>
    rogerchang23424 committed Feb 19, 2024
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  4. Add zbs test cases

    Signed-off-by: Roger Chang <[email protected]>
    rogerchang23424 committed Feb 19, 2024
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  5. Merge pull request riscv-software-src#539 from rogerchang23424/bitmanip

    Add bitmanip test cases
    aswaterman authored Feb 19, 2024
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Commits on Feb 29, 2024

  1. Merge pull request riscv-software-src#526 from lz-bro/fix_TranslateTest

    Restore $stap and $mstatus after test translate
    aswaterman authored Feb 29, 2024
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  2. Merge pull request riscv-software-src#532 from lz-bro/mb_translate

    Add virtual memory synchronization after completing the page tables
    aswaterman authored Feb 29, 2024
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Commits on Mar 1, 2024

  1. Merge pull request riscv-software-src#531 from aap-sc/aap-sc/improvem…

    …ents
    
     improvements to debug tests infrastructure to help with triaging process
    en-sc authored Mar 1, 2024
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Commits on Mar 2, 2024

  1. Merge pull request riscv-software-src#533 from lz-bro/fix_icount

    Clear breakpoints so that gdb will not single step
    aap-sc authored Mar 2, 2024
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Commits on Mar 5, 2024

  1. Fix CI debug test using ubuntu-20.04

    Signed-off-by: 梁镇 <[email protected]>
    Change-Id: I4657a0417b79d515655f6ad4a5ba4465ca58061f
    lz-bro committed Mar 5, 2024
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Commits on Mar 19, 2024

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Commits on Apr 2, 2024

  1. Merge pull request riscv-software-src#534 from lz-bro/fix_triggerDmode

    Check the mcontrol triggers, no other triggers.
    aap-sc authored Apr 2, 2024
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Commits on Apr 17, 2024

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Commits on May 1, 2024

  1. [debug tests] increase remotetimeout for all spike-based targets (ris…

    …cv-software-src#553)
    
    Spike simulator is very demanding to CPU resources. This causes debug
    tests to sporadically fail on slower machines. Increasing of gdb's
    `remotetimeout` should get rid of such failures, unless we run the
    testsuite on a potato.
    
    The only downside is that if OpenOCD is broken, tests can run longer.
    However, I think this is the sacrifice we can make, since execution time
    is not affected if everything works as expected.
    aap-sc authored May 1, 2024
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Commits on May 2, 2024

  1. debug: Fix loading of empty exclude lists with comments

    This patch fixes the case when we are using an empty exception list (for example just a YAML file with comments but without any test items to skip).
    MarekVCodasip committed May 2, 2024
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Commits on May 4, 2024

  1. Merge pull request riscv-software-src#554 from MarekVCodasip/exclusio…

    …n-fix
    
    debug: Fix loading of empty exclude lists with comments
    aap-sc authored May 4, 2024
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  2. Merge pull request riscv-software-src#544 from lz-bro/debug-test-ubun…

    …tu-20.04
    
    Use Ubuntu 20.04 for debug tests
    aap-sc authored May 4, 2024
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Commits on May 9, 2024

  1. Merge pull request riscv-software-src#549 from leesum1/trigger-fix

    debug: Fix nonexistent trigger registers trap handle in entry.S
    aap-sc authored May 9, 2024
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Commits on May 13, 2024

  1. Merge pull request riscv-software-src#491 from en-sc/en-sc/warning-re…

    …peat-read
    
    Remove old warning check in RepeatReadTest
    aap-sc authored May 13, 2024
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Commits on May 14, 2024

  1. debug: workaround for sporadic failures of some tests due to unexpect…

    …ed data present in pexpect match
    
    Problem was observed on UnavailableMultiTest - this test was sporadically failing.
    When the failure was observed the log of the failing test looked as follows:
    
    ```
      File "/whatever/RISCVTests/debug/testlib.py", line 504, in <genexpr>
        if all(targets[hart.id]["State"] == "running" for hart in harts):
               ~~~~~~~~~~~~~~~~^^^^^^^^^
    KeyError: 'State'
    ```
    
    Adding this modification to testlib.py
    
    ```
    --- a/debug/testlib.py
    +++ b/debug/testlib.py
    @@ -498,6 +498,10 @@ class Openocd:
             for line in lines[2:]:
                 if line.strip():
                     data.append(dict(zip(headers, line.split()[1:])))
    +        str_data = str(data)
    +        sys.stdout.flush()
    +        sys.stdout.write(f"parsed targets:\n{result}\n===\n{str_data}\n---\n")
    +        sys.stdout.flush()
             return data
    ```
    
    Allowed me to root cause the issue. Namely we have the following
    situation:
    
    ```
    parsed targets:
    Exception ignored in: <function _TemporaryFileCloser.__del__ at 0x7f2dee64d1c0>
    Traceback (most recent call last):
      File "/usr/local/lib/python3.11/tempfile.py", line 450, in __del__
        self.close()
      File "/usr/local/lib/python3.11/tempfile.py", line 446, in close
        unlink(self.name)
    FileNotFoundError: [Errno 2] No such file or directory: '/tmp/[email protected]'
    ...
        TargetName         Type       Endian TapName            State
    --  ------------------ ---------- ------ ------------------ ------------
     0  riscv.cpu0         riscv      little riscv.cpu          running
     1* riscv.cpu1         riscv      little riscv.cpu          running
    ===
    [{'Exception': '"/usr/local/lib/python3.11/tempfile.py",', 'ignored': 'line', 'in:': '450,', ...
    ```
    
    The only reasonable (to me) explanation for the observed behavior is below.
    
    Here is how we connect to TCL-RPC server:
    
    ```
      self.openocd_cli = pexpect.spawn(f"nc localhost {self.tclrpc_port}")
      tty.setraw(self.openocd_cli.child_fd)
    ```
    
    Later we request target list by issuing "targets" command:
    
    ```
      self.command("targets")
    ```
    
    Internally, pexpect.spawn implemented as follows:
    
    - we fork the process
    - set up pty and then call execve
    - all these steps are written in python
    
    "Exception ignored" messages are result of exceptions thrown from
    finalizers of NamedTemporaryFile objects. When exception is thrown from
    the finalizer - python unconditionally prints a "warning" to stderr. It
    seems that these messages are polluting our output from "nc" since python
    GC can be invoked before the execve syscall.
    
    The workaround is just to make sure that execve was executed before we
    rely on the format of command output. To have such a guarantee we just
    issue a dummy "echo" command and check that we have a proper reply in the
    output stream.
    
    While this explanation looks convincing, the behavior above still looks
    strange, given that we have https://bugs.python.org/issue14548 which
    was resolved long ago.
    
    However, the proposed workaround fixes the issue.
    aap-sc committed May 14, 2024
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  2. debug: fix sporadic failures of memory sampling tests

    Memory sampling tests fail sporadically for spike targets. A typical
    failure looks as follows (ROI from test log):
    
    ```
    ---------------------------------[ Message ]----------------------------------
    139670831 not less than 124104544
    --------------------------------[ Traceback ]---------------------------------
        ... SECTION IS SKIPPED FOR READABILITY ...
        raise TestFailed(f"{a!r} not less than {b!r}", comment)
    testlib.TestFailed
    ```
    
    Few observations:
    
    - 139670831 is 0x0853352f in hex, while 124104544 is 0x0765af60
    - Now, the assert which is failing corresponds to the following
      expression:
    
    ```
      assertLess(value, previous_value + tolerance)
    ```
    
    - tolerance is `0x500000`. (124104544 - 0x500000) is 0x0715af60
    
    If we look at the sampling output for such failing test, we'll see:
    
    ```
    ...
    0x1212340c5c: 0x0715af60
    timestamp after: 878087500
    timestamp before: 878088133
    0x1212340c5c: 0x0853352f
    ...
    ```
    
    The log above demonstrates the reason for the failure. Since memory
    sampling occures every poll (which by default happens approximately
    every 100ms) a value of the counter may exceed the threshold if the time
    between subsequent polls is increased (for whatever reason).
    
    In my opinion the failing assert can be safely removed, since the checks
    it perform are quite brittle and cannot be generalized. The assert
    violation is affected by CPU performance and sporadic delays between
    polls.
    
    For now, instead of assert removal we just avoid checks in-between
    memory sample bursts. This way we still can be certain that memory
    samples are frequent enough and hopefully this will avoid sporadic
    failures.
    aap-sc committed May 14, 2024
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Commits on May 16, 2024

  1. Merge pull request riscv-software-src#556 from aap-sc/aap-sc/sampling…

    …_sporadic_failure
    
    debug: fix sporadic failures of memory sampling tests
    en-sc authored May 16, 2024
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  2. Merge pull request riscv-software-src#555 from aap-sc/aap-sc/sporadic…

    …_faulure_fix
    
    debug: workaround for sporadic failures of some tests due to unexpected data present in pexpect match
    en-sc authored May 16, 2024
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Commits on May 23, 2024

  1. debug: fix HwbpManual test

    HwbpManual test was broken:
    * Value read back from `tselect` was compared with `tdata1` value.
    https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/gdbserver.py#L701-L703
    This resulted in the test being reported as not supported, after all the
    triggers were checked.
    * `tdata1.type` field was not set to `mcontrol`.
    * `tselect` value used to be changed by `handle_reset` and not restored.
    https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/programs/entry.S#L79-L84
    * Manual breakpoint used to be left behind.
    
    Signed-off-by: Evgeniy Naydanov <[email protected]>
    en-sc committed May 23, 2024
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Commits on May 30, 2024

  1. Support basic testing of more Zca instructions

    By using Zca-friendly registers, we can reuse the existing tests to get
    quick-and-dirty coverage of Zca, when the assembler is told to use Zca.
    (This doesn't break non-Zca targets.)
    aswaterman committed May 30, 2024
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  2. Support more basic testing of Zca instructions

    Continuation of fee361f
    aswaterman committed May 30, 2024
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Commits on May 31, 2024

  1. Merge pull request riscv-software-src#557 from en-sc/en-sc/manual-hwbp

    debug: fix HwbpManual test
    en-sc authored May 31, 2024
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Commits on Jun 6, 2024

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Commits on Jun 13, 2024

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Commits on Jun 24, 2024

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Commits on Jun 27, 2024

  1. Merge pull request riscv-software-src#561 from TommyMurphyTM1234/fix-…

    …list-tests
    
    Debug: suppress `PRNG seed ...` log messages when `gdbserver.py --list-tests <target>` used
    aap-sc authored Jun 27, 2024
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Commits on Jul 2, 2024

  1. README: add link to toolchain (riscv-software-src#569)

    Signed-off-by: Daniel Maslowski <[email protected]>
    orangecms authored Jul 2, 2024
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Commits on Jul 17, 2024

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Commits on Jul 31, 2024

  1. debug: update lds to merge more section (riscv-software-src#573)

    merge .bss.* to .bss then entry.S can clear it.
    zqb-all authored Jul 31, 2024
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Commits on Aug 7, 2024

  1. Remove debug/test binary file (riscv-software-src#574)

    The file was added by 00ab5f0 in riscv-software-src#567.
    Seems like a mistake.
    ```
    > readelf -h debug/test
    ELF Header:
      Magic:   7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00
      Class:                             ELF64
      Data:                              2's complement, little endian
      Version:                           1 (current)
      OS/ABI:                            UNIX - System V
      ABI Version:                       0
      Type:                              EXEC (Executable file)
      Machine:                           RISC-V
      Version:                           0x1
      Entry point address:               0x1212340000
      Start of program headers:          64 (bytes into file)
      Start of section headers:          16552 (bytes into file)
      Flags:                             0x0
      Size of this header:               64 (bytes)
      Size of program headers:           56 (bytes)
      Number of program headers:         2
      Size of section headers:           64 (bytes)
      Number of section headers:         18
      Section header string table index: 17
    ```
    en-sc authored Aug 7, 2024
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  2. [debug] Reserve the trigger in HwbpManual

    After riscv-collab/riscv-openocd#1111 is merged,
    the registers a user wishes to have direct control of should be
    reserved.
    This is the case in `HwbpManual`.
    
    The test still works with older OpenOCD versions, since no exception
    is generated when a command (`riscv reserve_trigger` in this case)
    is not found.
    en-sc committed Aug 7, 2024
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Commits on Aug 15, 2024

  1. Fit riscv-tests to newest riscv spec: renaming sptbr,sbadaddr,mbadaddr (

    riscv-software-src#578)
    
    issue#577
    
    In the newest riscv spec(2021 or later), two csr register
    "sptbr"(0x180) "s/mbadaddr"(0x243) were removed,
    and upgraded to "satp" "s/mtval". Together with more functions.
    
    This commit rename them to pass compile.
    HUJIYONG authored Aug 15, 2024
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Commits on Aug 27, 2024

  1. Fix EtriggerTest assuming that NULL causes a trap (riscv-software-src…

    …#579)
    
    There is already a mechanism for the test target to supply a known-bad
    address, so use that address if it is provided.
    Wren6991 authored Aug 27, 2024
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Commits on Sep 5, 2024

  1. Merge pull request riscv-software-src#575 from en-sc/en-sc/reserve-tr…

    …igger
    
    [debug] Reserve the trigger in `HwbpManual`
    en-sc authored Sep 5, 2024
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  2. [debug] Fix trigger reservation in HwbpManual

     Syntax of the command was changed: (on/off) became compulsory.
    en-sc committed Sep 5, 2024
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  3. Merge pull request riscv-software-src#580 from en-sc/en-sc/reserve-tr…

    …igger-fix
    
    [debug] Fix trigger reservation in HwbpManual
    en-sc authored Sep 5, 2024
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Commits on Sep 6, 2024

  1. [debug] Reserve triggers propperly in HwbpManual

    riscv-collab/riscv-openocd#1111 introduces a
    change in OpenOCD behavior: a manual trigger should be manually removed
    to step/resume from it.
    This was not concidered in previous stop-gap solutions
    (76ff703 and
    8cc4918)
    
    This commit:
    1. Determines if `reserve trigger` is supported by the target.
       This can be removed once
       riscv-collab/riscv-openocd#1111 is merged.
    2. Marks `HwbpManual` test as not applicable in case `reserve trigger`
       is not supported.
    3. Accounts for the change in OpenOCD's behavior when stepping from a
       manual BP.
    4. Cleans up some minor mistakes in `HwbpManual`
    en-sc committed Sep 6, 2024
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  2. Merge pull request riscv-software-src#581 from en-sc/en-sc/reserve-tr…

    …igger-fix-propper
    
    [debug] Reserve triggers propperly in HwbpManual
    en-sc authored Sep 6, 2024
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Commits on Oct 30, 2024

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