Build your own FPGA Chip or embedded FPGA IP with Python, and enjoy a fully open-source, auto-generated CAD flow specifically for your custom FPGA.
# Install PRGA and dependencies
cd /path/to/prga/
./envscr/install
# Install iverilog (Icarus Verilog) if Synopsys VCS is not available
# ...
# Activate Python virtual environment
source ./envscr/activate
# build an example FPGA
make -C examples/fpga/magic/k4_N2_8x8
# create CAD & verification project
make -C examples/app/bcd2bin/magic_k4_N2_8x8
# run RTL-to-bitstream flow and post-implementation simulation
make -C examples/app/bcd2bin/magic_k4_N2_8x8/tests/basic