Merge pull request #27 from RISCV-on-Microsemi-FPGA/develop

Merge to master Libero v12.3 designs

FlashPro_Express_Projects/README.MD

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+# RTG4 Development Kit FPGA Programming Files
+
+This folder contains FlashPro Express **(v12.3)** projects for the RTG4 Development Kit Mi-V sample designs.
+
+## FlashPro Express
+The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
+
+## Programming the Device using FlashPro Express
+ Before running these steps, connect the FPGA board to the computer using FlashPro5 or Embedded FlashPro and power up the board.
+
+    1. Open FlashPro Express
+    2. Select Project -> New Job Project from FlashPro Express Job   
+    3. Browse to the programming Job file (.job) using "Browse ...". The Job files are located
+       in the FlashPro_Express_Project/Programming_Files directory
+    4. Select the Job file, then select "Open"
+    5. Select the FlashPro_Express_Project folder (or any folder of your choice) as the project
+       location, then select "OK"
+    6. The FlashPro Express Job Project is created
+    7. Select the "RUN" button; the status bar will change from IDLE to the percentage complete
+    8. Once complete the status bar will display "1 PROGRAMMER(S) PASSED"
+
+## Design Features
+The Libero designs include the following features:
+* A MIV_RV32IMA_L1_AHB or MIV_RV32IMA_L1_AXI soft RISC-V processor.
+* RISC-V debug block allowing on-target debug using SoftConsole.
+* The operating frequency of the design is 50MHz.
+* Target memory is LSRAM.
+* User peripherals (GPIO, Timers, UART).
+
+The peripherals in this design are located at the following addresses.
+
+| Peripheral    | Address   |
+| ------------- |:-------------:|
+| CoreUARTapb   | 0x7000_1000   |
+| CoreGPIO_IN   | 0x7000_2000   |
+| CoreTimer_0   | 0x7000_3000   |
+| CoreTimer_1   | 0x7000_4000   |
+| CoreGPIO_OUT  | 0x7000_5000   |
+| LSRAM| 0x8000_0000|

Libero_Projects/README.md

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+# RTG4 Development Kit Mi-V Sample FPGA Designs
+This folder contains Tcl scripts that build Libero SoC (**v12.3**) design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs.
+
+## <a name="quick"></a> Instructions
+
+
+#### Running Libero SoC in GUI mode
+    1. Open Libero SoC
+    2. Execute the script, Project -> Execute Script
+    3. Select the directory that the script is located in using the "..."
+    4. Select the script and select "Open"
+    5. In the arguments text box, enter "AHB"
+    6. Select the "Run" button to execute the script
+    7. Once complete, a script report will be generated.
+
+Libero executes the script and opens the Mi-V sample project. The script adds Timing constraints to the project for Synthesis, Place and Route, and Timing Verification. Additionally, IO Constraints are added to the project for Place and Route. The project can now be taken through the remainder of the Libero SoC design flow.
+
+#### Running Libero SoC in GUI mode, with Script Arguments
+    1. Open Libero SoC
+    2. Execute the script, Project -> Execute Script
+    3. Select the directory that the script is located in, using the "..."
+    4. Select the script and select "Open"
+    5. In the arguments text box, enter "AHB SYNTHESIZE"
+    6. Select the "Run" button to execute the script
+    7. Once complete, a script report will be generated.
+
+In this example, the arguments "AHB SYNTHESIZE" are entered to take the project through to Synthesis.
+
+Libero executes the script and opens the Mi-V sample project. The script adds Timing constraints to the project for Synthesis, Place and Route, and Timing Verification. Additionally, IO Constraints are added to the project for Place and Route. The project can now be taken through the remainder of the Libero SoC design flow.
+
+## <a name="Script arguments"></a> Script Arguments
+In the examples above the arguments "AHB" and "AHB SYNTHESIZE" were entered. The complete set of script arguments are documented here.
+
+First argument:
+| Argument    |  Description   |
+| ------------- |:-------------:|
+| AHB      | Generate a sample design with the MiV_RV32IMA_L1_AHB |
+| AXI      | Generate a sample design with the MiV_RV32IMA_L1_AXI |
+
+Second argument:
+| Argument    |  Description   |
+| ------------- |:-------------:|
+| SYNTHESIZE | Run synthesis on the design  |
+| PLACE_AND_ROUTE | Run place and route on the design  |
+| GENERATE_BITSTREAM | Generate the bitstream for the design|
+| EXPORT_PROGRAMMING_FILE | Export the programming file (.job) |
+
+## Design Features
+The Libero designs include the following features:
+* A MIV_RV32IMA_L1_AHB or MIV_RV32IMA_L1_AXI soft RISC-V processor.
+* RISC-V debug block allowing on-target debug using SoftConsole.
+* The operating frequency of the design is 50MHz.
+* Target memory is LSRAM.
+* User peripherals (GPIO, Timers, UART).
+
+The peripherals in this design are located at the following addresses.
+
+| Peripheral    | Address   |
+| ------------- |:-------------:|
+| CoreUARTapb   | 0x7000_1000   |
+| CoreGPIO_IN   | 0x7000_2000   |
+| CoreTimer_0   | 0x7000_3000   |
+| CoreTimer_1   | 0x7000_4000   |
+| CoreGPIO_OUT  | 0x7000_5000   |
+| LSRAM| 0x8000_0000|

Libero_Projects/RTG4_DEV_KIT.tcl

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+set project_folder_name_axi MiV_AXI_BD
+set project_dir_axi "./$project_folder_name_axi"
+set Libero_project_name_axi RTG4_Dev_Kit_MiV_AXI_BaseDesign
+
+set project_folder_name_ahb MiV_AHB_BD
+set project_dir_ahb "./$project_folder_name_ahb"
+set Libero_project_name_ahb RTG4_Dev_Kit_MiV_AHB_BaseDesign
+
+set target [string toupper [lindex $argv 0]]
+set design_flow_stage [string toupper [lindex $argv 1]]
+
+
+proc create_new_project_label_axi { }\
+{
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "---------------------------Creating New Project------------------------------------"
+   puts "------------RTG4_Dev_Kit_MiV_AXI_BaseDesign--------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+}
+
+proc create_new_project_label_ahb { }\
+{
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "---------------------------Creating New Project------------------------------------"
+   puts "------------RTG4_Dev_Kit_MiV_AHB_BaseDesign------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+}
+
+proc project_exists { }\
+{
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "----------------------------------------Error-----------------------------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "Project already exists in folder. Please rename or remove and rerun script."
+   puts "-----------------------------------------------------------------------------------------------"
+}
+
+proc invalid_argument { }\
+{
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "----------------------Wrong Argument Entered ---------------------------------"
+   puts "-----------------------------------------------------------------------------------------------"
+   puts "Make sure you put AHB or AXI argument in front of the Design Flow argument."
+   puts "-----------------------------------------------------------------------------------------------"
+}
+
+proc  base_design_built {}\
+{
+  puts "-----------------------------------------------------------------------------------------------"
+  puts "------------------------------BaseDesign Built---------------------------------------"
+  puts "-----------------------------------------------------------------------------------------------"
+}
+
+if {"$target" == "AHB"} then {
+	if {[file exists $project_dir_ahb] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label_ahb
+		new_project -location  $project_dir_ahb -name $Libero_project_name_ahb -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		import_files -convert_EDN_to_HDL 0 -hdl_source {./import/hdl/reset_synchronizer.v}
+		build_design_hierarchy
+		set_root reset_synchronizer
+		source ./import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$target" == "AXI"} then {
+	if {[file exists $project_dir_axi] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label_axi
+		new_project -location  $project_dir_axi -name $Libero_project_name_axi -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		import_files -convert_EDN_to_HDL 0 -hdl_source {./import/hdl/reset_synchronizer.v}
+		build_design_hierarchy
+		set_root reset_synchronizer
+		source ./import/components/AXI/import_component_and_constraints_rtg4_dev_kit_axi.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$target" == "SYNTHESIZE"} then {
+		invalid_argument
+} elseif {"$target" == "PLACE_AND_ROUTE"} then {
+		invalid_argument
+} elseif {"$target" == "GENERATE_BITSTREAM"} then {
+		invalid_argument
+} elseif {"$target" == "EXPORT_PROGRAMMING_FILE"} then {
+		invalid_argument
+} else {
+	if {[file exists $project_dir_ahb] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label_ahb
+		new_project -location  $project_dir_ahb -name $Libero_project_name_ahb -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		import_files -convert_EDN_to_HDL 0 -hdl_source {./import/hdl/reset_synchronizer.v}
+		build_design_hierarchy
+		set_root reset_synchronizer
+		source ./import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl
+		save_project
+        base_design_built
+	}
+}
+
+if {"$design_flow_stage" == "SYNTHESIZE"} then {
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "-------------------------Begin Synthesis---------------------------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+    # Configuring Place_and_Route tool for a timing pass.
+    configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
+
+    run_tool -name {SYNTHESIZE}
+    save_project
+
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "---------------------------Synthesis Complete-------------------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then {
+
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "----------------------Begin Place and Route--------------------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+	# Configuring Place_and_Route tool for a timing pass.
+	configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
+
+	run_tool -name {PLACEROUTE}
+	save_project
+
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "----------------------Place and Route Complete--------------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then {
+
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "----------------------------Generating Bitstream----------------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+    # Configuring Place_and_Route tool for a timing pass.
+	configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
+
+    run_tool -name {GENERATEPROGRAMMINGDATA}
+    run_tool -name {GENERATEPROGRAMMINGFILE}
+    save_project
+
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "-------------------------------Bitstream Generated---------------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then {
+
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "----------------------Exporting Programming Files----------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+    # Configuring Place_and_Route tool for a timing pass.
+    configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
+
+    # pre-requisite to enable exporting programming file function
+    run_tool -name {GENERATEPROGRAMMINGDATA}
+    run_tool -name {GENERATEPROGRAMMINGFILE}
+
+	if {"$target" == "AHB"} then {
+          export_prog_job \
+         -job_file_name {RTG4_Dev_Kit_MiV_AHB_BaseDesign} \
+         -export_dir {./MiV_AHB_BD/designer/BaseDesign/export} \
+         -force_rtg4_otp 0 \
+         -design_bitstream_format {PPD} 
+		save_project
+
+	} else {
+          export_prog_job \
+         -job_file_name {RTG4_Dev_Kit_MiV_AXI_BaseDesign} \
+         -export_dir {./MiV_AXI_BD/designer/BaseDesign/export} \
+         -force_rtg4_otp 0 \
+         -design_bitstream_format {PPD} 
+		save_project
+	}
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "--------------------Programming Files Exported-------------------------------"
+    puts "-----------------------------------------------------------------------------------------------"
+
+} else {
+    puts "-----------------------------------------------------------------------------------------------"
+    puts "------------No Design Flow  Stage Selected at run time------------------"
+    puts "-----------------------------------------------------------------------------------------------"   
+
+}

Libero_Projects/import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl

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+set project_folder_name MiV_AHB_BD
+set project_dir2 "./$project_folder_name"
+
+
+puts "-------------------------------------------------------------------------"
+puts "-----------------------IMPORTING COMPONENTS------------------------------"
+puts "-------------------------------------------------------------------------"
+
+
+source ./import/components/AHB/top_level_rtg4_dev_kit_ahb.tcl
+
+build_design_hierarchy
+set_root BaseDesign
+
+puts "-------------------------------------------------------------------------"
+puts "--------------------APPLYING DESIGN CONSTRAINTS--------------------------"
+puts "-------------------------------------------------------------------------"
+
+import_files -io_pdc ./import/constraints/io/io_constraints.pdc
+import_files -sdc    ./import/constraints/io_jtag_constraints.sdc
+
+## Associate SDC constraint file to Place and Route tool
+organize_tool_files -tool {PLACEROUTE} \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -file $project_dir2/constraint/io/io_constraints.pdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {SYNTHESIZE} \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {VERIFYTIMING} \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+set_root BaseDesign
+
+run_tool -name {CONSTRAINT_MANAGEMENT}
+derive_constraints_sdc