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This repository has been archived by the owner on Jun 10, 2024. It is now read-only.

Releases: RISCV-on-Microsemi-FPGA/RTG4-Development-Kit

Libero v12.6 designs - v1.0

21 Dec 11:56
@kevinscully100 kevinscully100
12.6-v1.0
b93395e
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Libero v12.6 designs - v1.0 Latest
Latest

Updated to support Libero v12.6

This release features:

  • Tcl scripts updated to Libero v12.6
  • New MIV_RV32 core designs with 2 different configurations
  • New MIV_RV32IMAF AHB core design
  • RTG4 SRAM component updated to v1.0.115
  • Libero cores used in the design are downloaded automatically using the scripts.
  • Updated programming files
Assets 2
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Libero v12.3 designs - v1.0

28 Feb 01:23
@kevinscully100 kevinscully100
12.3-v1.0
dc1f133
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Libero v12.3 designs - v1.0 Pre-release
Pre-release

Updated to support Libero 12.3

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Libero v12.1 designs - v0.1

26 Oct 01:48
@kevinscully100 kevinscully100
12.1-v0.1
359ecbd
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Libero v12.1 designs - v0.1 Pre-release
Pre-release

Initial conversion of designs to Libero Tcl flow

Assets 2
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