Merge branch 'Docs/v1.3' into RC/v1.3-rc1

RoaLogic · Feb 5, 2018 · 816b13d · 816b13d
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diff --git a/DATASHEET.md b/DATASHEET.md
diff --git a/docs/RoaLogic_RV12_RISCV_Datasheet.pdf b/docs/RoaLogic_RV12_RISCV_Datasheet.pdf
diff --git a/docs/RoaLogic_RV12_RISCV_Datasheet.tex b/docs/RoaLogic_RV12_RISCV_Datasheet.tex
@@ -18,7 +18,7 @@
 
 	\input{tex/01-product-brief.tex}
 	\input{tex/02-introduction.tex}
-	%\input{tex/03-pipeline.tex}
+	\input{tex/03-pipeline.tex}
 	\input{tex/04-configurations.tex}
 	\input{tex/05-csrs.tex}
 	\input{tex/06-external-if.tex}

diff --git a/docs/RoaLogic_RV12_RISCV_Markdown.tex b/docs/RoaLogic_RV12_RISCV_Markdown.tex
@@ -9,7 +9,7 @@
 
 \input{markdown/02-introduction.tex}
 
-%\input{markdown/03-pipeline.tex}
+\input{markdown/03-pipeline.tex}
 
 \input{markdown/04-configurations.tex}
 

diff --git a/docs/assets/graffle/RV12 datasheet drawings.graffle/data.plist b/docs/assets/graffle/RV12 datasheet drawings.graffle/data.plist
diff --git a/docs/assets/img/Pipeline-EX-eps-converted-to.pdf b/docs/assets/img/Pipeline-EX-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-EX.eps b/docs/assets/img/Pipeline-EX.eps
diff --git a/docs/assets/img/Pipeline-ID-eps-converted-to.pdf b/docs/assets/img/Pipeline-ID-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-ID.eps b/docs/assets/img/Pipeline-ID.eps
diff --git a/docs/assets/img/Pipeline-IF-eps-converted-to.pdf b/docs/assets/img/Pipeline-IF-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-IF.eps b/docs/assets/img/Pipeline-IF.eps
diff --git a/docs/assets/img/Pipeline-MEM-eps-converted-to.pdf b/docs/assets/img/Pipeline-MEM-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-MEM.eps b/docs/assets/img/Pipeline-MEM.eps
diff --git a/docs/assets/img/Pipeline-Overlap-eps-converted-to.pdf b/docs/assets/img/Pipeline-Overlap-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-Overlap.eps b/docs/assets/img/Pipeline-Overlap.eps
diff --git a/docs/assets/img/Pipeline-Overview-eps-converted-to.pdf b/docs/assets/img/Pipeline-Overview-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-Overview.eps b/docs/assets/img/Pipeline-Overview.eps
diff --git a/docs/assets/img/Pipeline-PD-eps-converted-to.pdf b/docs/assets/img/Pipeline-PD-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-PD.eps b/docs/assets/img/Pipeline-PD.eps
diff --git a/docs/assets/img/Pipeline-RV12-eps-converted-to.pdf b/docs/assets/img/Pipeline-RV12-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-RV12.eps b/docs/assets/img/Pipeline-RV12.eps
diff --git a/docs/assets/img/Pipeline-Reg-eps-converted-to.pdf b/docs/assets/img/Pipeline-Reg-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-Reg.eps b/docs/assets/img/Pipeline-Reg.eps
diff --git a/docs/assets/img/Pipeline-WB-eps-converted-to.pdf b/docs/assets/img/Pipeline-WB-eps-converted-to.pdf
diff --git a/docs/assets/img/Pipeline-WB.eps b/docs/assets/img/Pipeline-WB.eps
diff --git a/docs/assets/img/RV12_Arch-eps-converted-to.pdf b/docs/assets/img/RV12_Arch-eps-converted-to.pdf
diff --git a/docs/assets/img/RV12_Arch.eps b/docs/assets/img/RV12_Arch.eps
diff --git a/docs/tex/00-setup.tex b/docs/tex/00-setup.tex
@@ -8,8 +8,8 @@
 \title{RV12 RISC-V 32/64-bit CPU Core}
 \heading{RV12 RISC-V CPU Core}
 \author{Roa Logic}
-\date{01-Nov-2017}
-\version{1.1}
+\date{01-Feb-2018}
+\version{1.3}
 \doctype{Datasheet}
 \project{http://roalogic.github.io/RV12}
 \author{Paul Hardy}

diff --git a/docs/tex/01-product-brief.tex b/docs/tex/01-product-brief.tex
@@ -13,7 +13,7 @@ \section{Introduction}\label{introduction}
 \end{figure}
 
 The RV12 implements a Harvard architecture for simultaneous instruction
-and data memory accesses. It features an optimizing folded 4-stage
+and data memory accesses. It features an optimizing folded 6-stage
 pipeline, which optimizes overlaps between the execution and memory
 accesses, thereby reducing stalls and improving efficiency.
 
@@ -26,8 +26,8 @@ \section{Introduction}\label{introduction}
 optimize the core for the application.
 
 RV12 is compliant with the RISC-V User Level ISA v2.2 and Privileged
-Architecture v1.9.1 specifications published by the RISC-V Foundation
-(https://riscv.org).
+Architecture v1.10 specifications published by the RISC-V Foundation
+(\href{http://www.riscv.org}{www.riscv.org}).
 
 \pagebreak
 
@@ -37,7 +37,7 @@ \section{Features}\label{features}
 
 \begin{itemize}
 \item
-  Royalty Free Industry standard instruction set (www.riscv.org)
+  Royalty Free Industry standard instruction set (\href{http://www.riscv.org}{www.riscv.org})
 \item
   Parameterized 32/64bit data
 \item
@@ -48,7 +48,7 @@ \section{Features}\label{features}
 \item
   Single cycle execution
 \item
-  Optimizing folded 4-stage pipeline
+  Optimizing folded 6-stage pipeline
 \item
   Optional/Parameterized branch-prediction-unit
 \item

diff --git a/docs/tex/02-introduction.tex b/docs/tex/02-introduction.tex
@@ -11,7 +11,7 @@ \chapter{Introduction to the RV12} \label{introduction-to-the-rv12}
 The RV12 implements a single core 32/64bit Reduced Instruction Set Computing
 (RISC) Central Processing Unit (CPU) with a single hardware thread, based on
 the RISC-V User Instruction Set Architecture v2.2 and Supervisor Instruction
-Set Architecture v1.9.1 specifications.  The core is highly configurable,
+Set Architecture v1.10 specifications.  The core is highly configurable,
 providing the user with a trade-off between area, power, and performance, thus
 allowing it to be optimized for the intended task.
 
@@ -56,7 +56,7 @@ \section{Privilege Levels}\label{privilege-levels}
 
 \section{Execution Pipeline}\label{execution-pipeline}
 
-The RV12 implements an optimizing 4-stage folded pipeline.  The classic RISC
+The RV12 implements an optimizing 6-stage folded pipeline.  The classic RISC
 pipeline consists of 5 stages; instruction fetch (IF), instruction decode (ID),
 execute (EX), memory access (MEM), and register write-back (WB).
 
@@ -90,15 +90,19 @@ \section{Execution Pipeline}\label{execution-pipeline}
   \caption{Overlapping Execution Stages}
 \end{figure}
 
-\subsection{Instruction Fetch/Pre-Decode(IF/PD)} \label{instruction-fetchpre-decode-ifpd}
+\subsection{Instruction Fetch (IF)} \label{instruction-fetch-if}
 
-During the instruction fetch stage one instruction is read from the instruction
-memory, a 16bit-compressed instruction is decoded, and the program counter is
-updated to point to the next instruction.
+During the Instruction Fetch stage one instruction is read from the instruction
+memory and the program counter is updated to point to the next instruction..
+
+\subsection{Instruction Pre-Decode (PD)} \label{instruction-pre-decode-pd}
+
+When RVC Support is enabled, the Instruction Pre-Decode stage decodes a
+16bit-compressed instruction into a native 32bit instruction.
 
 \subsection{Instruction Decode (ID)} \label{instruction-decode-id}
 
-During the instruction decode stage the Register File is accessed and the bypass
+During the Instruction Decode stage the Register File is accessed and the bypass
 controls are determined.
 
 \subsection{Execute (EX)} \label{execute-ex}
@@ -107,6 +111,11 @@ \subsection{Execute (EX)} \label{execute-ex}
 instruction, the memory accessed for a Load/Store instruction, and branches and
 jumps are calculated and checked against their predicted outcomes.
 
+\subsection{Memory (MEM)} \label{memory-mem}
+
+During the Memory stage, memory access by the pipeline is completed. Inclusion
+of this stage ensures high performance of the pipeline.
+
 \subsection{Write Back (WB)} \label{write-back-wb}
 
 During the Write Back stage the result from the Execution stage is written into

diff --git a/docs/tex/03-pipeline.tex b/docs/tex/03-pipeline.tex
@@ -1,7 +1,7 @@
 \chapter{RV12 Execution Pipeline}
 
 The RV12 implements a 32/64bit Integer modified form of the classic RISC pipeline.
-The pipeline consists of the Instruction Fetch, Pre-Decode, Instruction Decode, Execution, and Write Back stages as highlighted in the figure below.
+The pipeline consists of the Instruction Fetch, Pre-Decode, Instruction Decode, Execution, Memory Access, and Write Back stages as highlighted in the figure below.
 
 
 \begin{figure}[h]
@@ -11,20 +11,20 @@ \chapter{RV12 Execution Pipeline}
 
 \pagebreak
 
-\section{Instruction Fetch (IF)}\label{instruction-fetch-if}
-
-\begin{figure}[h]
-  \includegraphics{assets/img/Pipeline-IF}
-  \caption{Instruction Fetch Stage Implementation}
-\end{figure}
+\section{Instruction Fetch (IF)}\label{instr-fetch-if}
 
 The Instruction Fetch unit loads a new parcel from the program memory.
 A parcel is a code field that contains one or more instructions.
 The address of the parcel to load is held by the Program Counter (PC).
 The Program Counter is either 32 or 64bits wide, depending on the XLEN parameter.
 The Program Counter is updated whenever the Instruction Pipeline is not stalled.
 
-In case the pipeline must be flushed the Program Counter is restarted from the given address.
+If the pipeline is flushed the Program Counter is restarted from the given address.
+
+\begin{figure}[h]
+  \includegraphics{assets/img/Pipeline-IF}
+  \caption{Instruction Fetch Stage Implementation}
+\end{figure}
 
 \begin{longtable}[]{@{}lccl@{}}
 	\toprule
@@ -59,6 +59,7 @@ \section{Instruction Fetch (IF)}\label{instruction-fetch-if}
 	\texttt{if\_pc}         & to   & PD            & Instruction Fetch program counter\\
 	\texttt{if\_instr}      & to   & PD            & Instruction Fetch instruction\\
 	\texttt{if\_bubble}     & to   & PD            & Instruction Fetch bubble\\
+	\texttt{if\_exception}  & to   & PD            & Instruction Fetch exception status\\
 
 	\bottomrule
 \caption{IF Signals}
@@ -69,8 +70,7 @@ \section{Instruction Fetch (IF)}\label{instruction-fetch-if}
 
 \section{Pre-Decode (PD)}\label{pre-decode-pd}
 
-The Pre-Decode unti translates 16-bit compressed instructions to the base 32bit RISC-V instructions and then processes Program Counter modifying instructions.
-Jump-And-Link and Branch instructions modify the Program Counter in the Instruction Fetch stage.
+The Pre-Decode unit translates 16-bit compressed instructions to the base 32bit RISC-V instructions and then processes Program Counter modifying instructions like Jump-And-Link and Branch.
 This avoids waiting for the Execution stage to trigger the update and reduces the demand for pipeline flushes.
 The destination address for branches is predicted based on the data provided by the optional Branch Prediction Unit or determined statically based on the offset.
 
@@ -100,16 +100,18 @@ \section{Pre-Decode (PD)}\label{pre-decode-pd}
 
 \fi
 
-	\texttt{if\_pc}         & from & IF & Instruction\_fetch program counter\\
-	\texttt{if\_instr}      & from & IF & Instruction\_fetch instruction\\
-	\texttt{if\_bubble}     & from & IF & Instruction\_fetch bubble\\
+	\texttt{if\_pc}         & from & IF & Instruction Fetch program counter\\
+	\texttt{if\_instr}      & from & IF & Instruction Fetch instruction\\
+	\texttt{if\_bubble}     & from & IF & Instruction Fetch bubble\\
+	\texttt{if\_exception}  & from & IF & Instruction Fetch exception status\\
 	\texttt{pd\_branch\_pc} & to   & IF & New PC (for a branch instruction)\\
 	& & &\\
 	\texttt{bu\_predict}    & from & BP & Branch prediction from Branch Prediction Unit\\
 	\texttt{pd\_predict }   & to   & ID & Forwarded branch prediction\\
 	\texttt{pd\_pc}         & to   & ID & Pre-Decode program counter\\
 	\texttt{pd\_instr}      & to   & ID & Pre-Decode instruction\\
 	\texttt{pd\_bubble}     & to   & ID & Pre-Decode bubble\\
+	\texttt{pd\_exception}  & to   & ID & Pre-Decode exception status\\
 	\bottomrule
 	\caption{PD Signals}
 	\label{tab:pd-signals}
@@ -120,7 +122,7 @@ \section{Pre-Decode (PD)}\label{pre-decode-pd}
 \section{Instruction Decode (ID)}\label{instruction-decode-id-1}
 
 The Instruction Decode unit ensures the operands for the execution units are available.
-It accesses the Register File, calculates immediate values, and sets bypasses.
+It accesses the Register File, calculates immediate values, sets bypasses, and checks for illegal opcodes and opcode combinations.
 
 \begin{figure}[h]
   \includegraphics{assets/img/Pipeline-ID}
@@ -146,20 +148,22 @@ \section{Instruction Decode (ID)}\label{instruction-decode-id-1}
 	\endlastfoot
 \fi
 
-		\texttt{pd\_pc}	     & from & PD & Pre-Decode program counter\\
-		\texttt{pd\_instr}   & from & PD & Pre-Decode instruction\\
-		\texttt{pd\_bubble}  & from & PD & Pre-Decode bubble\\
+		\texttt{pd\_pc}	       & from & PD & Pre-Decode program counter\\
+		\texttt{pd\_instr}     & from & PD & Pre-Decode instruction\\
+		\texttt{pd\_bubble}    & from & PD & Pre-Decode bubble\\
+		\texttt{pd\_exception} & from & PD & Pre-Decode exception status\\
 		& & &\\
-		\texttt{src1}        & to   & RF & Source Register1 index\\
-		\texttt{src2}        & to   & RF & Source Register2 Index\\
+		\texttt{src1}          & to   & RF & Source Register1 index\\
+		\texttt{src2}          & to   & RF & Source Register2 Index\\
 		& & &\\
-		\texttt{id\_bypassA} & to   & EX & Bypass signals for srcA\\
-		\texttt{id\_bypassB} & to   & EX & Bypass signals for srcB\\
-		\texttt{id\_opA}     & to   & EX & Calculated operandA\\
-		\texttt{id\_opB}     & to   & EX & Calculated operandB\\
-		\texttt{id\_pc}      & to   & EX & Instruction Decode program counter\\
-		\texttt{id\_instr}   & to   & EX & Instruction Decode instruction\\
-		\texttt{id\_bubble}  & to   & EX & Instruction Decode bubble\\
+		\texttt{id\_bypassA}   & to   & EX & Bypass signals for srcA\\
+		\texttt{id\_bypassB}   & to   & EX & Bypass signals for srcB\\
+		\texttt{id\_opA}       & to   & EX & Calculated operandA\\
+		\texttt{id\_opB}       & to   & EX & Calculated operandB\\
+		\texttt{id\_pc}        & to   & EX & Instruction Decode program counter\\
+		\texttt{id\_instr}     & to   & EX & Instruction Decode instruction\\
+		\texttt{id\_bubble}    & to   & EX & Instruction Decode bubble\\
+		\texttt{id\_exception} & to   & EX & Instruction Decode exception status\\
 	\bottomrule
 	\caption{ID Signals}
 	\label{tab:id-signals}
@@ -205,33 +209,84 @@ \section{Execute (EX)}\label{execute-ex-1}
 	\endfoot
 	\endlastfoot
 \fi
-		id\_pc      & from & ID       & Instruction Decode program counter\\
-		id\_instr   & from & ID       & Instruction Decode instruction\\
-		id\_bubble  & from & ID       & Instruction Decode bubble\\
-		            &      &          & \\
-		opA         & from & RF       & Source Register1 value\\
-		opB         & from & RF       & Source Register2 value\\
-		            &      &          & \\
-		id\_bypassA & from & ID       & Bypass signals for srcA\\
-		id\_bypassB & from & ID       & Bypass signals for srcB\\
-		id\_opA     & from & ID       & Calculated operandA\\
-		id\_opB     & from & ID       & Calculated operandB\\
-		ex\_stall   & to   & ID       & Stall ID (and higher) stages\\
-		ex\_flush   & to   & ID/PD/IF & Flush ID (and higher) pipe stages\\
-		ex\_r       & to   & WB       & Result from execution units\\
-		ex\_pc      & to   & WB       & Execute program counter\\
-		ex\_instr   & to   & WB       & Execute instruction\\
-		ex\_bubble  & to   & WB       & Execute bubble\\
+		\texttt{id\_pc}        & from & ID       & Instruction Decode program counter\\
+		\texttt{id\_instr}     & from & ID       & Instruction Decode instruction\\
+		\texttt{id\_bubble}    & from & ID       & Instruction Decode bubble\\
+		\texttt{id\_exception} & from & ID       & Instruction Decode exception status\\
+		                       &      &          & \\
+		\texttt{opA}           & from & RF       & Source Register1 value\\
+		\texttt{opB}           & from & RF       & Source Register2 value\\
+		                       &      &          & \\
+		\texttt{id\_bypassA}   & from & ID       & Bypass signals for srcA\\
+		\texttt{id\_bypassB}   & from & ID       & Bypass signals for srcB\\
+		\texttt{id\_opA}       & from & ID       & Calculated operandA\\
+		\texttt{id\_opB}       & from & ID       & Calculated operandB\\
+		\texttt{ex\_stall}     & to   & ID       & Stall ID (and higher) stages\\
+		\texttt{ex\_flush}     & to   & ID/PD/IF & Flush ID (and higher) pipe stages\\
+		\texttt{ex\_r}         & to   & MEM      & Result from execution units\\
+		\texttt{ex\_pc}        & to   & MEM      & Execute program counter\\
+		\texttt{ex\_instr}     & to   & MEM      & Execute instruction\\
+		\texttt{ex\_bubble}    & to   & MEM      & Execute bubble\\
+		\texttt{ex\_exception} & to   & MEM      & Execute exception status\\
 	\bottomrule
 	\caption{EX Signals}
 	\label{tab:ex-signals}
 \end{longtable}
 
 \pagebreak
 
+
+\section{Memory-Access (MEM)}\label{memory-access-mem-1}
+
+The Memory Access stage waits for a memory read access to complete.
+When memory is accessed, address, data, and control signals are calculated during the Execute stage.
+The memory latches these signals and then performs the actual access. This means that read-data won't be available until 1 clock cycle later.
+This would be at the end of the Write-Back stage, and hence too late. Therefore the Memory-Access stage is added.
+
+\begin{figure}[h]
+  \includegraphics{assets/img/Pipeline-MEM}
+  \caption{Memory Stage Implementation}
+\end{figure}
+
+\begin{longtable}[]{@{}lccl@{}}
+	\toprule
+	\textbf{Signal} & \textbf{Direction} & \textbf{To/From} & \textbf{Description}\tabularnewline
+	\midrule
+\ifdefined\MARKDOWN
+	\endhead
+\else
+	\endfirsthead
+	\multicolumn{4}{c}{{(Continued from previous page)}} \\
+	\toprule
+	\textbf{Signal} & \textbf{Direction} & \textbf{To/From} & \textbf{Description}\tabularnewline
+	\midrule
+	\endhead
+	\midrule \multicolumn{4}{c}{{\tablename\ \thetable{} continued on next page\ldots}} \\
+	\endfoot
+	\endlastfoot
+\fi
+		\texttt{ex\_r}          & from & EX       & Result from Execution stage\\
+		\texttt{ex\_pc}         & from & EX       & Execute program counter\\
+		\texttt{ex\_instr}      & from & EX       & Execute instruction\\
+		\texttt{ex\_bubble}     & from & EX       & Execute bubble\\
+		\texttt{ex\_exception}  & from & EX       & Execute stage exception status\\
+		                        &      &          & \\
+		\texttt{mem\_r}         & to   & WB/EX    & Memory Access result\\
+		\texttt{mem\_instr}     & to   & WB/ID    & Memory Access instruction\\
+		\texttt{mem\_bubble}    & to   & WB/ID    & Memory Access bubble\\
+		\texttt{mem\_exception} & to   & WB/ID/EX & Memory Access exception status\\
+
+	\bottomrule
+	\caption{MEM Signals}
+	\label{tab:mem-signals}
+\end{longtable}
+
+\pagebreak
+
+
 \section{Write-Back (WB)}\label{write-back-wb-1}
 
-The Write-Back stage writes the results from the Execution Unit into the Register File.
+The Write-Back stage writes the results from the Execution Units and memory-read operations into the Register File.
 
 \begin{figure}[h]
   \includegraphics{assets/img/Pipeline-WB}
@@ -255,19 +310,24 @@ \section{Write-Back (WB)}\label{write-back-wb-1}
 	\endfoot
 	\endlastfoot
 \fi
-		\texttt{ex\_pc}     & from & EX & Execute program counter\\
-		\texttt{ex\_instr}  & from & EX & Execute instruction\\
-		\texttt{ex\_bubble} & from & EX & Execute bubble\\
-		\texttt{ex\_r}      & from & EX & Result from execution units\\
-		                    &      &    & \\
-		\texttt{wb\_r}      & to   & RF & Result to be written to RF\\
-		\texttt{wb\_dst}    & to   & RF & Destination register index\\
-		\texttt{wb\_we}     & to   & RF & Write enable\\
-		\texttt{wb\_pc}     & to   & WB & WriteBack program counter\\
-		\texttt{wb\_instr}  & to   & WB & WriteBack instruction\\
+		\texttt{mem\_r}         & from & MEM         & Result from Memory Access stage\\
+		\texttt{mem\_pc}        & from & MEM         & Memory Access program counter\\
+		\texttt{mem\_instr}     & from & MEM         & Memory Access instruction\\
+		\texttt{mem\_exception} & from & MEM         & Memory Access exception status\\\
+		\texttt{mem\_bubble}    & from & MEM         & Memory Access bubble\\
+		\texttt{dmem\_q}        & from & Data Memory & Result from Data Memory\\
+		\texttt{dmem\_ack}      & from & Data Memory & Data Memory acknowledge\\
+		                        &      &             & \\
+		\texttt{wb\_r}          & to   & RF/ID/EX    & Result to be written to RF\\
+		\texttt{wb\_dst}        & to   & RF          & Destination register index\\
+		\texttt{wb\_we}         & to   & RF          & Write enable\\
+		\texttt{wb\_pc}         & to   & State       & WriteBack program counter\\
+		\texttt{wb\_instr}      & to   & State/ID    & WriteBack instruction\\
+		\texttt{wb\_bubble}     & to   & State/ID    & WriteBack bubble\\
+		\texttt{wb\_exception}  & to   & State/ID/EX & WriteBack exception status\\
 
 	\bottomrule
-	\caption{EWBSignals}
+	\caption{WB Signals}
 	\label{tab:wb-signals}
 \end{longtable}